add SOFA GDS, lef, spef and post-pnr verilog files
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..39f529a
--- /dev/null
+++ b/README.md
@@ -0,0 +1,26 @@
+# OpenFPGA ready-to-use Macros
+
+This repository provide the following GDS-ready eFPGA IPs using OpenFPGA prototyping tool.
+
+
+## Available FPGA Macros
+
+- `SOFA_CHD`: Skywater Opensource FPGA (SOFA) - Custom High-Density Design
+ - Open-source 12x12 FPGA with adapted QuickLogic' soft-adder CLB architecture ([documentation](https://skywater-openfpga.readthedocs.io/en/latest/datasheet/sofa_chd/), [github](https://github.com/lnis-uofu/SOFA))
+ - Designed with Skywater130nm PDK with HD standard cell library + Custom Transmission Gate Cells
+ - Base K4 architecture from VPR with 60 vertical and horizontal channels
+ - Fabricated with eFabless Open MPW shuttle program ([slot-039](https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-one/slot-039))
+
+- `SOFA_HD`: Skywater Opensource FPGA (SOFA) - High-Density Design
+ - Open-source 12x12 FPGA ([documentation](https://skywater-openfpga.readthedocs.io/en/latest/datasheet/sofa_hd/), [github](https://github.com/lnis-uofu/SOFA))
+ - Designed with Skywater130nm PDK with HD standard cell library
+ - Base K4 architecture from VPR with 40 vertical and horizontal channels
+ - No adders (carry-chain) or flipflop reset pins
+ - Fabricated with eFabless Open MPW shuttle program ([slot-017](https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-one/slot-017))
+
+- `SOFA_QLHD`: Skywater Opensource FPGA (SOFA) - QuickLogic' soft-adder High-Density Design
+ - Opensource 12x12 FPGA with adapted QuickLogic' soft-adder CLB architecture ([documentation](https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/), [github](https://github.com/lnis-uofu/SOFA))
+ - Designed with Skywater130nm PDK with HD standard cell library
+ - Base K4 architecture from VPR with 60 vertical and horizontal channels
+ - Fabricated with eFabless Open MPW shuttle program ([slot-036](https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-one/slot-036))
+
diff --git a/SOFA_CHD/README.md b/SOFA_CHD/README.md
new file mode 100644
index 0000000..87abac1
--- /dev/null
+++ b/SOFA_CHD/README.md
@@ -0,0 +1,3 @@
+## FPGA1212_SOFA_CHD_PNR
+
+https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.gds.gz b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.gds.gz
new file mode 100644
index 0000000..645fa25
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.gds.gz
Binary files differ
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.lef b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.lef
new file mode 100644
index 0000000..bc1a90d
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.lef
@@ -0,0 +1,352 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+ DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.46 ;
+ WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+ TYPE CUT ;
+END mcon
+
+LAYER met1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 0.34 ;
+ WIDTH 0.14 ;
+END met1
+
+LAYER via
+ TYPE CUT ;
+END via
+
+LAYER met2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.46 ;
+ WIDTH 0.14 ;
+END met2
+
+LAYER via2
+ TYPE CUT ;
+END via2
+
+LAYER met3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 0.68 ;
+ WIDTH 0.3 ;
+END met3
+
+LAYER via3
+ TYPE CUT ;
+END via3
+
+LAYER met4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.92 ;
+ WIDTH 0.3 ;
+END met4
+
+LAYER via4
+ TYPE CUT ;
+END via4
+
+LAYER met5
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 3.4 ;
+ WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+ TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+ TYPE MASTERSLICE ;
+END pwell
+
+VIA L1M1_PR
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+ LAYER met1 ;
+ RECT -0.16 -0.16 0.16 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+ LAYER met2 ;
+ RECT -0.185 -0.185 0.185 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+ LAYER met3 ;
+ RECT -0.19 -0.19 0.19 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+ CLASS CORE ;
+ SYMMETRY Y ;
+ SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+ CLASS CORE ;
+ SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+END LIBRARY
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz
new file mode 100644
index 0000000..3e4a4c4
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz
Binary files differ
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.pt.v b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.pt.v
new file mode 100644
index 0000000..db99259
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.pt.v
@@ -0,0 +1,147071 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_117 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_118 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_117 ) ,
+ .X ( copt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( copt_net_115 ) ,
+ .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( mem_out[0] ) ,
+ .X ( copt_net_118 ) ) ;
+endmodule
+
+
+module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_513_ ) ,
+ .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_32 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ;
+cby_2__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_57 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( aps_rename_512_ ) ,
+ .Y ( BUF_net_100 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_31 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) ) ;
+cby_2__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_54 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) ,
+ .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) ) ;
+cby_2__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_51 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_96 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_48 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_45 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ;
+cby_2__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_42 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_92 ) ) ;
+cby_2__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_39 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( net_net_92 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_36 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_2__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_108 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_108 ) ,
+ .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_111 ) ,
+ .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( copt_net_109 ) ,
+ .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_110 ) ,
+ .X ( copt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_112 ) ,
+ .X ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( copt_net_113 ) ,
+ .X ( ropt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_121 ) ,
+ .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1376 ( .A ( ropt_net_122 ) ,
+ .X ( ropt_net_123 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ;
+cby_2__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ;
+cby_2__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) ) ;
+cby_2__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+cby_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) ) ;
+cby_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cby_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_2__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_2__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ ,
+ left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ ,
+ left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ ,
+ left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ ,
+ left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ ,
+ left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ,
+ IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper ,
+ left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in ,
+ prog_clk_0_S_out , prog_clk_0_N_out ) ;
+input [0:0] pReset ;
+input [0:29] chany_bottom_in ;
+input [0:29] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input pReset_S_in ;
+input prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size10_0_sram ;
+wire [0:3] mux_2level_size10_1_sram ;
+wire [0:3] mux_2level_size10_2_sram ;
+wire [0:3] mux_2level_size10_3_sram ;
+wire [0:3] mux_2level_size10_4_sram ;
+wire [0:3] mux_2level_size10_5_sram ;
+wire [0:3] mux_2level_size10_6_sram ;
+wire [0:3] mux_2level_size10_7_sram ;
+wire [0:0] mux_2level_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_6_ccff_tail ;
+wire [0:3] mux_2level_size12_0_sram ;
+wire [0:3] mux_2level_size12_1_sram ;
+wire [0:3] mux_2level_size12_2_sram ;
+wire [0:3] mux_2level_size12_3_sram ;
+wire [0:3] mux_2level_size12_4_sram ;
+wire [0:3] mux_2level_size12_5_sram ;
+wire [0:3] mux_2level_size12_6_sram ;
+wire [0:3] mux_2level_size12_7_sram ;
+wire [0:3] mux_2level_size12_8_sram ;
+wire [0:0] mux_2level_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_8_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_2level_size12_0 mux_left_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_2level_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_103 ) ) ;
+cby_2__1__mux_2level_size12_1 mux_right_ipin_0 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
+ chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+ .sram ( mux_2level_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( { aps_rename_514_ } ) ,
+ .p0 ( optlc_net_103 ) ) ;
+cby_2__1__mux_2level_size12_2 mux_right_ipin_2 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
+ chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+ .sram ( mux_2level_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_2__1__mux_2level_size12_3 mux_right_ipin_4 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] ,
+ chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) ,
+ .sram ( mux_2level_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_101 ) ) ;
+cby_2__1__mux_2level_size12_4 mux_right_ipin_6 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
+ chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+ .sram ( mux_2level_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( { aps_rename_516_ } ) ,
+ .p0 ( optlc_net_105 ) ) ;
+cby_2__1__mux_2level_size12_5 mux_right_ipin_8 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
+ chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+ .sram ( mux_2level_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size12_6 mux_right_ipin_10 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] ,
+ chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) ,
+ .sram ( mux_2level_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_101 ) ) ;
+cby_2__1__mux_2level_size12_7 mux_right_ipin_12 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
+ chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+ .sram ( mux_2level_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( { aps_rename_517_ } ) ,
+ .p0 ( optlc_net_103 ) ) ;
+cby_2__1__mux_2level_size12 mux_right_ipin_14 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
+ chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+ .sram ( mux_2level_size12_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_0_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_1_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_2_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_3_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_4_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_5_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_6 mem_right_ipin_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_6_sram ) ) ;
+cby_2__1__mux_2level_size12_mem_7 mem_right_ipin_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_7_sram ) ) ;
+cby_2__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_8_sram ) ) ;
+cby_2__1__mux_2level_size10_0 mux_right_ipin_1 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] ,
+ chany_bottom_out[26] } ) ,
+ .sram ( mux_2level_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( { aps_rename_515_ } ) ,
+ .p0 ( optlc_net_102 ) ) ;
+cby_2__1__mux_2level_size10_1 mux_right_ipin_3 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] ,
+ chany_bottom_out[28] } ) ,
+ .sram ( mux_2level_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size10_2 mux_right_ipin_5 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] ,
+ chany_bottom_out[21] } ) ,
+ .sram ( mux_2level_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_2__1__mux_2level_size10_3 mux_right_ipin_7 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] ,
+ chany_bottom_out[23] } ) ,
+ .sram ( mux_2level_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( { ZBUF_6_f_0 } ) ,
+ .p0 ( optlc_net_105 ) ) ;
+cby_2__1__mux_2level_size10_4 mux_right_ipin_9 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] ,
+ chany_bottom_out[25] } ) ,
+ .sram ( mux_2level_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( { ZBUF_6_f_1 } ) ,
+ .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size10_5 mux_right_ipin_11 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] ,
+ chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] ,
+ chany_bottom_out[27] } ) ,
+ .sram ( mux_2level_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_2__1__mux_2level_size10_6 mux_right_ipin_13 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] ,
+ chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] ,
+ chany_bottom_out[29] } ) ,
+ .sram ( mux_2level_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ;
+cby_2__1__mux_2level_size10 mux_right_ipin_15 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
+ chany_bottom_out[22] } ) ,
+ .sram ( mux_2level_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ;
+cby_2__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_0_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_1_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_2_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_3_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_4_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_5 mem_right_ipin_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_5_sram ) ) ;
+cby_2__1__mux_2level_size10_mem_6 mem_right_ipin_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_6_sram ) ) ;
+cby_2__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_8_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_2level_size10_7_sram ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( left_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_1106 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_2107 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 (
+ .A ( left_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .HI ( optlc_net_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
+ .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) ,
+ .HI ( optlc_net_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) ,
+ .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_112 ( .A ( aps_rename_517_ ) ,
+ .X ( left_grid_pin_28_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_113 ( .A ( aps_rename_514_ ) ,
+ .X ( left_grid_pin_16_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_114 ( .A ( aps_rename_516_ ) ,
+ .X ( left_grid_pin_22_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_115 ( .A ( aps_rename_515_ ) ,
+ .X ( left_grid_pin_17_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1359 ( .A ( ZBUF_6_f_0 ) ,
+ .X ( left_grid_pin_23_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3711261 ( .A ( ctsbuf_net_1106 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3761266 ( .A ( ctsbuf_net_2107 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1360 ( .A ( ZBUF_6_f_1 ) ,
+ .X ( left_grid_pin_25_[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_53 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_54 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_50 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_51 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_52 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_83 ) ) ;
+cby_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_47 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_48 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_49 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( net_net_83 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_44 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_45 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_46 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_41 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_42 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_43 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_38 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_39 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_40 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_35 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_36 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_37 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_82 ) ) ;
+cby_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_34 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cby_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_124 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1360 ( .A ( copt_net_105 ) ,
+ .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_106 ) ,
+ .X ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_107 ) ,
+ .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_109 ) ,
+ .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1375 ( .A ( copt_net_110 ) ,
+ .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1386 ( .A ( ropt_net_123 ) ,
+ .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1387 ( .A ( copt_net_111 ) ,
+ .X ( ropt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1388 ( .A ( ropt_net_122 ) ,
+ .X ( ropt_net_124 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_81 ) ) ;
+cby_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( net_net_81 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_80 ) ) ;
+cby_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+cby_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_79 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cby_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_77 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cby_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_1__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ ,
+ left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ ,
+ left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ ,
+ left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ ,
+ left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ ,
+ left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in ,
+ Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out ,
+ Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in ,
+ Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in ,
+ prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in ,
+ prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in ,
+ prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in ,
+ clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out ,
+ clk_3_S_out ) ;
+input [0:0] pReset ;
+input [0:29] chany_bottom_in ;
+input [0:29] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input Test_en_S_in ;
+input Test_en_E_in ;
+input Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input pReset_S_in ;
+output pReset_N_out ;
+input Reset_S_in ;
+input Reset_E_in ;
+input Reset_W_in ;
+output Reset_N_out ;
+output Reset_W_out ;
+output Reset_E_out ;
+input prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input prog_clk_2_N_in ;
+input prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input prog_clk_3_S_in ;
+input prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input clk_2_N_in ;
+input clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input clk_3_S_in ;
+input clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size10_0_sram ;
+wire [0:3] mux_2level_size10_1_sram ;
+wire [0:3] mux_2level_size10_2_sram ;
+wire [0:3] mux_2level_size10_3_sram ;
+wire [0:3] mux_2level_size10_4_sram ;
+wire [0:3] mux_2level_size10_5_sram ;
+wire [0:3] mux_2level_size10_6_sram ;
+wire [0:3] mux_2level_size10_7_sram ;
+wire [0:0] mux_2level_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_6_ccff_tail ;
+wire [0:3] mux_2level_size12_0_sram ;
+wire [0:3] mux_2level_size12_1_sram ;
+wire [0:3] mux_2level_size12_2_sram ;
+wire [0:3] mux_2level_size12_3_sram ;
+wire [0:3] mux_2level_size12_4_sram ;
+wire [0:3] mux_2level_size12_5_sram ;
+wire [0:3] mux_2level_size12_6_sram ;
+wire [0:3] mux_2level_size12_7_sram ;
+wire [0:0] mux_2level_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+
+assign Test_en_E_in = Test_en_S_in ;
+assign Test_en_E_in = Test_en_W_in ;
+assign Reset_E_in = Reset_S_in ;
+assign Reset_E_in = Reset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
+
+cby_1__1__mux_2level_size12_0 mux_right_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_2level_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_101 ) ) ;
+cby_1__1__mux_2level_size12_1 mux_right_ipin_2 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
+ chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+ .sram ( mux_2level_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_98 ) ) ;
+cby_1__1__mux_2level_size12_2 mux_right_ipin_4 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
+ chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) ,
+ .sram ( mux_2level_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_96 ) ) ;
+cby_1__1__mux_2level_size12_3 mux_right_ipin_6 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_2level_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_98 ) ) ;
+cby_1__1__mux_2level_size12_4 mux_right_ipin_8 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
+ chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+ .sram ( mux_2level_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_99 ) ) ;
+cby_1__1__mux_2level_size12_5 mux_right_ipin_10 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
+ chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) ,
+ .sram ( mux_2level_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_96 ) ) ;
+cby_1__1__mux_2level_size12_6 mux_right_ipin_12 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_2level_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ;
+cby_1__1__mux_2level_size12 mux_right_ipin_14 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
+ chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+ .sram ( mux_2level_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_98 ) ) ;
+cby_1__1__mux_2level_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_0_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_1_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_2_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_3_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_4_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_5 mem_right_ipin_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_5_sram ) ) ;
+cby_1__1__mux_2level_size12_mem_6 mem_right_ipin_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_6_sram ) ) ;
+cby_1__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_7_sram ) ) ;
+cby_1__1__mux_2level_size10_0 mux_right_ipin_1 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] ,
+ chany_bottom_out[25] } ) ,
+ .sram ( mux_2level_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_96 ) ) ;
+cby_1__1__mux_2level_size10_1 mux_right_ipin_3 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] ,
+ chany_bottom_out[27] } ) ,
+ .sram ( mux_2level_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_1__1__mux_2level_size10_2 mux_right_ipin_5 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] ,
+ chany_bottom_out[29] } ) ,
+ .sram ( mux_2level_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_100 ) ) ;
+cby_1__1__mux_2level_size10_3 mux_right_ipin_7 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] ,
+ chany_bottom_out[22] } ) ,
+ .sram ( mux_2level_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_96 ) ) ;
+cby_1__1__mux_2level_size10_4 mux_right_ipin_9 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] ,
+ chany_bottom_out[24] } ) ,
+ .sram ( mux_2level_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_102 ) ) ;
+cby_1__1__mux_2level_size10_5 mux_right_ipin_11 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] ,
+ chany_bottom_out[26] } ) ,
+ .sram ( mux_2level_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_97 ) ) ;
+cby_1__1__mux_2level_size10_6 mux_right_ipin_13 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] ,
+ chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] ,
+ chany_bottom_out[28] } ) ,
+ .sram ( mux_2level_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_97 ) ) ;
+cby_1__1__mux_2level_size10 mux_right_ipin_15 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
+ chany_bottom_out[21] } ) ,
+ .sram ( mux_2level_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ;
+cby_1__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_0_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_1_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_2_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_3_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_4_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_5 mem_right_ipin_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_5_sram ) ) ;
+cby_1__1__mux_2level_size10_mem_6 mem_right_ipin_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_6_sram ) ) ;
+cby_1__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( { copt_net_119 } ) ,
+ .mem_out ( mux_2level_size10_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_E_in ) ,
+ .X ( Reset_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_E_in ) ,
+ .X ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_1103 ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_2104 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) ,
+ .X ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) ,
+ .X ( aps_rename_512_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) ,
+ .X ( aps_rename_513_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) ,
+ .X ( prog_clk_3_S_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_S_FTB01 ( .A ( clk_2_S_in ) ,
+ .X ( aps_rename_514_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) ,
+ .X ( aps_rename_515_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) ,
+ .X ( aps_rename_516_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) ,
+ .X ( clk_3_S_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_85 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_87 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( pReset_S_in ) , .Y ( BUF_net_89 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( Reset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_91 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_E_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_93 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) ,
+ .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_513_ ) ,
+ .Y ( BUF_net_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
+ .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) ,
+ .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) ,
+ .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .HI ( optlc_net_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .HI ( optlc_net_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
+ .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_111 ( .A ( aps_rename_516_ ) ,
+ .X ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_112 ( .A ( aps_rename_511_ ) ,
+ .X ( prog_clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_113 ( .A ( aps_rename_514_ ) ,
+ .X ( clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_512_ ) ,
+ .X ( prog_clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_515_ ) ,
+ .X ( clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3711261 ( .A ( ctsbuf_net_1103 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3761266 ( .A ( ctsbuf_net_2104 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_119 ) ,
+ .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1383 ( .A ( copt_net_120 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_116 ) ,
+ .X ( copt_net_120 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_80 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_79 ) ,
+ .X ( copt_net_75 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_78 ) ,
+ .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_76 ) ,
+ .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_75 ) ,
+ .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[0] ) ,
+ .X ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_77 ) ,
+ .X ( copt_net_80 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_63 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_73 ) ,
+ .X ( copt_net_69 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( copt_net_72 ) ,
+ .X ( copt_net_70 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_69 ) ,
+ .X ( copt_net_71 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( copt_net_74 ) ,
+ .X ( copt_net_72 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_70 ) ,
+ .X ( copt_net_73 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_74 ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_0__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_0__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cby_0__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cby_0__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cby_0__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cby_0__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cby_0__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cby_0__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cby_0__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail ,
+ IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper ,
+ right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_bottom_in ;
+input [0:29] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input pReset_N_in ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_139 ;
+wire ropt_net_131 ;
+wire ropt_net_140 ;
+wire ropt_net_142 ;
+wire ropt_net_127 ;
+wire ropt_net_152 ;
+wire ropt_net_133 ;
+wire ropt_net_141 ;
+wire ropt_net_143 ;
+wire ropt_net_135 ;
+wire ropt_net_154 ;
+wire ropt_net_156 ;
+wire ropt_net_153 ;
+wire ropt_net_130 ;
+wire ropt_net_132 ;
+wire ropt_net_147 ;
+wire ropt_net_138 ;
+wire ropt_net_151 ;
+wire ropt_net_128 ;
+wire ropt_net_149 ;
+wire ropt_net_150 ;
+wire ropt_net_129 ;
+wire ropt_net_146 ;
+wire ropt_net_136 ;
+wire ropt_net_148 ;
+wire ropt_net_134 ;
+wire ropt_net_137 ;
+wire ropt_net_144 ;
+wire ropt_net_145 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size12_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_2level_size12 mux_right_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_2level_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_68 ) ) ;
+cby_0__1__mux_2level_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_2level_size12_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( right_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) ,
+ .X ( ropt_net_139 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) ,
+ .X ( ropt_net_131 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) ,
+ .X ( ropt_net_140 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) ,
+ .X ( ropt_net_142 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_11__10 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_13__12 ( .A ( chany_bottom_in[10] ) ,
+ .X ( ropt_net_127 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) ,
+ .X ( ropt_net_152 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) ,
+ .X ( ropt_net_133 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) ,
+ .X ( ropt_net_141 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) ,
+ .X ( ropt_net_143 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) ,
+ .X ( ropt_net_135 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) ,
+ .X ( ropt_net_154 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) ,
+ .X ( ropt_net_156 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) ,
+ .X ( ropt_net_153 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_bottom_in[28] ) ,
+ .X ( ropt_net_130 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) ,
+ .X ( ropt_net_132 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) ,
+ .X ( ropt_net_147 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[5] ) ,
+ .X ( ropt_net_138 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) ,
+ .X ( ropt_net_151 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[9] ) ,
+ .X ( ropt_net_128 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) ,
+ .X ( ropt_net_149 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) ,
+ .X ( ropt_net_150 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) ,
+ .X ( ropt_net_129 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) ,
+ .X ( ropt_net_146 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chany_top_in[15] ) ,
+ .X ( ropt_net_136 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) ,
+ .X ( ropt_net_148 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) ,
+ .X ( ropt_net_134 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chany_top_in[23] ) ,
+ .X ( ropt_net_137 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) ,
+ .X ( ropt_net_144 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) ,
+ .X ( ropt_net_145 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 (
+ .A ( right_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( optlc_net_68 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_127 ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_128 ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_129 ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1286 ( .A ( ropt_net_130 ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_131 ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_132 ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_133 ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_134 ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1291 ( .A ( ropt_net_135 ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1292 ( .A ( ropt_net_136 ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_137 ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_138 ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_139 ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_140 ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_141 ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_142 ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_143 ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_144 ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_145 ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1302 ( .A ( ropt_net_146 ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_147 ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_148 ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_149 ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1306 ( .A ( ropt_net_150 ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_151 ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1308 ( .A ( ropt_net_152 ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1309 ( .A ( ropt_net_153 ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1310 ( .A ( ropt_net_154 ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1312 ( .A ( ropt_net_156 ) ,
+ .X ( chany_top_out[20] ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_113 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_113 ) ,
+ .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_112 ) ,
+ .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_110 ) ,
+ .X ( copt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_111 ) ,
+ .X ( mem_out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_32 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ;
+cbx_1__2__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_57 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_31 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_93 ) ) ;
+cbx_1__2__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_54 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( net_net_93 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_51 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_507_ ) ) ;
+cbx_1__2__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_48 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_45 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_90 ) ) ;
+cbx_1__2__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_42 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_39 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_89 ) ) ;
+cbx_1__2__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_36 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__2__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_121 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_107 ) ,
+ .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_105 ) ,
+ .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( ropt_net_123 ) ,
+ .X ( copt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_106 ) ,
+ .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( copt_net_116 ) ,
+ .X ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1369 ( .A ( ropt_net_122 ) ,
+ .X ( ropt_net_121 ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_h_inst_1370 ( .A ( copt_net_115 ) ,
+ .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_117 ) ,
+ .X ( ropt_net_123 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_88 ) ) ;
+cbx_1__2__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+cbx_1__2__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) ) ;
+cbx_1__2__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cbx_1__2__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__2__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__2__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ ,
+ bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
+ bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
+ bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
+ ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper ,
+ bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT ,
+ SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out ,
+ pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+input [0:0] pReset ;
+input [0:29] chanx_left_in ;
+input [0:29] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:29] chanx_left_out ;
+output [0:29] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_W_out ;
+output pReset_S_out ;
+output pReset_E_out ;
+input prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size10_0_sram ;
+wire [0:3] mux_2level_size10_1_sram ;
+wire [0:3] mux_2level_size10_2_sram ;
+wire [0:3] mux_2level_size10_3_sram ;
+wire [0:3] mux_2level_size10_4_sram ;
+wire [0:3] mux_2level_size10_5_sram ;
+wire [0:3] mux_2level_size10_6_sram ;
+wire [0:3] mux_2level_size10_7_sram ;
+wire [0:0] mux_2level_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_6_ccff_tail ;
+wire [0:3] mux_2level_size12_0_sram ;
+wire [0:3] mux_2level_size12_1_sram ;
+wire [0:3] mux_2level_size12_2_sram ;
+wire [0:3] mux_2level_size12_3_sram ;
+wire [0:3] mux_2level_size12_4_sram ;
+wire [0:3] mux_2level_size12_5_sram ;
+wire [0:3] mux_2level_size12_6_sram ;
+wire [0:3] mux_2level_size12_7_sram ;
+wire [0:3] mux_2level_size12_8_sram ;
+wire [0:0] mux_2level_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_8_ccff_tail ;
+
+assign pReset_W_in = pReset_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_2level_size12_0 mux_bottom_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_2level_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_2level_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ;
+cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+ .sram ( mux_2level_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
+ chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
+ .sram ( mux_2level_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_98 ) ) ;
+cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_2level_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( { aps_rename_510_ } ) ,
+ .p0 ( optlc_net_98 ) ) ;
+cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+ .sram ( mux_2level_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_99 ) ) ;
+cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
+ chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
+ .sram ( mux_2level_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( { ropt_net_119 } ) ,
+ .p0 ( optlc_net_99 ) ) ;
+cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_2level_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_2level_size12 mux_top_ipin_14 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+ .sram ( mux_2level_size12_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( { aps_rename_513_ } ) ,
+ .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_2level_size12_mem_0 mem_bottom_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_0_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_1_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_2_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_3_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_4_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_5_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_6_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_7_sram ) ) ;
+cbx_1__2__mux_2level_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_8_sram ) ) ;
+cbx_1__2__mux_2level_size10_0 mux_top_ipin_1 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] ,
+ chanx_left_out[26] } ) ,
+ .sram ( mux_2level_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_100 ) ) ;
+cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] ,
+ chanx_left_out[28] } ) ,
+ .sram ( mux_2level_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_100 ) ) ;
+cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] ,
+ chanx_left_out[21] } ) ,
+ .sram ( mux_2level_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_102 ) ) ;
+cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] ,
+ chanx_left_out[23] } ) ,
+ .sram ( mux_2level_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( { aps_rename_511_ } ) ,
+ .p0 ( optlc_net_99 ) ) ;
+cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] ,
+ chanx_left_out[25] } ) ,
+ .sram ( mux_2level_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_98 ) ) ;
+cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] ,
+ chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] ,
+ chanx_left_out[27] } ) ,
+ .sram ( mux_2level_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( { aps_rename_512_ } ) ,
+ .p0 ( optlc_net_99 ) ) ;
+cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] ,
+ chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] ,
+ chanx_left_out[29] } ) ,
+ .sram ( mux_2level_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_102 ) ) ;
+cbx_1__2__mux_2level_size10 mux_top_ipin_15 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
+ chanx_left_out[22] } ) ,
+ .sram ( mux_2level_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_100 ) ) ;
+cbx_1__2__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_0_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_1_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_2_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_3_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_4_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_5_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_6_sram ) ) ;
+cbx_1__2__mux_2level_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_8_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_2level_size10_7_sram ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( bottom_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_S_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( aps_rename_514_ ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( aps_rename_515_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_1104 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 (
+ .A ( bottom_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
+ .HI ( optlc_net_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) ,
+ .HI ( optlc_net_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) ,
+ .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) ,
+ .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_111 ( .A ( aps_rename_513_ ) ,
+ .X ( bottom_grid_pin_14_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_35_inst_112 ( .A ( aps_rename_510_ ) ,
+ .X ( bottom_grid_pin_6_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_35_inst_113 ( .A ( aps_rename_511_ ) ,
+ .X ( bottom_grid_pin_7_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_35_inst_114 ( .A ( aps_rename_512_ ) ,
+ .X ( bottom_grid_pin_11_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_115 ( .A ( aps_rename_515_ ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_116 ( .A ( aps_rename_514_ ) ,
+ .X ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_119 ) ,
+ .X ( bottom_grid_pin_10_[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3711262 ( .A ( ctsbuf_net_1104 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+wire copt_net_109 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_111 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_109 ) ,
+ .X ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( mem_out[3] ) ,
+ .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_112 ) ,
+ .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_110 ) ,
+ .X ( copt_net_112 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_53 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_54 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_50 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_51 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_52 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_47 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_48 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_49 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ;
+cbx_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_44 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_45 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_46 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_41 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_42 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_43 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_38 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_39 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_40 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_35 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_36 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_37 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_85 ) ) ;
+cbx_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_34 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+cbx_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( net_net_85 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_101 ) ,
+ .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_103 ) ,
+ .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_104 ) ,
+ .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_105 ) ,
+ .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( copt_net_106 ) ,
+ .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_122 ) ,
+ .X ( ropt_net_123 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ;
+cbx_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+cbx_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_80 ) ) ;
+cbx_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+cbx_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
+ bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
+ bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
+ bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
+ ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP ,
+ REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH ,
+ COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out ,
+ pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out ,
+ prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out ,
+ prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out ,
+ prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out ,
+ clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in ,
+ clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in ,
+ clk_3_E_out , clk_3_W_out ) ;
+input [0:0] pReset ;
+input [0:29] chanx_left_in ;
+input [0:29] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:29] chanx_left_out ;
+output [0:29] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input REGIN_FEEDTHROUGH ;
+output REGOUT_FEEDTHROUGH ;
+input CIN_FEEDTHROUGH ;
+output COUT_FEEDTHROUGH ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_W_out ;
+output pReset_S_out ;
+output pReset_E_out ;
+input prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input prog_clk_1_W_in ;
+input prog_clk_1_E_in ;
+output prog_clk_1_N_out ;
+output prog_clk_1_S_out ;
+input prog_clk_2_E_in ;
+input prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_E_out ;
+input prog_clk_3_W_in ;
+input prog_clk_3_E_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+input clk_1_W_in ;
+input clk_1_E_in ;
+output clk_1_N_out ;
+output clk_1_S_out ;
+input clk_2_E_in ;
+input clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_E_out ;
+input clk_3_W_in ;
+input clk_3_E_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+
+wire ropt_net_117 ;
+wire ropt_net_121 ;
+wire ropt_net_116 ;
+wire ropt_net_119 ;
+wire ropt_net_118 ;
+wire ropt_net_120 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size10_0_sram ;
+wire [0:3] mux_2level_size10_1_sram ;
+wire [0:3] mux_2level_size10_2_sram ;
+wire [0:3] mux_2level_size10_3_sram ;
+wire [0:3] mux_2level_size10_4_sram ;
+wire [0:3] mux_2level_size10_5_sram ;
+wire [0:3] mux_2level_size10_6_sram ;
+wire [0:3] mux_2level_size10_7_sram ;
+wire [0:0] mux_2level_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size10_mem_6_ccff_tail ;
+wire [0:3] mux_2level_size12_0_sram ;
+wire [0:3] mux_2level_size12_1_sram ;
+wire [0:3] mux_2level_size12_2_sram ;
+wire [0:3] mux_2level_size12_3_sram ;
+wire [0:3] mux_2level_size12_4_sram ;
+wire [0:3] mux_2level_size12_5_sram ;
+wire [0:3] mux_2level_size12_6_sram ;
+wire [0:3] mux_2level_size12_7_sram ;
+wire [0:0] mux_2level_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+
+assign pReset_W_in = pReset_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign clk_1_E_in = clk_1_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
+
+cbx_1__1__mux_2level_size12_0 mux_top_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_2level_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_96 ) ) ;
+cbx_1__1__mux_2level_size12_1 mux_top_ipin_2 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_2level_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_99 ) ) ;
+cbx_1__1__mux_2level_size12_2 mux_top_ipin_4 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
+ chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
+ .sram ( mux_2level_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_94 ) ) ;
+cbx_1__1__mux_2level_size12_3 mux_top_ipin_6 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_2level_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_96 ) ) ;
+cbx_1__1__mux_2level_size12_4 mux_top_ipin_8 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_2level_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( { ZBUF_4_f_0 } ) ,
+ .p0 ( optlc_net_97 ) ) ;
+cbx_1__1__mux_2level_size12_5 mux_top_ipin_10 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
+ chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
+ .sram ( mux_2level_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( { ropt_net_115 } ) ,
+ .p0 ( optlc_net_94 ) ) ;
+cbx_1__1__mux_2level_size12_6 mux_top_ipin_12 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_2level_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_96 ) ) ;
+cbx_1__1__mux_2level_size12 mux_top_ipin_14 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_2level_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_95 ) ) ;
+cbx_1__1__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_0_sram ) ) ;
+cbx_1__1__mux_2level_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_1_sram ) ) ;
+cbx_1__1__mux_2level_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_2_sram ) ) ;
+cbx_1__1__mux_2level_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_3_sram ) ) ;
+cbx_1__1__mux_2level_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_4_sram ) ) ;
+cbx_1__1__mux_2level_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_5_sram ) ) ;
+cbx_1__1__mux_2level_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_6_sram ) ) ;
+cbx_1__1__mux_2level_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_7_sram ) ) ;
+cbx_1__1__mux_2level_size10_0 mux_top_ipin_1 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] ,
+ chanx_left_out[25] } ) ,
+ .sram ( mux_2level_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_94 ) ) ;
+cbx_1__1__mux_2level_size10_1 mux_top_ipin_3 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] ,
+ chanx_left_out[27] } ) ,
+ .sram ( mux_2level_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_99 ) ) ;
+cbx_1__1__mux_2level_size10_2 mux_top_ipin_5 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] ,
+ chanx_left_out[29] } ) ,
+ .sram ( mux_2level_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( { ZBUF_6_f_0 } ) ,
+ .p0 ( optlc_net_94 ) ) ;
+cbx_1__1__mux_2level_size10_3 mux_top_ipin_7 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] ,
+ chanx_left_out[22] } ) ,
+ .sram ( mux_2level_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( { ropt_net_114 } ) ,
+ .p0 ( optlc_net_97 ) ) ;
+cbx_1__1__mux_2level_size10_4 mux_top_ipin_9 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] ,
+ chanx_left_out[24] } ) ,
+ .sram ( mux_2level_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_98 ) ) ;
+cbx_1__1__mux_2level_size10_5 mux_top_ipin_11 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] ,
+ chanx_left_out[26] } ) ,
+ .sram ( mux_2level_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_95 ) ) ;
+cbx_1__1__mux_2level_size10_6 mux_top_ipin_13 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] ,
+ chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] ,
+ chanx_left_out[28] } ) ,
+ .sram ( mux_2level_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_94 ) ) ;
+cbx_1__1__mux_2level_size10 mux_top_ipin_15 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] } ) ,
+ .sram ( mux_2level_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( { ZBUF_4_f_1 } ) ,
+ .p0 ( optlc_net_97 ) ) ;
+cbx_1__1__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_0_sram ) ) ;
+cbx_1__1__mux_2level_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_1_sram ) ) ;
+cbx_1__1__mux_2level_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_2_sram ) ) ;
+cbx_1__1__mux_2level_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_3_sram ) ) ;
+cbx_1__1__mux_2level_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_4_sram ) ) ;
+cbx_1__1__mux_2level_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_5_sram ) ) ;
+cbx_1__1__mux_2level_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size10_6_sram ) ) ;
+cbx_1__1__mux_2level_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_size10_7_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_S_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
+ .X ( ctsbuf_net_1100 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) ,
+ .X ( prog_clk_1_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) ,
+ .X ( prog_clk_1_S_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) ,
+ .X ( prog_clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) ,
+ .X ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) ,
+ .X ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) ,
+ .X ( prog_clk_3_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) ,
+ .X ( clk_1_N_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) ,
+ .X ( clk_1_S_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_90 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_2_E_FTB01 ( .A ( clk_2_W_in ) ,
+ .X ( clk_2_E_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , .X ( net_net_91 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) ,
+ .X ( clk_3_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) ,
+ .X ( ropt_net_117 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) ,
+ .X ( ropt_net_121 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_116 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) ,
+ .X ( ropt_net_118 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) ,
+ .X ( ropt_net_120 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) ,
+ .Y ( prog_clk_3_E_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_511_ ) ,
+ .Y ( BUF_net_89 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( clk_3_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
+ .HI ( optlc_net_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) ,
+ .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) ,
+ .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_106 ( .A ( aps_rename_510_ ) ,
+ .X ( prog_clk_2_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_107 ( .A ( aps_rename_509_ ) ,
+ .X ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1346 ( .A ( ZBUF_6_f_0 ) ,
+ .X ( bottom_grid_pin_5_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3711253 ( .A ( ctsbuf_net_1100 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) ,
+ .X ( bottom_grid_pin_8_[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1348 ( .A ( ZBUF_4_f_1 ) ,
+ .X ( bottom_grid_pin_15_[0] ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_mt_inst_1365 ( .A ( ropt_net_114 ) ,
+ .X ( bottom_grid_pin_7_[0] ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_mt_inst_1366 ( .A ( ropt_net_115 ) ,
+ .X ( bottom_grid_pin_10_[0] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1367 ( .A ( ropt_net_116 ) ,
+ .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1368 ( .A ( ropt_net_117 ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1369 ( .A ( ropt_net_118 ) ,
+ .X ( REGOUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1370 ( .A ( ropt_net_119 ) ,
+ .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1371 ( .A ( ropt_net_120 ) ,
+ .X ( COUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1372 ( .A ( ropt_net_121 ) ,
+ .X ( chanx_left_out[23] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_132 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_132 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_2 copt_h_inst_1369 ( .A ( copt_net_132 ) ,
+ .X ( copt_net_128 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( copt_net_128 ) ,
+ .X ( copt_net_129 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_129 ) ,
+ .X ( copt_net_130 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1372 ( .A ( copt_net_130 ) ,
+ .X ( copt_net_131 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1373 ( .A ( copt_net_131 ) ,
+ .X ( mem_out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) ,
+ .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_109 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( BUF_net_109 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_110 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_105 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_105 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( BUF_net_105 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) ,
+ .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_102 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_104 ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( BUF_net_102 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_100 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_154_0 ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+input ZBUF_154_0 ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_154_0 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( ZBUF_154_0 ) , .Z ( SOC_OUT ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_154_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_154_0 ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ,
+ .ZBUF_154_0 ( ZBUF_154_0 ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail , ZBUF_154_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_154_0 ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ,
+ .ZBUF_154_0 ( ZBUF_154_0 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_99 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( net_net_99 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_97 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( aps_rename_507_ ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( BUF_net_97 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_94 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_94 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( BUF_net_94 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( BUF_net_92 ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_92 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_135 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_123 ) ,
+ .X ( copt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_121 ) ,
+ .X ( copt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( copt_net_126 ) ,
+ .X ( copt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_125 ) ,
+ .X ( copt_net_124 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_122 ) ,
+ .X ( copt_net_125 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_126 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( copt_net_124 ) ,
+ .X ( ropt_net_135 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__0__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_112 ) ) ;
+cbx_1__0__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( .A ( net_net_112 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__0__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__0__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__0__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_111 ) ) ;
+cbx_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_111 ( .A ( net_net_111 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ (
+ .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+cbx_1__0__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+cbx_1__0__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) ,
+ .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+cbx_1__0__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
+ .in ( { mux_2level_basis_input4_mem4_0_out[0] ,
+ mux_2level_basis_input4_mem4_1_out[0] ,
+ mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
+ bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ ,
+ top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ ,
+ top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ ,
+ top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ ,
+ top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ ,
+ top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower ,
+ top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower ,
+ top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower ,
+ top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower ,
+ top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower ,
+ top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower ,
+ top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower ,
+ top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower ,
+ top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower ,
+ SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in ,
+ pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in ,
+ prog_clk_0_W_out ) ;
+input [0:0] pReset ;
+input [0:29] chanx_left_in ;
+input [0:29] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:29] chanx_left_out ;
+output [0:29] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_16_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] top_width_0_height_0__pin_0_ ;
+input [0:0] top_width_0_height_0__pin_2_ ;
+input [0:0] top_width_0_height_0__pin_4_ ;
+input [0:0] top_width_0_height_0__pin_6_ ;
+input [0:0] top_width_0_height_0__pin_8_ ;
+input [0:0] top_width_0_height_0__pin_10_ ;
+input [0:0] top_width_0_height_0__pin_12_ ;
+input [0:0] top_width_0_height_0__pin_14_ ;
+input [0:0] top_width_0_height_0__pin_16_ ;
+output [0:0] top_width_0_height_0__pin_1_upper ;
+output [0:0] top_width_0_height_0__pin_1_lower ;
+output [0:0] top_width_0_height_0__pin_3_upper ;
+output [0:0] top_width_0_height_0__pin_3_lower ;
+output [0:0] top_width_0_height_0__pin_5_upper ;
+output [0:0] top_width_0_height_0__pin_5_lower ;
+output [0:0] top_width_0_height_0__pin_7_upper ;
+output [0:0] top_width_0_height_0__pin_7_lower ;
+output [0:0] top_width_0_height_0__pin_9_upper ;
+output [0:0] top_width_0_height_0__pin_9_lower ;
+output [0:0] top_width_0_height_0__pin_11_upper ;
+output [0:0] top_width_0_height_0__pin_11_lower ;
+output [0:0] top_width_0_height_0__pin_13_upper ;
+output [0:0] top_width_0_height_0__pin_13_lower ;
+output [0:0] top_width_0_height_0__pin_15_upper ;
+output [0:0] top_width_0_height_0__pin_15_lower ;
+output [0:0] top_width_0_height_0__pin_17_upper ;
+output [0:0] top_width_0_height_0__pin_17_lower ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_W_out ;
+output pReset_E_out ;
+input prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_size12_0_sram ;
+wire [0:3] mux_2level_size12_1_sram ;
+wire [0:3] mux_2level_size12_2_sram ;
+wire [0:3] mux_2level_size12_3_sram ;
+wire [0:3] mux_2level_size12_4_sram ;
+wire [0:3] mux_2level_size12_5_sram ;
+wire [0:3] mux_2level_size12_6_sram ;
+wire [0:3] mux_2level_size12_7_sram ;
+wire [0:3] mux_2level_size12_8_sram ;
+wire [0:0] mux_2level_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+
+assign pReset_W_in = pReset_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__0__mux_2level_size12_0 mux_top_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_2level_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ;
+cbx_1__0__mux_2level_size12_1 mux_top_ipin_1 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_2level_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_2level_size12_2 mux_top_ipin_2 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_2level_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ;
+cbx_1__0__mux_2level_size12_3 mux_top_ipin_3 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+ .sram ( mux_2level_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_119 ) ) ;
+cbx_1__0__mux_2level_size12_4 mux_top_ipin_4 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
+ chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
+ .sram ( mux_2level_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_2level_size12_5 mux_top_ipin_5 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
+ chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
+ .sram ( mux_2level_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ;
+cbx_1__0__mux_2level_size12_6 mux_top_ipin_6 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_2level_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_117 ) ) ;
+cbx_1__0__mux_2level_size12_7 mux_top_ipin_7 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_2level_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_2level_size12 mux_top_ipin_8 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_2level_size12_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_117 ) ) ;
+cbx_1__0__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_0_sram ) ) ;
+cbx_1__0__mux_2level_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_1_sram ) ) ;
+cbx_1__0__mux_2level_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_2_sram ) ) ;
+cbx_1__0__mux_2level_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_3_sram ) ) ;
+cbx_1__0__mux_2level_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_4_sram ) ) ;
+cbx_1__0__mux_2level_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_5_sram ) ) ;
+cbx_1__0__mux_2level_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_6_sram ) ) ;
+cbx_1__0__mux_2level_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_size12_7_sram ) ) ;
+cbx_1__0__mux_2level_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_2level_size12_8_sram ) ) ;
+cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .io_outpad ( top_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( top_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) ,
+ .io_outpad ( top_width_0_height_0__pin_2_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_3_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ,
+ .io_outpad ( top_width_0_height_0__pin_4_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_5_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) ,
+ .io_outpad ( top_width_0_height_0__pin_6_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_7_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) ,
+ .io_outpad ( top_width_0_height_0__pin_8_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_9_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ,
+ .ZBUF_154_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ) ;
+cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ,
+ .io_outpad ( top_width_0_height_0__pin_10_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_11_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) ,
+ .io_outpad ( top_width_0_height_0__pin_12_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_13_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ,
+ .io_outpad ( top_width_0_height_0__pin_14_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_15_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ,
+ .io_outpad ( top_width_0_height_0__pin_16_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_17_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( net_net_113 ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( aps_rename_512_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
+ .X ( ctsbuf_net_1120 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 (
+ .A ( top_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 (
+ .A ( top_width_0_height_0__pin_3_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_81__80 (
+ .A ( top_width_0_height_0__pin_5_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_82__81 (
+ .A ( top_width_0_height_0__pin_7_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_83__82 (
+ .A ( top_width_0_height_0__pin_9_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_84__83 (
+ .A ( top_width_0_height_0__pin_11_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_85__84 (
+ .A ( top_width_0_height_0__pin_13_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_86__85 (
+ .A ( top_width_0_height_0__pin_15_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_87__86 (
+ .A ( top_width_0_height_0__pin_17_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_113 ( .A ( net_net_113 ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( aps_rename_512_ ) ,
+ .Y ( BUF_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) ,
+ .HI ( optlc_net_116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) ,
+ .HI ( optlc_net_117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) ,
+ .HI ( optlc_net_118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_40 ) ,
+ .HI ( optlc_net_119 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_154_inst_123 ( .A ( aps_rename_511_ ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3711269 ( .A ( ctsbuf_net_1120 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_84 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_83 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_84 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_177 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_177 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_82 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_81 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_80 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_80 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_81 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_82 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_175 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_175 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_79 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_78 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_77 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_77 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_78 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_79 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_173 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_76 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_75 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_74 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_74 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_75 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_171 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_35 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_34 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_33 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_32 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_31 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_30 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_29 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_28 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_27 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_26 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_25 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_24 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_23 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_22 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_21 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_20 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_19 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_18 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_17 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_16 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_15 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_14 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_13 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_12 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_11 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_73 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_72 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_72 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_73 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_169 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_71 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_70 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_35 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_70 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_71 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_168 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_168 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_69 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_68 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_68 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_69 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_67 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_66 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_66 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_67 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_166 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_166 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_65 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_64 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_64 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_65 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_164 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_164 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_63 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_62 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_62 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_63 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_162 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_61 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_60 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_60 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_61 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_161 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_59 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_58 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_59 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_159 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_57 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_56 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_56 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_55 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_54 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_54 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_55 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_157 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_53 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_52 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_155 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_51 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_50 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_50 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_153 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_49 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_48 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_47 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_46 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_46 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_152 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_152 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_45 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_150 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_150 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_148 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_148 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_38 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_146 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_146 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_144 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_144 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_142 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_142 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_140 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_140 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_138 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_138 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_136 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_136 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_134 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_134 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_132 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_132 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_130 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_130 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_128 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_127 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_126 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_126 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_124 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_124 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_122 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_122 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_120 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_120 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_118 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_118 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_116 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_116 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_114 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_114 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_112 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_112 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_110 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_110 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_224 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1375 ( .A ( copt_net_184 ) ,
+ .X ( copt_net_183 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_184 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_183 ) ,
+ .X ( copt_net_185 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1378 ( .A ( copt_net_185 ) ,
+ .X ( copt_net_186 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1379 ( .A ( copt_net_186 ) ,
+ .X ( copt_net_187 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_187 ) ,
+ .X ( copt_net_188 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1410 ( .A ( copt_net_188 ) ,
+ .X ( ropt_net_220 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1411 ( .A ( ropt_net_220 ) ,
+ .X ( ropt_net_221 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1412 ( .A ( ropt_net_221 ) ,
+ .X ( ropt_net_222 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1413 ( .A ( ropt_net_222 ) ,
+ .X ( ropt_net_223 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1414 ( .A ( ropt_net_223 ) ,
+ .X ( ropt_net_224 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_108 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_108 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_20 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_106 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_106 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_104 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_104 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_102 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_102 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_100 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_96 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_88 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_88 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__2__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ ,
+ bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
+ bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
+ bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ ,
+ bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in ,
+ left_top_grid_pin_1_ , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
+ left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out ,
+ ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_right_grid_pin_1_ ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:0] bottom_left_grid_pin_50_ ;
+input [0:0] bottom_left_grid_pin_51_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_top_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] left_bottom_grid_pin_42_ ;
+input [0:0] left_bottom_grid_pin_43_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_BOT ;
+output SC_OUT_BOT ;
+input pReset_W_in ;
+input prog_clk_0_S_in ;
+
+wire ropt_net_206 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_2level_tapbuf_size2_0_sram ;
+wire [0:1] mux_2level_tapbuf_size2_10_sram ;
+wire [0:1] mux_2level_tapbuf_size2_11_sram ;
+wire [0:1] mux_2level_tapbuf_size2_12_sram ;
+wire [0:1] mux_2level_tapbuf_size2_13_sram ;
+wire [0:1] mux_2level_tapbuf_size2_14_sram ;
+wire [0:1] mux_2level_tapbuf_size2_15_sram ;
+wire [0:1] mux_2level_tapbuf_size2_16_sram ;
+wire [0:1] mux_2level_tapbuf_size2_17_sram ;
+wire [0:1] mux_2level_tapbuf_size2_18_sram ;
+wire [0:1] mux_2level_tapbuf_size2_19_sram ;
+wire [0:1] mux_2level_tapbuf_size2_1_sram ;
+wire [0:1] mux_2level_tapbuf_size2_20_sram ;
+wire [0:1] mux_2level_tapbuf_size2_21_sram ;
+wire [0:1] mux_2level_tapbuf_size2_22_sram ;
+wire [0:1] mux_2level_tapbuf_size2_23_sram ;
+wire [0:1] mux_2level_tapbuf_size2_24_sram ;
+wire [0:1] mux_2level_tapbuf_size2_25_sram ;
+wire [0:1] mux_2level_tapbuf_size2_26_sram ;
+wire [0:1] mux_2level_tapbuf_size2_27_sram ;
+wire [0:1] mux_2level_tapbuf_size2_28_sram ;
+wire [0:1] mux_2level_tapbuf_size2_29_sram ;
+wire [0:1] mux_2level_tapbuf_size2_2_sram ;
+wire [0:1] mux_2level_tapbuf_size2_30_sram ;
+wire [0:1] mux_2level_tapbuf_size2_31_sram ;
+wire [0:1] mux_2level_tapbuf_size2_32_sram ;
+wire [0:1] mux_2level_tapbuf_size2_33_sram ;
+wire [0:1] mux_2level_tapbuf_size2_34_sram ;
+wire [0:1] mux_2level_tapbuf_size2_35_sram ;
+wire [0:1] mux_2level_tapbuf_size2_36_sram ;
+wire [0:1] mux_2level_tapbuf_size2_3_sram ;
+wire [0:1] mux_2level_tapbuf_size2_4_sram ;
+wire [0:1] mux_2level_tapbuf_size2_5_sram ;
+wire [0:1] mux_2level_tapbuf_size2_6_sram ;
+wire [0:1] mux_2level_tapbuf_size2_7_sram ;
+wire [0:1] mux_2level_tapbuf_size2_8_sram ;
+wire [0:1] mux_2level_tapbuf_size2_9_sram ;
+wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_23_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_24_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_25_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_26_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_27_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_28_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_29_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_30_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_31_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_32_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_33_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_34_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_35_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size3_0_sram ;
+wire [0:1] mux_2level_tapbuf_size3_1_sram ;
+wire [0:1] mux_2level_tapbuf_size3_2_sram ;
+wire [0:1] mux_2level_tapbuf_size3_3_sram ;
+wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size4_0_sram ;
+wire [0:3] mux_2level_tapbuf_size4_10_sram ;
+wire [0:3] mux_2level_tapbuf_size4_11_sram ;
+wire [0:3] mux_2level_tapbuf_size4_1_sram ;
+wire [0:3] mux_2level_tapbuf_size4_2_sram ;
+wire [0:3] mux_2level_tapbuf_size4_3_sram ;
+wire [0:3] mux_2level_tapbuf_size4_4_sram ;
+wire [0:3] mux_2level_tapbuf_size4_5_sram ;
+wire [0:3] mux_2level_tapbuf_size4_6_sram ;
+wire [0:3] mux_2level_tapbuf_size4_7_sram ;
+wire [0:3] mux_2level_tapbuf_size4_8_sram ;
+wire [0:3] mux_2level_tapbuf_size4_9_sram ;
+wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_9_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__2__mux_2level_tapbuf_size4_0 mux_bottom_track_1 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
+ .sram ( mux_2level_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_1 mux_bottom_track_3 (
+ .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) ,
+ .sram ( mux_2level_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_2 mux_bottom_track_5 (
+ .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) ,
+ .sram ( mux_2level_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_3 mux_bottom_track_7 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) ,
+ .sram ( mux_2level_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_4 mux_bottom_track_9 (
+ .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) ,
+ .sram ( mux_2level_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_5 mux_bottom_track_11 (
+ .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) ,
+ .sram ( mux_2level_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_6 mux_left_track_1 (
+ .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_7 mux_left_track_3 (
+ .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_8 mux_left_track_5 (
+ .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_9 mux_left_track_7 (
+ .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_10 mux_left_track_9 (
+ .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4 mux_left_track_11 (
+ .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_1 mem_bottom_track_3 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_2 mem_bottom_track_5 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_3 mem_bottom_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_4 mem_bottom_track_9 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_5 mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_8_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_9_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem_10 mem_left_track_9 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_10_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_11_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_0 mux_bottom_track_13 (
+ .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) ,
+ .sram ( mux_2level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_1 mux_bottom_track_15 (
+ .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
+ .sram ( mux_2level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_2 mux_bottom_track_17 (
+ .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
+ .sram ( mux_2level_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_3 mux_bottom_track_19 (
+ .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+ .sram ( mux_2level_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_4 mux_bottom_track_21 (
+ .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+ .sram ( mux_2level_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_5 mux_bottom_track_23 (
+ .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
+ .sram ( mux_2level_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_6 mux_bottom_track_25 (
+ .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) ,
+ .sram ( mux_2level_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_7 mux_bottom_track_27 (
+ .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) ,
+ .sram ( mux_2level_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_8 mux_bottom_track_39 (
+ .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) ,
+ .sram ( mux_2level_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_9 mux_bottom_track_41 (
+ .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_10 mux_bottom_track_43 (
+ .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) ,
+ .sram ( mux_2level_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_11 mux_bottom_track_47 (
+ .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) ,
+ .sram ( mux_2level_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_12 mux_bottom_track_49 (
+ .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_13 mux_bottom_track_51 (
+ .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) ,
+ .sram ( mux_2level_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_14 mux_bottom_track_53 (
+ .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) ,
+ .sram ( mux_2level_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_15 mux_left_track_13 (
+ .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_180 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_16 mux_left_track_15 (
+ .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_17 mux_left_track_17 (
+ .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_18 mux_left_track_19 (
+ .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_19 mux_left_track_21 (
+ .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_20 mux_left_track_23 (
+ .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_21 mux_left_track_25 (
+ .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_22 mux_left_track_27 (
+ .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+ .out ( chanx_left_out[13] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_23 mux_left_track_31 (
+ .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_24 mux_left_track_33 (
+ .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_24_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_25 mux_left_track_35 (
+ .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_25_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_26 mux_left_track_37 (
+ .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_26_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_27 mux_left_track_39 (
+ .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_27_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chanx_left_out[19] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_28 mux_left_track_41 (
+ .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_28_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
+ .out ( chanx_left_out[20] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_29 mux_left_track_43 (
+ .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_29_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chanx_left_out[21] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_30 mux_left_track_45 (
+ .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_30_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_31 mux_left_track_47 (
+ .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_31_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_left_out[23] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_32 mux_left_track_49 (
+ .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_32_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
+ .out ( chanx_left_out[24] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_33 mux_left_track_51 (
+ .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_33_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chanx_left_out[25] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_34 mux_left_track_55 (
+ .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_34_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
+ .out ( chanx_left_out[27] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_35 mux_left_track_57 (
+ .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_35_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chanx_left_out[28] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2 mux_left_track_59 (
+ .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_36_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
+ .out ( chanx_left_out[29] ) , .p0 ( optlc_net_179 ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_1 mem_bottom_track_15 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_2 mem_bottom_track_17 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_3 mem_bottom_track_19 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_4 mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_5 mem_bottom_track_23 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_6 mem_bottom_track_25 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_7 mem_bottom_track_27 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_8 mem_bottom_track_39 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_9 mem_bottom_track_41 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_10 mem_bottom_track_43 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_11 mem_bottom_track_47 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_11_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_12 mem_bottom_track_49 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_12_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_13 mem_bottom_track_51 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_13_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_14 mem_bottom_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_14_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_15 mem_left_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_15_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_16 mem_left_track_15 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_16_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_17 mem_left_track_17 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_17_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_18 mem_left_track_19 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_18_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_19 mem_left_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_19_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_20 mem_left_track_23 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_20_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_21 mem_left_track_25 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_21_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_22 mem_left_track_27 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_22_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_23 mem_left_track_31 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_23_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_24 mem_left_track_33 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_24_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_25 mem_left_track_35 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_25_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_26 mem_left_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_26_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_26_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_27 mem_left_track_39 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_26_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_27_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_27_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_28 mem_left_track_41 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_27_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_28_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_28_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_29 mem_left_track_43 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_28_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_29_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_29_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_30 mem_left_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_29_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_30_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_30_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_31 mem_left_track_47 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_30_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_31_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_31_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_32 mem_left_track_49 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_31_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_32_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_32_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_33 mem_left_track_51 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_32_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_33_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_33_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_34 mem_left_track_55 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_34_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem_35 mem_left_track_57 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_35_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_35_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_35_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_36_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size3_0 mux_bottom_track_29 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[15] } ) ,
+ .sram ( mux_2level_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_181 ) ) ;
+sb_2__2__mux_2level_tapbuf_size3_1 mux_bottom_track_45 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] ,
+ chanx_left_in[23] } ) ,
+ .sram ( mux_2level_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_182 ) ) ;
+sb_2__2__mux_2level_tapbuf_size3_2 mux_left_track_29 (
+ .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size3 mux_left_track_53 (
+ .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_178 ) ) ;
+sb_2__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size3_mem_1 mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size3_mem_2 mem_left_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+sb_2__2__mux_2level_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_33_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[0] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[16] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[17] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[18] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_82__81 ( .A ( chanx_left_in[19] ) ,
+ .X ( ropt_net_206 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[28] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[29] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_85__84 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) ,
+ .HI ( optlc_net_178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) ,
+ .HI ( optlc_net_179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) ,
+ .HI ( optlc_net_180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) ,
+ .HI ( optlc_net_181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) ,
+ .HI ( optlc_net_182 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1398 ( .A ( ropt_net_206 ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_109__108 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_108__107 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_107__106 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_106__105 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_189 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_187 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_185 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_185 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_183 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_13 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_182 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_195 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_195 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_181 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_78 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_58 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__1__local_encoder2to3_58 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_78 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_180 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_77 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_76 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_57 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_56 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_57 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_76 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_77 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_75 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_74 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_55 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_54 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_55 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_74 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_75 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_73 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_72 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_53 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_52 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_52 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_53 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_72 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_71 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_70 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_51 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_50 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_51 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_70 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_71 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_69 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_68 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_49 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_48 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_49 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_68 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_69 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_67 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_66 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_47 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_46 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__1__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_47 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_66 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_179 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_65 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_64 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_45 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_44 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__1__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_45 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_64 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_177 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_63 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_62 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_61 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_43 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_42 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_43 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_61 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_62 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_60 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_59 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_58 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_41 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_40 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_41 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_58 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_59 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_57 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_56 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_55 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_39 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_38 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_39 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_55 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_56 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_57 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_54 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_53 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_52 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_37 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_36 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_2__1__local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_37 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_52 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_53 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_175 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_51 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_50 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_49 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_35 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_34 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_2__1__local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_35 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_49 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_50 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_174 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_174 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_2__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_9 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_10 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_48 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_47 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_33 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_32 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__1__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_33 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_47 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_48 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_172 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_46 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_45 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_31 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_31 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_45 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_46 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_44 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_43 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__1__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_29 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_43 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_44 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_171 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__1__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_27 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_41 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_42 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_169 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_25 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_39 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_23 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_38 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_167 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size9_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size9_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size9_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_8 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_506_ ) ) ;
+sb_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_2__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_6 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_7 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_165 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_505_ ) ) ;
+sb_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_2__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_3 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_4 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_163 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_2__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_0 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_1 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_35 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_31 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_32 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_33 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_2__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_29 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_30 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_161 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_161 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_2__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_26 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_27 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_193 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_193 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_2__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_24 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_159 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_2__1__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_18 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_157 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size8_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size8_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size8_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size8_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_221 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1403 ( .A ( ropt_net_224 ) ,
+ .X ( copt_net_204 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1404 ( .A ( copt_net_204 ) ,
+ .X ( copt_net_205 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1405 ( .A ( copt_net_205 ) ,
+ .X ( copt_net_206 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1406 ( .A ( copt_net_206 ) ,
+ .X ( copt_net_207 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1407 ( .A ( copt_net_207 ) ,
+ .X ( copt_net_208 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1412 ( .A ( ropt_net_223 ) ,
+ .X ( copt_net_213 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( copt_net_213 ) ,
+ .X ( ropt_net_219 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_219 ) ,
+ .X ( ropt_net_220 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_220 ) ,
+ .X ( ropt_net_221 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( copt_net_208 ) ,
+ .X ( ropt_net_222 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_222 ) ,
+ .X ( ropt_net_223 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1421 ( .A ( ccff_head[0] ) ,
+ .X ( ropt_net_224 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ;
+sb_2__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sb_2__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_155 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_155 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sb_2__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_153 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_153 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sb_2__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__1__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_2__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_151 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) ) ;
+endmodule
+
+
+module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
+ top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
+ top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
+ top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in ,
+ bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ ,
+ bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ ,
+ bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ ,
+ bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ ,
+ bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
+ left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out ,
+ chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out ,
+ prog_clk_0_N_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_left_grid_pin_50_ ;
+input [0:0] top_left_grid_pin_51_ ;
+input [0:0] top_right_grid_pin_1_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_right_grid_pin_1_ ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:0] bottom_left_grid_pin_50_ ;
+input [0:0] bottom_left_grid_pin_51_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] left_bottom_grid_pin_42_ ;
+input [0:0] left_bottom_grid_pin_43_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chany_bottom_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input pReset_W_in ;
+output pReset_N_out ;
+input prog_clk_0_N_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_tapbuf_size10_0_sram ;
+wire [0:0] mux_2level_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size2_0_sram ;
+wire [0:1] mux_2level_tapbuf_size2_1_sram ;
+wire [0:1] mux_2level_tapbuf_size2_2_sram ;
+wire [0:1] mux_2level_tapbuf_size2_3_sram ;
+wire [0:1] mux_2level_tapbuf_size2_4_sram ;
+wire [0:1] mux_2level_tapbuf_size2_5_sram ;
+wire [0:1] mux_2level_tapbuf_size2_6_sram ;
+wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size3_0_sram ;
+wire [0:1] mux_2level_tapbuf_size3_1_sram ;
+wire [0:1] mux_2level_tapbuf_size3_2_sram ;
+wire [0:1] mux_2level_tapbuf_size3_3_sram ;
+wire [0:1] mux_2level_tapbuf_size3_4_sram ;
+wire [0:1] mux_2level_tapbuf_size3_5_sram ;
+wire [0:1] mux_2level_tapbuf_size3_6_sram ;
+wire [0:1] mux_2level_tapbuf_size3_7_sram ;
+wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_7_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size4_0_sram ;
+wire [0:3] mux_2level_tapbuf_size4_1_sram ;
+wire [0:3] mux_2level_tapbuf_size4_2_sram ;
+wire [0:3] mux_2level_tapbuf_size4_3_sram ;
+wire [0:3] mux_2level_tapbuf_size4_4_sram ;
+wire [0:3] mux_2level_tapbuf_size4_5_sram ;
+wire [0:3] mux_2level_tapbuf_size4_6_sram ;
+wire [0:3] mux_2level_tapbuf_size4_7_sram ;
+wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_7_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size5_0_sram ;
+wire [0:3] mux_2level_tapbuf_size5_1_sram ;
+wire [0:3] mux_2level_tapbuf_size5_2_sram ;
+wire [0:3] mux_2level_tapbuf_size5_3_sram ;
+wire [0:3] mux_2level_tapbuf_size5_4_sram ;
+wire [0:3] mux_2level_tapbuf_size5_5_sram ;
+wire [0:0] mux_2level_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_5_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size6_0_sram ;
+wire [0:3] mux_2level_tapbuf_size6_1_sram ;
+wire [0:3] mux_2level_tapbuf_size6_2_sram ;
+wire [0:3] mux_2level_tapbuf_size6_3_sram ;
+wire [0:3] mux_2level_tapbuf_size6_4_sram ;
+wire [0:0] mux_2level_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size7_0_sram ;
+wire [0:3] mux_2level_tapbuf_size7_1_sram ;
+wire [0:3] mux_2level_tapbuf_size7_2_sram ;
+wire [0:3] mux_2level_tapbuf_size7_3_sram ;
+wire [0:3] mux_2level_tapbuf_size7_4_sram ;
+wire [0:3] mux_2level_tapbuf_size7_5_sram ;
+wire [0:3] mux_2level_tapbuf_size7_6_sram ;
+wire [0:0] mux_2level_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size8_0_sram ;
+wire [0:3] mux_2level_tapbuf_size8_1_sram ;
+wire [0:3] mux_2level_tapbuf_size8_2_sram ;
+wire [0:3] mux_2level_tapbuf_size8_3_sram ;
+wire [0:0] mux_2level_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size9_0_sram ;
+wire [0:3] mux_2level_tapbuf_size9_1_sram ;
+wire [0:3] mux_2level_tapbuf_size9_2_sram ;
+wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__1__mux_2level_tapbuf_size8_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] ,
+ chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) ,
+ .sram ( mux_2level_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size8_1 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[4] , chany_bottom_out[20] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] ,
+ chanx_left_in[23] } ) ,
+ .sram ( mux_2level_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size8_2 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[21] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] ,
+ chanx_left_in[24] } ) ,
+ .sram ( mux_2level_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size8 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_out[23] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] ,
+ chanx_left_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size8_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size8_mem_1 mem_bottom_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_1_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size8_mem_2 mem_bottom_track_3 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_2_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_3_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_0 mux_top_track_2 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] ,
+ chanx_left_in[10] , chanx_left_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_1 mux_top_track_4 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] ,
+ chanx_left_in[9] , chanx_left_in[20] } ) ,
+ .sram ( mux_2level_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_2 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] ,
+ chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] ,
+ chanx_left_in[17] , chanx_left_in[28] } ) ,
+ .sram ( mux_2level_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_201 ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_3 mux_top_track_20 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] ,
+ chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] ,
+ chanx_left_in[16] , chanx_left_in[27] } ) ,
+ .sram ( mux_2level_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_201 ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_4 mux_top_track_28 (
+ .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] ,
+ chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] ,
+ chanx_left_in[15] , chanx_left_in[26] } ) ,
+ .sram ( mux_2level_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_5 mux_bottom_track_13 (
+ .in ( { chany_bottom_out[12] , chany_bottom_out[27] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] ,
+ chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) ,
+ .sram ( mux_2level_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_201 ) ) ;
+sb_2__1__mux_2level_tapbuf_size7 mux_bottom_track_21 (
+ .in ( { chany_bottom_out[13] , chany_bottom_out[28] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_200 ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_1_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_2_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_3_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_4_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_mem_5 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_5_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size7_mem mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_6_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size9_0 mux_top_track_6 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] ,
+ top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] ,
+ top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] ,
+ chanx_left_in[8] , chanx_left_in[19] } ) ,
+ .sram ( mux_2level_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( { aps_rename_507_ } ) ,
+ .p0 ( optlc_net_198 ) ) ;
+sb_2__1__mux_2level_tapbuf_size9_1 mux_top_track_10 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] ,
+ chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] ,
+ chanx_left_in[18] , chanx_left_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_201 ) ) ;
+sb_2__1__mux_2level_tapbuf_size9 mux_bottom_track_11 (
+ .in ( { chany_bottom_out[11] , chany_bottom_out[25] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) ,
+ .sram ( mux_2level_tapbuf_size9_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_200 ) ) ;
+sb_2__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_1_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size9_mem mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_2_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_0 mux_top_track_36 (
+ .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] ,
+ chanx_left_in[14] , chanx_left_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_1 mux_top_track_44 (
+ .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] ,
+ chanx_left_in[13] , chanx_left_in[24] } ) ,
+ .sram ( mux_2level_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_2 mux_top_track_52 (
+ .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] ,
+ chanx_left_in[12] , chanx_left_in[23] } ) ,
+ .sram ( mux_2level_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chany_top_out[26] ) , .p0 ( optlc_net_198 ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_3 mux_bottom_track_53 (
+ .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] ,
+ chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) ,
+ .sram ( mux_2level_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_4 mux_left_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] ,
+ left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size5 mux_left_track_11 (
+ .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] ,
+ left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size5_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
+ SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_1_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_2_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_mem_3 mem_bottom_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_3_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_4_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_5_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size10 mux_bottom_track_7 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[24] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] ,
+ chanx_left_in[26] } ) ,
+ .sram ( mux_2level_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
+ SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( { aps_rename_508_ } ) ,
+ .p0 ( optlc_net_202 ) ) ;
+sb_2__1__mux_2level_tapbuf_size10_mem mem_bottom_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_0 mux_bottom_track_29 (
+ .in ( { chany_bottom_out[15] , chany_bottom_out[29] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[8] , chanx_left_in[19] } ) ,
+ .sram ( mux_2level_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
+ SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_202 ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_1 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
+ SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_202 ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_2 mux_left_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
+ SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_3 mux_left_track_7 (
+ .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 ,
+ SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_203 ) ) ;
+sb_2__1__mux_2level_tapbuf_size6 mux_left_track_9 (
+ .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
+ SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_mem_0 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_3_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_4_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_0 mux_bottom_track_37 (
+ .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] ,
+ chanx_left_in[9] , chanx_left_in[20] } ) ,
+ .sram ( mux_2level_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 ,
+ SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_202 ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_1 mux_bottom_track_45 (
+ .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] ,
+ chanx_left_in[10] , chanx_left_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 ,
+ SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_197 ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_2 mux_left_track_13 (
+ .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] ,
+ left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 ,
+ SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_3 mux_left_track_15 (
+ .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] ,
+ left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 ,
+ SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_203 ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_4 mux_left_track_17 (
+ .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] ,
+ left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 ,
+ SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_203 ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_5 mux_left_track_19 (
+ .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 ,
+ SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_203 ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_6 mux_left_track_21 (
+ .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 ,
+ SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_203 ) ) ;
+sb_2__1__mux_2level_tapbuf_size4 mux_left_track_23 (
+ .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] ,
+ chanx_left_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 ,
+ SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_mem_1 mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_mem_2 mem_left_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_mem_3 mem_left_track_15 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_mem_4 mem_left_track_17 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_mem_5 mem_left_track_19 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_mem_6 mem_left_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_0 mux_left_track_25 (
+ .in ( { chany_bottom_out[21] , chany_top_out[21] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_1 mux_left_track_27 (
+ .in ( { chany_bottom_out[23] , chany_top_out[23] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
+ .out ( chanx_left_out[13] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_2 mux_left_track_29 (
+ .in ( { chany_bottom_out[24] , chany_top_out[24] ,
+ left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_3 mux_left_track_31 (
+ .in ( { chany_bottom_out[25] , chany_top_out[25] ,
+ left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_4 mux_left_track_33 (
+ .in ( { chany_bottom_out[27] , chany_top_out[27] ,
+ left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_5 mux_left_track_35 (
+ .in ( { chany_bottom_out[28] , chany_top_out[28] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_6 mux_left_track_37 (
+ .in ( { chany_bottom_out[29] , chany_top_out[29] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size3 mux_left_track_51 (
+ .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
+ .out ( chanx_left_out[25] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_mem_0 mem_left_track_25 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_mem_1 mem_left_track_27 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_mem_2 mem_left_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_mem_3 mem_left_track_31 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_mem_4 mem_left_track_33 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_4_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_mem_5 mem_left_track_35 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_5_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_mem_6 mem_left_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_6_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_7_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_0 mux_left_track_41 (
+ .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) ,
+ .out ( chanx_left_out[20] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_1 mux_left_track_45 (
+ .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_2 mux_left_track_47 (
+ .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) ,
+ .out ( chanx_left_out[23] ) , .p0 ( optlc_net_196 ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_3 mux_left_track_49 (
+ .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
+ .out ( chanx_left_out[24] ) , .p0 ( optlc_net_200 ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_4 mux_left_track_53 (
+ .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_5 mux_left_track_55 (
+ .in ( { chany_top_in[4] , chanx_left_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) ,
+ .out ( chanx_left_out[27] ) , .p0 ( optlc_net_200 ) ) ;
+sb_2__1__mux_2level_tapbuf_size2 mux_left_track_57 (
+ .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 } ) ,
+ .out ( chanx_left_out[28] ) , .p0 ( optlc_net_199 ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_mem_0 mem_left_track_41 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_mem_1 mem_left_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_mem_2 mem_left_track_47 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_mem_3 mem_left_track_49 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_mem_4 mem_left_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_mem_5 mem_left_track_55 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+sb_2__1__mux_2level_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) ,
+ .HI ( optlc_net_196 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chany_top_in[1] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chany_top_in[25] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_145__144 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_146__145 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_150__149 ( .A ( left_bottom_grid_pin_41_[0] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_191 ( .A ( pReset_W_in ) , .Y ( BUF_net_191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) ,
+ .HI ( optlc_net_197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) ,
+ .HI ( optlc_net_198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) ,
+ .HI ( optlc_net_199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) ,
+ .HI ( optlc_net_200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) ,
+ .HI ( optlc_net_201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_173 ) ,
+ .HI ( optlc_net_202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_174 ) ,
+ .HI ( optlc_net_203 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_216 ( .A ( aps_rename_508_ ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_217 ( .A ( aps_rename_507_ ) ,
+ .X ( chany_top_out[3] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_185 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_185 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( copt_net_186 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_1 copt_h_inst_1378 ( .A ( copt_net_185 ) ,
+ .X ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 copt_h_inst_1379 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_186 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_34 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_33 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_32 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_31 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_30 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_29 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_28 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_27 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_26 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_25 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_24 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_23 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_22 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_21 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_20 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_19 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_18 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_17 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_16 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_15 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_14 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_13 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_12 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_11 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_85 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_85 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_165 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_165 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_84 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_83 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_84 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_82 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_81 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_81 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_82 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_80 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_79 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_79 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_80 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_163 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_163 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_78 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_77 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_77 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_78 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_76 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_75 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_75 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_74 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_73 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_73 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_74 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_161 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_72 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_71 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_71 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_72 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_159 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_70 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_69 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_69 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_70 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_157 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_68 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_67 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_67 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_68 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_155 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_66 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_65 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_65 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_66 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_153 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_64 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_63 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_63 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_64 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_151 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_62 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_61 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_61 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_62 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_149 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_60 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_59 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_59 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_60 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_147 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_58 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_57 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_145 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_56 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_55 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_143 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_54 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_53 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_53 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_141 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_52 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_51 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_51 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_52 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_139 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_50 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_49 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_49 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_50 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_137 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_48 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_47 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_47 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_48 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_46 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_45 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_45 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_46 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_135 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_41 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_133 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_133 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_39 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_40 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_131 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_37 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_38 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_129 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_36 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_127 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_33 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_125 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_123 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_121 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_119 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_117 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_115 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_113 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_113 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_111 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_111 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_109 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_108 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_106 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_206 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_177 ) ,
+ .X ( copt_net_175 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1369 ( .A ( copt_net_175 ) ,
+ .X ( copt_net_176 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_177 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_176 ) ,
+ .X ( copt_net_178 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1372 ( .A ( copt_net_178 ) ,
+ .X ( copt_net_179 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1373 ( .A ( copt_net_179 ) ,
+ .X ( copt_net_180 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( copt_net_180 ) ,
+ .X ( ropt_net_202 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1396 ( .A ( ropt_net_202 ) ,
+ .X ( ropt_net_203 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1397 ( .A ( ropt_net_205 ) ,
+ .X ( ropt_net_204 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1398 ( .A ( ropt_net_203 ) ,
+ .X ( ropt_net_205 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1399 ( .A ( ropt_net_204 ) ,
+ .X ( ropt_net_206 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_2__0__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_20 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_104 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_104 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_102 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_102 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_100 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_96 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_2__0__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_2__0__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_2__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
+ top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
+ top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
+ top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in ,
+ left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
+ left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
+ left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
+ left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
+ left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out ,
+ ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_left_grid_pin_50_ ;
+input [0:0] top_left_grid_pin_51_ ;
+input [0:0] top_right_grid_pin_1_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_3_ ;
+input [0:0] left_bottom_grid_pin_5_ ;
+input [0:0] left_bottom_grid_pin_7_ ;
+input [0:0] left_bottom_grid_pin_9_ ;
+input [0:0] left_bottom_grid_pin_11_ ;
+input [0:0] left_bottom_grid_pin_13_ ;
+input [0:0] left_bottom_grid_pin_15_ ;
+input [0:0] left_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input pReset_W_in ;
+output pReset_N_out ;
+input prog_clk_0_N_in ;
+
+wire ropt_net_193 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_2level_tapbuf_size2_0_sram ;
+wire [0:1] mux_2level_tapbuf_size2_10_sram ;
+wire [0:1] mux_2level_tapbuf_size2_11_sram ;
+wire [0:1] mux_2level_tapbuf_size2_12_sram ;
+wire [0:1] mux_2level_tapbuf_size2_13_sram ;
+wire [0:1] mux_2level_tapbuf_size2_14_sram ;
+wire [0:1] mux_2level_tapbuf_size2_15_sram ;
+wire [0:1] mux_2level_tapbuf_size2_16_sram ;
+wire [0:1] mux_2level_tapbuf_size2_17_sram ;
+wire [0:1] mux_2level_tapbuf_size2_18_sram ;
+wire [0:1] mux_2level_tapbuf_size2_19_sram ;
+wire [0:1] mux_2level_tapbuf_size2_1_sram ;
+wire [0:1] mux_2level_tapbuf_size2_20_sram ;
+wire [0:1] mux_2level_tapbuf_size2_21_sram ;
+wire [0:1] mux_2level_tapbuf_size2_22_sram ;
+wire [0:1] mux_2level_tapbuf_size2_23_sram ;
+wire [0:1] mux_2level_tapbuf_size2_24_sram ;
+wire [0:1] mux_2level_tapbuf_size2_25_sram ;
+wire [0:1] mux_2level_tapbuf_size2_26_sram ;
+wire [0:1] mux_2level_tapbuf_size2_27_sram ;
+wire [0:1] mux_2level_tapbuf_size2_28_sram ;
+wire [0:1] mux_2level_tapbuf_size2_29_sram ;
+wire [0:1] mux_2level_tapbuf_size2_2_sram ;
+wire [0:1] mux_2level_tapbuf_size2_30_sram ;
+wire [0:1] mux_2level_tapbuf_size2_31_sram ;
+wire [0:1] mux_2level_tapbuf_size2_32_sram ;
+wire [0:1] mux_2level_tapbuf_size2_33_sram ;
+wire [0:1] mux_2level_tapbuf_size2_34_sram ;
+wire [0:1] mux_2level_tapbuf_size2_35_sram ;
+wire [0:1] mux_2level_tapbuf_size2_3_sram ;
+wire [0:1] mux_2level_tapbuf_size2_4_sram ;
+wire [0:1] mux_2level_tapbuf_size2_5_sram ;
+wire [0:1] mux_2level_tapbuf_size2_6_sram ;
+wire [0:1] mux_2level_tapbuf_size2_7_sram ;
+wire [0:1] mux_2level_tapbuf_size2_8_sram ;
+wire [0:1] mux_2level_tapbuf_size2_9_sram ;
+wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_23_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_24_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_25_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_26_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_27_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_28_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_29_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_30_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_31_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_32_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_33_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_34_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size3_0_sram ;
+wire [0:1] mux_2level_tapbuf_size3_1_sram ;
+wire [0:1] mux_2level_tapbuf_size3_2_sram ;
+wire [0:1] mux_2level_tapbuf_size3_3_sram ;
+wire [0:1] mux_2level_tapbuf_size3_4_sram ;
+wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size4_0_sram ;
+wire [0:3] mux_2level_tapbuf_size4_10_sram ;
+wire [0:3] mux_2level_tapbuf_size4_11_sram ;
+wire [0:3] mux_2level_tapbuf_size4_1_sram ;
+wire [0:3] mux_2level_tapbuf_size4_2_sram ;
+wire [0:3] mux_2level_tapbuf_size4_3_sram ;
+wire [0:3] mux_2level_tapbuf_size4_4_sram ;
+wire [0:3] mux_2level_tapbuf_size4_5_sram ;
+wire [0:3] mux_2level_tapbuf_size4_6_sram ;
+wire [0:3] mux_2level_tapbuf_size4_7_sram ;
+wire [0:3] mux_2level_tapbuf_size4_8_sram ;
+wire [0:3] mux_2level_tapbuf_size4_9_sram ;
+wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_9_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__0__mux_2level_tapbuf_size4_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_left_in[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_1 mux_top_track_2 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_left_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_174 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_2 mux_top_track_4 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ top_right_grid_pin_1_[0] , chanx_left_in[28] } ) ,
+ .sram ( mux_2level_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_3 mux_top_track_6 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_left_in[27] } ) ,
+ .sram ( mux_2level_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_4 mux_top_track_8 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_left_in[26] } ) ,
+ .sram ( mux_2level_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_174 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_5 mux_top_track_10 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ top_right_grid_pin_1_[0] , chanx_left_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_174 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_6 mux_left_track_1 (
+ .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_7 mux_left_track_3 (
+ .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_8 mux_left_track_5 (
+ .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_9 mux_left_track_7 (
+ .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_10 mux_left_track_9 (
+ .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_170 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4 mux_left_track_11 (
+ .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_8_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_9_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem_10 mem_left_track_9 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_10_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_11_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_0 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] ,
+ chanx_left_in[24] } ) ,
+ .sram ( mux_2level_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_1 mux_top_track_44 (
+ .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] ,
+ chanx_left_in[8] } ) ,
+ .sram ( mux_2level_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_174 ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_2 mux_left_track_13 (
+ .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_3 mux_left_track_29 (
+ .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_2level_tapbuf_size3 mux_left_track_45 (
+ .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_mem_2 mem_left_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_mem_3 mem_left_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_28_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_4_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_0 mux_top_track_14 (
+ .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) ,
+ .sram ( mux_2level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_top_out[7] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_1 mux_top_track_16 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) ,
+ .sram ( mux_2level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_2 mux_top_track_18 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_top_out[9] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_3 mux_top_track_20 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) ,
+ .sram ( mux_2level_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_4 mux_top_track_22 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) ,
+ .sram ( mux_2level_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chany_top_out[11] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_5 mux_top_track_24 (
+ .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) ,
+ .sram ( mux_2level_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_6 mux_top_track_26 (
+ .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) ,
+ .sram ( mux_2level_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chany_top_out[13] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_7 mux_top_track_28 (
+ .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) ,
+ .sram ( mux_2level_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_8 mux_top_track_36 (
+ .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) ,
+ .sram ( mux_2level_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_9 mux_top_track_38 (
+ .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) ,
+ .sram ( mux_2level_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chany_top_out[19] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_10 mux_top_track_40 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+ .sram ( mux_2level_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chany_top_out[20] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_11 mux_top_track_42 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) ,
+ .sram ( mux_2level_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chany_top_out[21] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_12 mux_top_track_46 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) ,
+ .sram ( mux_2level_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chany_top_out[23] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_13 mux_top_track_48 (
+ .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) ,
+ .sram ( mux_2level_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+ .out ( chany_top_out[24] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_14 mux_top_track_50 (
+ .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) ,
+ .sram ( mux_2level_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chany_top_out[25] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_15 mux_left_track_15 (
+ .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_16 mux_left_track_17 (
+ .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_17 mux_left_track_19 (
+ .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_171 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_18 mux_left_track_21 (
+ .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_171 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_19 mux_left_track_23 (
+ .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_171 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_20 mux_left_track_25 (
+ .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_170 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_21 mux_left_track_27 (
+ .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
+ .out ( chanx_left_out[13] ) , .p0 ( optlc_net_170 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_22 mux_left_track_31 (
+ .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_170 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_23 mux_left_track_33 (
+ .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_24 mux_left_track_35 (
+ .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_24_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_171 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_25 mux_left_track_37 (
+ .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_25_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_171 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_26 mux_left_track_39 (
+ .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_26_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_left_out[19] ) , .p0 ( optlc_net_171 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_27 mux_left_track_41 (
+ .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_27_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
+ .out ( chanx_left_out[20] ) , .p0 ( optlc_net_170 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_28 mux_left_track_43 (
+ .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_28_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chanx_left_out[21] ) , .p0 ( optlc_net_170 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_29 mux_left_track_47 (
+ .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_29_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
+ .out ( chanx_left_out[23] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_30 mux_left_track_49 (
+ .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_30_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chanx_left_out[24] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_31 mux_left_track_51 (
+ .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_31_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
+ .out ( chanx_left_out[25] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_32 mux_left_track_53 (
+ .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_32_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_171 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_33 mux_left_track_55 (
+ .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_33_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
+ .out ( chanx_left_out[27] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_34 mux_left_track_57 (
+ .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_34_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chanx_left_out[28] ) , .p0 ( optlc_net_173 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2 mux_left_track_59 (
+ .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_35_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
+ .out ( chanx_left_out[29] ) , .p0 ( optlc_net_172 ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_10 mem_top_track_40 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_11 mem_top_track_42 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_11_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_12 mem_top_track_46 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_12_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_13 mem_top_track_48 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_13_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_14 mem_top_track_50 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_14_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_15 mem_left_track_15 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_15_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_16 mem_left_track_17 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_16_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_17 mem_left_track_19 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_17_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_18 mem_left_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_18_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_19 mem_left_track_23 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_19_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_20 mem_left_track_25 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_20_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_21 mem_left_track_27 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_21_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_22 mem_left_track_31 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_22_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_23 mem_left_track_33 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_23_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_24 mem_left_track_35 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_24_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_25 mem_left_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_25_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_26 mem_left_track_39 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_26_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_26_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_27 mem_left_track_41 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_26_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_27_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_27_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_28 mem_left_track_43 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_27_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_28_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_28_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_29 mem_left_track_47 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_29_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_29_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_30 mem_left_track_49 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_29_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_30_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_30_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_31 mem_left_track_51 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_30_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_31_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_31_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_32 mem_left_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_31_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_32_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_32_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_33 mem_left_track_55 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_32_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_33_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_33_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem_34 mem_left_track_57 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_33_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_34_sram ) ) ;
+sb_2__0__mux_2level_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_35_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) ,
+ .HI ( optlc_net_168 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( chanx_left_in[1] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( chanx_left_in[2] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[3] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[4] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[13] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_83__82 ( .A ( chanx_left_in[14] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_84__83 ( .A ( chanx_left_in[15] ) ,
+ .X ( ropt_net_193 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( pReset_W_in ) , .Y ( BUF_net_167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) ,
+ .HI ( optlc_net_169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) ,
+ .HI ( optlc_net_170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) ,
+ .HI ( optlc_net_171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) ,
+ .HI ( optlc_net_172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) ,
+ .HI ( optlc_net_173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) ,
+ .HI ( optlc_net_174 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1386 ( .A ( ropt_net_193 ) ,
+ .X ( chany_top_out[15] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_106__105 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_204 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_203 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_202 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_200 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_198 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_198 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_196 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_195 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_195 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_193 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_193 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_191 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_191 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_189 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size6_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_75 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_74 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_56 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_74 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_75 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_188 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_188 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_73 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_72 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_71 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_55 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_54 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_55 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_71 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_72 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_186 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_70 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_69 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_68 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_53 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_52 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_52 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_53 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_68 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_69 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_70 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_184 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_184 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_67 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_66 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_65 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_51 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_50 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_51 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_65 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_66 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_182 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_182 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_64 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_63 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_49 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_48 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_49 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_63 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_64 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_62 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_61 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_47 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_46 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_47 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_61 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_180 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_60 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_59 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_45 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_44 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_45 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_59 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_179 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_58 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_57 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_43 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_42 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_43 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_57 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_177 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_56 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_55 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_41 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_40 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_41 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_55 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_54 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_53 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_39 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_38 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_39 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_53 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_176 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_52 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_51 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_37 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_36 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_37 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_51 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_174 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_50 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_49 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_35 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_34 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_35 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_49 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_50 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_48 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_47 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_33 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_32 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_33 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_47 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_48 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_1_ ( .in ( in[3:4] ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_172 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_46 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_45 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_31 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_31 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_45 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_46 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_170 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_13 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_44 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_43 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_29 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_43 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_44 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_13 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_168 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_27 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_41 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_42 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_167 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__2__local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_25 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_39 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_165 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size9_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size9_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_506_ ) ) ;
+sb_1__2__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__2__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_9 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_10 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_163 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_8 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__2__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_6 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_7 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size10_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_505_ ) ) ;
+sb_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__2__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_3 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_4 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_161 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__2__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_0 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_1 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size8_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size8_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size8_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sb_1__2__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_23 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_35 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_36 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_37 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_38 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_159 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_159 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_31 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_32 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_33 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_27 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_28 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_29 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_30 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_242 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1436 ( .A ( copt_net_220 ) ,
+ .X ( copt_net_219 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1437 ( .A ( copt_net_221 ) ,
+ .X ( copt_net_220 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1438 ( .A ( copt_net_222 ) ,
+ .X ( copt_net_221 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1439 ( .A ( copt_net_223 ) ,
+ .X ( copt_net_222 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1440 ( .A ( copt_net_224 ) ,
+ .X ( copt_net_223 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1441 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_224 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1467 ( .A ( copt_net_219 ) ,
+ .X ( ropt_net_236 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1468 ( .A ( ropt_net_236 ) ,
+ .X ( ropt_net_237 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1469 ( .A ( ropt_net_240 ) ,
+ .X ( ropt_net_238 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1470 ( .A ( ropt_net_237 ) ,
+ .X ( ropt_net_239 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1471 ( .A ( ropt_net_239 ) ,
+ .X ( ropt_net_240 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1472 ( .A ( ropt_net_238 ) ,
+ .X ( ropt_net_241 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1473 ( .A ( ropt_net_241 ) ,
+ .X ( ropt_net_242 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_24 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_25 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_26 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_21 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_19 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_157 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_15 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_155 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_13 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_154 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_152 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_208 ( .A ( BUF_net_209 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_209 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_209 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__2__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__2__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_150 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ;
+endmodule
+
+
+module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ ,
+ right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
+ right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
+ bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
+ bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
+ bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ ,
+ bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in ,
+ left_top_grid_pin_1_ , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
+ left_bottom_grid_pin_43_ , ccff_head , chanx_right_out ,
+ chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT ,
+ pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out ,
+ prog_clk_0_S_in ) ;
+input [0:0] pReset ;
+input [0:29] chanx_right_in ;
+input [0:0] right_top_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:0] right_bottom_grid_pin_42_ ;
+input [0:0] right_bottom_grid_pin_43_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:0] bottom_left_grid_pin_50_ ;
+input [0:0] bottom_left_grid_pin_51_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_top_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] left_bottom_grid_pin_42_ ;
+input [0:0] left_bottom_grid_pin_43_ ;
+input [0:0] ccff_head ;
+output [0:29] chanx_right_out ;
+output [0:29] chany_bottom_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_BOT ;
+output SC_OUT_BOT ;
+input pReset_S_in ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_W_out ;
+output pReset_E_out ;
+input prog_clk_0_S_in ;
+
+wire ropt_net_234 ;
+wire ropt_net_233 ;
+wire ropt_net_231 ;
+wire ropt_net_235 ;
+wire ropt_net_232 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_tapbuf_size10_0_sram ;
+wire [0:3] mux_2level_tapbuf_size10_1_sram ;
+wire [0:0] mux_2level_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size2_0_sram ;
+wire [0:1] mux_2level_tapbuf_size2_10_sram ;
+wire [0:1] mux_2level_tapbuf_size2_1_sram ;
+wire [0:1] mux_2level_tapbuf_size2_2_sram ;
+wire [0:1] mux_2level_tapbuf_size2_3_sram ;
+wire [0:1] mux_2level_tapbuf_size2_4_sram ;
+wire [0:1] mux_2level_tapbuf_size2_5_sram ;
+wire [0:1] mux_2level_tapbuf_size2_6_sram ;
+wire [0:1] mux_2level_tapbuf_size2_7_sram ;
+wire [0:1] mux_2level_tapbuf_size2_8_sram ;
+wire [0:1] mux_2level_tapbuf_size2_9_sram ;
+wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size3_0_sram ;
+wire [0:1] mux_2level_tapbuf_size3_1_sram ;
+wire [0:1] mux_2level_tapbuf_size3_2_sram ;
+wire [0:1] mux_2level_tapbuf_size3_3_sram ;
+wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size4_0_sram ;
+wire [0:3] mux_2level_tapbuf_size4_1_sram ;
+wire [0:3] mux_2level_tapbuf_size4_2_sram ;
+wire [0:3] mux_2level_tapbuf_size4_3_sram ;
+wire [0:3] mux_2level_tapbuf_size4_4_sram ;
+wire [0:3] mux_2level_tapbuf_size4_5_sram ;
+wire [0:3] mux_2level_tapbuf_size4_6_sram ;
+wire [0:3] mux_2level_tapbuf_size4_7_sram ;
+wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size5_0_sram ;
+wire [0:3] mux_2level_tapbuf_size5_1_sram ;
+wire [0:3] mux_2level_tapbuf_size5_2_sram ;
+wire [0:3] mux_2level_tapbuf_size5_3_sram ;
+wire [0:3] mux_2level_tapbuf_size5_4_sram ;
+wire [0:0] mux_2level_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size6_0_sram ;
+wire [0:3] mux_2level_tapbuf_size6_1_sram ;
+wire [0:3] mux_2level_tapbuf_size6_2_sram ;
+wire [0:3] mux_2level_tapbuf_size6_3_sram ;
+wire [0:0] mux_2level_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size7_0_sram ;
+wire [0:3] mux_2level_tapbuf_size7_1_sram ;
+wire [0:3] mux_2level_tapbuf_size7_2_sram ;
+wire [0:3] mux_2level_tapbuf_size7_3_sram ;
+wire [0:3] mux_2level_tapbuf_size7_4_sram ;
+wire [0:3] mux_2level_tapbuf_size7_5_sram ;
+wire [0:3] mux_2level_tapbuf_size7_6_sram ;
+wire [0:3] mux_2level_tapbuf_size7_7_sram ;
+wire [0:3] mux_2level_tapbuf_size7_8_sram ;
+wire [0:0] mux_2level_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_8_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size8_0_sram ;
+wire [0:3] mux_2level_tapbuf_size8_1_sram ;
+wire [0:3] mux_2level_tapbuf_size8_2_sram ;
+wire [0:0] mux_2level_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size9_0_sram ;
+wire [0:3] mux_2level_tapbuf_size9_1_sram ;
+wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
+
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__2__mux_2level_tapbuf_size7_0 mux_right_track_0 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[9] ,
+ chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_1 mux_right_track_2 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_bottom_in[8] ,
+ chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) ,
+ .sram ( mux_2level_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_2 mux_right_track_12 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] ,
+ chanx_right_out[12] , chanx_right_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_212 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_3 mux_right_track_20 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] ,
+ chanx_right_out[13] , chanx_right_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_212 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_4 mux_right_track_28 (
+ .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] ,
+ chanx_right_out[15] , chanx_right_out[29] } ) ,
+ .sram ( mux_2level_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_215 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_5 mux_left_track_1 (
+ .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] ,
+ chany_bottom_in[21] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_6 mux_left_track_13 (
+ .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] ,
+ chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_7 mux_left_track_21 (
+ .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] ,
+ chany_bottom_in[16] , chany_bottom_in[27] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_210 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7 mux_left_track_29 (
+ .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] ,
+ chany_bottom_in[17] , chany_bottom_in[28] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_210 ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem_0 mem_right_track_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem_1 mem_right_track_2 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem_2 mem_right_track_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_2_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem_3 mem_right_track_20 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_3_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem_4 mem_right_track_28 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_4_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_5_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem_6 mem_left_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_6_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem_7 mem_left_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_7_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_8_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size8_0 mux_right_track_4 (
+ .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_bottom_in[7] ,
+ chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] ,
+ chanx_right_out[23] } ) ,
+ .sram ( mux_2level_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__2__mux_2level_tapbuf_size8_1 mux_left_track_3 (
+ .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] ,
+ chany_bottom_in[11] , chany_bottom_in[22] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__2__mux_2level_tapbuf_size8 mux_left_track_5 (
+ .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] ,
+ chany_bottom_in[12] , chany_bottom_in[23] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__2__mux_2level_tapbuf_size8_mem_0 mem_right_track_4 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_2_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size10_0 mux_right_track_6 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] ,
+ right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_bottom_in[6] ,
+ chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] ,
+ chanx_right_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( { aps_rename_507_ } ) ,
+ .p0 ( optlc_net_212 ) ) ;
+sb_1__2__mux_2level_tapbuf_size10 mux_left_track_7 (
+ .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] ,
+ chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__2__mux_2level_tapbuf_size10_mem_0 mem_right_track_6 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size9_0 mux_right_track_10 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] ,
+ chanx_right_out[11] , chanx_right_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( { aps_rename_508_ } ) ,
+ .p0 ( optlc_net_212 ) ) ;
+sb_1__2__mux_2level_tapbuf_size9 mux_left_track_11 (
+ .in ( { chanx_left_out[11] , ropt_net_231 , chany_bottom_in[3] ,
+ chany_bottom_in[14] , chany_bottom_in[25] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__2__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_0 mux_right_track_36 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] ,
+ chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) ,
+ .sram ( mux_2level_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_215 ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_1 mux_right_track_44 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] ,
+ chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) ,
+ .sram ( mux_2level_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_215 ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_2 mux_bottom_track_5 (
+ .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) ,
+ .sram ( mux_2level_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_3 mux_bottom_track_11 (
+ .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_right_out[12] ,
+ chanx_left_in[13] } ) ,
+ .sram ( mux_2level_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
+ SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__2__mux_2level_tapbuf_size5 mux_left_track_37 (
+ .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] ,
+ chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
+ SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_mem_0 mem_right_track_36 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_mem_1 mem_right_track_44 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_mem_2 mem_bottom_track_5 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_2_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_mem_3 mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_3_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_4_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_0 mux_right_track_52 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] ,
+ chany_bottom_in[21] , chanx_right_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
+ SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_212 ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_1 mux_bottom_track_13 (
+ .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] ,
+ chanx_right_out[13] , chanx_left_in[17] } ) ,
+ .sram ( mux_2level_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
+ SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_2 mux_bottom_track_15 (
+ .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] ,
+ chanx_right_out[15] , chanx_left_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
+ SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_3 mux_bottom_track_17 (
+ .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] ,
+ chanx_right_out[16] , chanx_left_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 ,
+ SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_4 mux_bottom_track_19 (
+ .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] ,
+ chanx_right_out[17] , chanx_left_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
+ SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_5 mux_bottom_track_37 (
+ .in ( { chanx_left_out[29] , chanx_right_in[29] ,
+ bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) ,
+ .sram ( mux_2level_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 ,
+ SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_6 mux_left_track_45 (
+ .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 ,
+ SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__2__mux_2level_tapbuf_size4 mux_left_track_53 (
+ .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 ,
+ SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_217 ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_52 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_mem_1 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_mem_2 mem_bottom_track_15 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_mem_3 mem_bottom_track_17 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_mem_4 mem_bottom_track_19 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_mem_5 mem_bottom_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_mem_6 mem_left_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( { copt_net_230 } ) ,
+ .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size6_0 mux_bottom_track_1 (
+ .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[1] , chanx_right_out[4] } ) ,
+ .sram ( mux_2level_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 ,
+ SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_217 ) ) ;
+sb_1__2__mux_2level_tapbuf_size6_1 mux_bottom_track_3 (
+ .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] ,
+ bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[2] , chanx_right_out[7] } ) ,
+ .sram ( mux_2level_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 ,
+ SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_217 ) ) ;
+sb_1__2__mux_2level_tapbuf_size6_2 mux_bottom_track_7 (
+ .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[5] , chanx_right_out[9] } ) ,
+ .sram ( mux_2level_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 ,
+ SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__2__mux_2level_tapbuf_size6 mux_bottom_track_9 (
+ .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] ,
+ bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[9] , chanx_right_out[11] } ) ,
+ .sram ( mux_2level_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 ,
+ SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_217 ) ) ;
+sb_1__2__mux_2level_tapbuf_size6_mem_0 mem_bottom_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size6_mem_1 mem_bottom_track_3 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size6_mem_2 mem_bottom_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_3_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size3_0 mux_bottom_track_21 (
+ .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] ,
+ chanx_right_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size3_1 mux_bottom_track_23 (
+ .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] ,
+ chanx_right_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
+ .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_217 ) ) ;
+sb_1__2__mux_2level_tapbuf_size3_2 mux_bottom_track_25 (
+ .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] ,
+ chanx_right_out[21] } ) ,
+ .sram ( mux_2level_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size3 mux_bottom_track_27 (
+ .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] ,
+ chanx_right_out[23] } ) ,
+ .sram ( mux_2level_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
+ .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size3_mem_1 mem_bottom_track_23 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size3_mem_2 mem_bottom_track_25 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size3_mem mem_bottom_track_27 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_0 mux_bottom_track_29 (
+ .in ( { chanx_left_out[24] , chanx_right_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_1 mux_bottom_track_31 (
+ .in ( { ropt_net_231 , chanx_right_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
+ .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_210 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_2 mux_bottom_track_33 (
+ .in ( { chanx_left_out[27] , chanx_right_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) ,
+ .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_3 mux_bottom_track_35 (
+ .in ( { chanx_left_out[28] , chanx_right_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
+ .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_4 mux_bottom_track_39 (
+ .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) ,
+ .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_5 mux_bottom_track_41 (
+ .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
+ .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_210 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_6 mux_bottom_track_43 (
+ .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) ,
+ .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_7 mux_bottom_track_45 (
+ .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_8 mux_bottom_track_47 (
+ .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) ,
+ .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_9 mux_bottom_track_49 (
+ .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
+ .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2 mux_bottom_track_51 (
+ .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) ,
+ .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_1 mem_bottom_track_31 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_2 mem_bottom_track_33 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_3 mem_bottom_track_35 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_4 mem_bottom_track_39 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_5 mem_bottom_track_41 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_6 mem_bottom_track_43 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_7 mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_8 mem_bottom_track_47 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem_9 mem_bottom_track_49 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+sb_1__2__mux_2level_tapbuf_size2_mem mem_bottom_track_51 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( net_net_207 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_107__106 ( .A ( chanx_right_in[0] ) ,
+ .X ( ropt_net_234 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_right_in[1] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_109__108 ( .A ( chanx_right_in[2] ) ,
+ .X ( ropt_net_233 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_125__124 ( .A ( chanx_right_in[24] ) ,
+ .X ( ropt_net_231 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( chanx_left_in[0] ) ,
+ .X ( ropt_net_235 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_145__144 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_146__145 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_149__148 ( .A ( SC_IN_BOT ) , .X ( ropt_net_232 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_206 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_206 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_207 ( .A ( net_net_207 ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) ,
+ .HI ( optlc_net_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) ,
+ .HI ( optlc_net_211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) ,
+ .HI ( optlc_net_212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) ,
+ .HI ( optlc_net_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) ,
+ .HI ( optlc_net_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) ,
+ .HI ( optlc_net_215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) ,
+ .HI ( optlc_net_216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) ,
+ .HI ( optlc_net_217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) ,
+ .HI ( optlc_net_218 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_229 ( .A ( aps_rename_507_ ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_230 ( .A ( aps_rename_508_ ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1461 ( .A ( copt_net_230 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1462 ( .A ( ropt_net_231 ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1463 ( .A ( ropt_net_232 ) ,
+ .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1464 ( .A ( ropt_net_233 ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1465 ( .A ( ropt_net_234 ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1466 ( .A ( ropt_net_235 ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_41 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_42 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_38 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_39 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_196 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_196 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_35 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_32 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_33 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_186 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_29 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_30 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_31 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_184 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_184 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_26 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_27 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_182 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_182 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__1__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_24 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_180 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_180 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_21 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_198 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_198 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_194 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_194 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__1__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_10 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size9_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size9_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size9_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size9_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_102 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_101 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_62 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_521_ ) ) ;
+sb_1__1__local_encoder2to4_62 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_101 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_102 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_178 ( .A ( aps_rename_521_ ) ,
+ .Y ( BUF_net_178 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_100 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_99 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_98 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_61 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_60 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_520_ ) ) ;
+sb_1__1__local_encoder2to4_60 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_61 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_98 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_99 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_100 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_176 ( .A ( aps_rename_520_ ) ,
+ .Y ( BUF_net_176 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_97 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_96 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_95 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_59 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_58 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_519_ ) ) ;
+sb_1__1__local_encoder2to4_58 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_59 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_95 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_96 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_97 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_174 ( .A ( aps_rename_519_ ) ,
+ .Y ( BUF_net_174 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_94 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_93 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_92 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_57 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_56 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_518_ ) ) ;
+sb_1__1__local_encoder2to4_56 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_57 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_92 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_93 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_94 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_172 ( .A ( aps_rename_518_ ) ,
+ .Y ( BUF_net_172 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_91 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_90 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_89 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_88 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_55 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_54 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) ,
+ .X ( aps_rename_517_ ) ) ;
+sb_1__1__local_encoder2to4_54 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_55 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_88 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_89 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_90 mux_l1_in_2_ (
+ .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_91 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_2_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_170 ( .A ( aps_rename_517_ ) ,
+ .Y ( BUF_net_170 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_87 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_86 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_85 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_84 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_53 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_52 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) ,
+ .X ( aps_rename_516_ ) ) ;
+sb_1__1__local_encoder2to4_52 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_53 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_84 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_85 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_86 mux_l1_in_2_ (
+ .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_87 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_2_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_168 ( .A ( aps_rename_516_ ) ,
+ .Y ( BUF_net_168 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_83 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_82 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_81 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_80 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_51 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_50 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( net_net_166 ) ) ;
+sb_1__1__local_encoder2to4_50 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_51 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_80 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_81 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_82 mux_l1_in_2_ (
+ .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_83 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_2_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_166 ( .A ( net_net_166 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_79 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_78 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_77 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_76 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_49 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_48 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_48 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_49 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_76 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_77 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_78 mux_l1_in_2_ (
+ .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_79 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_2_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_75 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_74 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_73 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_72 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_47 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_46 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) ,
+ .X ( aps_rename_515_ ) ) ;
+sb_1__1__local_encoder2to4_46 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_47 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_72 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_73 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_74 mux_l1_in_2_ (
+ .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_75 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_2_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_515_ ) ,
+ .Y ( BUF_net_165 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_71 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_70 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_69 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_68 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_45 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_44 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) ,
+ .X ( aps_rename_514_ ) ) ;
+sb_1__1__local_encoder2to4_44 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_45 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_68 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_69 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_70 mux_l1_in_2_ (
+ .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_71 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_2_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_514_ ) ,
+ .Y ( BUF_net_163 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_67 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_66 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_65 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_64 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_43 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_42 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) ,
+ .X ( aps_rename_513_ ) ) ;
+sb_1__1__local_encoder2to4_42 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_43 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_64 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_65 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_66 mux_l1_in_2_ (
+ .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_67 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_2_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_513_ ) ,
+ .Y ( BUF_net_161 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_63 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_62 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_61 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_60 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_41 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_40 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) ,
+ .X ( aps_rename_512_ ) ) ;
+sb_1__1__local_encoder2to4_40 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_41 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_60 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_61 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_62 mux_l1_in_2_ (
+ .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_63 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_2_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_512_ ) ,
+ .Y ( BUF_net_159 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_59 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_58 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_57 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_39 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_38 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_511_ ) ) ;
+sb_1__1__local_encoder2to4_38 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_39 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_57 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_58 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_59 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_157 ( .A ( aps_rename_511_ ) ,
+ .Y ( BUF_net_157 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_56 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_55 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_54 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_37 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_36 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_10 ( in , sram , sram_inv , out ,
+ p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_510_ ) ) ;
+sb_1__1__local_encoder2to4_36 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_37 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_54 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_55 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_56 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_155 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_53 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_52 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_51 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_35 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_34 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_509_ ) ) ;
+sb_1__1__local_encoder2to4_34 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_35 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_51 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_52 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_53 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_153 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_50 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_49 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_48 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_33 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_32 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_33 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_48 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_49 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_50 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_47 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_46 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_45 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_31 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_45 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_46 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_47 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_44 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_43 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_42 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_151 ) ) ;
+sb_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_42 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_43 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_44 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_41 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_40 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_39 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_508_ ) ) ;
+sb_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_39 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_40 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_41 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_150 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_150 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_38 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_37 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_507_ ) ) ;
+sb_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_36 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_37 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_38 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_148 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_35 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_33 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_33 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_34 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_35 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_32 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_31 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_506_ ) ) ;
+sb_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_30 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_31 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_32 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_146 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_29 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_27 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_27 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_28 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_26 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_25 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_505_ ) ) ;
+sb_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_24 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_25 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_26 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ (
+ .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_192 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_192 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_224 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1433 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_209 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1440 ( .A ( copt_net_217 ) ,
+ .X ( copt_net_216 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1441 ( .A ( copt_net_220 ) ,
+ .X ( copt_net_217 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1442 ( .A ( copt_net_209 ) ,
+ .X ( copt_net_218 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1443 ( .A ( copt_net_218 ) ,
+ .X ( copt_net_219 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1444 ( .A ( copt_net_219 ) ,
+ .X ( copt_net_220 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1445 ( .A ( copt_net_216 ) ,
+ .X ( ropt_net_224 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_23 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_21 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_22 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l1_in_2_ (
+ .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_20 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_19 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_18 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_19 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_20 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_2_ (
+ .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_17 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_144 ) ) ;
+sb_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_15 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_16 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l1_in_2_ (
+ .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( net_net_144 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_14 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_13 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_12 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_13 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_14 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_2_ (
+ .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_11 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_9 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_10 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l1_in_2_ (
+ .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_8 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_6 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_7 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_2_ (
+ .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_3 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_4 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_2_ (
+ .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_2level_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_0 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_1 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__1__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_2_ (
+ .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+endmodule
+
+
+module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
+ top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
+ top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
+ top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ ,
+ right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ ,
+ right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ ,
+ right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ ,
+ right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ ,
+ bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ ,
+ bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ ,
+ bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ ,
+ bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
+ left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out ,
+ chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in ,
+ Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out ,
+ pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in ,
+ prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out ,
+ prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in ,
+ prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out ,
+ prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in ,
+ prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out ,
+ prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out ,
+ clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out ,
+ clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in ,
+ clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out ,
+ clk_3_S_out ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_left_grid_pin_50_ ;
+input [0:0] top_left_grid_pin_51_ ;
+input [0:29] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:0] right_bottom_grid_pin_42_ ;
+input [0:0] right_bottom_grid_pin_43_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:0] bottom_left_grid_pin_50_ ;
+input [0:0] bottom_left_grid_pin_51_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] left_bottom_grid_pin_42_ ;
+input [0:0] left_bottom_grid_pin_43_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_right_out ;
+output [0:29] chany_bottom_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input Test_en_S_in ;
+output Test_en_N_out ;
+input pReset_S_in ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_N_out ;
+output pReset_W_out ;
+output pReset_E_out ;
+input Reset_S_in ;
+output Reset_N_out ;
+input prog_clk_0_N_in ;
+input prog_clk_1_N_in ;
+input prog_clk_1_S_in ;
+output prog_clk_1_E_out ;
+output prog_clk_1_W_out ;
+input prog_clk_2_N_in ;
+input prog_clk_2_E_in ;
+input prog_clk_2_S_in ;
+input prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+output prog_clk_2_E_out ;
+input prog_clk_3_W_in ;
+input prog_clk_3_E_in ;
+input prog_clk_3_S_in ;
+input prog_clk_3_N_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input clk_1_N_in ;
+input clk_1_S_in ;
+output clk_1_E_out ;
+output clk_1_W_out ;
+input clk_2_N_in ;
+input clk_2_E_in ;
+input clk_2_S_in ;
+input clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+output clk_2_E_out ;
+input clk_3_W_in ;
+input clk_3_E_in ;
+input clk_3_S_in ;
+input clk_3_N_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_tapbuf_size10_0_sram ;
+wire [0:3] mux_2level_tapbuf_size10_10_sram ;
+wire [0:3] mux_2level_tapbuf_size10_11_sram ;
+wire [0:3] mux_2level_tapbuf_size10_1_sram ;
+wire [0:3] mux_2level_tapbuf_size10_2_sram ;
+wire [0:3] mux_2level_tapbuf_size10_3_sram ;
+wire [0:3] mux_2level_tapbuf_size10_4_sram ;
+wire [0:3] mux_2level_tapbuf_size10_5_sram ;
+wire [0:3] mux_2level_tapbuf_size10_6_sram ;
+wire [0:3] mux_2level_tapbuf_size10_7_sram ;
+wire [0:3] mux_2level_tapbuf_size10_8_sram ;
+wire [0:3] mux_2level_tapbuf_size10_9_sram ;
+wire [0:0] mux_2level_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size10_mem_9_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size11_0_sram ;
+wire [0:3] mux_2level_tapbuf_size11_1_sram ;
+wire [0:3] mux_2level_tapbuf_size11_2_sram ;
+wire [0:3] mux_2level_tapbuf_size11_3_sram ;
+wire [0:3] mux_2level_tapbuf_size11_4_sram ;
+wire [0:3] mux_2level_tapbuf_size11_5_sram ;
+wire [0:3] mux_2level_tapbuf_size11_6_sram ;
+wire [0:3] mux_2level_tapbuf_size11_7_sram ;
+wire [0:0] mux_2level_tapbuf_size11_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size11_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size11_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size11_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size11_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size11_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size11_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size11_mem_7_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size12_0_sram ;
+wire [0:3] mux_2level_tapbuf_size12_1_sram ;
+wire [0:3] mux_2level_tapbuf_size12_2_sram ;
+wire [0:3] mux_2level_tapbuf_size12_3_sram ;
+wire [0:3] mux_2level_tapbuf_size12_4_sram ;
+wire [0:3] mux_2level_tapbuf_size12_5_sram ;
+wire [0:3] mux_2level_tapbuf_size12_6_sram ;
+wire [0:3] mux_2level_tapbuf_size12_7_sram ;
+wire [0:0] mux_2level_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size6_0_sram ;
+wire [0:3] mux_2level_tapbuf_size6_10_sram ;
+wire [0:3] mux_2level_tapbuf_size6_11_sram ;
+wire [0:3] mux_2level_tapbuf_size6_1_sram ;
+wire [0:3] mux_2level_tapbuf_size6_2_sram ;
+wire [0:3] mux_2level_tapbuf_size6_3_sram ;
+wire [0:3] mux_2level_tapbuf_size6_4_sram ;
+wire [0:3] mux_2level_tapbuf_size6_5_sram ;
+wire [0:3] mux_2level_tapbuf_size6_6_sram ;
+wire [0:3] mux_2level_tapbuf_size6_7_sram ;
+wire [0:3] mux_2level_tapbuf_size6_8_sram ;
+wire [0:3] mux_2level_tapbuf_size6_9_sram ;
+wire [0:0] mux_2level_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_9_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size9_0_sram ;
+wire [0:3] mux_2level_tapbuf_size9_1_sram ;
+wire [0:3] mux_2level_tapbuf_size9_2_sram ;
+wire [0:3] mux_2level_tapbuf_size9_3_sram ;
+wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size9_mem_3_ccff_tail ;
+
+assign prog_clk_1_E_out = prog_clk_1_S_in ;
+assign prog_clk_1_W_out = prog_clk_1_S_in ;
+assign prog_clk_2_W_out = prog_clk_2_E_in ;
+assign prog_clk_2_S_out = prog_clk_2_E_in ;
+assign prog_clk_2_N_out = prog_clk_2_E_in ;
+assign prog_clk_2_E_out = prog_clk_2_E_in ;
+assign prog_clk_3_E_out = prog_clk_3_E_in ;
+assign prog_clk_3_W_out = prog_clk_3_E_in ;
+assign prog_clk_3_N_out = prog_clk_3_E_in ;
+assign prog_clk_3_S_out = prog_clk_3_E_in ;
+assign clk_1_E_out = clk_1_S_in ;
+assign clk_1_W_out = clk_1_S_in ;
+assign clk_2_W_out = clk_2_E_in ;
+assign clk_2_S_out = clk_2_E_in ;
+assign clk_2_N_out = clk_2_E_in ;
+assign clk_2_E_out = clk_2_E_in ;
+assign clk_3_E_out = clk_3_E_in ;
+assign clk_3_W_out = clk_3_E_in ;
+assign clk_3_N_out = clk_3_E_in ;
+assign clk_3_S_out = clk_3_E_in ;
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_S_in = prog_clk_1_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_S_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_S_in ;
+assign prog_clk_3_E_in = prog_clk_3_N_in ;
+assign clk_1_S_in = clk_1_N_in ;
+assign clk_2_E_in = clk_2_N_in ;
+assign clk_2_E_in = clk_2_S_in ;
+assign clk_2_E_in = clk_2_W_in ;
+assign clk_3_E_in = clk_3_W_in ;
+assign clk_3_E_in = clk_3_S_in ;
+assign clk_3_E_in = clk_3_N_in ;
+
+sb_1__1__mux_2level_tapbuf_size11_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] ,
+ chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] ,
+ chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size11_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_204 ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_1 mux_top_track_2 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] ,
+ chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] ,
+ chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size11_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( { ropt_net_225 } ) ,
+ .p0 ( optlc_net_199 ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_2 mux_right_track_0 (
+ .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] ,
+ chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size11_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( { aps_rename_522_ } ) ,
+ .p0 ( optlc_net_203 ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_3 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] ,
+ chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) ,
+ .sram ( mux_2level_tapbuf_size11_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( { ZBUF_6_f_0 } ) ,
+ .p0 ( optlc_net_200 ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_4 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] ,
+ chanx_left_out[20] , chanx_right_in[25] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] ,
+ chanx_right_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size11_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( { aps_rename_523_ } ) ,
+ .p0 ( optlc_net_205 ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_5 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] ,
+ chanx_left_out[21] , chanx_right_in[21] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] ,
+ chanx_right_out[21] } ) ,
+ .sram ( mux_2level_tapbuf_size11_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_201 ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_6 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] ,
+ chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] ,
+ chany_top_out[20] , chany_bottom_in[29] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size11_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( { aps_rename_525_ } ) ,
+ .p0 ( optlc_net_205 ) ) ;
+sb_1__1__mux_2level_tapbuf_size11 mux_left_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] ,
+ chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] ,
+ chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size11_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_205 ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size11_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size11_0_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size11_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size11_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size11_1_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_mem_2 mem_right_track_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size11_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size11_2_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_mem_3 mem_right_track_2 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size11_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size11_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size11_3_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_mem_4 mem_bottom_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size11_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size11_4_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_mem_5 mem_bottom_track_3 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size11_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size11_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size11_5_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_mem_6 mem_left_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size11_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size11_6_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size11_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size11_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size11_7_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_0 mux_top_track_4 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] ,
+ chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] ,
+ chanx_right_out[23] , chanx_left_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_199 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_1 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] ,
+ chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] ,
+ chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] ,
+ chanx_left_in[13] , chanx_right_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_207 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_2 mux_top_track_20 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] ,
+ chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] ,
+ chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] ,
+ chanx_right_out[13] , chanx_right_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_202 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_3 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] ,
+ chanx_right_out[8] , chanx_right_out[23] } ) ,
+ .sram ( mux_2level_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( { ZBUF_39_0 } ) ,
+ .p0 ( optlc_net_203 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_4 mux_right_track_12 (
+ .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] ,
+ chanx_right_out[12] , chanx_right_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_202 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_5 mux_right_track_20 (
+ .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] ,
+ chanx_right_out[13] , chanx_right_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_202 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_6 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] ,
+ chanx_right_in[17] , chanx_left_out[23] ,
+ bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] ,
+ chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) ,
+ .sram ( mux_2level_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_199 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_7 mux_bottom_track_13 (
+ .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] ,
+ chanx_left_out[12] , chanx_left_out[27] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_204 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_8 mux_bottom_track_21 (
+ .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] ,
+ chanx_left_out[13] , chanx_left_out[28] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size10_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( { ZBUF_35_0 } ) ,
+ .p0 ( optlc_net_202 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_9 mux_left_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] ,
+ chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] ,
+ chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size10_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_199 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_10 mux_left_track_13 (
+ .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] ,
+ chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] ,
+ chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size10_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_207 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10 mux_left_track_21 (
+ .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] ,
+ chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] ,
+ chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size10_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
+ SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_207 ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size11_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_0_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_1 mem_top_track_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_1_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_2 mem_top_track_20 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_2_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_3 mem_right_track_4 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size11_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_3_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_4 mem_right_track_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_4_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_5 mem_right_track_20 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_5_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_6 mem_bottom_track_5 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size11_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_6_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_7 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_7_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_8 mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_8_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_9 mem_left_track_5 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size11_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_9_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem_10 mem_left_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_10_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_11_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_0 mux_top_track_6 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] ,
+ top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] ,
+ chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] ,
+ chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] ,
+ chanx_left_in[21] , chanx_right_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
+ SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_207 ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_1 mux_top_track_10 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] ,
+ chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] ,
+ chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] ,
+ chanx_left_in[17] , chanx_right_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
+ SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_208 ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_2 mux_right_track_6 (
+ .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] ,
+ chanx_right_out[9] , chanx_right_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
+ SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_206 ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_3 mux_right_track_10 (
+ .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] ,
+ chanx_right_out[11] , chanx_right_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
+ SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_202 ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_4 mux_bottom_track_7 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] ,
+ chanx_right_in[13] , chanx_left_out[24] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 ,
+ SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( { aps_rename_524_ } ) ,
+ .p0 ( optlc_net_199 ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_5 mux_bottom_track_11 (
+ .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] ,
+ chanx_left_out[11] , chanx_left_out[25] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
+ SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_207 ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_6 mux_left_track_7 (
+ .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] ,
+ chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] ,
+ chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 ,
+ SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_199 ) ) ;
+sb_1__1__mux_2level_tapbuf_size12 mux_left_track_11 (
+ .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] ,
+ chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] ,
+ chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 ,
+ SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_208 ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size12_0_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_mem_1 mem_top_track_10 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size12_1_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_mem_2 mem_right_track_6 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size12_2_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_mem_3 mem_right_track_10 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size12_3_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_mem_4 mem_bottom_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size12_4_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_mem_5 mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size12_5_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_mem_6 mem_left_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size12_6_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size12_7_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size9_0 mux_top_track_28 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] ,
+ chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] ,
+ chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] ,
+ chanx_right_out[29] } ) ,
+ .sram ( mux_2level_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 ,
+ SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_202 ) ) ;
+sb_1__1__mux_2level_tapbuf_size9_1 mux_right_track_28 (
+ .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] ,
+ right_bottom_grid_pin_38_[0] , chany_bottom_in[2] ,
+ chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] ,
+ chanx_right_out[29] } ) ,
+ .sram ( mux_2level_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 ,
+ SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_206 ) ) ;
+sb_1__1__mux_2level_tapbuf_size9_2 mux_bottom_track_29 (
+ .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] ,
+ chanx_left_out[15] , chanx_left_out[29] ,
+ bottom_left_grid_pin_46_[0] , chanx_right_out[15] ,
+ chanx_left_in[21] , chanx_right_out[29] } ) ,
+ .sram ( mux_2level_tapbuf_size9_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 ,
+ SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_206 ) ) ;
+sb_1__1__mux_2level_tapbuf_size9 mux_left_track_29 (
+ .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] ,
+ chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] ,
+ chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size9_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 ,
+ SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_204 ) ) ;
+sb_1__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_0_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size9_mem_1 mem_right_track_28 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_1_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size9_mem_2 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_2_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_3_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_0 mux_top_track_36 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] ,
+ chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] ,
+ chanx_right_out[16] } ) ,
+ .sram ( mux_2level_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 ,
+ SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_206 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_1 mux_top_track_44 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] ,
+ chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_2level_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 ,
+ SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_199 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_2 mux_top_track_52 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] ,
+ chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] ,
+ chanx_right_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 ,
+ SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
+ .out ( chany_top_out[26] ) , .p0 ( optlc_net_205 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_3 mux_right_track_36 (
+ .in ( { chany_bottom_out[16] , chany_top_in[17] ,
+ right_bottom_grid_pin_39_[0] , chany_bottom_in[1] ,
+ chany_top_out[16] , chanx_right_out[16] } ) ,
+ .sram ( mux_2level_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 ,
+ SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_206 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_4 mux_right_track_44 (
+ .in ( { chany_bottom_out[17] , chany_top_in[21] ,
+ right_bottom_grid_pin_40_[0] , chany_bottom_in[0] ,
+ chany_top_out[17] , chanx_right_out[17] } ) ,
+ .sram ( mux_2level_tapbuf_size6_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 ,
+ SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_200 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_5 mux_right_track_52 (
+ .in ( { chany_bottom_out[19] , chany_top_in[25] ,
+ right_bottom_grid_pin_41_[0] , chany_top_out[19] ,
+ chany_bottom_in[29] , chanx_right_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size6_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 ,
+ SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_200 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_6 mux_bottom_track_37 (
+ .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] ,
+ bottom_left_grid_pin_47_[0] , chanx_right_out[16] ,
+ chanx_left_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size6_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 ,
+ SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
+ .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_203 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_7 mux_bottom_track_45 (
+ .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] ,
+ bottom_left_grid_pin_48_[0] , chanx_right_out[17] ,
+ chanx_left_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size6_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 ,
+ SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_201 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_8 mux_bottom_track_53 (
+ .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size6_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 ,
+ SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) ,
+ .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_201 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_9 mux_left_track_37 (
+ .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] ,
+ chany_top_out[16] , chany_bottom_in[17] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 ,
+ SYNOPSYS_UNCONNECTED_167 , SYNOPSYS_UNCONNECTED_168 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_204 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_10 mux_left_track_45 (
+ .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] ,
+ chany_top_out[17] , chany_bottom_in[21] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_169 , SYNOPSYS_UNCONNECTED_170 ,
+ SYNOPSYS_UNCONNECTED_171 , SYNOPSYS_UNCONNECTED_172 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_205 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6 mux_left_track_53 (
+ .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] ,
+ chany_top_out[19] , chany_bottom_in[25] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_173 , SYNOPSYS_UNCONNECTED_174 ,
+ SYNOPSYS_UNCONNECTED_175 , SYNOPSYS_UNCONNECTED_176 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_201 ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_3 mem_right_track_36 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_3_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_4 mem_right_track_44 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_4_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_5 mem_right_track_52 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_5_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_6 mem_bottom_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_6_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_7 mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_7_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_8 mem_bottom_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_8_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_9 mem_left_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_9_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem_10 mem_left_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_10_sram ) ) ;
+sb_1__1__mux_2level_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_10_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size6_11_sram ) ) ;
+sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) ,
+ .X ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( aps_rename_526_ ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( aps_rename_527_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_4 Reset_N_FTB01 ( .A ( Reset_S_in ) ,
+ .X ( Reset_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_188 ( .A ( aps_rename_526_ ) ,
+ .Y ( BUF_net_188 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_190 ( .A ( aps_rename_527_ ) ,
+ .Y ( BUF_net_190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_177 ) ,
+ .HI ( optlc_net_199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_178 ) ,
+ .HI ( optlc_net_200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( SYNOPSYS_UNCONNECTED_179 ) ,
+ .HI ( optlc_net_201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( SYNOPSYS_UNCONNECTED_180 ) ,
+ .HI ( optlc_net_202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( SYNOPSYS_UNCONNECTED_181 ) ,
+ .HI ( optlc_net_203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_182 ) ,
+ .HI ( optlc_net_204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_183 ) ,
+ .HI ( optlc_net_205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_184 ) ,
+ .HI ( optlc_net_206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_185 ) ,
+ .HI ( optlc_net_207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( SYNOPSYS_UNCONNECTED_186 ) ,
+ .HI ( optlc_net_208 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_39_inst_221 ( .A ( aps_rename_522_ ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_726 ( .A ( aps_rename_524_ ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_727 ( .A ( aps_rename_525_ ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_728 ( .A ( aps_rename_523_ ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1430 ( .A ( ZBUF_6_f_0 ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_35_inst_1431 ( .A ( ZBUF_35_0 ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1432 ( .A ( ZBUF_39_0 ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1462 ( .A ( ropt_net_225 ) ,
+ .X ( chany_top_out[1] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size9_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( mem_out[3] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size9_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[3] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size9_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[3] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to4_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__0__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_9 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_10 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_8 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to4_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to4_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_199 ) ) ;
+sb_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__0__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_6 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_7 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_199 ( .A ( net_net_199 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to4_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to4_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__0__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_3 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_4 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( mem_out[3] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:3] in ;
+input [0:3] mem ;
+input [0:3] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 (
+ .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) ,
+ .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to4_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to4_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:3] data ;
+output [0:3] data_inv ;
+
+sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) ,
+ .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) ,
+ .Y ( data_inv[3] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:3] local_encoder2to4_0_data ;
+wire [0:3] local_encoder2to4_0_data_inv ;
+wire [0:3] local_encoder2to4_1_data ;
+wire [0:3] local_encoder2to4_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+
+sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) ,
+ .X ( aps_rename_505_ ) ) ;
+sb_1__0__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to4_0_data ) ,
+ .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+sb_1__0__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to4_1_data ) ,
+ .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_0 mux_l1_in_0_ (
+ .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_1 mux_l1_in_1_ (
+ .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] ,
+ mux_2level_tapbuf_basis_input4_mem4_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to4_1_data ) ,
+ .mem_inv ( local_encoder2to4_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) ,
+ .mem ( local_encoder2to4_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_198 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size8_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size8_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size8_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_73 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_72 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_71 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_54 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sb_1__0__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_71 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_72 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_73 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_196 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_196 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_70 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_69 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_68 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_67 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_53 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_52 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sb_1__0__local_encoder2to3_52 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_53 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_67 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_68 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_69 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_70 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_194 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_194 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_66 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_65 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_64 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_63 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_51 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_50 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+
+sb_1__0__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_51 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_63 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_64 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_65 mux_l1_in_2_ (
+ .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_66 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_192 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_192 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_190 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_33 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_189 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_188 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_188 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_186 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_186 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_184 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_184 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_182 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_182 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_180 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_180 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_178 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_178 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_176 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_62 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_61 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_49 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_48 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_49 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_61 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_60 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_59 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_47 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_46 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_47 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_59 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_58 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_57 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_45 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_44 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_45 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_57 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_56 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_55 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_43 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_42 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__0__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_43 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_55 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_174 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_54 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_53 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_41 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_40 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__0__local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_41 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_53 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_172 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_52 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_51 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_39 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_38 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__0__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_39 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_51 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_170 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_50 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_49 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_37 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_36 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__0__local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_37 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_49 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_50 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_15 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_169 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_48 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_47 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_35 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_34 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__0__local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_35 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_47 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_48 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_167 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_13 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_46 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_45 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_33 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_32 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__0__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_33 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_45 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_46 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_13 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_165 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_44 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_43 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_31 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__0__local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_31 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_43 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_44 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_163 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_29 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_41 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_42 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_1__0__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_27 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_39 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_161 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__0__local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_25 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_36 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_37 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_38 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_159 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__0__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_23 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_33 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_34 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_35 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_157 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__0__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_30 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_31 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_32 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_156 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_254 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1434 ( .A ( copt_net_225 ) ,
+ .X ( copt_net_220 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1435 ( .A ( copt_net_223 ) ,
+ .X ( copt_net_221 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1436 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_222 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1437 ( .A ( copt_net_222 ) ,
+ .X ( copt_net_223 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1438 ( .A ( copt_net_220 ) ,
+ .X ( copt_net_224 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1439 ( .A ( copt_net_221 ) ,
+ .X ( copt_net_225 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1461 ( .A ( copt_net_224 ) ,
+ .X ( ropt_net_248 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1462 ( .A ( ropt_net_248 ) ,
+ .X ( ropt_net_249 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1463 ( .A ( ropt_net_249 ) ,
+ .X ( ropt_net_250 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1464 ( .A ( ropt_net_250 ) ,
+ .X ( ropt_net_251 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1465 ( .A ( ropt_net_251 ) ,
+ .X ( ropt_net_252 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1466 ( .A ( ropt_net_252 ) ,
+ .X ( ropt_net_253 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1467 ( .A ( ropt_net_253 ) ,
+ .X ( ropt_net_254 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_27 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_28 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__0__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_24 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_25 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_26 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_154 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_21 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__0__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_19 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_152 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_15 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_151 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_151 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_13 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_1__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_149 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_149 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_1__0__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_1__0__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+sb_1__0__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ (
+ .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_147 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
+ top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
+ top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
+ top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ ,
+ right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ ,
+ right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ ,
+ right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ ,
+ right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in ,
+ left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
+ left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
+ left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
+ left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
+ left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
+ chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in ,
+ Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out ,
+ pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in ,
+ prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_left_grid_pin_50_ ;
+input [0:0] top_left_grid_pin_51_ ;
+input [0:29] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_3_ ;
+input [0:0] right_bottom_grid_pin_5_ ;
+input [0:0] right_bottom_grid_pin_7_ ;
+input [0:0] right_bottom_grid_pin_9_ ;
+input [0:0] right_bottom_grid_pin_11_ ;
+input [0:0] right_bottom_grid_pin_13_ ;
+input [0:0] right_bottom_grid_pin_15_ ;
+input [0:0] right_bottom_grid_pin_17_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_3_ ;
+input [0:0] left_bottom_grid_pin_5_ ;
+input [0:0] left_bottom_grid_pin_7_ ;
+input [0:0] left_bottom_grid_pin_9_ ;
+input [0:0] left_bottom_grid_pin_11_ ;
+input [0:0] left_bottom_grid_pin_13_ ;
+input [0:0] left_bottom_grid_pin_15_ ;
+input [0:0] left_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_right_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_TOP ;
+input Test_en_S_in ;
+output Test_en_N_out ;
+input pReset_S_in ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_N_out ;
+output pReset_W_out ;
+output pReset_E_out ;
+input Reset_S_in ;
+output Reset_N_out ;
+input prog_clk_0_N_in ;
+input prog_clk_3_S_in ;
+output prog_clk_3_N_out ;
+input clk_3_S_in ;
+output clk_3_N_out ;
+
+wire ropt_net_238 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_2level_tapbuf_size10_0_sram ;
+wire [0:0] mux_2level_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size2_0_sram ;
+wire [0:1] mux_2level_tapbuf_size2_10_sram ;
+wire [0:1] mux_2level_tapbuf_size2_1_sram ;
+wire [0:1] mux_2level_tapbuf_size2_2_sram ;
+wire [0:1] mux_2level_tapbuf_size2_3_sram ;
+wire [0:1] mux_2level_tapbuf_size2_4_sram ;
+wire [0:1] mux_2level_tapbuf_size2_5_sram ;
+wire [0:1] mux_2level_tapbuf_size2_6_sram ;
+wire [0:1] mux_2level_tapbuf_size2_7_sram ;
+wire [0:1] mux_2level_tapbuf_size2_8_sram ;
+wire [0:1] mux_2level_tapbuf_size2_9_sram ;
+wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size3_0_sram ;
+wire [0:1] mux_2level_tapbuf_size3_1_sram ;
+wire [0:1] mux_2level_tapbuf_size3_2_sram ;
+wire [0:1] mux_2level_tapbuf_size3_3_sram ;
+wire [0:1] mux_2level_tapbuf_size3_4_sram ;
+wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size4_0_sram ;
+wire [0:3] mux_2level_tapbuf_size4_1_sram ;
+wire [0:3] mux_2level_tapbuf_size4_2_sram ;
+wire [0:3] mux_2level_tapbuf_size4_3_sram ;
+wire [0:3] mux_2level_tapbuf_size4_4_sram ;
+wire [0:3] mux_2level_tapbuf_size4_5_sram ;
+wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size5_0_sram ;
+wire [0:3] mux_2level_tapbuf_size5_1_sram ;
+wire [0:3] mux_2level_tapbuf_size5_2_sram ;
+wire [0:3] mux_2level_tapbuf_size5_3_sram ;
+wire [0:3] mux_2level_tapbuf_size5_4_sram ;
+wire [0:3] mux_2level_tapbuf_size5_5_sram ;
+wire [0:0] mux_2level_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size6_0_sram ;
+wire [0:3] mux_2level_tapbuf_size6_1_sram ;
+wire [0:3] mux_2level_tapbuf_size6_2_sram ;
+wire [0:0] mux_2level_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size7_0_sram ;
+wire [0:3] mux_2level_tapbuf_size7_1_sram ;
+wire [0:3] mux_2level_tapbuf_size7_2_sram ;
+wire [0:3] mux_2level_tapbuf_size7_3_sram ;
+wire [0:3] mux_2level_tapbuf_size7_4_sram ;
+wire [0:3] mux_2level_tapbuf_size7_5_sram ;
+wire [0:3] mux_2level_tapbuf_size7_6_sram ;
+wire [0:3] mux_2level_tapbuf_size7_7_sram ;
+wire [0:3] mux_2level_tapbuf_size7_8_sram ;
+wire [0:3] mux_2level_tapbuf_size7_9_sram ;
+wire [0:0] mux_2level_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size7_mem_9_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size8_0_sram ;
+wire [0:3] mux_2level_tapbuf_size8_1_sram ;
+wire [0:3] mux_2level_tapbuf_size8_2_sram ;
+wire [0:0] mux_2level_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size9_0_sram ;
+wire [0:3] mux_2level_tapbuf_size9_1_sram ;
+wire [0:3] mux_2level_tapbuf_size9_2_sram ;
+wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail ;
+
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__0__mux_2level_tapbuf_size7_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] ,
+ chanx_left_in[0] , chanx_right_out[4] } ) ,
+ .sram ( mux_2level_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_1 mux_right_track_0 (
+ .in ( { chany_top_in[10] , chany_top_in[21] ,
+ right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] ,
+ right_bottom_grid_pin_13_[0] , chanx_right_out[4] ,
+ chanx_right_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_2 mux_right_track_12 (
+ .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] ,
+ right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] ,
+ chanx_right_out[12] , chanx_right_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_3 mux_right_track_20 (
+ .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] ,
+ right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] ,
+ chanx_right_out[13] , chanx_right_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_4 mux_right_track_28 (
+ .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] ,
+ chanx_right_out[15] , chanx_right_out[29] } ) ,
+ .sram ( mux_2level_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_5 mux_left_track_3 (
+ .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] ,
+ chanx_left_out[21] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_217 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_6 mux_left_track_5 (
+ .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] ,
+ chanx_left_out[23] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_217 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_7 mux_left_track_13 (
+ .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] ,
+ chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_212 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_8 mux_left_track_21 (
+ .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] ,
+ chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7 mux_left_track_29 (
+ .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] ,
+ chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size7_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_1 mem_right_track_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_1_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_2 mem_right_track_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_2_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_3 mem_right_track_20 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_3_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_4 mem_right_track_28 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_4_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_5_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_6_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_7 mem_left_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_7_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem_8 mem_left_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_8_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size7_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size7_9_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size6_0 mux_top_track_2 (
+ .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] ,
+ chanx_right_out[7] } ) ,
+ .sram ( mux_2level_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_219 ) ) ;
+sb_1__0__mux_2level_tapbuf_size6_1 mux_top_track_6 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] ,
+ chanx_right_out[9] } ) ,
+ .sram ( mux_2level_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__0__mux_2level_tapbuf_size6 mux_top_track_8 (
+ .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] ,
+ chanx_right_out[11] } ) ,
+ .sram ( mux_2level_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_219 ) ) ;
+sb_1__0__mux_2level_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_0 mux_top_track_4 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) ,
+ .sram ( mux_2level_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_1 mux_top_track_10 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) ,
+ .sram ( mux_2level_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_212 ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_2 mux_right_track_36 (
+ .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] ,
+ right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) ,
+ .sram ( mux_2level_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_3 mux_left_track_37 (
+ .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] ,
+ chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_212 ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_4 mux_left_track_45 (
+ .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] ,
+ chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_219 ) ) ;
+sb_1__0__mux_2level_tapbuf_size5 mux_left_track_53 (
+ .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] ,
+ chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size5_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_219 ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_1_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_mem_2 mem_right_track_36 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_2_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_mem_3 mem_left_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_3_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_mem_4 mem_left_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_4_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size5_5_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_0 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] ,
+ chanx_right_in[17] , chanx_right_out[13] } ) ,
+ .sram ( mux_2level_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
+ SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_216 ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_1 mux_top_track_14 (
+ .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] ,
+ chanx_right_out[15] } ) ,
+ .sram ( mux_2level_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
+ SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chany_top_out[7] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_2 mux_top_track_16 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] ,
+ chanx_right_in[25] , chanx_right_out[16] } ) ,
+ .sram ( mux_2level_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
+ SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_3 mux_top_track_18 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] ,
+ chanx_right_in[29] , chanx_right_out[17] } ) ,
+ .sram ( mux_2level_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
+ SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chany_top_out[9] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_4 mux_right_track_44 (
+ .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_2level_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
+ SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__0__mux_2level_tapbuf_size4 mux_right_track_52 (
+ .in ( { chany_top_in[9] , chany_top_in[20] ,
+ right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 ,
+ SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_213 ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_mem_4 mem_right_track_44 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_0 mux_top_track_20 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] ,
+ chanx_right_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_1 mux_top_track_22 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] ,
+ chanx_right_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chany_top_out[11] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_2 mux_top_track_24 (
+ .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] ,
+ chanx_right_out[21] } ) ,
+ .sram ( mux_2level_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_3 mux_top_track_26 (
+ .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] ,
+ chanx_right_out[23] } ) ,
+ .sram ( mux_2level_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chany_top_out[13] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size3 mux_top_track_36 (
+ .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] ,
+ chanx_right_out[29] } ) ,
+ .sram ( mux_2level_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_4_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_0 mux_top_track_28 (
+ .in ( { chanx_left_out[24] , chanx_right_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_1 mux_top_track_30 (
+ .in ( { chanx_left_out[25] , chanx_right_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
+ .out ( chany_top_out[15] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_2 mux_top_track_32 (
+ .in ( { chanx_left_out[27] , chanx_right_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chany_top_out[16] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_3 mux_top_track_34 (
+ .in ( { chanx_left_out[28] , chanx_right_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
+ .out ( chany_top_out[17] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_4 mux_top_track_40 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chany_top_out[20] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_5 mux_top_track_42 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
+ .out ( chany_top_out[21] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_6 mux_top_track_44 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_7 mux_top_track_46 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) ,
+ .sram ( mux_2level_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
+ .out ( chany_top_out[23] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_8 mux_top_track_48 (
+ .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) ,
+ .sram ( mux_2level_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chany_top_out[24] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_9 mux_top_track_50 (
+ .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) ,
+ .sram ( mux_2level_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
+ .out ( chany_top_out[25] ) , .p0 ( optlc_net_218 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2 mux_top_track_58 (
+ .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
+ .sram ( mux_2level_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
+ .out ( chany_top_out[29] ) , .p0 ( optlc_net_211 ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size8_0 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] ,
+ right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] ,
+ right_bottom_grid_pin_15_[0] , chanx_right_out[7] ,
+ chanx_right_out[21] } ) ,
+ .sram ( mux_2level_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 ,
+ SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_212 ) ) ;
+sb_1__0__mux_2level_tapbuf_size8_1 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] ,
+ right_bottom_grid_pin_17_[0] , chanx_right_out[8] ,
+ chanx_right_out[23] } ) ,
+ .sram ( mux_2level_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 ,
+ SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_215 ) ) ;
+sb_1__0__mux_2level_tapbuf_size8 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] ,
+ chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 ,
+ SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_212 ) ) ;
+sb_1__0__mux_2level_tapbuf_size8_mem_0 mem_right_track_2 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size8_mem_1 mem_right_track_4 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_1_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size8_2_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size10 mux_right_track_6 (
+ .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] ,
+ right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] ,
+ right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] ,
+ right_bottom_grid_pin_17_[0] , chanx_right_out[9] ,
+ chanx_right_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 ,
+ SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_215 ) ) ;
+sb_1__0__mux_2level_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size10_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size9_0 mux_right_track_10 (
+ .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] ,
+ right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] ,
+ right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] ,
+ chanx_right_out[11] , chanx_right_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 ,
+ SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
+ .out ( { aps_rename_506_ } ) ,
+ .p0 ( optlc_net_215 ) ) ;
+sb_1__0__mux_2level_tapbuf_size9_1 mux_left_track_7 (
+ .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] ,
+ chanx_left_out[24] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
+ left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 ,
+ SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_214 ) ) ;
+sb_1__0__mux_2level_tapbuf_size9 mux_left_track_11 (
+ .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] ,
+ chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
+ left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size9_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 ,
+ SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
+ .out ( { aps_rename_507_ } ) ,
+ .p0 ( optlc_net_217 ) ) ;
+sb_1__0__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_0_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_1_sram ) ) ;
+sb_1__0__mux_2level_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size9_2_sram ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_161 ) ,
+ .HI ( optlc_net_211 ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( net_net_204 ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_162 ) ,
+ .HI ( optlc_net_212 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) ,
+ .X ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) ,
+ .X ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( top_left_grid_pin_45_[0] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( chanx_left_in[2] ) ,
+ .X ( ropt_net_238 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chanx_left_in[4] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_left_in[5] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_145__144 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_146__145 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_200 ( .A ( BUF_net_201 ) ,
+ .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_201 ( .A ( Test_en_S_in ) , .Y ( BUF_net_201 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_202 ( .A ( BUF_net_203 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_203 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_203 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_204 ( .A ( net_net_204 ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( Reset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_206 ( .A ( Reset_S_in ) , .Y ( BUF_net_206 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) ,
+ .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_208 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_208 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_210 ( .A ( aps_rename_511_ ) ,
+ .Y ( BUF_net_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) ,
+ .HI ( optlc_net_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) ,
+ .HI ( optlc_net_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) ,
+ .HI ( optlc_net_215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) ,
+ .HI ( optlc_net_216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) ,
+ .HI ( optlc_net_217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) ,
+ .HI ( optlc_net_218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) ,
+ .HI ( optlc_net_219 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_230 ( .A ( aps_rename_507_ ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_231 ( .A ( aps_rename_506_ ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_232 ( .A ( aps_rename_509_ ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1452 ( .A ( ropt_net_238 ) ,
+ .X ( chany_top_out[28] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_58 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_57 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_56 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_55 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_54 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_54 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_45__44 ( .A ( copt_net_103 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_101 ) ,
+ .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_103 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_25 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_24 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_23 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_22 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_21 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_20 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_19 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_18 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_17 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_16 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_15 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_14 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_13 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_12 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_11 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_53 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_52 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_88 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_51 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_50 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_50 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_49 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_48 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_85 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_47 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_46 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_46 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_45 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_38 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_84 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_81 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_171 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_94 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_94 ) ,
+ .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_95 ) ,
+ .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_96 ) ,
+ .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_97 ) ,
+ .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_98 ) ,
+ .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( copt_net_99 ) ,
+ .X ( ropt_net_169 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_169 ) ,
+ .X ( ropt_net_170 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_170 ) ,
+ .X ( ropt_net_171 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__2__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__2__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_79 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__2__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__2__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_77 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_77 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__2__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__2__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__2__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__2__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_73 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ ,
+ right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
+ right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
+ bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out ,
+ ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out ,
+ prog_clk_0_E_in ) ;
+input [0:0] pReset ;
+input [0:29] chanx_right_in ;
+input [0:0] right_top_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:0] right_bottom_grid_pin_42_ ;
+input [0:0] right_bottom_grid_pin_43_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_1_ ;
+input [0:0] ccff_head ;
+output [0:29] chanx_right_out ;
+output [0:29] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input pReset_E_in ;
+output pReset_S_out ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_127 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_2level_tapbuf_size2_0_sram ;
+wire [0:1] mux_2level_tapbuf_size2_10_sram ;
+wire [0:1] mux_2level_tapbuf_size2_11_sram ;
+wire [0:1] mux_2level_tapbuf_size2_12_sram ;
+wire [0:1] mux_2level_tapbuf_size2_13_sram ;
+wire [0:1] mux_2level_tapbuf_size2_14_sram ;
+wire [0:1] mux_2level_tapbuf_size2_15_sram ;
+wire [0:1] mux_2level_tapbuf_size2_16_sram ;
+wire [0:1] mux_2level_tapbuf_size2_17_sram ;
+wire [0:1] mux_2level_tapbuf_size2_18_sram ;
+wire [0:1] mux_2level_tapbuf_size2_19_sram ;
+wire [0:1] mux_2level_tapbuf_size2_1_sram ;
+wire [0:1] mux_2level_tapbuf_size2_20_sram ;
+wire [0:1] mux_2level_tapbuf_size2_21_sram ;
+wire [0:1] mux_2level_tapbuf_size2_22_sram ;
+wire [0:1] mux_2level_tapbuf_size2_23_sram ;
+wire [0:1] mux_2level_tapbuf_size2_24_sram ;
+wire [0:1] mux_2level_tapbuf_size2_25_sram ;
+wire [0:1] mux_2level_tapbuf_size2_26_sram ;
+wire [0:1] mux_2level_tapbuf_size2_2_sram ;
+wire [0:1] mux_2level_tapbuf_size2_3_sram ;
+wire [0:1] mux_2level_tapbuf_size2_4_sram ;
+wire [0:1] mux_2level_tapbuf_size2_5_sram ;
+wire [0:1] mux_2level_tapbuf_size2_6_sram ;
+wire [0:1] mux_2level_tapbuf_size2_7_sram ;
+wire [0:1] mux_2level_tapbuf_size2_8_sram ;
+wire [0:1] mux_2level_tapbuf_size2_9_sram ;
+wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_23_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_24_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_25_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size3_0_sram ;
+wire [0:1] mux_2level_tapbuf_size3_1_sram ;
+wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size4_0_sram ;
+wire [0:3] mux_2level_tapbuf_size4_1_sram ;
+wire [0:3] mux_2level_tapbuf_size4_2_sram ;
+wire [0:3] mux_2level_tapbuf_size4_3_sram ;
+wire [0:3] mux_2level_tapbuf_size4_4_sram ;
+wire [0:3] mux_2level_tapbuf_size4_5_sram ;
+wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__2__mux_2level_tapbuf_size4_0 mux_right_track_0 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) ,
+ .sram ( mux_2level_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_1 mux_right_track_2 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) ,
+ .sram ( mux_2level_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_2 mux_right_track_4 (
+ .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) ,
+ .sram ( mux_2level_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_3 mux_right_track_6 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_4 mux_right_track_8 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) ,
+ .sram ( mux_2level_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_92 ) ) ;
+sb_0__2__mux_2level_tapbuf_size4 mux_right_track_10 (
+ .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) ,
+ .sram ( mux_2level_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_92 ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_mem_1 mem_right_track_2 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_mem_2 mem_right_track_4 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_mem_3 mem_right_track_6 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_mem_4 mem_right_track_8 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_0 mux_right_track_12 (
+ .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) ,
+ .sram ( mux_2level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_1 mux_right_track_14 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_2 mux_right_track_16 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) ,
+ .sram ( mux_2level_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_3 mux_right_track_18 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) ,
+ .sram ( mux_2level_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_4 mux_right_track_20 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) ,
+ .sram ( mux_2level_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_5 mux_right_track_22 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) ,
+ .sram ( mux_2level_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_6 mux_right_track_24 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
+ .sram ( mux_2level_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_7 mux_right_track_26 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) ,
+ .sram ( mux_2level_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_8 mux_right_track_30 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) ,
+ .sram ( mux_2level_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_9 mux_right_track_32 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) ,
+ .sram ( mux_2level_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_10 mux_right_track_34 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) ,
+ .sram ( mux_2level_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_11 mux_right_track_36 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) ,
+ .sram ( mux_2level_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_12 mux_right_track_38 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) ,
+ .sram ( mux_2level_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chanx_right_out[19] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_13 mux_right_track_40 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) ,
+ .sram ( mux_2level_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_right_out[20] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_14 mux_right_track_42 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) ,
+ .sram ( mux_2level_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chanx_right_out[21] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_15 mux_right_track_44 (
+ .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) ,
+ .sram ( mux_2level_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_16 mux_right_track_46 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) ,
+ .sram ( mux_2level_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chanx_right_out[23] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_17 mux_right_track_48 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) ,
+ .sram ( mux_2level_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chanx_right_out[24] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_18 mux_right_track_50 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
+ .sram ( mux_2level_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chanx_right_out[25] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_19 mux_right_track_54 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) ,
+ .sram ( mux_2level_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chanx_right_out[27] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_20 mux_right_track_56 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chanx_right_out[28] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_21 mux_right_track_58 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_right_out[29] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_22 mux_bottom_track_1 (
+ .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_23 mux_bottom_track_7 (
+ .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_92 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_24 mux_bottom_track_13 (
+ .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_24_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_25 mux_bottom_track_29 (
+ .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_25_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2 mux_bottom_track_45 (
+ .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_26_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_92 ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_0 mem_right_track_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_1 mem_right_track_14 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_2 mem_right_track_16 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_3 mem_right_track_18 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_4 mem_right_track_20 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_5 mem_right_track_22 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_6 mem_right_track_24 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_7 mem_right_track_26 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_8 mem_right_track_30 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_9 mem_right_track_32 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_10 mem_right_track_34 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_11 mem_right_track_36 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_11_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_12 mem_right_track_38 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_12_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_13 mem_right_track_40 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_13_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_14 mem_right_track_42 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_14_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_15 mem_right_track_44 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_15_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_16 mem_right_track_46 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_16_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_17 mem_right_track_48 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_17_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_18 mem_right_track_50 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_18_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_19 mem_right_track_54 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_19_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_20 mem_right_track_56 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_20_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_21 mem_right_track_58 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_21_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_22 mem_bottom_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_22_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_23 mem_bottom_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_23_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_24 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_24_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem_25 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_25_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size2_mem mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_26_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size3_0 mux_right_track_28 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[14] } ) ,
+ .sram ( mux_2level_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_2level_tapbuf_size3 mux_right_track_52 (
+ .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[2] } ) ,
+ .sram ( mux_2level_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_93 ) ) ;
+sb_0__2__mux_2level_tapbuf_size3_mem_0 mem_right_track_28 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+sb_0__2__mux_2level_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) ,
+ .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[0] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[1] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[2] ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[3] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[4] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[5] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[15] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[16] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( chanx_right_in[17] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[18] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[19] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[20] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[21] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( chanx_right_in[23] ) ,
+ .X ( ropt_net_127 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[24] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[26] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[27] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[29] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( pReset_E_in ) , .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) ,
+ .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) ,
+ .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1316 ( .A ( ropt_net_127 ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_114__113 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_113__112 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_112__111 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_111__110 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_109__108 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_108__107 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_107__106 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_204 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_204 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_202 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_200 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_38 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_27 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_198 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_198 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_196 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_195 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_13 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_194 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_194 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_192 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_192 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_190 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_190 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_70 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_62 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_62 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_70 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_208 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_208 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_69 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_68 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_61 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_60 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_60 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_61 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_68 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_69 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_188 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_188 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_67 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_66 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_59 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_58 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_58 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_59 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_66 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_186 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_186 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_65 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_64 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_57 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_56 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_57 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_64 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_184 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_184 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_63 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_62 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_55 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_54 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_55 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_62 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_182 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_182 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_61 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_60 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_53 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_52 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_52 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_53 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_60 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_61 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_180 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_180 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_59 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_58 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_51 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_50 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_51 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_58 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_59 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_178 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_178 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_57 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_56 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_49 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_48 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_49 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_56 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_57 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_176 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_55 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_54 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_47 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_46 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_47 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_54 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_55 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_174 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_53 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_52 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_45 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_44 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_45 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_52 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_53 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_172 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_51 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_50 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_43 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_42 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_43 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_50 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_170 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_49 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_48 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_41 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_40 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_41 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_48 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_49 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_168 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_47 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_46 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_39 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_38 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_39 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_46 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_47 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_1_ ( .in ( in[3:4] ) ,
+ .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_166 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_45 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_44 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_37 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_36 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_37 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_44 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_45 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_43 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_35 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_34 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_35 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_42 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_43 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_164 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_164 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_33 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_32 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_33 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_41 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_31 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_31 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_38 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_39 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_29 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_162 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_162 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_27 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_35 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_160 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_160 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_25 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_32 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_33 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_23 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_30 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_31 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_158 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_26 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_27 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:1] mem ;
+input [0:1] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) ,
+ .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_24 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem2_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_1_ (
+ .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_231 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1411 ( .A ( ropt_net_233 ) ,
+ .X ( copt_net_216 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1412 ( .A ( ropt_net_237 ) ,
+ .X ( copt_net_217 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1413 ( .A ( copt_net_217 ) ,
+ .X ( copt_net_218 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1414 ( .A ( copt_net_218 ) ,
+ .X ( copt_net_219 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1415 ( .A ( copt_net_219 ) ,
+ .X ( copt_net_220 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1416 ( .A ( ropt_net_235 ) ,
+ .X ( copt_net_221 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1424 ( .A ( copt_net_221 ) ,
+ .X ( ropt_net_229 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1425 ( .A ( ropt_net_229 ) ,
+ .X ( ropt_net_230 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1426 ( .A ( ropt_net_232 ) ,
+ .X ( ropt_net_231 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1427 ( .A ( ropt_net_230 ) ,
+ .X ( ropt_net_232 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1428 ( .A ( ropt_net_234 ) ,
+ .X ( ropt_net_233 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1429 ( .A ( ccff_head[0] ) ,
+ .X ( ropt_net_234 ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_h_inst_1430 ( .A ( copt_net_220 ) ,
+ .X ( ropt_net_235 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1431 ( .A ( copt_net_216 ) ,
+ .X ( ropt_net_236 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1432 ( .A ( ropt_net_236 ) ,
+ .X ( ropt_net_237 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_21 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_0__1__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_157 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_0__1__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_156 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sb_0__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_154 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__1__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_1_ (
+ .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+sb_0__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] ,
+ mux_2level_tapbuf_basis_input3_mem3_1_out[0] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ ,
+ chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
+ right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
+ bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out ,
+ chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out ,
+ prog_clk_0_E_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_1_ ;
+input [0:29] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:0] right_bottom_grid_pin_42_ ;
+input [0:0] right_bottom_grid_pin_43_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_1_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_right_out ;
+output [0:29] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input pReset_E_in ;
+output pReset_S_out ;
+input prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_2level_tapbuf_size2_0_sram ;
+wire [0:1] mux_2level_tapbuf_size2_1_sram ;
+wire [0:1] mux_2level_tapbuf_size2_2_sram ;
+wire [0:1] mux_2level_tapbuf_size2_3_sram ;
+wire [0:1] mux_2level_tapbuf_size2_4_sram ;
+wire [0:1] mux_2level_tapbuf_size2_5_sram ;
+wire [0:1] mux_2level_tapbuf_size2_6_sram ;
+wire [0:1] mux_2level_tapbuf_size2_7_sram ;
+wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size3_0_sram ;
+wire [0:1] mux_2level_tapbuf_size3_1_sram ;
+wire [0:1] mux_2level_tapbuf_size3_2_sram ;
+wire [0:1] mux_2level_tapbuf_size3_3_sram ;
+wire [0:1] mux_2level_tapbuf_size3_4_sram ;
+wire [0:1] mux_2level_tapbuf_size3_5_sram ;
+wire [0:1] mux_2level_tapbuf_size3_6_sram ;
+wire [0:1] mux_2level_tapbuf_size3_7_sram ;
+wire [0:1] mux_2level_tapbuf_size3_8_sram ;
+wire [0:1] mux_2level_tapbuf_size3_9_sram ;
+wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_8_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size4_0_sram ;
+wire [0:3] mux_2level_tapbuf_size4_10_sram ;
+wire [0:3] mux_2level_tapbuf_size4_11_sram ;
+wire [0:3] mux_2level_tapbuf_size4_1_sram ;
+wire [0:3] mux_2level_tapbuf_size4_2_sram ;
+wire [0:3] mux_2level_tapbuf_size4_3_sram ;
+wire [0:3] mux_2level_tapbuf_size4_4_sram ;
+wire [0:3] mux_2level_tapbuf_size4_5_sram ;
+wire [0:3] mux_2level_tapbuf_size4_6_sram ;
+wire [0:3] mux_2level_tapbuf_size4_7_sram ;
+wire [0:3] mux_2level_tapbuf_size4_8_sram ;
+wire [0:3] mux_2level_tapbuf_size4_9_sram ;
+wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_9_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size5_0_sram ;
+wire [0:3] mux_2level_tapbuf_size5_10_sram ;
+wire [0:3] mux_2level_tapbuf_size5_11_sram ;
+wire [0:3] mux_2level_tapbuf_size5_1_sram ;
+wire [0:3] mux_2level_tapbuf_size5_2_sram ;
+wire [0:3] mux_2level_tapbuf_size5_3_sram ;
+wire [0:3] mux_2level_tapbuf_size5_4_sram ;
+wire [0:3] mux_2level_tapbuf_size5_5_sram ;
+wire [0:3] mux_2level_tapbuf_size5_6_sram ;
+wire [0:3] mux_2level_tapbuf_size5_7_sram ;
+wire [0:3] mux_2level_tapbuf_size5_8_sram ;
+wire [0:3] mux_2level_tapbuf_size5_9_sram ;
+wire [0:0] mux_2level_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size5_mem_9_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size6_0_sram ;
+wire [0:3] mux_2level_tapbuf_size6_1_sram ;
+wire [0:3] mux_2level_tapbuf_size6_2_sram ;
+wire [0:3] mux_2level_tapbuf_size6_3_sram ;
+wire [0:3] mux_2level_tapbuf_size6_4_sram ;
+wire [0:3] mux_2level_tapbuf_size6_5_sram ;
+wire [0:3] mux_2level_tapbuf_size6_6_sram ;
+wire [0:3] mux_2level_tapbuf_size6_7_sram ;
+wire [0:0] mux_2level_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size6_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__1__mux_2level_tapbuf_size6_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] ,
+ chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_210 ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_1 mux_top_track_6 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] ,
+ chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_215 ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_2 mux_top_track_12 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] ,
+ chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_215 ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_3 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_bottom_out[7] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) ,
+ .sram ( mux_2level_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_213 ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_4 mux_right_track_6 (
+ .in ( { chany_top_in[2] , chany_bottom_out[9] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) ,
+ .sram ( mux_2level_tapbuf_size6_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_210 ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_5 mux_right_track_8 (
+ .in ( { chany_top_in[4] , chany_bottom_out[11] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) ,
+ .sram ( mux_2level_tapbuf_size6_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_215 ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_6 mux_bottom_track_7 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] ,
+ chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size6 mux_bottom_track_13 (
+ .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] ,
+ chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size6_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_mem_3 mem_right_track_2 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_3_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_mem_4 mem_right_track_6 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_4_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_mem_5 mem_right_track_8 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_5_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_mem_6 mem_bottom_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_6_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size6_mem mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size6_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size6_7_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_0 mux_top_track_2 (
+ .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] ,
+ chany_top_out[7] , chany_top_out[21] } ) ,
+ .sram ( mux_2level_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_213 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_1 mux_top_track_4 (
+ .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] ,
+ chany_top_out[8] , chany_top_out[23] } ) ,
+ .sram ( mux_2level_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_213 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_2 mux_top_track_10 (
+ .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] ,
+ chany_top_out[11] , chany_top_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_215 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_3 mux_top_track_20 (
+ .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] ,
+ chany_top_out[13] , chany_top_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_213 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_4 mux_right_track_0 (
+ .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] ,
+ right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_top_out[4] } ) ,
+ .sram ( mux_2level_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_210 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_5 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_bottom_out[8] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[8] } ) ,
+ .sram ( mux_2level_tapbuf_size5_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_210 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_6 mux_right_track_10 (
+ .in ( { chany_top_in[5] , chany_bottom_out[12] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[12] } ) ,
+ .sram ( mux_2level_tapbuf_size5_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_214 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_7 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] ,
+ chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size5_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_8 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] ,
+ chanx_right_in[18] , chanx_right_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size5_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_9 mux_bottom_track_11 (
+ .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] ,
+ chanx_right_in[16] , chanx_right_in[27] } ) ,
+ .sram ( mux_2level_tapbuf_size5_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_10 mux_bottom_track_21 (
+ .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] ,
+ chanx_right_in[14] , chanx_right_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size5_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_212 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5 mux_bottom_track_29 (
+ .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] ,
+ chanx_right_in[13] , chanx_right_in[24] } ) ,
+ .sram ( mux_2level_tapbuf_size5_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
+ SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_212 ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_0_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_1_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_2_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_3_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_4 mem_right_track_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_4_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_5 mem_right_track_4 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_5_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_6 mem_right_track_10 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_6_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_7 mem_bottom_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_7_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_8 mem_bottom_track_5 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_8_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_9 mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_9_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem_10 mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size6_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_10_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size5_mem mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size5_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size5_11_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_0 mux_top_track_28 (
+ .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] ,
+ chany_top_out[29] } ) ,
+ .sram ( mux_2level_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
+ SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_213 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_1 mux_top_track_52 (
+ .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] ,
+ chany_top_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
+ SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chany_top_out[26] ) , .p0 ( optlc_net_213 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_2 mux_right_track_12 (
+ .in ( { chany_top_in[9] , chany_bottom_out[13] ,
+ right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) ,
+ .sram ( mux_2level_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
+ SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_214 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_3 mux_right_track_14 (
+ .in ( { chany_top_in[13] , chany_bottom_out[15] ,
+ right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) ,
+ .sram ( mux_2level_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
+ SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_214 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_4 mux_right_track_16 (
+ .in ( { chany_bottom_out[16] , chany_top_in[17] ,
+ right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) ,
+ .sram ( mux_2level_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 ,
+ SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_210 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_5 mux_right_track_18 (
+ .in ( { chany_bottom_out[17] , chany_top_in[21] ,
+ right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) ,
+ .sram ( mux_2level_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
+ SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_210 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_6 mux_right_track_20 (
+ .in ( { chany_bottom_out[19] , chany_top_in[25] ,
+ right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) ,
+ .sram ( mux_2level_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 ,
+ SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_214 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_7 mux_right_track_22 (
+ .in ( { chany_bottom_out[20] , chany_top_in[29] ,
+ right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) ,
+ .sram ( mux_2level_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 ,
+ SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_213 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_8 mux_right_track_36 (
+ .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] ,
+ chany_top_out[29] , chany_bottom_in[29] } ) ,
+ .sram ( mux_2level_tapbuf_size4_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 ,
+ SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_9 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] ,
+ chanx_right_in[19] } ) ,
+ .sram ( mux_2level_tapbuf_size4_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 ,
+ SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_213 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_10 mux_bottom_track_37 (
+ .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] ,
+ chanx_right_in[23] } ) ,
+ .sram ( mux_2level_tapbuf_size4_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 ,
+ SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_212 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4 mux_bottom_track_45 (
+ .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] ,
+ chanx_right_in[22] } ) ,
+ .sram ( mux_2level_tapbuf_size4_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 ,
+ SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_2 mem_right_track_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_3 mem_right_track_14 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_4 mem_right_track_16 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_5 mem_right_track_18 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_6 mem_right_track_20 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_7 mem_right_track_22 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_8 mem_right_track_36 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_8_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_9 mem_bottom_track_3 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_9_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem_10 mem_bottom_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size5_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_10_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size4_mem mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_11_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_0 mux_top_track_36 (
+ .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) ,
+ .sram ( mux_2level_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_212 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_1 mux_top_track_44 (
+ .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) ,
+ .sram ( mux_2level_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_212 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_2 mux_right_track_24 (
+ .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] ,
+ chany_top_out[21] } ) ,
+ .sram ( mux_2level_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_212 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_3 mux_right_track_26 (
+ .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] ,
+ chany_top_out[23] } ) ,
+ .sram ( mux_2level_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_212 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_4 mux_right_track_28 (
+ .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] ,
+ chany_top_out[24] } ) ,
+ .sram ( mux_2level_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_5 mux_right_track_30 (
+ .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] ,
+ chany_top_out[25] } ) ,
+ .sram ( mux_2level_tapbuf_size3_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_6 mux_right_track_32 (
+ .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] ,
+ chany_top_out[27] } ) ,
+ .sram ( mux_2level_tapbuf_size3_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_7 mux_right_track_34 (
+ .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] ,
+ chany_top_out[28] } ) ,
+ .sram ( mux_2level_tapbuf_size3_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_211 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_8 mux_right_track_50 (
+ .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[4] } ) ,
+ .sram ( mux_2level_tapbuf_size3_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) ,
+ .out ( chanx_right_out[25] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3 mux_bottom_track_53 (
+ .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size3_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
+ .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_2 mem_right_track_24 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_3 mem_right_track_26 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_4 mem_right_track_28 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_4_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_5 mem_right_track_30 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_5_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_6 mem_right_track_32 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_6_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_7 mem_right_track_34 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_7_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem_8 mem_right_track_50 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_8_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size3_mem mem_bottom_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size3_9_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_0 mux_right_track_38 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) ,
+ .sram ( mux_2level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) ,
+ .out ( chanx_right_out[19] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_1 mux_right_track_40 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) ,
+ .sram ( mux_2level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
+ .out ( chanx_right_out[20] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_2 mux_right_track_44 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) ,
+ .sram ( mux_2level_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_3 mux_right_track_46 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) ,
+ .sram ( mux_2level_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
+ .out ( chanx_right_out[23] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_4 mux_right_track_48 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) ,
+ .sram ( mux_2level_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) ,
+ .out ( chanx_right_out[24] ) , .p0 ( optlc_net_212 ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_5 mux_right_track_52 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) ,
+ .sram ( mux_2level_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_6 mux_right_track_54 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) ,
+ .sram ( mux_2level_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) ,
+ .out ( chanx_right_out[27] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size2 mux_right_track_56 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) ,
+ .out ( chanx_right_out[28] ) , .p0 ( optlc_net_209 ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_mem_0 mem_right_track_38 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_mem_1 mem_right_track_40 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_mem_2 mem_right_track_44 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_mem_3 mem_right_track_46 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_mem_4 mem_right_track_48 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_mem_5 mem_right_track_52 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_mem_6 mem_right_track_54 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+sb_0__1__mux_2level_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) ,
+ .HI ( optlc_net_209 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_145__144 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_146__145 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_150__149 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_151__150 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_152__151 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_153__152 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_206 ( .A ( pReset_E_in ) , .Y ( BUF_net_206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) ,
+ .HI ( optlc_net_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) ,
+ .HI ( optlc_net_211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) ,
+ .HI ( optlc_net_212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) ,
+ .HI ( optlc_net_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) ,
+ .HI ( optlc_net_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) ,
+ .HI ( optlc_net_215 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_59 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_58 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_59 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_57 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_56 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_55 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_56 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_54 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_53 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_52 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ (
+ .in ( in[0:1] ) , .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_53 mux_l1_in_1_ (
+ .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__0__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__0__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__0__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__0__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__0__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+
+wire [0:0] out_inv ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 (
+ .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:2] local_encoder2to3_1_data ;
+wire [0:2] local_encoder2to3_1_data_inv ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+
+sb_0__0__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+sb_0__0__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) ,
+ .data ( local_encoder2to3_1_data ) ,
+ .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] ,
+ SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_1_data ) ,
+ .mem_inv ( local_encoder2to3_1_data_inv ) ,
+ .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_88 (
+ .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( copt_net_114 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_110 ) ,
+ .X ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_113 ) ,
+ .X ( copt_net_114 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_24 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_23 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_22 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_21 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_20 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_19 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_18 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_17 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_16 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_15 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_14 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_13 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_12 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_11 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_174 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_105 ) ,
+ .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_103 ) ,
+ .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_104 ) ,
+ .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_106 ) ,
+ .X ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_107 ) ,
+ .X ( copt_net_108 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( copt_net_108 ) ,
+ .X ( ropt_net_173 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_175 ) ,
+ .X ( ropt_net_174 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_173 ) ,
+ .X ( ropt_net_175 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_51 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_50 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_50 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_49 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_48 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_47 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_46 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_46 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_45 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_38 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_96 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_77 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_73 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv ,
+ out ) ;
+input [0:1] in ;
+input [0:0] mem ;
+input [0:0] mem_inv ;
+output [0:0] out ;
+
+sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) ,
+ .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
+wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in ) ,
+ .mem ( sram[0] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+sb_0__0__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ (
+ .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] ,
+ SYNOPSYS_UNCONNECTED_2 } ) ,
+ .mem ( sram[1] ) ,
+ .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_72 (
+ .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ ,
+ chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ ,
+ right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ ,
+ right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ ,
+ right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ ,
+ right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
+ ccff_tail , pReset_E_in , prog_clk_0_E_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_1_ ;
+input [0:29] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_3_ ;
+input [0:0] right_bottom_grid_pin_5_ ;
+input [0:0] right_bottom_grid_pin_7_ ;
+input [0:0] right_bottom_grid_pin_9_ ;
+input [0:0] right_bottom_grid_pin_11_ ;
+input [0:0] right_bottom_grid_pin_13_ ;
+input [0:0] right_bottom_grid_pin_15_ ;
+input [0:0] right_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_right_out ;
+output [0:0] ccff_tail ;
+input pReset_E_in ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_135 ;
+wire ropt_net_132 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_2level_tapbuf_size2_0_sram ;
+wire [0:1] mux_2level_tapbuf_size2_10_sram ;
+wire [0:1] mux_2level_tapbuf_size2_11_sram ;
+wire [0:1] mux_2level_tapbuf_size2_12_sram ;
+wire [0:1] mux_2level_tapbuf_size2_13_sram ;
+wire [0:1] mux_2level_tapbuf_size2_14_sram ;
+wire [0:1] mux_2level_tapbuf_size2_15_sram ;
+wire [0:1] mux_2level_tapbuf_size2_16_sram ;
+wire [0:1] mux_2level_tapbuf_size2_17_sram ;
+wire [0:1] mux_2level_tapbuf_size2_18_sram ;
+wire [0:1] mux_2level_tapbuf_size2_19_sram ;
+wire [0:1] mux_2level_tapbuf_size2_1_sram ;
+wire [0:1] mux_2level_tapbuf_size2_20_sram ;
+wire [0:1] mux_2level_tapbuf_size2_21_sram ;
+wire [0:1] mux_2level_tapbuf_size2_22_sram ;
+wire [0:1] mux_2level_tapbuf_size2_23_sram ;
+wire [0:1] mux_2level_tapbuf_size2_24_sram ;
+wire [0:1] mux_2level_tapbuf_size2_25_sram ;
+wire [0:1] mux_2level_tapbuf_size2_2_sram ;
+wire [0:1] mux_2level_tapbuf_size2_3_sram ;
+wire [0:1] mux_2level_tapbuf_size2_4_sram ;
+wire [0:1] mux_2level_tapbuf_size2_5_sram ;
+wire [0:1] mux_2level_tapbuf_size2_6_sram ;
+wire [0:1] mux_2level_tapbuf_size2_7_sram ;
+wire [0:1] mux_2level_tapbuf_size2_8_sram ;
+wire [0:1] mux_2level_tapbuf_size2_9_sram ;
+wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_23_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_24_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_2level_tapbuf_size3_0_sram ;
+wire [0:1] mux_2level_tapbuf_size3_1_sram ;
+wire [0:1] mux_2level_tapbuf_size3_2_sram ;
+wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:3] mux_2level_tapbuf_size4_0_sram ;
+wire [0:3] mux_2level_tapbuf_size4_1_sram ;
+wire [0:3] mux_2level_tapbuf_size4_2_sram ;
+wire [0:3] mux_2level_tapbuf_size4_3_sram ;
+wire [0:3] mux_2level_tapbuf_size4_4_sram ;
+wire [0:3] mux_2level_tapbuf_size4_5_sram ;
+wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__0__mux_2level_tapbuf_size2_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
+ .sram ( mux_2level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_1 mux_top_track_6 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) ,
+ .sram ( mux_2level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_2 mux_top_track_12 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) ,
+ .sram ( mux_2level_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_100 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_3 mux_top_track_28 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) ,
+ .sram ( mux_2level_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_99 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_4 mux_top_track_44 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) ,
+ .sram ( mux_2level_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_5 mux_right_track_14 (
+ .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_6 mux_right_track_16 (
+ .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_7 mux_right_track_18 (
+ .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_8 mux_right_track_20 (
+ .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_100 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_9 mux_right_track_22 (
+ .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_99 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_10 mux_right_track_24 (
+ .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_11 mux_right_track_26 (
+ .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_12 mux_right_track_30 (
+ .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_13 mux_right_track_32 (
+ .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_14 mux_right_track_34 (
+ .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_99 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_15 mux_right_track_36 (
+ .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_99 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_16 mux_right_track_38 (
+ .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chanx_right_out[19] ) , .p0 ( optlc_net_99 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_17 mux_right_track_40 (
+ .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_right_out[20] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_18 mux_right_track_42 (
+ .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chanx_right_out[21] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_19 mux_right_track_46 (
+ .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_right_out[23] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_20 mux_right_track_48 (
+ .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_right_out[24] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_21 mux_right_track_50 (
+ .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_right_out[25] ) , .p0 ( optlc_net_100 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_22 mux_right_track_52 (
+ .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_99 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_23 mux_right_track_54 (
+ .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_right_out[27] ) , .p0 ( optlc_net_99 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_24 mux_right_track_56 (
+ .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_24_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chanx_right_out[28] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2 mux_right_track_58 (
+ .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size2_25_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_right_out[29] ) , .p0 ( optlc_net_101 ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_5 mem_right_track_14 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_6 mem_right_track_16 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_7 mem_right_track_18 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_8 mem_right_track_20 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_9 mem_right_track_22 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_10 mem_right_track_24 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_11 mem_right_track_26 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_11_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_12 mem_right_track_30 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_12_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_13 mem_right_track_32 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_13_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_14 mem_right_track_34 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_14_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_15 mem_right_track_36 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_15_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_16 mem_right_track_38 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_16_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_17 mem_right_track_40 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_17_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_18 mem_right_track_42 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_18_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_19 mem_right_track_46 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_19_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_20 mem_right_track_48 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_20_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_21 mem_right_track_50 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_21_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_22 mem_right_track_52 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_22_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_23 mem_right_track_54 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_23_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem_24 mem_right_track_56 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size2_24_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_25_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_0 mux_right_track_0 (
+ .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_1 mux_right_track_2 (
+ .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] ,
+ right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_98 ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_2 mux_right_track_4 (
+ .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] ,
+ right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_101 ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_3 mux_right_track_6 (
+ .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_101 ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_4 mux_right_track_8 (
+ .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] ,
+ right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ;
+sb_0__0__mux_2level_tapbuf_size4 mux_right_track_10 (
+ .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] ,
+ right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_mem_1 mem_right_track_2 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_mem_2 mem_right_track_4 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_mem_3 mem_right_track_6 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_mem_4 mem_right_track_8 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size3_0 mux_right_track_12 (
+ .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size3_1 mux_right_track_28 (
+ .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_101 ) ) ;
+sb_0__0__mux_2level_tapbuf_size3 mux_right_track_44 (
+ .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_2level_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_102 ) ) ;
+sb_0__0__mux_2level_tapbuf_size3_mem_0 mem_right_track_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size3_mem_1 mem_right_track_28 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+sb_0__0__mux_2level_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[0] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_51__50 ( .A ( chanx_right_in[5] ) ,
+ .X ( ropt_net_135 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[6] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_right_in[9] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[10] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[11] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[12] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chanx_right_in[13] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[16] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[17] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[21] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[22] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( chanx_right_in[25] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( chanx_right_in[26] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[27] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[28] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( chanx_right_in[29] ) ,
+ .X ( ropt_net_132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) ,
+ .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) ,
+ .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) ,
+ .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) ,
+ .HI ( optlc_net_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) ,
+ .HI ( optlc_net_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) ,
+ .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1323 ( .A ( ropt_net_132 ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1326 ( .A ( ropt_net_135 ) ,
+ .X ( chany_top_out[4] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_245 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1727 ( .A ( copt_net_247 ) ,
+ .X ( copt_net_243 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1728 ( .A ( copt_net_243 ) ,
+ .X ( copt_net_244 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1729 ( .A ( copt_net_244 ) ,
+ .X ( copt_net_245 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1730 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_246 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1731 ( .A ( copt_net_246 ) ,
+ .X ( copt_net_247 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_30 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3 ( in , mem , mem_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_109__108 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_30 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_46 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_108__107 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_30 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_30 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_107__106 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_14 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_106__105 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_45 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2 ( in , sram , sram_inv , out ,
+ p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_45 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_176 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_177 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_44 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_14 ( in , sram , sram_inv , out ,
+ p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_173 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_174 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 ,
+ p_abuf2 ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+output p_abuf0 ;
+output p_abuf1 ;
+output p_abuf2 ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( p_abuf2 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( BUF_net_132 ) , .Y ( ff_Q[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf1 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( p_abuf2 ) , .Y ( BUF_net_132 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_29 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_28 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[1] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_29 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_43 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_29 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_43 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_29 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_28 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_42 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_28 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) ,
+ .X ( net_net_179 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_179 ( .A ( net_net_179 ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p0 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_1level_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_1level_size2_28 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_size2_29 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_size2_mem_28 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_29 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf1 ,
+ p_abuf3 , p_abuf4 , p0 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf1 ;
+output p_abuf3 ;
+output p_abuf4 ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:0] mux_1level_size2_0_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+wire [0:1] mux_1level_tapbuf_size2_0_sram ;
+wire [0:1] mux_1level_tapbuf_size2_1_sram ;
+wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q ) ,
+ .ff_clk ( fabric_clk ) , .p_abuf0 ( fabric_sc_out[0] ) ,
+ .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_14 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_tapbuf_size2 mux_fabric_out_1 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf4 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_14 mem_fabric_out_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf2 ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+grid_clb_mux_1level_size2_30 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_size2 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_size2_mem_30 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+output p_abuf2 ;
+input p0 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf1 ( p_abuf0 ) , .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) ,
+ .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_27 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_26 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_27 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_41 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_27 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_41 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_27 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_26 ( in , mem , mem_inv , out ,
+ p3 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p3 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_40 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_26 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_26 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_13 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_12 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv ,
+ out , p3 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p3 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_39 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_13 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_8 sky130_fd_sc_hd__inv_4_0_ (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_39 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_13 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv ,
+ out , p3 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p3 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_38 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_12 ( in , sram , sram_inv , out ,
+ p_abuf0 , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p3 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_169 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_170 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_25 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_24 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_25 ( in , mem , mem_inv , out ,
+ p3 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p3 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_37 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_25 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_37 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_25 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_24 ( in , mem , mem_inv , out ,
+ p3 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p3 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_36 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_24 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_24 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p3 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_1level_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_1level_size2_24 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ;
+grid_clb_mux_1level_size2_25 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p3 ( p3 ) ) ;
+grid_clb_mux_1level_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_25 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , p0 ,
+ p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+input p0 ;
+input p3 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:0] mux_1level_size2_0_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+wire [0:1] mux_1level_tapbuf_size2_0_sram ;
+wire [0:1] mux_1level_tapbuf_size2_1_sram ;
+wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p3 ( p3 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_1level_tapbuf_size2_12 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_13 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p3 ( p3 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_12 mem_fabric_out_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_13 mem_fabric_out_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+grid_clb_mux_1level_size2_26 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_1level_size2_0_out ) , .p3 ( p3 ) ) ;
+grid_clb_mux_1level_size2_27 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_size2_mem_26 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_27 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p0 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+input p0 ;
+input p3 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_23 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_22 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_23 ( in , mem , mem_inv , out ,
+ p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_35 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_23 ( in , sram , sram_inv , out , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_35 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_23 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_22 ( in , mem , mem_inv , out ,
+ p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_34 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_22 ( in , sram , sram_inv , out , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_22 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_11 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv ,
+ out , p3 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p3 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_33 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_11 ( in , sram , sram_inv , out ,
+ p_abuf0 , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p3 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_33 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_166 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_167 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv ,
+ out , p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_32 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_10 ( in , sram , sram_inv , out ,
+ p_abuf0 , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_163 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_21 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_20 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_21 ( in , mem , mem_inv , out ,
+ p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_31 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_21 ( in , sram , sram_inv , out , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_31 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_21 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_20 ( in , mem , mem_inv , out ,
+ p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_30 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_20 ( in , sram , sram_inv , out , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_20 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p6 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p6 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_1level_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_1level_size2_20 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_size2_21 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_size2_mem_20 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_21 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p3 , p6 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p3 ;
+input p6 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:0] mux_1level_size2_0_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+wire [0:1] mux_1level_tapbuf_size2_0_sram ;
+wire [0:1] mux_1level_tapbuf_size2_1_sram ;
+wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p6 ( p6 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_1level_tapbuf_size2_10 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_11 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_10 mem_fabric_out_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_11 mem_fabric_out_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+grid_clb_mux_1level_size2_22 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_1level_size2_0_out ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_size2_23 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_size2_mem_22 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_23 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p3 , p6 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p3 ;
+input p6 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_19 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_18 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_19 ( in , mem , mem_inv , out ,
+ p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_29 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_19 ( in , sram , sram_inv , out , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_29 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_19 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_18 ( in , mem , mem_inv , out ,
+ p4 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p4 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_28 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_18 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_18 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_9 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_8 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv ,
+ out , p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_27 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_9 ( in , sram , sram_inv , out ,
+ p_abuf0 , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_27 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_161 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv ,
+ out , p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_26 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_8 ( in , sram , sram_inv , out ,
+ p_abuf0 , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_157 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_17 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_16 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_17 ( in , mem , mem_inv , out ,
+ p4 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p4 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_25 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_17 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_25 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_17 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_16 ( in , mem , mem_inv , out ,
+ p4 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p4 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_24 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_16 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_16 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p4 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_1level_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_1level_size2_16 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ;
+grid_clb_mux_1level_size2_17 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p4 ( p4 ) ) ;
+grid_clb_mux_1level_size2_mem_16 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_17 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p4 , p6 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p4 ;
+input p6 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:0] mux_1level_size2_0_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+wire [0:1] mux_1level_tapbuf_size2_0_sram ;
+wire [0:1] mux_1level_tapbuf_size2_1_sram ;
+wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p4 ( p4 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_1level_tapbuf_size2_8 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_9 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_9 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+grid_clb_mux_1level_size2_18 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_1level_size2_0_out ) , .p4 ( p4 ) ) ;
+grid_clb_mux_1level_size2_19 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_size2_mem_18 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_19 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p4 , p6 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p4 ;
+input p6 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p4 ( p4 ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_15 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_14 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_15 ( in , mem , mem_inv , out ,
+ p6 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p6 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_23 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_15 ( in , sram , sram_inv , out , p6 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p6 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_23 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_15 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_14 ( in , mem , mem_inv , out ,
+ p2 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p2 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_22 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_14 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_14 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv ,
+ out , p2 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p2 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_21 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_7 ( in , sram , sram_inv , out ,
+ p_abuf0 , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_21 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_154 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_155 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv ,
+ out , p2 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p2 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_20 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_6 ( in , sram , sram_inv , out ,
+ p_abuf0 , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_151 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_13 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_12 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_13 ( in , mem , mem_inv , out ,
+ p2 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p2 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_19 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_13 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_19 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_13 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_12 ( in , mem , mem_inv , out ,
+ p2 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p2 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_18 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_12 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_12 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p2 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_1level_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_1level_size2_12 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ;
+grid_clb_mux_1level_size2_13 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_1level_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_13 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p2 , p6 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p2 ;
+input p6 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:0] mux_1level_size2_0_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+wire [0:1] mux_1level_tapbuf_size2_0_sram ;
+wire [0:1] mux_1level_tapbuf_size2_1_sram ;
+wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p2 ( p2 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_1level_tapbuf_size2_6 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_7 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_6 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_7 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+grid_clb_mux_1level_size2_14 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_1level_size2_0_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_1level_size2_15 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ;
+grid_clb_mux_1level_size2_mem_14 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_15 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p2 , p6 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p2 ;
+input p6 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , .p6 ( p6 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_11 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_11 ( in , mem , mem_inv , out ,
+ p2 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p2 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_17 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_11 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_17 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_11 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_10 ( in , mem , mem_inv , out ,
+ p5 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p5 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_16 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_10 ( in , sram , sram_inv , out , p5 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p5 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_10 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv ,
+ out , p2 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p2 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_15 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_5 ( in , sram , sram_inv , out ,
+ p_abuf0 , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_15 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_148 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_149 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv ,
+ out , p5 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p5 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_14 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_4 ( in , sram , sram_inv , out ,
+ p_abuf0 , p5 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p5 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_145 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_146 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_9 ( in , mem , mem_inv , out ,
+ p5 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p5 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_13 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_9 ( in , sram , sram_inv , out , p5 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p5 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_13 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_9 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_8 ( in , mem , mem_inv , out ,
+ p2 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p2 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_12 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_8 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_8 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p2 , p5 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p2 ;
+input p5 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_1level_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_1level_size2_8 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ;
+grid_clb_mux_1level_size2_9 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ;
+grid_clb_mux_1level_size2_mem_8 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_9 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p2 , p5 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p2 ;
+input p5 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:0] mux_1level_size2_0_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+wire [0:1] mux_1level_tapbuf_size2_0_sram ;
+wire [0:1] mux_1level_tapbuf_size2_1_sram ;
+wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p2 ( p2 ) , .p5 ( p5 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_1level_tapbuf_size2_4 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p5 ( p5 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_5 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_4 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_5 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+grid_clb_mux_1level_size2_10 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_1level_size2_0_out ) , .p5 ( p5 ) ) ;
+grid_clb_mux_1level_size2_11 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_1level_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_11 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p2 , p5 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p2 ;
+input p5 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , .p5 ( p5 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_7 ( in , mem , mem_inv , out ,
+ p5 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p5 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_11 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_7 ( in , sram , sram_inv , out , p5 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p5 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_11 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_7 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_6 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_10 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_6 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_9 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_3 ( in , sram , sram_inv , out ,
+ p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_9 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_142 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_143 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_8 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_2 ( in , sram , sram_inv , out ,
+ p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_139 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_140 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_5 ( in , mem , mem_inv , out ,
+ p1 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p1 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p1 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_7 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_5 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_7 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_5 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_4 ( in , mem , mem_inv , out ,
+ p1 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p1 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p1 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_6 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_4 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_4 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p1 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p1 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_1level_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_1level_size2_4 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ;
+grid_clb_mux_1level_size2_5 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p1 ( p1 ) ) ;
+grid_clb_mux_1level_size2_mem_4 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_5 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p0 , p1 , p5 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p1 ;
+input p5 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:0] mux_1level_size2_0_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+wire [0:1] mux_1level_tapbuf_size2_0_sram ;
+wire [0:1] mux_1level_tapbuf_size2_1_sram ;
+wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p1 ( p1 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_1level_tapbuf_size2_2 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_3 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_3 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+grid_clb_mux_1level_size2_6 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_size2_7 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ;
+grid_clb_mux_1level_size2_mem_6 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_7 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p5 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p1 ;
+input p5 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) ,
+ .p5 ( p5 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_3 ( in , mem , mem_inv , out ,
+ p4 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p4 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_5 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_3 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_5 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_3 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_2 ( in , mem , mem_inv , out ,
+ p4 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p4 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_4 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_2 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_2 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv ,
+ out , p4 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p4 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_3 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_1 ( in , sram , sram_inv , out ,
+ p_abuf0 , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p4 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_3 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_1 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_136 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_137 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv ,
+ out , p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_2 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_0 ( in , sram , sram_inv , out ,
+ p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+
+grid_clb_local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_133 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_134 (
+ .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_1 ( in , mem , mem_inv , out ,
+ p0 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p0 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_1 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_1 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_1 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_0 ( in , mem , mem_inv , out ,
+ p4 ) ;
+input [0:2] in ;
+input [0:2] mem ;
+input [0:2] mem_inv ;
+output [0:0] out ;
+input p4 ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 (
+ .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) ,
+ .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) ,
+ .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_0 ( addr , data , data_inv ) ;
+input [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) ,
+ .Y ( data_inv[1] ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) ,
+ .Y ( data[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_0 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
+ .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+grid_clb_local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram ) ,
+ .data ( local_encoder2to3_0_data ) ,
+ .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_0 mux_l1_in_0_ (
+ .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+ .mem ( local_encoder2to3_0_data ) ,
+ .mem_inv ( local_encoder2to3_0_data_inv ) ,
+ .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_248 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1720 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_236 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1721 ( .A ( copt_net_236 ) ,
+ .X ( copt_net_237 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1722 ( .A ( copt_net_237 ) ,
+ .X ( copt_net_238 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1723 ( .A ( copt_net_241 ) ,
+ .X ( copt_net_239 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1724 ( .A ( copt_net_239 ) ,
+ .X ( copt_net_240 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1725 ( .A ( copt_net_238 ) ,
+ .X ( copt_net_241 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1732 ( .A ( copt_net_240 ) ,
+ .X ( ropt_net_248 ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p0 , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p0 ;
+input p4 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_1level_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_1level_size2_0 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ;
+grid_clb_mux_1level_size2_1 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_1 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p0 , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p4 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:0] mux_1level_size2_0_out ;
+wire [0:1] mux_1level_size2_0_sram ;
+wire [0:0] mux_1level_size2_1_out ;
+wire [0:1] mux_1level_size2_1_sram ;
+wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+wire [0:1] mux_1level_tapbuf_size2_0_sram ;
+wire [0:1] mux_1level_tapbuf_size2_1_sram ;
+wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) , .p4 ( p4 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_1level_tapbuf_size2_0 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_1 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_1level_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p4 ( p4 ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_0 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+grid_clb_mux_1level_tapbuf_size2_mem_1 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+grid_clb_mux_1level_size2_2 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_1level_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_1level_size2_0_out ) , .p4 ( p4 ) ) ;
+grid_clb_mux_1level_size2_3 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_1level_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_1level_size2_1_out ) , .p4 ( p4 ) ) ;
+grid_clb_mux_1level_size2_mem_2 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_1level_size2_0_sram ) ) ;
+grid_clb_mux_1level_size2_mem_3 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p4 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_clb_ ( pReset , prog_clk , Test_en ,
+ clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 ,
+ clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i ,
+ clb_I7 , clb_I7i , clb_reg_in , clb_sc_in , clb_cin , clb_reset ,
+ clb_clk , ccff_head , clb_O , clb_reg_out , clb_sc_out , clb_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 ,
+ p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 ,
+ p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 , p4 , p5 , p6 , p7 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:1] clb_I0 ;
+input [0:1] clb_I0i ;
+input [0:1] clb_I1 ;
+input [0:1] clb_I1i ;
+input [0:1] clb_I2 ;
+input [0:1] clb_I2i ;
+input [0:1] clb_I3 ;
+input [0:1] clb_I3i ;
+input [0:1] clb_I4 ;
+input [0:1] clb_I4i ;
+input [0:1] clb_I5 ;
+input [0:1] clb_I5i ;
+input [0:1] clb_I6 ;
+input [0:1] clb_I6i ;
+input [0:1] clb_I7 ;
+input [0:1] clb_I7i ;
+input [0:0] clb_reg_in ;
+input [0:0] clb_sc_in ;
+input [0:0] clb_cin ;
+input [0:0] clb_reset ;
+input [0:0] clb_clk ;
+input [0:0] ccff_head ;
+output [0:15] clb_O ;
+output [0:0] clb_reg_out ;
+output [0:0] clb_sc_out ;
+output [0:0] clb_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+output p_abuf2 ;
+output p_abuf3 ;
+output p_abuf4 ;
+output p_abuf5 ;
+output p_abuf6 ;
+output p_abuf7 ;
+output p_abuf8 ;
+output p_abuf9 ;
+output p_abuf10 ;
+output p_abuf11 ;
+output p_abuf12 ;
+output p_abuf13 ;
+output p_abuf14 ;
+output p_abuf15 ;
+input p0 ;
+input p1 ;
+input p2 ;
+input p3 ;
+input p4 ;
+input p5 ;
+input p6 ;
+input p7 ;
+
+wire [0:0] direct_interc_32_out ;
+wire [0:0] direct_interc_34_out ;
+wire [0:0] direct_interc_41_out ;
+wire [0:0] direct_interc_43_out ;
+wire [0:0] direct_interc_50_out ;
+wire [0:0] direct_interc_52_out ;
+wire [0:0] direct_interc_59_out ;
+wire [0:0] direct_interc_61_out ;
+wire [0:0] direct_interc_68_out ;
+wire [0:0] direct_interc_70_out ;
+wire [0:0] direct_interc_77_out ;
+wire [0:0] direct_interc_79_out ;
+wire [0:0] direct_interc_86_out ;
+wire [0:0] direct_interc_88_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ;
+
+grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) ,
+ .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) ,
+ .fle_cin ( clb_cin ) , .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) ,
+ .ccff_head ( ccff_head ) ,
+ .fle_out ( { clb_O[1] , clb_O[0] } ) ,
+ .fle_reg_out ( direct_interc_32_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ,
+ .fle_cout ( direct_interc_34_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) ,
+ .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p0 ( p0 ) , .p4 ( p5 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) ,
+ .fle_reg_in ( direct_interc_32_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ,
+ .fle_cin ( direct_interc_34_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) ,
+ .fle_out ( { clb_O[3] , clb_O[2] } ) ,
+ .fle_reg_out ( direct_interc_41_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ,
+ .fle_cout ( direct_interc_43_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) ,
+ .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) ,
+ .p5 ( p6 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) ,
+ .fle_reg_in ( direct_interc_41_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ,
+ .fle_cin ( direct_interc_43_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) ,
+ .fle_out ( { clb_O[5] , clb_O[4] } ) ,
+ .fle_reg_out ( direct_interc_50_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ,
+ .fle_cout ( direct_interc_52_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) ,
+ .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p2 ( p3 ) , .p5 ( p6 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) ,
+ .fle_reg_in ( direct_interc_50_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ,
+ .fle_cin ( direct_interc_52_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) ,
+ .fle_out ( { clb_O[7] , clb_O[6] } ) ,
+ .fle_reg_out ( direct_interc_59_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ,
+ .fle_cout ( direct_interc_61_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) ,
+ .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) , .p6 ( p7 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) ,
+ .fle_reg_in ( direct_interc_59_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ,
+ .fle_cin ( direct_interc_61_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) ,
+ .fle_out ( { clb_O[9] , clb_O[8] } ) ,
+ .fle_reg_out ( direct_interc_68_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ,
+ .fle_cout ( direct_interc_70_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) ,
+ .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p4 ( p5 ) , .p6 ( p7 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) ,
+ .fle_reg_in ( direct_interc_68_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ,
+ .fle_cin ( direct_interc_70_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) ,
+ .fle_out ( { clb_O[11] , clb_O[10] } ) ,
+ .fle_reg_out ( direct_interc_77_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ,
+ .fle_cout ( direct_interc_79_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) ,
+ .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) , .p6 ( p7 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) ,
+ .fle_reg_in ( direct_interc_77_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ,
+ .fle_cin ( direct_interc_79_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) ,
+ .fle_out ( { clb_O[13] , clb_O[12] } ) ,
+ .fle_reg_out ( direct_interc_86_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ,
+ .fle_cout ( direct_interc_88_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) ,
+ .p_abuf0 ( p_abuf13 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) ,
+ .fle_reg_in ( direct_interc_86_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ,
+ .fle_cin ( direct_interc_88_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) ,
+ .fle_out ( { clb_O[15] , clb_O[14] } ) ,
+ .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) ,
+ .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ,
+ .p_abuf1 ( p_abuf14 ) , .p_abuf2 ( p_abuf15 ) , .p0 ( p1 ) ) ;
+endmodule
+
+
+module grid_clb ( pReset , top_width_0_height_0__pin_0_ ,
+ top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ ,
+ top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ ,
+ top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ ,
+ top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ ,
+ top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ ,
+ top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ ,
+ top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ ,
+ top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ ,
+ top_width_0_height_0__pin_33_ , top_width_0_height_0__pin_34_ ,
+ right_width_0_height_0__pin_16_ , right_width_0_height_0__pin_17_ ,
+ right_width_0_height_0__pin_18_ , right_width_0_height_0__pin_19_ ,
+ right_width_0_height_0__pin_20_ , right_width_0_height_0__pin_21_ ,
+ right_width_0_height_0__pin_22_ , right_width_0_height_0__pin_23_ ,
+ right_width_0_height_0__pin_24_ , right_width_0_height_0__pin_25_ ,
+ right_width_0_height_0__pin_26_ , right_width_0_height_0__pin_27_ ,
+ right_width_0_height_0__pin_28_ , right_width_0_height_0__pin_29_ ,
+ right_width_0_height_0__pin_30_ , right_width_0_height_0__pin_31_ ,
+ Reset , ccff_head , top_width_0_height_0__pin_36_upper ,
+ top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper ,
+ top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper ,
+ top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper ,
+ top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper ,
+ top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper ,
+ top_width_0_height_0__pin_41_lower , top_width_0_height_0__pin_42_upper ,
+ top_width_0_height_0__pin_42_lower , top_width_0_height_0__pin_43_upper ,
+ top_width_0_height_0__pin_43_lower ,
+ right_width_0_height_0__pin_44_upper ,
+ right_width_0_height_0__pin_44_lower ,
+ right_width_0_height_0__pin_45_upper ,
+ right_width_0_height_0__pin_45_lower ,
+ right_width_0_height_0__pin_46_upper ,
+ right_width_0_height_0__pin_46_lower ,
+ right_width_0_height_0__pin_47_upper ,
+ right_width_0_height_0__pin_47_lower ,
+ right_width_0_height_0__pin_48_upper ,
+ right_width_0_height_0__pin_48_lower ,
+ right_width_0_height_0__pin_49_upper ,
+ right_width_0_height_0__pin_49_lower ,
+ right_width_0_height_0__pin_50_upper ,
+ right_width_0_height_0__pin_50_lower ,
+ right_width_0_height_0__pin_51_upper ,
+ right_width_0_height_0__pin_51_lower , bottom_width_0_height_0__pin_52_ ,
+ bottom_width_0_height_0__pin_53_ , bottom_width_0_height_0__pin_54_ ,
+ ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ,
+ Test_en_E_in , Test_en_W_in , Test_en_W_out , Test_en_E_out ,
+ pReset_N_in , Reset_E_in , Reset_W_in , Reset_W_out , Reset_E_out ,
+ prog_clk_0_N_in , prog_clk_0_S_in , prog_clk_0_S_out , prog_clk_0_E_out ,
+ prog_clk_0_W_out , prog_clk_0_N_out , clk_0_N_in , clk_0_S_in ) ;
+input [0:0] pReset ;
+input [0:0] top_width_0_height_0__pin_0_ ;
+input [0:0] top_width_0_height_0__pin_1_ ;
+input [0:0] top_width_0_height_0__pin_2_ ;
+input [0:0] top_width_0_height_0__pin_3_ ;
+input [0:0] top_width_0_height_0__pin_4_ ;
+input [0:0] top_width_0_height_0__pin_5_ ;
+input [0:0] top_width_0_height_0__pin_6_ ;
+input [0:0] top_width_0_height_0__pin_7_ ;
+input [0:0] top_width_0_height_0__pin_8_ ;
+input [0:0] top_width_0_height_0__pin_9_ ;
+input [0:0] top_width_0_height_0__pin_10_ ;
+input [0:0] top_width_0_height_0__pin_11_ ;
+input [0:0] top_width_0_height_0__pin_12_ ;
+input [0:0] top_width_0_height_0__pin_13_ ;
+input [0:0] top_width_0_height_0__pin_14_ ;
+input [0:0] top_width_0_height_0__pin_15_ ;
+input [0:0] top_width_0_height_0__pin_32_ ;
+input [0:0] top_width_0_height_0__pin_33_ ;
+input [0:0] top_width_0_height_0__pin_34_ ;
+input [0:0] right_width_0_height_0__pin_16_ ;
+input [0:0] right_width_0_height_0__pin_17_ ;
+input [0:0] right_width_0_height_0__pin_18_ ;
+input [0:0] right_width_0_height_0__pin_19_ ;
+input [0:0] right_width_0_height_0__pin_20_ ;
+input [0:0] right_width_0_height_0__pin_21_ ;
+input [0:0] right_width_0_height_0__pin_22_ ;
+input [0:0] right_width_0_height_0__pin_23_ ;
+input [0:0] right_width_0_height_0__pin_24_ ;
+input [0:0] right_width_0_height_0__pin_25_ ;
+input [0:0] right_width_0_height_0__pin_26_ ;
+input [0:0] right_width_0_height_0__pin_27_ ;
+input [0:0] right_width_0_height_0__pin_28_ ;
+input [0:0] right_width_0_height_0__pin_29_ ;
+input [0:0] right_width_0_height_0__pin_30_ ;
+input [0:0] right_width_0_height_0__pin_31_ ;
+input [0:0] Reset ;
+input [0:0] ccff_head ;
+output [0:0] top_width_0_height_0__pin_36_upper ;
+output [0:0] top_width_0_height_0__pin_36_lower ;
+output [0:0] top_width_0_height_0__pin_37_upper ;
+output [0:0] top_width_0_height_0__pin_37_lower ;
+output [0:0] top_width_0_height_0__pin_38_upper ;
+output [0:0] top_width_0_height_0__pin_38_lower ;
+output [0:0] top_width_0_height_0__pin_39_upper ;
+output [0:0] top_width_0_height_0__pin_39_lower ;
+output [0:0] top_width_0_height_0__pin_40_upper ;
+output [0:0] top_width_0_height_0__pin_40_lower ;
+output [0:0] top_width_0_height_0__pin_41_upper ;
+output [0:0] top_width_0_height_0__pin_41_lower ;
+output [0:0] top_width_0_height_0__pin_42_upper ;
+output [0:0] top_width_0_height_0__pin_42_lower ;
+output [0:0] top_width_0_height_0__pin_43_upper ;
+output [0:0] top_width_0_height_0__pin_43_lower ;
+output [0:0] right_width_0_height_0__pin_44_upper ;
+output [0:0] right_width_0_height_0__pin_44_lower ;
+output [0:0] right_width_0_height_0__pin_45_upper ;
+output [0:0] right_width_0_height_0__pin_45_lower ;
+output [0:0] right_width_0_height_0__pin_46_upper ;
+output [0:0] right_width_0_height_0__pin_46_lower ;
+output [0:0] right_width_0_height_0__pin_47_upper ;
+output [0:0] right_width_0_height_0__pin_47_lower ;
+output [0:0] right_width_0_height_0__pin_48_upper ;
+output [0:0] right_width_0_height_0__pin_48_lower ;
+output [0:0] right_width_0_height_0__pin_49_upper ;
+output [0:0] right_width_0_height_0__pin_49_lower ;
+output [0:0] right_width_0_height_0__pin_50_upper ;
+output [0:0] right_width_0_height_0__pin_50_lower ;
+output [0:0] right_width_0_height_0__pin_51_upper ;
+output [0:0] right_width_0_height_0__pin_51_lower ;
+output [0:0] bottom_width_0_height_0__pin_52_ ;
+output [0:0] bottom_width_0_height_0__pin_53_ ;
+output [0:0] bottom_width_0_height_0__pin_54_ ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+output SC_OUT_BOT ;
+input Test_en_E_in ;
+input Test_en_W_in ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input pReset_N_in ;
+input Reset_E_in ;
+input Reset_W_in ;
+output Reset_W_out ;
+output Reset_E_out ;
+input prog_clk_0_N_in ;
+input prog_clk_0_S_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_E_out ;
+output prog_clk_0_W_out ;
+output prog_clk_0_N_out ;
+input clk_0_N_in ;
+input clk_0_S_in ;
+
+wire p_abuf10 ;
+wire p_abuf15 ;
+wire prog_clk_0 ;
+wire [0:0] prog_clk ;
+wire [0:0] clk ;
+wire clk_0 ;
+wire [0:0] Test_en ;
+
+assign SC_IN_BOT = SC_IN_TOP ;
+assign Test_en_W_in = Test_en_E_in ;
+assign Reset_W_in = Reset_E_in ;
+assign prog_clk[0] = prog_clk_0 ;
+assign prog_clk_0_S_in = prog_clk_0_N_in ;
+assign clk_0 = clk[0] ;
+assign clk_0_S_in = clk_0_N_in ;
+
+grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
+ .pReset ( pReset ) ,
+ .prog_clk ( { prog_clk_0 } ) ,
+ .Test_en ( Test_en ) ,
+ .clb_I0 ( { top_width_0_height_0__pin_0_[0] ,
+ top_width_0_height_0__pin_1_[0] } ) ,
+ .clb_I0i ( { top_width_0_height_0__pin_2_[0] ,
+ top_width_0_height_0__pin_3_[0] } ) ,
+ .clb_I1 ( { top_width_0_height_0__pin_4_[0] ,
+ top_width_0_height_0__pin_5_[0] } ) ,
+ .clb_I1i ( { top_width_0_height_0__pin_6_[0] ,
+ top_width_0_height_0__pin_7_[0] } ) ,
+ .clb_I2 ( { top_width_0_height_0__pin_8_[0] ,
+ top_width_0_height_0__pin_9_[0] } ) ,
+ .clb_I2i ( { top_width_0_height_0__pin_10_[0] ,
+ top_width_0_height_0__pin_11_[0] } ) ,
+ .clb_I3 ( { top_width_0_height_0__pin_12_[0] ,
+ top_width_0_height_0__pin_13_[0] } ) ,
+ .clb_I3i ( { top_width_0_height_0__pin_14_[0] ,
+ top_width_0_height_0__pin_15_[0] } ) ,
+ .clb_I4 ( { right_width_0_height_0__pin_16_[0] ,
+ right_width_0_height_0__pin_17_[0] } ) ,
+ .clb_I4i ( { right_width_0_height_0__pin_18_[0] ,
+ right_width_0_height_0__pin_19_[0] } ) ,
+ .clb_I5 ( { right_width_0_height_0__pin_20_[0] ,
+ right_width_0_height_0__pin_21_[0] } ) ,
+ .clb_I5i ( { right_width_0_height_0__pin_22_[0] ,
+ right_width_0_height_0__pin_23_[0] } ) ,
+ .clb_I6 ( { right_width_0_height_0__pin_24_[0] ,
+ right_width_0_height_0__pin_25_[0] } ) ,
+ .clb_I6i ( { right_width_0_height_0__pin_26_[0] ,
+ right_width_0_height_0__pin_27_[0] } ) ,
+ .clb_I7 ( { right_width_0_height_0__pin_28_[0] ,
+ right_width_0_height_0__pin_29_[0] } ) ,
+ .clb_I7i ( { right_width_0_height_0__pin_30_[0] ,
+ right_width_0_height_0__pin_31_[0] } ) ,
+ .clb_reg_in ( top_width_0_height_0__pin_32_ ) ,
+ .clb_sc_in ( { SC_IN_BOT } ) ,
+ .clb_cin ( top_width_0_height_0__pin_34_ ) , .clb_reset ( Reset ) ,
+ .clb_clk ( clk ) , .ccff_head ( ccff_head ) ,
+ .clb_O ( { aps_rename_506_ , aps_rename_507_ , aps_rename_508_ ,
+ aps_rename_509_ , aps_rename_510_ , aps_rename_511_ ,
+ aps_rename_512_ , aps_rename_513_ ,
+ right_width_0_height_0__pin_44_lower[0] , aps_rename_515_ ,
+ aps_rename_516_ , aps_rename_517_ ,
+ right_width_0_height_0__pin_48_lower[0] , aps_rename_518_ ,
+ right_width_0_height_0__pin_50_lower[0] , aps_rename_520_ } ) ,
+ .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) ,
+ .clb_sc_out ( { aps_rename_521_ } ) ,
+ .clb_cout ( bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( ccff_tail ) , .p_abuf0 ( SC_OUT_BOT ) ,
+ .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) ,
+ .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) ,
+ .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) ,
+ .p_abuf4 ( top_width_0_height_0__pin_38_lower[0] ) ,
+ .p_abuf5 ( top_width_0_height_0__pin_41_lower[0] ) ,
+ .p_abuf6 ( top_width_0_height_0__pin_40_lower[0] ) ,
+ .p_abuf7 ( top_width_0_height_0__pin_43_lower[0] ) ,
+ .p_abuf8 ( top_width_0_height_0__pin_42_lower[0] ) ,
+ .p_abuf9 ( right_width_0_height_0__pin_45_lower[0] ) ,
+ .p_abuf10 ( p_abuf10 ) ,
+ .p_abuf11 ( right_width_0_height_0__pin_47_lower[0] ) ,
+ .p_abuf12 ( right_width_0_height_0__pin_46_lower[0] ) ,
+ .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) ,
+ .p_abuf14 ( right_width_0_height_0__pin_51_lower[0] ) ,
+ .p_abuf15 ( p_abuf15 ) , .p0 ( optlc_net_224 ) , .p1 ( optlc_net_225 ) ,
+ .p2 ( optlc_net_226 ) , .p3 ( optlc_net_227 ) , .p4 ( optlc_net_228 ) ,
+ .p5 ( optlc_net_229 ) , .p6 ( optlc_net_230 ) , .p7 ( optlc_net_231 ) ) ;
+sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) ,
+ .X ( Test_en[0] ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) ,
+ .X ( aps_rename_522_ ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) ,
+ .X ( aps_rename_523_ ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_W_in ) ,
+ .X ( Reset_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) ,
+ .X ( net_net_182 ) ) ;
+sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk_0 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_1232 ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_2233 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_3234 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_4235 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_113__112 ( .A ( aps_rename_506_ ) ,
+ .X ( top_width_0_height_0__pin_36_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_114__113 ( .A ( aps_rename_507_ ) ,
+ .X ( top_width_0_height_0__pin_37_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_115__114 ( .A ( aps_rename_508_ ) ,
+ .X ( top_width_0_height_0__pin_38_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_116__115 ( .A ( aps_rename_509_ ) ,
+ .X ( top_width_0_height_0__pin_39_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_117__116 ( .A ( aps_rename_510_ ) ,
+ .X ( top_width_0_height_0__pin_40_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_118__117 ( .A ( aps_rename_511_ ) ,
+ .X ( top_width_0_height_0__pin_41_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_119__118 ( .A ( aps_rename_512_ ) ,
+ .X ( top_width_0_height_0__pin_42_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_120__119 ( .A ( aps_rename_513_ ) ,
+ .X ( top_width_0_height_0__pin_43_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_121__120 ( .A ( p_abuf10 ) ,
+ .X ( right_width_0_height_0__pin_44_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_122__121 ( .A ( aps_rename_515_ ) ,
+ .X ( right_width_0_height_0__pin_45_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_123__122 ( .A ( aps_rename_516_ ) ,
+ .X ( right_width_0_height_0__pin_46_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_124__123 ( .A ( aps_rename_517_ ) ,
+ .X ( right_width_0_height_0__pin_47_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_125__124 (
+ .A ( right_width_0_height_0__pin_48_lower[0] ) ,
+ .X ( right_width_0_height_0__pin_48_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_126__125 ( .A ( aps_rename_518_ ) ,
+ .X ( right_width_0_height_0__pin_49_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( p_abuf15 ) ,
+ .X ( right_width_0_height_0__pin_50_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_128__127 ( .A ( aps_rename_520_ ) ,
+ .X ( right_width_0_height_0__pin_51_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( aps_rename_521_ ) ,
+ .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) ,
+ .Y ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_181 ( .A ( aps_rename_522_ ) ,
+ .Y ( BUF_net_181 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( .A ( net_net_182 ) , .X ( Reset_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) ,
+ .HI ( optlc_net_224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( optlc_net_225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( optlc_net_226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( optlc_net_227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( optlc_net_228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .HI ( optlc_net_229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .HI ( optlc_net_230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .HI ( optlc_net_231 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_200 ( .A ( aps_rename_523_ ) ,
+ .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4181393 ( .A ( ctsbuf_net_1232 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_4231398 ( .A ( ctsbuf_net_2233 ) ,
+ .X ( prog_clk_0_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4281403 ( .A ( ctsbuf_net_3234 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4331408 ( .A ( ctsbuf_net_4235 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+endmodule
+
+
+module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , ccff_head , ccff_tail , sc_head ,
+ sc_tail , h_incr0 , p0 , p1 , p2 , p3 , p4 , p5 , p6 , p7 , p8 , p9 ,
+ p10 , p11 , p12 , p13 , p14 , p15 , p16 , p17 , p18 , p19 , p20 , p21 ,
+ p22 , p23 , p24 , p25 , p26 , p27 , p28 , p29 , p30 , p31 , p32 , p33 ,
+ p34 , p35 , p36 , p37 , p38 , p39 , p40 , p41 , p42 , p43 , p44 , p45 ,
+ p46 , p47 , p48 , p49 , p50 , p51 , p52 , p53 , p54 , p55 , p56 , p57 ,
+ p58 , p59 , p60 , p61 , p62 , p63 , p64 , p65 , p66 , p67 , p68 , p69 ,
+ p70 , p71 , p72 , p73 , p74 , p75 , p76 , p77 , p78 , p79 , p80 , p81 ,
+ p82 , p83 , p84 , p85 , p86 , p87 , p88 , p89 , p90 , p91 , p92 , p93 ,
+ p94 , p95 , p96 , p97 , p98 , p99 , p100 , p101 , p102 , p103 , p104 ,
+ p105 , p106 , p107 , p108 , p109 , p110 , p111 , p112 , p113 , p114 ,
+ p115 , p116 , p117 , p118 , p119 , p120 , p121 , p122 , p123 , p124 ,
+ p125 , p126 , p127 , p128 , p129 , p130 , p131 , p132 , p133 , p134 ,
+ p135 , p136 , p137 , p138 , p139 , p140 , p141 , p142 , p143 , p144 ,
+ p145 , p146 , p147 , p148 , p149 , p150 , p151 , p152 , p153 , p154 ,
+ p155 , p156 , p157 , p158 , p159 , p160 , p161 , p162 , p163 , p164 ,
+ p165 , p166 , p167 , p168 , p169 , p170 , p171 , p172 , p173 , p174 ,
+ p175 , p176 , p177 , p178 , p179 , p180 , p181 , p182 , p183 , p184 ,
+ p185 , p186 , p187 , p188 , p189 , p190 , p191 , p192 , p193 , p194 ,
+ p195 , p196 , p197 , p198 , p199 , p200 , p201 , p202 , p203 , p204 ,
+ p205 , p206 , p207 , p208 , p209 , p210 , p211 , p212 , p213 , p214 ,
+ p215 , p216 , p217 , p218 , p219 , p220 , p221 , p222 , p223 , p224 ,
+ p225 , p226 , p227 , p228 , p229 , p230 , p231 , p232 , p233 , p234 ,
+ p235 , p236 , p237 , p238 , p239 , p240 , p241 , p242 , p243 , p244 ,
+ p245 , p246 , p247 , p248 , p249 , p250 , p251 , p252 , p253 , p254 ,
+ p255 , p256 , p257 , p258 , p259 , p260 , p261 , p262 , p263 , p264 ,
+ p265 , p266 , p267 , p268 , p269 , p270 , p271 , p272 , p273 , p274 ,
+ p275 , p276 , p277 , p278 , p279 , p280 , p281 , p282 , p283 , p284 ,
+ p285 , p286 , p287 , p288 , p289 , p290 , p291 , p292 , p293 , p294 ,
+ p295 , p296 , p297 , p298 , p299 , p300 , p301 , p302 , p303 , p304 ,
+ p305 , p306 , p307 , p308 , p309 , p310 , p311 , p312 , p313 , p314 ,
+ p315 , p316 , p317 , p318 , p319 , p320 , p321 , p322 , p323 , p324 ,
+ p325 , p326 , p327 , p328 , p329 , p330 , p331 , p332 , p333 , p334 ,
+ p335 , p336 , p337 , p338 , p339 , p340 , p341 , p342 , p343 , p344 ,
+ p345 , p346 , p347 , p348 , p349 , p350 , p351 , p352 , p353 , p354 ,
+ p355 , p356 , p357 , p358 , p359 , p360 , p361 , p362 , p363 , p364 ,
+ p365 , p366 , p367 , p368 , p369 , p370 , p371 , p372 , p373 , p374 ,
+ p375 , p376 , p377 , p378 , p379 , p380 , p381 , p382 , p383 , p384 ,
+ p385 , p386 , p387 , p388 , p389 , p390 , p391 , p392 , p393 , p394 ,
+ p395 , p396 , p397 , p398 , p399 , p400 , p401 , p402 , p403 , p404 ,
+ p405 , p406 , p407 , p408 , p409 , p410 , p411 , p412 , p413 , p414 ,
+ p415 , p416 , p417 , p418 , p419 , p420 , p421 , p422 , p423 , p424 ,
+ p425 , p426 , p427 , p428 , p429 , p430 , p431 , p432 , p433 , p434 ,
+ p435 , p436 , p437 , p438 , p439 , p440 , p441 , p442 , p443 , p444 ,
+ p445 , p446 , p447 , p448 , p449 , p450 , p451 , p452 , p453 , p454 ,
+ p455 , p456 , p457 , p458 , p459 , p460 , p461 , p462 , p463 , p464 ,
+ p465 , p466 , p467 , p468 , p469 , p470 , p471 , p472 , p473 , p474 ,
+ p475 , p476 , p477 , p478 , p479 , p480 , p481 , p482 , p483 , p484 ,
+ p485 , p486 , p487 , p488 , p489 , p490 , p491 , p492 , p493 , p494 ,
+ p495 , p496 , p497 , p498 , p499 , p500 , p501 , p502 , p503 , p504 ,
+ p505 , p506 , p507 , p508 , p509 , p510 , p511 , p512 , p513 , p514 ,
+ p515 , p516 , p517 , p518 , p519 , p520 , p521 , p522 , p523 , p524 ,
+ p525 , p526 , p527 , p528 , p529 , p530 , p531 , p532 , p533 , p534 ,
+ p535 , p536 , p537 , p538 , p539 , p540 , p541 , p542 , p543 , p544 ,
+ p545 , p546 , p547 , p548 , p549 , p550 , p551 , p552 , p553 , p554 ,
+ p555 , p556 , p557 , p558 , p559 , p560 , p561 , p562 , p563 , p564 ,
+ p565 , p566 , p567 , p568 , p569 , p570 , p571 , p572 , p573 , p574 ,
+ p575 , p576 , p577 , p578 , p579 , p580 , p581 , p582 , p583 , p584 ,
+ p585 , p586 , p587 , p588 , p589 , p590 , p591 , p592 , p593 , p594 ,
+ p595 , p596 , p597 , p598 , p599 , p600 , p601 , p602 , p603 , p604 ,
+ p605 , p606 , p607 , p608 , p609 , p610 , p611 , p612 , p613 , p614 ,
+ p615 , p616 , p617 , p618 , p619 , p620 , p621 , p622 , p623 , p624 ,
+ p625 , p626 , p627 , p628 , p629 , p630 , p631 , p632 , p633 , p634 ,
+ p635 , p636 , p637 , p638 , p639 , p640 , p641 , p642 , p643 , p644 ,
+ p645 , p646 , p647 , p648 , p649 , p650 , p651 , p652 , p653 , p654 ,
+ p655 , p656 , p657 , p658 , p659 , p660 , p661 , p662 , p663 , p664 ,
+ p665 , p666 , p667 , p668 , p669 , p670 , p671 , p672 , p673 , p674 ,
+ p675 , p676 , p677 , p678 , p679 , p680 , p681 , p682 , p683 , p684 ,
+ p685 , p686 , p687 , p688 , p689 , p690 , p691 , p692 , p693 , p694 ,
+ p695 , p696 , p697 , p698 , p699 , p700 , p701 , p702 , p703 , p704 ,
+ p705 , p706 , p707 , p708 , p709 , p710 , p711 , p712 , p713 , p714 ,
+ p715 , p716 , p717 , p718 , p719 , p720 , p721 , p722 , p723 , p724 ,
+ p725 , p726 , p727 , p728 , p729 , p730 , p731 , p732 , p733 , p734 ,
+ p735 , p736 , p737 , p738 , p739 , p740 , p741 , p742 , p743 , p744 ,
+ p745 , p746 , p747 , p748 , p749 , p750 , p751 , p752 , p753 , p754 ,
+ p755 , p756 , p757 , p758 , p759 , p760 , p761 , p762 , p763 , p764 ,
+ p765 , p766 , p767 , p768 , p769 , p770 , p771 , p772 , p773 , p774 ,
+ p775 , p776 , p777 , p778 , p779 , p780 , p781 , p782 , p783 , p784 ,
+ p785 , p786 , p787 , p788 , p789 , p790 , p791 , p792 , p793 , p794 ,
+ p795 , p796 , p797 , p798 , p799 , p800 , p801 , p802 , p803 , p804 ,
+ p805 , p806 , p807 , p808 , p809 , p810 , p811 , p812 , p813 , p814 ,
+ p815 , p816 , p817 , p818 , p819 , p820 , p821 , p822 , p823 , p824 ,
+ p825 , p826 , p827 , p828 , p829 , p830 , p831 , p832 , p833 , p834 ,
+ p835 , p836 , p837 , p838 , p839 , p840 , p841 , p842 , p843 , p844 ,
+ p845 , p846 , p847 , p848 , p849 , p850 , p851 , p852 , p853 , p854 ,
+ p855 , p856 , p857 , p858 , p859 , p860 , p861 , p862 , p863 , p864 ,
+ p865 , p866 , p867 , p868 , p869 , p870 , p871 , p872 , p873 , p874 ,
+ p875 , p876 , p877 , p878 , p879 , p880 , p881 , p882 , p883 , p884 ,
+ p885 , p886 , p887 , p888 , p889 , p890 , p891 , p892 , p893 , p894 ,
+ p895 , p896 , p897 , p898 , p899 , p900 , p901 , p902 , p903 , p904 ,
+ p905 , p906 , p907 , p908 , p909 , p910 , p911 , p912 , p913 , p914 ,
+ p915 , p916 , p917 , p918 , p919 , p920 , p921 , p922 , p923 , p924 ,
+ p925 , p926 , p927 , p928 , p929 , p930 , p931 , p932 , p933 , p934 ,
+ p935 , p936 , p937 , p938 , p939 , p940 , p941 , p942 , p943 , p944 ,
+ p945 , p946 , p947 , p948 , p949 , p950 , p951 , p952 , p953 , p954 ,
+ p955 , p956 , p957 , p958 , p959 , p960 , p961 , p962 , p963 , p964 ,
+ p965 , p966 , p967 , p968 , p969 , p970 , p971 , p972 , p973 , p974 ,
+ p975 , p976 , p977 , p978 , p979 , p980 , p981 , p982 , p983 , p984 ,
+ p985 , p986 , p987 , p988 , p989 , p990 , p991 , p992 , p993 , p994 ,
+ p995 , p996 , p997 , p998 , p999 , p1000 , p1001 , p1002 , p1003 , p1004 ,
+ p1005 , p1006 , p1007 , p1008 , p1009 , p1010 , p1011 , p1012 , p1013 ,
+ p1014 , p1015 , p1016 , p1017 , p1018 , p1019 , p1020 , p1021 , p1022 ,
+ p1023 , p1024 , p1025 , p1026 , p1027 , p1028 , p1029 , p1030 , p1031 ,
+ p1032 , p1033 , p1034 , p1035 , p1036 , p1037 , p1038 , p1039 , p1040 ,
+ p1041 , p1042 , p1043 , p1044 , p1045 , p1046 , p1047 , p1048 , p1049 ,
+ p1050 , p1051 , p1052 , p1053 , p1054 , p1055 , p1056 , p1057 , p1058 ,
+ p1059 , p1060 , p1061 , p1062 , p1063 , p1064 , p1065 , p1066 , p1067 ,
+ p1068 , p1069 , p1070 , p1071 , p1072 , p1073 , p1074 , p1075 , p1076 ,
+ p1077 , p1078 , p1079 , p1080 , p1081 , p1082 , p1083 , p1084 , p1085 ,
+ p1086 , p1087 , p1088 , p1089 , p1090 , p1091 , p1092 , p1093 , p1094 ,
+ p1095 , p1096 , p1097 , p1098 , p1099 , p1100 , p1101 , p1102 , p1103 ,
+ p1104 , p1105 , p1106 , p1107 , p1108 , p1109 , p1110 , p1111 , p1112 ,
+ p1113 , p1114 , p1115 , p1116 , p1117 , p1118 , p1119 , p1120 , p1121 ,
+ p1122 , p1123 , p1124 , p1125 , p1126 , p1127 , p1128 , p1129 , p1130 ,
+ p1131 , p1132 , p1133 , p1134 , p1135 , p1136 , p1137 , p1138 , p1139 ,
+ p1140 , p1141 , p1142 , p1143 , p1144 , p1145 , p1146 , p1147 , p1148 ,
+ p1149 , p1150 , p1151 , p1152 , p1153 , p1154 , p1155 , p1156 , p1157 ,
+ p1158 , p1159 , p1160 , p1161 , p1162 , p1163 , p1164 , p1165 , p1166 ,
+ p1167 , p1168 , p1169 , p1170 , p1171 , p1172 , p1173 , p1174 , p1175 ,
+ p1176 , p1177 , p1178 , p1179 , p1180 , p1181 , p1182 , p1183 , p1184 ,
+ p1185 , p1186 , p1187 , p1188 , p1189 , p1190 , p1191 , p1192 , p1193 ,
+ p1194 , p1195 , p1196 , p1197 , p1198 , p1199 , p1200 , p1201 , p1202 ,
+ p1203 , p1204 , p1205 , p1206 , p1207 , p1208 , p1209 , p1210 , p1211 ,
+ p1212 , p1213 , p1214 , p1215 , p1216 , p1217 , p1218 , p1219 , p1220 ,
+ p1221 , p1222 , p1223 , p1224 , p1225 , p1226 , p1227 , p1228 , p1229 ,
+ p1230 , p1231 , p1232 , p1233 , p1234 , p1235 , p1236 , p1237 , p1238 ,
+ p1239 , p1240 , p1241 , p1242 , p1243 , p1244 , p1245 , p1246 , p1247 ,
+ p1248 , p1249 , p1250 , p1251 , p1252 , p1253 , p1254 , p1255 , p1256 ,
+ p1257 , p1258 , p1259 , p1260 , p1261 , p1262 , p1263 , p1264 , p1265 ,
+ p1266 , p1267 , p1268 , p1269 , p1270 , p1271 , p1272 , p1273 , p1274 ,
+ p1275 , p1276 , p1277 , p1278 , p1279 , p1280 , p1281 , p1282 , p1283 ,
+ p1284 , p1285 , p1286 , p1287 , p1288 , p1289 , p1290 , p1291 , p1292 ,
+ p1293 , p1294 , p1295 , p1296 , p1297 , p1298 , p1299 , p1300 , p1301 ,
+ p1302 , p1303 , p1304 , p1305 , p1306 , p1307 , p1308 , p1309 , p1310 ,
+ p1311 , p1312 , p1313 , p1314 , p1315 , p1316 , p1317 , p1318 , p1319 ,
+ p1320 , p1321 , p1322 , p1323 , p1324 , p1325 , p1326 , p1327 , p1328 ,
+ p1329 , p1330 , p1331 , p1332 , p1333 , p1334 , p1335 , p1336 , p1337 ,
+ p1338 , p1339 , p1340 , p1341 , p1342 , p1343 , p1344 , p1345 , p1346 ,
+ p1347 , p1348 , p1349 , p1350 , p1351 , p1352 , p1353 , p1354 , p1355 ,
+ p1356 , p1357 , p1358 , p1359 , p1360 , p1361 , p1362 , p1363 , p1364 ,
+ p1365 , p1366 , p1367 , p1368 , p1369 , p1370 , p1371 , p1372 , p1373 ,
+ p1374 , p1375 , p1376 , p1377 , p1378 , p1379 , p1380 , p1381 , p1382 ,
+ p1383 , p1384 , p1385 , p1386 , p1387 , p1388 , p1389 , p1390 , p1391 ,
+ p1392 , p1393 , p1394 , p1395 , p1396 , p1397 , p1398 , p1399 , p1400 ,
+ p1401 , p1402 , p1403 , p1404 , p1405 , p1406 , p1407 , p1408 , p1409 ,
+ p1410 , p1411 , p1412 , p1413 , p1414 , p1415 , p1416 , p1417 , p1418 ,
+ p1419 , p1420 , p1421 , p1422 , p1423 , p1424 , p1425 , p1426 , p1427 ,
+ p1428 , p1429 , p1430 , p1431 , p1432 , p1433 , p1434 , p1435 , p1436 ,
+ p1437 , p1438 , p1439 , p1440 , p1441 , p1442 , p1443 , p1444 , p1445 ,
+ p1446 , p1447 , p1448 , p1449 , p1450 , p1451 , p1452 , p1453 , p1454 ,
+ p1455 , p1456 , p1457 , p1458 , p1459 , p1460 , p1461 , p1462 , p1463 ,
+ p1464 , p1465 , p1466 , p1467 , p1468 , p1469 , p1470 , p1471 , p1472 ,
+ p1473 , p1474 , p1475 , p1476 , p1477 , p1478 , p1479 , p1480 , p1481 ,
+ p1482 , p1483 , p1484 , p1485 , p1486 , p1487 , p1488 , p1489 , p1490 ,
+ p1491 , p1492 , p1493 , p1494 , p1495 , p1496 , p1497 , p1498 , p1499 ,
+ p1500 , p1501 , p1502 , p1503 , p1504 , p1505 , p1506 , p1507 , p1508 ,
+ p1509 , p1510 , p1511 , p1512 , p1513 , p1514 , p1515 , p1516 , p1517 ,
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+ p1905 , p1906 , p1907 , p1908 , p1909 , p1910 , p1911 , p1912 , p1913 ,
+ p1914 , p1915 , p1916 , p1917 , p1918 , p1919 , p1920 , p1921 , p1922 ,
+ p1923 , p1924 , p1925 , p1926 , p1927 , p1928 , p1929 , p1930 , p1931 ,
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+ p3390 , p3391 , p3392 , p3393 , p3394 , p3395 , p3396 , p3397 , p3398 ,
+ p3399 , p3400 , p3401 , p3402 , p3403 , p3404 , p3405 , p3406 , p3407 ,
+ p3408 , p3409 , p3410 , p3411 , p3412 , p3413 , p3414 , p3415 , p3416 ,
+ p3417 , p3418 , p3419 , p3420 , p3421 , p3422 , p3423 , p3424 , p3425 ,
+ p3426 , p3427 , p3428 , p3429 , p3430 , p3431 , p3432 , p3433 , p3434 ,
+ p3435 , p3436 , p3437 , p3438 , p3439 , p3440 , p3441 , p3442 , p3443 ,
+ p3444 , p3445 , p3446 , p3447 , p3448 , p3449 , p3450 , p3451 , p3452 ,
+ p3453 , p3454 , p3455 , p3456 , p3457 , p3458 , p3459 , p3460 , p3461 ,
+ p3462 , p3463 , p3464 , p3465 , p3466 , p3467 , p3468 , p3469 , p3470 ,
+ p3471 , p3472 , p3473 , p3474 , p3475 , p3476 , p3477 , p3478 , p3479 ,
+ p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , p3487 , p3488 ,
+ p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , p3496 , p3497 ,
+ p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , p3505 , p3506 ,
+ p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , p3514 , p3515 ,
+ p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 , p3523 , p3524 ,
+ p3525 , p3526 , p3527 , p3528 , p3529 , p3530 , p3531 , p3532 , p3533 ,
+ p3534 , p3535 , p3536 , p3537 , p3538 , p3539 , p3540 , p3541 , p3542 ,
+ p3543 , p3544 , p3545 , p3546 , p3547 , p3548 , p3549 , p3550 , p3551 ,
+ p3552 , p3553 , p3554 , p3555 , p3556 , p3557 , p3558 , p3559 , p3560 ,
+ p3561 , p3562 , p3563 , p3564 , p3565 , p3566 , p3567 , p3568 , p3569 ,
+ p3570 , p3571 , p3572 , p3573 , p3574 , p3575 , p3576 , p3577 , p3578 ,
+ p3579 , p3580 , p3581 , p3582 , p3583 , p3584 , p3585 , p3586 , p3587 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:0] IO_ISOL_N ;
+input [0:0] clk ;
+input [0:0] Reset ;
+input [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+input sc_head ;
+output sc_tail ;
+input h_incr0 ;
+input p0 ;
+input p1 ;
+input p2 ;
+input p3 ;
+input p4 ;
+input p5 ;
+input p6 ;
+input p7 ;
+input p8 ;
+input p9 ;
+input p10 ;
+input p11 ;
+input p12 ;
+input p13 ;
+input p14 ;
+input p15 ;
+input p16 ;
+input p17 ;
+input p18 ;
+input p19 ;
+input p20 ;
+input p21 ;
+input p22 ;
+input p23 ;
+input p24 ;
+input p25 ;
+input p26 ;
+input p27 ;
+input p28 ;
+input p29 ;
+input p30 ;
+input p31 ;
+input p32 ;
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+
+wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__0_ccff_tail ;
+wire [0:29] cbx_1__0__0_chanx_left_out ;
+wire [0:29] cbx_1__0__0_chanx_right_out ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__10_ccff_tail ;
+wire [0:29] cbx_1__0__10_chanx_left_out ;
+wire [0:29] cbx_1__0__10_chanx_right_out ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__11_ccff_tail ;
+wire [0:29] cbx_1__0__11_chanx_left_out ;
+wire [0:29] cbx_1__0__11_chanx_right_out ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__1_ccff_tail ;
+wire [0:29] cbx_1__0__1_chanx_left_out ;
+wire [0:29] cbx_1__0__1_chanx_right_out ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__2_ccff_tail ;
+wire [0:29] cbx_1__0__2_chanx_left_out ;
+wire [0:29] cbx_1__0__2_chanx_right_out ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__3_ccff_tail ;
+wire [0:29] cbx_1__0__3_chanx_left_out ;
+wire [0:29] cbx_1__0__3_chanx_right_out ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__4_ccff_tail ;
+wire [0:29] cbx_1__0__4_chanx_left_out ;
+wire [0:29] cbx_1__0__4_chanx_right_out ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__5_ccff_tail ;
+wire [0:29] cbx_1__0__5_chanx_left_out ;
+wire [0:29] cbx_1__0__5_chanx_right_out ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__6_ccff_tail ;
+wire [0:29] cbx_1__0__6_chanx_left_out ;
+wire [0:29] cbx_1__0__6_chanx_right_out ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__7_ccff_tail ;
+wire [0:29] cbx_1__0__7_chanx_left_out ;
+wire [0:29] cbx_1__0__7_chanx_right_out ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__8_ccff_tail ;
+wire [0:29] cbx_1__0__8_chanx_left_out ;
+wire [0:29] cbx_1__0__8_chanx_right_out ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__9_ccff_tail ;
+wire [0:29] cbx_1__0__9_chanx_left_out ;
+wire [0:29] cbx_1__0__9_chanx_right_out ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__0_ccff_tail ;
+wire [0:29] cbx_1__12__0_chanx_left_out ;
+wire [0:29] cbx_1__12__0_chanx_right_out ;
+wire [0:0] cbx_1__12__0_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__10_ccff_tail ;
+wire [0:29] cbx_1__12__10_chanx_left_out ;
+wire [0:29] cbx_1__12__10_chanx_right_out ;
+wire [0:0] cbx_1__12__10_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__11_ccff_tail ;
+wire [0:29] cbx_1__12__11_chanx_left_out ;
+wire [0:29] cbx_1__12__11_chanx_right_out ;
+wire [0:0] cbx_1__12__11_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__1_ccff_tail ;
+wire [0:29] cbx_1__12__1_chanx_left_out ;
+wire [0:29] cbx_1__12__1_chanx_right_out ;
+wire [0:0] cbx_1__12__1_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__2_ccff_tail ;
+wire [0:29] cbx_1__12__2_chanx_left_out ;
+wire [0:29] cbx_1__12__2_chanx_right_out ;
+wire [0:0] cbx_1__12__2_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__3_ccff_tail ;
+wire [0:29] cbx_1__12__3_chanx_left_out ;
+wire [0:29] cbx_1__12__3_chanx_right_out ;
+wire [0:0] cbx_1__12__3_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__4_ccff_tail ;
+wire [0:29] cbx_1__12__4_chanx_left_out ;
+wire [0:29] cbx_1__12__4_chanx_right_out ;
+wire [0:0] cbx_1__12__4_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__5_ccff_tail ;
+wire [0:29] cbx_1__12__5_chanx_left_out ;
+wire [0:29] cbx_1__12__5_chanx_right_out ;
+wire [0:0] cbx_1__12__5_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__6_ccff_tail ;
+wire [0:29] cbx_1__12__6_chanx_left_out ;
+wire [0:29] cbx_1__12__6_chanx_right_out ;
+wire [0:0] cbx_1__12__6_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__7_ccff_tail ;
+wire [0:29] cbx_1__12__7_chanx_left_out ;
+wire [0:29] cbx_1__12__7_chanx_right_out ;
+wire [0:0] cbx_1__12__7_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__8_ccff_tail ;
+wire [0:29] cbx_1__12__8_chanx_left_out ;
+wire [0:29] cbx_1__12__8_chanx_right_out ;
+wire [0:0] cbx_1__12__8_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__9_ccff_tail ;
+wire [0:29] cbx_1__12__9_chanx_left_out ;
+wire [0:29] cbx_1__12__9_chanx_right_out ;
+wire [0:0] cbx_1__12__9_top_grid_pin_0_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__0_ccff_tail ;
+wire [0:29] cbx_1__1__0_chanx_left_out ;
+wire [0:29] cbx_1__1__0_chanx_right_out ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__100_ccff_tail ;
+wire [0:29] cbx_1__1__100_chanx_left_out ;
+wire [0:29] cbx_1__1__100_chanx_right_out ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__101_ccff_tail ;
+wire [0:29] cbx_1__1__101_chanx_left_out ;
+wire [0:29] cbx_1__1__101_chanx_right_out ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__102_ccff_tail ;
+wire [0:29] cbx_1__1__102_chanx_left_out ;
+wire [0:29] cbx_1__1__102_chanx_right_out ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__103_ccff_tail ;
+wire [0:29] cbx_1__1__103_chanx_left_out ;
+wire [0:29] cbx_1__1__103_chanx_right_out ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__104_ccff_tail ;
+wire [0:29] cbx_1__1__104_chanx_left_out ;
+wire [0:29] cbx_1__1__104_chanx_right_out ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__105_ccff_tail ;
+wire [0:29] cbx_1__1__105_chanx_left_out ;
+wire [0:29] cbx_1__1__105_chanx_right_out ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__106_ccff_tail ;
+wire [0:29] cbx_1__1__106_chanx_left_out ;
+wire [0:29] cbx_1__1__106_chanx_right_out ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__107_ccff_tail ;
+wire [0:29] cbx_1__1__107_chanx_left_out ;
+wire [0:29] cbx_1__1__107_chanx_right_out ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__108_ccff_tail ;
+wire [0:29] cbx_1__1__108_chanx_left_out ;
+wire [0:29] cbx_1__1__108_chanx_right_out ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__109_ccff_tail ;
+wire [0:29] cbx_1__1__109_chanx_left_out ;
+wire [0:29] cbx_1__1__109_chanx_right_out ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__10_ccff_tail ;
+wire [0:29] cbx_1__1__10_chanx_left_out ;
+wire [0:29] cbx_1__1__10_chanx_right_out ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__110_ccff_tail ;
+wire [0:29] cbx_1__1__110_chanx_left_out ;
+wire [0:29] cbx_1__1__110_chanx_right_out ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__111_ccff_tail ;
+wire [0:29] cbx_1__1__111_chanx_left_out ;
+wire [0:29] cbx_1__1__111_chanx_right_out ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__112_ccff_tail ;
+wire [0:29] cbx_1__1__112_chanx_left_out ;
+wire [0:29] cbx_1__1__112_chanx_right_out ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__113_ccff_tail ;
+wire [0:29] cbx_1__1__113_chanx_left_out ;
+wire [0:29] cbx_1__1__113_chanx_right_out ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__114_ccff_tail ;
+wire [0:29] cbx_1__1__114_chanx_left_out ;
+wire [0:29] cbx_1__1__114_chanx_right_out ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__115_ccff_tail ;
+wire [0:29] cbx_1__1__115_chanx_left_out ;
+wire [0:29] cbx_1__1__115_chanx_right_out ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__116_ccff_tail ;
+wire [0:29] cbx_1__1__116_chanx_left_out ;
+wire [0:29] cbx_1__1__116_chanx_right_out ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__117_ccff_tail ;
+wire [0:29] cbx_1__1__117_chanx_left_out ;
+wire [0:29] cbx_1__1__117_chanx_right_out ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__118_ccff_tail ;
+wire [0:29] cbx_1__1__118_chanx_left_out ;
+wire [0:29] cbx_1__1__118_chanx_right_out ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__119_ccff_tail ;
+wire [0:29] cbx_1__1__119_chanx_left_out ;
+wire [0:29] cbx_1__1__119_chanx_right_out ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__11_ccff_tail ;
+wire [0:29] cbx_1__1__11_chanx_left_out ;
+wire [0:29] cbx_1__1__11_chanx_right_out ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__120_ccff_tail ;
+wire [0:29] cbx_1__1__120_chanx_left_out ;
+wire [0:29] cbx_1__1__120_chanx_right_out ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__121_ccff_tail ;
+wire [0:29] cbx_1__1__121_chanx_left_out ;
+wire [0:29] cbx_1__1__121_chanx_right_out ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__122_ccff_tail ;
+wire [0:29] cbx_1__1__122_chanx_left_out ;
+wire [0:29] cbx_1__1__122_chanx_right_out ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__123_ccff_tail ;
+wire [0:29] cbx_1__1__123_chanx_left_out ;
+wire [0:29] cbx_1__1__123_chanx_right_out ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__124_ccff_tail ;
+wire [0:29] cbx_1__1__124_chanx_left_out ;
+wire [0:29] cbx_1__1__124_chanx_right_out ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__125_ccff_tail ;
+wire [0:29] cbx_1__1__125_chanx_left_out ;
+wire [0:29] cbx_1__1__125_chanx_right_out ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__126_ccff_tail ;
+wire [0:29] cbx_1__1__126_chanx_left_out ;
+wire [0:29] cbx_1__1__126_chanx_right_out ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__127_ccff_tail ;
+wire [0:29] cbx_1__1__127_chanx_left_out ;
+wire [0:29] cbx_1__1__127_chanx_right_out ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__128_ccff_tail ;
+wire [0:29] cbx_1__1__128_chanx_left_out ;
+wire [0:29] cbx_1__1__128_chanx_right_out ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__129_ccff_tail ;
+wire [0:29] cbx_1__1__129_chanx_left_out ;
+wire [0:29] cbx_1__1__129_chanx_right_out ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__12_ccff_tail ;
+wire [0:29] cbx_1__1__12_chanx_left_out ;
+wire [0:29] cbx_1__1__12_chanx_right_out ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__130_ccff_tail ;
+wire [0:29] cbx_1__1__130_chanx_left_out ;
+wire [0:29] cbx_1__1__130_chanx_right_out ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__131_ccff_tail ;
+wire [0:29] cbx_1__1__131_chanx_left_out ;
+wire [0:29] cbx_1__1__131_chanx_right_out ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__13_ccff_tail ;
+wire [0:29] cbx_1__1__13_chanx_left_out ;
+wire [0:29] cbx_1__1__13_chanx_right_out ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__14_ccff_tail ;
+wire [0:29] cbx_1__1__14_chanx_left_out ;
+wire [0:29] cbx_1__1__14_chanx_right_out ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__15_ccff_tail ;
+wire [0:29] cbx_1__1__15_chanx_left_out ;
+wire [0:29] cbx_1__1__15_chanx_right_out ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__16_ccff_tail ;
+wire [0:29] cbx_1__1__16_chanx_left_out ;
+wire [0:29] cbx_1__1__16_chanx_right_out ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__17_ccff_tail ;
+wire [0:29] cbx_1__1__17_chanx_left_out ;
+wire [0:29] cbx_1__1__17_chanx_right_out ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__18_ccff_tail ;
+wire [0:29] cbx_1__1__18_chanx_left_out ;
+wire [0:29] cbx_1__1__18_chanx_right_out ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__19_ccff_tail ;
+wire [0:29] cbx_1__1__19_chanx_left_out ;
+wire [0:29] cbx_1__1__19_chanx_right_out ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__1_ccff_tail ;
+wire [0:29] cbx_1__1__1_chanx_left_out ;
+wire [0:29] cbx_1__1__1_chanx_right_out ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__20_ccff_tail ;
+wire [0:29] cbx_1__1__20_chanx_left_out ;
+wire [0:29] cbx_1__1__20_chanx_right_out ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__21_ccff_tail ;
+wire [0:29] cbx_1__1__21_chanx_left_out ;
+wire [0:29] cbx_1__1__21_chanx_right_out ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__22_ccff_tail ;
+wire [0:29] cbx_1__1__22_chanx_left_out ;
+wire [0:29] cbx_1__1__22_chanx_right_out ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__23_ccff_tail ;
+wire [0:29] cbx_1__1__23_chanx_left_out ;
+wire [0:29] cbx_1__1__23_chanx_right_out ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__24_ccff_tail ;
+wire [0:29] cbx_1__1__24_chanx_left_out ;
+wire [0:29] cbx_1__1__24_chanx_right_out ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__25_ccff_tail ;
+wire [0:29] cbx_1__1__25_chanx_left_out ;
+wire [0:29] cbx_1__1__25_chanx_right_out ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__26_ccff_tail ;
+wire [0:29] cbx_1__1__26_chanx_left_out ;
+wire [0:29] cbx_1__1__26_chanx_right_out ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__27_ccff_tail ;
+wire [0:29] cbx_1__1__27_chanx_left_out ;
+wire [0:29] cbx_1__1__27_chanx_right_out ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__28_ccff_tail ;
+wire [0:29] cbx_1__1__28_chanx_left_out ;
+wire [0:29] cbx_1__1__28_chanx_right_out ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__29_ccff_tail ;
+wire [0:29] cbx_1__1__29_chanx_left_out ;
+wire [0:29] cbx_1__1__29_chanx_right_out ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__2_ccff_tail ;
+wire [0:29] cbx_1__1__2_chanx_left_out ;
+wire [0:29] cbx_1__1__2_chanx_right_out ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__30_ccff_tail ;
+wire [0:29] cbx_1__1__30_chanx_left_out ;
+wire [0:29] cbx_1__1__30_chanx_right_out ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__31_ccff_tail ;
+wire [0:29] cbx_1__1__31_chanx_left_out ;
+wire [0:29] cbx_1__1__31_chanx_right_out ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__32_ccff_tail ;
+wire [0:29] cbx_1__1__32_chanx_left_out ;
+wire [0:29] cbx_1__1__32_chanx_right_out ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__33_ccff_tail ;
+wire [0:29] cbx_1__1__33_chanx_left_out ;
+wire [0:29] cbx_1__1__33_chanx_right_out ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__34_ccff_tail ;
+wire [0:29] cbx_1__1__34_chanx_left_out ;
+wire [0:29] cbx_1__1__34_chanx_right_out ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__35_ccff_tail ;
+wire [0:29] cbx_1__1__35_chanx_left_out ;
+wire [0:29] cbx_1__1__35_chanx_right_out ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__36_ccff_tail ;
+wire [0:29] cbx_1__1__36_chanx_left_out ;
+wire [0:29] cbx_1__1__36_chanx_right_out ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__37_ccff_tail ;
+wire [0:29] cbx_1__1__37_chanx_left_out ;
+wire [0:29] cbx_1__1__37_chanx_right_out ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__38_ccff_tail ;
+wire [0:29] cbx_1__1__38_chanx_left_out ;
+wire [0:29] cbx_1__1__38_chanx_right_out ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__39_ccff_tail ;
+wire [0:29] cbx_1__1__39_chanx_left_out ;
+wire [0:29] cbx_1__1__39_chanx_right_out ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__3_ccff_tail ;
+wire [0:29] cbx_1__1__3_chanx_left_out ;
+wire [0:29] cbx_1__1__3_chanx_right_out ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__40_ccff_tail ;
+wire [0:29] cbx_1__1__40_chanx_left_out ;
+wire [0:29] cbx_1__1__40_chanx_right_out ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__41_ccff_tail ;
+wire [0:29] cbx_1__1__41_chanx_left_out ;
+wire [0:29] cbx_1__1__41_chanx_right_out ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__42_ccff_tail ;
+wire [0:29] cbx_1__1__42_chanx_left_out ;
+wire [0:29] cbx_1__1__42_chanx_right_out ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__43_ccff_tail ;
+wire [0:29] cbx_1__1__43_chanx_left_out ;
+wire [0:29] cbx_1__1__43_chanx_right_out ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__44_ccff_tail ;
+wire [0:29] cbx_1__1__44_chanx_left_out ;
+wire [0:29] cbx_1__1__44_chanx_right_out ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__45_ccff_tail ;
+wire [0:29] cbx_1__1__45_chanx_left_out ;
+wire [0:29] cbx_1__1__45_chanx_right_out ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__46_ccff_tail ;
+wire [0:29] cbx_1__1__46_chanx_left_out ;
+wire [0:29] cbx_1__1__46_chanx_right_out ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__47_ccff_tail ;
+wire [0:29] cbx_1__1__47_chanx_left_out ;
+wire [0:29] cbx_1__1__47_chanx_right_out ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__48_ccff_tail ;
+wire [0:29] cbx_1__1__48_chanx_left_out ;
+wire [0:29] cbx_1__1__48_chanx_right_out ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__49_ccff_tail ;
+wire [0:29] cbx_1__1__49_chanx_left_out ;
+wire [0:29] cbx_1__1__49_chanx_right_out ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__4_ccff_tail ;
+wire [0:29] cbx_1__1__4_chanx_left_out ;
+wire [0:29] cbx_1__1__4_chanx_right_out ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__50_ccff_tail ;
+wire [0:29] cbx_1__1__50_chanx_left_out ;
+wire [0:29] cbx_1__1__50_chanx_right_out ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__51_ccff_tail ;
+wire [0:29] cbx_1__1__51_chanx_left_out ;
+wire [0:29] cbx_1__1__51_chanx_right_out ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__52_ccff_tail ;
+wire [0:29] cbx_1__1__52_chanx_left_out ;
+wire [0:29] cbx_1__1__52_chanx_right_out ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__53_ccff_tail ;
+wire [0:29] cbx_1__1__53_chanx_left_out ;
+wire [0:29] cbx_1__1__53_chanx_right_out ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__54_ccff_tail ;
+wire [0:29] cbx_1__1__54_chanx_left_out ;
+wire [0:29] cbx_1__1__54_chanx_right_out ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__55_ccff_tail ;
+wire [0:29] cbx_1__1__55_chanx_left_out ;
+wire [0:29] cbx_1__1__55_chanx_right_out ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__56_ccff_tail ;
+wire [0:29] cbx_1__1__56_chanx_left_out ;
+wire [0:29] cbx_1__1__56_chanx_right_out ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__57_ccff_tail ;
+wire [0:29] cbx_1__1__57_chanx_left_out ;
+wire [0:29] cbx_1__1__57_chanx_right_out ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__58_ccff_tail ;
+wire [0:29] cbx_1__1__58_chanx_left_out ;
+wire [0:29] cbx_1__1__58_chanx_right_out ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__59_ccff_tail ;
+wire [0:29] cbx_1__1__59_chanx_left_out ;
+wire [0:29] cbx_1__1__59_chanx_right_out ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__5_ccff_tail ;
+wire [0:29] cbx_1__1__5_chanx_left_out ;
+wire [0:29] cbx_1__1__5_chanx_right_out ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__60_ccff_tail ;
+wire [0:29] cbx_1__1__60_chanx_left_out ;
+wire [0:29] cbx_1__1__60_chanx_right_out ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__61_ccff_tail ;
+wire [0:29] cbx_1__1__61_chanx_left_out ;
+wire [0:29] cbx_1__1__61_chanx_right_out ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__62_ccff_tail ;
+wire [0:29] cbx_1__1__62_chanx_left_out ;
+wire [0:29] cbx_1__1__62_chanx_right_out ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__63_ccff_tail ;
+wire [0:29] cbx_1__1__63_chanx_left_out ;
+wire [0:29] cbx_1__1__63_chanx_right_out ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__64_ccff_tail ;
+wire [0:29] cbx_1__1__64_chanx_left_out ;
+wire [0:29] cbx_1__1__64_chanx_right_out ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__65_ccff_tail ;
+wire [0:29] cbx_1__1__65_chanx_left_out ;
+wire [0:29] cbx_1__1__65_chanx_right_out ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__66_ccff_tail ;
+wire [0:29] cbx_1__1__66_chanx_left_out ;
+wire [0:29] cbx_1__1__66_chanx_right_out ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__67_ccff_tail ;
+wire [0:29] cbx_1__1__67_chanx_left_out ;
+wire [0:29] cbx_1__1__67_chanx_right_out ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__68_ccff_tail ;
+wire [0:29] cbx_1__1__68_chanx_left_out ;
+wire [0:29] cbx_1__1__68_chanx_right_out ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__69_ccff_tail ;
+wire [0:29] cbx_1__1__69_chanx_left_out ;
+wire [0:29] cbx_1__1__69_chanx_right_out ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__6_ccff_tail ;
+wire [0:29] cbx_1__1__6_chanx_left_out ;
+wire [0:29] cbx_1__1__6_chanx_right_out ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__70_ccff_tail ;
+wire [0:29] cbx_1__1__70_chanx_left_out ;
+wire [0:29] cbx_1__1__70_chanx_right_out ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__71_ccff_tail ;
+wire [0:29] cbx_1__1__71_chanx_left_out ;
+wire [0:29] cbx_1__1__71_chanx_right_out ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__72_ccff_tail ;
+wire [0:29] cbx_1__1__72_chanx_left_out ;
+wire [0:29] cbx_1__1__72_chanx_right_out ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__73_ccff_tail ;
+wire [0:29] cbx_1__1__73_chanx_left_out ;
+wire [0:29] cbx_1__1__73_chanx_right_out ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__74_ccff_tail ;
+wire [0:29] cbx_1__1__74_chanx_left_out ;
+wire [0:29] cbx_1__1__74_chanx_right_out ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__75_ccff_tail ;
+wire [0:29] cbx_1__1__75_chanx_left_out ;
+wire [0:29] cbx_1__1__75_chanx_right_out ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__76_ccff_tail ;
+wire [0:29] cbx_1__1__76_chanx_left_out ;
+wire [0:29] cbx_1__1__76_chanx_right_out ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__77_ccff_tail ;
+wire [0:29] cbx_1__1__77_chanx_left_out ;
+wire [0:29] cbx_1__1__77_chanx_right_out ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__78_ccff_tail ;
+wire [0:29] cbx_1__1__78_chanx_left_out ;
+wire [0:29] cbx_1__1__78_chanx_right_out ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__79_ccff_tail ;
+wire [0:29] cbx_1__1__79_chanx_left_out ;
+wire [0:29] cbx_1__1__79_chanx_right_out ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__7_ccff_tail ;
+wire [0:29] cbx_1__1__7_chanx_left_out ;
+wire [0:29] cbx_1__1__7_chanx_right_out ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__80_ccff_tail ;
+wire [0:29] cbx_1__1__80_chanx_left_out ;
+wire [0:29] cbx_1__1__80_chanx_right_out ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__81_ccff_tail ;
+wire [0:29] cbx_1__1__81_chanx_left_out ;
+wire [0:29] cbx_1__1__81_chanx_right_out ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__82_ccff_tail ;
+wire [0:29] cbx_1__1__82_chanx_left_out ;
+wire [0:29] cbx_1__1__82_chanx_right_out ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__83_ccff_tail ;
+wire [0:29] cbx_1__1__83_chanx_left_out ;
+wire [0:29] cbx_1__1__83_chanx_right_out ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__84_ccff_tail ;
+wire [0:29] cbx_1__1__84_chanx_left_out ;
+wire [0:29] cbx_1__1__84_chanx_right_out ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__85_ccff_tail ;
+wire [0:29] cbx_1__1__85_chanx_left_out ;
+wire [0:29] cbx_1__1__85_chanx_right_out ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__86_ccff_tail ;
+wire [0:29] cbx_1__1__86_chanx_left_out ;
+wire [0:29] cbx_1__1__86_chanx_right_out ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__87_ccff_tail ;
+wire [0:29] cbx_1__1__87_chanx_left_out ;
+wire [0:29] cbx_1__1__87_chanx_right_out ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__88_ccff_tail ;
+wire [0:29] cbx_1__1__88_chanx_left_out ;
+wire [0:29] cbx_1__1__88_chanx_right_out ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__89_ccff_tail ;
+wire [0:29] cbx_1__1__89_chanx_left_out ;
+wire [0:29] cbx_1__1__89_chanx_right_out ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__8_ccff_tail ;
+wire [0:29] cbx_1__1__8_chanx_left_out ;
+wire [0:29] cbx_1__1__8_chanx_right_out ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__90_ccff_tail ;
+wire [0:29] cbx_1__1__90_chanx_left_out ;
+wire [0:29] cbx_1__1__90_chanx_right_out ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__91_ccff_tail ;
+wire [0:29] cbx_1__1__91_chanx_left_out ;
+wire [0:29] cbx_1__1__91_chanx_right_out ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__92_ccff_tail ;
+wire [0:29] cbx_1__1__92_chanx_left_out ;
+wire [0:29] cbx_1__1__92_chanx_right_out ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__93_ccff_tail ;
+wire [0:29] cbx_1__1__93_chanx_left_out ;
+wire [0:29] cbx_1__1__93_chanx_right_out ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__94_ccff_tail ;
+wire [0:29] cbx_1__1__94_chanx_left_out ;
+wire [0:29] cbx_1__1__94_chanx_right_out ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__95_ccff_tail ;
+wire [0:29] cbx_1__1__95_chanx_left_out ;
+wire [0:29] cbx_1__1__95_chanx_right_out ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__96_ccff_tail ;
+wire [0:29] cbx_1__1__96_chanx_left_out ;
+wire [0:29] cbx_1__1__96_chanx_right_out ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__97_ccff_tail ;
+wire [0:29] cbx_1__1__97_chanx_left_out ;
+wire [0:29] cbx_1__1__97_chanx_right_out ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__98_ccff_tail ;
+wire [0:29] cbx_1__1__98_chanx_left_out ;
+wire [0:29] cbx_1__1__98_chanx_right_out ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__99_ccff_tail ;
+wire [0:29] cbx_1__1__99_chanx_left_out ;
+wire [0:29] cbx_1__1__99_chanx_right_out ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__9_ccff_tail ;
+wire [0:29] cbx_1__1__9_chanx_left_out ;
+wire [0:29] cbx_1__1__9_chanx_right_out ;
+wire [0:0] cby_0__1__0_ccff_tail ;
+wire [0:29] cby_0__1__0_chany_bottom_out ;
+wire [0:29] cby_0__1__0_chany_top_out ;
+wire [0:0] cby_0__1__0_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__10_ccff_tail ;
+wire [0:29] cby_0__1__10_chany_bottom_out ;
+wire [0:29] cby_0__1__10_chany_top_out ;
+wire [0:0] cby_0__1__10_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__11_ccff_tail ;
+wire [0:29] cby_0__1__11_chany_bottom_out ;
+wire [0:29] cby_0__1__11_chany_top_out ;
+wire [0:0] cby_0__1__11_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__1_ccff_tail ;
+wire [0:29] cby_0__1__1_chany_bottom_out ;
+wire [0:29] cby_0__1__1_chany_top_out ;
+wire [0:0] cby_0__1__1_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__2_ccff_tail ;
+wire [0:29] cby_0__1__2_chany_bottom_out ;
+wire [0:29] cby_0__1__2_chany_top_out ;
+wire [0:0] cby_0__1__2_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__3_ccff_tail ;
+wire [0:29] cby_0__1__3_chany_bottom_out ;
+wire [0:29] cby_0__1__3_chany_top_out ;
+wire [0:0] cby_0__1__3_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__4_ccff_tail ;
+wire [0:29] cby_0__1__4_chany_bottom_out ;
+wire [0:29] cby_0__1__4_chany_top_out ;
+wire [0:0] cby_0__1__4_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__5_ccff_tail ;
+wire [0:29] cby_0__1__5_chany_bottom_out ;
+wire [0:29] cby_0__1__5_chany_top_out ;
+wire [0:0] cby_0__1__5_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__6_ccff_tail ;
+wire [0:29] cby_0__1__6_chany_bottom_out ;
+wire [0:29] cby_0__1__6_chany_top_out ;
+wire [0:0] cby_0__1__6_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__7_ccff_tail ;
+wire [0:29] cby_0__1__7_chany_bottom_out ;
+wire [0:29] cby_0__1__7_chany_top_out ;
+wire [0:0] cby_0__1__7_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__8_ccff_tail ;
+wire [0:29] cby_0__1__8_chany_bottom_out ;
+wire [0:29] cby_0__1__8_chany_top_out ;
+wire [0:0] cby_0__1__8_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__9_ccff_tail ;
+wire [0:29] cby_0__1__9_chany_bottom_out ;
+wire [0:29] cby_0__1__9_chany_top_out ;
+wire [0:0] cby_0__1__9_left_grid_pin_0_ ;
+wire [0:0] cby_12__1__0_ccff_tail ;
+wire [0:29] cby_12__1__0_chany_bottom_out ;
+wire [0:29] cby_12__1__0_chany_top_out ;
+wire [0:0] cby_12__1__0_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__0_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__10_ccff_tail ;
+wire [0:29] cby_12__1__10_chany_bottom_out ;
+wire [0:29] cby_12__1__10_chany_top_out ;
+wire [0:0] cby_12__1__10_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__10_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__11_ccff_tail ;
+wire [0:29] cby_12__1__11_chany_bottom_out ;
+wire [0:29] cby_12__1__11_chany_top_out ;
+wire [0:0] cby_12__1__11_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__11_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__1_ccff_tail ;
+wire [0:29] cby_12__1__1_chany_bottom_out ;
+wire [0:29] cby_12__1__1_chany_top_out ;
+wire [0:0] cby_12__1__1_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__1_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__2_ccff_tail ;
+wire [0:29] cby_12__1__2_chany_bottom_out ;
+wire [0:29] cby_12__1__2_chany_top_out ;
+wire [0:0] cby_12__1__2_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__2_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__3_ccff_tail ;
+wire [0:29] cby_12__1__3_chany_bottom_out ;
+wire [0:29] cby_12__1__3_chany_top_out ;
+wire [0:0] cby_12__1__3_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__3_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__4_ccff_tail ;
+wire [0:29] cby_12__1__4_chany_bottom_out ;
+wire [0:29] cby_12__1__4_chany_top_out ;
+wire [0:0] cby_12__1__4_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__4_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__5_ccff_tail ;
+wire [0:29] cby_12__1__5_chany_bottom_out ;
+wire [0:29] cby_12__1__5_chany_top_out ;
+wire [0:0] cby_12__1__5_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__5_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__6_ccff_tail ;
+wire [0:29] cby_12__1__6_chany_bottom_out ;
+wire [0:29] cby_12__1__6_chany_top_out ;
+wire [0:0] cby_12__1__6_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__6_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__7_ccff_tail ;
+wire [0:29] cby_12__1__7_chany_bottom_out ;
+wire [0:29] cby_12__1__7_chany_top_out ;
+wire [0:0] cby_12__1__7_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__7_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__8_ccff_tail ;
+wire [0:29] cby_12__1__8_chany_bottom_out ;
+wire [0:29] cby_12__1__8_chany_top_out ;
+wire [0:0] cby_12__1__8_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__8_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__9_ccff_tail ;
+wire [0:29] cby_12__1__9_chany_bottom_out ;
+wire [0:29] cby_12__1__9_chany_top_out ;
+wire [0:0] cby_12__1__9_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__9_right_grid_pin_0_ ;
+wire [0:0] cby_1__1__0_ccff_tail ;
+wire [0:29] cby_1__1__0_chany_bottom_out ;
+wire [0:29] cby_1__1__0_chany_top_out ;
+wire [0:0] cby_1__1__0_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__100_ccff_tail ;
+wire [0:29] cby_1__1__100_chany_bottom_out ;
+wire [0:29] cby_1__1__100_chany_top_out ;
+wire [0:0] cby_1__1__100_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__101_ccff_tail ;
+wire [0:29] cby_1__1__101_chany_bottom_out ;
+wire [0:29] cby_1__1__101_chany_top_out ;
+wire [0:0] cby_1__1__101_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__102_ccff_tail ;
+wire [0:29] cby_1__1__102_chany_bottom_out ;
+wire [0:29] cby_1__1__102_chany_top_out ;
+wire [0:0] cby_1__1__102_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__103_ccff_tail ;
+wire [0:29] cby_1__1__103_chany_bottom_out ;
+wire [0:29] cby_1__1__103_chany_top_out ;
+wire [0:0] cby_1__1__103_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__104_ccff_tail ;
+wire [0:29] cby_1__1__104_chany_bottom_out ;
+wire [0:29] cby_1__1__104_chany_top_out ;
+wire [0:0] cby_1__1__104_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__105_ccff_tail ;
+wire [0:29] cby_1__1__105_chany_bottom_out ;
+wire [0:29] cby_1__1__105_chany_top_out ;
+wire [0:0] cby_1__1__105_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__106_ccff_tail ;
+wire [0:29] cby_1__1__106_chany_bottom_out ;
+wire [0:29] cby_1__1__106_chany_top_out ;
+wire [0:0] cby_1__1__106_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__107_ccff_tail ;
+wire [0:29] cby_1__1__107_chany_bottom_out ;
+wire [0:29] cby_1__1__107_chany_top_out ;
+wire [0:0] cby_1__1__107_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__108_ccff_tail ;
+wire [0:29] cby_1__1__108_chany_bottom_out ;
+wire [0:29] cby_1__1__108_chany_top_out ;
+wire [0:0] cby_1__1__108_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__109_ccff_tail ;
+wire [0:29] cby_1__1__109_chany_bottom_out ;
+wire [0:29] cby_1__1__109_chany_top_out ;
+wire [0:0] cby_1__1__109_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__10_ccff_tail ;
+wire [0:29] cby_1__1__10_chany_bottom_out ;
+wire [0:29] cby_1__1__10_chany_top_out ;
+wire [0:0] cby_1__1__10_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__110_ccff_tail ;
+wire [0:29] cby_1__1__110_chany_bottom_out ;
+wire [0:29] cby_1__1__110_chany_top_out ;
+wire [0:0] cby_1__1__110_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__111_ccff_tail ;
+wire [0:29] cby_1__1__111_chany_bottom_out ;
+wire [0:29] cby_1__1__111_chany_top_out ;
+wire [0:0] cby_1__1__111_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__112_ccff_tail ;
+wire [0:29] cby_1__1__112_chany_bottom_out ;
+wire [0:29] cby_1__1__112_chany_top_out ;
+wire [0:0] cby_1__1__112_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__113_ccff_tail ;
+wire [0:29] cby_1__1__113_chany_bottom_out ;
+wire [0:29] cby_1__1__113_chany_top_out ;
+wire [0:0] cby_1__1__113_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__114_ccff_tail ;
+wire [0:29] cby_1__1__114_chany_bottom_out ;
+wire [0:29] cby_1__1__114_chany_top_out ;
+wire [0:0] cby_1__1__114_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__115_ccff_tail ;
+wire [0:29] cby_1__1__115_chany_bottom_out ;
+wire [0:29] cby_1__1__115_chany_top_out ;
+wire [0:0] cby_1__1__115_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__116_ccff_tail ;
+wire [0:29] cby_1__1__116_chany_bottom_out ;
+wire [0:29] cby_1__1__116_chany_top_out ;
+wire [0:0] cby_1__1__116_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__117_ccff_tail ;
+wire [0:29] cby_1__1__117_chany_bottom_out ;
+wire [0:29] cby_1__1__117_chany_top_out ;
+wire [0:0] cby_1__1__117_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__118_ccff_tail ;
+wire [0:29] cby_1__1__118_chany_bottom_out ;
+wire [0:29] cby_1__1__118_chany_top_out ;
+wire [0:0] cby_1__1__118_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__119_ccff_tail ;
+wire [0:29] cby_1__1__119_chany_bottom_out ;
+wire [0:29] cby_1__1__119_chany_top_out ;
+wire [0:0] cby_1__1__119_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__11_ccff_tail ;
+wire [0:29] cby_1__1__11_chany_bottom_out ;
+wire [0:29] cby_1__1__11_chany_top_out ;
+wire [0:0] cby_1__1__11_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__120_ccff_tail ;
+wire [0:29] cby_1__1__120_chany_bottom_out ;
+wire [0:29] cby_1__1__120_chany_top_out ;
+wire [0:0] cby_1__1__120_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__121_ccff_tail ;
+wire [0:29] cby_1__1__121_chany_bottom_out ;
+wire [0:29] cby_1__1__121_chany_top_out ;
+wire [0:0] cby_1__1__121_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__122_ccff_tail ;
+wire [0:29] cby_1__1__122_chany_bottom_out ;
+wire [0:29] cby_1__1__122_chany_top_out ;
+wire [0:0] cby_1__1__122_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__123_ccff_tail ;
+wire [0:29] cby_1__1__123_chany_bottom_out ;
+wire [0:29] cby_1__1__123_chany_top_out ;
+wire [0:0] cby_1__1__123_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__124_ccff_tail ;
+wire [0:29] cby_1__1__124_chany_bottom_out ;
+wire [0:29] cby_1__1__124_chany_top_out ;
+wire [0:0] cby_1__1__124_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__125_ccff_tail ;
+wire [0:29] cby_1__1__125_chany_bottom_out ;
+wire [0:29] cby_1__1__125_chany_top_out ;
+wire [0:0] cby_1__1__125_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__126_ccff_tail ;
+wire [0:29] cby_1__1__126_chany_bottom_out ;
+wire [0:29] cby_1__1__126_chany_top_out ;
+wire [0:0] cby_1__1__126_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__127_ccff_tail ;
+wire [0:29] cby_1__1__127_chany_bottom_out ;
+wire [0:29] cby_1__1__127_chany_top_out ;
+wire [0:0] cby_1__1__127_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__128_ccff_tail ;
+wire [0:29] cby_1__1__128_chany_bottom_out ;
+wire [0:29] cby_1__1__128_chany_top_out ;
+wire [0:0] cby_1__1__128_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__129_ccff_tail ;
+wire [0:29] cby_1__1__129_chany_bottom_out ;
+wire [0:29] cby_1__1__129_chany_top_out ;
+wire [0:0] cby_1__1__129_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__12_ccff_tail ;
+wire [0:29] cby_1__1__12_chany_bottom_out ;
+wire [0:29] cby_1__1__12_chany_top_out ;
+wire [0:0] cby_1__1__12_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__130_ccff_tail ;
+wire [0:29] cby_1__1__130_chany_bottom_out ;
+wire [0:29] cby_1__1__130_chany_top_out ;
+wire [0:0] cby_1__1__130_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__131_ccff_tail ;
+wire [0:29] cby_1__1__131_chany_bottom_out ;
+wire [0:29] cby_1__1__131_chany_top_out ;
+wire [0:0] cby_1__1__131_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__13_ccff_tail ;
+wire [0:29] cby_1__1__13_chany_bottom_out ;
+wire [0:29] cby_1__1__13_chany_top_out ;
+wire [0:0] cby_1__1__13_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__14_ccff_tail ;
+wire [0:29] cby_1__1__14_chany_bottom_out ;
+wire [0:29] cby_1__1__14_chany_top_out ;
+wire [0:0] cby_1__1__14_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__15_ccff_tail ;
+wire [0:29] cby_1__1__15_chany_bottom_out ;
+wire [0:29] cby_1__1__15_chany_top_out ;
+wire [0:0] cby_1__1__15_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__16_ccff_tail ;
+wire [0:29] cby_1__1__16_chany_bottom_out ;
+wire [0:29] cby_1__1__16_chany_top_out ;
+wire [0:0] cby_1__1__16_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__17_ccff_tail ;
+wire [0:29] cby_1__1__17_chany_bottom_out ;
+wire [0:29] cby_1__1__17_chany_top_out ;
+wire [0:0] cby_1__1__17_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__18_ccff_tail ;
+wire [0:29] cby_1__1__18_chany_bottom_out ;
+wire [0:29] cby_1__1__18_chany_top_out ;
+wire [0:0] cby_1__1__18_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__19_ccff_tail ;
+wire [0:29] cby_1__1__19_chany_bottom_out ;
+wire [0:29] cby_1__1__19_chany_top_out ;
+wire [0:0] cby_1__1__19_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__1_ccff_tail ;
+wire [0:29] cby_1__1__1_chany_bottom_out ;
+wire [0:29] cby_1__1__1_chany_top_out ;
+wire [0:0] cby_1__1__1_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__20_ccff_tail ;
+wire [0:29] cby_1__1__20_chany_bottom_out ;
+wire [0:29] cby_1__1__20_chany_top_out ;
+wire [0:0] cby_1__1__20_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__21_ccff_tail ;
+wire [0:29] cby_1__1__21_chany_bottom_out ;
+wire [0:29] cby_1__1__21_chany_top_out ;
+wire [0:0] cby_1__1__21_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__22_ccff_tail ;
+wire [0:29] cby_1__1__22_chany_bottom_out ;
+wire [0:29] cby_1__1__22_chany_top_out ;
+wire [0:0] cby_1__1__22_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__23_ccff_tail ;
+wire [0:29] cby_1__1__23_chany_bottom_out ;
+wire [0:29] cby_1__1__23_chany_top_out ;
+wire [0:0] cby_1__1__23_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__24_ccff_tail ;
+wire [0:29] cby_1__1__24_chany_bottom_out ;
+wire [0:29] cby_1__1__24_chany_top_out ;
+wire [0:0] cby_1__1__24_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__25_ccff_tail ;
+wire [0:29] cby_1__1__25_chany_bottom_out ;
+wire [0:29] cby_1__1__25_chany_top_out ;
+wire [0:0] cby_1__1__25_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__26_ccff_tail ;
+wire [0:29] cby_1__1__26_chany_bottom_out ;
+wire [0:29] cby_1__1__26_chany_top_out ;
+wire [0:0] cby_1__1__26_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__27_ccff_tail ;
+wire [0:29] cby_1__1__27_chany_bottom_out ;
+wire [0:29] cby_1__1__27_chany_top_out ;
+wire [0:0] cby_1__1__27_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__28_ccff_tail ;
+wire [0:29] cby_1__1__28_chany_bottom_out ;
+wire [0:29] cby_1__1__28_chany_top_out ;
+wire [0:0] cby_1__1__28_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__29_ccff_tail ;
+wire [0:29] cby_1__1__29_chany_bottom_out ;
+wire [0:29] cby_1__1__29_chany_top_out ;
+wire [0:0] cby_1__1__29_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__2_ccff_tail ;
+wire [0:29] cby_1__1__2_chany_bottom_out ;
+wire [0:29] cby_1__1__2_chany_top_out ;
+wire [0:0] cby_1__1__2_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__30_ccff_tail ;
+wire [0:29] cby_1__1__30_chany_bottom_out ;
+wire [0:29] cby_1__1__30_chany_top_out ;
+wire [0:0] cby_1__1__30_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__31_ccff_tail ;
+wire [0:29] cby_1__1__31_chany_bottom_out ;
+wire [0:29] cby_1__1__31_chany_top_out ;
+wire [0:0] cby_1__1__31_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__32_ccff_tail ;
+wire [0:29] cby_1__1__32_chany_bottom_out ;
+wire [0:29] cby_1__1__32_chany_top_out ;
+wire [0:0] cby_1__1__32_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__33_ccff_tail ;
+wire [0:29] cby_1__1__33_chany_bottom_out ;
+wire [0:29] cby_1__1__33_chany_top_out ;
+wire [0:0] cby_1__1__33_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__34_ccff_tail ;
+wire [0:29] cby_1__1__34_chany_bottom_out ;
+wire [0:29] cby_1__1__34_chany_top_out ;
+wire [0:0] cby_1__1__34_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__35_ccff_tail ;
+wire [0:29] cby_1__1__35_chany_bottom_out ;
+wire [0:29] cby_1__1__35_chany_top_out ;
+wire [0:0] cby_1__1__35_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__36_ccff_tail ;
+wire [0:29] cby_1__1__36_chany_bottom_out ;
+wire [0:29] cby_1__1__36_chany_top_out ;
+wire [0:0] cby_1__1__36_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__37_ccff_tail ;
+wire [0:29] cby_1__1__37_chany_bottom_out ;
+wire [0:29] cby_1__1__37_chany_top_out ;
+wire [0:0] cby_1__1__37_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__38_ccff_tail ;
+wire [0:29] cby_1__1__38_chany_bottom_out ;
+wire [0:29] cby_1__1__38_chany_top_out ;
+wire [0:0] cby_1__1__38_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__39_ccff_tail ;
+wire [0:29] cby_1__1__39_chany_bottom_out ;
+wire [0:29] cby_1__1__39_chany_top_out ;
+wire [0:0] cby_1__1__39_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__3_ccff_tail ;
+wire [0:29] cby_1__1__3_chany_bottom_out ;
+wire [0:29] cby_1__1__3_chany_top_out ;
+wire [0:0] cby_1__1__3_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__40_ccff_tail ;
+wire [0:29] cby_1__1__40_chany_bottom_out ;
+wire [0:29] cby_1__1__40_chany_top_out ;
+wire [0:0] cby_1__1__40_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__41_ccff_tail ;
+wire [0:29] cby_1__1__41_chany_bottom_out ;
+wire [0:29] cby_1__1__41_chany_top_out ;
+wire [0:0] cby_1__1__41_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__42_ccff_tail ;
+wire [0:29] cby_1__1__42_chany_bottom_out ;
+wire [0:29] cby_1__1__42_chany_top_out ;
+wire [0:0] cby_1__1__42_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__43_ccff_tail ;
+wire [0:29] cby_1__1__43_chany_bottom_out ;
+wire [0:29] cby_1__1__43_chany_top_out ;
+wire [0:0] cby_1__1__43_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__44_ccff_tail ;
+wire [0:29] cby_1__1__44_chany_bottom_out ;
+wire [0:29] cby_1__1__44_chany_top_out ;
+wire [0:0] cby_1__1__44_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__45_ccff_tail ;
+wire [0:29] cby_1__1__45_chany_bottom_out ;
+wire [0:29] cby_1__1__45_chany_top_out ;
+wire [0:0] cby_1__1__45_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__46_ccff_tail ;
+wire [0:29] cby_1__1__46_chany_bottom_out ;
+wire [0:29] cby_1__1__46_chany_top_out ;
+wire [0:0] cby_1__1__46_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__47_ccff_tail ;
+wire [0:29] cby_1__1__47_chany_bottom_out ;
+wire [0:29] cby_1__1__47_chany_top_out ;
+wire [0:0] cby_1__1__47_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__48_ccff_tail ;
+wire [0:29] cby_1__1__48_chany_bottom_out ;
+wire [0:29] cby_1__1__48_chany_top_out ;
+wire [0:0] cby_1__1__48_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__49_ccff_tail ;
+wire [0:29] cby_1__1__49_chany_bottom_out ;
+wire [0:29] cby_1__1__49_chany_top_out ;
+wire [0:0] cby_1__1__49_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__4_ccff_tail ;
+wire [0:29] cby_1__1__4_chany_bottom_out ;
+wire [0:29] cby_1__1__4_chany_top_out ;
+wire [0:0] cby_1__1__4_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__50_ccff_tail ;
+wire [0:29] cby_1__1__50_chany_bottom_out ;
+wire [0:29] cby_1__1__50_chany_top_out ;
+wire [0:0] cby_1__1__50_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__51_ccff_tail ;
+wire [0:29] cby_1__1__51_chany_bottom_out ;
+wire [0:29] cby_1__1__51_chany_top_out ;
+wire [0:0] cby_1__1__51_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__52_ccff_tail ;
+wire [0:29] cby_1__1__52_chany_bottom_out ;
+wire [0:29] cby_1__1__52_chany_top_out ;
+wire [0:0] cby_1__1__52_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__53_ccff_tail ;
+wire [0:29] cby_1__1__53_chany_bottom_out ;
+wire [0:29] cby_1__1__53_chany_top_out ;
+wire [0:0] cby_1__1__53_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__54_ccff_tail ;
+wire [0:29] cby_1__1__54_chany_bottom_out ;
+wire [0:29] cby_1__1__54_chany_top_out ;
+wire [0:0] cby_1__1__54_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__55_ccff_tail ;
+wire [0:29] cby_1__1__55_chany_bottom_out ;
+wire [0:29] cby_1__1__55_chany_top_out ;
+wire [0:0] cby_1__1__55_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__56_ccff_tail ;
+wire [0:29] cby_1__1__56_chany_bottom_out ;
+wire [0:29] cby_1__1__56_chany_top_out ;
+wire [0:0] cby_1__1__56_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__57_ccff_tail ;
+wire [0:29] cby_1__1__57_chany_bottom_out ;
+wire [0:29] cby_1__1__57_chany_top_out ;
+wire [0:0] cby_1__1__57_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__58_ccff_tail ;
+wire [0:29] cby_1__1__58_chany_bottom_out ;
+wire [0:29] cby_1__1__58_chany_top_out ;
+wire [0:0] cby_1__1__58_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__59_ccff_tail ;
+wire [0:29] cby_1__1__59_chany_bottom_out ;
+wire [0:29] cby_1__1__59_chany_top_out ;
+wire [0:0] cby_1__1__59_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__5_ccff_tail ;
+wire [0:29] cby_1__1__5_chany_bottom_out ;
+wire [0:29] cby_1__1__5_chany_top_out ;
+wire [0:0] cby_1__1__5_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__60_ccff_tail ;
+wire [0:29] cby_1__1__60_chany_bottom_out ;
+wire [0:29] cby_1__1__60_chany_top_out ;
+wire [0:0] cby_1__1__60_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__61_ccff_tail ;
+wire [0:29] cby_1__1__61_chany_bottom_out ;
+wire [0:29] cby_1__1__61_chany_top_out ;
+wire [0:0] cby_1__1__61_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__62_ccff_tail ;
+wire [0:29] cby_1__1__62_chany_bottom_out ;
+wire [0:29] cby_1__1__62_chany_top_out ;
+wire [0:0] cby_1__1__62_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__63_ccff_tail ;
+wire [0:29] cby_1__1__63_chany_bottom_out ;
+wire [0:29] cby_1__1__63_chany_top_out ;
+wire [0:0] cby_1__1__63_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__64_ccff_tail ;
+wire [0:29] cby_1__1__64_chany_bottom_out ;
+wire [0:29] cby_1__1__64_chany_top_out ;
+wire [0:0] cby_1__1__64_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__65_ccff_tail ;
+wire [0:29] cby_1__1__65_chany_bottom_out ;
+wire [0:29] cby_1__1__65_chany_top_out ;
+wire [0:0] cby_1__1__65_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__66_ccff_tail ;
+wire [0:29] cby_1__1__66_chany_bottom_out ;
+wire [0:29] cby_1__1__66_chany_top_out ;
+wire [0:0] cby_1__1__66_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__67_ccff_tail ;
+wire [0:29] cby_1__1__67_chany_bottom_out ;
+wire [0:29] cby_1__1__67_chany_top_out ;
+wire [0:0] cby_1__1__67_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__68_ccff_tail ;
+wire [0:29] cby_1__1__68_chany_bottom_out ;
+wire [0:29] cby_1__1__68_chany_top_out ;
+wire [0:0] cby_1__1__68_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__69_ccff_tail ;
+wire [0:29] cby_1__1__69_chany_bottom_out ;
+wire [0:29] cby_1__1__69_chany_top_out ;
+wire [0:0] cby_1__1__69_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__6_ccff_tail ;
+wire [0:29] cby_1__1__6_chany_bottom_out ;
+wire [0:29] cby_1__1__6_chany_top_out ;
+wire [0:0] cby_1__1__6_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__70_ccff_tail ;
+wire [0:29] cby_1__1__70_chany_bottom_out ;
+wire [0:29] cby_1__1__70_chany_top_out ;
+wire [0:0] cby_1__1__70_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__71_ccff_tail ;
+wire [0:29] cby_1__1__71_chany_bottom_out ;
+wire [0:29] cby_1__1__71_chany_top_out ;
+wire [0:0] cby_1__1__71_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__72_ccff_tail ;
+wire [0:29] cby_1__1__72_chany_bottom_out ;
+wire [0:29] cby_1__1__72_chany_top_out ;
+wire [0:0] cby_1__1__72_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__73_ccff_tail ;
+wire [0:29] cby_1__1__73_chany_bottom_out ;
+wire [0:29] cby_1__1__73_chany_top_out ;
+wire [0:0] cby_1__1__73_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__74_ccff_tail ;
+wire [0:29] cby_1__1__74_chany_bottom_out ;
+wire [0:29] cby_1__1__74_chany_top_out ;
+wire [0:0] cby_1__1__74_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__75_ccff_tail ;
+wire [0:29] cby_1__1__75_chany_bottom_out ;
+wire [0:29] cby_1__1__75_chany_top_out ;
+wire [0:0] cby_1__1__75_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__76_ccff_tail ;
+wire [0:29] cby_1__1__76_chany_bottom_out ;
+wire [0:29] cby_1__1__76_chany_top_out ;
+wire [0:0] cby_1__1__76_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__77_ccff_tail ;
+wire [0:29] cby_1__1__77_chany_bottom_out ;
+wire [0:29] cby_1__1__77_chany_top_out ;
+wire [0:0] cby_1__1__77_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__78_ccff_tail ;
+wire [0:29] cby_1__1__78_chany_bottom_out ;
+wire [0:29] cby_1__1__78_chany_top_out ;
+wire [0:0] cby_1__1__78_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__79_ccff_tail ;
+wire [0:29] cby_1__1__79_chany_bottom_out ;
+wire [0:29] cby_1__1__79_chany_top_out ;
+wire [0:0] cby_1__1__79_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__7_ccff_tail ;
+wire [0:29] cby_1__1__7_chany_bottom_out ;
+wire [0:29] cby_1__1__7_chany_top_out ;
+wire [0:0] cby_1__1__7_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__80_ccff_tail ;
+wire [0:29] cby_1__1__80_chany_bottom_out ;
+wire [0:29] cby_1__1__80_chany_top_out ;
+wire [0:0] cby_1__1__80_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__81_ccff_tail ;
+wire [0:29] cby_1__1__81_chany_bottom_out ;
+wire [0:29] cby_1__1__81_chany_top_out ;
+wire [0:0] cby_1__1__81_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__82_ccff_tail ;
+wire [0:29] cby_1__1__82_chany_bottom_out ;
+wire [0:29] cby_1__1__82_chany_top_out ;
+wire [0:0] cby_1__1__82_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__83_ccff_tail ;
+wire [0:29] cby_1__1__83_chany_bottom_out ;
+wire [0:29] cby_1__1__83_chany_top_out ;
+wire [0:0] cby_1__1__83_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__84_ccff_tail ;
+wire [0:29] cby_1__1__84_chany_bottom_out ;
+wire [0:29] cby_1__1__84_chany_top_out ;
+wire [0:0] cby_1__1__84_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__85_ccff_tail ;
+wire [0:29] cby_1__1__85_chany_bottom_out ;
+wire [0:29] cby_1__1__85_chany_top_out ;
+wire [0:0] cby_1__1__85_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__86_ccff_tail ;
+wire [0:29] cby_1__1__86_chany_bottom_out ;
+wire [0:29] cby_1__1__86_chany_top_out ;
+wire [0:0] cby_1__1__86_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__87_ccff_tail ;
+wire [0:29] cby_1__1__87_chany_bottom_out ;
+wire [0:29] cby_1__1__87_chany_top_out ;
+wire [0:0] cby_1__1__87_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__88_ccff_tail ;
+wire [0:29] cby_1__1__88_chany_bottom_out ;
+wire [0:29] cby_1__1__88_chany_top_out ;
+wire [0:0] cby_1__1__88_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__89_ccff_tail ;
+wire [0:29] cby_1__1__89_chany_bottom_out ;
+wire [0:29] cby_1__1__89_chany_top_out ;
+wire [0:0] cby_1__1__89_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__8_ccff_tail ;
+wire [0:29] cby_1__1__8_chany_bottom_out ;
+wire [0:29] cby_1__1__8_chany_top_out ;
+wire [0:0] cby_1__1__8_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__90_ccff_tail ;
+wire [0:29] cby_1__1__90_chany_bottom_out ;
+wire [0:29] cby_1__1__90_chany_top_out ;
+wire [0:0] cby_1__1__90_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__91_ccff_tail ;
+wire [0:29] cby_1__1__91_chany_bottom_out ;
+wire [0:29] cby_1__1__91_chany_top_out ;
+wire [0:0] cby_1__1__91_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__92_ccff_tail ;
+wire [0:29] cby_1__1__92_chany_bottom_out ;
+wire [0:29] cby_1__1__92_chany_top_out ;
+wire [0:0] cby_1__1__92_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__93_ccff_tail ;
+wire [0:29] cby_1__1__93_chany_bottom_out ;
+wire [0:29] cby_1__1__93_chany_top_out ;
+wire [0:0] cby_1__1__93_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__94_ccff_tail ;
+wire [0:29] cby_1__1__94_chany_bottom_out ;
+wire [0:29] cby_1__1__94_chany_top_out ;
+wire [0:0] cby_1__1__94_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__95_ccff_tail ;
+wire [0:29] cby_1__1__95_chany_bottom_out ;
+wire [0:29] cby_1__1__95_chany_top_out ;
+wire [0:0] cby_1__1__95_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__96_ccff_tail ;
+wire [0:29] cby_1__1__96_chany_bottom_out ;
+wire [0:29] cby_1__1__96_chany_top_out ;
+wire [0:0] cby_1__1__96_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__97_ccff_tail ;
+wire [0:29] cby_1__1__97_chany_bottom_out ;
+wire [0:29] cby_1__1__97_chany_top_out ;
+wire [0:0] cby_1__1__97_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__98_ccff_tail ;
+wire [0:29] cby_1__1__98_chany_bottom_out ;
+wire [0:29] cby_1__1__98_chany_top_out ;
+wire [0:0] cby_1__1__98_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__99_ccff_tail ;
+wire [0:29] cby_1__1__99_chany_bottom_out ;
+wire [0:29] cby_1__1__99_chany_top_out ;
+wire [0:0] cby_1__1__99_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__9_ccff_tail ;
+wire [0:29] cby_1__1__9_chany_bottom_out ;
+wire [0:29] cby_1__1__9_chany_top_out ;
+wire [0:0] cby_1__1__9_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_31_ ;
+wire [0:0] direct_interc_0_out ;
+wire [0:0] direct_interc_100_out ;
+wire [0:0] direct_interc_101_out ;
+wire [0:0] direct_interc_102_out ;
+wire [0:0] direct_interc_103_out ;
+wire [0:0] direct_interc_104_out ;
+wire [0:0] direct_interc_105_out ;
+wire [0:0] direct_interc_106_out ;
+wire [0:0] direct_interc_107_out ;
+wire [0:0] direct_interc_108_out ;
+wire [0:0] direct_interc_109_out ;
+wire [0:0] direct_interc_10_out ;
+wire [0:0] direct_interc_110_out ;
+wire [0:0] direct_interc_111_out ;
+wire [0:0] direct_interc_112_out ;
+wire [0:0] direct_interc_113_out ;
+wire [0:0] direct_interc_114_out ;
+wire [0:0] direct_interc_115_out ;
+wire [0:0] direct_interc_116_out ;
+wire [0:0] direct_interc_117_out ;
+wire [0:0] direct_interc_118_out ;
+wire [0:0] direct_interc_119_out ;
+wire [0:0] direct_interc_11_out ;
+wire [0:0] direct_interc_120_out ;
+wire [0:0] direct_interc_121_out ;
+wire [0:0] direct_interc_122_out ;
+wire [0:0] direct_interc_123_out ;
+wire [0:0] direct_interc_124_out ;
+wire [0:0] direct_interc_125_out ;
+wire [0:0] direct_interc_126_out ;
+wire [0:0] direct_interc_127_out ;
+wire [0:0] direct_interc_128_out ;
+wire [0:0] direct_interc_129_out ;
+wire [0:0] direct_interc_12_out ;
+wire [0:0] direct_interc_130_out ;
+wire [0:0] direct_interc_131_out ;
+wire [0:0] direct_interc_132_out ;
+wire [0:0] direct_interc_133_out ;
+wire [0:0] direct_interc_134_out ;
+wire [0:0] direct_interc_135_out ;
+wire [0:0] direct_interc_136_out ;
+wire [0:0] direct_interc_137_out ;
+wire [0:0] direct_interc_138_out ;
+wire [0:0] direct_interc_139_out ;
+wire [0:0] direct_interc_13_out ;
+wire [0:0] direct_interc_140_out ;
+wire [0:0] direct_interc_141_out ;
+wire [0:0] direct_interc_142_out ;
+wire [0:0] direct_interc_143_out ;
+wire [0:0] direct_interc_144_out ;
+wire [0:0] direct_interc_145_out ;
+wire [0:0] direct_interc_146_out ;
+wire [0:0] direct_interc_147_out ;
+wire [0:0] direct_interc_148_out ;
+wire [0:0] direct_interc_149_out ;
+wire [0:0] direct_interc_14_out ;
+wire [0:0] direct_interc_150_out ;
+wire [0:0] direct_interc_151_out ;
+wire [0:0] direct_interc_152_out ;
+wire [0:0] direct_interc_153_out ;
+wire [0:0] direct_interc_154_out ;
+wire [0:0] direct_interc_155_out ;
+wire [0:0] direct_interc_156_out ;
+wire [0:0] direct_interc_157_out ;
+wire [0:0] direct_interc_158_out ;
+wire [0:0] direct_interc_159_out ;
+wire [0:0] direct_interc_15_out ;
+wire [0:0] direct_interc_160_out ;
+wire [0:0] direct_interc_161_out ;
+wire [0:0] direct_interc_162_out ;
+wire [0:0] direct_interc_163_out ;
+wire [0:0] direct_interc_164_out ;
+wire [0:0] direct_interc_165_out ;
+wire [0:0] direct_interc_166_out ;
+wire [0:0] direct_interc_167_out ;
+wire [0:0] direct_interc_168_out ;
+wire [0:0] direct_interc_169_out ;
+wire [0:0] direct_interc_16_out ;
+wire [0:0] direct_interc_170_out ;
+wire [0:0] direct_interc_171_out ;
+wire [0:0] direct_interc_172_out ;
+wire [0:0] direct_interc_173_out ;
+wire [0:0] direct_interc_174_out ;
+wire [0:0] direct_interc_175_out ;
+wire [0:0] direct_interc_176_out ;
+wire [0:0] direct_interc_177_out ;
+wire [0:0] direct_interc_178_out ;
+wire [0:0] direct_interc_179_out ;
+wire [0:0] direct_interc_17_out ;
+wire [0:0] direct_interc_180_out ;
+wire [0:0] direct_interc_181_out ;
+wire [0:0] direct_interc_182_out ;
+wire [0:0] direct_interc_183_out ;
+wire [0:0] direct_interc_184_out ;
+wire [0:0] direct_interc_185_out ;
+wire [0:0] direct_interc_186_out ;
+wire [0:0] direct_interc_187_out ;
+wire [0:0] direct_interc_188_out ;
+wire [0:0] direct_interc_189_out ;
+wire [0:0] direct_interc_18_out ;
+wire [0:0] direct_interc_190_out ;
+wire [0:0] direct_interc_191_out ;
+wire [0:0] direct_interc_192_out ;
+wire [0:0] direct_interc_193_out ;
+wire [0:0] direct_interc_194_out ;
+wire [0:0] direct_interc_195_out ;
+wire [0:0] direct_interc_196_out ;
+wire [0:0] direct_interc_197_out ;
+wire [0:0] direct_interc_198_out ;
+wire [0:0] direct_interc_199_out ;
+wire [0:0] direct_interc_19_out ;
+wire [0:0] direct_interc_1_out ;
+wire [0:0] direct_interc_200_out ;
+wire [0:0] direct_interc_201_out ;
+wire [0:0] direct_interc_202_out ;
+wire [0:0] direct_interc_203_out ;
+wire [0:0] direct_interc_204_out ;
+wire [0:0] direct_interc_205_out ;
+wire [0:0] direct_interc_206_out ;
+wire [0:0] direct_interc_207_out ;
+wire [0:0] direct_interc_208_out ;
+wire [0:0] direct_interc_209_out ;
+wire [0:0] direct_interc_20_out ;
+wire [0:0] direct_interc_210_out ;
+wire [0:0] direct_interc_211_out ;
+wire [0:0] direct_interc_212_out ;
+wire [0:0] direct_interc_213_out ;
+wire [0:0] direct_interc_214_out ;
+wire [0:0] direct_interc_215_out ;
+wire [0:0] direct_interc_216_out ;
+wire [0:0] direct_interc_217_out ;
+wire [0:0] direct_interc_218_out ;
+wire [0:0] direct_interc_219_out ;
+wire [0:0] direct_interc_21_out ;
+wire [0:0] direct_interc_220_out ;
+wire [0:0] direct_interc_221_out ;
+wire [0:0] direct_interc_222_out ;
+wire [0:0] direct_interc_223_out ;
+wire [0:0] direct_interc_224_out ;
+wire [0:0] direct_interc_225_out ;
+wire [0:0] direct_interc_226_out ;
+wire [0:0] direct_interc_227_out ;
+wire [0:0] direct_interc_228_out ;
+wire [0:0] direct_interc_229_out ;
+wire [0:0] direct_interc_22_out ;
+wire [0:0] direct_interc_230_out ;
+wire [0:0] direct_interc_231_out ;
+wire [0:0] direct_interc_232_out ;
+wire [0:0] direct_interc_233_out ;
+wire [0:0] direct_interc_234_out ;
+wire [0:0] direct_interc_235_out ;
+wire [0:0] direct_interc_236_out ;
+wire [0:0] direct_interc_237_out ;
+wire [0:0] direct_interc_238_out ;
+wire [0:0] direct_interc_239_out ;
+wire [0:0] direct_interc_23_out ;
+wire [0:0] direct_interc_240_out ;
+wire [0:0] direct_interc_241_out ;
+wire [0:0] direct_interc_242_out ;
+wire [0:0] direct_interc_243_out ;
+wire [0:0] direct_interc_244_out ;
+wire [0:0] direct_interc_245_out ;
+wire [0:0] direct_interc_246_out ;
+wire [0:0] direct_interc_247_out ;
+wire [0:0] direct_interc_248_out ;
+wire [0:0] direct_interc_249_out ;
+wire [0:0] direct_interc_24_out ;
+wire [0:0] direct_interc_250_out ;
+wire [0:0] direct_interc_251_out ;
+wire [0:0] direct_interc_252_out ;
+wire [0:0] direct_interc_253_out ;
+wire [0:0] direct_interc_254_out ;
+wire [0:0] direct_interc_255_out ;
+wire [0:0] direct_interc_256_out ;
+wire [0:0] direct_interc_257_out ;
+wire [0:0] direct_interc_258_out ;
+wire [0:0] direct_interc_259_out ;
+wire [0:0] direct_interc_25_out ;
+wire [0:0] direct_interc_260_out ;
+wire [0:0] direct_interc_261_out ;
+wire [0:0] direct_interc_262_out ;
+wire [0:0] direct_interc_263_out ;
+wire [0:0] direct_interc_264_out ;
+wire [0:0] direct_interc_265_out ;
+wire [0:0] direct_interc_266_out ;
+wire [0:0] direct_interc_267_out ;
+wire [0:0] direct_interc_268_out ;
+wire [0:0] direct_interc_269_out ;
+wire [0:0] direct_interc_26_out ;
+wire [0:0] direct_interc_270_out ;
+wire [0:0] direct_interc_271_out ;
+wire [0:0] direct_interc_272_out ;
+wire [0:0] direct_interc_273_out ;
+wire [0:0] direct_interc_274_out ;
+wire [0:0] direct_interc_275_out ;
+wire [0:0] direct_interc_276_out ;
+wire [0:0] direct_interc_277_out ;
+wire [0:0] direct_interc_278_out ;
+wire [0:0] direct_interc_279_out ;
+wire [0:0] direct_interc_27_out ;
+wire [0:0] direct_interc_280_out ;
+wire [0:0] direct_interc_281_out ;
+wire [0:0] direct_interc_282_out ;
+wire [0:0] direct_interc_283_out ;
+wire [0:0] direct_interc_284_out ;
+wire [0:0] direct_interc_285_out ;
+wire [0:0] direct_interc_286_out ;
+wire [0:0] direct_interc_287_out ;
+wire [0:0] direct_interc_288_out ;
+wire [0:0] direct_interc_289_out ;
+wire [0:0] direct_interc_28_out ;
+wire [0:0] direct_interc_290_out ;
+wire [0:0] direct_interc_291_out ;
+wire [0:0] direct_interc_292_out ;
+wire [0:0] direct_interc_293_out ;
+wire [0:0] direct_interc_294_out ;
+wire [0:0] direct_interc_295_out ;
+wire [0:0] direct_interc_296_out ;
+wire [0:0] direct_interc_297_out ;
+wire [0:0] direct_interc_298_out ;
+wire [0:0] direct_interc_299_out ;
+wire [0:0] direct_interc_29_out ;
+wire [0:0] direct_interc_2_out ;
+wire [0:0] direct_interc_300_out ;
+wire [0:0] direct_interc_301_out ;
+wire [0:0] direct_interc_302_out ;
+wire [0:0] direct_interc_303_out ;
+wire [0:0] direct_interc_304_out ;
+wire [0:0] direct_interc_305_out ;
+wire [0:0] direct_interc_306_out ;
+wire [0:0] direct_interc_307_out ;
+wire [0:0] direct_interc_308_out ;
+wire [0:0] direct_interc_309_out ;
+wire [0:0] direct_interc_30_out ;
+wire [0:0] direct_interc_310_out ;
+wire [0:0] direct_interc_311_out ;
+wire [0:0] direct_interc_312_out ;
+wire [0:0] direct_interc_313_out ;
+wire [0:0] direct_interc_314_out ;
+wire [0:0] direct_interc_315_out ;
+wire [0:0] direct_interc_316_out ;
+wire [0:0] direct_interc_317_out ;
+wire [0:0] direct_interc_318_out ;
+wire [0:0] direct_interc_319_out ;
+wire [0:0] direct_interc_31_out ;
+wire [0:0] direct_interc_320_out ;
+wire [0:0] direct_interc_321_out ;
+wire [0:0] direct_interc_322_out ;
+wire [0:0] direct_interc_323_out ;
+wire [0:0] direct_interc_324_out ;
+wire [0:0] direct_interc_325_out ;
+wire [0:0] direct_interc_326_out ;
+wire [0:0] direct_interc_327_out ;
+wire [0:0] direct_interc_328_out ;
+wire [0:0] direct_interc_329_out ;
+wire [0:0] direct_interc_32_out ;
+wire [0:0] direct_interc_330_out ;
+wire [0:0] direct_interc_331_out ;
+wire [0:0] direct_interc_332_out ;
+wire [0:0] direct_interc_333_out ;
+wire [0:0] direct_interc_334_out ;
+wire [0:0] direct_interc_335_out ;
+wire [0:0] direct_interc_336_out ;
+wire [0:0] direct_interc_337_out ;
+wire [0:0] direct_interc_338_out ;
+wire [0:0] direct_interc_339_out ;
+wire [0:0] direct_interc_33_out ;
+wire [0:0] direct_interc_340_out ;
+wire [0:0] direct_interc_341_out ;
+wire [0:0] direct_interc_342_out ;
+wire [0:0] direct_interc_343_out ;
+wire [0:0] direct_interc_344_out ;
+wire [0:0] direct_interc_345_out ;
+wire [0:0] direct_interc_346_out ;
+wire [0:0] direct_interc_347_out ;
+wire [0:0] direct_interc_348_out ;
+wire [0:0] direct_interc_349_out ;
+wire [0:0] direct_interc_34_out ;
+wire [0:0] direct_interc_350_out ;
+wire [0:0] direct_interc_351_out ;
+wire [0:0] direct_interc_352_out ;
+wire [0:0] direct_interc_353_out ;
+wire [0:0] direct_interc_354_out ;
+wire [0:0] direct_interc_355_out ;
+wire [0:0] direct_interc_356_out ;
+wire [0:0] direct_interc_357_out ;
+wire [0:0] direct_interc_358_out ;
+wire [0:0] direct_interc_359_out ;
+wire [0:0] direct_interc_35_out ;
+wire [0:0] direct_interc_360_out ;
+wire [0:0] direct_interc_361_out ;
+wire [0:0] direct_interc_362_out ;
+wire [0:0] direct_interc_363_out ;
+wire [0:0] direct_interc_364_out ;
+wire [0:0] direct_interc_365_out ;
+wire [0:0] direct_interc_366_out ;
+wire [0:0] direct_interc_367_out ;
+wire [0:0] direct_interc_368_out ;
+wire [0:0] direct_interc_369_out ;
+wire [0:0] direct_interc_36_out ;
+wire [0:0] direct_interc_370_out ;
+wire [0:0] direct_interc_371_out ;
+wire [0:0] direct_interc_372_out ;
+wire [0:0] direct_interc_373_out ;
+wire [0:0] direct_interc_374_out ;
+wire [0:0] direct_interc_375_out ;
+wire [0:0] direct_interc_376_out ;
+wire [0:0] direct_interc_377_out ;
+wire [0:0] direct_interc_378_out ;
+wire [0:0] direct_interc_379_out ;
+wire [0:0] direct_interc_37_out ;
+wire [0:0] direct_interc_380_out ;
+wire [0:0] direct_interc_381_out ;
+wire [0:0] direct_interc_382_out ;
+wire [0:0] direct_interc_383_out ;
+wire [0:0] direct_interc_384_out ;
+wire [0:0] direct_interc_385_out ;
+wire [0:0] direct_interc_386_out ;
+wire [0:0] direct_interc_387_out ;
+wire [0:0] direct_interc_388_out ;
+wire [0:0] direct_interc_389_out ;
+wire [0:0] direct_interc_38_out ;
+wire [0:0] direct_interc_390_out ;
+wire [0:0] direct_interc_391_out ;
+wire [0:0] direct_interc_392_out ;
+wire [0:0] direct_interc_393_out ;
+wire [0:0] direct_interc_394_out ;
+wire [0:0] direct_interc_395_out ;
+wire [0:0] direct_interc_396_out ;
+wire [0:0] direct_interc_397_out ;
+wire [0:0] direct_interc_398_out ;
+wire [0:0] direct_interc_399_out ;
+wire [0:0] direct_interc_39_out ;
+wire [0:0] direct_interc_3_out ;
+wire [0:0] direct_interc_400_out ;
+wire [0:0] direct_interc_401_out ;
+wire [0:0] direct_interc_402_out ;
+wire [0:0] direct_interc_403_out ;
+wire [0:0] direct_interc_404_out ;
+wire [0:0] direct_interc_405_out ;
+wire [0:0] direct_interc_406_out ;
+wire [0:0] direct_interc_40_out ;
+wire [0:0] direct_interc_41_out ;
+wire [0:0] direct_interc_42_out ;
+wire [0:0] direct_interc_43_out ;
+wire [0:0] direct_interc_44_out ;
+wire [0:0] direct_interc_45_out ;
+wire [0:0] direct_interc_46_out ;
+wire [0:0] direct_interc_47_out ;
+wire [0:0] direct_interc_48_out ;
+wire [0:0] direct_interc_49_out ;
+wire [0:0] direct_interc_4_out ;
+wire [0:0] direct_interc_50_out ;
+wire [0:0] direct_interc_51_out ;
+wire [0:0] direct_interc_52_out ;
+wire [0:0] direct_interc_53_out ;
+wire [0:0] direct_interc_54_out ;
+wire [0:0] direct_interc_55_out ;
+wire [0:0] direct_interc_56_out ;
+wire [0:0] direct_interc_57_out ;
+wire [0:0] direct_interc_58_out ;
+wire [0:0] direct_interc_59_out ;
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_60_out ;
+wire [0:0] direct_interc_61_out ;
+wire [0:0] direct_interc_62_out ;
+wire [0:0] direct_interc_63_out ;
+wire [0:0] direct_interc_64_out ;
+wire [0:0] direct_interc_65_out ;
+wire [0:0] direct_interc_66_out ;
+wire [0:0] direct_interc_67_out ;
+wire [0:0] direct_interc_68_out ;
+wire [0:0] direct_interc_69_out ;
+wire [0:0] direct_interc_6_out ;
+wire [0:0] direct_interc_70_out ;
+wire [0:0] direct_interc_71_out ;
+wire [0:0] direct_interc_72_out ;
+wire [0:0] direct_interc_73_out ;
+wire [0:0] direct_interc_74_out ;
+wire [0:0] direct_interc_75_out ;
+wire [0:0] direct_interc_76_out ;
+wire [0:0] direct_interc_77_out ;
+wire [0:0] direct_interc_78_out ;
+wire [0:0] direct_interc_79_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] direct_interc_80_out ;
+wire [0:0] direct_interc_81_out ;
+wire [0:0] direct_interc_82_out ;
+wire [0:0] direct_interc_83_out ;
+wire [0:0] direct_interc_84_out ;
+wire [0:0] direct_interc_85_out ;
+wire [0:0] direct_interc_86_out ;
+wire [0:0] direct_interc_87_out ;
+wire [0:0] direct_interc_88_out ;
+wire [0:0] direct_interc_89_out ;
+wire [0:0] direct_interc_8_out ;
+wire [0:0] direct_interc_90_out ;
+wire [0:0] direct_interc_91_out ;
+wire [0:0] direct_interc_92_out ;
+wire [0:0] direct_interc_93_out ;
+wire [0:0] direct_interc_94_out ;
+wire [0:0] direct_interc_95_out ;
+wire [0:0] direct_interc_96_out ;
+wire [0:0] direct_interc_97_out ;
+wire [0:0] direct_interc_98_out ;
+wire [0:0] direct_interc_99_out ;
+wire [0:0] direct_interc_9_out ;
+wire [0:0] grid_clb_0_ccff_tail ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_100_ccff_tail ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_101_ccff_tail ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_102_ccff_tail ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_103_ccff_tail ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_104_ccff_tail ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_105_ccff_tail ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_106_ccff_tail ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_107_ccff_tail ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_108_ccff_tail ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_109_ccff_tail ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_10_ccff_tail ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_110_ccff_tail ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_111_ccff_tail ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_112_ccff_tail ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_113_ccff_tail ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_114_ccff_tail ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_115_ccff_tail ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_116_ccff_tail ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_117_ccff_tail ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_118_ccff_tail ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_119_ccff_tail ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_11_ccff_tail ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_120_ccff_tail ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_121_ccff_tail ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_122_ccff_tail ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_123_ccff_tail ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_124_ccff_tail ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_125_ccff_tail ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_126_ccff_tail ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_127_ccff_tail ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_128_ccff_tail ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_129_ccff_tail ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_53_ ;
+wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_12_ccff_tail ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_130_ccff_tail ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_131_ccff_tail ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_132_ccff_tail ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_133_ccff_tail ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_134_ccff_tail ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_135_ccff_tail ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_136_ccff_tail ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_137_ccff_tail ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_138_ccff_tail ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_139_ccff_tail ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_13_ccff_tail ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_140_ccff_tail ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_141_ccff_tail ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_142_ccff_tail ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_143_ccff_tail ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_14_ccff_tail ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_15_ccff_tail ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_16_ccff_tail ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_17_ccff_tail ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_18_ccff_tail ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_19_ccff_tail ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_33_ ;
+wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_1_ccff_tail ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_20_ccff_tail ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_21_ccff_tail ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_22_ccff_tail ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_23_ccff_tail ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_24_ccff_tail ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_25_ccff_tail ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_26_ccff_tail ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_27_ccff_tail ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_28_ccff_tail ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_29_ccff_tail ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_2_ccff_tail ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_30_ccff_tail ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_31_ccff_tail ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_32_ccff_tail ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_33_ccff_tail ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_34_ccff_tail ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_35_ccff_tail ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_36_ccff_tail ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_37_ccff_tail ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_38_ccff_tail ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_39_ccff_tail ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_3_ccff_tail ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_40_ccff_tail ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_41_ccff_tail ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_42_ccff_tail ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_43_ccff_tail ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_44_ccff_tail ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_45_ccff_tail ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_46_ccff_tail ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_47_ccff_tail ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_48_ccff_tail ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_49_ccff_tail ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_4_ccff_tail ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_50_ccff_tail ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_51_ccff_tail ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_52_ccff_tail ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_53_ccff_tail ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_54_ccff_tail ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_55_ccff_tail ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_56_ccff_tail ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_57_ccff_tail ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_58_ccff_tail ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_59_ccff_tail ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_5_ccff_tail ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_60_ccff_tail ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_61_ccff_tail ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_62_ccff_tail ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_63_ccff_tail ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_64_ccff_tail ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_65_ccff_tail ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_66_ccff_tail ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_67_ccff_tail ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_68_ccff_tail ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_69_ccff_tail ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_6_ccff_tail ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_70_ccff_tail ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_71_ccff_tail ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_72_ccff_tail ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_73_ccff_tail ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_74_ccff_tail ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_75_ccff_tail ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_76_ccff_tail ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_77_ccff_tail ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_78_ccff_tail ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_79_ccff_tail ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_7_ccff_tail ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_80_ccff_tail ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_81_ccff_tail ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_82_ccff_tail ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_83_ccff_tail ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_84_ccff_tail ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_85_ccff_tail ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_86_ccff_tail ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_87_ccff_tail ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_88_ccff_tail ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_89_ccff_tail ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_8_ccff_tail ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_90_ccff_tail ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_91_ccff_tail ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_92_ccff_tail ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_93_ccff_tail ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_94_ccff_tail ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_95_ccff_tail ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_96_ccff_tail ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_97_ccff_tail ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_98_ccff_tail ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_99_ccff_tail ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_9_ccff_tail ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_io_bottom_0_ccff_tail ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_10_ccff_tail ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_11_ccff_tail ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_1_ccff_tail ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_2_ccff_tail ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_3_ccff_tail ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_4_ccff_tail ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_5_ccff_tail ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_6_ccff_tail ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_7_ccff_tail ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_8_ccff_tail ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_9_ccff_tail ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_left_0_ccff_tail ;
+wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_10_ccff_tail ;
+wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_11_ccff_tail ;
+wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_1_ccff_tail ;
+wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_2_ccff_tail ;
+wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_3_ccff_tail ;
+wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_4_ccff_tail ;
+wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_5_ccff_tail ;
+wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_6_ccff_tail ;
+wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_7_ccff_tail ;
+wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_8_ccff_tail ;
+wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_9_ccff_tail ;
+wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_0_ccff_tail ;
+wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_10_ccff_tail ;
+wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_11_ccff_tail ;
+wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_1_ccff_tail ;
+wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_2_ccff_tail ;
+wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_3_ccff_tail ;
+wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_4_ccff_tail ;
+wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_5_ccff_tail ;
+wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_6_ccff_tail ;
+wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_7_ccff_tail ;
+wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_8_ccff_tail ;
+wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_9_ccff_tail ;
+wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_0_ccff_tail ;
+wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_10_ccff_tail ;
+wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_11_ccff_tail ;
+wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_1_ccff_tail ;
+wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_2_ccff_tail ;
+wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_3_ccff_tail ;
+wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_4_ccff_tail ;
+wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_5_ccff_tail ;
+wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_6_ccff_tail ;
+wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_7_ccff_tail ;
+wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_8_ccff_tail ;
+wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_9_ccff_tail ;
+wire [0:29] sb_0__0__0_chanx_right_out ;
+wire [0:29] sb_0__0__0_chany_top_out ;
+wire [0:0] sb_0__12__0_ccff_tail ;
+wire [0:29] sb_0__12__0_chanx_right_out ;
+wire [0:29] sb_0__12__0_chany_bottom_out ;
+wire [0:0] sb_0__1__0_ccff_tail ;
+wire [0:29] sb_0__1__0_chanx_right_out ;
+wire [0:29] sb_0__1__0_chany_bottom_out ;
+wire [0:29] sb_0__1__0_chany_top_out ;
+wire [0:0] sb_0__1__10_ccff_tail ;
+wire [0:29] sb_0__1__10_chanx_right_out ;
+wire [0:29] sb_0__1__10_chany_bottom_out ;
+wire [0:29] sb_0__1__10_chany_top_out ;
+wire [0:0] sb_0__1__1_ccff_tail ;
+wire [0:29] sb_0__1__1_chanx_right_out ;
+wire [0:29] sb_0__1__1_chany_bottom_out ;
+wire [0:29] sb_0__1__1_chany_top_out ;
+wire [0:0] sb_0__1__2_ccff_tail ;
+wire [0:29] sb_0__1__2_chanx_right_out ;
+wire [0:29] sb_0__1__2_chany_bottom_out ;
+wire [0:29] sb_0__1__2_chany_top_out ;
+wire [0:0] sb_0__1__3_ccff_tail ;
+wire [0:29] sb_0__1__3_chanx_right_out ;
+wire [0:29] sb_0__1__3_chany_bottom_out ;
+wire [0:29] sb_0__1__3_chany_top_out ;
+wire [0:0] sb_0__1__4_ccff_tail ;
+wire [0:29] sb_0__1__4_chanx_right_out ;
+wire [0:29] sb_0__1__4_chany_bottom_out ;
+wire [0:29] sb_0__1__4_chany_top_out ;
+wire [0:0] sb_0__1__5_ccff_tail ;
+wire [0:29] sb_0__1__5_chanx_right_out ;
+wire [0:29] sb_0__1__5_chany_bottom_out ;
+wire [0:29] sb_0__1__5_chany_top_out ;
+wire [0:0] sb_0__1__6_ccff_tail ;
+wire [0:29] sb_0__1__6_chanx_right_out ;
+wire [0:29] sb_0__1__6_chany_bottom_out ;
+wire [0:29] sb_0__1__6_chany_top_out ;
+wire [0:0] sb_0__1__7_ccff_tail ;
+wire [0:29] sb_0__1__7_chanx_right_out ;
+wire [0:29] sb_0__1__7_chany_bottom_out ;
+wire [0:29] sb_0__1__7_chany_top_out ;
+wire [0:0] sb_0__1__8_ccff_tail ;
+wire [0:29] sb_0__1__8_chanx_right_out ;
+wire [0:29] sb_0__1__8_chany_bottom_out ;
+wire [0:29] sb_0__1__8_chany_top_out ;
+wire [0:0] sb_0__1__9_ccff_tail ;
+wire [0:29] sb_0__1__9_chanx_right_out ;
+wire [0:29] sb_0__1__9_chany_bottom_out ;
+wire [0:29] sb_0__1__9_chany_top_out ;
+wire [0:0] sb_12__0__0_ccff_tail ;
+wire [0:29] sb_12__0__0_chanx_left_out ;
+wire [0:29] sb_12__0__0_chany_top_out ;
+wire [0:0] sb_12__12__0_ccff_tail ;
+wire [0:29] sb_12__12__0_chanx_left_out ;
+wire [0:29] sb_12__12__0_chany_bottom_out ;
+wire [0:0] sb_12__1__0_ccff_tail ;
+wire [0:29] sb_12__1__0_chanx_left_out ;
+wire [0:29] sb_12__1__0_chany_bottom_out ;
+wire [0:29] sb_12__1__0_chany_top_out ;
+wire [0:0] sb_12__1__10_ccff_tail ;
+wire [0:29] sb_12__1__10_chanx_left_out ;
+wire [0:29] sb_12__1__10_chany_bottom_out ;
+wire [0:29] sb_12__1__10_chany_top_out ;
+wire [0:0] sb_12__1__1_ccff_tail ;
+wire [0:29] sb_12__1__1_chanx_left_out ;
+wire [0:29] sb_12__1__1_chany_bottom_out ;
+wire [0:29] sb_12__1__1_chany_top_out ;
+wire [0:0] sb_12__1__2_ccff_tail ;
+wire [0:29] sb_12__1__2_chanx_left_out ;
+wire [0:29] sb_12__1__2_chany_bottom_out ;
+wire [0:29] sb_12__1__2_chany_top_out ;
+wire [0:0] sb_12__1__3_ccff_tail ;
+wire [0:29] sb_12__1__3_chanx_left_out ;
+wire [0:29] sb_12__1__3_chany_bottom_out ;
+wire [0:29] sb_12__1__3_chany_top_out ;
+wire [0:0] sb_12__1__4_ccff_tail ;
+wire [0:29] sb_12__1__4_chanx_left_out ;
+wire [0:29] sb_12__1__4_chany_bottom_out ;
+wire [0:29] sb_12__1__4_chany_top_out ;
+wire [0:0] sb_12__1__5_ccff_tail ;
+wire [0:29] sb_12__1__5_chanx_left_out ;
+wire [0:29] sb_12__1__5_chany_bottom_out ;
+wire [0:29] sb_12__1__5_chany_top_out ;
+wire [0:0] sb_12__1__6_ccff_tail ;
+wire [0:29] sb_12__1__6_chanx_left_out ;
+wire [0:29] sb_12__1__6_chany_bottom_out ;
+wire [0:29] sb_12__1__6_chany_top_out ;
+wire [0:0] sb_12__1__7_ccff_tail ;
+wire [0:29] sb_12__1__7_chanx_left_out ;
+wire [0:29] sb_12__1__7_chany_bottom_out ;
+wire [0:29] sb_12__1__7_chany_top_out ;
+wire [0:0] sb_12__1__8_ccff_tail ;
+wire [0:29] sb_12__1__8_chanx_left_out ;
+wire [0:29] sb_12__1__8_chany_bottom_out ;
+wire [0:29] sb_12__1__8_chany_top_out ;
+wire [0:0] sb_12__1__9_ccff_tail ;
+wire [0:29] sb_12__1__9_chanx_left_out ;
+wire [0:29] sb_12__1__9_chany_bottom_out ;
+wire [0:29] sb_12__1__9_chany_top_out ;
+wire [0:0] sb_1__0__0_ccff_tail ;
+wire [0:29] sb_1__0__0_chanx_left_out ;
+wire [0:29] sb_1__0__0_chanx_right_out ;
+wire [0:29] sb_1__0__0_chany_top_out ;
+wire [0:0] sb_1__0__10_ccff_tail ;
+wire [0:29] sb_1__0__10_chanx_left_out ;
+wire [0:29] sb_1__0__10_chanx_right_out ;
+wire [0:29] sb_1__0__10_chany_top_out ;
+wire [0:0] sb_1__0__1_ccff_tail ;
+wire [0:29] sb_1__0__1_chanx_left_out ;
+wire [0:29] sb_1__0__1_chanx_right_out ;
+wire [0:29] sb_1__0__1_chany_top_out ;
+wire [0:0] sb_1__0__2_ccff_tail ;
+wire [0:29] sb_1__0__2_chanx_left_out ;
+wire [0:29] sb_1__0__2_chanx_right_out ;
+wire [0:29] sb_1__0__2_chany_top_out ;
+wire [0:0] sb_1__0__3_ccff_tail ;
+wire [0:29] sb_1__0__3_chanx_left_out ;
+wire [0:29] sb_1__0__3_chanx_right_out ;
+wire [0:29] sb_1__0__3_chany_top_out ;
+wire [0:0] sb_1__0__4_ccff_tail ;
+wire [0:29] sb_1__0__4_chanx_left_out ;
+wire [0:29] sb_1__0__4_chanx_right_out ;
+wire [0:29] sb_1__0__4_chany_top_out ;
+wire [0:0] sb_1__0__5_ccff_tail ;
+wire [0:29] sb_1__0__5_chanx_left_out ;
+wire [0:29] sb_1__0__5_chanx_right_out ;
+wire [0:29] sb_1__0__5_chany_top_out ;
+wire [0:0] sb_1__0__6_ccff_tail ;
+wire [0:29] sb_1__0__6_chanx_left_out ;
+wire [0:29] sb_1__0__6_chanx_right_out ;
+wire [0:29] sb_1__0__6_chany_top_out ;
+wire [0:0] sb_1__0__7_ccff_tail ;
+wire [0:29] sb_1__0__7_chanx_left_out ;
+wire [0:29] sb_1__0__7_chanx_right_out ;
+wire [0:29] sb_1__0__7_chany_top_out ;
+wire [0:0] sb_1__0__8_ccff_tail ;
+wire [0:29] sb_1__0__8_chanx_left_out ;
+wire [0:29] sb_1__0__8_chanx_right_out ;
+wire [0:29] sb_1__0__8_chany_top_out ;
+wire [0:0] sb_1__0__9_ccff_tail ;
+wire [0:29] sb_1__0__9_chanx_left_out ;
+wire [0:29] sb_1__0__9_chanx_right_out ;
+wire [0:29] sb_1__0__9_chany_top_out ;
+wire [0:0] sb_1__12__0_ccff_tail ;
+wire [0:29] sb_1__12__0_chanx_left_out ;
+wire [0:29] sb_1__12__0_chanx_right_out ;
+wire [0:29] sb_1__12__0_chany_bottom_out ;
+wire [0:0] sb_1__12__10_ccff_tail ;
+wire [0:29] sb_1__12__10_chanx_left_out ;
+wire [0:29] sb_1__12__10_chanx_right_out ;
+wire [0:29] sb_1__12__10_chany_bottom_out ;
+wire [0:0] sb_1__12__1_ccff_tail ;
+wire [0:29] sb_1__12__1_chanx_left_out ;
+wire [0:29] sb_1__12__1_chanx_right_out ;
+wire [0:29] sb_1__12__1_chany_bottom_out ;
+wire [0:0] sb_1__12__2_ccff_tail ;
+wire [0:29] sb_1__12__2_chanx_left_out ;
+wire [0:29] sb_1__12__2_chanx_right_out ;
+wire [0:29] sb_1__12__2_chany_bottom_out ;
+wire [0:0] sb_1__12__3_ccff_tail ;
+wire [0:29] sb_1__12__3_chanx_left_out ;
+wire [0:29] sb_1__12__3_chanx_right_out ;
+wire [0:29] sb_1__12__3_chany_bottom_out ;
+wire [0:0] sb_1__12__4_ccff_tail ;
+wire [0:29] sb_1__12__4_chanx_left_out ;
+wire [0:29] sb_1__12__4_chanx_right_out ;
+wire [0:29] sb_1__12__4_chany_bottom_out ;
+wire [0:0] sb_1__12__5_ccff_tail ;
+wire [0:29] sb_1__12__5_chanx_left_out ;
+wire [0:29] sb_1__12__5_chanx_right_out ;
+wire [0:29] sb_1__12__5_chany_bottom_out ;
+wire [0:0] sb_1__12__6_ccff_tail ;
+wire [0:29] sb_1__12__6_chanx_left_out ;
+wire [0:29] sb_1__12__6_chanx_right_out ;
+wire [0:29] sb_1__12__6_chany_bottom_out ;
+wire [0:0] sb_1__12__7_ccff_tail ;
+wire [0:29] sb_1__12__7_chanx_left_out ;
+wire [0:29] sb_1__12__7_chanx_right_out ;
+wire [0:29] sb_1__12__7_chany_bottom_out ;
+wire [0:0] sb_1__12__8_ccff_tail ;
+wire [0:29] sb_1__12__8_chanx_left_out ;
+wire [0:29] sb_1__12__8_chanx_right_out ;
+wire [0:29] sb_1__12__8_chany_bottom_out ;
+wire [0:0] sb_1__12__9_ccff_tail ;
+wire [0:29] sb_1__12__9_chanx_left_out ;
+wire [0:29] sb_1__12__9_chanx_right_out ;
+wire [0:29] sb_1__12__9_chany_bottom_out ;
+wire [0:0] sb_1__1__0_ccff_tail ;
+wire [0:29] sb_1__1__0_chanx_left_out ;
+wire [0:29] sb_1__1__0_chanx_right_out ;
+wire [0:29] sb_1__1__0_chany_bottom_out ;
+wire [0:29] sb_1__1__0_chany_top_out ;
+wire [0:0] sb_1__1__100_ccff_tail ;
+wire [0:29] sb_1__1__100_chanx_left_out ;
+wire [0:29] sb_1__1__100_chanx_right_out ;
+wire [0:29] sb_1__1__100_chany_bottom_out ;
+wire [0:29] sb_1__1__100_chany_top_out ;
+wire [0:0] sb_1__1__101_ccff_tail ;
+wire [0:29] sb_1__1__101_chanx_left_out ;
+wire [0:29] sb_1__1__101_chanx_right_out ;
+wire [0:29] sb_1__1__101_chany_bottom_out ;
+wire [0:29] sb_1__1__101_chany_top_out ;
+wire [0:0] sb_1__1__102_ccff_tail ;
+wire [0:29] sb_1__1__102_chanx_left_out ;
+wire [0:29] sb_1__1__102_chanx_right_out ;
+wire [0:29] sb_1__1__102_chany_bottom_out ;
+wire [0:29] sb_1__1__102_chany_top_out ;
+wire [0:0] sb_1__1__103_ccff_tail ;
+wire [0:29] sb_1__1__103_chanx_left_out ;
+wire [0:29] sb_1__1__103_chanx_right_out ;
+wire [0:29] sb_1__1__103_chany_bottom_out ;
+wire [0:29] sb_1__1__103_chany_top_out ;
+wire [0:0] sb_1__1__104_ccff_tail ;
+wire [0:29] sb_1__1__104_chanx_left_out ;
+wire [0:29] sb_1__1__104_chanx_right_out ;
+wire [0:29] sb_1__1__104_chany_bottom_out ;
+wire [0:29] sb_1__1__104_chany_top_out ;
+wire [0:0] sb_1__1__105_ccff_tail ;
+wire [0:29] sb_1__1__105_chanx_left_out ;
+wire [0:29] sb_1__1__105_chanx_right_out ;
+wire [0:29] sb_1__1__105_chany_bottom_out ;
+wire [0:29] sb_1__1__105_chany_top_out ;
+wire [0:0] sb_1__1__106_ccff_tail ;
+wire [0:29] sb_1__1__106_chanx_left_out ;
+wire [0:29] sb_1__1__106_chanx_right_out ;
+wire [0:29] sb_1__1__106_chany_bottom_out ;
+wire [0:29] sb_1__1__106_chany_top_out ;
+wire [0:0] sb_1__1__107_ccff_tail ;
+wire [0:29] sb_1__1__107_chanx_left_out ;
+wire [0:29] sb_1__1__107_chanx_right_out ;
+wire [0:29] sb_1__1__107_chany_bottom_out ;
+wire [0:29] sb_1__1__107_chany_top_out ;
+wire [0:0] sb_1__1__108_ccff_tail ;
+wire [0:29] sb_1__1__108_chanx_left_out ;
+wire [0:29] sb_1__1__108_chanx_right_out ;
+wire [0:29] sb_1__1__108_chany_bottom_out ;
+wire [0:29] sb_1__1__108_chany_top_out ;
+wire [0:0] sb_1__1__109_ccff_tail ;
+wire [0:29] sb_1__1__109_chanx_left_out ;
+wire [0:29] sb_1__1__109_chanx_right_out ;
+wire [0:29] sb_1__1__109_chany_bottom_out ;
+wire [0:29] sb_1__1__109_chany_top_out ;
+wire [0:0] sb_1__1__10_ccff_tail ;
+wire [0:29] sb_1__1__10_chanx_left_out ;
+wire [0:29] sb_1__1__10_chanx_right_out ;
+wire [0:29] sb_1__1__10_chany_bottom_out ;
+wire [0:29] sb_1__1__10_chany_top_out ;
+wire [0:0] sb_1__1__110_ccff_tail ;
+wire [0:29] sb_1__1__110_chanx_left_out ;
+wire [0:29] sb_1__1__110_chanx_right_out ;
+wire [0:29] sb_1__1__110_chany_bottom_out ;
+wire [0:29] sb_1__1__110_chany_top_out ;
+wire [0:0] sb_1__1__111_ccff_tail ;
+wire [0:29] sb_1__1__111_chanx_left_out ;
+wire [0:29] sb_1__1__111_chanx_right_out ;
+wire [0:29] sb_1__1__111_chany_bottom_out ;
+wire [0:29] sb_1__1__111_chany_top_out ;
+wire [0:0] sb_1__1__112_ccff_tail ;
+wire [0:29] sb_1__1__112_chanx_left_out ;
+wire [0:29] sb_1__1__112_chanx_right_out ;
+wire [0:29] sb_1__1__112_chany_bottom_out ;
+wire [0:29] sb_1__1__112_chany_top_out ;
+wire [0:0] sb_1__1__113_ccff_tail ;
+wire [0:29] sb_1__1__113_chanx_left_out ;
+wire [0:29] sb_1__1__113_chanx_right_out ;
+wire [0:29] sb_1__1__113_chany_bottom_out ;
+wire [0:29] sb_1__1__113_chany_top_out ;
+wire [0:0] sb_1__1__114_ccff_tail ;
+wire [0:29] sb_1__1__114_chanx_left_out ;
+wire [0:29] sb_1__1__114_chanx_right_out ;
+wire [0:29] sb_1__1__114_chany_bottom_out ;
+wire [0:29] sb_1__1__114_chany_top_out ;
+wire [0:0] sb_1__1__115_ccff_tail ;
+wire [0:29] sb_1__1__115_chanx_left_out ;
+wire [0:29] sb_1__1__115_chanx_right_out ;
+wire [0:29] sb_1__1__115_chany_bottom_out ;
+wire [0:29] sb_1__1__115_chany_top_out ;
+wire [0:0] sb_1__1__116_ccff_tail ;
+wire [0:29] sb_1__1__116_chanx_left_out ;
+wire [0:29] sb_1__1__116_chanx_right_out ;
+wire [0:29] sb_1__1__116_chany_bottom_out ;
+wire [0:29] sb_1__1__116_chany_top_out ;
+wire [0:0] sb_1__1__117_ccff_tail ;
+wire [0:29] sb_1__1__117_chanx_left_out ;
+wire [0:29] sb_1__1__117_chanx_right_out ;
+wire [0:29] sb_1__1__117_chany_bottom_out ;
+wire [0:29] sb_1__1__117_chany_top_out ;
+wire [0:0] sb_1__1__118_ccff_tail ;
+wire [0:29] sb_1__1__118_chanx_left_out ;
+wire [0:29] sb_1__1__118_chanx_right_out ;
+wire [0:29] sb_1__1__118_chany_bottom_out ;
+wire [0:29] sb_1__1__118_chany_top_out ;
+wire [0:0] sb_1__1__119_ccff_tail ;
+wire [0:29] sb_1__1__119_chanx_left_out ;
+wire [0:29] sb_1__1__119_chanx_right_out ;
+wire [0:29] sb_1__1__119_chany_bottom_out ;
+wire [0:29] sb_1__1__119_chany_top_out ;
+wire [0:0] sb_1__1__11_ccff_tail ;
+wire [0:29] sb_1__1__11_chanx_left_out ;
+wire [0:29] sb_1__1__11_chanx_right_out ;
+wire [0:29] sb_1__1__11_chany_bottom_out ;
+wire [0:29] sb_1__1__11_chany_top_out ;
+wire [0:0] sb_1__1__120_ccff_tail ;
+wire [0:29] sb_1__1__120_chanx_left_out ;
+wire [0:29] sb_1__1__120_chanx_right_out ;
+wire [0:29] sb_1__1__120_chany_bottom_out ;
+wire [0:29] sb_1__1__120_chany_top_out ;
+wire [0:0] sb_1__1__12_ccff_tail ;
+wire [0:29] sb_1__1__12_chanx_left_out ;
+wire [0:29] sb_1__1__12_chanx_right_out ;
+wire [0:29] sb_1__1__12_chany_bottom_out ;
+wire [0:29] sb_1__1__12_chany_top_out ;
+wire [0:0] sb_1__1__13_ccff_tail ;
+wire [0:29] sb_1__1__13_chanx_left_out ;
+wire [0:29] sb_1__1__13_chanx_right_out ;
+wire [0:29] sb_1__1__13_chany_bottom_out ;
+wire [0:29] sb_1__1__13_chany_top_out ;
+wire [0:0] sb_1__1__14_ccff_tail ;
+wire [0:29] sb_1__1__14_chanx_left_out ;
+wire [0:29] sb_1__1__14_chanx_right_out ;
+wire [0:29] sb_1__1__14_chany_bottom_out ;
+wire [0:29] sb_1__1__14_chany_top_out ;
+wire [0:0] sb_1__1__15_ccff_tail ;
+wire [0:29] sb_1__1__15_chanx_left_out ;
+wire [0:29] sb_1__1__15_chanx_right_out ;
+wire [0:29] sb_1__1__15_chany_bottom_out ;
+wire [0:29] sb_1__1__15_chany_top_out ;
+wire [0:0] sb_1__1__16_ccff_tail ;
+wire [0:29] sb_1__1__16_chanx_left_out ;
+wire [0:29] sb_1__1__16_chanx_right_out ;
+wire [0:29] sb_1__1__16_chany_bottom_out ;
+wire [0:29] sb_1__1__16_chany_top_out ;
+wire [0:0] sb_1__1__17_ccff_tail ;
+wire [0:29] sb_1__1__17_chanx_left_out ;
+wire [0:29] sb_1__1__17_chanx_right_out ;
+wire [0:29] sb_1__1__17_chany_bottom_out ;
+wire [0:29] sb_1__1__17_chany_top_out ;
+wire [0:0] sb_1__1__18_ccff_tail ;
+wire [0:29] sb_1__1__18_chanx_left_out ;
+wire [0:29] sb_1__1__18_chanx_right_out ;
+wire [0:29] sb_1__1__18_chany_bottom_out ;
+wire [0:29] sb_1__1__18_chany_top_out ;
+wire [0:0] sb_1__1__19_ccff_tail ;
+wire [0:29] sb_1__1__19_chanx_left_out ;
+wire [0:29] sb_1__1__19_chanx_right_out ;
+wire [0:29] sb_1__1__19_chany_bottom_out ;
+wire [0:29] sb_1__1__19_chany_top_out ;
+wire [0:0] sb_1__1__1_ccff_tail ;
+wire [0:29] sb_1__1__1_chanx_left_out ;
+wire [0:29] sb_1__1__1_chanx_right_out ;
+wire [0:29] sb_1__1__1_chany_bottom_out ;
+wire [0:29] sb_1__1__1_chany_top_out ;
+wire [0:0] sb_1__1__20_ccff_tail ;
+wire [0:29] sb_1__1__20_chanx_left_out ;
+wire [0:29] sb_1__1__20_chanx_right_out ;
+wire [0:29] sb_1__1__20_chany_bottom_out ;
+wire [0:29] sb_1__1__20_chany_top_out ;
+wire [0:0] sb_1__1__21_ccff_tail ;
+wire [0:29] sb_1__1__21_chanx_left_out ;
+wire [0:29] sb_1__1__21_chanx_right_out ;
+wire [0:29] sb_1__1__21_chany_bottom_out ;
+wire [0:29] sb_1__1__21_chany_top_out ;
+wire [0:0] sb_1__1__22_ccff_tail ;
+wire [0:29] sb_1__1__22_chanx_left_out ;
+wire [0:29] sb_1__1__22_chanx_right_out ;
+wire [0:29] sb_1__1__22_chany_bottom_out ;
+wire [0:29] sb_1__1__22_chany_top_out ;
+wire [0:0] sb_1__1__23_ccff_tail ;
+wire [0:29] sb_1__1__23_chanx_left_out ;
+wire [0:29] sb_1__1__23_chanx_right_out ;
+wire [0:29] sb_1__1__23_chany_bottom_out ;
+wire [0:29] sb_1__1__23_chany_top_out ;
+wire [0:0] sb_1__1__24_ccff_tail ;
+wire [0:29] sb_1__1__24_chanx_left_out ;
+wire [0:29] sb_1__1__24_chanx_right_out ;
+wire [0:29] sb_1__1__24_chany_bottom_out ;
+wire [0:29] sb_1__1__24_chany_top_out ;
+wire [0:0] sb_1__1__25_ccff_tail ;
+wire [0:29] sb_1__1__25_chanx_left_out ;
+wire [0:29] sb_1__1__25_chanx_right_out ;
+wire [0:29] sb_1__1__25_chany_bottom_out ;
+wire [0:29] sb_1__1__25_chany_top_out ;
+wire [0:0] sb_1__1__26_ccff_tail ;
+wire [0:29] sb_1__1__26_chanx_left_out ;
+wire [0:29] sb_1__1__26_chanx_right_out ;
+wire [0:29] sb_1__1__26_chany_bottom_out ;
+wire [0:29] sb_1__1__26_chany_top_out ;
+wire [0:0] sb_1__1__27_ccff_tail ;
+wire [0:29] sb_1__1__27_chanx_left_out ;
+wire [0:29] sb_1__1__27_chanx_right_out ;
+wire [0:29] sb_1__1__27_chany_bottom_out ;
+wire [0:29] sb_1__1__27_chany_top_out ;
+wire [0:0] sb_1__1__28_ccff_tail ;
+wire [0:29] sb_1__1__28_chanx_left_out ;
+wire [0:29] sb_1__1__28_chanx_right_out ;
+wire [0:29] sb_1__1__28_chany_bottom_out ;
+wire [0:29] sb_1__1__28_chany_top_out ;
+wire [0:0] sb_1__1__29_ccff_tail ;
+wire [0:29] sb_1__1__29_chanx_left_out ;
+wire [0:29] sb_1__1__29_chanx_right_out ;
+wire [0:29] sb_1__1__29_chany_bottom_out ;
+wire [0:29] sb_1__1__29_chany_top_out ;
+wire [0:0] sb_1__1__2_ccff_tail ;
+wire [0:29] sb_1__1__2_chanx_left_out ;
+wire [0:29] sb_1__1__2_chanx_right_out ;
+wire [0:29] sb_1__1__2_chany_bottom_out ;
+wire [0:29] sb_1__1__2_chany_top_out ;
+wire [0:0] sb_1__1__30_ccff_tail ;
+wire [0:29] sb_1__1__30_chanx_left_out ;
+wire [0:29] sb_1__1__30_chanx_right_out ;
+wire [0:29] sb_1__1__30_chany_bottom_out ;
+wire [0:29] sb_1__1__30_chany_top_out ;
+wire [0:0] sb_1__1__31_ccff_tail ;
+wire [0:29] sb_1__1__31_chanx_left_out ;
+wire [0:29] sb_1__1__31_chanx_right_out ;
+wire [0:29] sb_1__1__31_chany_bottom_out ;
+wire [0:29] sb_1__1__31_chany_top_out ;
+wire [0:0] sb_1__1__32_ccff_tail ;
+wire [0:29] sb_1__1__32_chanx_left_out ;
+wire [0:29] sb_1__1__32_chanx_right_out ;
+wire [0:29] sb_1__1__32_chany_bottom_out ;
+wire [0:29] sb_1__1__32_chany_top_out ;
+wire [0:0] sb_1__1__33_ccff_tail ;
+wire [0:29] sb_1__1__33_chanx_left_out ;
+wire [0:29] sb_1__1__33_chanx_right_out ;
+wire [0:29] sb_1__1__33_chany_bottom_out ;
+wire [0:29] sb_1__1__33_chany_top_out ;
+wire [0:0] sb_1__1__34_ccff_tail ;
+wire [0:29] sb_1__1__34_chanx_left_out ;
+wire [0:29] sb_1__1__34_chanx_right_out ;
+wire [0:29] sb_1__1__34_chany_bottom_out ;
+wire [0:29] sb_1__1__34_chany_top_out ;
+wire [0:0] sb_1__1__35_ccff_tail ;
+wire [0:29] sb_1__1__35_chanx_left_out ;
+wire [0:29] sb_1__1__35_chanx_right_out ;
+wire [0:29] sb_1__1__35_chany_bottom_out ;
+wire [0:29] sb_1__1__35_chany_top_out ;
+wire [0:0] sb_1__1__36_ccff_tail ;
+wire [0:29] sb_1__1__36_chanx_left_out ;
+wire [0:29] sb_1__1__36_chanx_right_out ;
+wire [0:29] sb_1__1__36_chany_bottom_out ;
+wire [0:29] sb_1__1__36_chany_top_out ;
+wire [0:0] sb_1__1__37_ccff_tail ;
+wire [0:29] sb_1__1__37_chanx_left_out ;
+wire [0:29] sb_1__1__37_chanx_right_out ;
+wire [0:29] sb_1__1__37_chany_bottom_out ;
+wire [0:29] sb_1__1__37_chany_top_out ;
+wire [0:0] sb_1__1__38_ccff_tail ;
+wire [0:29] sb_1__1__38_chanx_left_out ;
+wire [0:29] sb_1__1__38_chanx_right_out ;
+wire [0:29] sb_1__1__38_chany_bottom_out ;
+wire [0:29] sb_1__1__38_chany_top_out ;
+wire [0:0] sb_1__1__39_ccff_tail ;
+wire [0:29] sb_1__1__39_chanx_left_out ;
+wire [0:29] sb_1__1__39_chanx_right_out ;
+wire [0:29] sb_1__1__39_chany_bottom_out ;
+wire [0:29] sb_1__1__39_chany_top_out ;
+wire [0:0] sb_1__1__3_ccff_tail ;
+wire [0:29] sb_1__1__3_chanx_left_out ;
+wire [0:29] sb_1__1__3_chanx_right_out ;
+wire [0:29] sb_1__1__3_chany_bottom_out ;
+wire [0:29] sb_1__1__3_chany_top_out ;
+wire [0:0] sb_1__1__40_ccff_tail ;
+wire [0:29] sb_1__1__40_chanx_left_out ;
+wire [0:29] sb_1__1__40_chanx_right_out ;
+wire [0:29] sb_1__1__40_chany_bottom_out ;
+wire [0:29] sb_1__1__40_chany_top_out ;
+wire [0:0] sb_1__1__41_ccff_tail ;
+wire [0:29] sb_1__1__41_chanx_left_out ;
+wire [0:29] sb_1__1__41_chanx_right_out ;
+wire [0:29] sb_1__1__41_chany_bottom_out ;
+wire [0:29] sb_1__1__41_chany_top_out ;
+wire [0:0] sb_1__1__42_ccff_tail ;
+wire [0:29] sb_1__1__42_chanx_left_out ;
+wire [0:29] sb_1__1__42_chanx_right_out ;
+wire [0:29] sb_1__1__42_chany_bottom_out ;
+wire [0:29] sb_1__1__42_chany_top_out ;
+wire [0:0] sb_1__1__43_ccff_tail ;
+wire [0:29] sb_1__1__43_chanx_left_out ;
+wire [0:29] sb_1__1__43_chanx_right_out ;
+wire [0:29] sb_1__1__43_chany_bottom_out ;
+wire [0:29] sb_1__1__43_chany_top_out ;
+wire [0:0] sb_1__1__44_ccff_tail ;
+wire [0:29] sb_1__1__44_chanx_left_out ;
+wire [0:29] sb_1__1__44_chanx_right_out ;
+wire [0:29] sb_1__1__44_chany_bottom_out ;
+wire [0:29] sb_1__1__44_chany_top_out ;
+wire [0:0] sb_1__1__45_ccff_tail ;
+wire [0:29] sb_1__1__45_chanx_left_out ;
+wire [0:29] sb_1__1__45_chanx_right_out ;
+wire [0:29] sb_1__1__45_chany_bottom_out ;
+wire [0:29] sb_1__1__45_chany_top_out ;
+wire [0:0] sb_1__1__46_ccff_tail ;
+wire [0:29] sb_1__1__46_chanx_left_out ;
+wire [0:29] sb_1__1__46_chanx_right_out ;
+wire [0:29] sb_1__1__46_chany_bottom_out ;
+wire [0:29] sb_1__1__46_chany_top_out ;
+wire [0:0] sb_1__1__47_ccff_tail ;
+wire [0:29] sb_1__1__47_chanx_left_out ;
+wire [0:29] sb_1__1__47_chanx_right_out ;
+wire [0:29] sb_1__1__47_chany_bottom_out ;
+wire [0:29] sb_1__1__47_chany_top_out ;
+wire [0:0] sb_1__1__48_ccff_tail ;
+wire [0:29] sb_1__1__48_chanx_left_out ;
+wire [0:29] sb_1__1__48_chanx_right_out ;
+wire [0:29] sb_1__1__48_chany_bottom_out ;
+wire [0:29] sb_1__1__48_chany_top_out ;
+wire [0:0] sb_1__1__49_ccff_tail ;
+wire [0:29] sb_1__1__49_chanx_left_out ;
+wire [0:29] sb_1__1__49_chanx_right_out ;
+wire [0:29] sb_1__1__49_chany_bottom_out ;
+wire [0:29] sb_1__1__49_chany_top_out ;
+wire [0:0] sb_1__1__4_ccff_tail ;
+wire [0:29] sb_1__1__4_chanx_left_out ;
+wire [0:29] sb_1__1__4_chanx_right_out ;
+wire [0:29] sb_1__1__4_chany_bottom_out ;
+wire [0:29] sb_1__1__4_chany_top_out ;
+wire [0:0] sb_1__1__50_ccff_tail ;
+wire [0:29] sb_1__1__50_chanx_left_out ;
+wire [0:29] sb_1__1__50_chanx_right_out ;
+wire [0:29] sb_1__1__50_chany_bottom_out ;
+wire [0:29] sb_1__1__50_chany_top_out ;
+wire [0:0] sb_1__1__51_ccff_tail ;
+wire [0:29] sb_1__1__51_chanx_left_out ;
+wire [0:29] sb_1__1__51_chanx_right_out ;
+wire [0:29] sb_1__1__51_chany_bottom_out ;
+wire [0:29] sb_1__1__51_chany_top_out ;
+wire [0:0] sb_1__1__52_ccff_tail ;
+wire [0:29] sb_1__1__52_chanx_left_out ;
+wire [0:29] sb_1__1__52_chanx_right_out ;
+wire [0:29] sb_1__1__52_chany_bottom_out ;
+wire [0:29] sb_1__1__52_chany_top_out ;
+wire [0:0] sb_1__1__53_ccff_tail ;
+wire [0:29] sb_1__1__53_chanx_left_out ;
+wire [0:29] sb_1__1__53_chanx_right_out ;
+wire [0:29] sb_1__1__53_chany_bottom_out ;
+wire [0:29] sb_1__1__53_chany_top_out ;
+wire [0:0] sb_1__1__54_ccff_tail ;
+wire [0:29] sb_1__1__54_chanx_left_out ;
+wire [0:29] sb_1__1__54_chanx_right_out ;
+wire [0:29] sb_1__1__54_chany_bottom_out ;
+wire [0:29] sb_1__1__54_chany_top_out ;
+wire [0:0] sb_1__1__55_ccff_tail ;
+wire [0:29] sb_1__1__55_chanx_left_out ;
+wire [0:29] sb_1__1__55_chanx_right_out ;
+wire [0:29] sb_1__1__55_chany_bottom_out ;
+wire [0:29] sb_1__1__55_chany_top_out ;
+wire [0:0] sb_1__1__56_ccff_tail ;
+wire [0:29] sb_1__1__56_chanx_left_out ;
+wire [0:29] sb_1__1__56_chanx_right_out ;
+wire [0:29] sb_1__1__56_chany_bottom_out ;
+wire [0:29] sb_1__1__56_chany_top_out ;
+wire [0:0] sb_1__1__57_ccff_tail ;
+wire [0:29] sb_1__1__57_chanx_left_out ;
+wire [0:29] sb_1__1__57_chanx_right_out ;
+wire [0:29] sb_1__1__57_chany_bottom_out ;
+wire [0:29] sb_1__1__57_chany_top_out ;
+wire [0:0] sb_1__1__58_ccff_tail ;
+wire [0:29] sb_1__1__58_chanx_left_out ;
+wire [0:29] sb_1__1__58_chanx_right_out ;
+wire [0:29] sb_1__1__58_chany_bottom_out ;
+wire [0:29] sb_1__1__58_chany_top_out ;
+wire [0:0] sb_1__1__59_ccff_tail ;
+wire [0:29] sb_1__1__59_chanx_left_out ;
+wire [0:29] sb_1__1__59_chanx_right_out ;
+wire [0:29] sb_1__1__59_chany_bottom_out ;
+wire [0:29] sb_1__1__59_chany_top_out ;
+wire [0:0] sb_1__1__5_ccff_tail ;
+wire [0:29] sb_1__1__5_chanx_left_out ;
+wire [0:29] sb_1__1__5_chanx_right_out ;
+wire [0:29] sb_1__1__5_chany_bottom_out ;
+wire [0:29] sb_1__1__5_chany_top_out ;
+wire [0:0] sb_1__1__60_ccff_tail ;
+wire [0:29] sb_1__1__60_chanx_left_out ;
+wire [0:29] sb_1__1__60_chanx_right_out ;
+wire [0:29] sb_1__1__60_chany_bottom_out ;
+wire [0:29] sb_1__1__60_chany_top_out ;
+wire [0:0] sb_1__1__61_ccff_tail ;
+wire [0:29] sb_1__1__61_chanx_left_out ;
+wire [0:29] sb_1__1__61_chanx_right_out ;
+wire [0:29] sb_1__1__61_chany_bottom_out ;
+wire [0:29] sb_1__1__61_chany_top_out ;
+wire [0:0] sb_1__1__62_ccff_tail ;
+wire [0:29] sb_1__1__62_chanx_left_out ;
+wire [0:29] sb_1__1__62_chanx_right_out ;
+wire [0:29] sb_1__1__62_chany_bottom_out ;
+wire [0:29] sb_1__1__62_chany_top_out ;
+wire [0:0] sb_1__1__63_ccff_tail ;
+wire [0:29] sb_1__1__63_chanx_left_out ;
+wire [0:29] sb_1__1__63_chanx_right_out ;
+wire [0:29] sb_1__1__63_chany_bottom_out ;
+wire [0:29] sb_1__1__63_chany_top_out ;
+wire [0:0] sb_1__1__64_ccff_tail ;
+wire [0:29] sb_1__1__64_chanx_left_out ;
+wire [0:29] sb_1__1__64_chanx_right_out ;
+wire [0:29] sb_1__1__64_chany_bottom_out ;
+wire [0:29] sb_1__1__64_chany_top_out ;
+wire [0:0] sb_1__1__65_ccff_tail ;
+wire [0:29] sb_1__1__65_chanx_left_out ;
+wire [0:29] sb_1__1__65_chanx_right_out ;
+wire [0:29] sb_1__1__65_chany_bottom_out ;
+wire [0:29] sb_1__1__65_chany_top_out ;
+wire [0:0] sb_1__1__66_ccff_tail ;
+wire [0:29] sb_1__1__66_chanx_left_out ;
+wire [0:29] sb_1__1__66_chanx_right_out ;
+wire [0:29] sb_1__1__66_chany_bottom_out ;
+wire [0:29] sb_1__1__66_chany_top_out ;
+wire [0:0] sb_1__1__67_ccff_tail ;
+wire [0:29] sb_1__1__67_chanx_left_out ;
+wire [0:29] sb_1__1__67_chanx_right_out ;
+wire [0:29] sb_1__1__67_chany_bottom_out ;
+wire [0:29] sb_1__1__67_chany_top_out ;
+wire [0:0] sb_1__1__68_ccff_tail ;
+wire [0:29] sb_1__1__68_chanx_left_out ;
+wire [0:29] sb_1__1__68_chanx_right_out ;
+wire [0:29] sb_1__1__68_chany_bottom_out ;
+wire [0:29] sb_1__1__68_chany_top_out ;
+wire [0:0] sb_1__1__69_ccff_tail ;
+wire [0:29] sb_1__1__69_chanx_left_out ;
+wire [0:29] sb_1__1__69_chanx_right_out ;
+wire [0:29] sb_1__1__69_chany_bottom_out ;
+wire [0:29] sb_1__1__69_chany_top_out ;
+wire [0:0] sb_1__1__6_ccff_tail ;
+wire [0:29] sb_1__1__6_chanx_left_out ;
+wire [0:29] sb_1__1__6_chanx_right_out ;
+wire [0:29] sb_1__1__6_chany_bottom_out ;
+wire [0:29] sb_1__1__6_chany_top_out ;
+wire [0:0] sb_1__1__70_ccff_tail ;
+wire [0:29] sb_1__1__70_chanx_left_out ;
+wire [0:29] sb_1__1__70_chanx_right_out ;
+wire [0:29] sb_1__1__70_chany_bottom_out ;
+wire [0:29] sb_1__1__70_chany_top_out ;
+wire [0:0] sb_1__1__71_ccff_tail ;
+wire [0:29] sb_1__1__71_chanx_left_out ;
+wire [0:29] sb_1__1__71_chanx_right_out ;
+wire [0:29] sb_1__1__71_chany_bottom_out ;
+wire [0:29] sb_1__1__71_chany_top_out ;
+wire [0:0] sb_1__1__72_ccff_tail ;
+wire [0:29] sb_1__1__72_chanx_left_out ;
+wire [0:29] sb_1__1__72_chanx_right_out ;
+wire [0:29] sb_1__1__72_chany_bottom_out ;
+wire [0:29] sb_1__1__72_chany_top_out ;
+wire [0:0] sb_1__1__73_ccff_tail ;
+wire [0:29] sb_1__1__73_chanx_left_out ;
+wire [0:29] sb_1__1__73_chanx_right_out ;
+wire [0:29] sb_1__1__73_chany_bottom_out ;
+wire [0:29] sb_1__1__73_chany_top_out ;
+wire [0:0] sb_1__1__74_ccff_tail ;
+wire [0:29] sb_1__1__74_chanx_left_out ;
+wire [0:29] sb_1__1__74_chanx_right_out ;
+wire [0:29] sb_1__1__74_chany_bottom_out ;
+wire [0:29] sb_1__1__74_chany_top_out ;
+wire [0:0] sb_1__1__75_ccff_tail ;
+wire [0:29] sb_1__1__75_chanx_left_out ;
+wire [0:29] sb_1__1__75_chanx_right_out ;
+wire [0:29] sb_1__1__75_chany_bottom_out ;
+wire [0:29] sb_1__1__75_chany_top_out ;
+wire [0:0] sb_1__1__76_ccff_tail ;
+wire [0:29] sb_1__1__76_chanx_left_out ;
+wire [0:29] sb_1__1__76_chanx_right_out ;
+wire [0:29] sb_1__1__76_chany_bottom_out ;
+wire [0:29] sb_1__1__76_chany_top_out ;
+wire [0:0] sb_1__1__77_ccff_tail ;
+wire [0:29] sb_1__1__77_chanx_left_out ;
+wire [0:29] sb_1__1__77_chanx_right_out ;
+wire [0:29] sb_1__1__77_chany_bottom_out ;
+wire [0:29] sb_1__1__77_chany_top_out ;
+wire [0:0] sb_1__1__78_ccff_tail ;
+wire [0:29] sb_1__1__78_chanx_left_out ;
+wire [0:29] sb_1__1__78_chanx_right_out ;
+wire [0:29] sb_1__1__78_chany_bottom_out ;
+wire [0:29] sb_1__1__78_chany_top_out ;
+wire [0:0] sb_1__1__79_ccff_tail ;
+wire [0:29] sb_1__1__79_chanx_left_out ;
+wire [0:29] sb_1__1__79_chanx_right_out ;
+wire [0:29] sb_1__1__79_chany_bottom_out ;
+wire [0:29] sb_1__1__79_chany_top_out ;
+wire [0:0] sb_1__1__7_ccff_tail ;
+wire [0:29] sb_1__1__7_chanx_left_out ;
+wire [0:29] sb_1__1__7_chanx_right_out ;
+wire [0:29] sb_1__1__7_chany_bottom_out ;
+wire [0:29] sb_1__1__7_chany_top_out ;
+wire [0:0] sb_1__1__80_ccff_tail ;
+wire [0:29] sb_1__1__80_chanx_left_out ;
+wire [0:29] sb_1__1__80_chanx_right_out ;
+wire [0:29] sb_1__1__80_chany_bottom_out ;
+wire [0:29] sb_1__1__80_chany_top_out ;
+wire [0:0] sb_1__1__81_ccff_tail ;
+wire [0:29] sb_1__1__81_chanx_left_out ;
+wire [0:29] sb_1__1__81_chanx_right_out ;
+wire [0:29] sb_1__1__81_chany_bottom_out ;
+wire [0:29] sb_1__1__81_chany_top_out ;
+wire [0:0] sb_1__1__82_ccff_tail ;
+wire [0:29] sb_1__1__82_chanx_left_out ;
+wire [0:29] sb_1__1__82_chanx_right_out ;
+wire [0:29] sb_1__1__82_chany_bottom_out ;
+wire [0:29] sb_1__1__82_chany_top_out ;
+wire [0:0] sb_1__1__83_ccff_tail ;
+wire [0:29] sb_1__1__83_chanx_left_out ;
+wire [0:29] sb_1__1__83_chanx_right_out ;
+wire [0:29] sb_1__1__83_chany_bottom_out ;
+wire [0:29] sb_1__1__83_chany_top_out ;
+wire [0:0] sb_1__1__84_ccff_tail ;
+wire [0:29] sb_1__1__84_chanx_left_out ;
+wire [0:29] sb_1__1__84_chanx_right_out ;
+wire [0:29] sb_1__1__84_chany_bottom_out ;
+wire [0:29] sb_1__1__84_chany_top_out ;
+wire [0:0] sb_1__1__85_ccff_tail ;
+wire [0:29] sb_1__1__85_chanx_left_out ;
+wire [0:29] sb_1__1__85_chanx_right_out ;
+wire [0:29] sb_1__1__85_chany_bottom_out ;
+wire [0:29] sb_1__1__85_chany_top_out ;
+wire [0:0] sb_1__1__86_ccff_tail ;
+wire [0:29] sb_1__1__86_chanx_left_out ;
+wire [0:29] sb_1__1__86_chanx_right_out ;
+wire [0:29] sb_1__1__86_chany_bottom_out ;
+wire [0:29] sb_1__1__86_chany_top_out ;
+wire [0:0] sb_1__1__87_ccff_tail ;
+wire [0:29] sb_1__1__87_chanx_left_out ;
+wire [0:29] sb_1__1__87_chanx_right_out ;
+wire [0:29] sb_1__1__87_chany_bottom_out ;
+wire [0:29] sb_1__1__87_chany_top_out ;
+wire [0:0] sb_1__1__88_ccff_tail ;
+wire [0:29] sb_1__1__88_chanx_left_out ;
+wire [0:29] sb_1__1__88_chanx_right_out ;
+wire [0:29] sb_1__1__88_chany_bottom_out ;
+wire [0:29] sb_1__1__88_chany_top_out ;
+wire [0:0] sb_1__1__89_ccff_tail ;
+wire [0:29] sb_1__1__89_chanx_left_out ;
+wire [0:29] sb_1__1__89_chanx_right_out ;
+wire [0:29] sb_1__1__89_chany_bottom_out ;
+wire [0:29] sb_1__1__89_chany_top_out ;
+wire [0:0] sb_1__1__8_ccff_tail ;
+wire [0:29] sb_1__1__8_chanx_left_out ;
+wire [0:29] sb_1__1__8_chanx_right_out ;
+wire [0:29] sb_1__1__8_chany_bottom_out ;
+wire [0:29] sb_1__1__8_chany_top_out ;
+wire [0:0] sb_1__1__90_ccff_tail ;
+wire [0:29] sb_1__1__90_chanx_left_out ;
+wire [0:29] sb_1__1__90_chanx_right_out ;
+wire [0:29] sb_1__1__90_chany_bottom_out ;
+wire [0:29] sb_1__1__90_chany_top_out ;
+wire [0:0] sb_1__1__91_ccff_tail ;
+wire [0:29] sb_1__1__91_chanx_left_out ;
+wire [0:29] sb_1__1__91_chanx_right_out ;
+wire [0:29] sb_1__1__91_chany_bottom_out ;
+wire [0:29] sb_1__1__91_chany_top_out ;
+wire [0:0] sb_1__1__92_ccff_tail ;
+wire [0:29] sb_1__1__92_chanx_left_out ;
+wire [0:29] sb_1__1__92_chanx_right_out ;
+wire [0:29] sb_1__1__92_chany_bottom_out ;
+wire [0:29] sb_1__1__92_chany_top_out ;
+wire [0:0] sb_1__1__93_ccff_tail ;
+wire [0:29] sb_1__1__93_chanx_left_out ;
+wire [0:29] sb_1__1__93_chanx_right_out ;
+wire [0:29] sb_1__1__93_chany_bottom_out ;
+wire [0:29] sb_1__1__93_chany_top_out ;
+wire [0:0] sb_1__1__94_ccff_tail ;
+wire [0:29] sb_1__1__94_chanx_left_out ;
+wire [0:29] sb_1__1__94_chanx_right_out ;
+wire [0:29] sb_1__1__94_chany_bottom_out ;
+wire [0:29] sb_1__1__94_chany_top_out ;
+wire [0:0] sb_1__1__95_ccff_tail ;
+wire [0:29] sb_1__1__95_chanx_left_out ;
+wire [0:29] sb_1__1__95_chanx_right_out ;
+wire [0:29] sb_1__1__95_chany_bottom_out ;
+wire [0:29] sb_1__1__95_chany_top_out ;
+wire [0:0] sb_1__1__96_ccff_tail ;
+wire [0:29] sb_1__1__96_chanx_left_out ;
+wire [0:29] sb_1__1__96_chanx_right_out ;
+wire [0:29] sb_1__1__96_chany_bottom_out ;
+wire [0:29] sb_1__1__96_chany_top_out ;
+wire [0:0] sb_1__1__97_ccff_tail ;
+wire [0:29] sb_1__1__97_chanx_left_out ;
+wire [0:29] sb_1__1__97_chanx_right_out ;
+wire [0:29] sb_1__1__97_chany_bottom_out ;
+wire [0:29] sb_1__1__97_chany_top_out ;
+wire [0:0] sb_1__1__98_ccff_tail ;
+wire [0:29] sb_1__1__98_chanx_left_out ;
+wire [0:29] sb_1__1__98_chanx_right_out ;
+wire [0:29] sb_1__1__98_chany_bottom_out ;
+wire [0:29] sb_1__1__98_chany_top_out ;
+wire [0:0] sb_1__1__99_ccff_tail ;
+wire [0:29] sb_1__1__99_chanx_left_out ;
+wire [0:29] sb_1__1__99_chanx_right_out ;
+wire [0:29] sb_1__1__99_chany_bottom_out ;
+wire [0:29] sb_1__1__99_chany_top_out ;
+wire [0:0] sb_1__1__9_ccff_tail ;
+wire [0:29] sb_1__1__9_chanx_left_out ;
+wire [0:29] sb_1__1__9_chanx_right_out ;
+wire [0:29] sb_1__1__9_chany_bottom_out ;
+wire [0:29] sb_1__1__9_chany_top_out ;
+wire [1:0] UNCONN ;
+wire [317:0] scff_Wires ;
+wire [132:0] regin_feedthrough_wires ;
+wire [132:0] regout_feedthrough_wires ;
+wire [132:0] cin_feedthrough_wires ;
+wire [132:0] cout_feedthrough_wires ;
+wire [287:0] Test_enWires ;
+wire [636:0] pResetWires ;
+wire [287:0] ResetWires ;
+wire [624:0] prog_clk_0_wires ;
+wire [251:0] prog_clk_1_wires ;
+wire [135:0] prog_clk_2_wires ;
+wire [100:0] prog_clk_3_wires ;
+wire [251:0] clk_1_wires ;
+wire [135:0] clk_2_wires ;
+wire [100:0] clk_3_wires ;
+
+grid_clb grid_clb_1__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[0] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[0] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .ccff_head ( grid_io_left_0_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_0_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_0_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_0_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_0_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_0_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_0_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_0_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_0_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[23] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6 ) , .SC_OUT_BOT ( scff_Wires[25] ) ,
+ .Test_en_E_in ( Test_enWires[24] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9 ) ,
+ .pReset_N_in ( pResetWires[63] ) , .Reset_E_in ( ResetWires[24] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_10 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_11 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_12 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[4] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_13 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[0] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[1] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[3] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_14 ) ,
+ .clk_0_N_in ( clk_1_wires[4] ) , .clk_0_S_in ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+grid_clb grid_clb_1__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_16 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[1] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[1] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_18 } ) ,
+ .ccff_head ( grid_io_left_1_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_1_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_1_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_1_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_1_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_1_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_1_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_1_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_1_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[0] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_19 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[0] ) ,
+ .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[21] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_20 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_OUT_BOT ( scff_Wires[22] ) ,
+ .Test_en_E_in ( Test_enWires[46] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_22 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_23 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_24 ) ,
+ .pReset_N_in ( pResetWires[112] ) , .Reset_E_in ( ResetWires[46] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_25 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_26 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_27 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_28 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[3] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[6] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[7] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[9] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_29 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_30 ) , .clk_0_S_in ( clk_1_wires[3] ) ) ;
+grid_clb grid_clb_1__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_31 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[2] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_32 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[2] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_33 } ) ,
+ .ccff_head ( grid_io_left_2_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_2_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_2_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_2_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_2_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_2_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_2_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_2_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_2_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[1] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_34 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[1] ) ,
+ .ccff_tail ( grid_clb_2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[19] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , .SC_OUT_BOT ( scff_Wires[20] ) ,
+ .Test_en_E_in ( Test_enWires[68] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_37 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_38 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_39 ) ,
+ .pReset_N_in ( pResetWires[161] ) , .Reset_E_in ( ResetWires[68] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_40 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_41 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_42 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[11] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_43 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[11] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[12] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[14] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_44 ) ,
+ .clk_0_N_in ( clk_1_wires[11] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+grid_clb grid_clb_1__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_46 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[3] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_47 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[3] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_48 } ) ,
+ .ccff_head ( grid_io_left_3_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_3_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_3_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_3_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_3_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_3_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_3_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_3_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_3_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[2] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_49 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[2] ) ,
+ .ccff_tail ( grid_clb_3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[17] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires[18] ) ,
+ .Test_en_E_in ( Test_enWires[90] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_52 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_53 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_54 ) ,
+ .pReset_N_in ( pResetWires[210] ) , .Reset_E_in ( ResetWires[90] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_55 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_56 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_57 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_58 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[10] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[16] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[17] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[19] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_59 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_60 ) ,
+ .clk_0_S_in ( clk_1_wires[10] ) ) ;
+grid_clb grid_clb_1__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_61 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[4] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_62 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[4] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_63 } ) ,
+ .ccff_head ( grid_io_left_4_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_4_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_4_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_4_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_4_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_4_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_4_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_4_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_4_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_4_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_4_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_4_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_4_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_4_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_4_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_4_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_4_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_4_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_4_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_4_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_4_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_4_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_4_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_4_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_4_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_4_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_4_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_4_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_4_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_4_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_4_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_4_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_4_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[3] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_64 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[3] ) ,
+ .ccff_tail ( grid_clb_4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[15] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_66 ) , .SC_OUT_BOT ( scff_Wires[16] ) ,
+ .Test_en_E_in ( Test_enWires[112] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_67 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_68 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .pReset_N_in ( pResetWires[259] ) , .Reset_E_in ( ResetWires[112] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_71 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_72 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[18] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_73 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[21] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[22] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[24] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_74 ) ,
+ .clk_0_N_in ( clk_1_wires[18] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+grid_clb grid_clb_1__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_76 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[5] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_77 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[5] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_78 } ) ,
+ .ccff_head ( grid_io_left_5_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_5_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_5_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_5_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_5_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_5_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_5_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_5_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_5_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_5_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_5_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_5_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_5_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_5_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_5_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_5_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_5_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_5_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_5_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_5_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_5_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_5_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_5_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_5_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_5_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_5_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_5_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_5_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_5_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_5_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_5_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_5_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_5_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[4] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_79 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[4] ) ,
+ .ccff_tail ( grid_clb_5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[13] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_80 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_81 ) , .SC_OUT_BOT ( scff_Wires[14] ) ,
+ .Test_en_E_in ( Test_enWires[134] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_82 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_83 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_84 ) ,
+ .pReset_N_in ( pResetWires[308] ) , .Reset_E_in ( ResetWires[134] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_85 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_86 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_87 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_88 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[17] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[26] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[27] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[29] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_89 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_90 ) ,
+ .clk_0_S_in ( clk_1_wires[17] ) ) ;
+grid_clb grid_clb_1__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_91 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[6] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_92 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[6] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_93 } ) ,
+ .ccff_head ( grid_io_left_6_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_6_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_6_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_6_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_6_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_6_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_6_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_6_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_6_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_6_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_6_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_6_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_6_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_6_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_6_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_6_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_6_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_6_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_6_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_6_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_6_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_6_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_6_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_6_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_6_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_6_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_6_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_6_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_6_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_6_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_6_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_6_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_6_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[5] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_94 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[5] ) ,
+ .ccff_tail ( grid_clb_6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[11] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_95 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_96 ) , .SC_OUT_BOT ( scff_Wires[12] ) ,
+ .Test_en_E_in ( Test_enWires[156] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_97 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_98 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_99 ) ,
+ .pReset_N_in ( pResetWires[357] ) , .Reset_E_in ( ResetWires[156] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_100 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_101 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_102 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[25] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_103 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[31] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[32] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[34] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_104 ) ,
+ .clk_0_N_in ( clk_1_wires[25] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+grid_clb grid_clb_1__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_106 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[7] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_107 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[7] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_108 } ) ,
+ .ccff_head ( grid_io_left_7_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_7_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_7_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_7_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_7_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_7_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_7_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_7_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_7_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_7_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_7_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_7_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_7_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_7_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_7_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_7_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_7_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_7_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_7_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_7_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_7_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_7_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_7_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_7_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_7_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_7_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_7_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_7_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_7_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_7_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_7_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_7_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_7_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[6] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_109 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[6] ) ,
+ .ccff_tail ( grid_clb_7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[9] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_110 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_111 ) ,
+ .SC_OUT_BOT ( scff_Wires[10] ) , .Test_en_E_in ( Test_enWires[178] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_112 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_113 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_114 ) ,
+ .pReset_N_in ( pResetWires[406] ) , .Reset_E_in ( ResetWires[178] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_115 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_116 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_117 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_118 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[24] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[36] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[37] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[39] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_119 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_120 ) ,
+ .clk_0_S_in ( clk_1_wires[24] ) ) ;
+grid_clb grid_clb_1__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_121 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[8] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_122 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[8] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_123 } ) ,
+ .ccff_head ( grid_io_left_8_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_8_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_8_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_8_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_8_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_8_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_8_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_8_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_8_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_8_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_8_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_8_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_8_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_8_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_8_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_8_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_8_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_8_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_8_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_8_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_8_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_8_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_8_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_8_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_8_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_8_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_8_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_8_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_8_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_8_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_8_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_8_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_8_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[7] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_124 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[7] ) ,
+ .ccff_tail ( grid_clb_8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[7] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_125 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_126 ) , .SC_OUT_BOT ( scff_Wires[8] ) ,
+ .Test_en_E_in ( Test_enWires[200] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_127 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_128 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_129 ) ,
+ .pReset_N_in ( pResetWires[455] ) , .Reset_E_in ( ResetWires[200] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_130 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_131 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_132 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[32] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_133 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[41] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[42] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[44] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_134 ) ,
+ .clk_0_N_in ( clk_1_wires[32] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+grid_clb grid_clb_1__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_136 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[9] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_137 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[9] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_138 } ) ,
+ .ccff_head ( grid_io_left_9_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_9_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_9_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_9_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_9_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_9_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_9_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_9_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_9_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_9_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_9_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_9_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_9_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_9_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_9_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_9_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_9_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_9_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_9_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_9_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_9_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_9_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_9_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_9_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_9_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_9_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_9_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_9_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_9_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_9_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_9_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_9_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_9_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[8] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_139 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[8] ) ,
+ .ccff_tail ( grid_clb_9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[5] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_140 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_141 ) , .SC_OUT_BOT ( scff_Wires[6] ) ,
+ .Test_en_E_in ( Test_enWires[222] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_142 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_143 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_144 ) ,
+ .pReset_N_in ( pResetWires[504] ) , .Reset_E_in ( ResetWires[222] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_145 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_146 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_147 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_148 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[31] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[46] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[47] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[49] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_149 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_150 ) ,
+ .clk_0_S_in ( clk_1_wires[31] ) ) ;
+grid_clb grid_clb_1__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_151 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[10] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_152 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[10] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_153 } ) ,
+ .ccff_head ( grid_io_left_10_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_10_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_10_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_10_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_10_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_10_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_10_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_10_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_10_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_10_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_10_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_10_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_10_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_10_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_10_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_10_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_10_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_10_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_10_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_10_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_10_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_10_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_10_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_10_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_10_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_10_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_10_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_10_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_10_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_10_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_10_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_10_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_10_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[9] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_154 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[9] ) ,
+ .ccff_tail ( grid_clb_10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[3] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_155 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_156 ) , .SC_OUT_BOT ( scff_Wires[4] ) ,
+ .Test_en_E_in ( Test_enWires[244] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_157 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_158 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_159 ) ,
+ .pReset_N_in ( pResetWires[553] ) , .Reset_E_in ( ResetWires[244] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_160 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_161 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_162 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[39] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_163 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[51] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[52] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[54] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_164 ) ,
+ .clk_0_N_in ( clk_1_wires[39] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+grid_clb grid_clb_1__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_166 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_167 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_168 } ) ,
+ .ccff_head ( grid_io_left_11_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_11_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_11_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_11_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_11_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_11_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_11_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_11_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_11_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_11_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_11_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_11_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_11_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_11_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_11_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_11_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_11_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_11_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_11_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_11_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_11_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_11_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_11_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_11_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_11_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_11_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_11_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_11_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_11_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_11_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_11_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_11_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_11_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[10] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_169 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[10] ) ,
+ .ccff_tail ( grid_clb_11_ccff_tail ) , .SC_IN_TOP ( scff_Wires[1] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_170 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_171 ) , .SC_OUT_BOT ( scff_Wires[2] ) ,
+ .Test_en_E_in ( Test_enWires[266] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_172 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_173 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_174 ) ,
+ .pReset_N_in ( pResetWires[602] ) , .Reset_E_in ( ResetWires[266] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_175 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_176 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_177 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_178 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[38] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[56] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[57] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[61] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[59] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_179 ) ,
+ .clk_0_S_in ( clk_1_wires[38] ) ) ;
+grid_clb grid_clb_2__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_180 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[11] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_181 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[11] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_182 } ) ,
+ .ccff_head ( cby_1__1__0_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_12_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_12_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_12_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_12_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_12_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_12_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_12_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_12_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_12_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_12_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_12_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_12_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_12_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_12_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_12_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_12_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_12_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_12_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_12_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_12_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_12_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_12_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_12_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_12_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_12_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_12_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_12_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_12_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_12_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_12_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_12_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_12_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_183 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_12_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_184 ) , .SC_IN_BOT ( scff_Wires[28] ) ,
+ .SC_OUT_TOP ( scff_Wires[29] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_185 ) ,
+ .Test_en_E_in ( Test_enWires[25] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_186 ) ,
+ .Test_en_W_out ( Test_enWires[26] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_187 ) ,
+ .pReset_N_in ( pResetWires[68] ) , .Reset_E_in ( ResetWires[25] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_188 ) ,
+ .Reset_W_out ( ResetWires[26] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_189 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[6] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_190 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[63] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[64] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_191 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_192 ) ,
+ .clk_0_N_in ( clk_1_wires[6] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+grid_clb grid_clb_2__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_194 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[12] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_195 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[12] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_196 } ) ,
+ .ccff_head ( cby_1__1__1_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_13_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_13_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_13_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_13_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_13_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_13_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_13_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_13_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_13_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_13_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_13_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_13_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_13_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_13_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_13_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_13_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_13_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_13_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_13_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_13_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_13_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_13_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_13_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_13_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_13_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_13_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_13_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_13_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_13_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_13_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_13_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_13_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[11] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_197 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[11] ) ,
+ .ccff_tail ( grid_clb_13_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_198 ) , .SC_IN_BOT ( scff_Wires[30] ) ,
+ .SC_OUT_TOP ( scff_Wires[31] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_199 ) ,
+ .Test_en_E_in ( Test_enWires[47] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_200 ) ,
+ .Test_en_W_out ( Test_enWires[48] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_201 ) ,
+ .pReset_N_in ( pResetWires[117] ) , .Reset_E_in ( ResetWires[47] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_202 ) ,
+ .Reset_W_out ( ResetWires[48] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_203 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_204 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[5] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[66] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[67] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_205 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_206 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_207 ) ,
+ .clk_0_S_in ( clk_1_wires[5] ) ) ;
+grid_clb grid_clb_2__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_208 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[13] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_209 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[13] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_210 } ) ,
+ .ccff_head ( cby_1__1__2_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_14_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_14_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_14_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_14_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_14_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_14_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_14_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_14_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_14_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_14_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_14_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_14_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_14_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_14_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_14_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_14_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_14_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_14_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_14_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_14_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_14_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_14_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_14_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_14_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_14_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_14_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_14_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_14_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_14_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_14_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_14_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_14_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[12] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_211 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[12] ) ,
+ .ccff_tail ( grid_clb_14_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_212 ) , .SC_IN_BOT ( scff_Wires[32] ) ,
+ .SC_OUT_TOP ( scff_Wires[33] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_213 ) ,
+ .Test_en_E_in ( Test_enWires[69] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_214 ) ,
+ .Test_en_W_out ( Test_enWires[70] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_215 ) ,
+ .pReset_N_in ( pResetWires[166] ) , .Reset_E_in ( ResetWires[69] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_216 ) ,
+ .Reset_W_out ( ResetWires[70] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_217 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[13] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_218 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[69] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[70] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_219 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_220 ) ,
+ .clk_0_N_in ( clk_1_wires[13] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+grid_clb grid_clb_2__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_222 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[14] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_223 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[14] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_224 } ) ,
+ .ccff_head ( cby_1__1__3_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_15_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_15_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_15_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_15_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_15_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_15_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_15_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_15_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_15_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_15_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_15_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_15_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_15_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_15_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_15_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_15_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_15_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_15_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_15_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_15_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_15_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_15_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_15_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_15_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_15_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_15_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_15_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_15_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_15_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_15_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_15_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_15_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[13] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_225 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[13] ) ,
+ .ccff_tail ( grid_clb_15_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_226 ) , .SC_IN_BOT ( scff_Wires[34] ) ,
+ .SC_OUT_TOP ( scff_Wires[35] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_227 ) ,
+ .Test_en_E_in ( Test_enWires[91] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_228 ) ,
+ .Test_en_W_out ( Test_enWires[92] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_229 ) ,
+ .pReset_N_in ( pResetWires[215] ) , .Reset_E_in ( ResetWires[91] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_230 ) ,
+ .Reset_W_out ( ResetWires[92] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_231 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_232 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[12] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[72] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[73] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_233 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_234 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_235 ) ,
+ .clk_0_S_in ( clk_1_wires[12] ) ) ;
+grid_clb grid_clb_2__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_236 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[15] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_237 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[15] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_238 } ) ,
+ .ccff_head ( cby_1__1__4_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_16_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_16_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_16_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_16_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_16_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_16_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_16_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_16_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_16_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_16_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_16_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_16_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_16_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_16_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_16_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_16_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_16_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_16_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_16_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_16_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_16_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_16_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_16_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_16_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_16_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_16_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_16_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_16_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_16_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_16_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_16_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_16_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[14] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_239 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[14] ) ,
+ .ccff_tail ( grid_clb_16_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_240 ) , .SC_IN_BOT ( scff_Wires[36] ) ,
+ .SC_OUT_TOP ( scff_Wires[37] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_241 ) ,
+ .Test_en_E_in ( Test_enWires[113] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_242 ) ,
+ .Test_en_W_out ( Test_enWires[114] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_243 ) ,
+ .pReset_N_in ( pResetWires[264] ) , .Reset_E_in ( ResetWires[113] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_244 ) ,
+ .Reset_W_out ( ResetWires[114] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_245 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[20] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_246 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[75] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[76] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_247 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_248 ) ,
+ .clk_0_N_in ( clk_1_wires[20] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+grid_clb grid_clb_2__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_250 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[16] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_251 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[16] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_252 } ) ,
+ .ccff_head ( cby_1__1__5_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_17_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_17_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_17_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_17_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_17_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_17_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_17_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_17_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_17_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_17_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_17_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_17_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_17_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_17_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_17_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_17_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_17_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_17_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_17_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_17_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_17_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_17_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_17_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_17_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_17_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_17_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_17_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_17_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_17_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_17_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_17_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_17_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[15] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_253 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[15] ) ,
+ .ccff_tail ( grid_clb_17_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_254 ) , .SC_IN_BOT ( scff_Wires[38] ) ,
+ .SC_OUT_TOP ( scff_Wires[39] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_255 ) ,
+ .Test_en_E_in ( Test_enWires[135] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_256 ) ,
+ .Test_en_W_out ( Test_enWires[136] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_257 ) ,
+ .pReset_N_in ( pResetWires[313] ) , .Reset_E_in ( ResetWires[135] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_258 ) ,
+ .Reset_W_out ( ResetWires[136] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_259 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_260 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[19] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[78] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[79] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_261 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_262 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_263 ) ,
+ .clk_0_S_in ( clk_1_wires[19] ) ) ;
+grid_clb grid_clb_2__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_264 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[17] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_265 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[17] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_266 } ) ,
+ .ccff_head ( cby_1__1__6_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_18_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_18_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_18_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_18_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_18_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_18_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_18_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_18_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_18_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_18_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_18_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_18_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_18_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_18_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_18_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_18_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_18_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_18_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_18_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_18_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_18_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_18_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_18_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_18_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_18_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_18_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_18_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_18_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_18_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_18_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_18_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_18_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[16] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_267 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[16] ) ,
+ .ccff_tail ( grid_clb_18_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_268 ) , .SC_IN_BOT ( scff_Wires[40] ) ,
+ .SC_OUT_TOP ( scff_Wires[41] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_269 ) ,
+ .Test_en_E_in ( Test_enWires[157] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_270 ) ,
+ .Test_en_W_out ( Test_enWires[158] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_271 ) ,
+ .pReset_N_in ( pResetWires[362] ) , .Reset_E_in ( ResetWires[157] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_272 ) ,
+ .Reset_W_out ( ResetWires[158] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_273 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[27] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_274 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[81] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[82] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_275 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_276 ) ,
+ .clk_0_N_in ( clk_1_wires[27] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+grid_clb grid_clb_2__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_278 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[18] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_279 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[18] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_280 } ) ,
+ .ccff_head ( cby_1__1__7_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_19_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_19_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_19_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_19_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_19_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_19_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_19_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_19_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_19_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_19_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_19_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_19_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_19_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_19_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_19_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_19_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_19_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_19_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_19_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_19_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_19_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_19_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_19_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_19_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_19_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_19_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_19_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_19_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_19_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_19_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_19_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_19_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[17] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_281 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[17] ) ,
+ .ccff_tail ( grid_clb_19_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_282 ) , .SC_IN_BOT ( scff_Wires[42] ) ,
+ .SC_OUT_TOP ( scff_Wires[43] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_283 ) ,
+ .Test_en_E_in ( Test_enWires[179] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_284 ) ,
+ .Test_en_W_out ( Test_enWires[180] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_285 ) ,
+ .pReset_N_in ( pResetWires[411] ) , .Reset_E_in ( ResetWires[179] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_286 ) ,
+ .Reset_W_out ( ResetWires[180] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_287 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_288 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[26] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[84] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[85] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_289 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_290 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_291 ) ,
+ .clk_0_S_in ( clk_1_wires[26] ) ) ;
+grid_clb grid_clb_2__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_292 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[19] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_293 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[19] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_294 } ) ,
+ .ccff_head ( cby_1__1__8_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_20_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_20_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_20_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_20_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_20_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_20_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_20_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_20_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_20_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_20_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_20_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_20_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_20_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_20_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_20_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_20_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_20_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_20_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_20_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_20_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_20_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_20_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_20_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_20_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_20_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_20_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_20_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_20_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_20_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_20_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_20_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_20_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[18] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_295 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[18] ) ,
+ .ccff_tail ( grid_clb_20_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_296 ) , .SC_IN_BOT ( scff_Wires[44] ) ,
+ .SC_OUT_TOP ( scff_Wires[45] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_297 ) ,
+ .Test_en_E_in ( Test_enWires[201] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_298 ) ,
+ .Test_en_W_out ( Test_enWires[202] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_299 ) ,
+ .pReset_N_in ( pResetWires[460] ) , .Reset_E_in ( ResetWires[201] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_300 ) ,
+ .Reset_W_out ( ResetWires[202] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_301 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[34] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_302 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[87] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[88] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_303 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_304 ) ,
+ .clk_0_N_in ( clk_1_wires[34] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+grid_clb grid_clb_2__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_306 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[20] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_307 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[20] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_308 } ) ,
+ .ccff_head ( cby_1__1__9_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_21_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_21_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_21_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_21_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_21_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_21_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_21_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_21_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_21_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_21_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_21_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_21_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_21_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_21_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_21_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_21_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_21_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_21_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_21_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_21_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_21_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_21_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_21_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_21_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_21_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_21_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_21_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_21_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_21_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_21_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_21_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_21_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[19] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_309 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[19] ) ,
+ .ccff_tail ( grid_clb_21_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_310 ) , .SC_IN_BOT ( scff_Wires[46] ) ,
+ .SC_OUT_TOP ( scff_Wires[47] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_311 ) ,
+ .Test_en_E_in ( Test_enWires[223] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_312 ) ,
+ .Test_en_W_out ( Test_enWires[224] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_313 ) ,
+ .pReset_N_in ( pResetWires[509] ) , .Reset_E_in ( ResetWires[223] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_314 ) ,
+ .Reset_W_out ( ResetWires[224] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_315 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_316 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[33] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[90] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[91] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_317 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_318 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_319 ) ,
+ .clk_0_S_in ( clk_1_wires[33] ) ) ;
+grid_clb grid_clb_2__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_320 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[21] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_321 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[21] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_322 } ) ,
+ .ccff_head ( cby_1__1__10_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_22_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_22_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_22_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_22_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_22_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_22_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_22_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_22_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_22_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_22_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_22_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_22_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_22_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_22_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_22_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_22_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_22_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_22_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_22_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_22_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_22_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_22_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_22_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_22_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_22_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_22_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_22_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_22_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_22_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_22_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_22_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_22_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[20] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_323 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[20] ) ,
+ .ccff_tail ( grid_clb_22_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_324 ) , .SC_IN_BOT ( scff_Wires[48] ) ,
+ .SC_OUT_TOP ( scff_Wires[49] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_325 ) ,
+ .Test_en_E_in ( Test_enWires[245] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_326 ) ,
+ .Test_en_W_out ( Test_enWires[246] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_327 ) ,
+ .pReset_N_in ( pResetWires[558] ) , .Reset_E_in ( ResetWires[245] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_328 ) ,
+ .Reset_W_out ( ResetWires[246] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_329 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[41] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_330 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[93] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[94] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_331 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_332 ) ,
+ .clk_0_N_in ( clk_1_wires[41] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+grid_clb grid_clb_2__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_334 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_335 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_336 } ) ,
+ .ccff_head ( cby_1__1__11_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_23_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_23_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_23_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_23_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_23_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_23_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_23_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_23_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_23_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_23_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_23_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_23_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_23_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_23_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_23_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_23_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_23_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_23_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_23_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_23_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_23_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_23_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_23_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_23_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_23_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_23_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_23_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_23_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_23_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_23_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_23_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_23_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[21] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_337 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[21] ) ,
+ .ccff_tail ( grid_clb_23_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_338 ) , .SC_IN_BOT ( scff_Wires[50] ) ,
+ .SC_OUT_TOP ( scff_Wires[51] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_339 ) ,
+ .Test_en_E_in ( Test_enWires[267] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_340 ) ,
+ .Test_en_W_out ( Test_enWires[268] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_341 ) ,
+ .pReset_N_in ( pResetWires[606] ) , .Reset_E_in ( ResetWires[267] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_342 ) ,
+ .Reset_W_out ( ResetWires[268] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_343 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_344 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[40] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[96] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[97] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_345 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[99] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_346 ) ,
+ .clk_0_S_in ( clk_1_wires[40] ) ) ;
+grid_clb grid_clb_3__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_347 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[22] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_348 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[22] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_349 } ) ,
+ .ccff_head ( cby_1__1__12_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_24_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_24_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_24_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_24_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_24_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_24_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_24_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_24_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_24_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_24_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_24_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_24_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_24_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_24_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_24_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_24_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_24_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_24_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_24_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_24_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_24_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_24_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_24_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_24_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_24_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_24_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_24_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_24_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_24_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_24_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_24_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_24_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_350 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[76] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_351 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_352 ) ,
+ .SC_OUT_BOT ( scff_Wires[78] ) , .Test_en_E_in ( Test_enWires[27] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_353 ) ,
+ .Test_en_W_out ( Test_enWires[28] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_354 ) ,
+ .pReset_N_in ( pResetWires[72] ) , .Reset_E_in ( ResetWires[27] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_355 ) ,
+ .Reset_W_out ( ResetWires[28] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_356 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[46] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_357 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[101] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[102] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_358 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_359 ) ,
+ .clk_0_N_in ( clk_1_wires[46] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+grid_clb grid_clb_3__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_361 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[23] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_362 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[23] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_363 } ) ,
+ .ccff_head ( cby_1__1__13_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_25_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_25_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_25_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_25_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_25_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_25_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_25_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_25_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_25_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_25_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_25_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_25_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_25_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_25_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_25_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_25_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_25_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_25_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_25_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_25_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_25_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_25_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_25_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_25_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_25_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_25_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_25_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_25_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_25_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_25_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_25_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_25_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[22] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_364 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[22] ) ,
+ .ccff_tail ( grid_clb_25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[74] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_365 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_366 ) ,
+ .SC_OUT_BOT ( scff_Wires[75] ) , .Test_en_E_in ( Test_enWires[49] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_367 ) ,
+ .Test_en_W_out ( Test_enWires[50] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_368 ) ,
+ .pReset_N_in ( pResetWires[121] ) , .Reset_E_in ( ResetWires[49] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_369 ) ,
+ .Reset_W_out ( ResetWires[50] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_370 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_371 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[45] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[104] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[105] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_372 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_373 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_374 ) ,
+ .clk_0_S_in ( clk_1_wires[45] ) ) ;
+grid_clb grid_clb_3__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_375 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[24] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_376 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[24] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_377 } ) ,
+ .ccff_head ( cby_1__1__14_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_26_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_26_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_26_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_26_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_26_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_26_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_26_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_26_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_26_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_26_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_26_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_26_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_26_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_26_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_26_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_26_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_26_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_26_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_26_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_26_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_26_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_26_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_26_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_26_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_26_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_26_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_26_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_26_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_26_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_26_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_26_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_26_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[23] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_378 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[23] ) ,
+ .ccff_tail ( grid_clb_26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[72] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_379 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_380 ) ,
+ .SC_OUT_BOT ( scff_Wires[73] ) , .Test_en_E_in ( Test_enWires[71] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_381 ) ,
+ .Test_en_W_out ( Test_enWires[72] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_382 ) ,
+ .pReset_N_in ( pResetWires[170] ) , .Reset_E_in ( ResetWires[71] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_383 ) ,
+ .Reset_W_out ( ResetWires[72] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_384 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[53] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_385 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[107] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[108] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_386 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_387 ) ,
+ .clk_0_N_in ( clk_1_wires[53] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+grid_clb grid_clb_3__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_389 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[25] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_390 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[25] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_391 } ) ,
+ .ccff_head ( cby_1__1__15_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_27_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_27_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_27_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_27_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_27_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_27_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_27_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_27_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_27_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_27_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_27_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_27_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_27_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_27_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_27_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_27_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_27_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_27_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_27_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_27_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_27_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_27_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_27_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_27_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_27_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_27_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_27_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_27_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_27_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_27_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_27_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_27_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[24] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_392 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[24] ) ,
+ .ccff_tail ( grid_clb_27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[70] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_393 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_394 ) ,
+ .SC_OUT_BOT ( scff_Wires[71] ) , .Test_en_E_in ( Test_enWires[93] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_395 ) ,
+ .Test_en_W_out ( Test_enWires[94] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_396 ) ,
+ .pReset_N_in ( pResetWires[219] ) , .Reset_E_in ( ResetWires[93] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_397 ) ,
+ .Reset_W_out ( ResetWires[94] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_398 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_399 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[52] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[110] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[111] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_400 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_401 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_402 ) ,
+ .clk_0_S_in ( clk_1_wires[52] ) ) ;
+grid_clb grid_clb_3__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_403 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[26] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_404 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[26] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_405 } ) ,
+ .ccff_head ( cby_1__1__16_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_28_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_28_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_28_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_28_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_28_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_28_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_28_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_28_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_28_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_28_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_28_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_28_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_28_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_28_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_28_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_28_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_28_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_28_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_28_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_28_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_28_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_28_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_28_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_28_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_28_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_28_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_28_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_28_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_28_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_28_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_28_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_28_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[25] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_406 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[25] ) ,
+ .ccff_tail ( grid_clb_28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[68] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_407 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_408 ) ,
+ .SC_OUT_BOT ( scff_Wires[69] ) , .Test_en_E_in ( Test_enWires[115] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_409 ) ,
+ .Test_en_W_out ( Test_enWires[116] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_410 ) ,
+ .pReset_N_in ( pResetWires[268] ) , .Reset_E_in ( ResetWires[115] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_411 ) ,
+ .Reset_W_out ( ResetWires[116] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_412 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[60] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_413 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[113] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[114] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_414 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_415 ) ,
+ .clk_0_N_in ( clk_1_wires[60] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+grid_clb grid_clb_3__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_417 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[27] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_418 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[27] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_419 } ) ,
+ .ccff_head ( cby_1__1__17_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_29_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_29_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_29_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_29_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_29_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_29_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_29_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_29_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_29_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_29_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_29_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_29_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_29_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_29_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_29_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_29_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_29_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_29_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_29_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_29_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_29_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_29_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_29_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_29_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_29_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_29_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_29_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_29_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_29_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_29_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_29_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_29_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[26] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_420 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[26] ) ,
+ .ccff_tail ( grid_clb_29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[66] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_421 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_422 ) ,
+ .SC_OUT_BOT ( scff_Wires[67] ) , .Test_en_E_in ( Test_enWires[137] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_423 ) ,
+ .Test_en_W_out ( Test_enWires[138] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_424 ) ,
+ .pReset_N_in ( pResetWires[317] ) , .Reset_E_in ( ResetWires[137] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_425 ) ,
+ .Reset_W_out ( ResetWires[138] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_426 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_427 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[59] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[116] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[117] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_428 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_429 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_430 ) ,
+ .clk_0_S_in ( clk_1_wires[59] ) ) ;
+grid_clb grid_clb_3__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_431 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[28] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_432 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[28] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_433 } ) ,
+ .ccff_head ( cby_1__1__18_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_30_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_30_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_30_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_30_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_30_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_30_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_30_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_30_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_30_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_30_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_30_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_30_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_30_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_30_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_30_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_30_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_30_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_30_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_30_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_30_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_30_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_30_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_30_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_30_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_30_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_30_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_30_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_30_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_30_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_30_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_30_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_30_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[27] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_434 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[27] ) ,
+ .ccff_tail ( grid_clb_30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[64] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_435 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_436 ) ,
+ .SC_OUT_BOT ( scff_Wires[65] ) , .Test_en_E_in ( Test_enWires[159] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_437 ) ,
+ .Test_en_W_out ( Test_enWires[160] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_438 ) ,
+ .pReset_N_in ( pResetWires[366] ) , .Reset_E_in ( ResetWires[159] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_439 ) ,
+ .Reset_W_out ( ResetWires[160] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_440 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[67] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_441 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[119] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[120] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_442 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_443 ) ,
+ .clk_0_N_in ( clk_1_wires[67] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+grid_clb grid_clb_3__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_445 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[29] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_446 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[29] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_447 } ) ,
+ .ccff_head ( cby_1__1__19_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_31_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_31_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_31_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_31_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_31_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_31_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_31_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_31_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_31_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_31_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_31_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_31_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_31_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_31_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_31_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_31_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_31_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_31_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_31_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_31_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_31_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_31_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_31_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_31_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_31_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_31_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_31_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_31_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_31_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_31_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_31_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_31_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[28] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_448 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[28] ) ,
+ .ccff_tail ( grid_clb_31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[62] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_449 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_450 ) ,
+ .SC_OUT_BOT ( scff_Wires[63] ) , .Test_en_E_in ( Test_enWires[181] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_451 ) ,
+ .Test_en_W_out ( Test_enWires[182] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_452 ) ,
+ .pReset_N_in ( pResetWires[415] ) , .Reset_E_in ( ResetWires[181] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_453 ) ,
+ .Reset_W_out ( ResetWires[182] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_454 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_455 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[66] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[122] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[123] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_456 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_457 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_458 ) ,
+ .clk_0_S_in ( clk_1_wires[66] ) ) ;
+grid_clb grid_clb_3__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_459 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[30] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_460 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[30] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_461 } ) ,
+ .ccff_head ( cby_1__1__20_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_32_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_32_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_32_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_32_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_32_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_32_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_32_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_32_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_32_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_32_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_32_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_32_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_32_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_32_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_32_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_32_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_32_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_32_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_32_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_32_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_32_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_32_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_32_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_32_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_32_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_32_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_32_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_32_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_32_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_32_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_32_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_32_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[29] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_462 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[29] ) ,
+ .ccff_tail ( grid_clb_32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[60] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_463 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_464 ) ,
+ .SC_OUT_BOT ( scff_Wires[61] ) , .Test_en_E_in ( Test_enWires[203] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_465 ) ,
+ .Test_en_W_out ( Test_enWires[204] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_466 ) ,
+ .pReset_N_in ( pResetWires[464] ) , .Reset_E_in ( ResetWires[203] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_467 ) ,
+ .Reset_W_out ( ResetWires[204] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_468 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[74] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_469 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[125] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[126] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_470 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_471 ) ,
+ .clk_0_N_in ( clk_1_wires[74] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+grid_clb grid_clb_3__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_473 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[31] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_474 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[31] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_475 } ) ,
+ .ccff_head ( cby_1__1__21_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_33_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_33_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_33_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_33_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_33_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_33_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_33_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_33_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_33_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_33_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_33_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_33_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_33_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_33_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_33_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_33_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_33_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_33_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_33_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_33_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_33_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_33_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_33_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_33_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_33_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_33_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_33_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_33_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_33_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_33_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_33_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_33_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[30] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_476 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[30] ) ,
+ .ccff_tail ( grid_clb_33_ccff_tail ) , .SC_IN_TOP ( scff_Wires[58] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_477 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_478 ) ,
+ .SC_OUT_BOT ( scff_Wires[59] ) , .Test_en_E_in ( Test_enWires[225] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_479 ) ,
+ .Test_en_W_out ( Test_enWires[226] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_480 ) ,
+ .pReset_N_in ( pResetWires[513] ) , .Reset_E_in ( ResetWires[225] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_481 ) ,
+ .Reset_W_out ( ResetWires[226] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_482 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_483 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[73] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[128] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[129] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_484 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_485 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_486 ) ,
+ .clk_0_S_in ( clk_1_wires[73] ) ) ;
+grid_clb grid_clb_3__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_487 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[32] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_488 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[32] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_489 } ) ,
+ .ccff_head ( cby_1__1__22_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_34_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_34_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_34_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_34_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_34_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_34_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_34_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_34_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_34_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_34_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_34_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_34_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_34_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_34_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_34_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_34_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_34_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_34_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_34_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_34_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_34_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_34_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_34_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_34_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_34_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_34_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_34_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_34_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_34_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_34_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_34_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_34_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[31] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_490 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[31] ) ,
+ .ccff_tail ( grid_clb_34_ccff_tail ) , .SC_IN_TOP ( scff_Wires[56] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_491 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_492 ) ,
+ .SC_OUT_BOT ( scff_Wires[57] ) , .Test_en_E_in ( Test_enWires[247] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_493 ) ,
+ .Test_en_W_out ( Test_enWires[248] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_494 ) ,
+ .pReset_N_in ( pResetWires[562] ) , .Reset_E_in ( ResetWires[247] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_495 ) ,
+ .Reset_W_out ( ResetWires[248] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_496 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[81] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_497 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[131] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[132] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_498 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_499 ) ,
+ .clk_0_N_in ( clk_1_wires[81] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+grid_clb grid_clb_3__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_501 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_502 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_503 } ) ,
+ .ccff_head ( cby_1__1__23_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_35_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_35_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_35_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_35_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_35_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_35_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_35_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_35_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_35_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_35_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_35_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_35_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_35_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_35_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_35_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_35_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_35_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_35_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_35_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_35_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_35_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_35_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_35_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_35_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_35_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_35_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_35_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_35_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_35_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_35_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_35_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_35_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[32] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_504 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[32] ) ,
+ .ccff_tail ( grid_clb_35_ccff_tail ) , .SC_IN_TOP ( scff_Wires[54] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_505 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_506 ) ,
+ .SC_OUT_BOT ( scff_Wires[55] ) , .Test_en_E_in ( Test_enWires[269] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_507 ) ,
+ .Test_en_W_out ( Test_enWires[270] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_508 ) ,
+ .pReset_N_in ( pResetWires[609] ) , .Reset_E_in ( ResetWires[269] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_509 ) ,
+ .Reset_W_out ( ResetWires[270] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_510 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_511 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[80] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[134] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[135] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_512 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[137] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_513 ) ,
+ .clk_0_S_in ( clk_1_wires[80] ) ) ;
+grid_clb grid_clb_4__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_514 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[33] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_515 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[33] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_516 } ) ,
+ .ccff_head ( cby_1__1__24_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_36_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_36_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_36_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_36_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_36_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_36_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_36_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_36_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_36_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_36_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_36_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_36_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_36_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_36_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_36_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_36_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_36_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_36_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_36_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_36_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_36_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_36_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_36_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_36_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_36_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_36_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_36_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_36_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_36_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_36_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_36_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_36_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_517 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_36_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_518 ) , .SC_IN_BOT ( scff_Wires[81] ) ,
+ .SC_OUT_TOP ( scff_Wires[82] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_519 ) ,
+ .Test_en_E_in ( Test_enWires[29] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_520 ) ,
+ .Test_en_W_out ( Test_enWires[30] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_521 ) ,
+ .pReset_N_in ( pResetWires[76] ) , .Reset_E_in ( ResetWires[29] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_522 ) ,
+ .Reset_W_out ( ResetWires[30] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_523 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[48] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_524 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[139] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[140] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_525 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_526 ) ,
+ .clk_0_N_in ( clk_1_wires[48] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+grid_clb grid_clb_4__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_528 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[34] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_529 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[34] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_530 } ) ,
+ .ccff_head ( cby_1__1__25_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_37_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_37_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_37_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_37_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_37_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_37_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_37_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_37_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_37_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_37_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_37_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_37_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_37_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_37_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_37_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_37_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_37_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_37_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_37_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_37_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_37_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_37_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_37_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_37_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_37_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_37_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_37_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_37_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_37_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_37_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_37_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_37_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[33] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_531 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[33] ) ,
+ .ccff_tail ( grid_clb_37_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_532 ) , .SC_IN_BOT ( scff_Wires[83] ) ,
+ .SC_OUT_TOP ( scff_Wires[84] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_533 ) ,
+ .Test_en_E_in ( Test_enWires[51] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_534 ) ,
+ .Test_en_W_out ( Test_enWires[52] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_535 ) ,
+ .pReset_N_in ( pResetWires[125] ) , .Reset_E_in ( ResetWires[51] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_536 ) ,
+ .Reset_W_out ( ResetWires[52] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_537 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_538 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[47] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[142] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[143] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_539 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_540 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_541 ) ,
+ .clk_0_S_in ( clk_1_wires[47] ) ) ;
+grid_clb grid_clb_4__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_542 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[35] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_543 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[35] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_544 } ) ,
+ .ccff_head ( cby_1__1__26_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_38_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_38_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_38_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_38_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_38_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_38_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_38_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_38_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_38_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_38_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_38_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_38_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_38_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_38_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_38_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_38_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_38_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_38_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_38_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_38_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_38_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_38_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_38_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_38_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_38_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_38_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_38_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_38_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_38_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_38_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_38_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_38_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[34] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_545 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[34] ) ,
+ .ccff_tail ( grid_clb_38_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_546 ) , .SC_IN_BOT ( scff_Wires[85] ) ,
+ .SC_OUT_TOP ( scff_Wires[86] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_547 ) ,
+ .Test_en_E_in ( Test_enWires[73] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_548 ) ,
+ .Test_en_W_out ( Test_enWires[74] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_549 ) ,
+ .pReset_N_in ( pResetWires[174] ) , .Reset_E_in ( ResetWires[73] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_550 ) ,
+ .Reset_W_out ( ResetWires[74] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_551 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[55] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_552 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[145] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[146] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_553 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_554 ) ,
+ .clk_0_N_in ( clk_1_wires[55] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+grid_clb grid_clb_4__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_556 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[36] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_557 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[36] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_558 } ) ,
+ .ccff_head ( cby_1__1__27_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_39_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_39_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_39_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_39_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_39_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_39_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_39_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_39_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_39_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_39_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_39_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_39_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_39_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_39_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_39_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_39_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_39_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_39_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_39_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_39_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_39_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_39_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_39_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_39_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_39_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_39_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_39_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_39_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_39_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_39_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_39_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_39_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[35] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_559 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[35] ) ,
+ .ccff_tail ( grid_clb_39_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_560 ) , .SC_IN_BOT ( scff_Wires[87] ) ,
+ .SC_OUT_TOP ( scff_Wires[88] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_561 ) ,
+ .Test_en_E_in ( Test_enWires[95] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_562 ) ,
+ .Test_en_W_out ( Test_enWires[96] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_563 ) ,
+ .pReset_N_in ( pResetWires[223] ) , .Reset_E_in ( ResetWires[95] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_564 ) ,
+ .Reset_W_out ( ResetWires[96] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_565 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_566 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[54] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[148] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[149] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_567 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_568 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_569 ) ,
+ .clk_0_S_in ( clk_1_wires[54] ) ) ;
+grid_clb grid_clb_4__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_570 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[37] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_571 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[37] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_572 } ) ,
+ .ccff_head ( cby_1__1__28_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_40_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_40_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_40_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_40_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_40_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_40_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_40_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_40_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_40_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_40_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_40_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_40_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_40_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_40_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_40_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_40_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_40_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_40_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_40_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_40_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_40_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_40_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_40_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_40_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_40_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_40_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_40_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_40_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_40_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_40_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_40_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_40_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[36] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_573 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[36] ) ,
+ .ccff_tail ( grid_clb_40_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_574 ) , .SC_IN_BOT ( scff_Wires[89] ) ,
+ .SC_OUT_TOP ( scff_Wires[90] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_575 ) ,
+ .Test_en_E_in ( Test_enWires[117] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_576 ) ,
+ .Test_en_W_out ( Test_enWires[118] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_577 ) ,
+ .pReset_N_in ( pResetWires[272] ) , .Reset_E_in ( ResetWires[117] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_578 ) ,
+ .Reset_W_out ( ResetWires[118] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_579 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[62] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_580 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[151] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[152] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_581 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_582 ) ,
+ .clk_0_N_in ( clk_1_wires[62] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+grid_clb grid_clb_4__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_584 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[38] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_585 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[38] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_586 } ) ,
+ .ccff_head ( cby_1__1__29_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_41_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_41_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_41_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_41_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_41_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_41_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_41_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_41_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_41_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_41_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_41_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_41_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_41_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_41_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_41_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_41_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_41_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_41_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_41_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_41_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_41_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_41_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_41_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_41_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_41_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_41_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_41_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_41_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_41_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_41_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_41_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_41_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[37] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_587 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[37] ) ,
+ .ccff_tail ( grid_clb_41_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_588 ) , .SC_IN_BOT ( scff_Wires[91] ) ,
+ .SC_OUT_TOP ( scff_Wires[92] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_589 ) ,
+ .Test_en_E_in ( Test_enWires[139] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_590 ) ,
+ .Test_en_W_out ( Test_enWires[140] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_591 ) ,
+ .pReset_N_in ( pResetWires[321] ) , .Reset_E_in ( ResetWires[139] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_592 ) ,
+ .Reset_W_out ( ResetWires[140] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_593 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_594 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[61] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[154] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[155] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_595 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_596 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_597 ) ,
+ .clk_0_S_in ( clk_1_wires[61] ) ) ;
+grid_clb grid_clb_4__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_598 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[39] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_599 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[39] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_600 } ) ,
+ .ccff_head ( cby_1__1__30_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_42_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_42_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_42_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_42_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_42_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_42_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_42_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_42_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_42_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_42_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_42_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_42_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_42_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_42_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_42_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_42_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_42_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_42_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_42_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_42_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_42_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_42_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_42_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_42_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_42_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_42_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_42_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_42_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_42_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_42_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_42_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_42_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[38] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_601 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[38] ) ,
+ .ccff_tail ( grid_clb_42_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_602 ) , .SC_IN_BOT ( scff_Wires[93] ) ,
+ .SC_OUT_TOP ( scff_Wires[94] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_603 ) ,
+ .Test_en_E_in ( Test_enWires[161] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_604 ) ,
+ .Test_en_W_out ( Test_enWires[162] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_605 ) ,
+ .pReset_N_in ( pResetWires[370] ) , .Reset_E_in ( ResetWires[161] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_606 ) ,
+ .Reset_W_out ( ResetWires[162] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_607 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[69] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_608 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[157] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[158] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_609 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_610 ) ,
+ .clk_0_N_in ( clk_1_wires[69] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+grid_clb grid_clb_4__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_612 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[40] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_613 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[40] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_614 } ) ,
+ .ccff_head ( cby_1__1__31_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_43_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_43_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_43_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_43_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_43_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_43_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_43_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_43_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_43_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_43_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_43_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_43_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_43_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_43_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_43_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_43_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_43_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_43_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_43_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_43_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_43_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_43_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_43_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_43_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_43_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_43_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_43_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_43_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_43_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_43_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_43_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_43_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[39] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_615 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[39] ) ,
+ .ccff_tail ( grid_clb_43_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_616 ) , .SC_IN_BOT ( scff_Wires[95] ) ,
+ .SC_OUT_TOP ( scff_Wires[96] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_617 ) ,
+ .Test_en_E_in ( Test_enWires[183] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_618 ) ,
+ .Test_en_W_out ( Test_enWires[184] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_619 ) ,
+ .pReset_N_in ( pResetWires[419] ) , .Reset_E_in ( ResetWires[183] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_620 ) ,
+ .Reset_W_out ( ResetWires[184] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_621 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_622 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[68] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[160] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[161] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_623 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_624 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_625 ) ,
+ .clk_0_S_in ( clk_1_wires[68] ) ) ;
+grid_clb grid_clb_4__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_626 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[41] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_627 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[41] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_628 } ) ,
+ .ccff_head ( cby_1__1__32_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_44_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_44_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_44_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_44_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_44_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_44_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_44_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_44_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_44_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_44_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_44_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_44_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_44_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_44_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_44_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_44_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_44_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_44_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_44_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_44_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_44_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_44_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_44_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_44_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_44_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_44_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_44_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_44_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_44_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_44_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_44_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_44_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[40] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_629 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[40] ) ,
+ .ccff_tail ( grid_clb_44_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_630 ) , .SC_IN_BOT ( scff_Wires[97] ) ,
+ .SC_OUT_TOP ( scff_Wires[98] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_631 ) ,
+ .Test_en_E_in ( Test_enWires[205] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_632 ) ,
+ .Test_en_W_out ( Test_enWires[206] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_633 ) ,
+ .pReset_N_in ( pResetWires[468] ) , .Reset_E_in ( ResetWires[205] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_634 ) ,
+ .Reset_W_out ( ResetWires[206] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_635 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[76] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_636 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[163] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[164] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_637 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_638 ) ,
+ .clk_0_N_in ( clk_1_wires[76] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+grid_clb grid_clb_4__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_640 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[42] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_641 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[42] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_642 } ) ,
+ .ccff_head ( cby_1__1__33_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_45_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_45_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_45_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_45_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_45_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_45_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_45_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_45_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_45_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_45_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_45_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_45_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_45_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_45_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_45_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_45_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_45_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_45_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_45_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_45_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_45_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_45_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_45_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_45_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_45_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_45_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_45_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_45_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_45_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_45_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_45_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_45_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[41] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_643 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[41] ) ,
+ .ccff_tail ( grid_clb_45_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_644 ) , .SC_IN_BOT ( scff_Wires[99] ) ,
+ .SC_OUT_TOP ( scff_Wires[100] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_645 ) ,
+ .Test_en_E_in ( Test_enWires[227] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_646 ) ,
+ .Test_en_W_out ( Test_enWires[228] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_647 ) ,
+ .pReset_N_in ( pResetWires[517] ) , .Reset_E_in ( ResetWires[227] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_648 ) ,
+ .Reset_W_out ( ResetWires[228] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_649 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_650 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[75] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[166] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[167] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_651 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_652 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_653 ) ,
+ .clk_0_S_in ( clk_1_wires[75] ) ) ;
+grid_clb grid_clb_4__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_654 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[43] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_655 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[43] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_656 } ) ,
+ .ccff_head ( cby_1__1__34_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_46_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_46_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_46_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_46_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_46_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_46_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_46_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_46_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_46_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_46_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_46_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_46_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_46_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_46_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_46_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_46_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_46_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_46_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_46_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_46_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_46_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_46_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_46_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_46_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_46_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_46_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_46_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_46_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_46_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_46_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_46_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_46_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[42] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_657 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[42] ) ,
+ .ccff_tail ( grid_clb_46_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_658 ) , .SC_IN_BOT ( scff_Wires[101] ) ,
+ .SC_OUT_TOP ( scff_Wires[102] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_659 ) ,
+ .Test_en_E_in ( Test_enWires[249] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_660 ) ,
+ .Test_en_W_out ( Test_enWires[250] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_661 ) ,
+ .pReset_N_in ( pResetWires[566] ) , .Reset_E_in ( ResetWires[249] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_662 ) ,
+ .Reset_W_out ( ResetWires[250] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_663 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[83] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_664 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[169] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[170] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_665 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_666 ) ,
+ .clk_0_N_in ( clk_1_wires[83] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+grid_clb grid_clb_4__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_668 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_669 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_670 } ) ,
+ .ccff_head ( cby_1__1__35_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_47_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_47_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_47_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_47_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_47_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_47_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_47_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_47_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_47_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_47_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_47_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_47_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_47_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_47_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_47_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_47_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_47_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_47_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_47_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_47_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_47_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_47_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_47_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_47_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_47_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_47_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_47_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_47_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_47_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_47_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_47_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_47_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[43] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_671 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[43] ) ,
+ .ccff_tail ( grid_clb_47_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_672 ) , .SC_IN_BOT ( scff_Wires[103] ) ,
+ .SC_OUT_TOP ( scff_Wires[104] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_673 ) ,
+ .Test_en_E_in ( Test_enWires[271] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_674 ) ,
+ .Test_en_W_out ( Test_enWires[272] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_675 ) ,
+ .pReset_N_in ( pResetWires[612] ) , .Reset_E_in ( ResetWires[271] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_676 ) ,
+ .Reset_W_out ( ResetWires[272] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_677 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_678 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[82] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[172] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[173] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_679 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[175] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_680 ) ,
+ .clk_0_S_in ( clk_1_wires[82] ) ) ;
+grid_clb grid_clb_5__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_681 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[44] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_682 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[44] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_683 } ) ,
+ .ccff_head ( cby_1__1__36_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_48_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_48_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_48_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_48_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_48_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_48_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_48_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_48_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_48_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_48_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_48_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_48_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_48_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_48_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_48_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_48_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_48_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_48_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_48_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_48_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_48_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_48_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_48_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_48_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_48_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_48_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_48_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_48_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_48_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_48_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_48_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_48_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_684 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[129] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_685 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_686 ) ,
+ .SC_OUT_BOT ( scff_Wires[131] ) , .Test_en_E_in ( Test_enWires[31] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_687 ) ,
+ .Test_en_W_out ( Test_enWires[32] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_688 ) ,
+ .pReset_N_in ( pResetWires[80] ) , .Reset_E_in ( ResetWires[31] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_689 ) ,
+ .Reset_W_out ( ResetWires[32] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_690 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[88] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_691 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[177] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[178] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_692 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_693 ) ,
+ .clk_0_N_in ( clk_1_wires[88] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+grid_clb grid_clb_5__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_695 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[45] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_696 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[45] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_697 } ) ,
+ .ccff_head ( cby_1__1__37_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_49_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_49_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_49_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_49_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_49_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_49_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_49_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_49_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_49_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_49_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_49_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_49_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_49_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_49_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_49_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_49_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_49_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_49_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_49_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_49_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_49_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_49_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_49_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_49_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_49_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_49_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_49_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_49_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_49_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_49_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_49_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_49_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[44] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_698 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[44] ) ,
+ .ccff_tail ( grid_clb_49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[127] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_699 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_700 ) ,
+ .SC_OUT_BOT ( scff_Wires[128] ) , .Test_en_E_in ( Test_enWires[53] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_701 ) ,
+ .Test_en_W_out ( Test_enWires[54] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_702 ) ,
+ .pReset_N_in ( pResetWires[129] ) , .Reset_E_in ( ResetWires[53] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_703 ) ,
+ .Reset_W_out ( ResetWires[54] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_704 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_705 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[87] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[180] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[181] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_706 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_707 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_708 ) ,
+ .clk_0_S_in ( clk_1_wires[87] ) ) ;
+grid_clb grid_clb_5__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_709 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[46] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_710 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[46] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_711 } ) ,
+ .ccff_head ( cby_1__1__38_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_50_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_50_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_50_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_50_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_50_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_50_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_50_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_50_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_50_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_50_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_50_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_50_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_50_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_50_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_50_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_50_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_50_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_50_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_50_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_50_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_50_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_50_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_50_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_50_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_50_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_50_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_50_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_50_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_50_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_50_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_50_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_50_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[45] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_712 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[45] ) ,
+ .ccff_tail ( grid_clb_50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[125] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_713 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_714 ) ,
+ .SC_OUT_BOT ( scff_Wires[126] ) , .Test_en_E_in ( Test_enWires[75] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_715 ) ,
+ .Test_en_W_out ( Test_enWires[76] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_716 ) ,
+ .pReset_N_in ( pResetWires[178] ) , .Reset_E_in ( ResetWires[75] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_717 ) ,
+ .Reset_W_out ( ResetWires[76] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_718 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[95] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_719 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[183] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[184] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_720 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_721 ) ,
+ .clk_0_N_in ( clk_1_wires[95] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+grid_clb grid_clb_5__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_723 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[47] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_724 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[47] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_725 } ) ,
+ .ccff_head ( cby_1__1__39_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_51_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_51_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_51_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_51_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_51_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_51_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_51_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_51_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_51_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_51_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_51_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_51_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_51_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_51_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_51_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_51_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_51_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_51_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_51_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_51_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_51_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_51_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_51_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_51_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_51_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_51_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_51_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_51_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_51_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_51_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_51_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_51_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[46] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_726 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[46] ) ,
+ .ccff_tail ( grid_clb_51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[123] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_727 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_728 ) ,
+ .SC_OUT_BOT ( scff_Wires[124] ) , .Test_en_E_in ( Test_enWires[97] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_729 ) ,
+ .Test_en_W_out ( Test_enWires[98] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_730 ) ,
+ .pReset_N_in ( pResetWires[227] ) , .Reset_E_in ( ResetWires[97] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_731 ) ,
+ .Reset_W_out ( ResetWires[98] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_732 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_733 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[94] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[186] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[187] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_734 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_735 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_736 ) ,
+ .clk_0_S_in ( clk_1_wires[94] ) ) ;
+grid_clb grid_clb_5__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_737 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[48] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_738 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[48] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_739 } ) ,
+ .ccff_head ( cby_1__1__40_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_52_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_52_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_52_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_52_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_52_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_52_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_52_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_52_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_52_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_52_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_52_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_52_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_52_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_52_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_52_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_52_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_52_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_52_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_52_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_52_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_52_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_52_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_52_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_52_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_52_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_52_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_52_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_52_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_52_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_52_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_52_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_52_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[47] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_740 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[47] ) ,
+ .ccff_tail ( grid_clb_52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[121] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_741 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_742 ) ,
+ .SC_OUT_BOT ( scff_Wires[122] ) , .Test_en_E_in ( Test_enWires[119] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_743 ) ,
+ .Test_en_W_out ( Test_enWires[120] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_744 ) ,
+ .pReset_N_in ( pResetWires[276] ) , .Reset_E_in ( ResetWires[119] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_745 ) ,
+ .Reset_W_out ( ResetWires[120] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_746 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[102] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_747 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[189] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[190] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_748 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_749 ) ,
+ .clk_0_N_in ( clk_1_wires[102] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+grid_clb grid_clb_5__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_751 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[49] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_752 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[49] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_753 } ) ,
+ .ccff_head ( cby_1__1__41_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_53_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_53_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_53_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_53_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_53_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_53_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_53_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_53_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_53_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_53_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_53_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_53_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_53_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_53_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_53_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_53_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_53_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_53_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_53_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_53_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_53_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_53_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_53_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_53_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_53_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_53_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_53_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_53_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_53_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_53_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_53_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_53_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[48] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_754 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[48] ) ,
+ .ccff_tail ( grid_clb_53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[119] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_755 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_756 ) ,
+ .SC_OUT_BOT ( scff_Wires[120] ) , .Test_en_E_in ( Test_enWires[141] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_757 ) ,
+ .Test_en_W_out ( Test_enWires[142] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_758 ) ,
+ .pReset_N_in ( pResetWires[325] ) , .Reset_E_in ( ResetWires[141] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_759 ) ,
+ .Reset_W_out ( ResetWires[142] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_760 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_761 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[101] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[192] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[193] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_762 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_763 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_764 ) ,
+ .clk_0_S_in ( clk_1_wires[101] ) ) ;
+grid_clb grid_clb_5__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_765 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[50] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_766 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[50] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_767 } ) ,
+ .ccff_head ( cby_1__1__42_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_54_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_54_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_54_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_54_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_54_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_54_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_54_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_54_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_54_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_54_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_54_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_54_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_54_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_54_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_54_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_54_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_54_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_54_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_54_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_54_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_54_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_54_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_54_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_54_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_54_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_54_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_54_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_54_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_54_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_54_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_54_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_54_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[49] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_768 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[49] ) ,
+ .ccff_tail ( grid_clb_54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[117] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_769 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_770 ) ,
+ .SC_OUT_BOT ( scff_Wires[118] ) , .Test_en_E_in ( Test_enWires[163] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_771 ) ,
+ .Test_en_W_out ( Test_enWires[164] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_772 ) ,
+ .pReset_N_in ( pResetWires[374] ) , .Reset_E_in ( ResetWires[163] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_773 ) ,
+ .Reset_W_out ( ResetWires[164] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_774 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[109] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_775 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[195] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[196] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_776 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_777 ) ,
+ .clk_0_N_in ( clk_1_wires[109] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+grid_clb grid_clb_5__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_779 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[51] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_780 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[51] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_781 } ) ,
+ .ccff_head ( cby_1__1__43_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_55_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_55_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_55_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_55_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_55_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_55_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_55_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_55_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_55_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_55_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_55_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_55_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_55_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_55_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_55_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_55_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_55_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_55_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_55_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_55_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_55_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_55_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_55_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_55_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_55_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_55_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_55_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_55_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_55_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_55_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_55_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_55_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[50] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_782 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[50] ) ,
+ .ccff_tail ( grid_clb_55_ccff_tail ) , .SC_IN_TOP ( scff_Wires[115] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_783 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_784 ) ,
+ .SC_OUT_BOT ( scff_Wires[116] ) , .Test_en_E_in ( Test_enWires[185] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_785 ) ,
+ .Test_en_W_out ( Test_enWires[186] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_786 ) ,
+ .pReset_N_in ( pResetWires[423] ) , .Reset_E_in ( ResetWires[185] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_787 ) ,
+ .Reset_W_out ( ResetWires[186] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_788 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_789 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[108] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[198] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[199] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_790 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_791 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_792 ) ,
+ .clk_0_S_in ( clk_1_wires[108] ) ) ;
+grid_clb grid_clb_5__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_793 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[52] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_794 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[52] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_795 } ) ,
+ .ccff_head ( cby_1__1__44_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_56_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_56_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_56_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_56_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_56_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_56_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_56_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_56_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_56_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_56_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_56_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_56_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_56_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_56_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_56_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_56_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_56_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_56_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_56_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_56_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_56_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_56_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_56_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_56_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_56_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_56_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_56_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_56_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_56_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_56_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_56_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_56_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[51] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_796 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[51] ) ,
+ .ccff_tail ( grid_clb_56_ccff_tail ) , .SC_IN_TOP ( scff_Wires[113] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_797 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_798 ) ,
+ .SC_OUT_BOT ( scff_Wires[114] ) , .Test_en_E_in ( Test_enWires[207] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_799 ) ,
+ .Test_en_W_out ( Test_enWires[208] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_800 ) ,
+ .pReset_N_in ( pResetWires[472] ) , .Reset_E_in ( ResetWires[207] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_801 ) ,
+ .Reset_W_out ( ResetWires[208] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_802 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[116] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_803 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[201] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[202] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_804 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_805 ) ,
+ .clk_0_N_in ( clk_1_wires[116] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+grid_clb grid_clb_5__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_807 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[53] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_808 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[53] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_809 } ) ,
+ .ccff_head ( cby_1__1__45_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_57_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_57_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_57_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_57_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_57_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_57_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_57_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_57_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_57_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_57_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_57_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_57_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_57_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_57_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_57_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_57_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_57_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_57_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_57_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_57_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_57_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_57_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_57_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_57_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_57_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_57_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_57_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_57_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_57_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_57_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_57_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_57_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[52] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_810 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[52] ) ,
+ .ccff_tail ( grid_clb_57_ccff_tail ) , .SC_IN_TOP ( scff_Wires[111] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_811 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_812 ) ,
+ .SC_OUT_BOT ( scff_Wires[112] ) , .Test_en_E_in ( Test_enWires[229] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_813 ) ,
+ .Test_en_W_out ( Test_enWires[230] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_814 ) ,
+ .pReset_N_in ( pResetWires[521] ) , .Reset_E_in ( ResetWires[229] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_815 ) ,
+ .Reset_W_out ( ResetWires[230] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_816 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_817 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[115] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[204] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[205] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_818 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_819 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_820 ) ,
+ .clk_0_S_in ( clk_1_wires[115] ) ) ;
+grid_clb grid_clb_5__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_821 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[54] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_822 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[54] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_823 } ) ,
+ .ccff_head ( cby_1__1__46_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_58_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_58_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_58_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_58_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_58_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_58_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_58_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_58_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_58_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_58_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_58_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_58_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_58_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_58_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_58_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_58_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_58_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_58_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_58_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_58_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_58_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_58_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_58_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_58_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_58_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_58_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_58_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_58_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_58_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_58_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_58_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_58_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[53] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_824 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[53] ) ,
+ .ccff_tail ( grid_clb_58_ccff_tail ) , .SC_IN_TOP ( scff_Wires[109] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_825 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_826 ) ,
+ .SC_OUT_BOT ( scff_Wires[110] ) , .Test_en_E_in ( Test_enWires[251] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_827 ) ,
+ .Test_en_W_out ( Test_enWires[252] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_828 ) ,
+ .pReset_N_in ( pResetWires[570] ) , .Reset_E_in ( ResetWires[251] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_829 ) ,
+ .Reset_W_out ( ResetWires[252] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_830 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[123] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_831 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[207] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[208] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_832 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_833 ) ,
+ .clk_0_N_in ( clk_1_wires[123] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+grid_clb grid_clb_5__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_835 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_836 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_837 } ) ,
+ .ccff_head ( cby_1__1__47_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_59_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_59_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_59_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_59_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_59_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_59_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_59_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_59_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_59_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_59_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_59_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_59_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_59_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_59_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_59_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_59_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_59_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_59_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_59_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_59_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_59_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_59_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_59_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_59_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_59_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_59_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_59_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_59_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_59_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_59_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_59_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_59_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[54] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_838 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[54] ) ,
+ .ccff_tail ( grid_clb_59_ccff_tail ) , .SC_IN_TOP ( scff_Wires[107] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_839 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_840 ) ,
+ .SC_OUT_BOT ( scff_Wires[108] ) , .Test_en_E_in ( Test_enWires[273] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_841 ) ,
+ .Test_en_W_out ( Test_enWires[274] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_842 ) ,
+ .pReset_N_in ( pResetWires[615] ) , .Reset_E_in ( ResetWires[273] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_843 ) ,
+ .Reset_W_out ( ResetWires[274] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_844 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_845 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[122] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[210] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[211] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_846 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[213] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_847 ) ,
+ .clk_0_S_in ( clk_1_wires[122] ) ) ;
+grid_clb grid_clb_6__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_848 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[55] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_849 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[55] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_850 } ) ,
+ .ccff_head ( cby_1__1__48_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_60_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_60_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_60_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_60_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_60_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_60_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_60_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_60_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_60_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_60_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_60_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_60_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_60_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_60_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_60_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_60_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_60_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_60_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_60_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_60_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_60_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_60_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_60_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_60_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_60_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_60_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_60_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_60_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_60_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_60_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_60_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_60_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_851 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_60_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_852 ) , .SC_IN_BOT ( scff_Wires[134] ) ,
+ .SC_OUT_TOP ( scff_Wires[135] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_853 ) ,
+ .Test_en_E_in ( Test_enWires[33] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_854 ) ,
+ .Test_en_W_out ( Test_enWires[34] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_855 ) ,
+ .pReset_N_in ( pResetWires[84] ) , .Reset_E_in ( ResetWires[33] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_856 ) ,
+ .Reset_W_out ( ResetWires[34] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_857 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[90] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_858 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[215] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[216] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_859 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_860 ) ,
+ .clk_0_N_in ( clk_1_wires[90] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+grid_clb grid_clb_6__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_862 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[56] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_863 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[56] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_864 } ) ,
+ .ccff_head ( cby_1__1__49_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_61_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_61_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_61_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_61_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_61_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_61_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_61_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_61_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_61_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_61_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_61_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_61_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_61_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_61_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_61_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_61_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_61_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_61_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_61_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_61_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_61_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_61_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_61_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_61_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_61_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_61_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_61_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_61_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_61_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_61_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_61_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_61_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[55] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_865 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[55] ) ,
+ .ccff_tail ( grid_clb_61_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_866 ) , .SC_IN_BOT ( scff_Wires[136] ) ,
+ .SC_OUT_TOP ( scff_Wires[137] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_867 ) ,
+ .Test_en_E_in ( Test_enWires[55] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_868 ) ,
+ .Test_en_W_out ( Test_enWires[56] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_869 ) ,
+ .pReset_N_in ( pResetWires[133] ) , .Reset_E_in ( ResetWires[55] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_870 ) ,
+ .Reset_W_out ( ResetWires[56] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_871 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_872 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[89] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[218] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[219] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_873 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_874 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_875 ) ,
+ .clk_0_S_in ( clk_1_wires[89] ) ) ;
+grid_clb grid_clb_6__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_876 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[57] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_877 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[57] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_878 } ) ,
+ .ccff_head ( cby_1__1__50_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_62_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_62_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_62_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_62_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_62_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_62_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_62_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_62_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_62_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_62_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_62_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_62_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_62_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_62_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_62_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_62_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_62_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_62_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_62_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_62_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_62_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_62_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_62_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_62_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_62_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_62_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_62_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_62_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_62_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_62_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_62_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_62_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[56] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_879 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[56] ) ,
+ .ccff_tail ( grid_clb_62_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_880 ) , .SC_IN_BOT ( scff_Wires[138] ) ,
+ .SC_OUT_TOP ( scff_Wires[139] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_881 ) ,
+ .Test_en_E_in ( Test_enWires[77] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_882 ) ,
+ .Test_en_W_out ( Test_enWires[78] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_883 ) ,
+ .pReset_N_in ( pResetWires[182] ) , .Reset_E_in ( ResetWires[77] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_884 ) ,
+ .Reset_W_out ( ResetWires[78] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_885 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[97] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_886 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[221] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[222] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_887 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_888 ) ,
+ .clk_0_N_in ( clk_1_wires[97] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+grid_clb grid_clb_6__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_890 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[58] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_891 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[58] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_892 } ) ,
+ .ccff_head ( cby_1__1__51_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_63_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_63_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_63_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_63_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_63_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_63_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_63_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_63_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_63_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_63_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_63_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_63_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_63_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_63_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_63_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_63_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_63_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_63_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_63_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_63_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_63_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_63_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_63_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_63_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_63_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_63_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_63_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_63_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_63_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_63_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_63_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_63_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[57] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_893 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[57] ) ,
+ .ccff_tail ( grid_clb_63_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_894 ) , .SC_IN_BOT ( scff_Wires[140] ) ,
+ .SC_OUT_TOP ( scff_Wires[141] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_895 ) ,
+ .Test_en_E_in ( Test_enWires[99] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_896 ) ,
+ .Test_en_W_out ( Test_enWires[100] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_897 ) ,
+ .pReset_N_in ( pResetWires[231] ) , .Reset_E_in ( ResetWires[99] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_898 ) ,
+ .Reset_W_out ( ResetWires[100] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_899 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_900 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[96] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[224] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[225] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_901 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_902 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_903 ) ,
+ .clk_0_S_in ( clk_1_wires[96] ) ) ;
+grid_clb grid_clb_6__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_904 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[59] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_905 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[59] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_906 } ) ,
+ .ccff_head ( cby_1__1__52_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_64_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_64_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_64_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_64_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_64_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_64_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_64_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_64_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_64_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_64_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_64_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_64_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_64_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_64_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_64_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_64_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_64_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_64_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_64_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_64_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_64_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_64_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_64_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_64_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_64_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_64_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_64_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_64_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_64_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_64_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_64_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_64_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[58] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_907 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[58] ) ,
+ .ccff_tail ( grid_clb_64_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_908 ) , .SC_IN_BOT ( scff_Wires[142] ) ,
+ .SC_OUT_TOP ( scff_Wires[143] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_909 ) ,
+ .Test_en_E_in ( Test_enWires[121] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_910 ) ,
+ .Test_en_W_out ( Test_enWires[122] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_911 ) ,
+ .pReset_N_in ( pResetWires[280] ) , .Reset_E_in ( ResetWires[121] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_912 ) ,
+ .Reset_W_out ( ResetWires[122] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_913 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[104] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_914 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[227] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[228] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_915 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_916 ) ,
+ .clk_0_N_in ( clk_1_wires[104] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+grid_clb grid_clb_6__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_918 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[60] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_919 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[60] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_920 } ) ,
+ .ccff_head ( cby_1__1__53_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_65_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_65_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_65_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_65_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_65_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_65_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_65_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_65_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_65_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_65_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_65_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_65_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_65_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_65_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_65_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_65_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_65_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_65_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_65_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_65_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_65_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_65_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_65_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_65_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_65_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_65_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_65_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_65_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_65_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_65_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_65_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_65_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[59] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_921 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[59] ) ,
+ .ccff_tail ( grid_clb_65_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_922 ) , .SC_IN_BOT ( scff_Wires[144] ) ,
+ .SC_OUT_TOP ( scff_Wires[145] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_923 ) ,
+ .Test_en_E_in ( Test_enWires[143] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_924 ) ,
+ .Test_en_W_out ( Test_enWires[144] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_925 ) ,
+ .pReset_N_in ( pResetWires[329] ) , .Reset_E_in ( ResetWires[143] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_926 ) ,
+ .Reset_W_out ( ResetWires[144] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_927 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_928 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[103] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[230] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[231] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_929 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_930 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_931 ) ,
+ .clk_0_S_in ( clk_1_wires[103] ) ) ;
+grid_clb grid_clb_6__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_932 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[61] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_933 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[61] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_934 } ) ,
+ .ccff_head ( cby_1__1__54_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_66_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_66_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_66_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_66_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_66_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_66_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_66_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_66_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_66_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_66_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_66_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_66_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_66_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_66_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_66_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_66_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_66_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_66_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_66_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_66_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_66_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_66_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_66_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_66_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_66_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_66_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_66_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_66_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_66_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_66_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_66_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_66_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[60] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_935 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[60] ) ,
+ .ccff_tail ( grid_clb_66_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_936 ) , .SC_IN_BOT ( scff_Wires[146] ) ,
+ .SC_OUT_TOP ( scff_Wires[147] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_937 ) ,
+ .Test_en_E_in ( Test_enWires[165] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_938 ) ,
+ .Test_en_W_out ( Test_enWires[166] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_939 ) ,
+ .pReset_N_in ( pResetWires[378] ) , .Reset_E_in ( ResetWires[165] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_940 ) ,
+ .Reset_W_out ( ResetWires[166] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_941 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[111] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_942 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[233] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[234] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_943 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_944 ) ,
+ .clk_0_N_in ( clk_1_wires[111] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+grid_clb grid_clb_6__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_946 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[62] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_947 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[62] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_948 } ) ,
+ .ccff_head ( cby_1__1__55_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_67_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_67_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_67_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_67_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_67_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_67_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_67_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_67_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_67_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_67_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_67_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_67_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_67_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_67_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_67_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_67_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_67_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_67_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_67_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_67_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_67_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_67_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_67_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_67_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_67_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_67_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_67_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_67_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_67_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_67_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_67_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_67_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[61] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_949 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[61] ) ,
+ .ccff_tail ( grid_clb_67_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_950 ) , .SC_IN_BOT ( scff_Wires[148] ) ,
+ .SC_OUT_TOP ( scff_Wires[149] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_951 ) ,
+ .Test_en_E_in ( Test_enWires[187] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_952 ) ,
+ .Test_en_W_out ( Test_enWires[188] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_953 ) ,
+ .pReset_N_in ( pResetWires[427] ) , .Reset_E_in ( ResetWires[187] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_954 ) ,
+ .Reset_W_out ( ResetWires[188] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_955 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_956 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[110] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[236] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[237] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_957 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_958 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_959 ) ,
+ .clk_0_S_in ( clk_1_wires[110] ) ) ;
+grid_clb grid_clb_6__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_960 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[63] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_961 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[63] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_962 } ) ,
+ .ccff_head ( cby_1__1__56_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_68_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_68_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_68_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_68_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_68_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_68_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_68_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_68_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_68_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_68_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_68_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_68_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_68_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_68_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_68_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_68_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_68_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_68_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_68_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_68_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_68_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_68_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_68_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_68_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_68_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_68_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_68_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_68_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_68_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_68_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_68_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_68_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[62] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_963 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[62] ) ,
+ .ccff_tail ( grid_clb_68_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_964 ) , .SC_IN_BOT ( scff_Wires[150] ) ,
+ .SC_OUT_TOP ( scff_Wires[151] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_965 ) ,
+ .Test_en_E_in ( Test_enWires[209] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_966 ) ,
+ .Test_en_W_out ( Test_enWires[210] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_967 ) ,
+ .pReset_N_in ( pResetWires[476] ) , .Reset_E_in ( ResetWires[209] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_968 ) ,
+ .Reset_W_out ( ResetWires[210] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_969 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[118] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_970 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[239] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[240] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_971 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_972 ) ,
+ .clk_0_N_in ( clk_1_wires[118] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+grid_clb grid_clb_6__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_974 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[64] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_975 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[64] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_976 } ) ,
+ .ccff_head ( cby_1__1__57_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_69_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_69_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_69_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_69_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_69_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_69_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_69_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_69_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_69_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_69_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_69_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_69_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_69_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_69_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_69_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_69_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_69_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_69_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_69_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_69_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_69_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_69_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_69_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_69_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_69_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_69_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_69_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_69_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_69_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_69_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_69_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_69_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[63] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_977 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[63] ) ,
+ .ccff_tail ( grid_clb_69_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_978 ) , .SC_IN_BOT ( scff_Wires[152] ) ,
+ .SC_OUT_TOP ( scff_Wires[153] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_979 ) ,
+ .Test_en_E_in ( Test_enWires[231] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_980 ) ,
+ .Test_en_W_out ( Test_enWires[232] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_981 ) ,
+ .pReset_N_in ( pResetWires[525] ) , .Reset_E_in ( ResetWires[231] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_982 ) ,
+ .Reset_W_out ( ResetWires[232] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_983 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_984 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[117] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[242] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[243] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_985 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_986 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_987 ) ,
+ .clk_0_S_in ( clk_1_wires[117] ) ) ;
+grid_clb grid_clb_6__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_988 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[65] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_989 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[65] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_990 } ) ,
+ .ccff_head ( cby_1__1__58_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_70_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_70_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_70_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_70_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_70_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_70_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_70_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_70_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_70_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_70_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_70_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_70_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_70_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_70_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_70_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_70_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_70_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_70_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_70_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_70_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_70_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_70_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_70_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_70_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_70_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_70_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_70_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_70_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_70_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_70_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_70_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_70_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[64] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_991 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[64] ) ,
+ .ccff_tail ( grid_clb_70_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_992 ) , .SC_IN_BOT ( scff_Wires[154] ) ,
+ .SC_OUT_TOP ( scff_Wires[155] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_993 ) ,
+ .Test_en_E_in ( Test_enWires[253] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_994 ) ,
+ .Test_en_W_out ( Test_enWires[254] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_995 ) ,
+ .pReset_N_in ( pResetWires[574] ) , .Reset_E_in ( ResetWires[253] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_996 ) ,
+ .Reset_W_out ( ResetWires[254] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_997 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[125] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_998 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[245] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[246] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_999 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1000 ) ,
+ .clk_0_N_in ( clk_1_wires[125] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+grid_clb grid_clb_6__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1002 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1003 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1004 } ) ,
+ .ccff_head ( cby_1__1__59_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_71_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_71_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_71_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_71_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_71_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_71_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_71_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_71_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_71_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_71_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_71_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_71_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_71_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_71_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_71_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_71_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_71_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_71_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_71_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_71_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_71_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_71_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_71_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_71_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_71_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_71_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_71_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_71_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_71_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_71_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_71_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_71_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[65] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1005 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[65] ) ,
+ .ccff_tail ( grid_clb_71_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1006 ) ,
+ .SC_IN_BOT ( scff_Wires[156] ) , .SC_OUT_TOP ( scff_Wires[157] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1007 ) ,
+ .Test_en_E_in ( Test_enWires[275] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_1008 ) ,
+ .Test_en_W_out ( Test_enWires[276] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1009 ) ,
+ .pReset_N_in ( pResetWires[618] ) , .Reset_E_in ( ResetWires[275] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_1010 ) ,
+ .Reset_W_out ( ResetWires[276] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1011 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1012 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[124] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[248] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[249] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1013 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[251] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1014 ) ,
+ .clk_0_S_in ( clk_1_wires[124] ) ) ;
+grid_clb grid_clb_7__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1015 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[66] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1016 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[66] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1017 } ) ,
+ .ccff_head ( cby_1__1__60_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_72_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_72_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_72_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_72_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_72_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_72_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_72_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_72_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_72_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_72_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_72_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_72_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_72_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_72_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_72_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_72_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_72_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_72_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_72_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_72_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_72_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_72_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_72_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_72_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_72_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_72_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_72_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_72_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_72_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_72_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_72_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_72_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1018 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[182] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1019 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1020 ) ,
+ .SC_OUT_BOT ( scff_Wires[184] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1021 ) ,
+ .Test_en_W_in ( Test_enWires[35] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1022 ) ,
+ .Test_en_E_out ( Test_enWires[36] ) , .pReset_N_in ( pResetWires[88] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1023 ) ,
+ .Reset_W_in ( ResetWires[35] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1024 ) ,
+ .Reset_E_out ( ResetWires[36] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[130] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1025 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[253] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[254] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1026 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1027 ) ,
+ .clk_0_N_in ( clk_1_wires[130] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+grid_clb grid_clb_7__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1029 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[67] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1030 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[67] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1031 } ) ,
+ .ccff_head ( cby_1__1__61_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_73_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_73_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_73_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_73_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_73_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_73_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_73_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_73_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_73_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_73_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_73_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_73_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_73_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_73_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_73_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_73_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_73_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_73_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_73_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_73_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_73_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_73_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_73_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_73_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_73_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_73_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_73_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_73_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_73_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_73_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_73_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_73_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[66] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1032 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[66] ) ,
+ .ccff_tail ( grid_clb_73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[180] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1033 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1034 ) ,
+ .SC_OUT_BOT ( scff_Wires[181] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1035 ) ,
+ .Test_en_W_in ( Test_enWires[57] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1036 ) ,
+ .Test_en_E_out ( Test_enWires[58] ) , .pReset_N_in ( pResetWires[137] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1037 ) ,
+ .Reset_W_in ( ResetWires[57] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1038 ) ,
+ .Reset_E_out ( ResetWires[58] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1039 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[129] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[256] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[257] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1040 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1041 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1042 ) ,
+ .clk_0_S_in ( clk_1_wires[129] ) ) ;
+grid_clb grid_clb_7__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1043 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[68] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1044 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[68] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1045 } ) ,
+ .ccff_head ( cby_1__1__62_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_74_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_74_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_74_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_74_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_74_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_74_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_74_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_74_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_74_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_74_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_74_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_74_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_74_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_74_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_74_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_74_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_74_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_74_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_74_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_74_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_74_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_74_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_74_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_74_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_74_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_74_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_74_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_74_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_74_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_74_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_74_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_74_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[67] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1046 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[67] ) ,
+ .ccff_tail ( grid_clb_74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[178] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1047 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1048 ) ,
+ .SC_OUT_BOT ( scff_Wires[179] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1049 ) ,
+ .Test_en_W_in ( Test_enWires[79] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1050 ) ,
+ .Test_en_E_out ( Test_enWires[80] ) , .pReset_N_in ( pResetWires[186] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1051 ) ,
+ .Reset_W_in ( ResetWires[79] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1052 ) ,
+ .Reset_E_out ( ResetWires[80] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[137] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1053 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[259] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[260] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1054 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1055 ) ,
+ .clk_0_N_in ( clk_1_wires[137] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+grid_clb grid_clb_7__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1057 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[69] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1058 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[69] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1059 } ) ,
+ .ccff_head ( cby_1__1__63_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_75_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_75_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_75_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_75_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_75_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_75_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_75_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_75_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_75_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_75_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_75_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_75_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_75_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_75_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_75_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_75_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_75_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_75_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_75_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_75_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_75_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_75_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_75_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_75_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_75_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_75_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_75_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_75_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_75_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_75_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_75_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_75_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[68] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1060 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[68] ) ,
+ .ccff_tail ( grid_clb_75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[176] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1061 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1062 ) ,
+ .SC_OUT_BOT ( scff_Wires[177] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1063 ) ,
+ .Test_en_W_in ( Test_enWires[101] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1064 ) ,
+ .Test_en_E_out ( Test_enWires[102] ) , .pReset_N_in ( pResetWires[235] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1065 ) ,
+ .Reset_W_in ( ResetWires[101] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1066 ) ,
+ .Reset_E_out ( ResetWires[102] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1067 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[136] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[262] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[263] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1068 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1069 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1070 ) ,
+ .clk_0_S_in ( clk_1_wires[136] ) ) ;
+grid_clb grid_clb_7__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1071 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[70] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1072 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[70] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1073 } ) ,
+ .ccff_head ( cby_1__1__64_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_76_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_76_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_76_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_76_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_76_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_76_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_76_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_76_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_76_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_76_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_76_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_76_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_76_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_76_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_76_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_76_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_76_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_76_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_76_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_76_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_76_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_76_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_76_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_76_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_76_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_76_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_76_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_76_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_76_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_76_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_76_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_76_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[69] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1074 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[69] ) ,
+ .ccff_tail ( grid_clb_76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[174] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1075 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1076 ) ,
+ .SC_OUT_BOT ( scff_Wires[175] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1077 ) ,
+ .Test_en_W_in ( Test_enWires[123] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1078 ) ,
+ .Test_en_E_out ( Test_enWires[124] ) , .pReset_N_in ( pResetWires[284] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1079 ) ,
+ .Reset_W_in ( ResetWires[123] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1080 ) ,
+ .Reset_E_out ( ResetWires[124] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[144] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1081 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[265] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[266] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1082 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1083 ) ,
+ .clk_0_N_in ( clk_1_wires[144] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+grid_clb grid_clb_7__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1085 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[71] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1086 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[71] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1087 } ) ,
+ .ccff_head ( cby_1__1__65_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_77_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_77_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_77_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_77_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_77_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_77_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_77_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_77_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_77_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_77_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_77_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_77_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_77_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_77_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_77_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_77_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_77_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_77_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_77_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_77_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_77_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_77_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_77_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_77_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_77_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_77_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_77_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_77_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_77_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_77_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_77_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_77_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[70] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1088 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[70] ) ,
+ .ccff_tail ( grid_clb_77_ccff_tail ) , .SC_IN_TOP ( scff_Wires[172] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1089 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1090 ) ,
+ .SC_OUT_BOT ( scff_Wires[173] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1091 ) ,
+ .Test_en_W_in ( Test_enWires[145] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1092 ) ,
+ .Test_en_E_out ( Test_enWires[146] ) , .pReset_N_in ( pResetWires[333] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1093 ) ,
+ .Reset_W_in ( ResetWires[145] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1094 ) ,
+ .Reset_E_out ( ResetWires[146] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1095 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[143] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[268] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[269] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1096 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1097 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1098 ) ,
+ .clk_0_S_in ( clk_1_wires[143] ) ) ;
+grid_clb grid_clb_7__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1099 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[72] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1100 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[72] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1101 } ) ,
+ .ccff_head ( cby_1__1__66_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_78_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_78_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_78_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_78_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_78_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_78_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_78_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_78_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_78_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_78_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_78_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_78_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_78_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_78_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_78_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_78_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_78_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_78_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_78_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_78_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_78_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_78_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_78_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_78_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_78_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_78_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_78_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_78_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_78_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_78_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_78_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_78_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[71] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1102 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[71] ) ,
+ .ccff_tail ( grid_clb_78_ccff_tail ) , .SC_IN_TOP ( scff_Wires[170] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1103 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1104 ) ,
+ .SC_OUT_BOT ( scff_Wires[171] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1105 ) ,
+ .Test_en_W_in ( Test_enWires[167] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1106 ) ,
+ .Test_en_E_out ( Test_enWires[168] ) , .pReset_N_in ( pResetWires[382] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1107 ) ,
+ .Reset_W_in ( ResetWires[167] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1108 ) ,
+ .Reset_E_out ( ResetWires[168] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[151] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1109 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[271] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[272] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1110 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1111 ) ,
+ .clk_0_N_in ( clk_1_wires[151] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+grid_clb grid_clb_7__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1113 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[73] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1114 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[73] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1115 } ) ,
+ .ccff_head ( cby_1__1__67_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_79_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_79_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_79_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_79_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_79_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_79_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_79_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_79_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_79_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_79_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_79_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_79_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_79_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_79_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_79_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_79_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_79_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_79_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_79_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_79_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_79_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_79_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_79_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_79_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_79_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_79_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_79_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_79_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_79_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_79_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_79_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_79_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[72] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1116 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[72] ) ,
+ .ccff_tail ( grid_clb_79_ccff_tail ) , .SC_IN_TOP ( scff_Wires[168] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1117 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1118 ) ,
+ .SC_OUT_BOT ( scff_Wires[169] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1119 ) ,
+ .Test_en_W_in ( Test_enWires[189] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1120 ) ,
+ .Test_en_E_out ( Test_enWires[190] ) , .pReset_N_in ( pResetWires[431] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1121 ) ,
+ .Reset_W_in ( ResetWires[189] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1122 ) ,
+ .Reset_E_out ( ResetWires[190] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1123 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[150] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[274] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[275] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1124 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1125 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1126 ) ,
+ .clk_0_S_in ( clk_1_wires[150] ) ) ;
+grid_clb grid_clb_7__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1127 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[74] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1128 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[74] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1129 } ) ,
+ .ccff_head ( cby_1__1__68_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_80_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_80_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_80_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_80_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_80_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_80_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_80_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_80_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_80_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_80_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_80_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_80_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_80_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_80_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_80_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_80_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_80_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_80_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_80_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_80_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_80_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_80_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_80_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_80_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_80_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_80_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_80_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_80_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_80_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_80_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_80_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_80_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[73] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1130 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[73] ) ,
+ .ccff_tail ( grid_clb_80_ccff_tail ) , .SC_IN_TOP ( scff_Wires[166] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1131 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1132 ) ,
+ .SC_OUT_BOT ( scff_Wires[167] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1133 ) ,
+ .Test_en_W_in ( Test_enWires[211] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1134 ) ,
+ .Test_en_E_out ( Test_enWires[212] ) , .pReset_N_in ( pResetWires[480] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1135 ) ,
+ .Reset_W_in ( ResetWires[211] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1136 ) ,
+ .Reset_E_out ( ResetWires[212] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[158] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1137 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[277] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[278] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1138 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1139 ) ,
+ .clk_0_N_in ( clk_1_wires[158] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+grid_clb grid_clb_7__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1141 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[75] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1142 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[75] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1143 } ) ,
+ .ccff_head ( cby_1__1__69_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_81_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_81_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_81_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_81_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_81_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_81_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_81_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_81_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_81_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_81_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_81_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_81_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_81_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_81_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_81_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_81_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_81_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_81_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_81_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_81_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_81_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_81_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_81_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_81_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_81_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_81_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_81_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_81_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_81_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_81_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_81_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_81_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[74] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1144 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[74] ) ,
+ .ccff_tail ( grid_clb_81_ccff_tail ) , .SC_IN_TOP ( scff_Wires[164] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1145 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1146 ) ,
+ .SC_OUT_BOT ( scff_Wires[165] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1147 ) ,
+ .Test_en_W_in ( Test_enWires[233] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1148 ) ,
+ .Test_en_E_out ( Test_enWires[234] ) , .pReset_N_in ( pResetWires[529] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1149 ) ,
+ .Reset_W_in ( ResetWires[233] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1150 ) ,
+ .Reset_E_out ( ResetWires[234] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1151 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[157] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[280] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[281] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1152 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1153 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1154 ) ,
+ .clk_0_S_in ( clk_1_wires[157] ) ) ;
+grid_clb grid_clb_7__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1155 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[76] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1156 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[76] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1157 } ) ,
+ .ccff_head ( cby_1__1__70_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_82_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_82_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_82_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_82_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_82_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_82_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_82_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_82_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_82_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_82_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_82_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_82_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_82_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_82_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_82_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_82_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_82_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_82_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_82_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_82_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_82_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_82_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_82_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_82_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_82_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_82_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_82_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_82_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_82_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_82_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_82_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_82_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[75] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1158 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[75] ) ,
+ .ccff_tail ( grid_clb_82_ccff_tail ) , .SC_IN_TOP ( scff_Wires[162] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1159 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1160 ) ,
+ .SC_OUT_BOT ( scff_Wires[163] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1161 ) ,
+ .Test_en_W_in ( Test_enWires[255] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1162 ) ,
+ .Test_en_E_out ( Test_enWires[256] ) , .pReset_N_in ( pResetWires[578] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1163 ) ,
+ .Reset_W_in ( ResetWires[255] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1164 ) ,
+ .Reset_E_out ( ResetWires[256] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[165] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1165 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[283] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[284] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1166 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1167 ) ,
+ .clk_0_N_in ( clk_1_wires[165] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+grid_clb grid_clb_7__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1169 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1170 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1171 } ) ,
+ .ccff_head ( cby_1__1__71_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_83_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_83_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_83_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_83_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_83_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_83_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_83_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_83_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_83_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_83_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_83_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_83_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_83_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_83_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_83_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_83_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_83_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_83_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_83_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_83_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_83_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_83_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_83_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_83_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_83_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_83_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_83_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_83_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_83_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_83_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_83_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_83_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[76] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1172 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[76] ) ,
+ .ccff_tail ( grid_clb_83_ccff_tail ) , .SC_IN_TOP ( scff_Wires[160] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1173 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1174 ) ,
+ .SC_OUT_BOT ( scff_Wires[161] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1175 ) ,
+ .Test_en_W_in ( Test_enWires[277] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1176 ) ,
+ .Test_en_E_out ( Test_enWires[278] ) , .pReset_N_in ( pResetWires[621] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1177 ) ,
+ .Reset_W_in ( ResetWires[277] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1178 ) ,
+ .Reset_E_out ( ResetWires[278] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1179 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[164] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[286] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[287] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1180 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[289] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1181 ) ,
+ .clk_0_S_in ( clk_1_wires[164] ) ) ;
+grid_clb grid_clb_8__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1182 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[77] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1183 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[77] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1184 } ) ,
+ .ccff_head ( cby_1__1__72_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_84_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_84_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_84_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_84_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_84_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_84_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_84_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_84_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_84_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_84_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_84_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_84_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_84_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_84_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_84_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_84_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_84_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_84_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_84_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_84_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_84_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_84_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_84_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_84_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_84_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_84_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_84_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_84_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_84_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_84_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_84_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_84_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1185 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_84_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1186 ) ,
+ .SC_IN_BOT ( scff_Wires[187] ) , .SC_OUT_TOP ( scff_Wires[188] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1187 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1188 ) ,
+ .Test_en_W_in ( Test_enWires[37] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1189 ) ,
+ .Test_en_E_out ( Test_enWires[38] ) , .pReset_N_in ( pResetWires[92] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1190 ) ,
+ .Reset_W_in ( ResetWires[37] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1191 ) ,
+ .Reset_E_out ( ResetWires[38] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[132] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1192 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[291] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[292] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1193 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1194 ) ,
+ .clk_0_N_in ( clk_1_wires[132] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+grid_clb grid_clb_8__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1196 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[78] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1197 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[78] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1198 } ) ,
+ .ccff_head ( cby_1__1__73_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_85_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_85_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_85_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_85_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_85_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_85_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_85_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_85_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_85_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_85_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_85_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_85_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_85_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_85_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_85_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_85_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_85_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_85_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_85_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_85_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_85_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_85_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_85_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_85_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_85_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_85_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_85_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_85_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_85_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_85_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_85_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_85_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[77] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1199 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[77] ) ,
+ .ccff_tail ( grid_clb_85_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1200 ) ,
+ .SC_IN_BOT ( scff_Wires[189] ) , .SC_OUT_TOP ( scff_Wires[190] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1201 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1202 ) ,
+ .Test_en_W_in ( Test_enWires[59] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1203 ) ,
+ .Test_en_E_out ( Test_enWires[60] ) , .pReset_N_in ( pResetWires[141] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1204 ) ,
+ .Reset_W_in ( ResetWires[59] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1205 ) ,
+ .Reset_E_out ( ResetWires[60] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1206 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[131] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[294] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[295] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1207 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1208 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1209 ) ,
+ .clk_0_S_in ( clk_1_wires[131] ) ) ;
+grid_clb grid_clb_8__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1210 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[79] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1211 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[79] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1212 } ) ,
+ .ccff_head ( cby_1__1__74_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_86_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_86_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_86_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_86_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_86_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_86_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_86_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_86_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_86_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_86_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_86_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_86_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_86_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_86_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_86_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_86_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_86_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_86_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_86_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_86_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_86_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_86_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_86_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_86_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_86_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_86_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_86_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_86_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_86_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_86_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_86_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_86_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[78] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1213 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[78] ) ,
+ .ccff_tail ( grid_clb_86_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1214 ) ,
+ .SC_IN_BOT ( scff_Wires[191] ) , .SC_OUT_TOP ( scff_Wires[192] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1215 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1216 ) ,
+ .Test_en_W_in ( Test_enWires[81] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1217 ) ,
+ .Test_en_E_out ( Test_enWires[82] ) , .pReset_N_in ( pResetWires[190] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1218 ) ,
+ .Reset_W_in ( ResetWires[81] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1219 ) ,
+ .Reset_E_out ( ResetWires[82] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[139] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1220 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[297] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[298] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1221 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1222 ) ,
+ .clk_0_N_in ( clk_1_wires[139] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+grid_clb grid_clb_8__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1224 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[80] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1225 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[80] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1226 } ) ,
+ .ccff_head ( cby_1__1__75_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_87_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_87_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_87_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_87_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_87_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_87_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_87_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_87_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_87_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_87_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_87_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_87_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_87_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_87_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_87_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_87_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_87_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_87_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_87_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_87_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_87_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_87_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_87_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_87_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_87_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_87_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_87_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_87_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_87_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_87_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_87_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_87_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[79] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1227 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[79] ) ,
+ .ccff_tail ( grid_clb_87_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1228 ) ,
+ .SC_IN_BOT ( scff_Wires[193] ) , .SC_OUT_TOP ( scff_Wires[194] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1229 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1230 ) ,
+ .Test_en_W_in ( Test_enWires[103] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1231 ) ,
+ .Test_en_E_out ( Test_enWires[104] ) , .pReset_N_in ( pResetWires[239] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1232 ) ,
+ .Reset_W_in ( ResetWires[103] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1233 ) ,
+ .Reset_E_out ( ResetWires[104] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1234 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[138] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[300] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[301] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1235 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1236 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1237 ) ,
+ .clk_0_S_in ( clk_1_wires[138] ) ) ;
+grid_clb grid_clb_8__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1238 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[81] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1239 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[81] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1240 } ) ,
+ .ccff_head ( cby_1__1__76_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_88_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_88_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_88_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_88_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_88_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_88_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_88_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_88_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_88_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_88_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_88_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_88_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_88_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_88_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_88_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_88_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_88_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_88_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_88_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_88_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_88_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_88_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_88_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_88_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_88_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_88_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_88_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_88_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_88_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_88_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_88_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_88_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[80] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1241 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[80] ) ,
+ .ccff_tail ( grid_clb_88_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1242 ) ,
+ .SC_IN_BOT ( scff_Wires[195] ) , .SC_OUT_TOP ( scff_Wires[196] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1243 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1244 ) ,
+ .Test_en_W_in ( Test_enWires[125] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1245 ) ,
+ .Test_en_E_out ( Test_enWires[126] ) , .pReset_N_in ( pResetWires[288] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1246 ) ,
+ .Reset_W_in ( ResetWires[125] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1247 ) ,
+ .Reset_E_out ( ResetWires[126] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[146] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1248 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[303] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[304] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1249 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1250 ) ,
+ .clk_0_N_in ( clk_1_wires[146] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+grid_clb grid_clb_8__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1252 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[82] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1253 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[82] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1254 } ) ,
+ .ccff_head ( cby_1__1__77_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_89_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_89_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_89_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_89_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_89_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_89_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_89_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_89_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_89_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_89_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_89_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_89_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_89_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_89_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_89_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_89_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_89_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_89_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_89_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_89_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_89_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_89_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_89_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_89_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_89_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_89_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_89_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_89_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_89_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_89_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_89_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_89_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[81] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1255 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[81] ) ,
+ .ccff_tail ( grid_clb_89_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1256 ) ,
+ .SC_IN_BOT ( scff_Wires[197] ) , .SC_OUT_TOP ( scff_Wires[198] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1257 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1258 ) ,
+ .Test_en_W_in ( Test_enWires[147] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1259 ) ,
+ .Test_en_E_out ( Test_enWires[148] ) , .pReset_N_in ( pResetWires[337] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1260 ) ,
+ .Reset_W_in ( ResetWires[147] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1261 ) ,
+ .Reset_E_out ( ResetWires[148] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1262 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[145] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[306] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[307] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1263 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1264 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1265 ) ,
+ .clk_0_S_in ( clk_1_wires[145] ) ) ;
+grid_clb grid_clb_8__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1266 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[83] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1267 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[83] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1268 } ) ,
+ .ccff_head ( cby_1__1__78_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_90_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_90_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_90_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_90_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_90_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_90_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_90_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_90_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_90_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_90_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_90_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_90_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_90_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_90_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_90_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_90_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_90_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_90_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_90_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_90_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_90_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_90_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_90_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_90_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_90_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_90_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_90_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_90_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_90_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_90_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_90_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_90_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[82] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1269 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[82] ) ,
+ .ccff_tail ( grid_clb_90_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1270 ) ,
+ .SC_IN_BOT ( scff_Wires[199] ) , .SC_OUT_TOP ( scff_Wires[200] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1271 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1272 ) ,
+ .Test_en_W_in ( Test_enWires[169] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1273 ) ,
+ .Test_en_E_out ( Test_enWires[170] ) , .pReset_N_in ( pResetWires[386] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1274 ) ,
+ .Reset_W_in ( ResetWires[169] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1275 ) ,
+ .Reset_E_out ( ResetWires[170] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[153] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1276 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[309] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[310] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1277 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1278 ) ,
+ .clk_0_N_in ( clk_1_wires[153] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+grid_clb grid_clb_8__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1280 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[84] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1281 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[84] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1282 } ) ,
+ .ccff_head ( cby_1__1__79_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_91_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_91_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_91_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_91_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_91_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_91_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_91_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_91_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_91_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_91_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_91_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_91_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_91_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_91_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_91_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_91_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_91_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_91_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_91_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_91_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_91_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_91_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_91_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_91_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_91_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_91_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_91_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_91_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_91_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_91_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_91_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_91_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[83] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1283 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[83] ) ,
+ .ccff_tail ( grid_clb_91_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1284 ) ,
+ .SC_IN_BOT ( scff_Wires[201] ) , .SC_OUT_TOP ( scff_Wires[202] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1285 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1286 ) ,
+ .Test_en_W_in ( Test_enWires[191] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1287 ) ,
+ .Test_en_E_out ( Test_enWires[192] ) , .pReset_N_in ( pResetWires[435] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1288 ) ,
+ .Reset_W_in ( ResetWires[191] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1289 ) ,
+ .Reset_E_out ( ResetWires[192] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1290 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[152] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[312] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[313] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1291 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1292 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1293 ) ,
+ .clk_0_S_in ( clk_1_wires[152] ) ) ;
+grid_clb grid_clb_8__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1294 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[85] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1295 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[85] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1296 } ) ,
+ .ccff_head ( cby_1__1__80_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_92_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_92_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_92_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_92_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_92_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_92_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_92_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_92_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_92_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_92_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_92_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_92_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_92_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_92_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_92_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_92_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_92_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_92_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_92_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_92_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_92_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_92_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_92_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_92_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_92_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_92_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_92_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_92_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_92_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_92_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_92_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_92_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[84] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1297 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[84] ) ,
+ .ccff_tail ( grid_clb_92_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1298 ) ,
+ .SC_IN_BOT ( scff_Wires[203] ) , .SC_OUT_TOP ( scff_Wires[204] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1299 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1300 ) ,
+ .Test_en_W_in ( Test_enWires[213] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1301 ) ,
+ .Test_en_E_out ( Test_enWires[214] ) , .pReset_N_in ( pResetWires[484] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1302 ) ,
+ .Reset_W_in ( ResetWires[213] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1303 ) ,
+ .Reset_E_out ( ResetWires[214] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[160] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1304 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[315] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[316] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1305 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1306 ) ,
+ .clk_0_N_in ( clk_1_wires[160] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+grid_clb grid_clb_8__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1308 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[86] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1309 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[86] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1310 } ) ,
+ .ccff_head ( cby_1__1__81_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_93_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_93_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_93_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_93_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_93_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_93_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_93_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_93_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_93_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_93_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_93_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_93_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_93_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_93_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_93_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_93_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_93_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_93_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_93_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_93_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_93_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_93_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_93_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_93_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_93_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_93_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_93_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_93_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_93_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_93_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_93_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_93_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[85] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1311 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[85] ) ,
+ .ccff_tail ( grid_clb_93_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1312 ) ,
+ .SC_IN_BOT ( scff_Wires[205] ) , .SC_OUT_TOP ( scff_Wires[206] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1313 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1314 ) ,
+ .Test_en_W_in ( Test_enWires[235] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1315 ) ,
+ .Test_en_E_out ( Test_enWires[236] ) , .pReset_N_in ( pResetWires[533] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1316 ) ,
+ .Reset_W_in ( ResetWires[235] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1317 ) ,
+ .Reset_E_out ( ResetWires[236] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1318 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[159] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[318] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[319] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1319 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1320 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1321 ) ,
+ .clk_0_S_in ( clk_1_wires[159] ) ) ;
+grid_clb grid_clb_8__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1322 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[87] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1323 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[87] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1324 } ) ,
+ .ccff_head ( cby_1__1__82_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_94_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_94_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_94_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_94_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_94_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_94_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_94_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_94_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_94_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_94_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_94_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_94_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_94_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_94_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_94_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_94_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_94_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_94_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_94_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_94_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_94_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_94_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_94_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_94_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_94_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_94_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_94_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_94_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_94_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_94_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_94_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_94_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[86] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1325 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[86] ) ,
+ .ccff_tail ( grid_clb_94_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1326 ) ,
+ .SC_IN_BOT ( scff_Wires[207] ) , .SC_OUT_TOP ( scff_Wires[208] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1327 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1328 ) ,
+ .Test_en_W_in ( Test_enWires[257] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1329 ) ,
+ .Test_en_E_out ( Test_enWires[258] ) , .pReset_N_in ( pResetWires[582] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1330 ) ,
+ .Reset_W_in ( ResetWires[257] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1331 ) ,
+ .Reset_E_out ( ResetWires[258] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[167] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1332 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[321] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[322] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1333 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1334 ) ,
+ .clk_0_N_in ( clk_1_wires[167] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+grid_clb grid_clb_8__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1336 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1337 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1338 } ) ,
+ .ccff_head ( cby_1__1__83_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_95_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_95_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_95_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_95_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_95_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_95_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_95_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_95_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_95_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_95_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_95_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_95_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_95_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_95_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_95_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_95_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_95_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_95_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_95_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_95_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_95_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_95_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_95_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_95_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_95_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_95_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_95_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_95_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_95_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_95_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_95_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_95_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[87] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1339 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[87] ) ,
+ .ccff_tail ( grid_clb_95_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1340 ) ,
+ .SC_IN_BOT ( scff_Wires[209] ) , .SC_OUT_TOP ( scff_Wires[210] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1341 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1342 ) ,
+ .Test_en_W_in ( Test_enWires[279] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1343 ) ,
+ .Test_en_E_out ( Test_enWires[280] ) , .pReset_N_in ( pResetWires[624] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1344 ) ,
+ .Reset_W_in ( ResetWires[279] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1345 ) ,
+ .Reset_E_out ( ResetWires[280] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1346 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[166] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[324] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[325] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1347 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[327] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1348 ) ,
+ .clk_0_S_in ( clk_1_wires[166] ) ) ;
+grid_clb grid_clb_9__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1349 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[88] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1350 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[88] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1351 } ) ,
+ .ccff_head ( cby_1__1__84_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_96_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_96_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_96_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_96_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_96_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_96_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_96_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_96_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_96_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_96_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_96_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_96_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_96_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_96_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_96_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_96_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_96_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_96_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_96_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_96_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_96_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_96_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_96_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_96_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_96_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_96_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_96_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_96_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_96_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_96_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_96_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_96_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1352 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[235] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1353 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1354 ) ,
+ .SC_OUT_BOT ( scff_Wires[237] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1355 ) ,
+ .Test_en_W_in ( Test_enWires[39] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1356 ) ,
+ .Test_en_E_out ( Test_enWires[40] ) , .pReset_N_in ( pResetWires[96] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1357 ) ,
+ .Reset_W_in ( ResetWires[39] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1358 ) ,
+ .Reset_E_out ( ResetWires[40] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[172] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1359 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[329] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[330] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1360 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1361 ) ,
+ .clk_0_N_in ( clk_1_wires[172] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+grid_clb grid_clb_9__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1363 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[89] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1364 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[89] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1365 } ) ,
+ .ccff_head ( cby_1__1__85_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_97_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_97_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_97_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_97_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_97_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_97_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_97_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_97_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_97_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_97_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_97_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_97_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_97_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_97_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_97_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_97_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_97_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_97_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_97_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_97_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_97_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_97_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_97_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_97_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_97_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_97_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_97_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_97_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_97_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_97_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_97_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_97_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[88] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1366 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[88] ) ,
+ .ccff_tail ( grid_clb_97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[233] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1367 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1368 ) ,
+ .SC_OUT_BOT ( scff_Wires[234] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1369 ) ,
+ .Test_en_W_in ( Test_enWires[61] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1370 ) ,
+ .Test_en_E_out ( Test_enWires[62] ) , .pReset_N_in ( pResetWires[145] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1371 ) ,
+ .Reset_W_in ( ResetWires[61] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1372 ) ,
+ .Reset_E_out ( ResetWires[62] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1373 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[171] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[332] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[333] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1374 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1375 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1376 ) ,
+ .clk_0_S_in ( clk_1_wires[171] ) ) ;
+grid_clb grid_clb_9__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1377 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[90] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1378 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[90] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1379 } ) ,
+ .ccff_head ( cby_1__1__86_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_98_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_98_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_98_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_98_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_98_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_98_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_98_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_98_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_98_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_98_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_98_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_98_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_98_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_98_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_98_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_98_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_98_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_98_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_98_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_98_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_98_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_98_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_98_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_98_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_98_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_98_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_98_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_98_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_98_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_98_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_98_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_98_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[89] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1380 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[89] ) ,
+ .ccff_tail ( grid_clb_98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[231] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1381 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1382 ) ,
+ .SC_OUT_BOT ( scff_Wires[232] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1383 ) ,
+ .Test_en_W_in ( Test_enWires[83] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1384 ) ,
+ .Test_en_E_out ( Test_enWires[84] ) , .pReset_N_in ( pResetWires[194] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1385 ) ,
+ .Reset_W_in ( ResetWires[83] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1386 ) ,
+ .Reset_E_out ( ResetWires[84] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[179] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1387 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[335] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[336] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1388 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1389 ) ,
+ .clk_0_N_in ( clk_1_wires[179] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+grid_clb grid_clb_9__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1391 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[91] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1392 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[91] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1393 } ) ,
+ .ccff_head ( cby_1__1__87_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_99_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_99_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_99_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_99_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_99_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_99_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_99_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_99_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_99_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_99_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_99_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_99_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_99_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_99_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_99_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_99_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_99_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_99_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_99_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_99_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_99_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_99_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_99_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_99_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_99_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_99_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_99_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_99_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_99_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_99_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_99_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_99_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[90] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1394 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[90] ) ,
+ .ccff_tail ( grid_clb_99_ccff_tail ) , .SC_IN_TOP ( scff_Wires[229] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1395 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1396 ) ,
+ .SC_OUT_BOT ( scff_Wires[230] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1397 ) ,
+ .Test_en_W_in ( Test_enWires[105] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1398 ) ,
+ .Test_en_E_out ( Test_enWires[106] ) , .pReset_N_in ( pResetWires[243] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1399 ) ,
+ .Reset_W_in ( ResetWires[105] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1400 ) ,
+ .Reset_E_out ( ResetWires[106] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1401 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[178] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[338] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[339] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1402 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1403 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1404 ) ,
+ .clk_0_S_in ( clk_1_wires[178] ) ) ;
+grid_clb grid_clb_9__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1405 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[92] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1406 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[92] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1407 } ) ,
+ .ccff_head ( cby_1__1__88_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_100_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_100_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_100_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_100_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_100_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_100_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_100_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_100_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_100_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_100_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_100_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_100_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_100_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_100_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_100_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_100_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_100_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_100_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_100_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_100_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_100_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_100_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_100_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_100_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_100_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_100_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_100_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_100_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_100_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_100_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_100_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_100_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[91] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1408 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[91] ) ,
+ .ccff_tail ( grid_clb_100_ccff_tail ) , .SC_IN_TOP ( scff_Wires[227] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1409 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1410 ) ,
+ .SC_OUT_BOT ( scff_Wires[228] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1411 ) ,
+ .Test_en_W_in ( Test_enWires[127] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1412 ) ,
+ .Test_en_E_out ( Test_enWires[128] ) , .pReset_N_in ( pResetWires[292] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1413 ) ,
+ .Reset_W_in ( ResetWires[127] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1414 ) ,
+ .Reset_E_out ( ResetWires[128] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[186] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1415 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[341] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[342] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1416 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1417 ) ,
+ .clk_0_N_in ( clk_1_wires[186] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+grid_clb grid_clb_9__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1419 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[93] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1420 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[93] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1421 } ) ,
+ .ccff_head ( cby_1__1__89_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_101_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_101_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_101_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_101_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_101_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_101_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_101_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_101_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_101_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_101_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_101_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_101_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_101_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_101_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_101_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_101_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_101_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_101_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_101_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_101_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_101_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_101_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_101_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_101_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_101_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_101_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_101_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_101_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_101_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_101_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_101_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_101_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[92] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1422 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[92] ) ,
+ .ccff_tail ( grid_clb_101_ccff_tail ) , .SC_IN_TOP ( scff_Wires[225] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1423 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1424 ) ,
+ .SC_OUT_BOT ( scff_Wires[226] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1425 ) ,
+ .Test_en_W_in ( Test_enWires[149] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1426 ) ,
+ .Test_en_E_out ( Test_enWires[150] ) , .pReset_N_in ( pResetWires[341] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1427 ) ,
+ .Reset_W_in ( ResetWires[149] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1428 ) ,
+ .Reset_E_out ( ResetWires[150] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1429 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[185] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[344] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[345] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1430 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1431 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1432 ) ,
+ .clk_0_S_in ( clk_1_wires[185] ) ) ;
+grid_clb grid_clb_9__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1433 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[94] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1434 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[94] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1435 } ) ,
+ .ccff_head ( cby_1__1__90_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_102_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_102_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_102_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_102_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_102_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_102_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_102_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_102_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_102_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_102_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_102_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_102_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_102_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_102_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_102_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_102_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_102_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_102_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_102_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_102_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_102_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_102_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_102_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_102_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_102_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_102_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_102_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_102_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_102_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_102_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_102_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_102_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[93] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1436 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[93] ) ,
+ .ccff_tail ( grid_clb_102_ccff_tail ) , .SC_IN_TOP ( scff_Wires[223] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1437 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1438 ) ,
+ .SC_OUT_BOT ( scff_Wires[224] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1439 ) ,
+ .Test_en_W_in ( Test_enWires[171] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1440 ) ,
+ .Test_en_E_out ( Test_enWires[172] ) , .pReset_N_in ( pResetWires[390] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1441 ) ,
+ .Reset_W_in ( ResetWires[171] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1442 ) ,
+ .Reset_E_out ( ResetWires[172] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[193] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1443 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[347] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[348] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1444 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1445 ) ,
+ .clk_0_N_in ( clk_1_wires[193] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+grid_clb grid_clb_9__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1447 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[95] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1448 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[95] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1449 } ) ,
+ .ccff_head ( cby_1__1__91_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_103_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_103_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_103_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_103_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_103_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_103_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_103_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_103_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_103_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_103_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_103_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_103_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_103_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_103_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_103_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_103_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_103_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_103_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_103_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_103_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_103_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_103_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_103_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_103_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_103_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_103_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_103_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_103_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_103_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_103_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_103_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_103_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[94] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1450 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[94] ) ,
+ .ccff_tail ( grid_clb_103_ccff_tail ) , .SC_IN_TOP ( scff_Wires[221] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1451 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1452 ) ,
+ .SC_OUT_BOT ( scff_Wires[222] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1453 ) ,
+ .Test_en_W_in ( Test_enWires[193] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1454 ) ,
+ .Test_en_E_out ( Test_enWires[194] ) , .pReset_N_in ( pResetWires[439] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1455 ) ,
+ .Reset_W_in ( ResetWires[193] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1456 ) ,
+ .Reset_E_out ( ResetWires[194] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1457 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[192] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[350] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[351] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1458 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1459 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1460 ) ,
+ .clk_0_S_in ( clk_1_wires[192] ) ) ;
+grid_clb grid_clb_9__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1461 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[96] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1462 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[96] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1463 } ) ,
+ .ccff_head ( cby_1__1__92_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_104_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_104_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_104_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_104_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_104_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_104_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_104_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_104_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_104_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_104_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_104_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_104_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_104_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_104_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_104_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_104_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_104_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_104_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_104_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_104_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_104_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_104_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_104_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_104_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_104_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_104_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_104_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_104_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_104_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_104_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_104_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_104_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[95] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1464 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[95] ) ,
+ .ccff_tail ( grid_clb_104_ccff_tail ) , .SC_IN_TOP ( scff_Wires[219] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1465 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1466 ) ,
+ .SC_OUT_BOT ( scff_Wires[220] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1467 ) ,
+ .Test_en_W_in ( Test_enWires[215] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1468 ) ,
+ .Test_en_E_out ( Test_enWires[216] ) , .pReset_N_in ( pResetWires[488] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1469 ) ,
+ .Reset_W_in ( ResetWires[215] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1470 ) ,
+ .Reset_E_out ( ResetWires[216] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[200] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1471 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[353] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[354] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1472 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1473 ) ,
+ .clk_0_N_in ( clk_1_wires[200] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+grid_clb grid_clb_9__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1475 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[97] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1476 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[97] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1477 } ) ,
+ .ccff_head ( cby_1__1__93_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_105_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_105_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_105_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_105_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_105_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_105_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_105_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_105_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_105_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_105_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_105_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_105_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_105_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_105_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_105_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_105_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_105_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_105_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_105_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_105_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_105_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_105_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_105_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_105_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_105_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_105_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_105_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_105_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_105_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_105_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_105_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_105_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[96] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1478 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[96] ) ,
+ .ccff_tail ( grid_clb_105_ccff_tail ) , .SC_IN_TOP ( scff_Wires[217] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1479 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1480 ) ,
+ .SC_OUT_BOT ( scff_Wires[218] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1481 ) ,
+ .Test_en_W_in ( Test_enWires[237] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1482 ) ,
+ .Test_en_E_out ( Test_enWires[238] ) , .pReset_N_in ( pResetWires[537] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1483 ) ,
+ .Reset_W_in ( ResetWires[237] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1484 ) ,
+ .Reset_E_out ( ResetWires[238] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1485 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[199] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[356] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[357] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1486 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1487 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1488 ) ,
+ .clk_0_S_in ( clk_1_wires[199] ) ) ;
+grid_clb grid_clb_9__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1489 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[98] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1490 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[98] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1491 } ) ,
+ .ccff_head ( cby_1__1__94_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_106_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_106_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_106_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_106_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_106_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_106_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_106_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_106_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_106_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_106_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_106_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_106_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_106_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_106_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_106_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_106_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_106_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_106_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_106_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_106_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_106_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_106_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_106_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_106_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_106_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_106_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_106_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_106_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_106_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_106_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_106_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_106_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[97] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1492 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[97] ) ,
+ .ccff_tail ( grid_clb_106_ccff_tail ) , .SC_IN_TOP ( scff_Wires[215] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1493 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1494 ) ,
+ .SC_OUT_BOT ( scff_Wires[216] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1495 ) ,
+ .Test_en_W_in ( Test_enWires[259] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1496 ) ,
+ .Test_en_E_out ( Test_enWires[260] ) , .pReset_N_in ( pResetWires[586] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1497 ) ,
+ .Reset_W_in ( ResetWires[259] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1498 ) ,
+ .Reset_E_out ( ResetWires[260] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[207] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1499 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[359] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[360] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1500 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1501 ) ,
+ .clk_0_N_in ( clk_1_wires[207] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+grid_clb grid_clb_9__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1503 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1504 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1505 } ) ,
+ .ccff_head ( cby_1__1__95_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_107_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_107_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_107_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_107_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_107_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_107_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_107_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_107_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_107_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_107_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_107_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_107_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_107_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_107_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_107_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_107_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_107_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_107_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_107_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_107_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_107_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_107_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_107_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_107_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_107_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_107_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_107_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_107_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_107_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_107_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_107_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_107_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[98] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1506 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[98] ) ,
+ .ccff_tail ( grid_clb_107_ccff_tail ) , .SC_IN_TOP ( scff_Wires[213] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1507 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1508 ) ,
+ .SC_OUT_BOT ( scff_Wires[214] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1509 ) ,
+ .Test_en_W_in ( Test_enWires[281] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1510 ) ,
+ .Test_en_E_out ( Test_enWires[282] ) , .pReset_N_in ( pResetWires[627] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1511 ) ,
+ .Reset_W_in ( ResetWires[281] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1512 ) ,
+ .Reset_E_out ( ResetWires[282] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1513 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[206] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[362] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[363] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1514 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[365] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1515 ) ,
+ .clk_0_S_in ( clk_1_wires[206] ) ) ;
+grid_clb grid_clb_10__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1516 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[99] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1517 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[99] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1518 } ) ,
+ .ccff_head ( cby_1__1__96_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_108_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_108_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_108_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_108_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_108_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_108_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_108_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_108_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_108_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_108_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_108_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_108_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_108_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_108_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_108_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_108_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_108_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_108_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_108_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_108_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_108_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_108_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_108_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_108_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_108_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_108_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_108_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_108_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_108_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_108_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_108_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_108_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1519 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_108_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1520 ) ,
+ .SC_IN_BOT ( scff_Wires[240] ) , .SC_OUT_TOP ( scff_Wires[241] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1521 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1522 ) ,
+ .Test_en_W_in ( Test_enWires[41] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1523 ) ,
+ .Test_en_E_out ( Test_enWires[42] ) , .pReset_N_in ( pResetWires[100] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1524 ) ,
+ .Reset_W_in ( ResetWires[41] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1525 ) ,
+ .Reset_E_out ( ResetWires[42] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[174] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1526 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[367] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[368] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1527 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1528 ) ,
+ .clk_0_N_in ( clk_1_wires[174] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+grid_clb grid_clb_10__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1530 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[100] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1531 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[100] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1532 } ) ,
+ .ccff_head ( cby_1__1__97_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_109_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_109_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_109_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_109_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_109_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_109_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_109_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_109_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_109_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_109_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_109_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_109_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_109_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_109_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_109_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_109_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_109_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_109_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_109_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_109_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_109_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_109_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_109_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_109_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_109_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_109_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_109_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_109_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_109_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_109_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_109_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_109_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[99] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1533 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[99] ) ,
+ .ccff_tail ( grid_clb_109_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1534 ) ,
+ .SC_IN_BOT ( scff_Wires[242] ) , .SC_OUT_TOP ( scff_Wires[243] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1535 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1536 ) ,
+ .Test_en_W_in ( Test_enWires[63] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1537 ) ,
+ .Test_en_E_out ( Test_enWires[64] ) , .pReset_N_in ( pResetWires[149] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1538 ) ,
+ .Reset_W_in ( ResetWires[63] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1539 ) ,
+ .Reset_E_out ( ResetWires[64] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1540 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[173] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[370] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[371] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1541 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1542 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1543 ) ,
+ .clk_0_S_in ( clk_1_wires[173] ) ) ;
+grid_clb grid_clb_10__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1544 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[101] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1545 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[101] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1546 } ) ,
+ .ccff_head ( cby_1__1__98_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_110_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_110_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_110_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_110_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_110_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_110_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_110_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_110_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_110_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_110_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_110_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_110_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_110_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_110_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_110_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_110_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_110_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_110_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_110_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_110_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_110_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_110_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_110_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_110_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_110_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_110_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_110_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_110_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_110_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_110_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_110_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_110_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[100] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1547 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[100] ) ,
+ .ccff_tail ( grid_clb_110_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1548 ) ,
+ .SC_IN_BOT ( scff_Wires[244] ) , .SC_OUT_TOP ( scff_Wires[245] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1549 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1550 ) ,
+ .Test_en_W_in ( Test_enWires[85] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1551 ) ,
+ .Test_en_E_out ( Test_enWires[86] ) , .pReset_N_in ( pResetWires[198] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1552 ) ,
+ .Reset_W_in ( ResetWires[85] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1553 ) ,
+ .Reset_E_out ( ResetWires[86] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[181] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1554 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[373] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[374] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1555 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1556 ) ,
+ .clk_0_N_in ( clk_1_wires[181] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+grid_clb grid_clb_10__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1558 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[102] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1559 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[102] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1560 } ) ,
+ .ccff_head ( cby_1__1__99_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_111_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_111_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_111_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_111_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_111_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_111_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_111_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_111_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_111_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_111_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_111_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_111_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_111_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_111_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_111_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_111_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_111_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_111_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_111_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_111_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_111_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_111_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_111_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_111_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_111_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_111_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_111_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_111_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_111_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_111_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_111_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_111_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[101] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1561 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[101] ) ,
+ .ccff_tail ( grid_clb_111_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1562 ) ,
+ .SC_IN_BOT ( scff_Wires[246] ) , .SC_OUT_TOP ( scff_Wires[247] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1563 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1564 ) ,
+ .Test_en_W_in ( Test_enWires[107] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1565 ) ,
+ .Test_en_E_out ( Test_enWires[108] ) , .pReset_N_in ( pResetWires[247] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1566 ) ,
+ .Reset_W_in ( ResetWires[107] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1567 ) ,
+ .Reset_E_out ( ResetWires[108] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1568 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[180] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[376] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[377] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1569 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1570 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1571 ) ,
+ .clk_0_S_in ( clk_1_wires[180] ) ) ;
+grid_clb grid_clb_10__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1572 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[103] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1573 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[103] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1574 } ) ,
+ .ccff_head ( cby_1__1__100_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_112_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_112_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_112_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_112_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_112_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_112_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_112_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_112_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_112_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_112_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_112_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_112_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_112_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_112_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_112_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_112_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_112_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_112_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_112_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_112_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_112_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_112_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_112_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_112_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_112_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_112_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_112_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_112_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_112_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_112_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_112_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_112_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[102] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1575 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[102] ) ,
+ .ccff_tail ( grid_clb_112_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1576 ) ,
+ .SC_IN_BOT ( scff_Wires[248] ) , .SC_OUT_TOP ( scff_Wires[249] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1577 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1578 ) ,
+ .Test_en_W_in ( Test_enWires[129] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1579 ) ,
+ .Test_en_E_out ( Test_enWires[130] ) , .pReset_N_in ( pResetWires[296] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1580 ) ,
+ .Reset_W_in ( ResetWires[129] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1581 ) ,
+ .Reset_E_out ( ResetWires[130] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[188] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1582 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[379] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[380] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1583 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1584 ) ,
+ .clk_0_N_in ( clk_1_wires[188] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+grid_clb grid_clb_10__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1586 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[104] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1587 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[104] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1588 } ) ,
+ .ccff_head ( cby_1__1__101_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_113_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_113_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_113_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_113_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_113_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_113_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_113_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_113_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_113_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_113_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_113_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_113_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_113_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_113_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_113_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_113_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_113_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_113_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_113_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_113_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_113_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_113_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_113_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_113_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_113_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_113_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_113_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_113_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_113_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_113_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_113_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_113_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[103] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1589 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[103] ) ,
+ .ccff_tail ( grid_clb_113_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1590 ) ,
+ .SC_IN_BOT ( scff_Wires[250] ) , .SC_OUT_TOP ( scff_Wires[251] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1591 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1592 ) ,
+ .Test_en_W_in ( Test_enWires[151] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1593 ) ,
+ .Test_en_E_out ( Test_enWires[152] ) , .pReset_N_in ( pResetWires[345] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1594 ) ,
+ .Reset_W_in ( ResetWires[151] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1595 ) ,
+ .Reset_E_out ( ResetWires[152] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1596 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[187] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[382] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[383] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1597 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1598 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1599 ) ,
+ .clk_0_S_in ( clk_1_wires[187] ) ) ;
+grid_clb grid_clb_10__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1600 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[105] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1601 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[105] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1602 } ) ,
+ .ccff_head ( cby_1__1__102_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_114_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_114_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_114_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_114_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_114_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_114_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_114_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_114_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_114_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_114_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_114_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_114_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_114_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_114_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_114_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_114_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_114_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_114_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_114_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_114_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_114_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_114_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_114_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_114_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_114_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_114_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_114_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_114_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_114_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_114_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_114_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_114_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[104] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1603 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[104] ) ,
+ .ccff_tail ( grid_clb_114_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1604 ) ,
+ .SC_IN_BOT ( scff_Wires[252] ) , .SC_OUT_TOP ( scff_Wires[253] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1605 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1606 ) ,
+ .Test_en_W_in ( Test_enWires[173] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1607 ) ,
+ .Test_en_E_out ( Test_enWires[174] ) , .pReset_N_in ( pResetWires[394] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1608 ) ,
+ .Reset_W_in ( ResetWires[173] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1609 ) ,
+ .Reset_E_out ( ResetWires[174] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[195] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1610 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[385] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[386] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1611 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1612 ) ,
+ .clk_0_N_in ( clk_1_wires[195] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+grid_clb grid_clb_10__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1614 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[106] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1615 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[106] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1616 } ) ,
+ .ccff_head ( cby_1__1__103_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_115_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_115_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_115_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_115_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_115_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_115_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_115_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_115_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_115_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_115_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_115_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_115_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_115_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_115_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_115_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_115_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_115_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_115_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_115_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_115_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_115_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_115_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_115_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_115_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_115_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_115_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_115_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_115_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_115_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_115_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_115_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_115_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[105] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1617 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[105] ) ,
+ .ccff_tail ( grid_clb_115_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1618 ) ,
+ .SC_IN_BOT ( scff_Wires[254] ) , .SC_OUT_TOP ( scff_Wires[255] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1619 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1620 ) ,
+ .Test_en_W_in ( Test_enWires[195] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1621 ) ,
+ .Test_en_E_out ( Test_enWires[196] ) , .pReset_N_in ( pResetWires[443] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1622 ) ,
+ .Reset_W_in ( ResetWires[195] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1623 ) ,
+ .Reset_E_out ( ResetWires[196] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1624 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[194] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[388] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[389] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1625 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1626 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1627 ) ,
+ .clk_0_S_in ( clk_1_wires[194] ) ) ;
+grid_clb grid_clb_10__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1628 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[107] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1629 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[107] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1630 } ) ,
+ .ccff_head ( cby_1__1__104_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_116_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_116_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_116_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_116_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_116_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_116_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_116_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_116_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_116_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_116_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_116_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_116_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_116_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_116_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_116_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_116_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_116_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_116_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_116_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_116_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_116_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_116_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_116_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_116_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_116_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_116_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_116_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_116_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_116_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_116_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_116_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_116_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[106] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1631 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[106] ) ,
+ .ccff_tail ( grid_clb_116_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1632 ) ,
+ .SC_IN_BOT ( scff_Wires[256] ) , .SC_OUT_TOP ( scff_Wires[257] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1633 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1634 ) ,
+ .Test_en_W_in ( Test_enWires[217] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1635 ) ,
+ .Test_en_E_out ( Test_enWires[218] ) , .pReset_N_in ( pResetWires[492] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1636 ) ,
+ .Reset_W_in ( ResetWires[217] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1637 ) ,
+ .Reset_E_out ( ResetWires[218] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[202] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1638 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[391] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[392] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1639 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1640 ) ,
+ .clk_0_N_in ( clk_1_wires[202] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+grid_clb grid_clb_10__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1642 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[108] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1643 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[108] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1644 } ) ,
+ .ccff_head ( cby_1__1__105_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_117_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_117_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_117_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_117_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_117_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_117_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_117_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_117_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_117_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_117_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_117_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_117_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_117_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_117_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_117_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_117_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_117_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_117_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_117_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_117_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_117_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_117_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_117_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_117_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_117_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_117_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_117_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_117_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_117_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_117_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_117_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_117_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[107] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1645 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[107] ) ,
+ .ccff_tail ( grid_clb_117_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1646 ) ,
+ .SC_IN_BOT ( scff_Wires[258] ) , .SC_OUT_TOP ( scff_Wires[259] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1647 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1648 ) ,
+ .Test_en_W_in ( Test_enWires[239] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1649 ) ,
+ .Test_en_E_out ( Test_enWires[240] ) , .pReset_N_in ( pResetWires[541] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1650 ) ,
+ .Reset_W_in ( ResetWires[239] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1651 ) ,
+ .Reset_E_out ( ResetWires[240] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1652 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[201] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[394] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[395] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1653 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1654 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1655 ) ,
+ .clk_0_S_in ( clk_1_wires[201] ) ) ;
+grid_clb grid_clb_10__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1656 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[109] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1657 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[109] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1658 } ) ,
+ .ccff_head ( cby_1__1__106_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_118_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_118_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_118_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_118_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_118_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_118_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_118_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_118_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_118_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_118_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_118_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_118_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_118_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_118_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_118_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_118_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_118_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_118_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_118_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_118_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_118_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_118_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_118_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_118_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_118_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_118_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_118_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_118_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_118_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_118_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_118_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_118_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[108] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1659 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[108] ) ,
+ .ccff_tail ( grid_clb_118_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1660 ) ,
+ .SC_IN_BOT ( scff_Wires[260] ) , .SC_OUT_TOP ( scff_Wires[261] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1661 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1662 ) ,
+ .Test_en_W_in ( Test_enWires[261] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1663 ) ,
+ .Test_en_E_out ( Test_enWires[262] ) , .pReset_N_in ( pResetWires[590] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1664 ) ,
+ .Reset_W_in ( ResetWires[261] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1665 ) ,
+ .Reset_E_out ( ResetWires[262] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[209] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1666 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[397] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[398] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1667 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1668 ) ,
+ .clk_0_N_in ( clk_1_wires[209] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+grid_clb grid_clb_10__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1670 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1671 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1672 } ) ,
+ .ccff_head ( cby_1__1__107_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_119_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_119_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_119_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_119_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_119_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_119_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_119_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_119_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_119_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_119_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_119_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_119_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_119_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_119_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_119_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_119_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_119_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_119_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_119_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_119_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_119_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_119_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_119_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_119_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_119_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_119_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_119_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_119_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_119_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_119_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_119_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_119_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[109] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1673 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[109] ) ,
+ .ccff_tail ( grid_clb_119_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1674 ) ,
+ .SC_IN_BOT ( scff_Wires[262] ) , .SC_OUT_TOP ( scff_Wires[263] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1675 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1676 ) ,
+ .Test_en_W_in ( Test_enWires[283] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1677 ) ,
+ .Test_en_E_out ( Test_enWires[284] ) , .pReset_N_in ( pResetWires[630] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1678 ) ,
+ .Reset_W_in ( ResetWires[283] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1679 ) ,
+ .Reset_E_out ( ResetWires[284] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1680 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[208] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[400] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[401] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1681 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[403] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1682 ) ,
+ .clk_0_S_in ( clk_1_wires[208] ) ) ;
+grid_clb grid_clb_11__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1683 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[110] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1684 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[110] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1685 } ) ,
+ .ccff_head ( cby_1__1__108_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_120_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_120_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_120_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_120_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_120_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_120_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_120_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_120_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_120_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_120_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_120_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_120_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_120_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_120_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_120_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_120_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_120_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_120_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_120_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_120_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_120_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_120_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_120_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_120_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_120_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_120_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_120_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_120_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_120_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_120_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_120_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_120_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1686 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[288] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1687 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1688 ) ,
+ .SC_OUT_BOT ( scff_Wires[290] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1689 ) ,
+ .Test_en_W_in ( Test_enWires[43] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1690 ) ,
+ .Test_en_E_out ( Test_enWires[44] ) , .pReset_N_in ( pResetWires[104] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1691 ) ,
+ .Reset_W_in ( ResetWires[43] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1692 ) ,
+ .Reset_E_out ( ResetWires[44] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[214] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1693 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[405] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[406] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1694 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1695 ) ,
+ .clk_0_N_in ( clk_1_wires[214] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+grid_clb grid_clb_11__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1697 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[111] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1698 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[111] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1699 } ) ,
+ .ccff_head ( cby_1__1__109_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_121_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_121_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_121_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_121_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_121_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_121_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_121_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_121_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_121_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_121_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_121_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_121_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_121_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_121_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_121_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_121_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_121_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_121_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_121_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_121_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_121_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_121_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_121_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_121_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_121_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_121_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_121_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_121_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_121_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_121_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_121_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_121_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[110] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1700 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[110] ) ,
+ .ccff_tail ( grid_clb_121_ccff_tail ) , .SC_IN_TOP ( scff_Wires[286] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1701 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1702 ) ,
+ .SC_OUT_BOT ( scff_Wires[287] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1703 ) ,
+ .Test_en_W_in ( Test_enWires[65] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1704 ) ,
+ .Test_en_E_out ( Test_enWires[66] ) , .pReset_N_in ( pResetWires[153] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1705 ) ,
+ .Reset_W_in ( ResetWires[65] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1706 ) ,
+ .Reset_E_out ( ResetWires[66] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1707 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[213] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[408] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[409] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1708 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1709 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1710 ) ,
+ .clk_0_S_in ( clk_1_wires[213] ) ) ;
+grid_clb grid_clb_11__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1711 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[112] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1712 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[112] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1713 } ) ,
+ .ccff_head ( cby_1__1__110_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_122_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_122_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_122_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_122_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_122_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_122_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_122_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_122_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_122_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_122_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_122_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_122_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_122_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_122_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_122_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_122_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_122_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_122_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_122_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_122_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_122_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_122_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_122_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_122_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_122_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_122_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_122_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_122_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_122_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_122_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_122_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_122_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[111] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1714 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[111] ) ,
+ .ccff_tail ( grid_clb_122_ccff_tail ) , .SC_IN_TOP ( scff_Wires[284] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1715 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1716 ) ,
+ .SC_OUT_BOT ( scff_Wires[285] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1717 ) ,
+ .Test_en_W_in ( Test_enWires[87] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1718 ) ,
+ .Test_en_E_out ( Test_enWires[88] ) , .pReset_N_in ( pResetWires[202] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1719 ) ,
+ .Reset_W_in ( ResetWires[87] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1720 ) ,
+ .Reset_E_out ( ResetWires[88] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[221] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1721 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[411] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[412] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1722 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1723 ) ,
+ .clk_0_N_in ( clk_1_wires[221] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+grid_clb grid_clb_11__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1725 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[113] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1726 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[113] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1727 } ) ,
+ .ccff_head ( cby_1__1__111_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_123_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_123_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_123_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_123_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_123_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_123_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_123_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_123_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_123_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_123_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_123_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_123_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_123_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_123_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_123_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_123_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_123_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_123_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_123_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_123_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_123_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_123_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_123_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_123_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_123_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_123_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_123_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_123_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_123_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_123_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_123_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_123_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[112] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1728 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[112] ) ,
+ .ccff_tail ( grid_clb_123_ccff_tail ) , .SC_IN_TOP ( scff_Wires[282] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1729 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1730 ) ,
+ .SC_OUT_BOT ( scff_Wires[283] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1731 ) ,
+ .Test_en_W_in ( Test_enWires[109] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1732 ) ,
+ .Test_en_E_out ( Test_enWires[110] ) , .pReset_N_in ( pResetWires[251] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1733 ) ,
+ .Reset_W_in ( ResetWires[109] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1734 ) ,
+ .Reset_E_out ( ResetWires[110] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1735 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[220] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[414] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[415] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1736 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1737 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1738 ) ,
+ .clk_0_S_in ( clk_1_wires[220] ) ) ;
+grid_clb grid_clb_11__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1739 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[114] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1740 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[114] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1741 } ) ,
+ .ccff_head ( cby_1__1__112_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_124_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_124_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_124_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_124_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_124_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_124_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_124_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_124_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_124_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_124_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_124_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_124_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_124_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_124_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_124_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_124_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_124_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_124_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_124_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_124_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_124_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_124_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_124_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_124_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_124_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_124_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_124_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_124_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_124_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_124_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_124_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_124_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[113] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1742 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[113] ) ,
+ .ccff_tail ( grid_clb_124_ccff_tail ) , .SC_IN_TOP ( scff_Wires[280] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1743 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1744 ) ,
+ .SC_OUT_BOT ( scff_Wires[281] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1745 ) ,
+ .Test_en_W_in ( Test_enWires[131] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1746 ) ,
+ .Test_en_E_out ( Test_enWires[132] ) , .pReset_N_in ( pResetWires[300] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1747 ) ,
+ .Reset_W_in ( ResetWires[131] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1748 ) ,
+ .Reset_E_out ( ResetWires[132] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[228] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1749 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[417] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[418] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1750 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1751 ) ,
+ .clk_0_N_in ( clk_1_wires[228] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+grid_clb grid_clb_11__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1753 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[115] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1754 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[115] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1755 } ) ,
+ .ccff_head ( cby_1__1__113_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_125_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_125_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_125_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_125_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_125_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_125_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_125_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_125_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_125_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_125_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_125_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_125_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_125_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_125_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_125_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_125_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_125_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_125_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_125_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_125_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_125_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_125_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_125_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_125_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_125_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_125_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_125_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_125_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_125_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_125_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_125_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_125_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[114] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1756 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[114] ) ,
+ .ccff_tail ( grid_clb_125_ccff_tail ) , .SC_IN_TOP ( scff_Wires[278] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1757 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1758 ) ,
+ .SC_OUT_BOT ( scff_Wires[279] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1759 ) ,
+ .Test_en_W_in ( Test_enWires[153] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1760 ) ,
+ .Test_en_E_out ( Test_enWires[154] ) , .pReset_N_in ( pResetWires[349] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1761 ) ,
+ .Reset_W_in ( ResetWires[153] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1762 ) ,
+ .Reset_E_out ( ResetWires[154] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1763 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[227] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[420] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[421] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1764 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1765 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1766 ) ,
+ .clk_0_S_in ( clk_1_wires[227] ) ) ;
+grid_clb grid_clb_11__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1767 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[116] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1768 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[116] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1769 } ) ,
+ .ccff_head ( cby_1__1__114_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_126_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_126_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_126_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_126_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_126_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_126_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_126_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_126_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_126_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_126_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_126_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_126_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_126_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_126_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_126_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_126_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_126_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_126_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_126_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_126_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_126_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_126_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_126_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_126_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_126_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_126_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_126_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_126_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_126_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_126_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_126_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_126_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[115] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1770 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[115] ) ,
+ .ccff_tail ( grid_clb_126_ccff_tail ) , .SC_IN_TOP ( scff_Wires[276] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1771 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1772 ) ,
+ .SC_OUT_BOT ( scff_Wires[277] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1773 ) ,
+ .Test_en_W_in ( Test_enWires[175] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1774 ) ,
+ .Test_en_E_out ( Test_enWires[176] ) , .pReset_N_in ( pResetWires[398] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1775 ) ,
+ .Reset_W_in ( ResetWires[175] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1776 ) ,
+ .Reset_E_out ( ResetWires[176] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[235] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1777 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[423] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[424] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1778 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1779 ) ,
+ .clk_0_N_in ( clk_1_wires[235] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+grid_clb grid_clb_11__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1781 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[117] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1782 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[117] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1783 } ) ,
+ .ccff_head ( cby_1__1__115_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_127_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_127_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_127_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_127_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_127_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_127_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_127_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_127_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_127_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_127_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_127_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_127_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_127_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_127_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_127_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_127_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_127_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_127_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_127_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_127_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_127_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_127_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_127_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_127_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_127_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_127_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_127_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_127_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_127_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_127_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_127_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_127_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[116] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1784 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[116] ) ,
+ .ccff_tail ( grid_clb_127_ccff_tail ) , .SC_IN_TOP ( scff_Wires[274] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1785 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1786 ) ,
+ .SC_OUT_BOT ( scff_Wires[275] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1787 ) ,
+ .Test_en_W_in ( Test_enWires[197] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1788 ) ,
+ .Test_en_E_out ( Test_enWires[198] ) , .pReset_N_in ( pResetWires[447] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1789 ) ,
+ .Reset_W_in ( ResetWires[197] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1790 ) ,
+ .Reset_E_out ( ResetWires[198] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1791 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[234] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[426] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[427] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1792 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1793 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1794 ) ,
+ .clk_0_S_in ( clk_1_wires[234] ) ) ;
+grid_clb grid_clb_11__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1795 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[118] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1796 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[118] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1797 } ) ,
+ .ccff_head ( cby_1__1__116_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_128_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_128_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_128_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_128_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_128_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_128_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_128_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_128_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_128_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_128_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_128_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_128_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_128_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_128_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_128_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_128_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_128_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_128_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_128_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_128_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_128_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_128_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_128_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_128_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_128_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_128_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_128_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_128_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_128_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_128_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_128_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_128_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[117] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1798 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[117] ) ,
+ .ccff_tail ( grid_clb_128_ccff_tail ) , .SC_IN_TOP ( scff_Wires[272] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1799 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1800 ) ,
+ .SC_OUT_BOT ( scff_Wires[273] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1801 ) ,
+ .Test_en_W_in ( Test_enWires[219] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1802 ) ,
+ .Test_en_E_out ( Test_enWires[220] ) , .pReset_N_in ( pResetWires[496] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1803 ) ,
+ .Reset_W_in ( ResetWires[219] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1804 ) ,
+ .Reset_E_out ( ResetWires[220] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[242] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1805 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[429] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[430] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1806 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1807 ) ,
+ .clk_0_N_in ( clk_1_wires[242] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+grid_clb grid_clb_11__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1809 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[119] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1810 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[119] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1811 } ) ,
+ .ccff_head ( cby_1__1__117_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_129_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_129_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_129_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_129_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_129_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_129_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_129_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_129_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_129_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_129_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_129_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_129_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_129_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_129_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_129_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_129_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_129_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_129_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_129_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_129_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_129_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_129_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_129_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_129_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_129_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_129_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_129_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_129_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_129_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_129_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_129_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_129_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[118] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1812 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[118] ) ,
+ .ccff_tail ( grid_clb_129_ccff_tail ) , .SC_IN_TOP ( scff_Wires[270] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1813 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1814 ) ,
+ .SC_OUT_BOT ( scff_Wires[271] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1815 ) ,
+ .Test_en_W_in ( Test_enWires[241] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1816 ) ,
+ .Test_en_E_out ( Test_enWires[242] ) , .pReset_N_in ( pResetWires[545] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1817 ) ,
+ .Reset_W_in ( ResetWires[241] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1818 ) ,
+ .Reset_E_out ( ResetWires[242] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1819 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[241] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[432] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[433] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1820 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1821 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1822 ) ,
+ .clk_0_S_in ( clk_1_wires[241] ) ) ;
+grid_clb grid_clb_11__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1823 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[120] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1824 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[120] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1825 } ) ,
+ .ccff_head ( cby_1__1__118_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_130_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_130_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_130_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_130_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_130_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_130_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_130_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_130_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_130_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_130_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_130_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_130_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_130_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_130_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_130_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_130_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_130_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_130_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_130_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_130_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_130_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_130_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_130_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_130_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_130_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_130_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_130_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_130_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_130_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_130_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_130_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_130_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[119] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1826 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[119] ) ,
+ .ccff_tail ( grid_clb_130_ccff_tail ) , .SC_IN_TOP ( scff_Wires[268] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1827 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1828 ) ,
+ .SC_OUT_BOT ( scff_Wires[269] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1829 ) ,
+ .Test_en_W_in ( Test_enWires[263] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1830 ) ,
+ .Test_en_E_out ( Test_enWires[264] ) , .pReset_N_in ( pResetWires[594] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1831 ) ,
+ .Reset_W_in ( ResetWires[263] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1832 ) ,
+ .Reset_E_out ( ResetWires[264] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[249] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1833 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[435] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[436] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1834 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1835 ) ,
+ .clk_0_N_in ( clk_1_wires[249] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+grid_clb grid_clb_11__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1837 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1838 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1839 } ) ,
+ .ccff_head ( cby_1__1__119_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_131_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_131_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_131_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_131_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_131_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_131_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_131_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_131_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_131_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_131_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_131_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_131_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_131_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_131_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_131_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_131_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_131_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_131_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_131_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_131_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_131_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_131_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_131_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_131_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_131_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_131_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_131_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_131_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_131_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_131_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_131_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_131_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[120] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1840 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[120] ) ,
+ .ccff_tail ( grid_clb_131_ccff_tail ) , .SC_IN_TOP ( scff_Wires[266] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1841 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1842 ) ,
+ .SC_OUT_BOT ( scff_Wires[267] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1843 ) ,
+ .Test_en_W_in ( Test_enWires[285] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1844 ) ,
+ .Test_en_E_out ( Test_enWires[286] ) , .pReset_N_in ( pResetWires[633] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1845 ) ,
+ .Reset_W_in ( ResetWires[285] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1846 ) ,
+ .Reset_E_out ( ResetWires[286] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1847 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[248] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[438] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[439] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1848 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[441] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1849 ) ,
+ .clk_0_S_in ( clk_1_wires[248] ) ) ;
+grid_clb grid_clb_12__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1850 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[121] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1851 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[121] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1852 } ) ,
+ .ccff_head ( cby_1__1__120_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_132_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_132_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_132_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_132_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_132_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_132_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_132_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_132_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_132_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_132_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_132_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_132_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_132_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_132_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_132_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_132_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_132_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_132_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_132_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_132_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_132_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_132_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_132_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_132_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_132_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_132_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_132_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_132_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_132_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_132_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_132_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_132_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1853 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_132_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1854 ) ,
+ .SC_IN_BOT ( scff_Wires[293] ) , .SC_OUT_TOP ( scff_Wires[294] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1855 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1856 ) ,
+ .Test_en_W_in ( Test_enWires[45] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1857 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1858 ) ,
+ .pReset_N_in ( pResetWires[108] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1859 ) ,
+ .Reset_W_in ( ResetWires[45] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1860 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1861 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[216] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1862 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[443] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[444] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1863 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1864 ) ,
+ .clk_0_N_in ( clk_1_wires[216] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+grid_clb grid_clb_12__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1866 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[122] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1867 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[122] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1868 } ) ,
+ .ccff_head ( cby_1__1__121_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_133_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_133_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_133_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_133_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_133_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_133_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_133_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_133_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_133_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_133_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_133_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_133_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_133_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_133_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_133_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_133_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_133_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_133_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_133_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_133_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_133_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_133_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_133_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_133_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_133_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_133_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_133_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_133_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_133_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_133_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_133_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_133_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[121] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1869 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[121] ) ,
+ .ccff_tail ( grid_clb_133_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1870 ) ,
+ .SC_IN_BOT ( scff_Wires[295] ) , .SC_OUT_TOP ( scff_Wires[296] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1871 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1872 ) ,
+ .Test_en_W_in ( Test_enWires[67] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1873 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1874 ) ,
+ .pReset_N_in ( pResetWires[157] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1875 ) ,
+ .Reset_W_in ( ResetWires[67] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1876 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1877 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1878 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[215] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[446] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[447] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1879 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1880 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1881 ) ,
+ .clk_0_S_in ( clk_1_wires[215] ) ) ;
+grid_clb grid_clb_12__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1882 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[123] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1883 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[123] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1884 } ) ,
+ .ccff_head ( cby_1__1__122_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_134_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_134_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_134_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_134_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_134_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_134_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_134_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_134_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_134_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_134_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_134_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_134_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_134_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_134_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_134_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_134_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_134_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_134_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_134_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_134_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_134_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_134_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_134_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_134_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_134_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_134_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_134_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_134_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_134_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_134_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_134_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_134_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[122] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1885 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[122] ) ,
+ .ccff_tail ( grid_clb_134_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1886 ) ,
+ .SC_IN_BOT ( scff_Wires[297] ) , .SC_OUT_TOP ( scff_Wires[298] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1887 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1888 ) ,
+ .Test_en_W_in ( Test_enWires[89] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1889 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1890 ) ,
+ .pReset_N_in ( pResetWires[206] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1891 ) ,
+ .Reset_W_in ( ResetWires[89] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1892 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1893 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[223] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1894 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[449] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[450] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1895 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1896 ) ,
+ .clk_0_N_in ( clk_1_wires[223] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+grid_clb grid_clb_12__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1898 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[124] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1899 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[124] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1900 } ) ,
+ .ccff_head ( cby_1__1__123_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_135_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_135_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_135_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_135_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_135_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_135_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_135_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_135_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_135_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_135_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_135_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_135_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_135_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_135_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_135_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_135_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_135_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_135_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_135_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_135_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_135_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_135_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_135_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_135_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_135_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_135_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_135_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_135_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_135_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_135_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_135_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_135_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[123] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1901 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[123] ) ,
+ .ccff_tail ( grid_clb_135_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1902 ) ,
+ .SC_IN_BOT ( scff_Wires[299] ) , .SC_OUT_TOP ( scff_Wires[300] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1903 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1904 ) ,
+ .Test_en_W_in ( Test_enWires[111] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1905 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1906 ) ,
+ .pReset_N_in ( pResetWires[255] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1907 ) ,
+ .Reset_W_in ( ResetWires[111] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1908 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1909 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1910 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[222] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[452] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[453] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1911 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1912 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1913 ) ,
+ .clk_0_S_in ( clk_1_wires[222] ) ) ;
+grid_clb grid_clb_12__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1914 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[125] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1915 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[125] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1916 } ) ,
+ .ccff_head ( cby_1__1__124_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_136_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_136_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_136_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_136_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_136_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_136_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_136_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_136_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_136_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_136_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_136_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_136_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_136_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_136_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_136_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_136_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_136_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_136_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_136_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_136_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_136_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_136_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_136_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_136_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_136_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_136_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_136_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_136_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_136_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_136_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_136_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_136_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[124] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1917 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[124] ) ,
+ .ccff_tail ( grid_clb_136_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1918 ) ,
+ .SC_IN_BOT ( scff_Wires[301] ) , .SC_OUT_TOP ( scff_Wires[302] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1919 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1920 ) ,
+ .Test_en_W_in ( Test_enWires[133] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1921 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1922 ) ,
+ .pReset_N_in ( pResetWires[304] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1923 ) ,
+ .Reset_W_in ( ResetWires[133] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1924 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1925 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[230] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1926 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[455] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[456] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1927 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1928 ) ,
+ .clk_0_N_in ( clk_1_wires[230] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+grid_clb grid_clb_12__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1930 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[126] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1931 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[126] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1932 } ) ,
+ .ccff_head ( cby_1__1__125_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_137_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_137_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_137_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_137_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_137_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_137_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_137_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_137_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_137_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_137_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_137_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_137_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_137_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_137_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_137_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_137_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_137_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_137_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_137_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_137_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_137_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_137_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_137_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_137_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_137_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_137_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_137_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_137_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_137_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_137_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_137_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_137_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[125] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1933 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[125] ) ,
+ .ccff_tail ( grid_clb_137_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1934 ) ,
+ .SC_IN_BOT ( scff_Wires[303] ) , .SC_OUT_TOP ( scff_Wires[304] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1935 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1936 ) ,
+ .Test_en_W_in ( Test_enWires[155] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1937 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1938 ) ,
+ .pReset_N_in ( pResetWires[353] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1939 ) ,
+ .Reset_W_in ( ResetWires[155] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1940 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1941 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1942 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[229] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[458] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[459] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1943 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1944 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1945 ) ,
+ .clk_0_S_in ( clk_1_wires[229] ) ) ;
+grid_clb grid_clb_12__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1946 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[127] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1947 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[127] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1948 } ) ,
+ .ccff_head ( cby_1__1__126_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_138_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_138_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_138_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_138_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_138_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_138_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_138_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_138_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_138_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_138_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_138_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_138_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_138_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_138_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_138_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_138_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_138_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_138_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_138_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_138_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_138_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_138_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_138_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_138_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_138_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_138_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_138_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_138_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_138_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_138_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_138_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_138_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[126] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1949 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[126] ) ,
+ .ccff_tail ( grid_clb_138_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1950 ) ,
+ .SC_IN_BOT ( scff_Wires[305] ) , .SC_OUT_TOP ( scff_Wires[306] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1951 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1952 ) ,
+ .Test_en_W_in ( Test_enWires[177] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1953 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1954 ) ,
+ .pReset_N_in ( pResetWires[402] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1955 ) ,
+ .Reset_W_in ( ResetWires[177] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1956 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1957 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[237] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1958 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[461] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[462] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1959 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1960 ) ,
+ .clk_0_N_in ( clk_1_wires[237] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+grid_clb grid_clb_12__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1962 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[128] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1963 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[128] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1964 } ) ,
+ .ccff_head ( cby_1__1__127_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_139_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_139_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_139_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_139_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_139_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_139_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_139_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_139_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_139_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_139_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_139_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_139_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_139_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_139_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_139_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_139_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_139_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_139_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_139_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_139_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_139_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_139_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_139_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_139_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_139_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_139_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_139_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_139_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_139_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_139_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_139_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_139_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[127] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1965 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[127] ) ,
+ .ccff_tail ( grid_clb_139_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1966 ) ,
+ .SC_IN_BOT ( scff_Wires[307] ) , .SC_OUT_TOP ( scff_Wires[308] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1967 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1968 ) ,
+ .Test_en_W_in ( Test_enWires[199] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1969 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1970 ) ,
+ .pReset_N_in ( pResetWires[451] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1971 ) ,
+ .Reset_W_in ( ResetWires[199] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1972 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1973 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1974 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[236] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[464] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[465] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1975 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1976 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1977 ) ,
+ .clk_0_S_in ( clk_1_wires[236] ) ) ;
+grid_clb grid_clb_12__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1978 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[129] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1979 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[129] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1980 } ) ,
+ .ccff_head ( cby_1__1__128_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_140_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_140_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_140_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_140_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_140_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_140_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_140_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_140_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_140_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_140_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_140_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_140_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_140_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_140_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_140_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_140_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_140_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_140_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_140_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_140_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_140_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_140_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_140_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_140_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_140_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_140_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_140_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_140_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_140_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_140_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_140_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_140_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[128] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1981 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[128] ) ,
+ .ccff_tail ( grid_clb_140_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1982 ) ,
+ .SC_IN_BOT ( scff_Wires[309] ) , .SC_OUT_TOP ( scff_Wires[310] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1983 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1984 ) ,
+ .Test_en_W_in ( Test_enWires[221] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1985 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1986 ) ,
+ .pReset_N_in ( pResetWires[500] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1987 ) ,
+ .Reset_W_in ( ResetWires[221] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1988 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1989 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[244] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1990 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[467] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[468] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1991 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1992 ) ,
+ .clk_0_N_in ( clk_1_wires[244] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+grid_clb grid_clb_12__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1994 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[130] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1995 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[130] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1996 } ) ,
+ .ccff_head ( cby_1__1__129_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_141_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_141_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_141_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_141_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_141_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_141_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_141_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_141_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_141_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_141_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_141_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_141_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_141_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_141_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_141_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_141_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_141_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_141_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_141_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_141_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_141_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_141_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_141_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_141_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_141_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_141_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_141_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_141_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_141_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_141_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_141_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_141_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[129] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1997 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[129] ) ,
+ .ccff_tail ( grid_clb_141_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1998 ) ,
+ .SC_IN_BOT ( scff_Wires[311] ) , .SC_OUT_TOP ( scff_Wires[312] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1999 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2000 ) ,
+ .Test_en_W_in ( Test_enWires[243] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2001 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2002 ) ,
+ .pReset_N_in ( pResetWires[549] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_2003 ) ,
+ .Reset_W_in ( ResetWires[243] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_2004 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_2005 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2006 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[243] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[470] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[471] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2007 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2008 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2009 ) ,
+ .clk_0_S_in ( clk_1_wires[243] ) ) ;
+grid_clb grid_clb_12__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2010 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[131] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2011 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[131] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_2012 } ) ,
+ .ccff_head ( cby_1__1__130_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_142_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_142_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_142_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_142_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_142_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_142_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_142_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_142_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_142_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_142_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_142_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_142_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_142_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_142_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_142_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_142_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_142_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_142_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_142_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_142_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_142_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_142_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_142_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_142_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_142_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_142_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_142_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_142_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_142_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_142_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_142_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_142_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[130] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2013 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[130] ) ,
+ .ccff_tail ( grid_clb_142_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2014 ) ,
+ .SC_IN_BOT ( scff_Wires[313] ) , .SC_OUT_TOP ( scff_Wires[314] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2015 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2016 ) ,
+ .Test_en_W_in ( Test_enWires[265] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2017 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2018 ) ,
+ .pReset_N_in ( pResetWires[598] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_2019 ) ,
+ .Reset_W_in ( ResetWires[265] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_2020 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_2021 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[251] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_2022 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[473] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[474] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2023 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2024 ) ,
+ .clk_0_N_in ( clk_1_wires[251] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+grid_clb grid_clb_12__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2026 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2027 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_2028 } ) ,
+ .ccff_head ( cby_1__1__131_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_143_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_143_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_143_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_143_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_143_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_143_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_143_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_143_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_143_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_143_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_143_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_143_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_143_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_143_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_143_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_143_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_143_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_143_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_143_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_143_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_143_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_143_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_143_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_143_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_143_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_143_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_143_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_143_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_143_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_143_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_143_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_143_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[131] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2029 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[131] ) ,
+ .ccff_tail ( grid_clb_143_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2030 ) ,
+ .SC_IN_BOT ( scff_Wires[315] ) , .SC_OUT_TOP ( scff_Wires[316] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2031 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2032 ) ,
+ .Test_en_W_in ( Test_enWires[287] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2033 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2034 ) ,
+ .pReset_N_in ( pResetWires[636] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_2035 ) ,
+ .Reset_W_in ( ResetWires[287] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_2036 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_2037 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2038 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[250] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[476] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[477] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2039 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[479] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2040 ) ,
+ .clk_0_S_in ( clk_1_wires[250] ) ) ;
+sb_0__0_ sb_0__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2041 } ) ,
+ .chany_top_in ( cby_0__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__0__0_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) ,
+ .ccff_head ( grid_io_bottom_11_ccff_tail ) ,
+ .chany_top_out ( sb_0__0__0_chany_top_out ) ,
+ .chanx_right_out ( sb_0__0__0_chanx_right_out ) ,
+ .ccff_tail ( ccff_tail ) , .pReset_E_in ( pResetWires[25] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[5] ) ) ;
+sb_0__1_ sb_0__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2042 } ) ,
+ .chany_top_in ( cby_0__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__0_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__0_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__0_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__0_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__0_ccff_tail ) , .pReset_E_in ( pResetWires[61] ) ,
+ .pReset_S_out ( pResetWires[64] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[4] ) ) ;
+sb_0__1_ sb_0__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2043 } ) ,
+ .chany_top_in ( cby_0__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__1_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__1_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__1_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__1_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__1_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__1_ccff_tail ) , .pReset_E_in ( pResetWires[110] ) ,
+ .pReset_S_out ( pResetWires[113] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[10] ) ) ;
+sb_0__1_ sb_0__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2044 } ) ,
+ .chany_top_in ( cby_0__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__2_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__2_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__2_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__2_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__2_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__2_ccff_tail ) , .pReset_E_in ( pResetWires[159] ) ,
+ .pReset_S_out ( pResetWires[162] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[15] ) ) ;
+sb_0__1_ sb_0__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2045 } ) ,
+ .chany_top_in ( cby_0__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__3_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__3_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__3_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__3_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__3_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__3_ccff_tail ) , .pReset_E_in ( pResetWires[208] ) ,
+ .pReset_S_out ( pResetWires[211] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[20] ) ) ;
+sb_0__1_ sb_0__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2046 } ) ,
+ .chany_top_in ( cby_0__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__4_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__4_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__4_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__4_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__4_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__4_ccff_tail ) , .pReset_E_in ( pResetWires[257] ) ,
+ .pReset_S_out ( pResetWires[260] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[25] ) ) ;
+sb_0__1_ sb_0__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2047 } ) ,
+ .chany_top_in ( cby_0__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__5_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__5_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__5_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__5_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__5_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__5_ccff_tail ) , .pReset_E_in ( pResetWires[306] ) ,
+ .pReset_S_out ( pResetWires[309] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[30] ) ) ;
+sb_0__1_ sb_0__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2048 } ) ,
+ .chany_top_in ( cby_0__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__6_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__6_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__6_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__6_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__6_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__6_ccff_tail ) , .pReset_E_in ( pResetWires[355] ) ,
+ .pReset_S_out ( pResetWires[358] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[35] ) ) ;
+sb_0__1_ sb_0__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2049 } ) ,
+ .chany_top_in ( cby_0__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__7_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__7_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__7_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__7_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__7_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__7_ccff_tail ) , .pReset_E_in ( pResetWires[404] ) ,
+ .pReset_S_out ( pResetWires[407] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[40] ) ) ;
+sb_0__1_ sb_0__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2050 } ) ,
+ .chany_top_in ( cby_0__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__8_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__8_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__8_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__8_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__8_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__8_ccff_tail ) , .pReset_E_in ( pResetWires[453] ) ,
+ .pReset_S_out ( pResetWires[456] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[45] ) ) ;
+sb_0__1_ sb_0__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2051 } ) ,
+ .chany_top_in ( cby_0__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__9_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__9_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__9_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__9_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__9_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__9_ccff_tail ) , .pReset_E_in ( pResetWires[502] ) ,
+ .pReset_S_out ( pResetWires[505] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[50] ) ) ;
+sb_0__1_ sb_0__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2052 } ) ,
+ .chany_top_in ( cby_0__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__10_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__10_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__10_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__10_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__10_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__10_ccff_tail ) , .pReset_E_in ( pResetWires[551] ) ,
+ .pReset_S_out ( pResetWires[554] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[55] ) ) ;
+sb_0__2_ sb_0__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2053 } ) ,
+ .chanx_right_in ( cbx_1__12__0_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__11_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( grid_io_top_0_ccff_tail ) ,
+ .chanx_right_out ( sb_0__12__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__12__0_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__12__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) ,
+ .SC_OUT_BOT ( scff_Wires[0] ) , .pReset_E_in ( pResetWires[600] ) ,
+ .pReset_S_out ( pResetWires[603] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[62] ) ) ;
+sb_1__0_ sb_1__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2054 } ) ,
+ .chany_top_in ( cby_1__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__1_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__0_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_10_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__0_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__0_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) ,
+ .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p913 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2055 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2056 ) ,
+ .pReset_E_in ( pResetWires[28] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2057 ) ,
+ .pReset_N_out ( pResetWires[27] ) , .pReset_W_out ( pResetWires[26] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( p913 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p913 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p913 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+sb_1__0_ sb_2__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) ,
+ .chany_top_in ( cby_1__1__12_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__2_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__1_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_9_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__1_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__1_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1191 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( p945 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2064 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2065 ) ,
+ .pReset_E_in ( pResetWires[31] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2066 ) ,
+ .pReset_N_out ( pResetWires[30] ) , .pReset_W_out ( pResetWires[29] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( p945 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p945 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p945 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+sb_1__0_ sb_3__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) ,
+ .chany_top_in ( cby_1__1__24_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__3_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__2_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_8_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__2_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__2_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) ,
+ .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1498 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2072 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2073 ) ,
+ .pReset_E_in ( pResetWires[34] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2074 ) ,
+ .pReset_N_out ( pResetWires[33] ) , .pReset_W_out ( pResetWires[32] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( p1498 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1461 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1498 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+sb_1__0_ sb_4__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) ,
+ .chany_top_in ( cby_1__1__36_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__4_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__3_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_7_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__3_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__3_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1067 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( p1473 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2081 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2082 ) ,
+ .pReset_E_in ( pResetWires[37] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2083 ) ,
+ .pReset_N_out ( pResetWires[36] ) , .pReset_W_out ( pResetWires[35] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( p1473 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1473 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1473 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+sb_1__0_ sb_5__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) ,
+ .chany_top_in ( cby_1__1__48_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__5_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__4_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_6_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__4_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__4_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) ,
+ .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1205 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2089 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2090 ) ,
+ .pReset_E_in ( pResetWires[40] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2091 ) ,
+ .pReset_N_out ( pResetWires[39] ) , .pReset_W_out ( pResetWires[38] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( p1205 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1205 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1205 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+sb_1__0_ sb_6__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) ,
+ .chany_top_in ( cby_1__1__60_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__6_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__5_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_5_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__5_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__5_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1397 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2097 ) , .Test_en_S_in ( Test_en[0] ) ,
+ .Test_en_N_out ( Test_enWires[1] ) , .pReset_S_in ( pReset[0] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2098 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2099 ) ,
+ .pReset_N_out ( pResetWires[42] ) , .pReset_W_out ( pResetWires[41] ) ,
+ .pReset_E_out ( pResetWires[43] ) , .Reset_S_in ( Reset[0] ) ,
+ .Reset_N_out ( ResetWires[1] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[217] ) ,
+ .prog_clk_3_S_in ( prog_clk[0] ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[90] ) , .clk_3_S_in ( clk[0] ) ,
+ .clk_3_N_out ( clk_3_wires[90] ) ) ;
+sb_1__0_ sb_7__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2100 } ) ,
+ .chany_top_in ( cby_1__1__72_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__7_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__6_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_4_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__6_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__6_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) ,
+ .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p340 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2101 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2102 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2103 ) ,
+ .pReset_W_in ( pResetWires[44] ) , .pReset_N_out ( pResetWires[45] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2104 ) ,
+ .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( p340 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2105 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p340 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p340 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+sb_1__0_ sb_8__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2108 } ) ,
+ .chany_top_in ( cby_1__1__84_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__8_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__7_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_3_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__7_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__7_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1556 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2109 ) , .Test_en_S_in ( p956 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2110 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2111 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2112 ) ,
+ .pReset_W_in ( pResetWires[47] ) , .pReset_N_out ( pResetWires[48] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2113 ) ,
+ .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( p956 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2114 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p956 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p956 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+sb_1__0_ sb_9__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2117 } ) ,
+ .chany_top_in ( cby_1__1__96_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__9_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__8_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_2_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__8_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__8_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) ,
+ .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p1216 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2118 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2119 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2120 ) ,
+ .pReset_W_in ( pResetWires[50] ) , .pReset_N_out ( pResetWires[51] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2121 ) ,
+ .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( p1216 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2122 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1216 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p1216 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+sb_1__0_ sb_10__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2125 } ) ,
+ .chany_top_in ( cby_1__1__108_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__10_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__9_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_1_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__9_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__9_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p949 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2126 ) , .Test_en_S_in ( p657 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2127 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2128 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2129 ) ,
+ .pReset_W_in ( pResetWires[53] ) , .pReset_N_out ( pResetWires[54] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2130 ) ,
+ .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( p657 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2131 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p657 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p657 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+sb_1__0_ sb_11__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2134 } ) ,
+ .chany_top_in ( cby_1__1__120_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__11_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__10_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_0_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__10_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__10_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) ,
+ .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1253 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2135 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2136 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2137 ) ,
+ .pReset_W_in ( pResetWires[56] ) , .pReset_N_out ( pResetWires[57] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2138 ) ,
+ .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( p1253 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2139 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1151 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1253 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+sb_1__1_ sb_1__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2142 } ) ,
+ .chany_top_in ( cby_1__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__11_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__0_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__0_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__11_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__0_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p3095 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2143 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2144 ) ,
+ .pReset_E_in ( pResetWires[66] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2145 ) ,
+ .pReset_N_out ( pResetWires[65] ) , .pReset_W_out ( pResetWires[62] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2146 ) , .Reset_S_in ( p3478 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2147 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[8] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[4] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2148 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[1] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p2808 ) ,
+ .prog_clk_2_E_in ( p454 ) , .prog_clk_2_S_in ( p852 ) ,
+ .prog_clk_2_W_in ( p165 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2149 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2150 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2151 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2152 ) ,
+ .prog_clk_3_W_in ( p2427 ) , .prog_clk_3_E_in ( p670 ) ,
+ .prog_clk_3_S_in ( p3469 ) , .prog_clk_3_N_in ( p2724 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2153 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2154 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2155 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2156 ) ,
+ .clk_1_N_in ( clk_2_wires[4] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2157 ) ,
+ .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) ,
+ .clk_2_N_in ( p3369 ) , .clk_2_E_in ( p223 ) , .clk_2_S_in ( p265 ) ,
+ .clk_2_W_in ( p2905 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2158 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2159 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2160 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2161 ) , .clk_3_W_in ( p2985 ) ,
+ .clk_3_E_in ( p1021 ) , .clk_3_S_in ( p1138 ) , .clk_3_N_in ( p3329 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2162 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2163 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2164 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+sb_1__1_ sb_1__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2166 } ) ,
+ .chany_top_in ( cby_1__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__12_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__1_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__1_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__12_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__1_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p3269 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2167 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2168 ) ,
+ .pReset_E_in ( pResetWires[115] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2169 ) ,
+ .pReset_N_out ( pResetWires[114] ) , .pReset_W_out ( pResetWires[111] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , .Reset_S_in ( p3199 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2171 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p2102 ) ,
+ .prog_clk_1_S_in ( p1041 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2172 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2173 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2174 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[1] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2175 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2176 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2177 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[3] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2178 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2179 ) ,
+ .prog_clk_3_W_in ( p1949 ) , .prog_clk_3_E_in ( p1321 ) ,
+ .prog_clk_3_S_in ( p3250 ) , .prog_clk_3_N_in ( p410 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2180 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2181 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2182 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p2102 ) ,
+ .clk_1_S_in ( p107 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2185 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2186 ) ,
+ .clk_2_E_in ( clk_2_wires[1] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2187 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2188 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2189 ) ,
+ .clk_2_S_out ( clk_2_wires[3] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2190 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p1949 ) ,
+ .clk_3_E_in ( p367 ) , .clk_3_S_in ( p883 ) , .clk_3_N_in ( p2015 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2192 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2193 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2194 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sb_1__1_ sb_1__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2196 } ) ,
+ .chany_top_in ( cby_1__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__13_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__2_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__2_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__13_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__2_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p2692 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2197 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2198 ) ,
+ .pReset_E_in ( pResetWires[164] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2199 ) ,
+ .pReset_N_out ( pResetWires[163] ) , .pReset_W_out ( pResetWires[160] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2200 ) , .Reset_S_in ( p3528 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2201 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[18] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[11] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2202 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[8] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3014 ) ,
+ .prog_clk_2_E_in ( p863 ) , .prog_clk_2_S_in ( p1128 ) ,
+ .prog_clk_2_W_in ( p488 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2203 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2204 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2205 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2206 ) ,
+ .prog_clk_3_W_in ( p2650 ) , .prog_clk_3_E_in ( p445 ) ,
+ .prog_clk_3_S_in ( p3518 ) , .prog_clk_3_N_in ( p2925 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2207 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2208 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2209 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2210 ) ,
+ .clk_1_N_in ( clk_2_wires[11] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2211 ) ,
+ .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) ,
+ .clk_2_N_in ( p3487 ) , .clk_2_E_in ( p136 ) , .clk_2_S_in ( p593 ) ,
+ .clk_2_W_in ( p2544 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2212 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2213 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2214 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2215 ) , .clk_3_W_in ( p2416 ) ,
+ .clk_3_E_in ( p985 ) , .clk_3_S_in ( p128 ) , .clk_3_N_in ( p3476 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2216 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2217 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2218 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+sb_1__1_ sb_1__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2220 } ) ,
+ .chany_top_in ( cby_1__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__14_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__3_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__3_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__14_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__3_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p3202 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2221 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2222 ) ,
+ .pReset_E_in ( pResetWires[213] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2223 ) ,
+ .pReset_N_out ( pResetWires[212] ) , .pReset_W_out ( pResetWires[209] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , .Reset_S_in ( p3129 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2225 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p1241 ) ,
+ .prog_clk_1_S_in ( p1096 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2226 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2227 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2228 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[6] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2229 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2230 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2231 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[10] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[8] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2232 ) ,
+ .prog_clk_3_W_in ( p1468 ) , .prog_clk_3_E_in ( p1278 ) ,
+ .prog_clk_3_S_in ( p3147 ) , .prog_clk_3_N_in ( p1648 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2233 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2234 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2235 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2236 ) , .clk_1_N_in ( p1241 ) ,
+ .clk_1_S_in ( p112 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2238 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2239 ) ,
+ .clk_2_E_in ( clk_2_wires[6] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2240 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2241 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2242 ) ,
+ .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2243 ) , .clk_3_W_in ( p1468 ) ,
+ .clk_3_E_in ( p176 ) , .clk_3_S_in ( p1082 ) , .clk_3_N_in ( p431 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2244 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2245 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2246 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+sb_1__1_ sb_1__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2248 } ) ,
+ .chany_top_in ( cby_1__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__15_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__4_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__4_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__15_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__4_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p3354 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2249 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2250 ) ,
+ .pReset_E_in ( pResetWires[262] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2251 ) ,
+ .pReset_N_out ( pResetWires[261] ) , .pReset_W_out ( pResetWires[258] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2252 ) , .Reset_S_in ( p2693 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2253 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[28] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2254 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[9] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[15] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p2858 ) ,
+ .prog_clk_2_E_in ( p870 ) , .prog_clk_2_S_in ( p877 ) ,
+ .prog_clk_2_W_in ( p468 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2255 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2256 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2257 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2258 ) ,
+ .prog_clk_3_W_in ( p3009 ) , .prog_clk_3_E_in ( p73 ) ,
+ .prog_clk_3_S_in ( p3318 ) , .prog_clk_3_N_in ( p2756 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2259 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2260 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2261 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2262 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2263 ) ,
+ .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) ,
+ .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p2957 ) ,
+ .clk_2_E_in ( p1108 ) , .clk_2_S_in ( p614 ) , .clk_2_W_in ( p3051 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2264 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2265 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2266 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2267 ) , .clk_3_W_in ( p3096 ) ,
+ .clk_3_E_in ( p248 ) , .clk_3_S_in ( p109 ) , .clk_3_N_in ( p2927 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2268 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2269 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2270 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+sb_1__1_ sb_1__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2272 } ) ,
+ .chany_top_in ( cby_1__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__16_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__5_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__5_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__16_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__5_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p3447 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2273 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2274 ) ,
+ .pReset_E_in ( pResetWires[311] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2275 ) ,
+ .pReset_N_out ( pResetWires[310] ) , .pReset_W_out ( pResetWires[307] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , .Reset_S_in ( p3461 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2277 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p1770 ) ,
+ .prog_clk_1_S_in ( p778 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2278 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2279 ) ,
+ .prog_clk_2_N_in ( p3296 ) , .prog_clk_2_E_in ( p403 ) ,
+ .prog_clk_2_S_in ( p185 ) , .prog_clk_2_W_in ( p63 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2280 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2281 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2282 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2283 ) ,
+ .prog_clk_3_W_in ( p3398 ) , .prog_clk_3_E_in ( p184 ) ,
+ .prog_clk_3_S_in ( p3440 ) , .prog_clk_3_N_in ( p3252 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2284 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2285 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2286 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_1_N_in ( p1770 ) ,
+ .clk_1_S_in ( p49 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2288 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2289 ) , .clk_2_N_in ( p3488 ) ,
+ .clk_2_E_in ( p825 ) , .clk_2_S_in ( p1032 ) , .clk_2_W_in ( p3391 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2290 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2291 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2292 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2293 ) , .clk_3_W_in ( p3123 ) ,
+ .clk_3_E_in ( p633 ) , .clk_3_S_in ( p1085 ) , .clk_3_N_in ( p3464 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2294 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2295 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2296 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+sb_1__1_ sb_1__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2298 } ) ,
+ .chany_top_in ( cby_1__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__17_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__6_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__6_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__17_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__6_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2981 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2299 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2300 ) ,
+ .pReset_E_in ( pResetWires[360] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2301 ) ,
+ .pReset_N_out ( pResetWires[359] ) , .pReset_W_out ( pResetWires[356] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2302 ) , .Reset_S_in ( p3566 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2303 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[38] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[18] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2304 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[22] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p2068 ) ,
+ .prog_clk_2_E_in ( p17 ) , .prog_clk_2_S_in ( p691 ) ,
+ .prog_clk_2_W_in ( p523 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2305 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2306 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2307 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2308 ) ,
+ .prog_clk_3_W_in ( p3363 ) , .prog_clk_3_E_in ( p613 ) ,
+ .prog_clk_3_S_in ( p3562 ) , .prog_clk_3_N_in ( p1975 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2309 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2310 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2311 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2312 ) ,
+ .clk_1_N_in ( clk_2_wires[18] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2313 ) ,
+ .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) ,
+ .clk_2_N_in ( p3417 ) , .clk_2_E_in ( p934 ) , .clk_2_S_in ( p1005 ) ,
+ .clk_2_W_in ( p3320 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2315 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2316 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , .clk_3_W_in ( p2455 ) ,
+ .clk_3_E_in ( p354 ) , .clk_3_S_in ( p140 ) , .clk_3_N_in ( p3377 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2318 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2319 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2320 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+sb_1__1_ sb_1__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2322 } ) ,
+ .chany_top_in ( cby_1__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__18_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__7_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__7_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__18_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__7_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p3362 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2323 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2324 ) ,
+ .pReset_E_in ( pResetWires[409] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2325 ) ,
+ .pReset_N_out ( pResetWires[408] ) , .pReset_W_out ( pResetWires[405] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , .Reset_S_in ( p3459 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2327 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p2182 ) ,
+ .prog_clk_1_S_in ( p398 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2328 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2329 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2330 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[13] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2331 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2332 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2333 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[17] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[15] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2334 ) ,
+ .prog_clk_3_W_in ( p1899 ) , .prog_clk_3_E_in ( p722 ) ,
+ .prog_clk_3_S_in ( p3430 ) , .prog_clk_3_N_in ( p1289 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2335 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2336 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2337 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2338 ) , .clk_1_N_in ( p2182 ) ,
+ .clk_1_S_in ( p1057 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2339 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2340 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2341 ) ,
+ .clk_2_E_in ( clk_2_wires[13] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2342 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2343 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2344 ) ,
+ .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2345 ) , .clk_3_W_in ( p1899 ) ,
+ .clk_3_E_in ( p245 ) , .clk_3_S_in ( p52 ) , .clk_3_N_in ( p1965 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2346 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2347 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2348 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+sb_1__1_ sb_1__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2350 } ) ,
+ .chany_top_in ( cby_1__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__19_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__8_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__8_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__19_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__8_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p3091 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2351 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2352 ) ,
+ .pReset_E_in ( pResetWires[458] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2353 ) ,
+ .pReset_N_out ( pResetWires[457] ) , .pReset_W_out ( pResetWires[454] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2354 ) , .Reset_S_in ( p2704 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2355 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[48] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2356 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[16] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[29] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3544 ) ,
+ .prog_clk_2_E_in ( p252 ) , .prog_clk_2_S_in ( p1185 ) ,
+ .prog_clk_2_W_in ( p255 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2357 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2358 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2359 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2360 ) ,
+ .prog_clk_3_W_in ( p3492 ) , .prog_clk_3_E_in ( p602 ) ,
+ .prog_clk_3_S_in ( p3025 ) , .prog_clk_3_N_in ( p3536 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2361 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2362 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2363 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2364 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2365 ) ,
+ .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) ,
+ .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p3533 ) ,
+ .clk_2_E_in ( p572 ) , .clk_2_S_in ( p1206 ) , .clk_2_W_in ( p3470 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2366 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2367 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2368 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_3_W_in ( p2974 ) ,
+ .clk_3_E_in ( p832 ) , .clk_3_S_in ( p725 ) , .clk_3_N_in ( p3520 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2370 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2371 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2372 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+sb_1__1_ sb_1__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2374 } ) ,
+ .chany_top_in ( cby_1__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__20_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__9_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__9_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__20_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__9_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p3367 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2375 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2376 ) ,
+ .pReset_E_in ( pResetWires[507] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2377 ) ,
+ .pReset_N_out ( pResetWires[506] ) , .pReset_W_out ( pResetWires[503] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , .Reset_S_in ( p2860 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2379 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p1900 ) ,
+ .prog_clk_1_S_in ( p143 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2380 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2381 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2382 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[20] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2383 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2384 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2385 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2386 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[22] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2387 ) ,
+ .prog_clk_3_W_in ( p1610 ) , .prog_clk_3_E_in ( p1329 ) ,
+ .prog_clk_3_S_in ( p3305 ) , .prog_clk_3_N_in ( p1705 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2388 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2389 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2390 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2391 ) , .clk_1_N_in ( p1900 ) ,
+ .clk_1_S_in ( p973 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2392 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2393 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2394 ) ,
+ .clk_2_E_in ( clk_2_wires[20] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2395 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2396 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2397 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2398 ) ,
+ .clk_2_N_out ( clk_2_wires[22] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_3_W_in ( p1610 ) ,
+ .clk_3_E_in ( p64 ) , .clk_3_S_in ( p616 ) , .clk_3_N_in ( p1626 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2400 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2401 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2402 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+sb_1__1_ sb_1__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2404 } ) ,
+ .chany_top_in ( cby_1__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__21_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__10_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__10_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__21_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__10_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p3133 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2405 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2406 ) ,
+ .pReset_E_in ( pResetWires[556] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2407 ) ,
+ .pReset_N_out ( pResetWires[555] ) , .pReset_W_out ( pResetWires[552] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2408 ) , .Reset_S_in ( p3449 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2409 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[58] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2410 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[23] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[36] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p2610 ) ,
+ .prog_clk_2_E_in ( p714 ) , .prog_clk_2_S_in ( p1049 ) ,
+ .prog_clk_2_W_in ( p634 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2411 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2412 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2413 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2414 ) ,
+ .prog_clk_3_W_in ( p1866 ) , .prog_clk_3_E_in ( p519 ) ,
+ .prog_clk_3_S_in ( p3424 ) , .prog_clk_3_N_in ( p2550 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2415 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2416 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2417 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2418 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2419 ) ,
+ .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) ,
+ .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p3274 ) ,
+ .clk_2_E_in ( p1059 ) , .clk_2_S_in ( p1431 ) , .clk_2_W_in ( p1955 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2420 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2421 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2422 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_3_W_in ( p2183 ) ,
+ .clk_3_E_in ( p142 ) , .clk_3_S_in ( p1364 ) , .clk_3_N_in ( p3235 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2424 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2425 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2426 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+sb_1__1_ sb_2__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2428 } ) ,
+ .chany_top_in ( cby_1__1__13_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__22_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__12_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__11_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__22_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__11_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__11_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__11_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p3119 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2429 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2430 ) ,
+ .pReset_E_in ( pResetWires[70] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2431 ) ,
+ .pReset_N_out ( pResetWires[69] ) , .pReset_W_out ( pResetWires[67] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , .Reset_S_in ( p2842 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2433 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p1477 ) ,
+ .prog_clk_1_S_in ( p1102 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2434 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2435 ) ,
+ .prog_clk_2_N_in ( p3002 ) , .prog_clk_2_E_in ( p856 ) ,
+ .prog_clk_2_S_in ( p711 ) , .prog_clk_2_W_in ( p700 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2436 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2437 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2438 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2439 ) ,
+ .prog_clk_3_W_in ( p2868 ) , .prog_clk_3_E_in ( p774 ) ,
+ .prog_clk_3_S_in ( p3037 ) , .prog_clk_3_N_in ( p2903 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2440 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2441 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2442 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_1_N_in ( p1477 ) ,
+ .clk_1_S_in ( p300 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2444 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_2_N_in ( p2873 ) ,
+ .clk_2_E_in ( p905 ) , .clk_2_S_in ( p1115 ) , .clk_2_W_in ( p3036 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2446 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2447 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2448 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_3_W_in ( p3122 ) ,
+ .clk_3_E_in ( p50 ) , .clk_3_S_in ( p119 ) , .clk_3_N_in ( p2751 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2450 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2451 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2452 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+sb_1__1_ sb_2__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2454 } ) ,
+ .chany_top_in ( cby_1__1__14_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__23_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__13_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__12_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__23_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__12_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__12_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__12_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p2821 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2455 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2456 ) ,
+ .pReset_E_in ( pResetWires[119] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2457 ) ,
+ .pReset_N_out ( pResetWires[118] ) , .pReset_W_out ( pResetWires[116] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , .Reset_S_in ( p2158 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2459 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p1532 ) ,
+ .prog_clk_1_S_in ( p544 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2460 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2461 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[69] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2462 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2463 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2464 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[2] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2465 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2466 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2467 ) ,
+ .prog_clk_3_W_in ( p1594 ) , .prog_clk_3_E_in ( p717 ) ,
+ .prog_clk_3_S_in ( p2747 ) , .prog_clk_3_N_in ( p601 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2468 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2469 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2470 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , .clk_1_N_in ( p1532 ) ,
+ .clk_1_S_in ( p25 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2472 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2473 ) ,
+ .clk_2_N_in ( clk_3_wires[69] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2474 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2475 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2476 ) ,
+ .clk_2_W_out ( clk_2_wires[2] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2477 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2478 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2479 ) , .clk_3_W_in ( p1594 ) ,
+ .clk_3_E_in ( p62 ) , .clk_3_S_in ( p955 ) , .clk_3_N_in ( p1286 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2480 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2481 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2482 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+sb_1__1_ sb_2__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2484 } ) ,
+ .chany_top_in ( cby_1__1__15_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__24_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__14_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__13_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__24_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__13_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__13_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__13_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2669 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2485 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2486 ) ,
+ .pReset_E_in ( pResetWires[168] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2487 ) ,
+ .pReset_N_out ( pResetWires[167] ) , .pReset_W_out ( pResetWires[165] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , .Reset_S_in ( p3301 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2489 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1546 ) ,
+ .prog_clk_1_S_in ( p1056 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2490 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2491 ) ,
+ .prog_clk_2_N_in ( p2149 ) , .prog_clk_2_E_in ( p742 ) ,
+ .prog_clk_2_S_in ( p3249 ) , .prog_clk_2_W_in ( p581 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2492 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2493 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2494 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2495 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2496 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2497 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2498 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[65] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2499 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2500 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2501 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1546 ) ,
+ .clk_1_S_in ( p205 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2502 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .clk_2_N_in ( p2149 ) ,
+ .clk_2_E_in ( p220 ) , .clk_2_S_in ( p1402 ) , .clk_2_W_in ( p236 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2504 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2505 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2506 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2507 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2508 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2509 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2510 ) ,
+ .clk_3_N_in ( clk_3_wires[65] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2511 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2512 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2513 ) ,
+ .clk_3_S_out ( clk_3_wires[68] ) ) ;
+sb_1__1_ sb_2__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2514 } ) ,
+ .chany_top_in ( cby_1__1__16_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__25_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__15_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__14_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__25_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__14_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__14_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__14_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p2198 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2515 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2516 ) ,
+ .pReset_E_in ( pResetWires[217] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2517 ) ,
+ .pReset_N_out ( pResetWires[216] ) , .pReset_W_out ( pResetWires[214] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , .Reset_S_in ( p2198 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2519 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1240 ) ,
+ .prog_clk_1_S_in ( p1989 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2520 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2521 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[59] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2522 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2523 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2524 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[7] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2525 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2526 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2527 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2528 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2529 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2530 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[59] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2531 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2532 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2533 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1240 ) ,
+ .clk_1_S_in ( p141 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2534 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2535 ) ,
+ .clk_2_N_in ( clk_3_wires[59] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2536 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2537 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2538 ) ,
+ .clk_2_W_out ( clk_2_wires[7] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2539 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2540 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2541 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2542 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2543 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2544 ) ,
+ .clk_3_N_in ( clk_3_wires[59] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2545 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2546 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2547 ) ,
+ .clk_3_S_out ( clk_3_wires[64] ) ) ;
+sb_1__1_ sb_2__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2548 } ) ,
+ .chany_top_in ( cby_1__1__17_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__26_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__16_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__15_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__26_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__15_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__15_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__15_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2797 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2549 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2550 ) ,
+ .pReset_E_in ( pResetWires[266] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2551 ) ,
+ .pReset_N_out ( pResetWires[265] ) , .pReset_W_out ( pResetWires[263] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , .Reset_S_in ( p3364 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2553 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1250 ) ,
+ .prog_clk_1_S_in ( p579 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2554 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2555 ) ,
+ .prog_clk_2_N_in ( p1450 ) , .prog_clk_2_E_in ( p994 ) ,
+ .prog_clk_2_S_in ( p3321 ) , .prog_clk_2_W_in ( p662 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2556 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2557 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2558 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2559 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2560 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2561 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2562 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[55] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2563 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2564 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2565 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1250 ) ,
+ .clk_1_S_in ( p51 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2566 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2567 ) , .clk_2_N_in ( p1450 ) ,
+ .clk_2_E_in ( p558 ) , .clk_2_S_in ( p1640 ) , .clk_2_W_in ( p195 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2568 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2569 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2570 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2571 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2572 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2573 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2574 ) ,
+ .clk_3_N_in ( clk_3_wires[55] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2575 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2576 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2577 ) ,
+ .clk_3_S_out ( clk_3_wires[58] ) ) ;
+sb_1__1_ sb_2__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2578 } ) ,
+ .chany_top_in ( cby_1__1__18_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__27_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__17_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__16_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__27_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__16_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__16_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__16_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p2378 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2579 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2580 ) ,
+ .pReset_E_in ( pResetWires[315] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2581 ) ,
+ .pReset_N_out ( pResetWires[314] ) , .pReset_W_out ( pResetWires[312] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , .Reset_S_in ( p3457 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2583 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1442 ) ,
+ .prog_clk_1_S_in ( p217 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2584 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2585 ) ,
+ .prog_clk_2_N_in ( p2359 ) , .prog_clk_2_E_in ( p42 ) ,
+ .prog_clk_2_S_in ( p3428 ) , .prog_clk_2_W_in ( p274 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2586 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2587 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2588 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2589 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2590 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[51] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2591 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2592 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2593 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2594 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[52] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1442 ) ,
+ .clk_1_S_in ( p1004 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2595 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2596 ) , .clk_2_N_in ( p1347 ) ,
+ .clk_2_E_in ( p693 ) , .clk_2_S_in ( p1973 ) , .clk_2_W_in ( p138 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2597 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2598 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2599 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2600 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2601 ) ,
+ .clk_3_E_in ( clk_3_wires[51] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2602 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2603 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2604 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2605 ) ,
+ .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) ) ;
+sb_1__1_ sb_2__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2606 } ) ,
+ .chany_top_in ( cby_1__1__19_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__28_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__18_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__17_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__28_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__17_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__17_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__17_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p954 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2607 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2608 ) ,
+ .pReset_E_in ( pResetWires[364] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2609 ) ,
+ .pReset_N_out ( pResetWires[363] ) , .pReset_W_out ( pResetWires[361] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , .Reset_S_in ( p2965 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2611 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1194 ) ,
+ .prog_clk_1_S_in ( p900 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2612 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2613 ) ,
+ .prog_clk_2_N_in ( p2812 ) , .prog_clk_2_E_in ( p126 ) ,
+ .prog_clk_2_S_in ( p2907 ) , .prog_clk_2_W_in ( p422 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2614 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2615 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2616 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2617 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2618 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2619 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[53] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2620 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2621 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2622 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[56] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_1_N_in ( p1194 ) ,
+ .clk_1_S_in ( p210 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2624 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2625 ) , .clk_2_N_in ( p2181 ) ,
+ .clk_2_E_in ( p423 ) , .clk_2_S_in ( p952 ) , .clk_2_W_in ( p167 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2626 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2627 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2628 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2629 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2630 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2631 ) ,
+ .clk_3_S_in ( clk_3_wires[53] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2632 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2633 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2634 ) ,
+ .clk_3_N_out ( clk_3_wires[56] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+sb_1__1_ sb_2__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2636 } ) ,
+ .chany_top_in ( cby_1__1__20_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__29_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__19_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__18_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__29_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__18_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__18_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__18_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p2236 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2637 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2638 ) ,
+ .pReset_E_in ( pResetWires[413] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2639 ) ,
+ .pReset_N_out ( pResetWires[412] ) , .pReset_W_out ( pResetWires[410] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , .Reset_S_in ( p2236 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2641 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1579 ) ,
+ .prog_clk_1_S_in ( p1974 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2642 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2643 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2644 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2645 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[57] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2646 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[14] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2647 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2648 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2649 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2650 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2651 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[57] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2652 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2653 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2654 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[62] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2655 ) , .clk_1_N_in ( p1579 ) ,
+ .clk_1_S_in ( p966 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2656 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2657 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2658 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2659 ) ,
+ .clk_2_S_in ( clk_3_wires[57] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2660 ) ,
+ .clk_2_W_out ( clk_2_wires[14] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2661 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2662 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2663 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2664 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2665 ) ,
+ .clk_3_S_in ( clk_3_wires[57] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2666 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2667 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2668 ) ,
+ .clk_3_N_out ( clk_3_wires[62] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+sb_1__1_ sb_2__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2670 } ) ,
+ .chany_top_in ( cby_1__1__21_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__30_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__20_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__19_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__30_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__19_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__19_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__19_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p2622 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2671 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2672 ) ,
+ .pReset_E_in ( pResetWires[462] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2673 ) ,
+ .pReset_N_out ( pResetWires[461] ) , .pReset_W_out ( pResetWires[459] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , .Reset_S_in ( p3218 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2675 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1337 ) ,
+ .prog_clk_1_S_in ( p316 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2676 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2677 ) ,
+ .prog_clk_2_N_in ( p2214 ) , .prog_clk_2_E_in ( p144 ) ,
+ .prog_clk_2_S_in ( p3165 ) , .prog_clk_2_W_in ( p733 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2678 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2679 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2680 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2681 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2682 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2683 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[63] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2684 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2685 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2686 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[66] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_1_N_in ( p1337 ) ,
+ .clk_1_S_in ( p447 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2688 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_2_N_in ( p1538 ) ,
+ .clk_2_E_in ( p923 ) , .clk_2_S_in ( p1668 ) , .clk_2_W_in ( p191 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2690 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2691 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2692 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2693 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2694 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2695 ) ,
+ .clk_3_S_in ( clk_3_wires[63] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2696 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2697 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2698 ) ,
+ .clk_3_N_out ( clk_3_wires[66] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+sb_1__1_ sb_2__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2700 } ) ,
+ .chany_top_in ( cby_1__1__22_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__31_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__21_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__20_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__31_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__20_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__20_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__20_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p3284 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2701 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2702 ) ,
+ .pReset_E_in ( pResetWires[511] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2703 ) ,
+ .pReset_N_out ( pResetWires[510] ) , .pReset_W_out ( pResetWires[508] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , .Reset_S_in ( p3509 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2705 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p2138 ) ,
+ .prog_clk_1_S_in ( p578 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2706 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2707 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2708 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2709 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[67] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2710 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[21] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2711 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2712 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2713 ) ,
+ .prog_clk_3_W_in ( p1571 ) , .prog_clk_3_E_in ( p147 ) ,
+ .prog_clk_3_S_in ( p3495 ) , .prog_clk_3_N_in ( p590 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2714 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2715 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2716 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , .clk_1_N_in ( p2138 ) ,
+ .clk_1_S_in ( p203 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2718 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2719 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2720 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2721 ) ,
+ .clk_2_S_in ( clk_3_wires[67] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2722 ) ,
+ .clk_2_W_out ( clk_2_wires[21] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2723 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2724 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , .clk_3_W_in ( p1571 ) ,
+ .clk_3_E_in ( p750 ) , .clk_3_S_in ( p1262 ) , .clk_3_N_in ( p2006 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2726 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2727 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2728 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+sb_1__1_ sb_2__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2730 } ) ,
+ .chany_top_in ( cby_1__1__23_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__32_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__22_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__21_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__32_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__21_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__21_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__21_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p2975 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2731 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2732 ) ,
+ .pReset_E_in ( pResetWires[560] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2733 ) ,
+ .pReset_N_out ( pResetWires[559] ) , .pReset_W_out ( pResetWires[557] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , .Reset_S_in ( p3177 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2735 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p2195 ) ,
+ .prog_clk_1_S_in ( p483 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2736 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2737 ) ,
+ .prog_clk_2_N_in ( p2616 ) , .prog_clk_2_E_in ( p991 ) ,
+ .prog_clk_2_S_in ( p1134 ) , .prog_clk_2_W_in ( p680 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2738 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2739 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2740 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2741 ) ,
+ .prog_clk_3_W_in ( p2848 ) , .prog_clk_3_E_in ( p373 ) ,
+ .prog_clk_3_S_in ( p3149 ) , .prog_clk_3_N_in ( p2512 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2742 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2743 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2744 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_1_N_in ( p2147 ) ,
+ .clk_1_S_in ( p862 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2746 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .clk_2_N_in ( p3224 ) ,
+ .clk_2_E_in ( p360 ) , .clk_2_S_in ( p133 ) , .clk_2_W_in ( p2882 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2748 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2749 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2750 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2751 ) , .clk_3_W_in ( p2995 ) ,
+ .clk_3_E_in ( p1090 ) , .clk_3_S_in ( p999 ) , .clk_3_N_in ( p3136 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2752 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2753 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2754 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+sb_1__1_ sb_3__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2756 } ) ,
+ .chany_top_in ( cby_1__1__25_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__33_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__24_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__22_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__33_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__22_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__22_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__22_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p3356 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2757 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2758 ) ,
+ .pReset_E_in ( pResetWires[74] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2759 ) ,
+ .pReset_N_out ( pResetWires[73] ) , .pReset_W_out ( pResetWires[71] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2760 ) , .Reset_S_in ( p3271 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2761 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[106] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[30] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2762 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[43] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p3511 ) ,
+ .prog_clk_2_E_in ( p448 ) , .prog_clk_2_S_in ( p848 ) ,
+ .prog_clk_2_W_in ( p289 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2763 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2764 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2765 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2766 ) ,
+ .prog_clk_3_W_in ( p2495 ) , .prog_clk_3_E_in ( p153 ) ,
+ .prog_clk_3_S_in ( p3317 ) , .prog_clk_3_N_in ( p3494 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2767 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2768 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2769 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2770 ) ,
+ .clk_1_N_in ( clk_2_wires[30] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2771 ) ,
+ .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) ,
+ .clk_2_N_in ( p1629 ) , .clk_2_E_in ( p229 ) , .clk_2_S_in ( p821 ) ,
+ .clk_2_W_in ( p2729 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2772 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2773 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2774 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2775 ) , .clk_3_W_in ( p2791 ) ,
+ .clk_3_E_in ( p1136 ) , .clk_3_S_in ( p27 ) , .clk_3_N_in ( p1753 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2776 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2777 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2778 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+sb_1__1_ sb_3__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2780 } ) ,
+ .chany_top_in ( cby_1__1__26_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__34_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__25_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__23_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__34_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__23_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__23_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__23_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2229 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2781 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2782 ) ,
+ .pReset_E_in ( pResetWires[123] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2783 ) ,
+ .pReset_N_out ( pResetWires[122] ) , .pReset_W_out ( pResetWires[120] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , .Reset_S_in ( p3076 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2785 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1771 ) ,
+ .prog_clk_1_S_in ( p500 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2786 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2787 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2788 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[28] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2789 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2790 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2791 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[29] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2792 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2793 ) ,
+ .prog_clk_3_W_in ( p1766 ) , .prog_clk_3_E_in ( p1633 ) ,
+ .prog_clk_3_S_in ( p3033 ) , .prog_clk_3_N_in ( p537 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2794 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2795 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2796 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2797 ) , .clk_1_N_in ( p1771 ) ,
+ .clk_1_S_in ( p227 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2799 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2800 ) ,
+ .clk_2_E_in ( clk_2_wires[28] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2801 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2802 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2803 ) ,
+ .clk_2_S_out ( clk_2_wires[29] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2804 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2805 ) , .clk_3_W_in ( p1766 ) ,
+ .clk_3_E_in ( p993 ) , .clk_3_S_in ( p319 ) , .clk_3_N_in ( p1696 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2806 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2807 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2808 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+sb_1__1_ sb_3__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2810 } ) ,
+ .chany_top_in ( cby_1__1__27_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__35_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__26_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__24_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__35_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__24_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__24_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__24_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p3489 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2811 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2812 ) ,
+ .pReset_E_in ( pResetWires[172] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2813 ) ,
+ .pReset_N_out ( pResetWires[171] ) , .pReset_W_out ( pResetWires[169] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , .Reset_S_in ( p3545 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2815 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[112] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[41] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2816 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[50] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p3213 ) ,
+ .prog_clk_2_E_in ( p75 ) , .prog_clk_2_S_in ( p992 ) ,
+ .prog_clk_2_W_in ( p413 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2817 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2818 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2819 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2820 ) ,
+ .prog_clk_3_W_in ( p3263 ) , .prog_clk_3_E_in ( p730 ) ,
+ .prog_clk_3_S_in ( p3538 ) , .prog_clk_3_N_in ( p3170 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2821 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2822 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2823 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2824 ) ,
+ .clk_1_N_in ( clk_2_wires[41] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2825 ) ,
+ .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) ,
+ .clk_2_N_in ( p3289 ) , .clk_2_E_in ( p554 ) , .clk_2_S_in ( p1127 ) ,
+ .clk_2_W_in ( p3231 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2826 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2827 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2828 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2829 ) , .clk_3_W_in ( p1803 ) ,
+ .clk_3_E_in ( p1000 ) , .clk_3_S_in ( p169 ) , .clk_3_N_in ( p3255 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2832 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+sb_1__1_ sb_3__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2834 } ) ,
+ .chany_top_in ( cby_1__1__28_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__36_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__27_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__25_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__36_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__25_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__25_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__25_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2952 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2835 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2836 ) ,
+ .pReset_E_in ( pResetWires[221] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2837 ) ,
+ .pReset_N_out ( pResetWires[220] ) , .pReset_W_out ( pResetWires[218] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , .Reset_S_in ( p2210 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2839 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p2126 ) ,
+ .prog_clk_1_S_in ( p362 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2840 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2841 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2842 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[37] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2843 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2844 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2845 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[40] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[38] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2846 ) ,
+ .prog_clk_3_W_in ( p1204 ) , .prog_clk_3_E_in ( p1324 ) ,
+ .prog_clk_3_S_in ( p2912 ) , .prog_clk_3_N_in ( p1614 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2847 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2848 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2849 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2850 ) , .clk_1_N_in ( p2126 ) ,
+ .clk_1_S_in ( p1078 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2851 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2852 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2853 ) ,
+ .clk_2_E_in ( clk_2_wires[37] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2854 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2855 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2856 ) ,
+ .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2857 ) , .clk_3_W_in ( p1204 ) ,
+ .clk_3_E_in ( p358 ) , .clk_3_S_in ( p296 ) , .clk_3_N_in ( p1951 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2858 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2859 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2860 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+sb_1__1_ sb_3__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2862 } ) ,
+ .chany_top_in ( cby_1__1__29_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__37_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__28_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__26_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__37_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__26_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__26_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__26_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p2806 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2863 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2864 ) ,
+ .pReset_E_in ( pResetWires[270] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2865 ) ,
+ .pReset_N_out ( pResetWires[269] ) , .pReset_W_out ( pResetWires[267] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2866 ) , .Reset_S_in ( p3283 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2867 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[118] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2868 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[39] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[57] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3506 ) ,
+ .prog_clk_2_E_in ( p1015 ) , .prog_clk_2_S_in ( p567 ) ,
+ .prog_clk_2_W_in ( p515 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2869 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2870 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2871 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2872 ) ,
+ .prog_clk_3_W_in ( p2854 ) , .prog_clk_3_E_in ( p751 ) ,
+ .prog_clk_3_S_in ( p3257 ) , .prog_clk_3_N_in ( p3505 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2873 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2874 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2875 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2876 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2877 ) ,
+ .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) ,
+ .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p3507 ) ,
+ .clk_2_E_in ( p44 ) , .clk_2_S_in ( p23 ) , .clk_2_W_in ( p2910 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2878 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2879 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2880 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , .clk_3_W_in ( p2941 ) ,
+ .clk_3_E_in ( p752 ) , .clk_3_S_in ( p759 ) , .clk_3_N_in ( p3500 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2882 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2883 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2884 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+sb_1__1_ sb_3__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2886 } ) ,
+ .chany_top_in ( cby_1__1__30_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__38_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__29_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__27_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__38_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__27_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__27_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__27_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p2215 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2887 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2888 ) ,
+ .pReset_E_in ( pResetWires[319] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2889 ) ,
+ .pReset_N_out ( pResetWires[318] ) , .pReset_W_out ( pResetWires[316] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .Reset_S_in ( p2701 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2891 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1116 ) ,
+ .prog_clk_1_S_in ( p893 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2892 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2893 ) ,
+ .prog_clk_2_N_in ( p2590 ) , .prog_clk_2_E_in ( p550 ) ,
+ .prog_clk_2_S_in ( p2554 ) , .prog_clk_2_W_in ( p1650 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2894 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2895 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2896 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2897 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2898 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[47] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2899 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2900 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2901 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[50] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2902 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_1_N_in ( p1116 ) ,
+ .clk_1_S_in ( p26 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2904 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2905 ) , .clk_2_N_in ( p2244 ) ,
+ .clk_2_E_in ( p118 ) , .clk_2_S_in ( p891 ) , .clk_2_W_in ( p735 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2906 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2907 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2908 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2909 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2910 ) ,
+ .clk_3_E_in ( clk_3_wires[47] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2911 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2912 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2913 ) ,
+ .clk_3_W_out ( clk_3_wires[50] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2914 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+sb_1__1_ sb_3__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2916 } ) ,
+ .chany_top_in ( cby_1__1__31_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__39_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__30_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__28_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__39_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__28_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__28_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__28_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p3266 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2917 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2918 ) ,
+ .pReset_E_in ( pResetWires[368] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2919 ) ,
+ .pReset_N_out ( pResetWires[367] ) , .pReset_W_out ( pResetWires[365] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , .Reset_S_in ( p3217 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2921 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[124] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[54] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2922 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[64] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p3401 ) ,
+ .prog_clk_2_E_in ( p330 ) , .prog_clk_2_S_in ( p689 ) ,
+ .prog_clk_2_W_in ( p723 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2923 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2924 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2925 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2926 ) ,
+ .prog_clk_3_W_in ( p3285 ) , .prog_clk_3_E_in ( p731 ) ,
+ .prog_clk_3_S_in ( p3259 ) , .prog_clk_3_N_in ( p3386 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2927 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2928 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2929 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2930 ) ,
+ .clk_1_N_in ( clk_2_wires[54] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2931 ) ,
+ .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) ,
+ .clk_2_N_in ( p2444 ) , .clk_2_E_in ( p1058 ) , .clk_2_S_in ( p941 ) ,
+ .clk_2_W_in ( p3243 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2932 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2933 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2934 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , .clk_3_W_in ( p2628 ) ,
+ .clk_3_E_in ( p475 ) , .clk_3_S_in ( p120 ) , .clk_3_N_in ( p2259 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2936 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2937 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2938 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+sb_1__1_ sb_3__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2940 } ) ,
+ .chany_top_in ( cby_1__1__32_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__40_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__31_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__29_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__40_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__29_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__29_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__29_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p3073 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2941 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2942 ) ,
+ .pReset_E_in ( pResetWires[417] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2943 ) ,
+ .pReset_N_out ( pResetWires[416] ) , .pReset_W_out ( pResetWires[414] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , .Reset_S_in ( p3567 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2945 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p2400 ) ,
+ .prog_clk_1_S_in ( p790 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2946 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2947 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2948 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[50] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2949 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2950 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2951 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[53] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[51] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2952 ) ,
+ .prog_clk_3_W_in ( p1840 ) , .prog_clk_3_E_in ( p1264 ) ,
+ .prog_clk_3_S_in ( p3560 ) , .prog_clk_3_N_in ( p1714 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2953 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2954 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2955 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2956 ) , .clk_1_N_in ( p2400 ) ,
+ .clk_1_S_in ( p170 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2957 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2958 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2959 ) ,
+ .clk_2_E_in ( clk_2_wires[50] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2960 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2961 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2962 ) ,
+ .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2963 ) , .clk_3_W_in ( p1840 ) ,
+ .clk_3_E_in ( p543 ) , .clk_3_S_in ( p782 ) , .clk_3_N_in ( p2261 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2964 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2965 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2966 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+sb_1__1_ sb_3__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2968 } ) ,
+ .chany_top_in ( cby_1__1__33_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__41_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__32_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__30_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__41_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__30_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__30_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__30_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p1934 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2969 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2970 ) ,
+ .pReset_E_in ( pResetWires[466] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2971 ) ,
+ .pReset_N_out ( pResetWires[465] ) , .pReset_W_out ( pResetWires[463] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , .Reset_S_in ( p3527 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2973 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[130] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2974 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[52] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[71] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3132 ) ,
+ .prog_clk_2_E_in ( p561 ) , .prog_clk_2_S_in ( p106 ) ,
+ .prog_clk_2_W_in ( p276 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2975 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2976 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2977 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2978 ) ,
+ .prog_clk_3_W_in ( p3422 ) , .prog_clk_3_E_in ( p789 ) ,
+ .prog_clk_3_S_in ( p3525 ) , .prog_clk_3_N_in ( p3052 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2979 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2980 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2981 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2982 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2983 ) ,
+ .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) ,
+ .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p1916 ) ,
+ .clk_2_E_in ( p771 ) , .clk_2_S_in ( p897 ) , .clk_2_W_in ( p3384 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2984 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2985 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2986 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , .clk_3_W_in ( p2813 ) ,
+ .clk_3_E_in ( p188 ) , .clk_3_S_in ( p881 ) , .clk_3_N_in ( p1709 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2988 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2989 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2990 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+sb_1__1_ sb_3__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2992 } ) ,
+ .chany_top_in ( cby_1__1__34_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__42_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__33_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__31_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__42_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__31_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__31_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__31_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p3293 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2993 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2994 ) ,
+ .pReset_E_in ( pResetWires[515] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2995 ) ,
+ .pReset_N_out ( pResetWires[514] ) , .pReset_W_out ( pResetWires[512] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , .Reset_S_in ( p3510 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2997 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p2474 ) ,
+ .prog_clk_1_S_in ( p699 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2998 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2999 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3000 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[63] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3001 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3002 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3003 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3004 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[64] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3005 ) ,
+ .prog_clk_3_W_in ( p1950 ) , .prog_clk_3_E_in ( p744 ) ,
+ .prog_clk_3_S_in ( p3498 ) , .prog_clk_3_N_in ( p1292 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3006 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3007 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3008 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_N_in ( p2474 ) ,
+ .clk_1_S_in ( p48 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3010 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3011 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3012 ) ,
+ .clk_2_E_in ( clk_2_wires[63] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3013 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3014 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3015 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3016 ) ,
+ .clk_2_N_out ( clk_2_wires[64] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3017 ) , .clk_3_W_in ( p1950 ) ,
+ .clk_3_E_in ( p383 ) , .clk_3_S_in ( p442 ) , .clk_3_N_in ( p2294 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3018 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3019 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3020 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+sb_1__1_ sb_3__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3022 } ) ,
+ .chany_top_in ( cby_1__1__35_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__43_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__34_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__32_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__43_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__32_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__32_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__32_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2822 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3023 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3024 ) ,
+ .pReset_E_in ( pResetWires[564] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3025 ) ,
+ .pReset_N_out ( pResetWires[563] ) , .pReset_W_out ( pResetWires[561] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , .Reset_S_in ( p3404 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3027 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[136] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3028 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[65] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[78] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p3407 ) ,
+ .prog_clk_2_E_in ( p748 ) , .prog_clk_2_S_in ( p809 ) ,
+ .prog_clk_2_W_in ( p547 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3029 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3030 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3031 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3032 ) ,
+ .prog_clk_3_W_in ( p3112 ) , .prog_clk_3_E_in ( p14 ) ,
+ .prog_clk_3_S_in ( p3388 ) , .prog_clk_3_N_in ( p3380 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3033 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3034 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3035 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3036 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3037 ) ,
+ .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) ,
+ .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p2691 ) ,
+ .clk_2_E_in ( p584 ) , .clk_2_S_in ( p76 ) , .clk_2_W_in ( p3032 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3038 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3039 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3040 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3041 ) , .clk_3_W_in ( p2818 ) ,
+ .clk_3_E_in ( p520 ) , .clk_3_S_in ( p1031 ) , .clk_3_N_in ( p2517 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3042 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3043 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3044 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+sb_1__1_ sb_4__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3046 } ) ,
+ .chany_top_in ( cby_1__1__37_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__44_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__36_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__33_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__44_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__33_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__33_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__33_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p3277 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3047 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3048 ) ,
+ .pReset_E_in ( pResetWires[78] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3049 ) ,
+ .pReset_N_out ( pResetWires[77] ) , .pReset_W_out ( pResetWires[75] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , .Reset_S_in ( p3400 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3051 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p1485 ) ,
+ .prog_clk_1_S_in ( p721 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3052 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3053 ) ,
+ .prog_clk_2_N_in ( p3116 ) , .prog_clk_2_E_in ( p91 ) ,
+ .prog_clk_2_S_in ( p1105 ) , .prog_clk_2_W_in ( p769 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3054 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3055 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3056 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3057 ) ,
+ .prog_clk_3_W_in ( p3557 ) , .prog_clk_3_E_in ( p459 ) ,
+ .prog_clk_3_S_in ( p3373 ) , .prog_clk_3_N_in ( p3061 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3058 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3059 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3060 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_1_N_in ( p1485 ) ,
+ .clk_1_S_in ( p98 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3062 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , .clk_2_N_in ( p3423 ) ,
+ .clk_2_E_in ( p498 ) , .clk_2_S_in ( p264 ) , .clk_2_W_in ( p3554 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3064 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3065 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3066 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , .clk_3_W_in ( p2232 ) ,
+ .clk_3_E_in ( p1065 ) , .clk_3_S_in ( p804 ) , .clk_3_N_in ( p3393 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3068 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3069 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3070 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+sb_1__1_ sb_4__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3072 } ) ,
+ .chany_top_in ( cby_1__1__38_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__45_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__37_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__34_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__45_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__34_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__34_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__34_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p3105 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3073 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3074 ) ,
+ .pReset_E_in ( pResetWires[127] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3075 ) ,
+ .pReset_N_out ( pResetWires[126] ) , .pReset_W_out ( pResetWires[124] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , .Reset_S_in ( p3456 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3077 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p2061 ) ,
+ .prog_clk_1_S_in ( p111 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3078 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3079 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[25] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3080 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3081 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3082 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[27] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3083 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3084 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p1906 ) ,
+ .prog_clk_3_E_in ( p1646 ) , .prog_clk_3_S_in ( p3433 ) ,
+ .prog_clk_3_N_in ( p65 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3085 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3086 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3087 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , .clk_1_N_in ( p2061 ) ,
+ .clk_1_S_in ( p907 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3089 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3090 ) ,
+ .clk_2_N_in ( clk_3_wires[25] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3091 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3092 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3093 ) ,
+ .clk_2_W_out ( clk_2_wires[27] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3094 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3095 ) ,
+ .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p1906 ) ,
+ .clk_3_E_in ( p957 ) , .clk_3_S_in ( p1062 ) , .clk_3_N_in ( p1994 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3096 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3097 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3098 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+sb_1__1_ sb_4__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3100 } ) ,
+ .chany_top_in ( cby_1__1__39_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__46_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__38_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__35_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__46_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__35_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__35_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__35_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2130 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3101 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3102 ) ,
+ .pReset_E_in ( pResetWires[176] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3103 ) ,
+ .pReset_N_out ( pResetWires[175] ) , .pReset_W_out ( pResetWires[173] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , .Reset_S_in ( p3099 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3105 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1491 ) ,
+ .prog_clk_1_S_in ( p271 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3106 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3107 ) ,
+ .prog_clk_2_N_in ( p2382 ) , .prog_clk_2_E_in ( p466 ) ,
+ .prog_clk_2_S_in ( p3023 ) , .prog_clk_2_W_in ( p424 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3108 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3109 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3110 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3111 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3112 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3113 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3114 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[21] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3115 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3116 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3117 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1491 ) ,
+ .clk_1_S_in ( p815 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3118 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3119 ) , .clk_2_N_in ( p2382 ) ,
+ .clk_2_E_in ( p5 ) , .clk_2_S_in ( p2070 ) , .clk_2_W_in ( p1075 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3120 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3121 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3122 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3123 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3124 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3125 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3126 ) ,
+ .clk_3_N_in ( clk_3_wires[21] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3127 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3128 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3129 ) ,
+ .clk_3_S_out ( clk_3_wires[24] ) ) ;
+sb_1__1_ sb_4__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3130 } ) ,
+ .chany_top_in ( cby_1__1__40_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__47_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__39_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__36_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__47_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__36_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__36_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__36_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p2440 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3131 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3132 ) ,
+ .pReset_E_in ( pResetWires[225] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3133 ) ,
+ .pReset_N_out ( pResetWires[224] ) , .pReset_W_out ( pResetWires[222] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , .Reset_S_in ( p2440 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3135 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p1420 ) ,
+ .prog_clk_1_S_in ( p2292 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3136 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3137 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[15] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3138 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3139 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3140 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[36] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3141 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3142 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[34] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3143 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3144 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3145 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[15] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3146 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3147 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3148 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p1420 ) ,
+ .clk_1_S_in ( p685 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3149 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3150 ) ,
+ .clk_2_N_in ( clk_3_wires[15] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3151 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3152 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3153 ) ,
+ .clk_2_W_out ( clk_2_wires[36] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3154 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3155 ) ,
+ .clk_2_E_out ( clk_2_wires[34] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3156 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3157 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3158 ) ,
+ .clk_3_N_in ( clk_3_wires[15] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3159 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3160 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3161 ) ,
+ .clk_3_S_out ( clk_3_wires[20] ) ) ;
+sb_1__1_ sb_4__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3162 } ) ,
+ .chany_top_in ( cby_1__1__41_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__48_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__40_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__37_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__48_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__37_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__37_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__37_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p2193 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3163 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3164 ) ,
+ .pReset_E_in ( pResetWires[274] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3165 ) ,
+ .pReset_N_out ( pResetWires[273] ) , .pReset_W_out ( pResetWires[271] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .Reset_S_in ( p2193 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3167 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1141 ) ,
+ .prog_clk_1_S_in ( p486 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3168 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3169 ) ,
+ .prog_clk_2_N_in ( p1526 ) , .prog_clk_2_E_in ( p1022 ) ,
+ .prog_clk_2_S_in ( p1966 ) , .prog_clk_2_W_in ( p460 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3170 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3171 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3172 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3173 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3174 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3175 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3176 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[11] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3177 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3178 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3179 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1141 ) ,
+ .clk_1_S_in ( p123 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3180 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_2_N_in ( p1526 ) ,
+ .clk_2_E_in ( p502 ) , .clk_2_S_in ( p1017 ) , .clk_2_W_in ( p135 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3182 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3183 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3184 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3185 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3186 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3187 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3188 ) ,
+ .clk_3_N_in ( clk_3_wires[11] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3189 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3190 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3191 ) ,
+ .clk_3_S_out ( clk_3_wires[14] ) ) ;
+sb_1__1_ sb_4__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3192 } ) ,
+ .chany_top_in ( cby_1__1__42_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__49_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__41_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__38_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__49_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__38_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__38_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__38_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p3131 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3193 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3194 ) ,
+ .pReset_E_in ( pResetWires[323] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3195 ) ,
+ .pReset_N_out ( pResetWires[322] ) , .pReset_W_out ( pResetWires[320] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , .Reset_S_in ( p3131 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3197 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1236 ) ,
+ .prog_clk_1_S_in ( p767 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3198 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3199 ) ,
+ .prog_clk_2_N_in ( p2647 ) , .prog_clk_2_E_in ( p456 ) ,
+ .prog_clk_2_S_in ( p3048 ) , .prog_clk_2_W_in ( p1657 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3200 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3201 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3202 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3203 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3204 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[7] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3205 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3206 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3207 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[46] ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[8] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1236 ) ,
+ .clk_1_S_in ( p288 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3208 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3209 ) , .clk_2_N_in ( p1895 ) ,
+ .clk_2_E_in ( p85 ) , .clk_2_S_in ( p1358 ) , .clk_2_W_in ( p805 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3210 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3211 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3212 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3213 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3214 ) ,
+ .clk_3_E_in ( clk_3_wires[7] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3215 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3216 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3217 ) ,
+ .clk_3_W_out ( clk_3_wires[46] ) , .clk_3_N_out ( clk_3_wires[8] ) ,
+ .clk_3_S_out ( clk_3_wires[10] ) ) ;
+sb_1__1_ sb_4__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3218 } ) ,
+ .chany_top_in ( cby_1__1__43_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__50_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__42_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__39_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__50_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__39_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__39_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__39_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2150 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3219 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3220 ) ,
+ .pReset_E_in ( pResetWires[372] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3221 ) ,
+ .pReset_N_out ( pResetWires[371] ) , .pReset_W_out ( pResetWires[369] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , .Reset_S_in ( p2832 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3223 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1448 ) ,
+ .prog_clk_1_S_in ( p963 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3224 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3225 ) ,
+ .prog_clk_2_N_in ( p2412 ) , .prog_clk_2_E_in ( p820 ) ,
+ .prog_clk_2_S_in ( p2733 ) , .prog_clk_2_W_in ( p635 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3226 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3227 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3228 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3229 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3230 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3231 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[9] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3232 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3233 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3234 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[12] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_1_N_in ( p1448 ) ,
+ .clk_1_S_in ( p472 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3236 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , .clk_2_N_in ( p2412 ) ,
+ .clk_2_E_in ( p39 ) , .clk_2_S_in ( p1387 ) , .clk_2_W_in ( p400 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3238 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3239 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3240 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3241 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3242 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3243 ) ,
+ .clk_3_S_in ( clk_3_wires[9] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3244 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3245 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3246 ) ,
+ .clk_3_N_out ( clk_3_wires[12] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+sb_1__1_ sb_4__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3248 } ) ,
+ .chany_top_in ( cby_1__1__44_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__51_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__43_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__40_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__51_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__40_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__40_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__40_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1825 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3249 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3250 ) ,
+ .pReset_E_in ( pResetWires[421] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3251 ) ,
+ .pReset_N_out ( pResetWires[420] ) , .pReset_W_out ( pResetWires[418] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , .Reset_S_in ( p1825 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3253 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1214 ) ,
+ .prog_clk_1_S_in ( p1623 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3254 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3255 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3256 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3257 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[13] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3258 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[49] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3259 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3260 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[47] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3261 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3262 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[13] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3263 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3264 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3265 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[18] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3266 ) , .clk_1_N_in ( p1214 ) ,
+ .clk_1_S_in ( p1047 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3267 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3268 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3269 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3270 ) ,
+ .clk_2_S_in ( clk_3_wires[13] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3271 ) ,
+ .clk_2_W_out ( clk_2_wires[49] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3272 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3273 ) ,
+ .clk_2_E_out ( clk_2_wires[47] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3274 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3275 ) ,
+ .clk_3_S_in ( clk_3_wires[13] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3276 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3277 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3278 ) ,
+ .clk_3_N_out ( clk_3_wires[18] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+sb_1__1_ sb_4__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3280 } ) ,
+ .chany_top_in ( cby_1__1__45_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__52_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__44_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__41_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__52_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__41_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__41_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__41_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p3288 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3281 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3282 ) ,
+ .pReset_E_in ( pResetWires[470] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3283 ) ,
+ .pReset_N_out ( pResetWires[469] ) , .pReset_W_out ( pResetWires[467] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , .Reset_S_in ( p3348 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3285 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1439 ) ,
+ .prog_clk_1_S_in ( p1081 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3286 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3287 ) ,
+ .prog_clk_2_N_in ( p2436 ) , .prog_clk_2_E_in ( p882 ) ,
+ .prog_clk_2_S_in ( p3315 ) , .prog_clk_2_W_in ( p268 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3288 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3289 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3290 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3291 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3292 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3293 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[19] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3294 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3295 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3296 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[22] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_1_N_in ( p1439 ) ,
+ .clk_1_S_in ( p384 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3298 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3299 ) , .clk_2_N_in ( p2124 ) ,
+ .clk_2_E_in ( p408 ) , .clk_2_S_in ( p1282 ) , .clk_2_W_in ( p836 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3300 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3301 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3302 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3303 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3304 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3305 ) ,
+ .clk_3_S_in ( clk_3_wires[19] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3306 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3307 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3308 ) ,
+ .clk_3_N_out ( clk_3_wires[22] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+sb_1__1_ sb_4__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3310 } ) ,
+ .chany_top_in ( cby_1__1__46_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__53_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__45_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__42_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__53_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__42_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__42_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__42_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p1948 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3311 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3312 ) ,
+ .pReset_E_in ( pResetWires[519] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3313 ) ,
+ .pReset_N_out ( pResetWires[518] ) , .pReset_W_out ( pResetWires[516] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , .Reset_S_in ( p3515 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3315 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p1591 ) ,
+ .prog_clk_1_S_in ( p108 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3316 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3317 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3318 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3319 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[23] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3320 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[62] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3321 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3322 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p1446 ) ,
+ .prog_clk_3_E_in ( p1309 ) , .prog_clk_3_S_in ( p3497 ) ,
+ .prog_clk_3_N_in ( p621 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3323 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3324 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3325 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3326 ) , .clk_1_N_in ( p1591 ) ,
+ .clk_1_S_in ( p415 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3328 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3329 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3330 ) ,
+ .clk_2_S_in ( clk_3_wires[23] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3331 ) ,
+ .clk_2_W_out ( clk_2_wires[62] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3332 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3333 ) ,
+ .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p1446 ) ,
+ .clk_3_E_in ( p187 ) , .clk_3_S_in ( p1649 ) , .clk_3_N_in ( p1355 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3334 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3335 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3336 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+sb_1__1_ sb_4__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3338 } ) ,
+ .chany_top_in ( cby_1__1__47_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__54_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__46_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__43_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__54_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__43_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__43_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__43_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p2441 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3339 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3340 ) ,
+ .pReset_E_in ( pResetWires[568] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3341 ) ,
+ .pReset_N_out ( pResetWires[567] ) , .pReset_W_out ( pResetWires[565] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , .Reset_S_in ( p3273 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3343 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p1849 ) ,
+ .prog_clk_1_S_in ( p529 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3344 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3345 ) ,
+ .prog_clk_2_N_in ( p3415 ) , .prog_clk_2_E_in ( p589 ) ,
+ .prog_clk_2_S_in ( p250 ) , .prog_clk_2_W_in ( p215 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3346 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3347 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3348 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3349 ) ,
+ .prog_clk_3_W_in ( p3176 ) , .prog_clk_3_E_in ( p506 ) ,
+ .prog_clk_3_S_in ( p3242 ) , .prog_clk_3_N_in ( p3383 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3350 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3351 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3352 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_1_N_in ( p1849 ) ,
+ .clk_1_S_in ( p1197 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3354 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_2_N_in ( p3102 ) ,
+ .clk_2_E_in ( p19 ) , .clk_2_S_in ( p1232 ) , .clk_2_W_in ( p3151 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3356 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3357 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3358 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3359 ) , .clk_3_W_in ( p2816 ) ,
+ .clk_3_E_in ( p892 ) , .clk_3_S_in ( p588 ) , .clk_3_N_in ( p3063 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3360 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3361 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3362 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+sb_1__1_ sb_5__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3364 } ) ,
+ .chany_top_in ( cby_1__1__49_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__55_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__48_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__44_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__55_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__44_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__44_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__44_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p1549 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3365 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3366 ) ,
+ .pReset_E_in ( pResetWires[82] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3367 ) ,
+ .pReset_N_out ( pResetWires[81] ) , .pReset_W_out ( pResetWires[79] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , .Reset_S_in ( p2978 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3369 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[182] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[32] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3370 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[85] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p2424 ) ,
+ .prog_clk_2_E_in ( p272 ) , .prog_clk_2_S_in ( p654 ) ,
+ .prog_clk_2_W_in ( p574 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3371 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3372 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3373 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3374 ) ,
+ .prog_clk_3_W_in ( p3580 ) , .prog_clk_3_E_in ( p277 ) ,
+ .prog_clk_3_S_in ( p2886 ) , .prog_clk_3_N_in ( p2319 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3375 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3376 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3377 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3378 ) ,
+ .clk_1_N_in ( clk_2_wires[32] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3379 ) ,
+ .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) ,
+ .clk_2_N_in ( p3454 ) , .clk_2_E_in ( p850 ) , .clk_2_S_in ( p1124 ) ,
+ .clk_2_W_in ( p3578 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3380 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3381 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3382 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3383 ) , .clk_3_W_in ( p2982 ) ,
+ .clk_3_E_in ( p527 ) , .clk_3_S_in ( p7 ) , .clk_3_N_in ( p3441 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3384 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3385 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3386 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+sb_1__1_ sb_5__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3388 } ) ,
+ .chany_top_in ( cby_1__1__50_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__56_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__49_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__45_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__56_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__45_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__45_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__45_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p3341 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3389 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3390 ) ,
+ .pReset_E_in ( pResetWires[131] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3391 ) ,
+ .pReset_N_out ( pResetWires[130] ) , .pReset_W_out ( pResetWires[128] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , .Reset_S_in ( p2853 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3393 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p2386 ) ,
+ .prog_clk_1_S_in ( p372 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3394 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3395 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3396 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3397 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3398 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[26] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3399 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[31] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3400 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3401 ) ,
+ .prog_clk_3_W_in ( p2103 ) , .prog_clk_3_E_in ( p158 ) ,
+ .prog_clk_3_S_in ( p3319 ) , .prog_clk_3_N_in ( p322 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3402 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3403 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3404 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3405 ) , .clk_1_N_in ( p2386 ) ,
+ .clk_1_S_in ( p822 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3406 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3407 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3408 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3409 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3410 ) ,
+ .clk_2_W_in ( clk_2_wires[26] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3411 ) ,
+ .clk_2_S_out ( clk_2_wires[31] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3412 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3413 ) , .clk_3_W_in ( p2103 ) ,
+ .clk_3_E_in ( p467 ) , .clk_3_S_in ( p86 ) , .clk_3_N_in ( p2291 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3414 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3415 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3416 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+sb_1__1_ sb_5__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3418 } ) ,
+ .chany_top_in ( cby_1__1__51_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__57_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__50_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__46_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__57_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__46_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__46_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__46_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p1209 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3419 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3420 ) ,
+ .pReset_E_in ( pResetWires[180] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3421 ) ,
+ .pReset_N_out ( pResetWires[179] ) , .pReset_W_out ( pResetWires[177] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3422 ) , .Reset_S_in ( p3294 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3423 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[188] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[45] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3424 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[92] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3577 ) ,
+ .prog_clk_2_E_in ( p333 ) , .prog_clk_2_S_in ( p1144 ) ,
+ .prog_clk_2_W_in ( p842 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3425 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3426 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3427 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3428 ) ,
+ .prog_clk_3_W_in ( p2789 ) , .prog_clk_3_E_in ( p962 ) ,
+ .prog_clk_3_S_in ( p3254 ) , .prog_clk_3_N_in ( p3574 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3429 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3430 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3431 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3432 ) ,
+ .clk_1_N_in ( clk_2_wires[45] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3433 ) ,
+ .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) ,
+ .clk_2_N_in ( p3130 ) , .clk_2_E_in ( p1063 ) , .clk_2_S_in ( p29 ) ,
+ .clk_2_W_in ( p2713 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3434 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3435 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3436 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3437 ) , .clk_3_W_in ( p2478 ) ,
+ .clk_3_E_in ( p281 ) , .clk_3_S_in ( p1104 ) , .clk_3_N_in ( p3053 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3438 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3439 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3440 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+sb_1__1_ sb_5__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3442 } ) ,
+ .chany_top_in ( cby_1__1__52_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__58_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__51_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__47_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__58_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__47_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__47_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__47_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2962 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3443 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3444 ) ,
+ .pReset_E_in ( pResetWires[229] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3445 ) ,
+ .pReset_N_out ( pResetWires[228] ) , .pReset_W_out ( pResetWires[226] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , .Reset_S_in ( p3092 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3447 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p1782 ) ,
+ .prog_clk_1_S_in ( p369 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3448 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3449 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3450 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3451 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3452 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[35] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3453 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[44] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[42] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3454 ) ,
+ .prog_clk_3_W_in ( p1917 ) , .prog_clk_3_E_in ( p860 ) ,
+ .prog_clk_3_S_in ( p3045 ) , .prog_clk_3_N_in ( p2290 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3455 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3456 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3457 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , .clk_1_N_in ( p1782 ) ,
+ .clk_1_S_in ( p1173 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3459 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3460 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3461 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3462 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3463 ) ,
+ .clk_2_W_in ( clk_2_wires[35] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3464 ) ,
+ .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , .clk_3_W_in ( p1917 ) ,
+ .clk_3_E_in ( p11 ) , .clk_3_S_in ( p849 ) , .clk_3_N_in ( p1674 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3466 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3467 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3468 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+sb_1__1_ sb_5__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3470 } ) ,
+ .chany_top_in ( cby_1__1__53_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__59_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__52_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__48_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__59_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__48_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__48_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__48_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2454 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3471 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3472 ) ,
+ .pReset_E_in ( pResetWires[278] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3473 ) ,
+ .pReset_N_out ( pResetWires[277] ) , .pReset_W_out ( pResetWires[275] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3474 ) , .Reset_S_in ( p3017 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3475 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[194] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3476 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[43] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[99] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p3455 ) ,
+ .prog_clk_2_E_in ( p193 ) , .prog_clk_2_S_in ( p971 ) ,
+ .prog_clk_2_W_in ( p174 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3477 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3478 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3479 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3480 ) ,
+ .prog_clk_3_W_in ( p1882 ) , .prog_clk_3_E_in ( p865 ) ,
+ .prog_clk_3_S_in ( p2908 ) , .prog_clk_3_N_in ( p3431 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3481 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3482 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3483 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3484 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3485 ) ,
+ .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) ,
+ .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p3358 ) ,
+ .clk_2_E_in ( p646 ) , .clk_2_S_in ( p868 ) , .clk_2_W_in ( p1625 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3486 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3487 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3488 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_3_W_in ( p1908 ) ,
+ .clk_3_E_in ( p514 ) , .clk_3_S_in ( p198 ) , .clk_3_N_in ( p3322 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3490 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3491 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3492 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+sb_1__1_ sb_5__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3494 } ) ,
+ .chany_top_in ( cby_1__1__54_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__60_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__53_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__49_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__60_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__49_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__49_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__49_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p2843 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3495 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3496 ) ,
+ .pReset_E_in ( pResetWires[327] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3497 ) ,
+ .pReset_N_out ( pResetWires[326] ) , .pReset_W_out ( pResetWires[324] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , .Reset_S_in ( p3188 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3499 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p1126 ) ,
+ .prog_clk_1_S_in ( p104 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3500 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3501 ) ,
+ .prog_clk_2_N_in ( p2479 ) , .prog_clk_2_E_in ( p826 ) ,
+ .prog_clk_2_S_in ( p3171 ) , .prog_clk_2_W_in ( p684 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3502 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3503 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3504 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3505 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3506 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[3] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3507 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3508 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3509 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[6] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3510 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_1_N_in ( p1126 ) ,
+ .clk_1_S_in ( p864 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3512 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , .clk_2_N_in ( p2032 ) ,
+ .clk_2_E_in ( p177 ) , .clk_2_S_in ( p972 ) , .clk_2_W_in ( p55 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3514 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3515 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3516 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3517 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3518 ) ,
+ .clk_3_E_in ( clk_3_wires[3] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3519 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3520 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3521 ) ,
+ .clk_3_W_out ( clk_3_wires[6] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3522 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+sb_1__1_ sb_5__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3524 } ) ,
+ .chany_top_in ( cby_1__1__55_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__61_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__54_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__50_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__61_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__50_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__50_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__50_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p3220 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3525 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3526 ) ,
+ .pReset_E_in ( pResetWires[376] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3527 ) ,
+ .pReset_N_out ( pResetWires[375] ) , .pReset_W_out ( pResetWires[373] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , .Reset_S_in ( p2819 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3529 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[200] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[58] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3530 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[106] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p3564 ) ,
+ .prog_clk_2_E_in ( p157 ) , .prog_clk_2_S_in ( p368 ) ,
+ .prog_clk_2_W_in ( p772 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3531 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3532 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3533 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3534 ) ,
+ .prog_clk_3_W_in ( p3452 ) , .prog_clk_3_E_in ( p477 ) ,
+ .prog_clk_3_S_in ( p3168 ) , .prog_clk_3_N_in ( p3563 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3535 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3536 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3537 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3538 ) ,
+ .clk_1_N_in ( clk_2_wires[58] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3539 ) ,
+ .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) ,
+ .clk_2_N_in ( p3103 ) , .clk_2_E_in ( p948 ) , .clk_2_S_in ( p1072 ) ,
+ .clk_2_W_in ( p3432 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3540 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3541 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3542 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3543 ) , .clk_3_W_in ( p2591 ) ,
+ .clk_3_E_in ( p566 ) , .clk_3_S_in ( p906 ) , .clk_3_N_in ( p3028 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3544 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3545 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3546 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
+sb_1__1_ sb_5__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3548 } ) ,
+ .chany_top_in ( cby_1__1__56_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__62_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__55_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__51_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__62_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__51_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__51_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__51_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p3071 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3549 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3550 ) ,
+ .pReset_E_in ( pResetWires[425] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3551 ) ,
+ .pReset_N_out ( pResetWires[424] ) , .pReset_W_out ( pResetWires[422] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , .Reset_S_in ( p3420 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3553 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p1826 ) ,
+ .prog_clk_1_S_in ( p32 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3554 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3555 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3556 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3557 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3558 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[48] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3559 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[57] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[55] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3560 ) ,
+ .prog_clk_3_W_in ( p1787 ) , .prog_clk_3_E_in ( p781 ) ,
+ .prog_clk_3_S_in ( p3379 ) , .prog_clk_3_N_in ( p1637 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3561 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3562 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3563 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3564 ) , .clk_1_N_in ( p1826 ) ,
+ .clk_1_S_in ( p884 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3565 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3566 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3567 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3568 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3569 ) ,
+ .clk_2_W_in ( clk_2_wires[48] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3570 ) ,
+ .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , .clk_3_W_in ( p1787 ) ,
+ .clk_3_E_in ( p302 ) , .clk_3_S_in ( p396 ) , .clk_3_N_in ( p1707 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3572 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3573 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3574 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
+sb_1__1_ sb_5__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3576 } ) ,
+ .chany_top_in ( cby_1__1__57_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__63_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__56_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__52_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__63_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__52_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__52_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__52_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p2485 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3577 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3578 ) ,
+ .pReset_E_in ( pResetWires[474] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3579 ) ,
+ .pReset_N_out ( pResetWires[473] ) , .pReset_W_out ( pResetWires[471] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3580 ) , .Reset_S_in ( p3418 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3581 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[206] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3582 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[56] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[113] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3343 ) ,
+ .prog_clk_2_E_in ( p638 ) , .prog_clk_2_S_in ( p83 ) ,
+ .prog_clk_2_W_in ( p94 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3583 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3584 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3585 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3586 ) ,
+ .prog_clk_3_W_in ( p3443 ) , .prog_clk_3_E_in ( p495 ) ,
+ .prog_clk_3_S_in ( p3390 ) , .prog_clk_3_N_in ( p3326 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3587 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3588 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3589 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3590 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3591 ) ,
+ .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) ,
+ .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p3549 ) ,
+ .clk_2_E_in ( p71 ) , .clk_2_S_in ( p987 ) , .clk_2_W_in ( p3434 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3592 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3593 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3594 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3595 ) , .clk_3_W_in ( p3302 ) ,
+ .clk_3_E_in ( p1133 ) , .clk_3_S_in ( p984 ) , .clk_3_N_in ( p3540 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3596 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3597 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3598 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3599 ) ) ;
+sb_1__1_ sb_5__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3600 } ) ,
+ .chany_top_in ( cby_1__1__58_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__64_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__57_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__53_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__64_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__53_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__53_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__53_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p2644 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3601 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3602 ) ,
+ .pReset_E_in ( pResetWires[523] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3603 ) ,
+ .pReset_N_out ( pResetWires[522] ) , .pReset_W_out ( pResetWires[520] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , .Reset_S_in ( p3303 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3605 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p1553 ) ,
+ .prog_clk_1_S_in ( p402 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3606 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3607 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3608 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3609 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3610 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[61] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3611 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3612 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[66] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3613 ) ,
+ .prog_clk_3_W_in ( p1800 ) , .prog_clk_3_E_in ( p345 ) ,
+ .prog_clk_3_S_in ( p3237 ) , .prog_clk_3_N_in ( p1979 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3614 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3615 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3616 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3617 ) , .clk_1_N_in ( p1553 ) ,
+ .clk_1_S_in ( p1120 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3618 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3619 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3620 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3621 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3622 ) ,
+ .clk_2_W_in ( clk_2_wires[61] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3623 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3624 ) ,
+ .clk_2_N_out ( clk_2_wires[66] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3625 ) , .clk_3_W_in ( p1800 ) ,
+ .clk_3_E_in ( p531 ) , .clk_3_S_in ( p127 ) , .clk_3_N_in ( p1316 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3626 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3627 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3628 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3629 ) ) ;
+sb_1__1_ sb_5__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3630 } ) ,
+ .chany_top_in ( cby_1__1__59_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__65_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__58_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__54_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__65_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__54_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__54_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__54_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p2869 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3631 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3632 ) ,
+ .pReset_E_in ( pResetWires[572] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3633 ) ,
+ .pReset_N_out ( pResetWires[571] ) , .pReset_W_out ( pResetWires[569] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3634 ) , .Reset_S_in ( p2820 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3635 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[212] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3636 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[67] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[120] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p3453 ) ,
+ .prog_clk_2_E_in ( p314 ) , .prog_clk_2_S_in ( p1157 ) ,
+ .prog_clk_2_W_in ( p761 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3637 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3638 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3639 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3640 ) ,
+ .prog_clk_3_W_in ( p2407 ) , .prog_clk_3_E_in ( p872 ) ,
+ .prog_clk_3_S_in ( p2715 ) , .prog_clk_3_N_in ( p3425 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3641 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3642 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3643 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3644 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3645 ) ,
+ .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) ,
+ .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3532 ) ,
+ .clk_2_E_in ( p812 ) , .clk_2_S_in ( p315 ) , .clk_2_W_in ( p2287 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3646 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3647 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3648 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3649 ) , .clk_3_W_in ( p2435 ) ,
+ .clk_3_E_in ( p194 ) , .clk_3_S_in ( p950 ) , .clk_3_N_in ( p3523 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3650 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3651 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3652 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3653 ) ) ;
+sb_1__1_ sb_6__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3654 } ) ,
+ .chany_top_in ( cby_1__1__61_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__66_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__60_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__55_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__66_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__55_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__55_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__55_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__55_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__55_ccff_tail ) , .Test_en_S_in ( Test_enWires[2] ) ,
+ .Test_en_N_out ( Test_enWires[3] ) , .pReset_S_in ( pResetWires[2] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3655 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3656 ) ,
+ .pReset_N_out ( pResetWires[85] ) , .pReset_W_out ( pResetWires[83] ) ,
+ .pReset_E_out ( pResetWires[86] ) , .Reset_S_in ( ResetWires[2] ) ,
+ .Reset_N_out ( ResetWires[3] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p644 ) ,
+ .prog_clk_1_S_in ( p192 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3657 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3658 ) ,
+ .prog_clk_2_N_in ( p2639 ) , .prog_clk_2_E_in ( p246 ) ,
+ .prog_clk_2_S_in ( p313 ) , .prog_clk_2_W_in ( p87 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3659 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3660 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3661 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3662 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3663 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3664 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[89] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3665 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3666 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3667 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[92] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_1_N_in ( p644 ) ,
+ .clk_1_S_in ( p766 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3669 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3670 ) , .clk_2_N_in ( p1559 ) ,
+ .clk_2_E_in ( p747 ) , .clk_2_S_in ( p1291 ) , .clk_2_W_in ( p585 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3671 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3672 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3673 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3674 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3675 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3676 ) ,
+ .clk_3_S_in ( clk_3_wires[89] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3677 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3678 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3679 ) ,
+ .clk_3_N_out ( clk_3_wires[92] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3680 ) ) ;
+sb_1__1_ sb_6__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3681 } ) ,
+ .chany_top_in ( cby_1__1__62_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__67_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__61_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__56_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__67_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__56_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__56_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__56_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__56_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__56_ccff_tail ) , .Test_en_S_in ( Test_enWires[4] ) ,
+ .Test_en_N_out ( Test_enWires[5] ) , .pReset_S_in ( pResetWires[4] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3682 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3683 ) ,
+ .pReset_N_out ( pResetWires[134] ) , .pReset_W_out ( pResetWires[132] ) ,
+ .pReset_E_out ( pResetWires[135] ) , .Reset_S_in ( ResetWires[4] ) ,
+ .Reset_N_out ( ResetWires[5] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1409 ) ,
+ .prog_clk_1_S_in ( p82 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3684 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3685 ) ,
+ .prog_clk_2_N_in ( p2117 ) , .prog_clk_2_E_in ( p734 ) ,
+ .prog_clk_2_S_in ( p350 ) , .prog_clk_2_W_in ( p241 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3686 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3687 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3688 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3689 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3690 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3691 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[91] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3692 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3693 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3694 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[94] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_1_N_in ( p1409 ) ,
+ .clk_1_S_in ( p1040 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3696 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3697 ) , .clk_2_N_in ( p2117 ) ,
+ .clk_2_E_in ( p364 ) , .clk_2_S_in ( p1673 ) , .clk_2_W_in ( p548 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3698 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3699 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3700 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3701 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3702 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3703 ) ,
+ .clk_3_S_in ( clk_3_wires[91] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3704 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3705 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3706 ) ,
+ .clk_3_N_out ( clk_3_wires[94] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3707 ) ) ;
+sb_1__1_ sb_6__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3708 } ) ,
+ .chany_top_in ( cby_1__1__63_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__68_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__62_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__57_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__68_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__57_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__57_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__57_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__57_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__57_ccff_tail ) , .Test_en_S_in ( Test_enWires[6] ) ,
+ .Test_en_N_out ( Test_enWires[7] ) , .pReset_S_in ( pResetWires[6] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3709 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3710 ) ,
+ .pReset_N_out ( pResetWires[183] ) , .pReset_W_out ( pResetWires[181] ) ,
+ .pReset_E_out ( pResetWires[184] ) , .Reset_S_in ( ResetWires[6] ) ,
+ .Reset_N_out ( ResetWires[7] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1724 ) ,
+ .prog_clk_1_S_in ( p499 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3711 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3712 ) ,
+ .prog_clk_2_N_in ( p2490 ) , .prog_clk_2_E_in ( p681 ) ,
+ .prog_clk_2_S_in ( p944 ) , .prog_clk_2_W_in ( p269 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3713 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3714 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3715 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3716 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3717 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3718 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[93] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3719 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3720 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3721 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[96] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_1_N_in ( p1724 ) ,
+ .clk_1_S_in ( p377 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3723 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3724 ) , .clk_2_N_in ( p2105 ) ,
+ .clk_2_E_in ( p363 ) , .clk_2_S_in ( p69 ) , .clk_2_W_in ( p280 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3725 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3726 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3727 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3728 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3729 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3730 ) ,
+ .clk_3_S_in ( clk_3_wires[93] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3731 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3732 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3733 ) ,
+ .clk_3_N_out ( clk_3_wires[96] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3734 ) ) ;
+sb_1__1_ sb_6__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3735 } ) ,
+ .chany_top_in ( cby_1__1__64_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__69_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__63_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__58_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__69_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__58_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__58_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__58_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__58_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__58_ccff_tail ) , .Test_en_S_in ( Test_enWires[8] ) ,
+ .Test_en_N_out ( Test_enWires[9] ) , .pReset_S_in ( pResetWires[8] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3736 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3737 ) ,
+ .pReset_N_out ( pResetWires[232] ) , .pReset_W_out ( pResetWires[230] ) ,
+ .pReset_E_out ( pResetWires[233] ) , .Reset_S_in ( ResetWires[8] ) ,
+ .Reset_N_out ( ResetWires[9] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1522 ) ,
+ .prog_clk_1_S_in ( p387 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3738 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3739 ) ,
+ .prog_clk_2_N_in ( p2481 ) , .prog_clk_2_E_in ( p504 ) ,
+ .prog_clk_2_S_in ( p139 ) , .prog_clk_2_W_in ( p674 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3740 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3741 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3742 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3743 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3744 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3745 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[95] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3746 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3747 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3748 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[98] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_1_N_in ( p1522 ) ,
+ .clk_1_S_in ( p716 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3750 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3751 ) , .clk_2_N_in ( p2392 ) ,
+ .clk_2_E_in ( p871 ) , .clk_2_S_in ( p1642 ) , .clk_2_W_in ( p320 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3752 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3753 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3754 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3755 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3756 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3757 ) ,
+ .clk_3_S_in ( clk_3_wires[95] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3758 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3759 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3760 ) ,
+ .clk_3_N_out ( clk_3_wires[98] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3761 ) ) ;
+sb_1__1_ sb_6__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3762 } ) ,
+ .chany_top_in ( cby_1__1__65_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__70_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__64_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__59_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__70_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__59_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__59_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__59_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__59_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__59_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[10] ) , .Test_en_N_out ( Test_enWires[11] ) ,
+ .pReset_S_in ( pResetWires[10] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3763 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3764 ) ,
+ .pReset_N_out ( pResetWires[281] ) , .pReset_W_out ( pResetWires[279] ) ,
+ .pReset_E_out ( pResetWires[282] ) , .Reset_S_in ( ResetWires[10] ) ,
+ .Reset_N_out ( ResetWires[11] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p1245 ) ,
+ .prog_clk_1_S_in ( p1159 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3765 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3766 ) ,
+ .prog_clk_2_N_in ( p2079 ) , .prog_clk_2_E_in ( p168 ) ,
+ .prog_clk_2_S_in ( p1290 ) , .prog_clk_2_W_in ( p600 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3767 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3768 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3769 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3770 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3771 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3772 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[97] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3773 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3774 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3775 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[100] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_1_N_in ( p1245 ) ,
+ .clk_1_S_in ( p45 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3777 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3778 ) , .clk_2_N_in ( p2118 ) ,
+ .clk_2_E_in ( p942 ) , .clk_2_S_in ( p1374 ) , .clk_2_W_in ( p212 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3779 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3780 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3781 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3782 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3783 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3784 ) ,
+ .clk_3_S_in ( clk_3_wires[97] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3785 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3786 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3787 ) ,
+ .clk_3_N_out ( clk_3_wires[100] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3788 ) ) ;
+sb_1__1_ sb_6__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3789 } ) ,
+ .chany_top_in ( cby_1__1__66_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__71_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__65_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__60_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__71_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__60_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__60_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__60_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__60_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__60_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[12] ) , .Test_en_N_out ( Test_enWires[13] ) ,
+ .pReset_S_in ( pResetWires[12] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3790 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3791 ) ,
+ .pReset_N_out ( pResetWires[330] ) , .pReset_W_out ( pResetWires[328] ) ,
+ .pReset_E_out ( pResetWires[331] ) , .Reset_S_in ( ResetWires[12] ) ,
+ .Reset_N_out ( ResetWires[13] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p2080 ) ,
+ .prog_clk_1_S_in ( p404 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3792 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3793 ) ,
+ .prog_clk_2_N_in ( p2212 ) , .prog_clk_2_E_in ( p175 ) ,
+ .prog_clk_2_S_in ( p90 ) , .prog_clk_2_W_in ( p1644 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3794 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3795 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3796 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3797 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3798 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3799 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[99] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3800 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[0] ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[2] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3801 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_1_N_in ( p2080 ) ,
+ .clk_1_S_in ( p927 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3803 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3804 ) , .clk_2_N_in ( p2212 ) ,
+ .clk_2_E_in ( p876 ) , .clk_2_S_in ( p1288 ) , .clk_2_W_in ( p231 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3805 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3806 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3807 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3808 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3809 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3810 ) ,
+ .clk_3_S_in ( clk_3_wires[99] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3811 ) ,
+ .clk_3_E_out ( clk_3_wires[0] ) , .clk_3_W_out ( clk_3_wires[2] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3812 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3813 ) ) ;
+sb_1__1_ sb_6__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3814 } ) ,
+ .chany_top_in ( cby_1__1__67_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__72_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__66_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__61_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__72_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__61_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__61_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__61_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__61_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__61_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[14] ) , .Test_en_N_out ( Test_enWires[15] ) ,
+ .pReset_S_in ( pResetWires[14] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3815 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3816 ) ,
+ .pReset_N_out ( pResetWires[379] ) , .pReset_W_out ( pResetWires[377] ) ,
+ .pReset_E_out ( pResetWires[380] ) , .Reset_S_in ( ResetWires[14] ) ,
+ .Reset_N_out ( ResetWires[15] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p1843 ) ,
+ .prog_clk_1_S_in ( p651 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3817 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3818 ) ,
+ .prog_clk_2_N_in ( p3543 ) , .prog_clk_2_E_in ( p538 ) ,
+ .prog_clk_2_S_in ( p1069 ) , .prog_clk_2_W_in ( p706 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3819 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3820 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3821 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3822 ) ,
+ .prog_clk_3_W_in ( p2470 ) , .prog_clk_3_E_in ( p390 ) ,
+ .prog_clk_3_S_in ( p428 ) , .prog_clk_3_N_in ( p3542 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3823 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3824 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3825 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_1_N_in ( p1843 ) ,
+ .clk_1_S_in ( p208 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3827 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3828 ) , .clk_2_N_in ( p3126 ) ,
+ .clk_2_E_in ( p8 ) , .clk_2_S_in ( p946 ) , .clk_2_W_in ( p2720 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3829 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3830 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3831 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3832 ) , .clk_3_W_in ( p2777 ) ,
+ .clk_3_E_in ( p1114 ) , .clk_3_S_in ( p216 ) , .clk_3_N_in ( p3039 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3833 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3834 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3835 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3836 ) ) ;
+sb_1__1_ sb_6__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3837 } ) ,
+ .chany_top_in ( cby_1__1__68_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__73_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__67_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__62_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__73_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__62_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__62_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__62_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__62_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__62_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[16] ) , .Test_en_N_out ( Test_enWires[17] ) ,
+ .pReset_S_in ( pResetWires[16] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3838 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3839 ) ,
+ .pReset_N_out ( pResetWires[428] ) , .pReset_W_out ( pResetWires[426] ) ,
+ .pReset_E_out ( pResetWires[429] ) , .Reset_S_in ( ResetWires[16] ) ,
+ .Reset_N_out ( ResetWires[17] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p1817 ) ,
+ .prog_clk_1_S_in ( p20 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3840 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3841 ) ,
+ .prog_clk_2_N_in ( p3340 ) , .prog_clk_2_E_in ( p926 ) ,
+ .prog_clk_2_S_in ( p492 ) , .prog_clk_2_W_in ( p912 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3842 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3843 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3844 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3845 ) ,
+ .prog_clk_3_W_in ( p2942 ) , .prog_clk_3_E_in ( p610 ) ,
+ .prog_clk_3_S_in ( p841 ) , .prog_clk_3_N_in ( p3323 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3846 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3847 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3848 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_1_N_in ( p1817 ) ,
+ .clk_1_S_in ( p615 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3850 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , .clk_2_N_in ( p3514 ) ,
+ .clk_2_E_in ( p282 ) , .clk_2_S_in ( p705 ) , .clk_2_W_in ( p2895 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3852 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3853 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3854 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3855 ) , .clk_3_W_in ( p2845 ) ,
+ .clk_3_E_in ( p694 ) , .clk_3_S_in ( p708 ) , .clk_3_N_in ( p3502 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3856 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3857 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3858 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3859 ) ) ;
+sb_1__1_ sb_6__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3860 } ) ,
+ .chany_top_in ( cby_1__1__69_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__74_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__68_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__63_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__74_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__63_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__63_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__63_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__63_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__63_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[18] ) , .Test_en_N_out ( Test_enWires[19] ) ,
+ .pReset_S_in ( pResetWires[18] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3861 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3862 ) ,
+ .pReset_N_out ( pResetWires[477] ) , .pReset_W_out ( pResetWires[475] ) ,
+ .pReset_E_out ( pResetWires[478] ) , .Reset_S_in ( ResetWires[18] ) ,
+ .Reset_N_out ( ResetWires[19] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p1207 ) ,
+ .prog_clk_1_S_in ( p334 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3863 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3864 ) ,
+ .prog_clk_2_N_in ( p3445 ) , .prog_clk_2_E_in ( p244 ) ,
+ .prog_clk_2_S_in ( p1034 ) , .prog_clk_2_W_in ( p242 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3865 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3866 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3867 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3868 ) ,
+ .prog_clk_3_W_in ( p3267 ) , .prog_clk_3_E_in ( p839 ) ,
+ .prog_clk_3_S_in ( p639 ) , .prog_clk_3_N_in ( p3438 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3869 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3870 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3871 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_1_N_in ( p1207 ) ,
+ .clk_1_S_in ( p827 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3873 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .clk_2_N_in ( p3085 ) ,
+ .clk_2_E_in ( p427 ) , .clk_2_S_in ( p575 ) , .clk_2_W_in ( p3251 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3875 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3876 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3877 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3878 ) , .clk_3_W_in ( p2967 ) ,
+ .clk_3_E_in ( p797 ) , .clk_3_S_in ( p458 ) , .clk_3_N_in ( p3064 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3879 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3880 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3881 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3882 ) ) ;
+sb_1__1_ sb_6__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3883 } ) ,
+ .chany_top_in ( cby_1__1__70_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__75_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__69_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__64_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__75_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__64_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__64_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__64_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__64_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__64_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[20] ) , .Test_en_N_out ( Test_enWires[21] ) ,
+ .pReset_S_in ( pResetWires[20] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3884 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3885 ) ,
+ .pReset_N_out ( pResetWires[526] ) , .pReset_W_out ( pResetWires[524] ) ,
+ .pReset_E_out ( pResetWires[527] ) , .Reset_S_in ( ResetWires[20] ) ,
+ .Reset_N_out ( ResetWires[21] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p2602 ) ,
+ .prog_clk_1_S_in ( p3 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3886 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3887 ) ,
+ .prog_clk_2_N_in ( p3531 ) , .prog_clk_2_E_in ( p587 ) ,
+ .prog_clk_2_S_in ( p491 ) , .prog_clk_2_W_in ( p776 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3888 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3889 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3890 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3891 ) ,
+ .prog_clk_3_W_in ( p2651 ) , .prog_clk_3_E_in ( p677 ) ,
+ .prog_clk_3_S_in ( p405 ) , .prog_clk_3_N_in ( p3526 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3892 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3893 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3894 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_1_N_in ( p2602 ) ,
+ .clk_1_S_in ( p695 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3896 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3897 ) , .clk_2_N_in ( p3336 ) ,
+ .clk_2_E_in ( p134 ) , .clk_2_S_in ( p667 ) , .clk_2_W_in ( p2527 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3898 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3899 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3900 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3901 ) , .clk_3_W_in ( p2660 ) ,
+ .clk_3_E_in ( p512 ) , .clk_3_S_in ( p1099 ) , .clk_3_N_in ( p3334 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3902 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3903 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3904 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3905 ) ) ;
+sb_1__1_ sb_6__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3906 } ) ,
+ .chany_top_in ( cby_1__1__71_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__76_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__70_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__65_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__76_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__65_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__65_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__65_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__65_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__65_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[22] ) , .Test_en_N_out ( Test_enWires[23] ) ,
+ .pReset_S_in ( pResetWires[22] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3907 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3908 ) ,
+ .pReset_N_out ( pResetWires[575] ) , .pReset_W_out ( pResetWires[573] ) ,
+ .pReset_E_out ( pResetWires[576] ) , .Reset_S_in ( ResetWires[22] ) ,
+ .Reset_N_out ( ResetWires[23] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p1506 ) ,
+ .prog_clk_1_S_in ( p335 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3909 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3910 ) ,
+ .prog_clk_2_N_in ( p3512 ) , .prog_clk_2_E_in ( p592 ) ,
+ .prog_clk_2_S_in ( p947 ) , .prog_clk_2_W_in ( p233 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3911 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3912 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3913 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3914 ) ,
+ .prog_clk_3_W_in ( p3405 ) , .prog_clk_3_E_in ( p261 ) ,
+ .prog_clk_3_S_in ( p755 ) , .prog_clk_3_N_in ( p3499 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3915 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3916 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3917 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_1_N_in ( p1506 ) ,
+ .clk_1_S_in ( p1036 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , .clk_2_N_in ( p2462 ) ,
+ .clk_2_E_in ( p1025 ) , .clk_2_S_in ( p352 ) , .clk_2_W_in ( p3385 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3921 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3922 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3923 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , .clk_3_W_in ( p2385 ) ,
+ .clk_3_E_in ( p701 ) , .clk_3_S_in ( p1152 ) , .clk_3_N_in ( p2263 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3925 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3926 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3927 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3928 ) ) ;
+sb_1__1_ sb_7__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3929 } ) ,
+ .chany_top_in ( cby_1__1__73_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__77_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__72_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__66_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__77_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__66_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__66_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__66_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p3015 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3930 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3931 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3932 ) ,
+ .pReset_W_in ( pResetWires[87] ) , .pReset_N_out ( pResetWires[89] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_3933 ) ,
+ .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( p3094 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3934 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[258] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[74] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3935 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[127] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3347 ) ,
+ .prog_clk_2_E_in ( p890 ) , .prog_clk_2_S_in ( p953 ) ,
+ .prog_clk_2_W_in ( p599 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3936 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3937 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3938 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3939 ) ,
+ .prog_clk_3_W_in ( p2840 ) , .prog_clk_3_E_in ( p627 ) ,
+ .prog_clk_3_S_in ( p3043 ) , .prog_clk_3_N_in ( p3307 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3940 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3941 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3942 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3943 ) ,
+ .clk_1_N_in ( clk_2_wires[74] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3944 ) ,
+ .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) ,
+ .clk_2_N_in ( p3513 ) , .clk_2_E_in ( p845 ) , .clk_2_S_in ( p679 ) ,
+ .clk_2_W_in ( p3047 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3946 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3947 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , .clk_3_W_in ( p3070 ) ,
+ .clk_3_E_in ( p60 ) , .clk_3_S_in ( p1052 ) , .clk_3_N_in ( p3501 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3949 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3950 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3951 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3952 ) ) ;
+sb_1__1_ sb_7__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3953 } ) ,
+ .chany_top_in ( cby_1__1__74_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__78_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__73_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__67_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__78_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__67_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__67_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__67_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p2865 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3954 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3955 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3956 ) ,
+ .pReset_W_in ( pResetWires[136] ) , .pReset_N_out ( pResetWires[138] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_3957 ) ,
+ .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( p3491 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3958 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p1795 ) ,
+ .prog_clk_1_S_in ( p28 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3959 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3960 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3961 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[72] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3962 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3963 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3964 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[73] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3965 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3966 ) ,
+ .prog_clk_3_W_in ( p1530 ) , .prog_clk_3_E_in ( p283 ) ,
+ .prog_clk_3_S_in ( p3473 ) , .prog_clk_3_N_in ( p163 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3967 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3968 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3969 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( p1795 ) ,
+ .clk_1_S_in ( p1014 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3971 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3972 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3973 ) ,
+ .clk_2_E_in ( clk_2_wires[72] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3974 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3975 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3976 ) ,
+ .clk_2_S_out ( clk_2_wires[73] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3977 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3978 ) , .clk_3_W_in ( p1530 ) ,
+ .clk_3_E_in ( p704 ) , .clk_3_S_in ( p598 ) , .clk_3_N_in ( p1692 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3979 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3980 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3981 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3982 ) ) ;
+sb_1__1_ sb_7__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3983 } ) ,
+ .chany_top_in ( cby_1__1__75_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__79_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__74_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__68_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__79_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__68_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__68_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__68_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p3192 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3984 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3985 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3986 ) ,
+ .pReset_W_in ( pResetWires[185] ) , .pReset_N_out ( pResetWires[187] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_3987 ) ,
+ .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( p3572 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3988 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[264] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[85] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3989 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[134] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3480 ) ,
+ .prog_clk_2_E_in ( p290 ) , .prog_clk_2_S_in ( p770 ) ,
+ .prog_clk_2_W_in ( p718 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3990 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3991 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3992 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3993 ) ,
+ .prog_clk_3_W_in ( p3290 ) , .prog_clk_3_E_in ( p199 ) ,
+ .prog_clk_3_S_in ( p3569 ) , .prog_clk_3_N_in ( p3475 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3994 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3995 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3996 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3997 ) ,
+ .clk_1_N_in ( clk_2_wires[85] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3998 ) ,
+ .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) ,
+ .clk_2_N_in ( p3101 ) , .clk_2_E_in ( p617 ) , .clk_2_S_in ( p1121 ) ,
+ .clk_2_W_in ( p3247 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3999 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4000 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4001 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4002 ) , .clk_3_W_in ( p2093 ) ,
+ .clk_3_E_in ( p888 ) , .clk_3_S_in ( p124 ) , .clk_3_N_in ( p3067 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4003 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4004 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4005 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4006 ) ) ;
+sb_1__1_ sb_7__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4007 } ) ,
+ .chany_top_in ( cby_1__1__76_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__80_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__75_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__69_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__80_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__69_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__69_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__69_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p2219 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4008 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4009 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4010 ) ,
+ .pReset_W_in ( pResetWires[234] ) , .pReset_N_out ( pResetWires[236] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4011 ) ,
+ .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( p3583 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4012 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p2139 ) ,
+ .prog_clk_1_S_in ( p34 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4013 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4014 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4015 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[81] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4016 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4017 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4018 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[84] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[82] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4019 ) ,
+ .prog_clk_3_W_in ( p1912 ) , .prog_clk_3_E_in ( p1308 ) ,
+ .prog_clk_3_S_in ( p3582 ) , .prog_clk_3_N_in ( p518 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4020 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4021 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4022 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) , .clk_1_N_in ( p2162 ) ,
+ .clk_1_S_in ( p738 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4024 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4025 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4026 ) ,
+ .clk_2_E_in ( clk_2_wires[81] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4027 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4028 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4029 ) ,
+ .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4030 ) , .clk_3_W_in ( p1912 ) ,
+ .clk_3_E_in ( p130 ) , .clk_3_S_in ( p551 ) , .clk_3_N_in ( p2007 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4031 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4032 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4033 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4034 ) ) ;
+sb_1__1_ sb_7__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4035 } ) ,
+ .chany_top_in ( cby_1__1__77_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__81_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__76_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__70_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__81_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__70_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__70_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__70_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p1851 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4036 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4037 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4038 ) ,
+ .pReset_W_in ( pResetWires[283] ) , .pReset_N_out ( pResetWires[285] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4039 ) ,
+ .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( p3281 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4040 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[270] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4041 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[83] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[141] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3350 ) ,
+ .prog_clk_2_E_in ( p803 ) , .prog_clk_2_S_in ( p1055 ) ,
+ .prog_clk_2_W_in ( p626 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4042 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4043 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4044 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4045 ) ,
+ .prog_clk_3_W_in ( p3003 ) , .prog_clk_3_E_in ( p79 ) ,
+ .prog_clk_3_S_in ( p3245 ) , .prog_clk_3_N_in ( p3308 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4046 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4047 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4048 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4049 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4050 ) ,
+ .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) ,
+ .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3298 ) ,
+ .clk_2_E_in ( p516 ) , .clk_2_S_in ( p365 ) , .clk_2_W_in ( p2881 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4051 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4052 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4053 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4054 ) , .clk_3_W_in ( p2827 ) ,
+ .clk_3_E_in ( p611 ) , .clk_3_S_in ( p989 ) , .clk_3_N_in ( p3253 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4055 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4056 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4057 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4058 ) ) ;
+sb_1__1_ sb_7__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4059 } ) ,
+ .chany_top_in ( cby_1__1__78_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__82_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__77_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__71_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__82_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__71_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__71_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__71_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2668 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4060 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4061 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4062 ) ,
+ .pReset_W_in ( pResetWires[332] ) , .pReset_N_out ( pResetWires[334] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4063 ) ,
+ .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( p2668 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4064 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1568 ) ,
+ .prog_clk_1_S_in ( p407 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4065 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4066 ) ,
+ .prog_clk_2_N_in ( p2940 ) , .prog_clk_2_E_in ( p81 ) ,
+ .prog_clk_2_S_in ( p2534 ) , .prog_clk_2_W_in ( p1645 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4067 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4068 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4069 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4070 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[1] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4071 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4072 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4073 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[4] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4074 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4075 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p1568 ) ,
+ .clk_1_S_in ( p666 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p1915 ) ,
+ .clk_2_E_in ( p783 ) , .clk_2_S_in ( p857 ) , .clk_2_W_in ( p9 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4079 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4080 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4081 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4082 ) ,
+ .clk_3_W_in ( clk_3_wires[1] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4083 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4084 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4085 ) ,
+ .clk_3_E_out ( clk_3_wires[4] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4086 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4087 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4088 ) ) ;
+sb_1__1_ sb_7__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4089 } ) ,
+ .chany_top_in ( cby_1__1__79_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__83_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__78_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__72_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__83_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__72_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__72_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__72_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p2866 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4090 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4091 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4092 ) ,
+ .pReset_W_in ( pResetWires[381] ) , .pReset_N_out ( pResetWires[383] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4093 ) ,
+ .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( p3535 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4094 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[276] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[98] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4095 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[148] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p3413 ) ,
+ .prog_clk_2_E_in ( p117 ) , .prog_clk_2_S_in ( p879 ) ,
+ .prog_clk_2_W_in ( p675 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4096 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4097 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4098 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4099 ) ,
+ .prog_clk_3_W_in ( p3481 ) , .prog_clk_3_E_in ( p517 ) ,
+ .prog_clk_3_S_in ( p3522 ) , .prog_clk_3_N_in ( p3382 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4100 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4101 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4102 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4103 ) ,
+ .clk_1_N_in ( clk_2_wires[98] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4104 ) ,
+ .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) ,
+ .clk_2_N_in ( p3125 ) , .clk_2_E_in ( p1182 ) , .clk_2_S_in ( p760 ) ,
+ .clk_2_W_in ( p3474 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4105 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4106 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4107 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4108 ) , .clk_3_W_in ( p3227 ) ,
+ .clk_3_E_in ( p419 ) , .clk_3_S_in ( p80 ) , .clk_3_N_in ( p3042 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4109 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4110 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4111 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4112 ) ) ;
+sb_1__1_ sb_7__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4113 } ) ,
+ .chany_top_in ( cby_1__1__80_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__84_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__79_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__73_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__84_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__73_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__73_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__73_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p3463 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4114 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4115 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4116 ) ,
+ .pReset_W_in ( pResetWires[430] ) , .pReset_N_out ( pResetWires[432] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4117 ) ,
+ .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( p2223 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4118 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p1905 ) ,
+ .prog_clk_1_S_in ( p450 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4119 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4120 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4121 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[94] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4122 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4123 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4124 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[97] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[95] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4125 ) ,
+ .prog_clk_3_W_in ( p2075 ) , .prog_clk_3_E_in ( p1260 ) ,
+ .prog_clk_3_S_in ( p3435 ) , .prog_clk_3_N_in ( p2279 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4126 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4127 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4128 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4129 ) , .clk_1_N_in ( p1905 ) ,
+ .clk_1_S_in ( p929 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4130 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4131 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4132 ) ,
+ .clk_2_E_in ( clk_2_wires[94] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4133 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4134 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4135 ) ,
+ .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4136 ) , .clk_3_W_in ( p2075 ) ,
+ .clk_3_E_in ( p173 ) , .clk_3_S_in ( p796 ) , .clk_3_N_in ( p1619 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4137 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4138 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4139 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4140 ) ) ;
+sb_1__1_ sb_7__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4141 } ) ,
+ .chany_top_in ( cby_1__1__81_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__85_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__80_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__74_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__85_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__74_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__74_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__74_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p3280 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4142 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4143 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4144 ) ,
+ .pReset_W_in ( pResetWires[479] ) , .pReset_N_out ( pResetWires[481] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4145 ) ,
+ .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( p3409 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4146 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[282] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4147 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[96] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[155] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p2377 ) ,
+ .prog_clk_2_E_in ( p586 ) , .prog_clk_2_S_in ( p61 ) ,
+ .prog_clk_2_W_in ( p38 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4148 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4149 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4150 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4151 ) ,
+ .prog_clk_3_W_in ( p3074 ) , .prog_clk_3_E_in ( p12 ) ,
+ .prog_clk_3_S_in ( p3387 ) , .prog_clk_3_N_in ( p2301 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4152 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4153 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4154 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4155 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4156 ) ,
+ .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) ,
+ .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3585 ) ,
+ .clk_2_E_in ( p609 ) , .clk_2_S_in ( p746 ) , .clk_2_W_in ( p3026 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4157 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4158 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4159 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_3_W_in ( p2990 ) ,
+ .clk_3_E_in ( p1051 ) , .clk_3_S_in ( p1110 ) , .clk_3_N_in ( p3584 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4161 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4162 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4163 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4164 ) ) ;
+sb_1__1_ sb_7__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4165 } ) ,
+ .chany_top_in ( cby_1__1__82_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__86_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__81_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__75_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__86_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__75_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__75_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__75_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p3352 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4166 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4167 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4168 ) ,
+ .pReset_W_in ( pResetWires[528] ) , .pReset_N_out ( pResetWires[530] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4169 ) ,
+ .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( p3075 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4170 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p2405 ) ,
+ .prog_clk_1_S_in ( p834 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4171 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4172 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4173 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[107] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4174 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4175 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4176 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4177 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[108] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4178 ) ,
+ .prog_clk_3_W_in ( p1856 ) , .prog_clk_3_E_in ( p1325 ) ,
+ .prog_clk_3_S_in ( p3316 ) , .prog_clk_3_N_in ( p1715 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4179 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4180 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4181 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , .clk_1_N_in ( p2437 ) ,
+ .clk_1_S_in ( p247 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4183 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4184 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4185 ) ,
+ .clk_2_E_in ( clk_2_wires[107] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4186 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4187 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4188 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4189 ) ,
+ .clk_2_N_out ( clk_2_wires[108] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4190 ) , .clk_3_W_in ( p1856 ) ,
+ .clk_3_E_in ( p260 ) , .clk_3_S_in ( p1012 ) , .clk_3_N_in ( p2297 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4191 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4192 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4193 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4194 ) ) ;
+sb_1__1_ sb_7__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4195 } ) ,
+ .chany_top_in ( cby_1__1__83_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__87_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__82_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__76_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__87_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__76_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__76_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__76_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p3344 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4196 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4197 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4198 ) ,
+ .pReset_W_in ( pResetWires[577] ) , .pReset_N_out ( pResetWires[579] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4199 ) ,
+ .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( p3508 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4200 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[288] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4201 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[109] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[162] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3581 ) ,
+ .prog_clk_2_E_in ( p156 ) , .prog_clk_2_S_in ( p939 ) ,
+ .prog_clk_2_W_in ( p745 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4202 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4203 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4204 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4205 ) ,
+ .prog_clk_3_W_in ( p3368 ) , .prog_clk_3_E_in ( p903 ) ,
+ .prog_clk_3_S_in ( p3503 ) , .prog_clk_3_N_in ( p3579 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4206 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4207 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4208 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4209 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4210 ) ,
+ .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) ,
+ .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p3077 ) ,
+ .clk_2_E_in ( p847 ) , .clk_2_S_in ( p1202 ) , .clk_2_W_in ( p3331 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4211 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4212 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4213 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4214 ) , .clk_3_W_in ( p2856 ) ,
+ .clk_3_E_in ( p563 ) , .clk_3_S_in ( p349 ) , .clk_3_N_in ( p3031 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4215 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4216 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4217 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4218 ) ) ;
+sb_1__1_ sb_8__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4219 } ) ,
+ .chany_top_in ( cby_1__1__85_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__88_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__84_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__77_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__88_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__77_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__77_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__77_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p1783 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4220 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4221 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4222 ) ,
+ .pReset_W_in ( pResetWires[91] ) , .pReset_N_out ( pResetWires[93] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4223 ) ,
+ .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( p2950 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4224 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p2108 ) ,
+ .prog_clk_1_S_in ( p507 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4225 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4226 ) ,
+ .prog_clk_2_N_in ( p3451 ) , .prog_clk_2_E_in ( p253 ) ,
+ .prog_clk_2_S_in ( p764 ) , .prog_clk_2_W_in ( p267 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4227 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4228 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4229 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4230 ) ,
+ .prog_clk_3_W_in ( p3186 ) , .prog_clk_3_E_in ( p855 ) ,
+ .prog_clk_3_S_in ( p2906 ) , .prog_clk_3_N_in ( p3429 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4231 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4232 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4233 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_1_N_in ( p2108 ) ,
+ .clk_1_S_in ( p619 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4235 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4236 ) , .clk_2_N_in ( p3097 ) ,
+ .clk_2_E_in ( p885 ) , .clk_2_S_in ( p659 ) , .clk_2_W_in ( p3157 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4237 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4238 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4239 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_3_W_in ( p2631 ) ,
+ .clk_3_E_in ( p641 ) , .clk_3_S_in ( p835 ) , .clk_3_N_in ( p3057 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4241 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4242 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4243 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4244 ) ) ;
+sb_1__1_ sb_8__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4245 } ) ,
+ .chany_top_in ( cby_1__1__86_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__89_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__85_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__78_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__89_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__78_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__78_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__78_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p2373 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4246 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4247 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4248 ) ,
+ .pReset_W_in ( pResetWires[140] ) , .pReset_N_out ( pResetWires[142] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4249 ) ,
+ .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( p3556 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4250 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p1027 ) ,
+ .prog_clk_1_S_in ( p607 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4251 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4252 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[43] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4253 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4254 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4255 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[71] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4256 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4257 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p1520 ) ,
+ .prog_clk_3_E_in ( p1259 ) , .prog_clk_3_S_in ( p3552 ) ,
+ .prog_clk_3_N_in ( p451 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4258 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4259 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4260 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4261 ) , .clk_1_N_in ( p1027 ) ,
+ .clk_1_S_in ( p197 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4262 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4263 ) ,
+ .clk_2_N_in ( clk_3_wires[43] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4264 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4265 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4266 ) ,
+ .clk_2_W_out ( clk_2_wires[71] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4267 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4268 ) ,
+ .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p1520 ) ,
+ .clk_3_E_in ( p251 ) , .clk_3_S_in ( p348 ) , .clk_3_N_in ( p6 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4269 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4270 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4271 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4272 ) ) ;
+sb_1__1_ sb_8__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4273 } ) ,
+ .chany_top_in ( cby_1__1__87_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__90_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__86_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__79_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__90_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__79_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__79_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__79_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2160 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4274 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4275 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4276 ) ,
+ .pReset_W_in ( pResetWires[189] ) , .pReset_N_out ( pResetWires[191] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4277 ) ,
+ .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( p3216 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4278 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p1599 ) ,
+ .prog_clk_1_S_in ( p131 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4279 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4280 ) ,
+ .prog_clk_2_N_in ( p2403 ) , .prog_clk_2_E_in ( p553 ) ,
+ .prog_clk_2_S_in ( p3150 ) , .prog_clk_2_W_in ( p219 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4281 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4282 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4283 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4284 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4285 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4286 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4287 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[39] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4288 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4289 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4290 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p1599 ) ,
+ .clk_1_S_in ( p936 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4291 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4292 ) , .clk_2_N_in ( p1830 ) ,
+ .clk_2_E_in ( p898 ) , .clk_2_S_in ( p441 ) , .clk_2_W_in ( p604 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4293 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4294 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4295 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4296 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4297 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4298 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4299 ) ,
+ .clk_3_N_in ( clk_3_wires[39] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4300 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4301 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4302 ) ,
+ .clk_3_S_out ( clk_3_wires[42] ) ) ;
+sb_1__1_ sb_8__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4303 } ) ,
+ .chany_top_in ( cby_1__1__88_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__91_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__87_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__80_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__91_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__80_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__80_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__80_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p2406 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4304 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4305 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4306 ) ,
+ .pReset_W_in ( pResetWires[238] ) , .pReset_N_out ( pResetWires[240] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4307 ) ,
+ .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( p2406 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4308 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p1848 ) ,
+ .prog_clk_1_S_in ( p2280 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4309 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4310 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[33] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4311 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4312 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4313 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[80] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4314 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4315 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[78] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4316 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4317 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4318 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[33] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4319 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4320 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4321 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p1848 ) ,
+ .clk_1_S_in ( p576 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4322 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4323 ) ,
+ .clk_2_N_in ( clk_3_wires[33] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4324 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4325 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4326 ) ,
+ .clk_2_W_out ( clk_2_wires[80] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4327 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4328 ) ,
+ .clk_2_E_out ( clk_2_wires[78] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4329 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4330 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4331 ) ,
+ .clk_3_N_in ( clk_3_wires[33] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4332 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4333 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4334 ) ,
+ .clk_3_S_out ( clk_3_wires[38] ) ) ;
+sb_1__1_ sb_8__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4335 } ) ,
+ .chany_top_in ( cby_1__1__89_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__92_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__88_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__81_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__92_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__81_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__81_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__81_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2380 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4336 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4337 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4338 ) ,
+ .pReset_W_in ( pResetWires[287] ) , .pReset_N_out ( pResetWires[289] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4339 ) ,
+ .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( p2955 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4340 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1810 ) ,
+ .prog_clk_1_S_in ( p930 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4341 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4342 ) ,
+ .prog_clk_2_N_in ( p2368 ) , .prog_clk_2_E_in ( p329 ) ,
+ .prog_clk_2_S_in ( p2909 ) , .prog_clk_2_W_in ( p35 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4343 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4344 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4345 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4346 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4347 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4348 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4349 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[29] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4350 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4351 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4352 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1810 ) ,
+ .clk_1_S_in ( p146 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4353 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4354 ) , .clk_2_N_in ( p2221 ) ,
+ .clk_2_E_in ( p818 ) , .clk_2_S_in ( p1287 ) , .clk_2_W_in ( p788 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4355 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4356 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4357 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4358 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4359 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4360 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4361 ) ,
+ .clk_3_N_in ( clk_3_wires[29] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4362 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4363 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4364 ) ,
+ .clk_3_S_out ( clk_3_wires[32] ) ) ;
+sb_1__1_ sb_8__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4365 } ) ,
+ .chany_top_in ( cby_1__1__90_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__93_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__89_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__82_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__93_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__82_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__82_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__82_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p2488 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4366 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4367 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4368 ) ,
+ .pReset_W_in ( pResetWires[336] ) , .pReset_N_out ( pResetWires[338] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4369 ) ,
+ .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( p3200 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4370 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1160 ) ,
+ .prog_clk_1_S_in ( p457 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4371 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4372 ) ,
+ .prog_clk_2_N_in ( p2597 ) , .prog_clk_2_E_in ( p526 ) ,
+ .prog_clk_2_S_in ( p3158 ) , .prog_clk_2_W_in ( p1265 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4373 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4374 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4375 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4376 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[5] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4377 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4378 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4379 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[44] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4380 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[26] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1160 ) ,
+ .clk_1_S_in ( p649 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4381 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4382 ) , .clk_2_N_in ( p2451 ) ,
+ .clk_2_E_in ( p332 ) , .clk_2_S_in ( p1372 ) , .clk_2_W_in ( p301 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4383 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4384 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4385 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4386 ) ,
+ .clk_3_W_in ( clk_3_wires[5] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4387 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4388 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4389 ) ,
+ .clk_3_E_out ( clk_3_wires[44] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4390 ) ,
+ .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) ) ;
+sb_1__1_ sb_8__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4391 } ) ,
+ .chany_top_in ( cby_1__1__91_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__94_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__90_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__83_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__94_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__83_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__83_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__83_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p2107 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4392 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4393 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4394 ) ,
+ .pReset_W_in ( pResetWires[385] ) , .pReset_N_out ( pResetWires[387] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4395 ) ,
+ .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( p2671 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4396 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1184 ) ,
+ .prog_clk_1_S_in ( p151 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4397 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4398 ) ,
+ .prog_clk_2_N_in ( p2343 ) , .prog_clk_2_E_in ( p171 ) ,
+ .prog_clk_2_S_in ( p2532 ) , .prog_clk_2_W_in ( p521 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4399 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4400 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4401 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4402 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4403 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4404 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[27] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4405 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4406 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4407 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[30] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_1_N_in ( p1184 ) ,
+ .clk_1_S_in ( p889 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4409 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_2_N_in ( p2101 ) ,
+ .clk_2_E_in ( p703 ) , .clk_2_S_in ( p1306 ) , .clk_2_W_in ( p392 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4411 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4412 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4413 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4414 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4415 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4416 ) ,
+ .clk_3_S_in ( clk_3_wires[27] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4417 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4418 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4419 ) ,
+ .clk_3_N_out ( clk_3_wires[30] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4420 ) ) ;
+sb_1__1_ sb_8__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4421 } ) ,
+ .chany_top_in ( cby_1__1__92_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__95_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__91_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__84_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__95_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__84_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__84_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__84_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p1797 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4422 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4423 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4424 ) ,
+ .pReset_W_in ( pResetWires[434] ) , .pReset_N_out ( pResetWires[436] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4425 ) ,
+ .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( p1797 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4426 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1941 ) ,
+ .prog_clk_1_S_in ( p1635 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4427 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4428 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4429 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4430 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[31] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4431 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[93] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4432 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4433 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[91] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4434 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4435 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[31] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4436 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4437 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4438 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[36] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_1_N_in ( p1941 ) ,
+ .clk_1_S_in ( p775 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4440 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4441 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4442 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4443 ) ,
+ .clk_2_S_in ( clk_3_wires[31] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4444 ) ,
+ .clk_2_W_out ( clk_2_wires[93] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4445 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4446 ) ,
+ .clk_2_E_out ( clk_2_wires[91] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4447 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4448 ) ,
+ .clk_3_S_in ( clk_3_wires[31] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4449 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4450 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4451 ) ,
+ .clk_3_N_out ( clk_3_wires[36] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4452 ) ) ;
+sb_1__1_ sb_8__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4453 } ) ,
+ .chany_top_in ( cby_1__1__93_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__96_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__92_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__85_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__96_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__85_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__85_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__85_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2084 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4454 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4455 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4456 ) ,
+ .pReset_W_in ( pResetWires[483] ) , .pReset_N_out ( pResetWires[485] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4457 ) ,
+ .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( p2849 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4458 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1804 ) ,
+ .prog_clk_1_S_in ( p559 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4459 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4460 ) ,
+ .prog_clk_2_N_in ( p2242 ) , .prog_clk_2_E_in ( p326 ) ,
+ .prog_clk_2_S_in ( p2738 ) , .prog_clk_2_W_in ( p202 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4461 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4462 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4463 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4464 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4465 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4466 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[37] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4467 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4468 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4469 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[40] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_1_N_in ( p1804 ) ,
+ .clk_1_S_in ( p1033 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4471 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4472 ) , .clk_2_N_in ( p2208 ) ,
+ .clk_2_E_in ( p787 ) , .clk_2_S_in ( p2067 ) , .clk_2_W_in ( p470 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4473 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4474 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4475 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4476 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4477 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4478 ) ,
+ .clk_3_S_in ( clk_3_wires[37] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4479 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4480 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4481 ) ,
+ .clk_3_N_out ( clk_3_wires[40] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4482 ) ) ;
+sb_1__1_ sb_8__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4483 } ) ,
+ .chany_top_in ( cby_1__1__94_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__97_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__93_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__86_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__97_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__86_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__86_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__86_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p3204 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4484 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4485 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4486 ) ,
+ .pReset_W_in ( pResetWires[532] ) , .pReset_N_out ( pResetWires[534] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4487 ) ,
+ .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( p3573 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4488 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p1567 ) ,
+ .prog_clk_1_S_in ( p43 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4489 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4490 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4491 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4492 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[41] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4493 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[106] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4494 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4495 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p2492 ) ,
+ .prog_clk_3_E_in ( p1266 ) , .prog_clk_3_S_in ( p3570 ) ,
+ .prog_clk_3_N_in ( p540 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4496 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4497 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4498 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , .clk_1_N_in ( p1567 ) ,
+ .clk_1_S_in ( p837 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4500 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4501 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4502 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4503 ) ,
+ .clk_2_S_in ( clk_3_wires[41] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4504 ) ,
+ .clk_2_W_out ( clk_2_wires[106] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4505 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4506 ) ,
+ .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p2492 ) ,
+ .clk_3_E_in ( p854 ) , .clk_3_S_in ( p1695 ) , .clk_3_N_in ( p1333 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4507 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4508 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4509 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4510 ) ) ;
+sb_1__1_ sb_8__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4511 } ) ,
+ .chany_top_in ( cby_1__1__95_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__98_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__94_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__87_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__98_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__87_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__87_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__87_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p3546 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4512 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4513 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4514 ) ,
+ .pReset_W_in ( pResetWires[581] ) , .pReset_N_out ( pResetWires[583] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4515 ) ,
+ .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( p1744 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4516 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p1536 ) ,
+ .prog_clk_1_S_in ( p798 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4517 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4518 ) ,
+ .prog_clk_2_N_in ( p3299 ) , .prog_clk_2_E_in ( p190 ) ,
+ .prog_clk_2_S_in ( p866 ) , .prog_clk_2_W_in ( p263 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4519 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4520 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4521 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4522 ) ,
+ .prog_clk_3_W_in ( p3446 ) , .prog_clk_3_E_in ( p432 ) ,
+ .prog_clk_3_S_in ( p3539 ) , .prog_clk_3_N_in ( p3246 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4523 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4524 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4525 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_1_N_in ( p1536 ) ,
+ .clk_1_S_in ( p116 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4527 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , .clk_2_N_in ( p3397 ) ,
+ .clk_2_E_in ( p455 ) , .clk_2_S_in ( p1039 ) , .clk_2_W_in ( p3436 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4529 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4530 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4531 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4532 ) , .clk_3_W_in ( p3080 ) ,
+ .clk_3_E_in ( p867 ) , .clk_3_S_in ( p394 ) , .clk_3_N_in ( p3392 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4533 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4534 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4535 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4536 ) ) ;
+sb_1__1_ sb_9__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4537 } ) ,
+ .chany_top_in ( cby_1__1__97_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__99_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__96_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__88_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__99_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__88_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__88_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__88_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p3114 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4538 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4539 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4540 ) ,
+ .pReset_W_in ( pResetWires[95] ) , .pReset_N_out ( pResetWires[97] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4541 ) ,
+ .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( p3517 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4542 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[334] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[76] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4543 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[169] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3576 ) ,
+ .prog_clk_2_E_in ( p749 ) , .prog_clk_2_S_in ( p719 ) ,
+ .prog_clk_2_W_in ( p618 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4544 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4545 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4546 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4547 ) ,
+ .prog_clk_3_W_in ( p2415 ) , .prog_clk_3_E_in ( p672 ) ,
+ .prog_clk_3_S_in ( p3496 ) , .prog_clk_3_N_in ( p3575 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4548 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4549 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4550 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4551 ) ,
+ .clk_1_N_in ( clk_2_wires[76] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4552 ) ,
+ .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) ,
+ .clk_2_N_in ( p3444 ) , .clk_2_E_in ( p791 ) , .clk_2_S_in ( p777 ) ,
+ .clk_2_W_in ( p2284 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4553 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4554 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4555 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , .clk_3_W_in ( p1452 ) ,
+ .clk_3_E_in ( p172 ) , .clk_3_S_in ( p709 ) , .clk_3_N_in ( p3442 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4557 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4558 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4559 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4560 ) ) ;
+sb_1__1_ sb_9__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4561 } ) ,
+ .chany_top_in ( cby_1__1__98_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__100_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__97_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__89_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__100_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__89_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__89_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__89_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p2872 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4562 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4563 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4564 ) ,
+ .pReset_W_in ( pResetWires[144] ) , .pReset_N_out ( pResetWires[146] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4565 ) ,
+ .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( p3100 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4566 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p2200 ) ,
+ .prog_clk_1_S_in ( p206 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4567 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4568 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4569 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4570 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4571 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[70] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4572 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[75] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4573 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4574 ) ,
+ .prog_clk_3_W_in ( p1828 ) , .prog_clk_3_E_in ( p833 ) ,
+ .prog_clk_3_S_in ( p3029 ) , .prog_clk_3_N_in ( p46 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4575 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4576 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4577 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4578 ) , .clk_1_N_in ( p2200 ) ,
+ .clk_1_S_in ( p922 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4579 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4580 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4581 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4582 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4583 ) ,
+ .clk_2_W_in ( clk_2_wires[70] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4584 ) ,
+ .clk_2_S_out ( clk_2_wires[75] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4585 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4586 ) , .clk_3_W_in ( p1828 ) ,
+ .clk_3_E_in ( p258 ) , .clk_3_S_in ( p682 ) , .clk_3_N_in ( p1961 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4587 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4588 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4589 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4590 ) ) ;
+sb_1__1_ sb_9__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4591 } ) ,
+ .chany_top_in ( cby_1__1__99_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__101_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__98_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__90_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__101_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__90_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__90_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__90_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p3485 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4592 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4593 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4594 ) ,
+ .pReset_W_in ( pResetWires[193] ) , .pReset_N_out ( pResetWires[195] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4595 ) ,
+ .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( p3272 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4596 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[340] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[89] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4597 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[176] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p3547 ) ,
+ .prog_clk_2_E_in ( p189 ) , .prog_clk_2_S_in ( p149 ) ,
+ .prog_clk_2_W_in ( p440 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4598 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4599 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4600 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4601 ) ,
+ .prog_clk_3_W_in ( p3221 ) , .prog_clk_3_E_in ( p1131 ) ,
+ .prog_clk_3_S_in ( p3465 ) , .prog_clk_3_N_in ( p3537 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4602 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4603 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4604 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4605 ) ,
+ .clk_1_N_in ( clk_2_wires[89] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4606 ) ,
+ .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) ,
+ .clk_2_N_in ( p3124 ) , .clk_2_E_in ( p663 ) , .clk_2_S_in ( p1242 ) ,
+ .clk_2_W_in ( p3135 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4608 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4609 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , .clk_3_W_in ( p2809 ) ,
+ .clk_3_E_in ( p901 ) , .clk_3_S_in ( p753 ) , .clk_3_N_in ( p3027 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4611 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4612 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4613 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4614 ) ) ;
+sb_1__1_ sb_9__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4615 } ) ,
+ .chany_top_in ( cby_1__1__100_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__102_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__99_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__91_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__102_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__91_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__91_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__91_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2799 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4616 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4617 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4618 ) ,
+ .pReset_W_in ( pResetWires[242] ) , .pReset_N_out ( pResetWires[244] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4619 ) ,
+ .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( p2636 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4620 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p1837 ) ,
+ .prog_clk_1_S_in ( p304 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4621 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4622 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4623 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4624 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4625 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[79] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4626 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[88] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[86] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4627 ) ,
+ .prog_clk_3_W_in ( p1749 ) , .prog_clk_3_E_in ( p998 ) ,
+ .prog_clk_3_S_in ( p2714 ) , .prog_clk_3_N_in ( p2258 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4628 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4629 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4630 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_N_in ( p1837 ) ,
+ .clk_1_S_in ( p932 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4632 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4633 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4634 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4635 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4636 ) ,
+ .clk_2_W_in ( clk_2_wires[79] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4637 ) ,
+ .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4638 ) , .clk_3_W_in ( p1749 ) ,
+ .clk_3_E_in ( p18 ) , .clk_3_S_in ( p425 ) , .clk_3_N_in ( p1713 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4639 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4640 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4641 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4642 ) ) ;
+sb_1__1_ sb_9__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4643 } ) ,
+ .chany_top_in ( cby_1__1__101_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__103_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__100_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__92_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__103_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__92_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__92_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__92_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p3359 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4644 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4645 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4646 ) ,
+ .pReset_W_in ( pResetWires[291] ) , .pReset_N_out ( pResetWires[293] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4647 ) ,
+ .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( p3209 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4648 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[346] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4649 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[87] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[183] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p3571 ) ,
+ .prog_clk_2_E_in ( p630 ) , .prog_clk_2_S_in ( p669 ) ,
+ .prog_clk_2_W_in ( p916 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4650 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4651 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4652 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4653 ) ,
+ .prog_clk_3_W_in ( p3483 ) , .prog_clk_3_E_in ( p603 ) ,
+ .prog_clk_3_S_in ( p3324 ) , .prog_clk_3_N_in ( p3568 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4654 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4655 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4656 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4657 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4658 ) ,
+ .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) ,
+ .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p3587 ) ,
+ .clk_2_E_in ( p784 ) , .clk_2_S_in ( p1023 ) , .clk_2_W_in ( p3477 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4659 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4660 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4661 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , .clk_3_W_in ( p2211 ) ,
+ .clk_3_E_in ( p47 ) , .clk_3_S_in ( p31 ) , .clk_3_N_in ( p3586 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4663 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4664 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4665 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4666 ) ) ;
+sb_1__1_ sb_9__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4667 } ) ,
+ .chany_top_in ( cby_1__1__102_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__104_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__101_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__93_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__104_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__93_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__93_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__93_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p2057 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4668 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4669 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4670 ) ,
+ .pReset_W_in ( pResetWires[340] ) , .pReset_N_out ( pResetWires[342] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4671 ) ,
+ .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( p2958 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4672 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1898 ) ,
+ .prog_clk_1_S_in ( p961 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4673 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4674 ) ,
+ .prog_clk_2_N_in ( p2656 ) , .prog_clk_2_E_in ( p653 ) ,
+ .prog_clk_2_S_in ( p2890 ) , .prog_clk_2_W_in ( p1268 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4675 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4676 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4677 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4678 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[45] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4679 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4680 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4681 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[48] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4682 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4683 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_1_N_in ( p1898 ) ,
+ .clk_1_S_in ( p239 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4685 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4686 ) , .clk_2_N_in ( p2371 ) ,
+ .clk_2_E_in ( p411 ) , .clk_2_S_in ( p503 ) , .clk_2_W_in ( p204 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4687 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4688 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4689 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4690 ) ,
+ .clk_3_W_in ( clk_3_wires[45] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4691 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4692 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4693 ) ,
+ .clk_3_E_out ( clk_3_wires[48] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4694 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4695 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4696 ) ) ;
+sb_1__1_ sb_9__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4697 } ) ,
+ .chany_top_in ( cby_1__1__103_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__105_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__102_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__94_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__105_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__94_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__94_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__94_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p3448 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4698 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4699 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4700 ) ,
+ .pReset_W_in ( pResetWires[389] ) , .pReset_N_out ( pResetWires[391] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4701 ) ,
+ .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( p3450 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4702 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[352] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[102] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4703 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[190] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p3479 ) ,
+ .prog_clk_2_E_in ( p573 ) , .prog_clk_2_S_in ( p1066 ) ,
+ .prog_clk_2_W_in ( p70 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4704 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4705 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4706 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4707 ) ,
+ .prog_clk_3_W_in ( p1515 ) , .prog_clk_3_E_in ( p727 ) ,
+ .prog_clk_3_S_in ( p3427 ) , .prog_clk_3_N_in ( p3471 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4708 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4709 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4710 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4711 ) ,
+ .clk_1_N_in ( clk_2_wires[102] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4712 ) ,
+ .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) ,
+ .clk_2_N_in ( p3410 ) , .clk_2_E_in ( p1130 ) , .clk_2_S_in ( p88 ) ,
+ .clk_2_W_in ( p1275 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4713 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4714 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4715 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4716 ) , .clk_3_W_in ( p1608 ) ,
+ .clk_3_E_in ( p162 ) , .clk_3_S_in ( p661 ) , .clk_3_N_in ( p3381 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4717 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4718 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4719 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4720 ) ) ;
+sb_1__1_ sb_9__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4721 } ) ,
+ .chany_top_in ( cby_1__1__104_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__106_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__103_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__95_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__106_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__95_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__95_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__95_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p3286 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4722 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4723 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4724 ) ,
+ .pReset_W_in ( pResetWires[438] ) , .pReset_N_out ( pResetWires[440] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4725 ) ,
+ .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( p3345 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4726 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p1877 ) ,
+ .prog_clk_1_S_in ( p395 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4727 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4728 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4729 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4730 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4731 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[92] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4732 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[101] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[99] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4733 ) ,
+ .prog_clk_3_W_in ( p1181 ) , .prog_clk_3_E_in ( p121 ) ,
+ .prog_clk_3_S_in ( p3328 ) , .prog_clk_3_N_in ( p1362 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4734 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4735 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4736 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_1_N_in ( p1877 ) ,
+ .clk_1_S_in ( p1083 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4738 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4739 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4740 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4741 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4742 ) ,
+ .clk_2_W_in ( clk_2_wires[92] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4743 ) ,
+ .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , .clk_3_W_in ( p1181 ) ,
+ .clk_3_E_in ( p286 ) , .clk_3_S_in ( p511 ) , .clk_3_N_in ( p1672 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4745 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4746 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4747 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4748 ) ) ;
+sb_1__1_ sb_9__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4749 } ) ,
+ .chany_top_in ( cby_1__1__105_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__107_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__104_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__96_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__107_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__96_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__96_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__96_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p3084 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4750 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4751 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4752 ) ,
+ .pReset_W_in ( pResetWires[487] ) , .pReset_N_out ( pResetWires[489] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4753 ) ,
+ .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( p3534 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4754 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[358] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4755 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[100] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[197] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p2654 ) ,
+ .prog_clk_2_E_in ( p480 ) , .prog_clk_2_S_in ( p1100 ) ,
+ .prog_clk_2_W_in ( p13 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4756 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4757 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4758 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4759 ) ,
+ .prog_clk_3_W_in ( p3208 ) , .prog_clk_3_E_in ( p806 ) ,
+ .prog_clk_3_S_in ( p3524 ) , .prog_clk_3_N_in ( p2556 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4760 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4761 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4762 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4763 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4764 ) ,
+ .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) ,
+ .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p3548 ) ,
+ .clk_2_E_in ( p1046 ) , .clk_2_S_in ( p57 ) , .clk_2_W_in ( p3141 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4765 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4766 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4767 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4768 ) , .clk_3_W_in ( p2487 ) ,
+ .clk_3_E_in ( p294 ) , .clk_3_S_in ( p1153 ) , .clk_3_N_in ( p3541 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4769 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4770 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4771 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4772 ) ) ;
+sb_1__1_ sb_9__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4773 } ) ,
+ .chany_top_in ( cby_1__1__106_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__108_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__105_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__97_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__108_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__97_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__97_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__97_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p3516 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4774 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4775 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4776 ) ,
+ .pReset_W_in ( pResetWires[536] ) , .pReset_N_out ( pResetWires[538] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4777 ) ,
+ .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( p3484 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4778 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p1881 ) ,
+ .prog_clk_1_S_in ( p542 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4779 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4780 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4781 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4782 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4783 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[105] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4784 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4785 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[110] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4786 ) ,
+ .prog_clk_3_W_in ( p1922 ) , .prog_clk_3_E_in ( p737 ) ,
+ .prog_clk_3_S_in ( p3504 ) , .prog_clk_3_N_in ( p1718 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4787 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4788 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4789 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , .clk_1_N_in ( p1881 ) ,
+ .clk_1_S_in ( p145 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4791 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4792 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4793 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4794 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4795 ) ,
+ .clk_2_W_in ( clk_2_wires[105] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4796 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4797 ) ,
+ .clk_2_N_out ( clk_2_wires[110] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4798 ) , .clk_3_W_in ( p1922 ) ,
+ .clk_3_E_in ( p110 ) , .clk_3_S_in ( p671 ) , .clk_3_N_in ( p1638 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4799 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4800 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4801 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4802 ) ) ;
+sb_1__1_ sb_9__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4803 } ) ,
+ .chany_top_in ( cby_1__1__107_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__109_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__106_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__98_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__109_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__98_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__98_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__98_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2697 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4804 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4805 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4806 ) ,
+ .pReset_W_in ( pResetWires[585] ) , .pReset_N_out ( pResetWires[587] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4807 ) ,
+ .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( p2960 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4808 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[364] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4809 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[111] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[204] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p3490 ) ,
+ .prog_clk_2_E_in ( p975 ) , .prog_clk_2_S_in ( p712 ) ,
+ .prog_clk_2_W_in ( p99 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4810 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4811 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4812 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4813 ) ,
+ .prog_clk_3_W_in ( p3270 ) , .prog_clk_3_E_in ( p720 ) ,
+ .prog_clk_3_S_in ( p2901 ) , .prog_clk_3_N_in ( p3466 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4814 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4815 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4816 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4817 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4818 ) ,
+ .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) ,
+ .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3399 ) ,
+ .clk_2_E_in ( p732 ) , .clk_2_S_in ( p179 ) , .clk_2_W_in ( p3256 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4819 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4820 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4821 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , .clk_3_W_in ( p3109 ) ,
+ .clk_3_E_in ( p183 ) , .clk_3_S_in ( p1244 ) , .clk_3_N_in ( p3378 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4823 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4824 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4825 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4826 ) ) ;
+sb_1__1_ sb_10__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4827 } ) ,
+ .chany_top_in ( cby_1__1__109_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__110_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__108_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__99_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__110_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__99_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__99_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__99_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p2951 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4828 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4829 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4830 ) ,
+ .pReset_W_in ( pResetWires[99] ) , .pReset_N_out ( pResetWires[101] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4831 ) ,
+ .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( p3460 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4832 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p2365 ) ,
+ .prog_clk_1_S_in ( p312 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4833 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4834 ) ,
+ .prog_clk_2_N_in ( p3355 ) , .prog_clk_2_E_in ( p793 ) ,
+ .prog_clk_2_S_in ( p308 ) , .prog_clk_2_W_in ( p152 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4835 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4836 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4837 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4838 ) ,
+ .prog_clk_3_W_in ( p3419 ) , .prog_clk_3_E_in ( p795 ) ,
+ .prog_clk_3_S_in ( p3439 ) , .prog_clk_3_N_in ( p3304 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4839 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4840 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4841 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_1_N_in ( p2365 ) ,
+ .clk_1_S_in ( p1142 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4843 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4844 ) , .clk_2_N_in ( p3493 ) ,
+ .clk_2_E_in ( p37 ) , .clk_2_S_in ( p622 ) , .clk_2_W_in ( p3376 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4845 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4846 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4847 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4848 ) , .clk_3_W_in ( p3134 ) ,
+ .clk_3_E_in ( p1053 ) , .clk_3_S_in ( p1218 ) , .clk_3_N_in ( p3472 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4849 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4850 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4851 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4852 ) ) ;
+sb_1__1_ sb_10__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4853 } ) ,
+ .chany_top_in ( cby_1__1__110_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__111_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__109_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__100_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__111_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__100_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__100_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__100_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p3000 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4854 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4855 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4856 ) ,
+ .pReset_W_in ( pResetWires[148] ) , .pReset_N_out ( pResetWires[150] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4857 ) ,
+ .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( p3115 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4858 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p1611 ) ,
+ .prog_clk_1_S_in ( p266 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4859 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4860 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[87] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4861 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4862 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4863 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4864 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4865 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4866 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p1449 ) ,
+ .prog_clk_3_E_in ( p1653 ) , .prog_clk_3_S_in ( p3046 ) ,
+ .prog_clk_3_N_in ( p318 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4867 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4868 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4869 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4870 ) , .clk_1_N_in ( p1611 ) ,
+ .clk_1_S_in ( p1043 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4871 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4872 ) ,
+ .clk_2_N_in ( clk_3_wires[87] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4873 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4874 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4875 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4876 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4877 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4878 ) ,
+ .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p1449 ) ,
+ .clk_3_E_in ( p105 ) , .clk_3_S_in ( p838 ) , .clk_3_N_in ( p1255 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4879 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4880 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4881 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4882 ) ) ;
+sb_1__1_ sb_10__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4883 } ) ,
+ .chany_top_in ( cby_1__1__111_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__112_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__110_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__101_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__112_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__101_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__101_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__101_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p2445 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4884 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4885 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4886 ) ,
+ .pReset_W_in ( pResetWires[197] ) , .pReset_N_out ( pResetWires[199] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4887 ) ,
+ .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( p3117 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4888 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1819 ) ,
+ .prog_clk_1_S_in ( p21 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4889 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4890 ) ,
+ .prog_clk_2_N_in ( p2095 ) , .prog_clk_2_E_in ( p235 ) ,
+ .prog_clk_2_S_in ( p3050 ) , .prog_clk_2_W_in ( p309 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4891 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4892 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4893 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4894 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4895 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4896 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4897 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[83] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4898 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4899 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4900 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1819 ) ,
+ .clk_1_S_in ( p911 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4901 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4902 ) , .clk_2_N_in ( p2095 ) ,
+ .clk_2_E_in ( p959 ) , .clk_2_S_in ( p1161 ) , .clk_2_W_in ( p831 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4903 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4904 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4905 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4906 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4907 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4908 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4909 ) ,
+ .clk_3_N_in ( clk_3_wires[83] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4910 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4911 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4912 ) ,
+ .clk_3_S_out ( clk_3_wires[86] ) ) ;
+sb_1__1_ sb_10__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4913 } ) ,
+ .chany_top_in ( cby_1__1__112_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__113_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__111_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__102_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__113_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__102_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__102_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__102_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p2430 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4914 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4915 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4916 ) ,
+ .pReset_W_in ( pResetWires[246] ) , .pReset_N_out ( pResetWires[248] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4917 ) ,
+ .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( p2430 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4918 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1239 ) ,
+ .prog_clk_1_S_in ( p2283 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4919 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4920 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[77] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4921 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4922 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4923 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4924 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4925 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4926 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[119] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4927 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4928 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4929 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[77] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4930 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4931 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4932 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1239 ) ,
+ .clk_1_S_in ( p1079 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4933 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4934 ) ,
+ .clk_2_N_in ( clk_3_wires[77] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4935 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4936 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4937 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4938 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4939 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4940 ) ,
+ .clk_2_E_out ( clk_2_wires[119] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4941 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4942 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4943 ) ,
+ .clk_3_N_in ( clk_3_wires[77] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4944 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4945 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4946 ) ,
+ .clk_3_S_out ( clk_3_wires[82] ) ) ;
+sb_1__1_ sb_10__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4947 } ) ,
+ .chany_top_in ( cby_1__1__113_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__114_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__112_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__103_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__114_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__103_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__103_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__103_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p1946 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4948 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4949 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4950 ) ,
+ .pReset_W_in ( pResetWires[295] ) , .pReset_N_out ( pResetWires[297] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4951 ) ,
+ .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( p3361 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4952 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p1889 ) ,
+ .prog_clk_1_S_in ( p22 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4953 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4954 ) ,
+ .prog_clk_2_N_in ( p2646 ) , .prog_clk_2_E_in ( p56 ) ,
+ .prog_clk_2_S_in ( p3314 ) , .prog_clk_2_W_in ( p530 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4955 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4956 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4957 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4958 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4959 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4960 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4961 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[73] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4962 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4963 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4964 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p1889 ) ,
+ .clk_1_S_in ( p1076 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4965 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4966 ) , .clk_2_N_in ( p2143 ) ,
+ .clk_2_E_in ( p925 ) , .clk_2_S_in ( p1727 ) , .clk_2_W_in ( p397 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4967 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4968 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4969 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4970 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4971 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4972 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4973 ) ,
+ .clk_3_N_in ( clk_3_wires[73] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4974 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4975 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4976 ) ,
+ .clk_3_S_out ( clk_3_wires[76] ) ) ;
+sb_1__1_ sb_10__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4977 } ) ,
+ .chany_top_in ( cby_1__1__114_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__115_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__113_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__104_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__115_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__104_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__104_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__104_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p2708 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4978 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4979 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4980 ) ,
+ .pReset_W_in ( pResetWires[344] ) , .pReset_N_out ( pResetWires[346] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4981 ) ,
+ .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( p2708 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4982 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1483 ) ,
+ .prog_clk_1_S_in ( p228 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4983 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4984 ) ,
+ .prog_clk_2_N_in ( p2594 ) , .prog_clk_2_E_in ( p479 ) ,
+ .prog_clk_2_S_in ( p2545 ) , .prog_clk_2_W_in ( p161 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4985 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4986 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4987 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4988 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[49] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4989 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4990 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4991 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4992 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4993 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[70] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1483 ) ,
+ .clk_1_S_in ( p658 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4994 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4995 ) , .clk_2_N_in ( p1403 ) ,
+ .clk_2_E_in ( p166 ) , .clk_2_S_in ( p1294 ) , .clk_2_W_in ( p792 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4996 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4997 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4998 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4999 ) ,
+ .clk_3_W_in ( clk_3_wires[49] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5000 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5001 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5002 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5003 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5004 ) ,
+ .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) ) ;
+sb_1__1_ sb_10__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5005 } ) ,
+ .chany_top_in ( cby_1__1__115_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__116_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__114_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__105_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__116_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__105_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__105_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__105_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p2658 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5006 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5007 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5008 ) ,
+ .pReset_W_in ( pResetWires[393] ) , .pReset_N_out ( pResetWires[395] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5009 ) ,
+ .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( p2700 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5010 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1440 ) ,
+ .prog_clk_1_S_in ( p546 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5011 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5012 ) ,
+ .prog_clk_2_N_in ( p2794 ) , .prog_clk_2_E_in ( p201 ) ,
+ .prog_clk_2_S_in ( p2520 ) , .prog_clk_2_W_in ( p536 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5013 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5014 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5015 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5016 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5017 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5018 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[71] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5019 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5020 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5021 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[74] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_1_N_in ( p1440 ) ,
+ .clk_1_S_in ( p569 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5023 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5024 ) , .clk_2_N_in ( p2120 ) ,
+ .clk_2_E_in ( p493 ) , .clk_2_S_in ( p1295 ) , .clk_2_W_in ( p211 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5025 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5026 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5027 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5028 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5029 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5030 ) ,
+ .clk_3_S_in ( clk_3_wires[71] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5031 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5032 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5033 ) ,
+ .clk_3_N_out ( clk_3_wires[74] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5034 ) ) ;
+sb_1__1_ sb_10__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5035 } ) ,
+ .chany_top_in ( cby_1__1__116_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__117_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__115_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__106_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__117_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__106_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__106_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__106_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p2361 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5036 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5037 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5038 ) ,
+ .pReset_W_in ( pResetWires[442] ) , .pReset_N_out ( pResetWires[444] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5039 ) ,
+ .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( p2361 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5040 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p1755 ) ,
+ .prog_clk_1_S_in ( p2247 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5041 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5042 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5043 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5044 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[75] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5045 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5046 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5047 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5048 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[126] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5049 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5050 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[75] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5051 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5052 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5053 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[80] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5054 ) , .clk_1_N_in ( p1755 ) ,
+ .clk_1_S_in ( p686 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5055 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5056 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5057 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5058 ) ,
+ .clk_2_S_in ( clk_3_wires[75] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5059 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5060 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5061 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5062 ) ,
+ .clk_2_E_out ( clk_2_wires[126] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5063 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5064 ) ,
+ .clk_3_S_in ( clk_3_wires[75] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5065 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5066 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5067 ) ,
+ .clk_3_N_out ( clk_3_wires[80] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5068 ) ) ;
+sb_1__1_ sb_10__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5069 } ) ,
+ .chany_top_in ( cby_1__1__117_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__118_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__116_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__107_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__118_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__107_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__107_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__107_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p2480 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5070 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5071 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5072 ) ,
+ .pReset_W_in ( pResetWires[491] ) , .pReset_N_out ( pResetWires[493] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5073 ) ,
+ .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( p2998 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5074 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p1813 ) ,
+ .prog_clk_1_S_in ( p325 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5075 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5076 ) ,
+ .prog_clk_2_N_in ( p1887 ) , .prog_clk_2_E_in ( p668 ) ,
+ .prog_clk_2_S_in ( p2885 ) , .prog_clk_2_W_in ( p595 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5077 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5078 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5079 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5080 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5081 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5082 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[81] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5083 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5084 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5085 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[84] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_1_N_in ( p1813 ) ,
+ .clk_1_S_in ( p830 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5087 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5088 ) , .clk_2_N_in ( p1887 ) ,
+ .clk_2_E_in ( p225 ) , .clk_2_S_in ( p1421 ) , .clk_2_W_in ( p224 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5089 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5090 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5091 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5092 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5093 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5094 ) ,
+ .clk_3_S_in ( clk_3_wires[81] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5095 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5096 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5097 ) ,
+ .clk_3_N_out ( clk_3_wires[84] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5098 ) ) ;
+sb_1__1_ sb_10__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5099 } ) ,
+ .chany_top_in ( cby_1__1__118_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__119_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__117_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__108_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__119_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__108_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__108_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__108_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p2970 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5100 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5101 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5102 ) ,
+ .pReset_W_in ( pResetWires[540] ) , .pReset_N_out ( pResetWires[542] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5103 ) ,
+ .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( p3197 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5104 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p1545 ) ,
+ .prog_clk_1_S_in ( p811 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5105 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5106 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5107 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5108 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[85] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5109 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5110 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5111 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5112 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1531 ) ,
+ .prog_clk_3_E_in ( p1279 ) , .prog_clk_3_S_in ( p3161 ) ,
+ .prog_clk_3_N_in ( p414 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5113 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5114 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5115 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5116 ) , .clk_1_N_in ( p1545 ) ,
+ .clk_1_S_in ( p292 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5117 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5118 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5119 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5120 ) ,
+ .clk_2_S_in ( clk_3_wires[85] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5121 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5122 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5123 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5124 ) ,
+ .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1531 ) ,
+ .clk_3_E_in ( p409 ) , .clk_3_S_in ( p1716 ) , .clk_3_N_in ( p1293 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5125 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5126 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5127 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5128 ) ) ;
+sb_1__1_ sb_10__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5129 } ) ,
+ .chany_top_in ( cby_1__1__119_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__120_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__118_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__109_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__120_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__109_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__109_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__109_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p2078 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5130 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5131 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5132 ) ,
+ .pReset_W_in ( pResetWires[589] ) , .pReset_N_out ( pResetWires[591] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5133 ) ,
+ .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( p3093 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5134 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p2165 ) ,
+ .prog_clk_1_S_in ( p30 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5135 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5136 ) ,
+ .prog_clk_2_N_in ( p3104 ) , .prog_clk_2_E_in ( p324 ) ,
+ .prog_clk_2_S_in ( p660 ) , .prog_clk_2_W_in ( p103 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5137 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5138 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5139 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5140 ) ,
+ .prog_clk_3_W_in ( p3530 ) , .prog_clk_3_E_in ( p74 ) ,
+ .prog_clk_3_S_in ( p3058 ) , .prog_clk_3_N_in ( p3030 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5141 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5142 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5143 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_1_N_in ( p2165 ) ,
+ .clk_1_S_in ( p943 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5145 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , .clk_2_N_in ( p2367 ) ,
+ .clk_2_E_in ( p650 ) , .clk_2_S_in ( p564 ) , .clk_2_W_in ( p3521 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5147 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5148 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5149 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , .clk_3_W_in ( p3196 ) ,
+ .clk_3_E_in ( p1024 ) , .clk_3_S_in ( p697 ) , .clk_3_N_in ( p2322 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5151 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5152 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5153 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5154 ) ) ;
+sb_1__1_ sb_11__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5155 } ) ,
+ .chany_top_in ( cby_1__1__121_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__121_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__120_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__110_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__121_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__110_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__110_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__110_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p3408 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5156 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5157 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5158 ) ,
+ .pReset_W_in ( pResetWires[103] ) , .pReset_N_out ( pResetWires[105] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5159 ) ,
+ .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( p3370 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5160 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[410] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[116] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5161 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[211] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p2607 ) ,
+ .prog_clk_2_E_in ( p756 ) , .prog_clk_2_S_in ( p1045 ) ,
+ .prog_clk_2_W_in ( p4 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5162 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5163 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5164 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5165 ) ,
+ .prog_clk_3_W_in ( p2776 ) , .prog_clk_3_E_in ( p919 ) ,
+ .prog_clk_3_S_in ( p3394 ) , .prog_clk_3_N_in ( p2530 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5166 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5167 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5168 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5169 ) ,
+ .clk_1_N_in ( clk_2_wires[116] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5170 ) ,
+ .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) ,
+ .clk_2_N_in ( p3275 ) , .clk_2_E_in ( p1030 ) , .clk_2_S_in ( p378 ) ,
+ .clk_2_W_in ( p3248 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5171 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5172 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5173 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5174 ) , .clk_3_W_in ( p3297 ) ,
+ .clk_3_E_in ( p305 ) , .clk_3_S_in ( p1199 ) , .clk_3_N_in ( p3229 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5175 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5176 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5177 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5178 ) ) ;
+sb_1__1_ sb_11__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5179 } ) ,
+ .chany_top_in ( cby_1__1__122_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__122_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__121_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__111_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__122_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__111_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__111_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__111_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p2837 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5180 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5181 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5182 ) ,
+ .pReset_W_in ( pResetWires[152] ) , .pReset_N_out ( pResetWires[154] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5183 ) ,
+ .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( p3555 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5184 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p1580 ) ,
+ .prog_clk_1_S_in ( p606 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5185 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5186 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5187 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5188 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5189 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[113] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5190 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[115] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5191 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5192 ) ,
+ .prog_clk_3_W_in ( p2468 ) , .prog_clk_3_E_in ( p344 ) ,
+ .prog_clk_3_S_in ( p3551 ) , .prog_clk_3_N_in ( p160 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5193 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5194 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5195 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5196 ) , .clk_1_N_in ( p1580 ) ,
+ .clk_1_S_in ( p605 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5197 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5198 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5199 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5200 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5201 ) ,
+ .clk_2_W_in ( clk_2_wires[113] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5202 ) ,
+ .clk_2_S_out ( clk_2_wires[115] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5203 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5204 ) , .clk_3_W_in ( p2468 ) ,
+ .clk_3_E_in ( p1001 ) , .clk_3_S_in ( p380 ) , .clk_3_N_in ( p1267 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5205 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5206 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5207 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5208 ) ) ;
+sb_1__1_ sb_11__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5209 } ) ,
+ .chany_top_in ( cby_1__1__123_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__123_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__122_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__112_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__123_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__112_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__112_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__112_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p3205 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5210 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5211 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5212 ) ,
+ .pReset_W_in ( pResetWires[201] ) , .pReset_N_out ( pResetWires[203] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5213 ) ,
+ .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( p1401 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5214 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[416] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[123] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5215 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[218] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3365 ) ,
+ .prog_clk_2_E_in ( p469 ) , .prog_clk_2_S_in ( p1113 ) ,
+ .prog_clk_2_W_in ( p359 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5216 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5217 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5218 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5219 ) ,
+ .prog_clk_3_W_in ( p2641 ) , .prog_clk_3_E_in ( p132 ) ,
+ .prog_clk_3_S_in ( p3154 ) , .prog_clk_3_N_in ( p3335 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5220 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5221 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5222 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5223 ) ,
+ .clk_1_N_in ( clk_2_wires[123] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5224 ) ,
+ .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) ,
+ .clk_2_N_in ( p3558 ) , .clk_2_E_in ( p743 ) , .clk_2_S_in ( p918 ) ,
+ .clk_2_W_in ( p3056 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5225 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5226 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5227 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , .clk_3_W_in ( p3090 ) ,
+ .clk_3_E_in ( p1087 ) , .clk_3_S_in ( p337 ) , .clk_3_N_in ( p3553 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5229 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5230 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5231 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5232 ) ) ;
+sb_1__1_ sb_11__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5233 } ) ,
+ .chany_top_in ( cby_1__1__124_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__124_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__123_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__113_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__124_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__113_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__113_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__113_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p3529 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5234 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5235 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5236 ) ,
+ .pReset_W_in ( pResetWires[250] ) , .pReset_N_out ( pResetWires[252] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5237 ) ,
+ .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( p3300 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5238 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p1835 ) ,
+ .prog_clk_1_S_in ( p896 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5239 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5240 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5241 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5242 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5243 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[118] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5244 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[122] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[120] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5245 ) ,
+ .prog_clk_3_W_in ( p1612 ) , .prog_clk_3_E_in ( p846 ) ,
+ .prog_clk_3_S_in ( p3519 ) , .prog_clk_3_N_in ( p1686 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5246 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5247 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5248 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_N_in ( p1835 ) ,
+ .clk_1_S_in ( p463 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5250 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5251 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5252 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5253 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5254 ) ,
+ .clk_2_W_in ( clk_2_wires[118] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5255 ) ,
+ .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5256 ) , .clk_3_W_in ( p1612 ) ,
+ .clk_3_E_in ( p453 ) , .clk_3_S_in ( p186 ) , .clk_3_N_in ( p1702 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5257 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5258 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5259 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5260 ) ) ;
+sb_1__1_ sb_11__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5261 } ) ,
+ .chany_top_in ( cby_1__1__125_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__125_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__124_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__114_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__125_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__114_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__114_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__114_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p2983 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5262 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5263 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5264 ) ,
+ .pReset_W_in ( pResetWires[299] ) , .pReset_N_out ( pResetWires[301] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5265 ) ,
+ .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( p3559 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5266 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[422] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5267 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[121] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[225] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p3268 ) ,
+ .prog_clk_2_E_in ( p779 ) , .prog_clk_2_S_in ( p1011 ) ,
+ .prog_clk_2_W_in ( p222 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5268 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5269 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5270 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5271 ) ,
+ .prog_clk_3_W_in ( p2680 ) , .prog_clk_3_E_in ( p257 ) ,
+ .prog_clk_3_S_in ( p3550 ) , .prog_clk_3_N_in ( p3238 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5272 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5273 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5274 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5275 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5276 ) ,
+ .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) ,
+ .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p2971 ) ,
+ .clk_2_E_in ( p1107 ) , .clk_2_S_in ( p940 ) , .clk_2_W_in ( p2546 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5277 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5278 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5279 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_W_in ( p2434 ) ,
+ .clk_3_E_in ( p487 ) , .clk_3_S_in ( p113 ) , .clk_3_N_in ( p2875 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5281 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5282 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5283 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5284 ) ) ;
+sb_1__1_ sb_11__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5285 } ) ,
+ .chany_top_in ( cby_1__1__126_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__126_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__125_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__115_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__126_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__115_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__115_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__115_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2617 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5286 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5287 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5288 ) ,
+ .pReset_W_in ( pResetWires[348] ) , .pReset_N_out ( pResetWires[350] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5289 ) ,
+ .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( p3184 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5290 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p1200 ) ,
+ .prog_clk_1_S_in ( p95 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5291 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5292 ) ,
+ .prog_clk_2_N_in ( p3462 ) , .prog_clk_2_E_in ( p249 ) ,
+ .prog_clk_2_S_in ( p1061 ) , .prog_clk_2_W_in ( p489 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5293 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5294 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5295 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5296 ) ,
+ .prog_clk_3_W_in ( p2467 ) , .prog_clk_3_E_in ( p1003 ) ,
+ .prog_clk_3_S_in ( p3144 ) , .prog_clk_3_N_in ( p3426 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5297 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5298 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5299 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_1_N_in ( p1200 ) ,
+ .clk_1_S_in ( p594 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5301 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5302 ) , .clk_2_N_in ( p2600 ) ,
+ .clk_2_E_in ( p1092 ) , .clk_2_S_in ( p688 ) , .clk_2_W_in ( p2894 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5303 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5304 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5305 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , .clk_3_W_in ( p2991 ) ,
+ .clk_3_E_in ( p640 ) , .clk_3_S_in ( p1195 ) , .clk_3_N_in ( p2524 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5307 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5308 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5309 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5310 ) ) ;
+sb_1__1_ sb_11__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5311 } ) ,
+ .chany_top_in ( cby_1__1__127_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__127_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__126_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__116_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__127_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__116_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__116_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__116_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p3005 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5312 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5313 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5314 ) ,
+ .pReset_W_in ( pResetWires[397] ) , .pReset_N_out ( pResetWires[399] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5315 ) ,
+ .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( p3458 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5316 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[428] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[130] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5317 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[232] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3282 ) ,
+ .prog_clk_2_E_in ( p933 ) , .prog_clk_2_S_in ( p978 ) ,
+ .prog_clk_2_W_in ( p298 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5318 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5319 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5320 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5321 ) ,
+ .prog_clk_3_W_in ( p3107 ) , .prog_clk_3_E_in ( p429 ) ,
+ .prog_clk_3_S_in ( p3437 ) , .prog_clk_3_N_in ( p3244 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5322 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5323 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5324 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5325 ) ,
+ .clk_1_N_in ( clk_2_wires[130] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5326 ) ,
+ .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) ,
+ .clk_2_N_in ( p2614 ) , .clk_2_E_in ( p724 ) , .clk_2_S_in ( p1010 ) ,
+ .clk_2_W_in ( p3024 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5327 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5328 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5329 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_3_W_in ( p2984 ) ,
+ .clk_3_E_in ( p200 ) , .clk_3_S_in ( p102 ) , .clk_3_N_in ( p2533 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5331 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5332 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5333 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5334 ) ) ;
+sb_1__1_ sb_11__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5335 } ) ,
+ .chany_top_in ( cby_1__1__128_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__128_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__127_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__117_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__128_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__117_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__117_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__117_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p2676 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5336 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5337 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5338 ) ,
+ .pReset_W_in ( pResetWires[446] ) , .pReset_N_out ( pResetWires[448] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5339 ) ,
+ .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( p3265 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5340 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p1519 ) ,
+ .prog_clk_1_S_in ( p807 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5341 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5342 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5343 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5344 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5345 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[125] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5346 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[129] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[127] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5347 ) ,
+ .prog_clk_3_W_in ( p1548 ) , .prog_clk_3_E_in ( p238 ) ,
+ .prog_clk_3_S_in ( p3241 ) , .prog_clk_3_N_in ( p1341 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5348 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5349 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5350 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5351 ) , .clk_1_N_in ( p1519 ) ,
+ .clk_1_S_in ( p78 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5352 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5353 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5354 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5355 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5356 ) ,
+ .clk_2_W_in ( clk_2_wires[125] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5357 ) ,
+ .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5358 ) , .clk_3_W_in ( p1548 ) ,
+ .clk_3_E_in ( p577 ) , .clk_3_S_in ( p461 ) , .clk_3_N_in ( p1273 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5359 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5360 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5361 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5362 ) ) ;
+sb_1__1_ sb_11__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5363 } ) ,
+ .chany_top_in ( cby_1__1__129_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__129_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__128_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__118_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__129_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__118_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__118_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__118_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p3195 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5364 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5365 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5366 ) ,
+ .pReset_W_in ( pResetWires[495] ) , .pReset_N_out ( pResetWires[497] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5367 ) ,
+ .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( p2857 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5368 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[434] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5369 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[128] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[239] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3411 ) ,
+ .prog_clk_2_E_in ( p67 ) , .prog_clk_2_S_in ( p1009 ) ,
+ .prog_clk_2_W_in ( p196 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5370 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5371 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5372 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5373 ) ,
+ .prog_clk_3_W_in ( p2826 ) , .prog_clk_3_E_in ( p757 ) ,
+ .prog_clk_3_S_in ( p3148 ) , .prog_clk_3_N_in ( p3396 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5374 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5375 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5376 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5377 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5378 ) ,
+ .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) ,
+ .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p3565 ) ,
+ .clk_2_E_in ( p430 ) , .clk_2_S_in ( p981 ) , .clk_2_W_in ( p2892 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5379 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5380 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5381 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , .clk_3_W_in ( p2954 ) ,
+ .clk_3_E_in ( p1088 ) , .clk_3_S_in ( p673 ) , .clk_3_N_in ( p3561 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5383 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5384 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5385 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5386 ) ) ;
+sb_1__1_ sb_11__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5387 } ) ,
+ .chany_top_in ( cby_1__1__130_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__130_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__129_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__119_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__130_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__119_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__119_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__119_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p3482 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5388 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5389 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5390 ) ,
+ .pReset_W_in ( pResetWires[544] ) , .pReset_N_out ( pResetWires[546] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5391 ) ,
+ .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( p3412 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5392 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p1215 ) ,
+ .prog_clk_1_S_in ( p951 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5393 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5394 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5395 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5396 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5397 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[132] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5398 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5399 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[134] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5400 ) ,
+ .prog_clk_3_W_in ( p2106 ) , .prog_clk_3_E_in ( p278 ) ,
+ .prog_clk_3_S_in ( p3467 ) , .prog_clk_3_N_in ( p1627 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5401 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5402 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5403 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , .clk_1_N_in ( p1215 ) ,
+ .clk_1_S_in ( p435 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5405 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5406 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5407 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5408 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5409 ) ,
+ .clk_2_W_in ( clk_2_wires[132] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5410 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5411 ) ,
+ .clk_2_N_out ( clk_2_wires[134] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5412 ) , .clk_3_W_in ( p2106 ) ,
+ .clk_3_E_in ( p740 ) , .clk_3_S_in ( p343 ) , .clk_3_N_in ( p690 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5413 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5414 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5415 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5416 ) ) ;
+sb_1__1_ sb_11__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5417 } ) ,
+ .chany_top_in ( cby_1__1__131_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__131_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__130_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__120_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__131_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__120_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__120_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__120_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p3189 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5418 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5419 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5420 ) ,
+ .pReset_W_in ( pResetWires[593] ) , .pReset_N_out ( pResetWires[595] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5421 ) ,
+ .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( p3402 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5422 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[440] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5423 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[135] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[246] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p2959 ) ,
+ .prog_clk_2_E_in ( p129 ) , .prog_clk_2_S_in ( p938 ) ,
+ .prog_clk_2_W_in ( p874 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5424 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5425 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5426 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5427 ) ,
+ .prog_clk_3_W_in ( p3175 ) , .prog_clk_3_E_in ( p462 ) ,
+ .prog_clk_3_S_in ( p3371 ) , .prog_clk_3_N_in ( p2930 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5428 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5429 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5430 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5431 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5432 ) ,
+ .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) ,
+ .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p3414 ) ,
+ .clk_2_E_in ( p471 ) , .clk_2_S_in ( p58 ) , .clk_2_W_in ( p3146 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5433 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5434 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5435 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5436 ) , .clk_3_W_in ( p3193 ) ,
+ .clk_3_E_in ( p1029 ) , .clk_3_S_in ( p1139 ) , .clk_3_N_in ( p3389 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5437 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5438 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5439 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5440 ) ) ;
+sb_1__2_ sb_1__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5441 } ) ,
+ .chanx_right_in ( cbx_1__12__1_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__11_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__0_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_1_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1095 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5442 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5443 ) ,
+ .pReset_E_in ( pResetWires[604] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5444 ) ,
+ .pReset_W_out ( pResetWires[601] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5445 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[60] ) ) ;
+sb_1__2_ sb_2__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5446 } ) ,
+ .chanx_right_in ( cbx_1__12__2_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__23_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__1_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_2_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__1_ccff_tail ) , .SC_IN_BOT ( scff_Wires[52] ) ,
+ .SC_OUT_BOT ( scff_Wires[53] ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5447 ) ,
+ .pReset_E_in ( pResetWires[607] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5448 ) ,
+ .pReset_W_out ( pResetWires[605] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5449 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[100] ) ) ;
+sb_1__2_ sb_3__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5450 } ) ,
+ .chanx_right_in ( cbx_1__12__3_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__35_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__2_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_3_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1809 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5451 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5452 ) ,
+ .pReset_E_in ( pResetWires[610] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5453 ) ,
+ .pReset_W_out ( pResetWires[608] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5454 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[138] ) ) ;
+sb_1__2_ sb_4__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5455 } ) ,
+ .chanx_right_in ( cbx_1__12__4_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__47_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__3_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_4_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__3_ccff_tail ) , .SC_IN_BOT ( scff_Wires[105] ) ,
+ .SC_OUT_BOT ( scff_Wires[106] ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5456 ) ,
+ .pReset_E_in ( pResetWires[613] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5457 ) ,
+ .pReset_W_out ( pResetWires[611] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5458 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[176] ) ) ;
+sb_1__2_ sb_5__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5459 } ) ,
+ .chanx_right_in ( cbx_1__12__5_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__59_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__4_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_5_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1251 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5460 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5461 ) ,
+ .pReset_E_in ( pResetWires[616] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5462 ) ,
+ .pReset_W_out ( pResetWires[614] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5463 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[214] ) ) ;
+sb_1__2_ sb_6__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5464 } ) ,
+ .chanx_right_in ( cbx_1__12__6_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__71_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__5_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_6_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__5_ccff_tail ) , .SC_IN_BOT ( scff_Wires[158] ) ,
+ .SC_OUT_BOT ( scff_Wires[159] ) , .pReset_S_in ( pResetWires[24] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5465 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5466 ) ,
+ .pReset_W_out ( pResetWires[617] ) , .pReset_E_out ( pResetWires[619] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[252] ) ) ;
+sb_1__2_ sb_7__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5467 } ) ,
+ .chanx_right_in ( cbx_1__12__7_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__83_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__6_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_7_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1180 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5468 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5469 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5470 ) ,
+ .pReset_W_in ( pResetWires[620] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5471 ) ,
+ .pReset_E_out ( pResetWires[622] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[290] ) ) ;
+sb_1__2_ sb_8__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5472 } ) ,
+ .chanx_right_in ( cbx_1__12__8_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__95_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__7_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_8_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__7_ccff_tail ) , .SC_IN_BOT ( scff_Wires[211] ) ,
+ .SC_OUT_BOT ( scff_Wires[212] ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5473 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5474 ) ,
+ .pReset_W_in ( pResetWires[623] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5475 ) ,
+ .pReset_E_out ( pResetWires[625] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[328] ) ) ;
+sb_1__2_ sb_9__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5476 } ) ,
+ .chanx_right_in ( cbx_1__12__9_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__107_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__8_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_9_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p823 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5477 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5478 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5479 ) ,
+ .pReset_W_in ( pResetWires[626] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5480 ) ,
+ .pReset_E_out ( pResetWires[628] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[366] ) ) ;
+sb_1__2_ sb_10__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5481 } ) ,
+ .chanx_right_in ( cbx_1__12__10_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__119_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__9_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_10_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__9_ccff_tail ) , .SC_IN_BOT ( scff_Wires[264] ) ,
+ .SC_OUT_BOT ( scff_Wires[265] ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5482 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5483 ) ,
+ .pReset_W_in ( pResetWires[629] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5484 ) ,
+ .pReset_E_out ( pResetWires[631] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[404] ) ) ;
+sb_1__2_ sb_11__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5485 } ) ,
+ .chanx_right_in ( cbx_1__12__11_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__131_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__10_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_11_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1816 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5486 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5487 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5488 ) ,
+ .pReset_W_in ( pResetWires[632] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5489 ) ,
+ .pReset_E_out ( pResetWires[634] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[442] ) ) ;
+sb_2__0_ sb_12__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5490 } ) ,
+ .chany_top_in ( cby_12__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) ,
+ .chanx_left_in ( cbx_1__0__11_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_right_11_ccff_tail ) ,
+ .chany_top_out ( sb_12__0__0_chany_top_out ) ,
+ .chanx_left_out ( sb_12__0__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__0__0_ccff_tail ) , .pReset_W_in ( pResetWires[59] ) ,
+ .pReset_N_out ( pResetWires[60] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[445] ) ) ;
+sb_2__1_ sb_12__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5491 } ) ,
+ .chany_top_in ( cby_12__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__0_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__121_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_10_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__0_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__0_ccff_tail ) , .pReset_W_in ( pResetWires[107] ) ,
+ .pReset_N_out ( pResetWires[109] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[448] ) ) ;
+sb_2__1_ sb_12__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5492 } ) ,
+ .chany_top_in ( cby_12__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__1_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__122_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_9_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__1_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__1_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__1_ccff_tail ) , .pReset_W_in ( pResetWires[156] ) ,
+ .pReset_N_out ( pResetWires[158] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[451] ) ) ;
+sb_2__1_ sb_12__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5493 } ) ,
+ .chany_top_in ( cby_12__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__2_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__123_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_8_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__2_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__2_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__2_ccff_tail ) , .pReset_W_in ( pResetWires[205] ) ,
+ .pReset_N_out ( pResetWires[207] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[454] ) ) ;
+sb_2__1_ sb_12__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5494 } ) ,
+ .chany_top_in ( cby_12__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__3_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__124_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_7_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__3_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__3_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__3_ccff_tail ) , .pReset_W_in ( pResetWires[254] ) ,
+ .pReset_N_out ( pResetWires[256] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[457] ) ) ;
+sb_2__1_ sb_12__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5495 } ) ,
+ .chany_top_in ( cby_12__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__4_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__125_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_6_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__4_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__4_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__4_ccff_tail ) , .pReset_W_in ( pResetWires[303] ) ,
+ .pReset_N_out ( pResetWires[305] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[460] ) ) ;
+sb_2__1_ sb_12__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5496 } ) ,
+ .chany_top_in ( cby_12__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__5_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__126_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_5_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__5_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__5_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__5_ccff_tail ) , .pReset_W_in ( pResetWires[352] ) ,
+ .pReset_N_out ( pResetWires[354] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[463] ) ) ;
+sb_2__1_ sb_12__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5497 } ) ,
+ .chany_top_in ( cby_12__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__6_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__127_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_4_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__6_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__6_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__6_ccff_tail ) , .pReset_W_in ( pResetWires[401] ) ,
+ .pReset_N_out ( pResetWires[403] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[466] ) ) ;
+sb_2__1_ sb_12__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5498 } ) ,
+ .chany_top_in ( cby_12__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__7_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__128_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_3_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__7_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__7_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__7_ccff_tail ) , .pReset_W_in ( pResetWires[450] ) ,
+ .pReset_N_out ( pResetWires[452] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[469] ) ) ;
+sb_2__1_ sb_12__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5499 } ) ,
+ .chany_top_in ( cby_12__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__8_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__129_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_2_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__8_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__8_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__8_ccff_tail ) , .pReset_W_in ( pResetWires[499] ) ,
+ .pReset_N_out ( pResetWires[501] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[472] ) ) ;
+sb_2__1_ sb_12__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5500 } ) ,
+ .chany_top_in ( cby_12__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__9_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__130_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_1_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__9_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__9_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__9_ccff_tail ) , .pReset_W_in ( pResetWires[548] ) ,
+ .pReset_N_out ( pResetWires[550] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[475] ) ) ;
+sb_2__1_ sb_12__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5501 } ) ,
+ .chany_top_in ( cby_12__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__10_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__131_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_0_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__10_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__10_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__10_ccff_tail ) ,
+ .pReset_W_in ( pResetWires[597] ) , .pReset_N_out ( pResetWires[599] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[478] ) ) ;
+sb_2__2_ sb_12__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5502 } ) ,
+ .chany_bottom_in ( cby_12__1__11_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__11_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( ccff_head ) ,
+ .chany_bottom_out ( sb_12__12__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__12__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__12__0_ccff_tail ) , .SC_IN_BOT ( scff_Wires[317] ) ,
+ .SC_OUT_BOT ( sc_tail ) , .pReset_W_in ( pResetWires[635] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[480] ) ) ;
+cbx_1__0_ cbx_1__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5503 } ) ,
+ .chanx_left_in ( sb_0__0__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__0_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123:131] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123:131] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123:131] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) ,
+ .SC_IN_BOT ( p1561 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5504 ) ,
+ .pReset_E_in ( pResetWires[26] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5505 ) ,
+ .pReset_W_out ( pResetWires[25] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5506 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[0] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[5] ) ) ;
+cbx_1__0_ cbx_2__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5507 } ) ,
+ .chanx_left_in ( sb_1__0__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__1_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114:122] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114:122] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114:122] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1191 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5508 ) ,
+ .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) ,
+ .pReset_E_in ( pResetWires[29] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5509 ) ,
+ .pReset_W_out ( pResetWires[28] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5510 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[63] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5511 ) ) ;
+cbx_1__0_ cbx_3__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5512 } ) ,
+ .chanx_left_in ( sb_1__0__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__2_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105:113] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105:113] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105:113] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) ,
+ .SC_IN_BOT ( p1508 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5513 ) ,
+ .pReset_E_in ( pResetWires[32] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5514 ) ,
+ .pReset_W_out ( pResetWires[31] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5515 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[101] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5516 ) ) ;
+cbx_1__0_ cbx_4__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5517 } ) ,
+ .chanx_left_in ( sb_1__0__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__3_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:104] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:104] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:104] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1067 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5518 ) ,
+ .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) ,
+ .pReset_E_in ( pResetWires[35] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5519 ) ,
+ .pReset_W_out ( pResetWires[34] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5520 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[139] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5521 ) ) ;
+cbx_1__0_ cbx_5__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5522 } ) ,
+ .chanx_left_in ( sb_1__0__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__4_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87:95] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87:95] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87:95] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) ,
+ .SC_IN_BOT ( p1518 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5523 ) ,
+ .pReset_E_in ( pResetWires[38] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5524 ) ,
+ .pReset_W_out ( pResetWires[37] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5525 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[177] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5526 ) ) ;
+cbx_1__0_ cbx_6__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5527 } ) ,
+ .chanx_left_in ( sb_1__0__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__5_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78:86] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78:86] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78:86] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1490 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5528 ) ,
+ .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) ,
+ .pReset_E_in ( pResetWires[41] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5529 ) ,
+ .pReset_W_out ( pResetWires[40] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5530 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[215] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5531 ) ) ;
+cbx_1__0_ cbx_7__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5532 } ) ,
+ .chanx_left_in ( sb_1__0__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__6_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69:77] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69:77] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69:77] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) ,
+ .SC_IN_BOT ( p1472 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5533 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5534 ) ,
+ .pReset_W_in ( pResetWires[43] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5535 ) ,
+ .pReset_E_out ( pResetWires[44] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[253] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5536 ) ) ;
+cbx_1__0_ cbx_8__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5537 } ) ,
+ .chanx_left_in ( sb_1__0__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__7_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:68] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:68] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:68] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1556 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5538 ) ,
+ .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5539 ) ,
+ .pReset_W_in ( pResetWires[46] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5540 ) ,
+ .pReset_E_out ( pResetWires[47] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[291] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5541 ) ) ;
+cbx_1__0_ cbx_9__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5542 } ) ,
+ .chanx_left_in ( sb_1__0__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__8_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51:59] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51:59] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51:59] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) ,
+ .SC_IN_BOT ( p1395 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5543 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5544 ) ,
+ .pReset_W_in ( pResetWires[49] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5545 ) ,
+ .pReset_E_out ( pResetWires[50] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[329] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5546 ) ) ;
+cbx_1__0_ cbx_10__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5547 } ) ,
+ .chanx_left_in ( sb_1__0__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__9_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42:50] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42:50] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42:50] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p949 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5548 ) ,
+ .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5549 ) ,
+ .pReset_W_in ( pResetWires[52] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5550 ) ,
+ .pReset_E_out ( pResetWires[53] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[367] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5551 ) ) ;
+cbx_1__0_ cbx_11__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5552 } ) ,
+ .chanx_left_in ( sb_1__0__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__10_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33:41] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33:41] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33:41] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) ,
+ .SC_IN_BOT ( p1404 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5553 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5554 ) ,
+ .pReset_W_in ( pResetWires[55] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5555 ) ,
+ .pReset_E_out ( pResetWires[56] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[405] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5556 ) ) ;
+cbx_1__0_ cbx_12__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5557 } ) ,
+ .chanx_left_in ( sb_1__0__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__0__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__0__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__11_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:32] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:32] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:32] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p880 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5558 ) ,
+ .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5559 ) ,
+ .pReset_W_in ( pResetWires[58] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5560 ) ,
+ .pReset_E_out ( pResetWires[59] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[443] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5561 ) ) ;
+cbx_1__1_ cbx_1__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5562 } ) ,
+ .chanx_left_in ( sb_0__1__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__0_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) ,
+ .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p1423 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5563 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[0] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[0] ) ,
+ .pReset_E_in ( pResetWires[62] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5564 ) ,
+ .pReset_W_out ( pResetWires[61] ) , .pReset_S_out ( pResetWires[63] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5565 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[6] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[4] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5566 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[2] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[3] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p2661 ) ,
+ .prog_clk_2_W_in ( p637 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5567 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5568 ) ,
+ .prog_clk_3_W_in ( p2663 ) , .prog_clk_3_E_in ( p1310 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5569 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5570 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5571 ) ,
+ .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) ,
+ .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p1482 ) ,
+ .clk_2_W_in ( p2552 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2663 ) ,
+ .clk_3_E_in ( p2583 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5575 ) ) ;
+cbx_1__1_ cbx_1__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5576 } ) ,
+ .chanx_left_in ( sb_0__1__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__1_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) ,
+ .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p1838 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5577 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[1] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[1] ) ,
+ .pReset_E_in ( pResetWires[111] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5578 ) ,
+ .pReset_W_out ( pResetWires[110] ) , .pReset_S_out ( pResetWires[112] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5579 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[11] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p1167 ) ,
+ .prog_clk_1_E_in ( p97 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5580 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5581 ) ,
+ .prog_clk_2_E_in ( p3357 ) , .prog_clk_2_W_in ( p508 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5582 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5583 ) ,
+ .prog_clk_3_W_in ( p1149 ) , .prog_clk_3_E_in ( p2549 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5584 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p1149 ) ,
+ .clk_1_E_in ( p1710 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2695 ) ,
+ .clk_2_W_in ( p1210 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p1149 ) ,
+ .clk_3_E_in ( p3325 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) ) ;
+cbx_1__1_ cbx_1__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5592 } ) ,
+ .chanx_left_in ( sb_0__1__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__2_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) ,
+ .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1486 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5593 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[2] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[2] ) ,
+ .pReset_E_in ( pResetWires[160] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5594 ) ,
+ .pReset_W_out ( pResetWires[159] ) , .pReset_S_out ( pResetWires[161] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5595 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[16] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[15] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5596 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[9] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[10] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p3279 ) ,
+ .prog_clk_2_W_in ( p1089 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5597 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5598 ) ,
+ .prog_clk_3_W_in ( p2351 ) , .prog_clk_3_E_in ( p2053 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5599 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5600 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5601 ) ,
+ .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) ,
+ .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2132 ) ,
+ .clk_2_W_in ( p2321 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p2351 ) ,
+ .clk_3_E_in ( p3232 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5605 ) ) ;
+cbx_1__1_ cbx_1__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5606 } ) ,
+ .chanx_left_in ( sb_0__1__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__3_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) ,
+ .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1613 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5607 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[3] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[3] ) ,
+ .pReset_E_in ( pResetWires[209] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5608 ) ,
+ .pReset_W_out ( pResetWires[208] ) , .pReset_S_out ( pResetWires[210] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5609 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[21] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p1457 ) ,
+ .prog_clk_1_E_in ( p1117 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5610 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5611 ) ,
+ .prog_clk_2_E_in ( p2992 ) , .prog_clk_2_W_in ( p178 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5612 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5613 ) ,
+ .prog_clk_3_W_in ( p2828 ) , .prog_clk_3_E_in ( p1430 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5614 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_1_W_in ( p1823 ) ,
+ .clk_1_E_in ( p1296 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5616 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_2_E_in ( p1468 ) ,
+ .clk_2_W_in ( p2759 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p2828 ) ,
+ .clk_3_E_in ( p2897 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5621 ) ) ;
+cbx_1__1_ cbx_1__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5622 } ) ,
+ .chanx_left_in ( sb_0__1__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__4_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) ,
+ .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1165 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5623 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[4] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[4] ) ,
+ .pReset_E_in ( pResetWires[258] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5624 ) ,
+ .pReset_W_out ( pResetWires[257] ) , .pReset_S_out ( pResetWires[259] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5625 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[26] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[25] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5626 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[16] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[17] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p2411 ) ,
+ .prog_clk_2_W_in ( p565 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5627 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5628 ) ,
+ .prog_clk_3_W_in ( p2648 ) , .prog_clk_3_E_in ( p1659 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5629 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5630 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5631 ) ,
+ .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) ,
+ .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p1741 ) ,
+ .clk_2_W_in ( p2563 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p2648 ) ,
+ .clk_3_E_in ( p2345 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5635 ) ) ;
+cbx_1__1_ cbx_1__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5636 } ) ,
+ .chanx_left_in ( sb_0__1__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__5_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) ,
+ .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p2114 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5637 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[5] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[5] ) ,
+ .pReset_E_in ( pResetWires[307] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5638 ) ,
+ .pReset_W_out ( pResetWires[306] ) , .pReset_S_out ( pResetWires[308] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5639 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[31] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p1375 ) ,
+ .prog_clk_1_E_in ( p501 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5640 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5641 ) ,
+ .prog_clk_2_E_in ( p2685 ) , .prog_clk_2_W_in ( p474 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5642 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5643 ) ,
+ .prog_clk_3_W_in ( p2401 ) , .prog_clk_3_E_in ( p2275 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5644 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_1_W_in ( p2428 ) ,
+ .clk_1_E_in ( p1953 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5646 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_2_E_in ( p2357 ) ,
+ .clk_2_W_in ( p2314 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p2401 ) ,
+ .clk_3_E_in ( p2570 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5651 ) ) ;
+cbx_1__1_ cbx_1__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5652 } ) ,
+ .chanx_left_in ( sb_0__1__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__6_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) ,
+ .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1542 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5653 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[6] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[6] ) ,
+ .pReset_E_in ( pResetWires[356] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5654 ) ,
+ .pReset_W_out ( pResetWires[355] ) , .pReset_S_out ( pResetWires[357] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5655 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[36] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[35] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5656 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[23] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[24] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p3278 ) ,
+ .prog_clk_2_W_in ( p1175 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5657 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5658 ) ,
+ .prog_clk_3_W_in ( p1578 ) , .prog_clk_3_E_in ( p1748 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5659 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5660 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5661 ) ,
+ .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) ,
+ .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p1763 ) ,
+ .clk_2_W_in ( p1317 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p1578 ) ,
+ .clk_3_E_in ( p3258 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5665 ) ) ;
+cbx_1__1_ cbx_1__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5666 } ) ,
+ .chanx_left_in ( sb_0__1__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__7_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) ,
+ .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1589 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5667 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[7] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[7] ) ,
+ .pReset_E_in ( pResetWires[405] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5668 ) ,
+ .pReset_W_out ( pResetWires[404] ) , .pReset_S_out ( pResetWires[406] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5669 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[41] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1462 ) ,
+ .prog_clk_1_E_in ( p339 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5670 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5671 ) ,
+ .prog_clk_2_E_in ( p1148 ) , .prog_clk_2_W_in ( p713 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5672 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5673 ) ,
+ .prog_clk_3_W_in ( p1913 ) , .prog_clk_3_E_in ( p2031 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5674 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p1913 ) ,
+ .clk_1_E_in ( p1305 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_2_E_in ( p2148 ) ,
+ .clk_2_W_in ( p1667 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p1913 ) ,
+ .clk_3_E_in ( p509 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) ) ;
+cbx_1__1_ cbx_1__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5682 } ) ,
+ .chanx_left_in ( sb_0__1__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__8_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) ,
+ .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1606 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5683 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[8] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[8] ) ,
+ .pReset_E_in ( pResetWires[454] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5684 ) ,
+ .pReset_W_out ( pResetWires[453] ) , .pReset_S_out ( pResetWires[455] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5685 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[46] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[45] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5686 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[30] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[31] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p3011 ) ,
+ .prog_clk_2_W_in ( p570 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5687 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5688 ) ,
+ .prog_clk_3_W_in ( p1393 ) , .prog_clk_3_E_in ( p1669 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5689 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5690 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5691 ) ,
+ .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) ,
+ .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p1756 ) ,
+ .clk_2_W_in ( p1354 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p1393 ) ,
+ .clk_3_E_in ( p2900 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5695 ) ) ;
+cbx_1__1_ cbx_1__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5696 } ) ,
+ .chanx_left_in ( sb_0__1__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__9_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) ,
+ .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p1188 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5697 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[9] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[9] ) ,
+ .pReset_E_in ( pResetWires[503] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5698 ) ,
+ .pReset_W_out ( pResetWires[502] ) , .pReset_S_out ( pResetWires[504] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5699 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[51] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p1497 ) ,
+ .prog_clk_1_E_in ( p904 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5700 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5701 ) ,
+ .prog_clk_2_E_in ( p2596 ) , .prog_clk_2_W_in ( p967 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5702 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5703 ) ,
+ .prog_clk_3_W_in ( p1577 ) , .prog_clk_3_E_in ( p2051 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5704 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_1_W_in ( p1577 ) ,
+ .clk_1_E_in ( p374 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5706 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_2_E_in ( p2145 ) ,
+ .clk_2_W_in ( p1332 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p1577 ) ,
+ .clk_3_E_in ( p2539 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5711 ) ) ;
+cbx_1__1_ cbx_1__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5712 } ) ,
+ .chanx_left_in ( sb_0__1__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__10_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) ,
+ .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p485 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5713 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[10] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[10] ) ,
+ .pReset_E_in ( pResetWires[552] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5714 ) ,
+ .pReset_W_out ( pResetWires[551] ) , .pReset_S_out ( pResetWires[553] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5715 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[56] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[55] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5716 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[37] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[38] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p2222 ) ,
+ .prog_clk_2_W_in ( p473 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5717 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5718 ) ,
+ .prog_clk_3_W_in ( p2633 ) , .prog_clk_3_E_in ( p2311 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5719 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5720 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5721 ) ,
+ .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) ,
+ .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2418 ) ,
+ .clk_2_W_in ( p2541 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2633 ) ,
+ .clk_3_E_in ( p2074 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5725 ) ) ;
+cbx_1__1_ cbx_2__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5726 } ) ,
+ .chanx_left_in ( sb_1__1__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__11_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__11_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__11_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p1541 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5727 ) ,
+ .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[11] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[11] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[11] ) ,
+ .pReset_E_in ( pResetWires[67] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5728 ) ,
+ .pReset_W_out ( pResetWires[66] ) , .pReset_S_out ( pResetWires[68] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5729 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[66] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5730 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[1] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5731 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[5] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2939 ) ,
+ .prog_clk_2_W_in ( p710 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5732 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5733 ) ,
+ .prog_clk_3_W_in ( p1758 ) , .prog_clk_3_E_in ( p1346 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5734 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5735 ) ,
+ .clk_1_W_in ( clk_1_wires[1] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5736 ) ,
+ .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) ,
+ .clk_2_E_in ( p1407 ) , .clk_2_W_in ( p1658 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5737 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p1758 ) ,
+ .clk_3_E_in ( p2929 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) ) ;
+cbx_1__1_ cbx_2__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5741 } ) ,
+ .chanx_left_in ( sb_1__1__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__12_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__12_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__12_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__12_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p1886 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5742 ) ,
+ .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[12] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[12] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[12] ) ,
+ .pReset_E_in ( pResetWires[116] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5743 ) ,
+ .pReset_W_out ( pResetWires[115] ) , .pReset_S_out ( pResetWires[117] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5744 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[69] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5745 ) ,
+ .prog_clk_1_W_in ( p1484 ) , .prog_clk_1_E_in ( p417 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5746 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5747 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[2] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5748 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[1] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5749 ) ,
+ .prog_clk_3_W_in ( p1487 ) , .prog_clk_3_E_in ( p1349 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5750 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , .clk_1_W_in ( p1487 ) ,
+ .clk_1_E_in ( p1147 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5752 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5753 ) ,
+ .clk_2_E_in ( clk_2_wires[2] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5754 ) ,
+ .clk_2_W_out ( clk_2_wires[1] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1487 ) ,
+ .clk_3_E_in ( p1726 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5757 ) ) ;
+cbx_1__1_ cbx_2__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5758 } ) ,
+ .chanx_left_in ( sb_1__1__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__13_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__13_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__13_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__13_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1919 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5759 ) ,
+ .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[13] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[13] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[13] ) ,
+ .pReset_E_in ( pResetWires[165] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5760 ) ,
+ .pReset_W_out ( pResetWires[164] ) , .pReset_S_out ( pResetWires[166] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5761 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[72] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5762 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[8] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5763 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[12] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p2379 ) ,
+ .prog_clk_2_W_in ( p758 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5764 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5765 ) ,
+ .prog_clk_3_W_in ( p1944 ) , .prog_clk_3_E_in ( p2303 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5766 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5767 ) ,
+ .clk_1_W_in ( clk_1_wires[8] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5768 ) ,
+ .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) ,
+ .clk_2_E_in ( p2381 ) , .clk_2_W_in ( p1703 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5769 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p1944 ) ,
+ .clk_3_E_in ( p2342 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5772 ) ) ;
+cbx_1__1_ cbx_2__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5773 } ) ,
+ .chanx_left_in ( sb_1__1__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__14_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__14_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__14_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__14_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p2127 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5774 ) ,
+ .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[14] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[14] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[14] ) ,
+ .pReset_E_in ( pResetWires[214] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5775 ) ,
+ .pReset_W_out ( pResetWires[213] ) , .pReset_S_out ( pResetWires[215] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5776 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[75] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5777 ) ,
+ .prog_clk_1_W_in ( p1428 ) , .prog_clk_1_E_in ( p990 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5778 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5779 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[7] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5780 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[6] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5781 ) ,
+ .prog_clk_3_W_in ( p1429 ) , .prog_clk_3_E_in ( p464 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5782 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) , .clk_1_W_in ( p1429 ) ,
+ .clk_1_E_in ( p355 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5784 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5785 ) ,
+ .clk_2_E_in ( clk_2_wires[7] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5786 ) ,
+ .clk_2_W_out ( clk_2_wires[6] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1429 ) ,
+ .clk_3_E_in ( p2009 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5789 ) ) ;
+cbx_1__1_ cbx_2__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5790 } ) ,
+ .chanx_left_in ( sb_1__1__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__15_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__15_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__15_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__15_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p1757 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5791 ) ,
+ .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[15] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[15] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[15] ) ,
+ .pReset_E_in ( pResetWires[263] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5792 ) ,
+ .pReset_W_out ( pResetWires[262] ) , .pReset_S_out ( pResetWires[264] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5793 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[78] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5794 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[15] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5795 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[19] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p3187 ) ,
+ .prog_clk_2_W_in ( p623 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5796 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5797 ) ,
+ .prog_clk_3_W_in ( p2476 ) , .prog_clk_3_E_in ( p2013 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5798 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5799 ) ,
+ .clk_1_W_in ( clk_1_wires[15] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5800 ) ,
+ .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) ,
+ .clk_2_E_in ( p2190 ) , .clk_2_W_in ( p2320 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5801 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p2476 ) ,
+ .clk_3_E_in ( p3145 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) ) ;
+cbx_1__1_ cbx_2__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5805 } ) ,
+ .chanx_left_in ( sb_1__1__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__16_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__16_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__16_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__16_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p1883 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5806 ) ,
+ .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[16] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[16] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[16] ) ,
+ .pReset_E_in ( pResetWires[312] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5807 ) ,
+ .pReset_W_out ( pResetWires[311] ) , .pReset_S_out ( pResetWires[313] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5808 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[81] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5809 ) ,
+ .prog_clk_1_W_in ( p1914 ) , .prog_clk_1_E_in ( p1257 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5810 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5811 ) ,
+ .prog_clk_2_E_in ( p2413 ) , .prog_clk_2_W_in ( p505 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5812 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5813 ) ,
+ .prog_clk_3_W_in ( p2781 ) , .prog_clk_3_E_in ( p2065 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5814 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_1_W_in ( p2395 ) ,
+ .clk_1_E_in ( p1525 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5816 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_2_E_in ( p2167 ) ,
+ .clk_2_W_in ( p2755 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p2811 ) ,
+ .clk_3_E_in ( p2317 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5821 ) ) ;
+cbx_1__1_ cbx_2__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5822 } ) ,
+ .chanx_left_in ( sb_1__1__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__17_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__17_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__17_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__17_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p1451 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5823 ) ,
+ .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[17] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[17] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[17] ) ,
+ .pReset_E_in ( pResetWires[361] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5824 ) ,
+ .pReset_W_out ( pResetWires[360] ) , .pReset_S_out ( pResetWires[362] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5825 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[84] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5826 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[22] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5827 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[26] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p2834 ) ,
+ .prog_clk_2_W_in ( p813 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5828 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5829 ) ,
+ .prog_clk_3_W_in ( p2815 ) , .prog_clk_3_E_in ( p1681 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5830 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5831 ) ,
+ .clk_1_W_in ( clk_1_wires[22] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5832 ) ,
+ .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) ,
+ .clk_2_E_in ( p1920 ) , .clk_2_W_in ( p2754 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5833 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p2815 ) ,
+ .clk_3_E_in ( p2731 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5836 ) ) ;
+cbx_1__1_ cbx_2__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5837 } ) ,
+ .chanx_left_in ( sb_1__1__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__18_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__18_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__18_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__18_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p1730 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5838 ) ,
+ .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[18] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[18] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[18] ) ,
+ .pReset_E_in ( pResetWires[410] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5839 ) ,
+ .pReset_W_out ( pResetWires[409] ) , .pReset_S_out ( pResetWires[411] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5840 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[87] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5841 ) ,
+ .prog_clk_1_W_in ( p1246 ) , .prog_clk_1_E_in ( p232 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5842 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5843 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[14] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5844 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[13] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5845 ) ,
+ .prog_clk_3_W_in ( p1176 ) , .prog_clk_3_E_in ( p1137 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5846 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_1_W_in ( p1176 ) ,
+ .clk_1_E_in ( p1074 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5848 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5849 ) ,
+ .clk_2_E_in ( clk_2_wires[14] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5850 ) ,
+ .clk_2_W_out ( clk_2_wires[13] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p1176 ) ,
+ .clk_3_E_in ( p1689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5853 ) ) ;
+cbx_1__1_ cbx_2__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5854 } ) ,
+ .chanx_left_in ( sb_1__1__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__19_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__19_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__19_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__19_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p1576 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5855 ) ,
+ .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[19] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[19] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[19] ) ,
+ .pReset_E_in ( pResetWires[459] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5856 ) ,
+ .pReset_W_out ( pResetWires[458] ) , .pReset_S_out ( pResetWires[460] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5857 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[90] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5858 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[29] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5859 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[33] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p2798 ) ,
+ .prog_clk_2_W_in ( p1035 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5860 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5861 ) ,
+ .prog_clk_3_W_in ( p1901 ) , .prog_clk_3_E_in ( p2585 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5862 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5863 ) ,
+ .clk_1_W_in ( clk_1_wires[29] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5864 ) ,
+ .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) ,
+ .clk_2_E_in ( p2630 ) , .clk_2_W_in ( p1616 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5865 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p1901 ) ,
+ .clk_3_E_in ( p2746 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5868 ) ) ;
+cbx_1__1_ cbx_2__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5869 } ) ,
+ .chanx_left_in ( sb_1__1__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__20_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__20_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__20_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__20_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p2209 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5870 ) ,
+ .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[20] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[20] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[20] ) ,
+ .pReset_E_in ( pResetWires[508] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5871 ) ,
+ .pReset_W_out ( pResetWires[507] ) , .pReset_S_out ( pResetWires[509] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5872 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[93] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5873 ) ,
+ .prog_clk_1_W_in ( p1544 ) , .prog_clk_1_E_in ( p1416 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5874 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5875 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[21] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5876 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[20] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5877 ) ,
+ .prog_clk_3_W_in ( p1544 ) , .prog_clk_3_E_in ( p1314 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5878 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , .clk_1_W_in ( p1544 ) ,
+ .clk_1_E_in ( p1319 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5880 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5881 ) ,
+ .clk_2_E_in ( clk_2_wires[21] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5882 ) ,
+ .clk_2_W_out ( clk_2_wires[20] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1544 ) ,
+ .clk_3_E_in ( p1983 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5885 ) ) ;
+cbx_1__1_ cbx_2__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5886 } ) ,
+ .chanx_left_in ( sb_1__1__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__21_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__21_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__21_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__21_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p2175 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5887 ) ,
+ .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[21] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[21] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[21] ) ,
+ .pReset_E_in ( pResetWires[557] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5888 ) ,
+ .pReset_W_out ( pResetWires[556] ) , .pReset_S_out ( pResetWires[558] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5889 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[96] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5890 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[36] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5891 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[40] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p2432 ) ,
+ .prog_clk_2_W_in ( p376 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5892 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5893 ) ,
+ .prog_clk_3_W_in ( p1850 ) , .prog_clk_3_E_in ( p420 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5894 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5895 ) ,
+ .clk_1_W_in ( clk_1_wires[36] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5896 ) ,
+ .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) ,
+ .clk_2_E_in ( p1219 ) , .clk_2_W_in ( p1701 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5897 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p1850 ) ,
+ .clk_3_E_in ( p2329 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5900 ) ) ;
+cbx_1__1_ cbx_3__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5901 } ) ,
+ .chanx_left_in ( sb_1__1__11_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__22_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__22_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__22_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__22_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) ,
+ .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1488 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5902 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[22] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[22] ) ,
+ .pReset_E_in ( pResetWires[71] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5903 ) ,
+ .pReset_W_out ( pResetWires[70] ) , .pReset_S_out ( pResetWires[72] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5904 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[104] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5905 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5906 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[44] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[45] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p3111 ) ,
+ .prog_clk_2_W_in ( p996 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5907 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5908 ) ,
+ .prog_clk_3_W_in ( p1228 ) , .prog_clk_3_E_in ( p1617 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5909 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5910 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5911 ) ,
+ .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) ,
+ .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p1847 ) ,
+ .clk_2_W_in ( p652 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p1228 ) ,
+ .clk_3_E_in ( p3054 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5915 ) ) ;
+cbx_1__1_ cbx_3__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5916 } ) ,
+ .chanx_left_in ( sb_1__1__12_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__23_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__23_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__23_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__23_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) ,
+ .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1535 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5917 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[23] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[23] ) ,
+ .pReset_E_in ( pResetWires[120] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5918 ) ,
+ .pReset_W_out ( pResetWires[119] ) , .pReset_S_out ( pResetWires[121] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5919 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[107] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5920 ) ,
+ .prog_clk_1_W_in ( p1502 ) , .prog_clk_1_E_in ( p977 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5921 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5922 ) ,
+ .prog_clk_2_E_in ( p2687 ) , .prog_clk_2_W_in ( p800 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5923 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5924 ) ,
+ .prog_clk_3_W_in ( p1938 ) , .prog_clk_3_E_in ( p1969 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5925 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_1_W_in ( p1791 ) ,
+ .clk_1_E_in ( p1322 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5927 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_2_E_in ( p2157 ) ,
+ .clk_2_W_in ( p1628 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p1938 ) ,
+ .clk_3_E_in ( p2528 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5932 ) ) ;
+cbx_1__1_ cbx_3__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5933 } ) ,
+ .chanx_left_in ( sb_1__1__13_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__24_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__24_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__24_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__24_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) ,
+ .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1587 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5934 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[24] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[24] ) ,
+ .pReset_E_in ( pResetWires[169] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5935 ) ,
+ .pReset_W_out ( pResetWires[168] ) , .pReset_S_out ( pResetWires[170] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5936 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[110] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5937 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5938 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[51] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[52] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p2589 ) ,
+ .prog_clk_2_W_in ( p642 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5939 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5940 ) ,
+ .prog_clk_3_W_in ( p2355 ) , .prog_clk_3_E_in ( p2588 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5941 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5942 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5943 ) ,
+ .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) ,
+ .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p2637 ) ,
+ .clk_2_W_in ( p2308 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p2355 ) ,
+ .clk_3_E_in ( p2523 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5947 ) ) ;
+cbx_1__1_ cbx_3__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5948 } ) ,
+ .chanx_left_in ( sb_1__1__14_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__25_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__25_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__25_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__25_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) ,
+ .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1400 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5949 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[25] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[25] ) ,
+ .pReset_E_in ( pResetWires[218] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5950 ) ,
+ .pReset_W_out ( pResetWires[217] ) , .pReset_S_out ( pResetWires[219] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5951 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[113] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5952 ) ,
+ .prog_clk_1_W_in ( p1489 ) , .prog_clk_1_E_in ( p388 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5953 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5954 ) ,
+ .prog_clk_2_E_in ( p2961 ) , .prog_clk_2_W_in ( p773 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5955 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5956 ) ,
+ .prog_clk_3_W_in ( p1507 ) , .prog_clk_3_E_in ( p2011 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5957 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_1_W_in ( p1507 ) ,
+ .clk_1_E_in ( p1304 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5959 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_2_E_in ( p2137 ) ,
+ .clk_2_W_in ( p1307 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p1507 ) ,
+ .clk_3_E_in ( p2915 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5964 ) ) ;
+cbx_1__1_ cbx_3__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5965 } ) ,
+ .chanx_left_in ( sb_1__1__15_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__26_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__26_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__26_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__26_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) ,
+ .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1135 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5966 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[26] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[26] ) ,
+ .pReset_E_in ( pResetWires[267] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5967 ) ,
+ .pReset_W_out ( pResetWires[266] ) , .pReset_S_out ( pResetWires[268] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5968 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[116] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5969 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5970 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[58] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[59] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p3190 ) ,
+ .prog_clk_2_W_in ( p148 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5971 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5972 ) ,
+ .prog_clk_3_W_in ( p1441 ) , .prog_clk_3_E_in ( p2710 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5973 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5974 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5975 ) ,
+ .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) ,
+ .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p2814 ) ,
+ .clk_2_W_in ( p1348 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p1441 ) ,
+ .clk_3_E_in ( p3167 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5979 ) ) ;
+cbx_1__1_ cbx_3__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5980 } ) ,
+ .chanx_left_in ( sb_1__1__16_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__27_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__27_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__27_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__27_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) ,
+ .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p1170 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5981 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[27] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[27] ) ,
+ .pReset_E_in ( pResetWires[316] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5982 ) ,
+ .pReset_W_out ( pResetWires[315] ) , .pReset_S_out ( pResetWires[317] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5983 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[119] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5984 ) ,
+ .prog_clk_1_W_in ( p1458 ) , .prog_clk_1_E_in ( p297 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5985 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5986 ) ,
+ .prog_clk_2_E_in ( p1759 ) , .prog_clk_2_W_in ( p1080 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5987 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5988 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5989 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[50] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5990 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p2204 ) ,
+ .clk_1_E_in ( p910 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5991 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5992 ) , .clk_2_E_in ( p1759 ) ,
+ .clk_2_W_in ( p1952 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5993 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5994 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5995 ) ,
+ .clk_3_E_in ( clk_3_wires[50] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5996 ) ,
+ .clk_3_W_out ( clk_3_wires[51] ) ) ;
+cbx_1__1_ cbx_3__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5997 } ) ,
+ .chanx_left_in ( sb_1__1__17_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__28_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__28_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__28_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__28_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) ,
+ .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1478 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5998 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[28] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[28] ) ,
+ .pReset_E_in ( pResetWires[365] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5999 ) ,
+ .pReset_W_out ( pResetWires[364] ) , .pReset_S_out ( pResetWires[366] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6000 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[122] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6001 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6002 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[65] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[66] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2657 ) ,
+ .prog_clk_2_W_in ( p968 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6003 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6004 ) ,
+ .prog_clk_3_W_in ( p1595 ) , .prog_clk_3_E_in ( p2063 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6005 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6006 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6007 ) ,
+ .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) ,
+ .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p2077 ) ,
+ .clk_2_W_in ( p1366 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p1595 ) ,
+ .clk_3_E_in ( p2547 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6011 ) ) ;
+cbx_1__1_ cbx_3__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6012 } ) ,
+ .chanx_left_in ( sb_1__1__18_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__29_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__29_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__29_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__29_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) ,
+ .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p1764 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6013 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[29] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[29] ) ,
+ .pReset_E_in ( pResetWires[414] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6014 ) ,
+ .pReset_W_out ( pResetWires[413] ) , .pReset_S_out ( pResetWires[415] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6015 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[125] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6016 ) ,
+ .prog_clk_1_W_in ( p1419 ) , .prog_clk_1_E_in ( p1156 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6017 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6018 ) ,
+ .prog_clk_2_E_in ( p2782 ) , .prog_clk_2_W_in ( p375 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6019 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6020 ) ,
+ .prog_clk_3_W_in ( p2111 ) , .prog_clk_3_E_in ( p2582 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6021 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_1_W_in ( p1453 ) ,
+ .clk_1_E_in ( p1690 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6023 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_2_E_in ( p2601 ) ,
+ .clk_2_W_in ( p2030 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p2111 ) ,
+ .clk_3_E_in ( p2740 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6028 ) ) ;
+cbx_1__1_ cbx_3__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6029 } ) ,
+ .chanx_left_in ( sb_1__1__19_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__30_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__30_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__30_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__30_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) ,
+ .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1586 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6030 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[30] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[30] ) ,
+ .pReset_E_in ( pResetWires[463] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6031 ) ,
+ .pReset_W_out ( pResetWires[462] ) , .pReset_S_out ( pResetWires[464] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6032 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[128] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6033 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6034 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[72] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[73] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p3121 ) ,
+ .prog_clk_2_W_in ( p817 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6035 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6036 ) ,
+ .prog_clk_3_W_in ( p1222 ) , .prog_clk_3_E_in ( p2071 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6037 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6038 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6039 ) ,
+ .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) ,
+ .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p2123 ) ,
+ .clk_2_W_in ( p580 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p1222 ) ,
+ .clk_3_E_in ( p3062 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6043 ) ) ;
+cbx_1__1_ cbx_3__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6044 } ) ,
+ .chanx_left_in ( sb_1__1__20_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__31_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__31_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__31_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__31_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) ,
+ .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1777 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6045 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[31] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[31] ) ,
+ .pReset_E_in ( pResetWires[512] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6046 ) ,
+ .pReset_W_out ( pResetWires[511] ) , .pReset_S_out ( pResetWires[513] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6047 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[131] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6048 ) ,
+ .prog_clk_1_W_in ( p1048 ) , .prog_clk_1_E_in ( p1326 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6049 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6050 ) ,
+ .prog_clk_2_E_in ( p2997 ) , .prog_clk_2_W_in ( p736 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6051 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6052 ) ,
+ .prog_clk_3_W_in ( p2021 ) , .prog_clk_3_E_in ( p1720 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6053 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_1_W_in ( p2021 ) ,
+ .clk_1_E_in ( p1671 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6055 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_2_E_in ( p1950 ) ,
+ .clk_2_W_in ( p2069 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p2021 ) ,
+ .clk_3_E_in ( p2914 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6060 ) ) ;
+cbx_1__1_ cbx_3__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6061 } ) ,
+ .chanx_left_in ( sb_1__1__21_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__32_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__32_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__32_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__32_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) ,
+ .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1243 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6062 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[32] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[32] ) ,
+ .pReset_E_in ( pResetWires[561] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6063 ) ,
+ .pReset_W_out ( pResetWires[560] ) , .pReset_S_out ( pResetWires[562] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6064 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[134] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6065 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6066 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[79] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[80] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p1903 ) ,
+ .prog_clk_2_W_in ( p780 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6067 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6068 ) ,
+ .prog_clk_3_W_in ( p1572 ) , .prog_clk_3_E_in ( p1318 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6069 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6070 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6071 ) ,
+ .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) ,
+ .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p1584 ) ,
+ .clk_2_W_in ( p1359 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p1572 ) ,
+ .clk_3_E_in ( p1684 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6075 ) ) ;
+cbx_1__1_ cbx_4__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6076 } ) ,
+ .chanx_left_in ( sb_1__1__22_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__33_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__33_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__33_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__33_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p1247 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6077 ) ,
+ .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[33] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[33] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[33] ) ,
+ .pReset_E_in ( pResetWires[75] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6078 ) ,
+ .pReset_W_out ( pResetWires[74] ) , .pReset_S_out ( pResetWires[76] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6079 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[142] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6080 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[43] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6081 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[47] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p3120 ) ,
+ .prog_clk_2_W_in ( p596 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6082 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6083 ) ,
+ .prog_clk_3_W_in ( p1547 ) , .prog_clk_3_E_in ( p2331 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6084 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6085 ) ,
+ .clk_1_W_in ( clk_1_wires[43] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6086 ) ,
+ .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) ,
+ .clk_2_E_in ( p2486 ) , .clk_2_W_in ( p1353 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6087 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p1547 ) ,
+ .clk_3_E_in ( p3066 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6090 ) ) ;
+cbx_1__1_ cbx_4__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6091 } ) ,
+ .chanx_left_in ( sb_1__1__23_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__34_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__34_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__34_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__34_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p1146 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6092 ) ,
+ .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[34] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[34] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[34] ) ,
+ .pReset_E_in ( pResetWires[124] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6093 ) ,
+ .pReset_W_out ( pResetWires[123] ) , .pReset_S_out ( pResetWires[125] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6094 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[145] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6095 ) ,
+ .prog_clk_1_W_in ( p1555 ) , .prog_clk_1_E_in ( p754 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6096 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6097 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[27] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6098 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[28] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6099 ) ,
+ .prog_clk_3_W_in ( p1812 ) , .prog_clk_3_E_in ( p1694 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6100 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) , .clk_1_W_in ( p1812 ) ,
+ .clk_1_E_in ( p77 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6102 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6103 ) ,
+ .clk_2_E_in ( clk_2_wires[27] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6104 ) ,
+ .clk_2_W_out ( clk_2_wires[28] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1812 ) ,
+ .clk_3_E_in ( p532 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6107 ) ) ;
+cbx_1__1_ cbx_4__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6108 } ) ,
+ .chanx_left_in ( sb_1__1__24_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__35_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__35_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__35_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__35_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p931 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6109 ) ,
+ .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[35] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[35] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[35] ) ,
+ .pReset_E_in ( pResetWires[173] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6110 ) ,
+ .pReset_W_out ( pResetWires[172] ) , .pReset_S_out ( pResetWires[174] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6111 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[148] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6112 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[50] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6113 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[54] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p2472 ) ,
+ .prog_clk_2_W_in ( p915 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6114 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6115 ) ,
+ .prog_clk_3_W_in ( p2784 ) , .prog_clk_3_E_in ( p1991 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6116 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6117 ) ,
+ .clk_1_W_in ( clk_1_wires[50] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6118 ) ,
+ .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) ,
+ .clk_2_E_in ( p2227 ) , .clk_2_W_in ( p2757 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6119 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p2784 ) ,
+ .clk_3_E_in ( p2296 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6122 ) ) ;
+cbx_1__1_ cbx_4__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6123 } ) ,
+ .chanx_left_in ( sb_1__1__25_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__36_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__36_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__36_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__36_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p1607 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6124 ) ,
+ .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[36] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[36] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[36] ) ,
+ .pReset_E_in ( pResetWires[222] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6125 ) ,
+ .pReset_W_out ( pResetWires[221] ) , .pReset_S_out ( pResetWires[223] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6126 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[151] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6127 ) ,
+ .prog_clk_1_W_in ( p1563 ) , .prog_clk_1_E_in ( p370 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6128 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6129 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[36] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6130 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[37] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6131 ) ,
+ .prog_clk_3_W_in ( p1563 ) , .prog_clk_3_E_in ( p875 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6132 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , .clk_1_W_in ( p1563 ) ,
+ .clk_1_E_in ( p1166 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6134 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6135 ) ,
+ .clk_2_E_in ( clk_2_wires[36] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6136 ) ,
+ .clk_2_W_out ( clk_2_wires[37] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p1563 ) ,
+ .clk_3_E_in ( p1342 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6139 ) ) ;
+cbx_1__1_ cbx_4__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6140 } ) ,
+ .chanx_left_in ( sb_1__1__26_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__37_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__37_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__37_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__37_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p1945 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6141 ) ,
+ .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[37] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[37] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[37] ) ,
+ .pReset_E_in ( pResetWires[271] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6142 ) ,
+ .pReset_W_out ( pResetWires[270] ) , .pReset_S_out ( pResetWires[272] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6143 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[154] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6144 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[57] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6145 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[61] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p3353 ) ,
+ .prog_clk_2_W_in ( p299 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6146 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6147 ) ,
+ .prog_clk_3_W_in ( p2369 ) , .prog_clk_3_E_in ( p2333 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6148 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6149 ) ,
+ .clk_1_W_in ( clk_1_wires[57] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6150 ) ,
+ .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) ,
+ .clk_2_E_in ( p2453 ) , .clk_2_W_in ( p2306 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6151 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2369 ) ,
+ .clk_3_E_in ( p3311 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6154 ) ) ;
+cbx_1__1_ cbx_4__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6155 } ) ,
+ .chanx_left_in ( sb_1__1__27_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__38_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__38_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__38_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__38_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1469 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6156 ) ,
+ .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[38] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[38] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[38] ) ,
+ .pReset_E_in ( pResetWires[320] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6157 ) ,
+ .pReset_W_out ( pResetWires[319] ) , .pReset_S_out ( pResetWires[321] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6158 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[157] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6159 ) ,
+ .prog_clk_1_W_in ( p1785 ) , .prog_clk_1_E_in ( p886 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6160 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6161 ) ,
+ .prog_clk_2_E_in ( p1789 ) , .prog_clk_2_W_in ( p1328 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6162 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6163 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6164 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[46] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6165 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p1774 ) ,
+ .clk_1_E_in ( p421 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6166 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6167 ) , .clk_2_E_in ( p1789 ) ,
+ .clk_2_W_in ( p1618 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6169 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6170 ) ,
+ .clk_3_E_in ( clk_3_wires[46] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6171 ) ,
+ .clk_3_W_out ( clk_3_wires[47] ) ) ;
+cbx_1__1_ cbx_4__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6172 } ) ,
+ .chanx_left_in ( sb_1__1__28_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__39_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__39_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__39_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__39_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p1943 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6173 ) ,
+ .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[39] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[39] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[39] ) ,
+ .pReset_E_in ( pResetWires[369] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6174 ) ,
+ .pReset_W_out ( pResetWires[368] ) , .pReset_S_out ( pResetWires[370] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6175 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[160] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6176 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[64] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6177 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[68] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p3007 ) ,
+ .prog_clk_2_W_in ( p631 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6178 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6179 ) ,
+ .prog_clk_3_W_in ( p2623 ) , .prog_clk_3_E_in ( p1976 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6180 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6181 ) ,
+ .clk_1_W_in ( clk_1_wires[64] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6182 ) ,
+ .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) ,
+ .clk_2_E_in ( p2091 ) , .clk_2_W_in ( p2505 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6183 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p2623 ) ,
+ .clk_3_E_in ( p2878 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6186 ) ) ;
+cbx_1__1_ cbx_4__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6187 } ) ,
+ .chanx_left_in ( sb_1__1__29_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__40_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__40_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__40_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__40_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p2237 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6188 ) ,
+ .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[40] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[40] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[40] ) ,
+ .pReset_E_in ( pResetWires[418] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6189 ) ,
+ .pReset_W_out ( pResetWires[417] ) , .pReset_S_out ( pResetWires[419] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6190 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[163] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6191 ) ,
+ .prog_clk_1_W_in ( p1597 ) , .prog_clk_1_E_in ( p328 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6192 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6193 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[49] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6194 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[50] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6195 ) ,
+ .prog_clk_3_W_in ( p1597 ) , .prog_clk_3_E_in ( p182 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6196 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6197 ) , .clk_1_W_in ( p1597 ) ,
+ .clk_1_E_in ( p729 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6199 ) ,
+ .clk_2_E_in ( clk_2_wires[49] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6200 ) ,
+ .clk_2_W_out ( clk_2_wires[50] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1597 ) ,
+ .clk_3_E_in ( p1992 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6203 ) ) ;
+cbx_1__1_ cbx_4__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6204 } ) ,
+ .chanx_left_in ( sb_1__1__30_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__41_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__41_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__41_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__41_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p2155 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6205 ) ,
+ .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[41] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[41] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[41] ) ,
+ .pReset_E_in ( pResetWires[467] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6206 ) ,
+ .pReset_W_out ( pResetWires[466] ) , .pReset_S_out ( pResetWires[468] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6207 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[166] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6208 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[71] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6209 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[75] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p3291 ) ,
+ .prog_clk_2_W_in ( p664 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6210 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6211 ) ,
+ .prog_clk_3_W_in ( p1249 ) , .prog_clk_3_E_in ( p1725 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6212 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6213 ) ,
+ .clk_1_W_in ( clk_1_wires[71] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6214 ) ,
+ .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) ,
+ .clk_2_E_in ( p1769 ) , .clk_2_W_in ( p979 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6215 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p1249 ) ,
+ .clk_3_E_in ( p3239 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6218 ) ) ;
+cbx_1__1_ cbx_4__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6219 } ) ,
+ .chanx_left_in ( sb_1__1__31_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__42_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__42_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__42_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__42_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1743 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6220 ) ,
+ .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[42] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[42] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[42] ) ,
+ .pReset_E_in ( pResetWires[516] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6221 ) ,
+ .pReset_W_out ( pResetWires[515] ) , .pReset_S_out ( pResetWires[517] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6222 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[169] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6223 ) ,
+ .prog_clk_1_W_in ( p1211 ) , .prog_clk_1_E_in ( p965 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6224 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6225 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[62] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6226 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[63] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6227 ) ,
+ .prog_clk_3_W_in ( p1211 ) , .prog_clk_3_E_in ( p1258 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6228 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6229 ) , .clk_1_W_in ( p1211 ) ,
+ .clk_1_E_in ( p317 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6230 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6231 ) ,
+ .clk_2_E_in ( clk_2_wires[62] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6232 ) ,
+ .clk_2_W_out ( clk_2_wires[63] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1211 ) ,
+ .clk_3_E_in ( p1685 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6235 ) ) ;
+cbx_1__1_ cbx_4__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6236 } ) ,
+ .chanx_left_in ( sb_1__1__32_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__43_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__43_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__43_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__43_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p1471 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6237 ) ,
+ .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[43] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[43] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[43] ) ,
+ .pReset_E_in ( pResetWires[565] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6238 ) ,
+ .pReset_W_out ( pResetWires[564] ) , .pReset_S_out ( pResetWires[566] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6239 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[172] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6240 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[78] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6241 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[82] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p2790 ) ,
+ .prog_clk_2_W_in ( p1050 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6242 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6243 ) ,
+ .prog_clk_3_W_in ( p1846 ) , .prog_clk_3_E_in ( p2564 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6244 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6245 ) ,
+ .clk_1_W_in ( clk_1_wires[78] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6246 ) ,
+ .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) ,
+ .clk_2_E_in ( p2640 ) , .clk_2_W_in ( p1697 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6247 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p1846 ) ,
+ .clk_3_E_in ( p2739 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6250 ) ) ;
+cbx_1__1_ cbx_5__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6251 } ) ,
+ .chanx_left_in ( sb_1__1__33_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__44_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__44_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__44_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__44_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) ,
+ .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1068 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6252 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[44] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[44] ) ,
+ .pReset_E_in ( pResetWires[79] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6253 ) ,
+ .pReset_W_out ( pResetWires[78] ) , .pReset_S_out ( pResetWires[80] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6254 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[180] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6255 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6256 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[86] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[87] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p1455 ) ,
+ .prog_clk_2_W_in ( p41 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6257 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6258 ) ,
+ .prog_clk_3_W_in ( p2383 ) , .prog_clk_3_E_in ( p1261 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6259 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6260 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6261 ) ,
+ .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) ,
+ .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p1551 ) ,
+ .clk_2_W_in ( p2315 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p2383 ) ,
+ .clk_3_E_in ( p1386 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6265 ) ) ;
+cbx_1__1_ cbx_5__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6266 } ) ,
+ .chanx_left_in ( sb_1__1__34_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__45_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__45_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__45_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__45_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) ,
+ .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p1226 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6267 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[45] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[45] ) ,
+ .pReset_E_in ( pResetWires[128] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6268 ) ,
+ .pReset_W_out ( pResetWires[127] ) , .pReset_S_out ( pResetWires[129] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6269 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[183] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6270 ) ,
+ .prog_clk_1_W_in ( p1443 ) , .prog_clk_1_E_in ( p285 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6271 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6272 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6273 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[25] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6274 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1841 ) ,
+ .prog_clk_3_E_in ( p1954 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6275 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , .clk_1_W_in ( p1841 ) ,
+ .clk_1_E_in ( p1112 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6277 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6278 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6279 ) ,
+ .clk_2_W_in ( clk_2_wires[25] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6280 ) ,
+ .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1841 ) ,
+ .clk_3_E_in ( p416 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6282 ) ) ;
+cbx_1__1_ cbx_5__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6283 } ) ,
+ .chanx_left_in ( sb_1__1__35_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__46_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__46_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__46_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__46_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) ,
+ .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1174 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6284 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[46] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[46] ) ,
+ .pReset_E_in ( pResetWires[177] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6285 ) ,
+ .pReset_W_out ( pResetWires[176] ) , .pReset_S_out ( pResetWires[178] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6286 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[186] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6287 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6288 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[93] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[94] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p2673 ) ,
+ .prog_clk_2_W_in ( p853 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6289 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6290 ) ,
+ .prog_clk_3_W_in ( p2171 ) , .prog_clk_3_E_in ( p1691 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6291 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6292 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6293 ) ,
+ .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) ,
+ .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p1834 ) ,
+ .clk_2_W_in ( p2004 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p2171 ) ,
+ .clk_3_E_in ( p2535 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6297 ) ) ;
+cbx_1__1_ cbx_5__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6298 } ) ,
+ .chanx_left_in ( sb_1__1__36_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__47_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__47_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__47_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__47_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) ,
+ .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p1432 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6299 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[47] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[47] ) ,
+ .pReset_E_in ( pResetWires[226] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6300 ) ,
+ .pReset_W_out ( pResetWires[225] ) , .pReset_S_out ( pResetWires[227] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6301 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[189] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6302 ) ,
+ .prog_clk_1_W_in ( p726 ) , .prog_clk_1_E_in ( p1271 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6303 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6304 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6305 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[34] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6306 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p726 ) ,
+ .prog_clk_3_E_in ( p1680 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6307 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_1_W_in ( p726 ) ,
+ .clk_1_E_in ( p1323 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6309 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6310 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6311 ) ,
+ .clk_2_W_in ( clk_2_wires[34] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6312 ) ,
+ .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p726 ) ,
+ .clk_3_E_in ( p524 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6314 ) ) ;
+cbx_1__1_ cbx_5__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6315 } ) ,
+ .chanx_left_in ( sb_1__1__37_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__48_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__48_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__48_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__48_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) ,
+ .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1605 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6316 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[48] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[48] ) ,
+ .pReset_E_in ( pResetWires[275] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6317 ) ,
+ .pReset_W_out ( pResetWires[274] ) , .pReset_S_out ( pResetWires[276] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6318 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[192] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6319 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6320 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[100] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[101] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p3079 ) ,
+ .prog_clk_2_W_in ( p692 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6321 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6322 ) ,
+ .prog_clk_3_W_in ( p2136 ) , .prog_clk_3_E_in ( p2254 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6323 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6324 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6325 ) ,
+ .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) ,
+ .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p2408 ) ,
+ .clk_2_W_in ( p1981 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p2136 ) ,
+ .clk_3_E_in ( p3035 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6329 ) ) ;
+cbx_1__1_ cbx_5__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6330 } ) ,
+ .chanx_left_in ( sb_1__1__38_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__49_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__49_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__49_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__49_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) ,
+ .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p1562 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6331 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[49] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[49] ) ,
+ .pReset_E_in ( pResetWires[324] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6332 ) ,
+ .pReset_W_out ( pResetWires[323] ) , .pReset_S_out ( pResetWires[325] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6333 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[195] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6334 ) ,
+ .prog_clk_1_W_in ( p1480 ) , .prog_clk_1_E_in ( p240 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6335 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6336 ) ,
+ .prog_clk_2_E_in ( p620 ) , .prog_clk_2_W_in ( p541 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6337 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6338 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6339 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[6] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6340 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p2191 ) ,
+ .clk_1_E_in ( p1313 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6341 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6342 ) , .clk_2_E_in ( p620 ) ,
+ .clk_2_W_in ( p2001 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6343 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6344 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6345 ) ,
+ .clk_3_E_in ( clk_3_wires[6] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6346 ) ,
+ .clk_3_W_out ( clk_3_wires[7] ) ) ;
+cbx_1__1_ cbx_5__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6347 } ) ,
+ .chanx_left_in ( sb_1__1__39_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__50_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__50_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__50_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__50_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) ,
+ .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p1111 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6348 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[50] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[50] ) ,
+ .pReset_E_in ( pResetWires[373] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6349 ) ,
+ .pReset_W_out ( pResetWires[372] ) , .pReset_S_out ( pResetWires[374] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6350 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[198] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6351 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6352 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[107] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[108] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p3128 ) ,
+ .prog_clk_2_W_in ( p555 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6353 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6354 ) ,
+ .prog_clk_3_W_in ( p1852 ) , .prog_clk_3_E_in ( p1320 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6355 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6356 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6357 ) ,
+ .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) ,
+ .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p1574 ) ,
+ .clk_2_W_in ( p1656 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p1852 ) ,
+ .clk_3_E_in ( p3021 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6361 ) ) ;
+cbx_1__1_ cbx_5__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6362 } ) ,
+ .chanx_left_in ( sb_1__1__40_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__51_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__51_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__51_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__51_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) ,
+ .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1438 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6363 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[51] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[51] ) ,
+ .pReset_E_in ( pResetWires[422] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6364 ) ,
+ .pReset_W_out ( pResetWires[421] ) , .pReset_S_out ( pResetWires[423] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6365 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[201] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6366 ) ,
+ .prog_clk_1_W_in ( p909 ) , .prog_clk_1_E_in ( p1229 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6367 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6368 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6369 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[47] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6370 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p909 ) ,
+ .prog_clk_3_E_in ( p1665 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6371 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_1_W_in ( p909 ) ,
+ .clk_1_E_in ( p1345 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6373 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6374 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6375 ) ,
+ .clk_2_W_in ( clk_2_wires[47] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6376 ) ,
+ .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p909 ) ,
+ .clk_3_E_in ( p385 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6378 ) ) ;
+cbx_1__1_ cbx_5__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6379 } ) ,
+ .chanx_left_in ( sb_1__1__41_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__52_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__52_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__52_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__52_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) ,
+ .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1760 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6380 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[52] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[52] ) ,
+ .pReset_E_in ( pResetWires[471] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6381 ) ,
+ .pReset_W_out ( pResetWires[470] ) , .pReset_S_out ( pResetWires[472] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6382 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[204] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6383 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6384 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[114] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[115] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p3087 ) ,
+ .prog_clk_2_W_in ( p665 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6385 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6386 ) ,
+ .prog_clk_3_W_in ( p2231 ) , .prog_clk_3_E_in ( p1621 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6387 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6388 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6389 ) ,
+ .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) ,
+ .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p1780 ) ,
+ .clk_2_W_in ( p1993 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p2231 ) ,
+ .clk_3_E_in ( p3055 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6393 ) ) ;
+cbx_1__1_ cbx_5__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6394 } ) ,
+ .chanx_left_in ( sb_1__1__42_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__53_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__53_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__53_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__53_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) ,
+ .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p2086 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6395 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[53] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[53] ) ,
+ .pReset_E_in ( pResetWires[520] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6396 ) ,
+ .pReset_W_out ( pResetWires[519] ) , .pReset_S_out ( pResetWires[521] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6397 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[207] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6398 ) ,
+ .prog_clk_1_W_in ( p1190 ) , .prog_clk_1_E_in ( p1132 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6399 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6400 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6401 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[60] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6402 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p1524 ) ,
+ .prog_clk_3_E_in ( p1634 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6403 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , .clk_1_W_in ( p1524 ) ,
+ .clk_1_E_in ( p2024 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6405 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6406 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6407 ) ,
+ .clk_2_W_in ( clk_2_wires[60] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6408 ) ,
+ .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p1524 ) ,
+ .clk_3_E_in ( p284 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6410 ) ) ;
+cbx_1__1_ cbx_5__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6411 } ) ,
+ .chanx_left_in ( sb_1__1__43_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__54_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__54_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__54_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__54_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) ,
+ .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1750 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6412 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[54] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[54] ) ,
+ .pReset_E_in ( pResetWires[569] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6413 ) ,
+ .pReset_W_out ( pResetWires[568] ) , .pReset_S_out ( pResetWires[570] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6414 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[210] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6415 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6416 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[121] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[122] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p3041 ) ,
+ .prog_clk_2_W_in ( p533 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6417 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6418 ) ,
+ .prog_clk_3_W_in ( p1602 ) , .prog_clk_3_E_in ( p2045 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6419 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6420 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6421 ) ,
+ .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) ,
+ .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p2197 ) ,
+ .clk_2_W_in ( p1315 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p1602 ) ,
+ .clk_3_E_in ( p3069 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6425 ) ) ;
+cbx_1__1_ cbx_6__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6426 } ) ,
+ .chanx_left_in ( sb_1__1__44_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__55_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__55_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__55_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__55_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p1765 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6427 ) ,
+ .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[55] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[55] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[55] ) ,
+ .pReset_E_in ( pResetWires[83] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6428 ) ,
+ .pReset_W_out ( pResetWires[82] ) , .pReset_S_out ( pResetWires[84] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6429 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[218] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6430 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[85] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6431 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[89] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p3346 ) ,
+ .prog_clk_2_W_in ( p525 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6432 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6433 ) ,
+ .prog_clk_3_W_in ( p2115 ) , .prog_clk_3_E_in ( p2270 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6434 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6435 ) ,
+ .clk_1_W_in ( clk_1_wires[85] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6436 ) ,
+ .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) ,
+ .clk_2_E_in ( p2469 ) , .clk_2_W_in ( p2019 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6437 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2115 ) ,
+ .clk_3_E_in ( p3309 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6440 ) ) ;
+cbx_1__1_ cbx_6__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6441 } ) ,
+ .chanx_left_in ( sb_1__1__45_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__56_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__56_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__56_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__56_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1603 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6442 ) ,
+ .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[56] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[56] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[56] ) ,
+ .pReset_E_in ( pResetWires[132] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6443 ) ,
+ .pReset_W_out ( pResetWires[131] ) , .pReset_S_out ( pResetWires[133] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6444 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[221] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6445 ) ,
+ .prog_clk_1_W_in ( p1678 ) , .prog_clk_1_E_in ( p1389 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6446 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6447 ) ,
+ .prog_clk_2_E_in ( p1500 ) , .prog_clk_2_W_in ( p361 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6448 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6449 ) ,
+ .prog_clk_3_W_in ( p2384 ) , .prog_clk_3_E_in ( p2516 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6450 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_1_W_in ( p1893 ) ,
+ .clk_1_E_in ( p1300 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6452 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_2_E_in ( p2706 ) ,
+ .clk_2_W_in ( p2293 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p2384 ) ,
+ .clk_3_E_in ( p1391 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6457 ) ) ;
+cbx_1__1_ cbx_6__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6458 } ) ,
+ .chanx_left_in ( sb_1__1__46_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__57_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__57_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__57_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__57_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p1904 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6459 ) ,
+ .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[57] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[57] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[57] ) ,
+ .pReset_E_in ( pResetWires[181] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6460 ) ,
+ .pReset_W_out ( pResetWires[180] ) , .pReset_S_out ( pResetWires[182] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6461 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[224] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6462 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[92] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6463 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[96] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p2649 ) ,
+ .prog_clk_2_W_in ( p115 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6464 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6465 ) ,
+ .prog_clk_3_W_in ( p1874 ) , .prog_clk_3_E_in ( p1737 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6466 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6467 ) ,
+ .clk_1_W_in ( clk_1_wires[92] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6468 ) ,
+ .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) ,
+ .clk_2_E_in ( p1930 ) , .clk_2_W_in ( p1698 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6469 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p1874 ) ,
+ .clk_3_E_in ( p2508 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6472 ) ) ;
+cbx_1__1_ cbx_6__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6473 } ) ,
+ .chanx_left_in ( sb_1__1__47_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__58_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__58_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__58_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__58_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p2356 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6474 ) ,
+ .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[58] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[58] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[58] ) ,
+ .pReset_E_in ( pResetWires[230] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6475 ) ,
+ .pReset_W_out ( pResetWires[229] ) , .pReset_S_out ( pResetWires[231] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6476 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[227] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6477 ) ,
+ .prog_clk_1_W_in ( p1154 ) , .prog_clk_1_E_in ( p887 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6478 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6479 ) ,
+ .prog_clk_2_E_in ( p2659 ) , .prog_clk_2_W_in ( p552 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6480 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6481 ) ,
+ .prog_clk_3_W_in ( p2240 ) , .prog_clk_3_E_in ( p545 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6482 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_1_W_in ( p2096 ) ,
+ .clk_1_E_in ( p331 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6484 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_2_E_in ( p1091 ) ,
+ .clk_2_W_in ( p2027 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p2240 ) ,
+ .clk_3_E_in ( p2522 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6489 ) ) ;
+cbx_1__1_ cbx_6__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6490 } ) ,
+ .chanx_left_in ( sb_1__1__48_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__59_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__59_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__59_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__59_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p1093 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6491 ) ,
+ .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[59] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[59] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[59] ) ,
+ .pReset_E_in ( pResetWires[279] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6492 ) ,
+ .pReset_W_out ( pResetWires[278] ) , .pReset_S_out ( pResetWires[280] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6493 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[230] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6494 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[99] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6495 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[103] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p3106 ) ,
+ .prog_clk_2_W_in ( p557 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6496 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6497 ) ,
+ .prog_clk_3_W_in ( p2666 ) , .prog_clk_3_E_in ( p1388 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6498 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6499 ) ,
+ .clk_1_W_in ( clk_1_wires[99] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6500 ) ,
+ .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) ,
+ .clk_2_E_in ( p1511 ) , .clk_2_W_in ( p2560 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6501 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p2666 ) ,
+ .clk_3_E_in ( p3040 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6504 ) ) ;
+cbx_1__1_ cbx_6__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6505 } ) ,
+ .chanx_left_in ( sb_1__1__49_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__60_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__60_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__60_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__60_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p1598 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6506 ) ,
+ .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[60] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[60] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[60] ) ,
+ .pReset_E_in ( pResetWires[328] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6507 ) ,
+ .pReset_W_out ( pResetWires[327] ) , .pReset_S_out ( pResetWires[329] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6508 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[233] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6509 ) ,
+ .prog_clk_1_W_in ( p1217 ) , .prog_clk_1_E_in ( p597 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6510 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6511 ) ,
+ .prog_clk_2_E_in ( p1918 ) , .prog_clk_2_W_in ( p1344 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6512 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6513 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6514 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[2] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6515 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p1593 ) ,
+ .clk_1_E_in ( p125 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6516 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_2_E_in ( p1918 ) ,
+ .clk_2_W_in ( p1357 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6518 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6519 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6520 ) ,
+ .clk_3_E_in ( clk_3_wires[2] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6521 ) ,
+ .clk_3_W_out ( clk_3_wires[3] ) ) ;
+cbx_1__1_ cbx_6__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6522 } ) ,
+ .chanx_left_in ( sb_1__1__50_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__61_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__61_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__61_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__61_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p1896 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6523 ) ,
+ .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[61] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[61] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[61] ) ,
+ .pReset_E_in ( pResetWires[377] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6524 ) ,
+ .pReset_W_out ( pResetWires[376] ) , .pReset_S_out ( pResetWires[378] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6525 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[236] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6526 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[106] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6527 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[110] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p2855 ) ,
+ .prog_clk_2_W_in ( p476 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6528 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6529 ) ,
+ .prog_clk_3_W_in ( p2484 ) , .prog_clk_3_E_in ( p1647 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6530 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6531 ) ,
+ .clk_1_W_in ( clk_1_wires[106] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6532 ) ,
+ .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) ,
+ .clk_2_E_in ( p1807 ) , .clk_2_W_in ( p2310 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6533 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p2484 ) ,
+ .clk_3_E_in ( p2767 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6536 ) ) ;
+cbx_1__1_ cbx_6__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6537 } ) ,
+ .chanx_left_in ( sb_1__1__51_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__62_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__62_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__62_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__62_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p2178 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6538 ) ,
+ .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[62] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[62] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[62] ) ,
+ .pReset_E_in ( pResetWires[426] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6539 ) ,
+ .pReset_W_out ( pResetWires[425] ) , .pReset_S_out ( pResetWires[427] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6540 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[239] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6541 ) ,
+ .prog_clk_1_W_in ( p1521 ) , .prog_clk_1_E_in ( p452 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6542 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6543 ) ,
+ .prog_clk_2_E_in ( p2493 ) , .prog_clk_2_W_in ( p234 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6544 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6545 ) ,
+ .prog_clk_3_W_in ( p2172 ) , .prog_clk_3_E_in ( p2026 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6546 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_1_W_in ( p2207 ) ,
+ .clk_1_E_in ( p1070 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6548 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_2_E_in ( p2174 ) ,
+ .clk_2_W_in ( p1990 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p2172 ) ,
+ .clk_3_E_in ( p2305 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6553 ) ) ;
+cbx_1__1_ cbx_6__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6554 } ) ,
+ .chanx_left_in ( sb_1__1__52_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__63_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__63_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__63_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__63_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p1501 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6555 ) ,
+ .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[63] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[63] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[63] ) ,
+ .pReset_E_in ( pResetWires[475] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6556 ) ,
+ .pReset_W_out ( pResetWires[474] ) , .pReset_S_out ( pResetWires[476] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6557 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[242] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6558 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[113] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6559 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[117] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2626 ) ,
+ .prog_clk_2_W_in ( p433 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6560 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6561 ) ,
+ .prog_clk_3_W_in ( p2477 ) , .prog_clk_3_E_in ( p2286 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6562 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6563 ) ,
+ .clk_1_W_in ( clk_1_wires[113] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6564 ) ,
+ .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) ,
+ .clk_2_E_in ( p2471 ) , .clk_2_W_in ( p2313 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6565 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p2376 ) ,
+ .clk_3_E_in ( p2506 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6568 ) ) ;
+cbx_1__1_ cbx_6__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6569 } ) ,
+ .chanx_left_in ( sb_1__1__53_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__64_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__64_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__64_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__64_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p1858 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6570 ) ,
+ .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[64] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[64] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[64] ) ,
+ .pReset_E_in ( pResetWires[524] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6571 ) ,
+ .pReset_W_out ( pResetWires[523] ) , .pReset_S_out ( pResetWires[525] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6572 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[245] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6573 ) ,
+ .prog_clk_1_W_in ( p1557 ) , .prog_clk_1_E_in ( p346 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6574 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6575 ) ,
+ .prog_clk_2_E_in ( p3226 ) , .prog_clk_2_W_in ( p207 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6576 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6577 ) ,
+ .prog_clk_3_W_in ( p1799 ) , .prog_clk_3_E_in ( p1254 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6578 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_1_W_in ( p1799 ) ,
+ .clk_1_E_in ( p1212 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6580 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_2_E_in ( p1424 ) ,
+ .clk_2_W_in ( p1704 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p1799 ) ,
+ .clk_3_E_in ( p3156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6585 ) ) ;
+cbx_1__1_ cbx_6__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6586 } ) ,
+ .chanx_left_in ( sb_1__1__54_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__65_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__65_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__65_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__65_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p1859 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6587 ) ,
+ .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[65] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[65] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[65] ) ,
+ .pReset_E_in ( pResetWires[573] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6588 ) ,
+ .pReset_W_out ( pResetWires[572] ) , .pReset_S_out ( pResetWires[574] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6589 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[248] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6590 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[120] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6591 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[124] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p2475 ) ,
+ .prog_clk_2_W_in ( p702 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6592 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6593 ) ,
+ .prog_clk_3_W_in ( p2192 ) , .prog_clk_3_E_in ( p1676 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6594 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6595 ) ,
+ .clk_1_W_in ( clk_1_wires[120] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6596 ) ,
+ .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) ,
+ .clk_2_E_in ( p1942 ) , .clk_2_W_in ( p2022 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6597 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2192 ) ,
+ .clk_3_E_in ( p2250 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6600 ) ) ;
+cbx_1__1_ cbx_7__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6601 } ) ,
+ .chanx_left_in ( sb_1__1__55_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__66_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__66_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__66_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__66_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) ,
+ .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p1186 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6602 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[66] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[66] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6603 ) ,
+ .pReset_W_in ( pResetWires[86] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6604 ) ,
+ .pReset_S_out ( pResetWires[88] ) , .pReset_E_out ( pResetWires[87] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[256] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6605 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6606 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[128] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[129] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p2979 ) ,
+ .prog_clk_2_W_in ( p353 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6607 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6608 ) ,
+ .prog_clk_3_W_in ( p1733 ) , .prog_clk_3_E_in ( p2054 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6609 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6610 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6611 ) ,
+ .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) ,
+ .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p2234 ) ,
+ .clk_2_W_in ( p1632 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p1733 ) ,
+ .clk_3_E_in ( p2934 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6615 ) ) ;
+cbx_1__1_ cbx_7__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6616 } ) ,
+ .chanx_left_in ( sb_1__1__56_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__67_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__67_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__67_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__67_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) ,
+ .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p1122 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6617 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[67] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[67] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6618 ) ,
+ .pReset_W_in ( pResetWires[135] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6619 ) ,
+ .pReset_S_out ( pResetWires[137] ) , .pReset_E_out ( pResetWires[136] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[259] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6620 ) ,
+ .prog_clk_1_W_in ( p1935 ) , .prog_clk_1_E_in ( p311 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6621 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6622 ) ,
+ .prog_clk_2_E_in ( p2186 ) , .prog_clk_2_W_in ( p155 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6623 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6624 ) ,
+ .prog_clk_3_W_in ( p2104 ) , .prog_clk_3_E_in ( p1312 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6625 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_1_W_in ( p2104 ) ,
+ .clk_1_E_in ( p1044 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6627 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_2_E_in ( p1530 ) ,
+ .clk_2_W_in ( p2017 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2104 ) ,
+ .clk_3_E_in ( p1986 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6632 ) ) ;
+cbx_1__1_ cbx_7__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6633 } ) ,
+ .chanx_left_in ( sb_1__1__57_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__68_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__68_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__68_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__68_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) ,
+ .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1208 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6634 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[68] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[68] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6635 ) ,
+ .pReset_W_in ( pResetWires[184] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6636 ) ,
+ .pReset_S_out ( pResetWires[186] ) , .pReset_E_out ( pResetWires[185] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[262] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6637 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6638 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[135] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[136] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p2956 ) ,
+ .prog_clk_2_W_in ( p568 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6639 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6640 ) ,
+ .prog_clk_3_W_in ( p1926 ) , .prog_clk_3_E_in ( p2047 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6641 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6642 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6643 ) ,
+ .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) ,
+ .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2125 ) ,
+ .clk_2_W_in ( p1679 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p1926 ) ,
+ .clk_3_E_in ( p2916 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6647 ) ) ;
+cbx_1__1_ cbx_7__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6648 } ) ,
+ .chanx_left_in ( sb_1__1__58_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__69_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__69_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__69_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__69_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) ,
+ .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1793 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6649 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[69] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[69] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6650 ) ,
+ .pReset_W_in ( pResetWires[233] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6651 ) ,
+ .pReset_S_out ( pResetWires[235] ) , .pReset_E_out ( pResetWires[234] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[265] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6652 ) ,
+ .prog_clk_1_W_in ( p982 ) , .prog_clk_1_E_in ( p426 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6653 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6654 ) ,
+ .prog_clk_2_E_in ( p3421 ) , .prog_clk_2_W_in ( p582 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6655 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6656 ) ,
+ .prog_clk_3_W_in ( p2621 ) , .prog_clk_3_E_in ( p2349 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6657 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_1_W_in ( p2151 ) ,
+ .clk_1_E_in ( p1655 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6659 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_2_E_in ( p2387 ) ,
+ .clk_2_W_in ( p2531 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p2667 ) ,
+ .clk_3_E_in ( p3374 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6664 ) ) ;
+cbx_1__1_ cbx_7__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6665 } ) ,
+ .chanx_left_in ( sb_1__1__59_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__70_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__70_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__70_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__70_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) ,
+ .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p2154 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6666 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[70] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[70] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6667 ) ,
+ .pReset_W_in ( pResetWires[282] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6668 ) ,
+ .pReset_S_out ( pResetWires[284] ) , .pReset_E_out ( pResetWires[283] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[268] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6669 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6670 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[142] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[143] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p2705 ) ,
+ .prog_clk_2_W_in ( p816 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6671 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6672 ) ,
+ .prog_clk_3_W_in ( p1773 ) , .prog_clk_3_E_in ( p1654 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6673 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6674 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6675 ) ,
+ .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) ,
+ .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p1790 ) ,
+ .clk_2_W_in ( p1700 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p1773 ) ,
+ .clk_3_E_in ( p2572 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6679 ) ) ;
+cbx_1__1_ cbx_7__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6680 } ) ,
+ .chanx_left_in ( sb_1__1__60_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__71_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__71_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__71_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__71_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) ,
+ .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p2085 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6681 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[71] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[71] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6682 ) ,
+ .pReset_W_in ( pResetWires[331] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6683 ) ,
+ .pReset_S_out ( pResetWires[333] ) , .pReset_E_out ( pResetWires[332] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[271] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6684 ) ,
+ .prog_clk_1_W_in ( p1894 ) , .prog_clk_1_E_in ( p814 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6685 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6686 ) ,
+ .prog_clk_2_E_in ( p1731 ) , .prog_clk_2_W_in ( p465 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6687 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6688 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[0] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6689 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[1] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_1_W_in ( p2423 ) ,
+ .clk_1_E_in ( p1997 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6691 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6692 ) , .clk_2_E_in ( p1731 ) ,
+ .clk_2_W_in ( p2285 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6693 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6694 ) ,
+ .clk_3_W_in ( clk_3_wires[0] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6695 ) ,
+ .clk_3_E_out ( clk_3_wires[1] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6696 ) ) ;
+cbx_1__1_ cbx_7__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6697 } ) ,
+ .chanx_left_in ( sb_1__1__61_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__72_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__72_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__72_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__72_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) ,
+ .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p1163 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6698 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[72] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[72] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6699 ) ,
+ .pReset_W_in ( pResetWires[380] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6700 ) ,
+ .pReset_S_out ( pResetWires[382] ) , .pReset_E_out ( pResetWires[381] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[274] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6701 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6702 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[149] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[150] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p2498 ) ,
+ .prog_clk_2_W_in ( p636 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6703 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6704 ) ,
+ .prog_clk_3_W_in ( p2393 ) , .prog_clk_3_E_in ( p262 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6705 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6706 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6707 ) ,
+ .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) ,
+ .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p899 ) ,
+ .clk_2_W_in ( p2304 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p2393 ) ,
+ .clk_3_E_in ( p2339 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6711 ) ) ;
+cbx_1__1_ cbx_7__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6712 } ) ,
+ .chanx_left_in ( sb_1__1__62_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__73_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__73_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__73_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__73_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) ,
+ .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p1418 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6713 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[73] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[73] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6714 ) ,
+ .pReset_W_in ( pResetWires[429] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6715 ) ,
+ .pReset_S_out ( pResetWires[431] ) , .pReset_E_out ( pResetWires[430] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[277] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6716 ) ,
+ .prog_clk_1_W_in ( p861 ) , .prog_clk_1_E_in ( p980 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6717 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6718 ) ,
+ .prog_clk_2_E_in ( p2645 ) , .prog_clk_2_W_in ( p819 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6719 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6720 ) ,
+ .prog_clk_3_W_in ( p1879 ) , .prog_clk_3_E_in ( p2064 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6721 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_1_W_in ( p1815 ) ,
+ .clk_1_E_in ( p1299 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6723 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_2_E_in ( p2185 ) ,
+ .clk_2_W_in ( p1630 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p1879 ) ,
+ .clk_3_E_in ( p2537 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6728 ) ) ;
+cbx_1__1_ cbx_7__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6729 } ) ,
+ .chanx_left_in ( sb_1__1__63_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__74_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__74_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__74_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__74_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) ,
+ .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p1145 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6730 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[74] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[74] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6731 ) ,
+ .pReset_W_in ( pResetWires[478] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6732 ) ,
+ .pReset_S_out ( pResetWires[480] ) , .pReset_E_out ( pResetWires[479] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[280] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6733 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6734 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[156] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[157] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p2803 ) ,
+ .prog_clk_2_W_in ( p828 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6735 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6736 ) ,
+ .prog_clk_3_W_in ( p2228 ) , .prog_clk_3_E_in ( p1687 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6737 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6738 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6739 ) ,
+ .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) ,
+ .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p1862 ) ,
+ .clk_2_W_in ( p1978 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p2228 ) ,
+ .clk_3_E_in ( p2762 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6743 ) ) ;
+cbx_1__1_ cbx_7__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6744 } ) ,
+ .chanx_left_in ( sb_1__1__64_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__75_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__75_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__75_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__75_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) ,
+ .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p1947 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6745 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[75] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[75] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6746 ) ,
+ .pReset_W_in ( pResetWires[527] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6747 ) ,
+ .pReset_S_out ( pResetWires[529] ) , .pReset_E_out ( pResetWires[528] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[283] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6748 ) ,
+ .prog_clk_1_W_in ( p1237 ) , .prog_clk_1_E_in ( p89 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6749 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6750 ) ,
+ .prog_clk_2_E_in ( p3008 ) , .prog_clk_2_W_in ( p808 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6751 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6752 ) ,
+ .prog_clk_3_W_in ( p2201 ) , .prog_clk_3_E_in ( p2062 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6753 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_1_W_in ( p1604 ) ,
+ .clk_1_E_in ( p1660 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6755 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_2_E_in ( p2238 ) ,
+ .clk_2_W_in ( p1988 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p2201 ) ,
+ .clk_3_E_in ( p2877 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6760 ) ) ;
+cbx_1__1_ cbx_7__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6761 } ) ,
+ .chanx_left_in ( sb_1__1__65_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__76_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__76_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__76_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__76_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) ,
+ .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1543 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6762 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[76] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[76] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6763 ) ,
+ .pReset_W_in ( pResetWires[576] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6764 ) ,
+ .pReset_S_out ( pResetWires[578] ) , .pReset_E_out ( pResetWires[577] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[286] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6765 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6766 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[163] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[164] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2987 ) ,
+ .prog_clk_2_W_in ( p181 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6767 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6768 ) ,
+ .prog_clk_3_W_in ( p2199 ) , .prog_clk_3_E_in ( p1361 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6769 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6770 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6771 ) ,
+ .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) ,
+ .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p1335 ) ,
+ .clk_2_W_in ( p2016 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2199 ) ,
+ .clk_3_E_in ( p2874 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6775 ) ) ;
+cbx_1__1_ cbx_8__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6776 } ) ,
+ .chanx_left_in ( sb_1__1__66_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__77_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__77_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__77_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__77_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p1831 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6777 ) ,
+ .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[77] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[77] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[77] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6778 ) ,
+ .pReset_W_in ( pResetWires[90] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6779 ) ,
+ .pReset_S_out ( pResetWires[92] ) , .pReset_E_out ( pResetWires[91] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[294] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6780 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[127] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6781 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[131] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p2674 ) ,
+ .prog_clk_2_W_in ( p924 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6782 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6783 ) ,
+ .prog_clk_3_W_in ( p2612 ) , .prog_clk_3_E_in ( p2066 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6784 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6785 ) ,
+ .clk_1_W_in ( clk_1_wires[127] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6786 ) ,
+ .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) ,
+ .clk_2_E_in ( p2128 ) , .clk_2_W_in ( p2553 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6787 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p2612 ) ,
+ .clk_3_E_in ( p2526 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6790 ) ) ;
+cbx_1__1_ cbx_8__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6791 } ) ,
+ .chanx_left_in ( sb_1__1__67_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__78_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__78_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__78_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__78_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p1514 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6792 ) ,
+ .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[78] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[78] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[78] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6793 ) ,
+ .pReset_W_in ( pResetWires[139] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6794 ) ,
+ .pReset_S_out ( pResetWires[141] ) , .pReset_E_out ( pResetWires[140] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[297] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6795 ) ,
+ .prog_clk_1_W_in ( p1223 ) , .prog_clk_1_E_in ( p1086 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6796 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6797 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[71] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6798 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[72] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6799 ) ,
+ .prog_clk_3_W_in ( p1223 ) , .prog_clk_3_E_in ( p1301 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6800 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6801 ) , .clk_1_W_in ( p1223 ) ,
+ .clk_1_E_in ( p92 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6802 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6803 ) ,
+ .clk_2_E_in ( clk_2_wires[71] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6804 ) ,
+ .clk_2_W_out ( clk_2_wires[72] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p1223 ) ,
+ .clk_3_E_in ( p1379 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6807 ) ) ;
+cbx_1__1_ cbx_8__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6808 } ) ,
+ .chanx_left_in ( sb_1__1__68_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__79_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__79_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__79_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__79_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p1876 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6809 ) ,
+ .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[79] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[79] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[79] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6810 ) ,
+ .pReset_W_in ( pResetWires[188] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6811 ) ,
+ .pReset_S_out ( pResetWires[190] ) , .pReset_E_out ( pResetWires[189] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[300] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6812 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[134] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6813 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[138] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p2168 ) ,
+ .prog_clk_2_W_in ( p632 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6814 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6815 ) ,
+ .prog_clk_3_W_in ( p2173 ) , .prog_clk_3_E_in ( p2002 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6816 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6817 ) ,
+ .clk_1_W_in ( clk_1_wires[134] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6818 ) ,
+ .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) ,
+ .clk_2_E_in ( p2073 ) , .clk_2_W_in ( p2018 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6819 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2173 ) ,
+ .clk_3_E_in ( p2049 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6822 ) ) ;
+cbx_1__1_ cbx_8__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6823 } ) ,
+ .chanx_left_in ( sb_1__1__69_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__80_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__80_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__80_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__80_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p2494 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6824 ) ,
+ .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[80] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[80] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[80] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6825 ) ,
+ .pReset_W_in ( pResetWires[237] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6826 ) ,
+ .pReset_S_out ( pResetWires[239] ) , .pReset_E_out ( pResetWires[238] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[303] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6827 ) ,
+ .prog_clk_1_W_in ( p1220 ) , .prog_clk_1_E_in ( p1101 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6828 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6829 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[80] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6830 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[81] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6831 ) ,
+ .prog_clk_3_W_in ( p1445 ) , .prog_clk_3_E_in ( p287 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6832 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6833 ) , .clk_1_W_in ( p1445 ) ,
+ .clk_1_E_in ( p270 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6834 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6835 ) ,
+ .clk_2_E_in ( clk_2_wires[80] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6836 ) ,
+ .clk_2_W_out ( clk_2_wires[81] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1445 ) ,
+ .clk_3_E_in ( p2268 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6839 ) ) ;
+cbx_1__1_ cbx_8__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6840 } ) ,
+ .chanx_left_in ( sb_1__1__70_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__81_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__81_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__81_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__81_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p2092 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6841 ) ,
+ .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[81] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[81] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[81] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6842 ) ,
+ .pReset_W_in ( pResetWires[286] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6843 ) ,
+ .pReset_S_out ( pResetWires[288] ) , .pReset_E_out ( pResetWires[287] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[306] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6844 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[141] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6845 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[145] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p2870 ) ,
+ .prog_clk_2_W_in ( p549 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6846 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6847 ) ,
+ .prog_clk_3_W_in ( p2177 ) , .prog_clk_3_E_in ( p2335 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6848 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6849 ) ,
+ .clk_1_W_in ( clk_1_wires[141] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6850 ) ,
+ .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) ,
+ .clk_2_E_in ( p2446 ) , .clk_2_W_in ( p1998 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6851 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p2177 ) ,
+ .clk_3_E_in ( p2723 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6854 ) ) ;
+cbx_1__1_ cbx_8__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6855 } ) ,
+ .chanx_left_in ( sb_1__1__71_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__82_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__82_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__82_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__82_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1408 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6856 ) ,
+ .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[82] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[82] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[82] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6857 ) ,
+ .pReset_W_in ( pResetWires[335] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6858 ) ,
+ .pReset_S_out ( pResetWires[337] ) , .pReset_E_out ( pResetWires[336] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[309] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6859 ) ,
+ .prog_clk_1_W_in ( p1558 ) , .prog_clk_1_E_in ( p295 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6860 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6861 ) ,
+ .prog_clk_2_E_in ( p1509 ) , .prog_clk_2_W_in ( p1330 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6862 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6863 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[4] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6864 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[5] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_1_W_in ( p1570 ) ,
+ .clk_1_E_in ( p1155 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6866 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_2_E_in ( p1509 ) ,
+ .clk_2_W_in ( p1376 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6868 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6869 ) ,
+ .clk_3_W_in ( clk_3_wires[4] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6870 ) ,
+ .clk_3_E_out ( clk_3_wires[5] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6871 ) ) ;
+cbx_1__1_ cbx_8__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6872 } ) ,
+ .chanx_left_in ( sb_1__1__72_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__83_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__83_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__83_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__83_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p1902 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6873 ) ,
+ .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[83] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[83] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[83] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6874 ) ,
+ .pReset_W_in ( pResetWires[384] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6875 ) ,
+ .pReset_S_out ( pResetWires[386] ) , .pReset_E_out ( pResetWires[385] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[312] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6876 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[148] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6877 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[152] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p2109 ) ,
+ .prog_clk_2_W_in ( p496 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6878 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6879 ) ,
+ .prog_clk_3_W_in ( p2425 ) , .prog_clk_3_E_in ( p2282 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6880 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6881 ) ,
+ .clk_1_W_in ( clk_1_wires[148] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6882 ) ,
+ .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) ,
+ .clk_2_E_in ( p2410 ) , .clk_2_W_in ( p2300 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6883 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p2425 ) ,
+ .clk_3_E_in ( p1985 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6886 ) ) ;
+cbx_1__1_ cbx_8__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6887 } ) ,
+ .chanx_left_in ( sb_1__1__73_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__84_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__84_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__84_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__84_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p1853 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6888 ) ,
+ .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[84] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[84] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[84] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6889 ) ,
+ .pReset_W_in ( pResetWires[433] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6890 ) ,
+ .pReset_S_out ( pResetWires[435] ) , .pReset_E_out ( pResetWires[434] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[315] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6891 ) ,
+ .prog_clk_1_W_in ( p1224 ) , .prog_clk_1_E_in ( p964 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6892 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6893 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[93] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6894 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[94] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6895 ) ,
+ .prog_clk_3_W_in ( p1476 ) , .prog_clk_3_E_in ( p259 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6896 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6897 ) , .clk_1_W_in ( p1476 ) ,
+ .clk_1_E_in ( p2 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6898 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6899 ) ,
+ .clk_2_E_in ( clk_2_wires[93] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6900 ) ,
+ .clk_2_W_out ( clk_2_wires[94] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p1476 ) ,
+ .clk_3_E_in ( p1662 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6903 ) ) ;
+cbx_1__1_ cbx_8__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6904 } ) ,
+ .chanx_left_in ( sb_1__1__74_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__85_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__85_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__85_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__85_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p2431 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6905 ) ,
+ .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[85] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[85] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[85] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6906 ) ,
+ .pReset_W_in ( pResetWires[482] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6907 ) ,
+ .pReset_S_out ( pResetWires[484] ) , .pReset_E_out ( pResetWires[483] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[318] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6908 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[155] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6909 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[159] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p3016 ) ,
+ .prog_clk_2_W_in ( p539 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6910 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6911 ) ,
+ .prog_clk_3_W_in ( p2239 ) , .prog_clk_3_E_in ( p2348 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6912 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6913 ) ,
+ .clk_1_W_in ( clk_1_wires[155] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6914 ) ,
+ .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) ,
+ .clk_2_E_in ( p2422 ) , .clk_2_W_in ( p1963 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6915 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p2239 ) ,
+ .clk_3_E_in ( p2893 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6918 ) ) ;
+cbx_1__1_ cbx_8__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6919 } ) ,
+ .chanx_left_in ( sb_1__1__75_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__86_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__86_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__86_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__86_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p1788 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6920 ) ,
+ .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[86] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[86] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[86] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6921 ) ,
+ .pReset_W_in ( pResetWires[531] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6922 ) ,
+ .pReset_S_out ( pResetWires[533] ) , .pReset_E_out ( pResetWires[532] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[321] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6923 ) ,
+ .prog_clk_1_W_in ( p1427 ) , .prog_clk_1_E_in ( p243 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6924 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6925 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[106] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6926 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[107] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6927 ) ,
+ .prog_clk_3_W_in ( p1528 ) , .prog_clk_3_E_in ( p2277 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6928 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6929 ) , .clk_1_W_in ( p1528 ) ,
+ .clk_1_E_in ( p1028 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6930 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6931 ) ,
+ .clk_2_E_in ( clk_2_wires[106] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6932 ) ,
+ .clk_2_W_out ( clk_2_wires[107] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1528 ) ,
+ .clk_3_E_in ( p1675 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6935 ) ) ;
+cbx_1__1_ cbx_8__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6936 } ) ,
+ .chanx_left_in ( sb_1__1__76_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__87_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__87_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__87_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__87_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p1493 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6937 ) ,
+ .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[87] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[87] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[87] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6938 ) ,
+ .pReset_W_in ( pResetWires[580] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6939 ) ,
+ .pReset_S_out ( pResetWires[582] ) , .pReset_E_out ( pResetWires[581] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[324] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6940 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[162] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6941 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[166] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p2823 ) ,
+ .prog_clk_2_W_in ( p391 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6942 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6943 ) ,
+ .prog_clk_3_W_in ( p2394 ) , .prog_clk_3_E_in ( p2010 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6944 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6945 ) ,
+ .clk_1_W_in ( clk_1_wires[162] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6946 ) ,
+ .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) ,
+ .clk_2_E_in ( p2176 ) , .clk_2_W_in ( p2325 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6947 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2394 ) ,
+ .clk_3_E_in ( p2752 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6950 ) ) ;
+cbx_1__1_ cbx_9__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6951 } ) ,
+ .chanx_left_in ( sb_1__1__77_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__88_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__88_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__88_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__88_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) ,
+ .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p1872 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6952 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[88] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[88] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6953 ) ,
+ .pReset_W_in ( pResetWires[94] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6954 ) ,
+ .pReset_S_out ( pResetWires[96] ) , .pReset_E_out ( pResetWires[95] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[332] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6955 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6956 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[170] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[171] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p2605 ) ,
+ .prog_clk_2_W_in ( p494 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6957 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6958 ) ,
+ .prog_clk_3_W_in ( p2072 ) , .prog_clk_3_E_in ( p1378 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6959 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6960 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6961 ) ,
+ .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) ,
+ .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p1609 ) ,
+ .clk_2_W_in ( p1987 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p2072 ) ,
+ .clk_3_E_in ( p2542 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6965 ) ) ;
+cbx_1__1_ cbx_9__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6966 } ) ,
+ .chanx_left_in ( sb_1__1__78_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__89_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__89_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__89_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__89_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) ,
+ .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1820 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6967 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[89] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[89] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6968 ) ,
+ .pReset_W_in ( pResetWires[143] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6969 ) ,
+ .pReset_S_out ( pResetWires[145] ) , .pReset_E_out ( pResetWires[144] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[335] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6970 ) ,
+ .prog_clk_1_W_in ( p1203 ) , .prog_clk_1_E_in ( p323 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6971 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6972 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6973 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[69] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6974 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1460 ) ,
+ .prog_clk_3_E_in ( p1682 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6975 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6976 ) , .clk_1_W_in ( p1460 ) ,
+ .clk_1_E_in ( p1670 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6977 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6978 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6979 ) ,
+ .clk_2_W_in ( clk_2_wires[69] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6980 ) ,
+ .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1460 ) ,
+ .clk_3_E_in ( p159 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6982 ) ) ;
+cbx_1__1_ cbx_9__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6983 } ) ,
+ .chanx_left_in ( sb_1__1__79_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__90_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__90_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__90_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__90_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) ,
+ .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p629 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6984 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[90] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[90] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6985 ) ,
+ .pReset_W_in ( pResetWires[192] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6986 ) ,
+ .pReset_S_out ( pResetWires[194] ) , .pReset_E_out ( pResetWires[193] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[338] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6987 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6988 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[177] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[178] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p2963 ) ,
+ .prog_clk_2_W_in ( p230 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6989 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6990 ) ,
+ .prog_clk_3_W_in ( p2863 ) , .prog_clk_3_E_in ( p1996 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6991 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6992 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6993 ) ,
+ .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) ,
+ .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p2087 ) ,
+ .clk_2_W_in ( p2717 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p2863 ) ,
+ .clk_3_E_in ( p2876 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6997 ) ) ;
+cbx_1__1_ cbx_9__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6998 } ) ,
+ .chanx_left_in ( sb_1__1__80_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__91_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__91_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__91_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__91_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) ,
+ .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1172 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6999 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[91] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[91] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7000 ) ,
+ .pReset_W_in ( pResetWires[241] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7001 ) ,
+ .pReset_S_out ( pResetWires[243] ) , .pReset_E_out ( pResetWires[242] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[341] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7002 ) ,
+ .prog_clk_1_W_in ( p824 ) , .prog_clk_1_E_in ( p976 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7003 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7004 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7005 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[78] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7006 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p1106 ) ,
+ .prog_clk_3_E_in ( p1664 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7007 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7008 ) , .clk_1_W_in ( p1106 ) ,
+ .clk_1_E_in ( p150 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7009 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7010 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7011 ) ,
+ .clk_2_W_in ( clk_2_wires[78] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7012 ) ,
+ .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p1106 ) ,
+ .clk_3_E_in ( p656 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7014 ) ) ;
+cbx_1__1_ cbx_9__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7015 } ) ,
+ .chanx_left_in ( sb_1__1__81_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__92_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__92_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__92_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__92_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) ,
+ .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1252 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7016 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[92] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[92] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7017 ) ,
+ .pReset_W_in ( pResetWires[290] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7018 ) ,
+ .pReset_S_out ( pResetWires[292] ) , .pReset_E_out ( pResetWires[291] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[344] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7019 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7020 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[184] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[185] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p3110 ) ,
+ .prog_clk_2_W_in ( p763 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7021 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7022 ) ,
+ .prog_clk_3_W_in ( p1892 ) , .prog_clk_3_E_in ( p2768 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7023 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7024 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7025 ) ,
+ .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) ,
+ .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p2871 ) ,
+ .clk_2_W_in ( p1643 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p1892 ) ,
+ .clk_3_E_in ( p3020 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7029 ) ) ;
+cbx_1__1_ cbx_9__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7030 } ) ,
+ .chanx_left_in ( sb_1__1__82_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__93_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__93_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__93_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__93_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) ,
+ .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1534 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7031 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[93] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[93] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7032 ) ,
+ .pReset_W_in ( pResetWires[339] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7033 ) ,
+ .pReset_S_out ( pResetWires[341] ) , .pReset_E_out ( pResetWires[340] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[347] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7034 ) ,
+ .prog_clk_1_W_in ( p1073 ) , .prog_clk_1_E_in ( p1277 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7035 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7036 ) ,
+ .prog_clk_2_E_in ( p1399 ) , .prog_clk_2_W_in ( p715 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7037 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7038 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[44] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7039 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[45] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_1_W_in ( p1891 ) ,
+ .clk_1_E_in ( p1394 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7041 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7042 ) , .clk_2_E_in ( p1399 ) ,
+ .clk_2_W_in ( p1666 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7043 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7044 ) ,
+ .clk_3_W_in ( clk_3_wires[44] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7045 ) ,
+ .clk_3_E_out ( clk_3_wires[45] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7046 ) ) ;
+cbx_1__1_ cbx_9__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7047 } ) ,
+ .chanx_left_in ( sb_1__1__83_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__94_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__94_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__94_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__94_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) ,
+ .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1415 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7048 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[94] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[94] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7049 ) ,
+ .pReset_W_in ( pResetWires[388] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7050 ) ,
+ .pReset_S_out ( pResetWires[390] ) , .pReset_E_out ( pResetWires[389] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[350] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7051 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7052 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[191] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[192] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p2460 ) ,
+ .prog_clk_2_W_in ( p482 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7053 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7054 ) ,
+ .prog_clk_3_W_in ( p2370 ) , .prog_clk_3_E_in ( p1746 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7055 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7056 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7057 ) ,
+ .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) ,
+ .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p1776 ) ,
+ .clk_2_W_in ( p2252 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p2370 ) ,
+ .clk_3_E_in ( p2307 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7061 ) ) ;
+cbx_1__1_ cbx_9__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7062 } ) ,
+ .chanx_left_in ( sb_1__1__84_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__95_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__95_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__95_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__95_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) ,
+ .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p1436 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7063 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[95] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[95] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7064 ) ,
+ .pReset_W_in ( pResetWires[437] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7065 ) ,
+ .pReset_S_out ( pResetWires[439] ) , .pReset_E_out ( pResetWires[438] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[353] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7066 ) ,
+ .prog_clk_1_W_in ( p1119 ) , .prog_clk_1_E_in ( p1221 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7067 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7068 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7069 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[91] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7070 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1119 ) ,
+ .prog_clk_3_E_in ( p213 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7071 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) , .clk_1_W_in ( p1119 ) ,
+ .clk_1_E_in ( p1334 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7073 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7074 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7075 ) ,
+ .clk_2_W_in ( clk_2_wires[91] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7076 ) ,
+ .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1119 ) ,
+ .clk_3_E_in ( p645 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7078 ) ) ;
+cbx_1__1_ cbx_9__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7079 } ) ,
+ .chanx_left_in ( sb_1__1__85_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__96_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__96_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__96_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__96_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) ,
+ .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1398 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7080 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[96] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[96] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7081 ) ,
+ .pReset_W_in ( pResetWires[486] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7082 ) ,
+ .pReset_S_out ( pResetWires[488] ) , .pReset_E_out ( pResetWires[487] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[356] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7083 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7084 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[198] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[199] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p3010 ) ,
+ .prog_clk_2_W_in ( p0 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7085 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7086 ) ,
+ .prog_clk_3_W_in ( p1569 ) , .prog_clk_3_E_in ( p2056 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7087 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7088 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7089 ) ,
+ .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) ,
+ .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p2152 ) ,
+ .clk_2_W_in ( p1311 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p1569 ) ,
+ .clk_3_E_in ( p2879 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7093 ) ) ;
+cbx_1__1_ cbx_9__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7094 } ) ,
+ .chanx_left_in ( sb_1__1__86_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__97_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__97_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__97_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__97_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) ,
+ .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p1503 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7095 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[97] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[97] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7096 ) ,
+ .pReset_W_in ( pResetWires[535] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7097 ) ,
+ .pReset_S_out ( pResetWires[537] ) , .pReset_E_out ( pResetWires[536] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[359] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7098 ) ,
+ .prog_clk_1_W_in ( p1505 ) , .prog_clk_1_E_in ( p1177 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7099 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7100 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7101 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[104] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7102 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p1533 ) ,
+ .prog_clk_3_E_in ( p1624 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7103 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7104 ) , .clk_1_W_in ( p1533 ) ,
+ .clk_1_E_in ( p1298 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7105 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7106 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7107 ) ,
+ .clk_2_W_in ( clk_2_wires[104] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7108 ) ,
+ .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p1533 ) ,
+ .clk_3_E_in ( p226 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7110 ) ) ;
+cbx_1__1_ cbx_9__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7111 } ) ,
+ .chanx_left_in ( sb_1__1__87_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__98_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__98_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__98_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__98_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) ,
+ .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1596 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7112 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[98] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[98] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7113 ) ,
+ .pReset_W_in ( pResetWires[584] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7114 ) ,
+ .pReset_S_out ( pResetWires[586] ) , .pReset_E_out ( pResetWires[585] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[362] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7115 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7116 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[205] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[206] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p2851 ) ,
+ .prog_clk_2_W_in ( p762 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7117 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7118 ) ,
+ .prog_clk_3_W_in ( p2653 ) , .prog_clk_3_E_in ( p2020 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7119 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7120 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7121 ) ,
+ .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) ,
+ .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p2202 ) ,
+ .clk_2_W_in ( p2558 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p2653 ) ,
+ .clk_3_E_in ( p2766 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7125 ) ) ;
+cbx_1__1_ cbx_10__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7126 } ) ,
+ .chanx_left_in ( sb_1__1__88_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__99_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__99_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__99_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__99_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1932 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7127 ) ,
+ .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[99] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[99] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[99] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7128 ) ,
+ .pReset_W_in ( pResetWires[98] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7129 ) ,
+ .pReset_S_out ( pResetWires[100] ) , .pReset_E_out ( pResetWires[99] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[370] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7130 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[169] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7131 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[173] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p3198 ) ,
+ .prog_clk_2_W_in ( p1231 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7132 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7133 ) ,
+ .prog_clk_3_W_in ( p1201 ) , .prog_clk_3_E_in ( p1381 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7134 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7135 ) ,
+ .clk_1_W_in ( clk_1_wires[169] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7136 ) ,
+ .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) ,
+ .clk_2_E_in ( p1168 ) , .clk_2_W_in ( p1109 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7137 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p1201 ) ,
+ .clk_3_E_in ( p3174 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7140 ) ) ;
+cbx_1__1_ cbx_10__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7141 } ) ,
+ .chanx_left_in ( sb_1__1__89_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__100_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__100_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__100_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__100_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p974 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7142 ) ,
+ .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[100] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[100] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[100] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7143 ) ,
+ .pReset_W_in ( pResetWires[147] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7144 ) ,
+ .pReset_S_out ( pResetWires[149] ) , .pReset_E_out ( pResetWires[148] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[373] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7145 ) ,
+ .prog_clk_1_W_in ( p1444 ) , .prog_clk_1_E_in ( p2083 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7146 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7147 ) ,
+ .prog_clk_2_E_in ( p2867 ) , .prog_clk_2_W_in ( p1396 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7148 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7149 ) ,
+ .prog_clk_3_W_in ( p2592 ) , .prog_clk_3_E_in ( p2131 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7150 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_1_W_in ( p2187 ) ,
+ .clk_1_E_in ( p2039 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7152 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_2_E_in ( p2099 ) ,
+ .clk_2_W_in ( p2576 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2592 ) ,
+ .clk_3_E_in ( p2771 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7157 ) ) ;
+cbx_1__1_ cbx_10__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7158 } ) ,
+ .chanx_left_in ( sb_1__1__90_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__101_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__101_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__101_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__101_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p1751 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7159 ) ,
+ .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[101] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[101] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[101] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7160 ) ,
+ .pReset_W_in ( pResetWires[196] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7161 ) ,
+ .pReset_S_out ( pResetWires[198] ) , .pReset_E_out ( pResetWires[197] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[376] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7162 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[176] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7163 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[180] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2795 ) ,
+ .prog_clk_2_W_in ( p1118 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7164 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7165 ) ,
+ .prog_clk_3_W_in ( p1754 ) , .prog_clk_3_E_in ( p1865 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7166 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7167 ) ,
+ .clk_1_W_in ( clk_1_wires[176] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7168 ) ,
+ .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) ,
+ .clk_2_E_in ( p1928 ) , .clk_2_W_in ( p1683 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7169 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p1754 ) ,
+ .clk_3_E_in ( p2773 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7172 ) ) ;
+cbx_1__1_ cbx_10__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7173 } ) ,
+ .chanx_left_in ( sb_1__1__91_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__102_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__102_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__102_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__102_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p1013 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7174 ) ,
+ .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[102] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[102] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[102] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7175 ) ,
+ .pReset_W_in ( pResetWires[245] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7176 ) ,
+ .pReset_S_out ( pResetWires[247] ) , .pReset_E_out ( pResetWires[246] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[379] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7177 ) ,
+ .prog_clk_1_W_in ( p1234 ) , .prog_clk_1_E_in ( p2038 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7178 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7179 ) ,
+ .prog_clk_2_E_in ( p1456 ) , .prog_clk_2_W_in ( p1352 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7180 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7181 ) ,
+ .prog_clk_3_W_in ( p2059 ) , .prog_clk_3_E_in ( p1721 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7182 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_1_W_in ( p2059 ) ,
+ .clk_1_E_in ( p2134 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7184 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_2_E_in ( p1888 ) ,
+ .clk_2_W_in ( p2169 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p2059 ) ,
+ .clk_3_E_in ( p1426 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7189 ) ) ;
+cbx_1__1_ cbx_10__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7190 } ) ,
+ .chanx_left_in ( sb_1__1__92_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__103_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__103_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__103_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__103_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p1844 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7191 ) ,
+ .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[103] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[103] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[103] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7192 ) ,
+ .pReset_W_in ( pResetWires[294] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7193 ) ,
+ .pReset_S_out ( pResetWires[296] ) , .pReset_E_out ( pResetWires[295] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[382] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7194 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[183] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7195 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[187] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p3183 ) ,
+ .prog_clk_2_W_in ( p785 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7196 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7197 ) ,
+ .prog_clk_3_W_in ( p969 ) , .prog_clk_3_E_in ( p2318 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7198 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7199 ) ,
+ .clk_1_W_in ( clk_1_wires[183] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7200 ) ,
+ .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) ,
+ .clk_2_E_in ( p2433 ) , .clk_2_W_in ( p1016 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7201 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p969 ) ,
+ .clk_3_E_in ( p3172 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7204 ) ) ;
+cbx_1__1_ cbx_10__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7205 } ) ,
+ .chanx_left_in ( sb_1__1__93_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__104_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__104_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__104_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__104_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1248 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7206 ) ,
+ .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[104] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[104] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[104] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7207 ) ,
+ .pReset_W_in ( pResetWires[343] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7208 ) ,
+ .pReset_S_out ( pResetWires[345] ) , .pReset_E_out ( pResetWires[344] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[385] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7209 ) ,
+ .prog_clk_1_W_in ( p1495 ) , .prog_clk_1_E_in ( p1537 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7210 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7211 ) ,
+ .prog_clk_2_E_in ( p1248 ) , .prog_clk_2_W_in ( p1383 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7212 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7213 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[48] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7214 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[49] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_1_W_in ( p1824 ) ,
+ .clk_1_E_in ( p1331 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7216 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7217 ) , .clk_2_E_in ( p1248 ) ,
+ .clk_2_W_in ( p1739 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7218 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7219 ) ,
+ .clk_3_W_in ( clk_3_wires[48] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7220 ) ,
+ .clk_3_E_out ( clk_3_wires[49] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7221 ) ) ;
+cbx_1__1_ cbx_10__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7222 } ) ,
+ .chanx_left_in ( sb_1__1__94_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__105_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__105_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__105_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__105_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p2082 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7223 ) ,
+ .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[105] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[105] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[105] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7224 ) ,
+ .pReset_W_in ( pResetWires[392] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7225 ) ,
+ .pReset_S_out ( pResetWires[394] ) , .pReset_E_out ( pResetWires[393] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[388] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7226 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[190] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7227 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[194] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p3072 ) ,
+ .prog_clk_2_W_in ( p1123 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7228 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7229 ) ,
+ .prog_clk_3_W_in ( p2465 ) , .prog_clk_3_E_in ( p2599 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7230 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7231 ) ,
+ .clk_1_W_in ( clk_1_wires[190] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7232 ) ,
+ .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) ,
+ .clk_2_E_in ( p2629 ) , .clk_2_W_in ( p2326 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7233 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p2391 ) ,
+ .clk_3_E_in ( p3060 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7236 ) ) ;
+cbx_1__1_ cbx_10__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7237 } ) ,
+ .chanx_left_in ( sb_1__1__95_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__106_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__106_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__106_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__106_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p2203 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7238 ) ,
+ .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[106] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[106] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[106] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7239 ) ,
+ .pReset_W_in ( pResetWires[441] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7240 ) ,
+ .pReset_S_out ( pResetWires[443] ) , .pReset_E_out ( pResetWires[442] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[391] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7241 ) ,
+ .prog_clk_1_W_in ( p1198 ) , .prog_clk_1_E_in ( p2194 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7242 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7243 ) ,
+ .prog_clk_2_E_in ( p3108 ) , .prog_clk_2_W_in ( p1171 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7244 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7245 ) ,
+ .prog_clk_3_W_in ( p1924 ) , .prog_clk_3_E_in ( p2374 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7246 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_1_W_in ( p1924 ) ,
+ .clk_1_E_in ( p1982 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7248 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_2_E_in ( p2456 ) ,
+ .clk_2_W_in ( p1719 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p1924 ) ,
+ .clk_3_E_in ( p3065 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7253 ) ) ;
+cbx_1__1_ cbx_10__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7254 } ) ,
+ .chanx_left_in ( sb_1__1__96_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__107_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__107_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__107_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__107_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p1540 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7255 ) ,
+ .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[107] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[107] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[107] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7256 ) ,
+ .pReset_W_in ( pResetWires[490] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7257 ) ,
+ .pReset_S_out ( pResetWires[492] ) , .pReset_E_out ( pResetWires[491] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[394] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7258 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[197] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7259 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[201] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p2225 ) ,
+ .prog_clk_2_W_in ( p1192 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7260 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7261 ) ,
+ .prog_clk_3_W_in ( p1940 ) , .prog_clk_3_E_in ( p2575 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7262 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7263 ) ,
+ .clk_1_W_in ( clk_1_wires[197] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7264 ) ,
+ .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) ,
+ .clk_2_E_in ( p2608 ) , .clk_2_W_in ( p1722 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7265 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p1940 ) ,
+ .clk_3_E_in ( p2113 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7268 ) ) ;
+cbx_1__1_ cbx_10__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7269 } ) ,
+ .chanx_left_in ( sb_1__1__97_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__108_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__108_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__108_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__108_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1768 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7270 ) ,
+ .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[108] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[108] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[108] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7271 ) ,
+ .pReset_W_in ( pResetWires[539] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7272 ) ,
+ .pReset_S_out ( pResetWires[541] ) , .pReset_E_out ( pResetWires[540] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[397] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7273 ) ,
+ .prog_clk_1_W_in ( p1098 ) , .prog_clk_1_E_in ( p908 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7274 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7275 ) ,
+ .prog_clk_2_E_in ( p1939 ) , .prog_clk_2_W_in ( p1230 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7276 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7277 ) ,
+ .prog_clk_3_W_in ( p1230 ) , .prog_clk_3_E_in ( p1728 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7278 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_1_W_in ( p1230 ) ,
+ .clk_1_E_in ( p908 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7280 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_2_E_in ( p1728 ) ,
+ .clk_2_W_in ( p1230 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1230 ) ,
+ .clk_3_E_in ( p1939 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7285 ) ) ;
+cbx_1__1_ cbx_10__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7286 } ) ,
+ .chanx_left_in ( sb_1__1__98_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__109_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__109_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__109_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__109_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p1936 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7287 ) ,
+ .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[109] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[109] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[109] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7288 ) ,
+ .pReset_W_in ( pResetWires[588] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7289 ) ,
+ .pReset_S_out ( pResetWires[590] ) , .pReset_E_out ( pResetWires[589] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[400] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7290 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[204] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7291 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[208] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p2483 ) ,
+ .prog_clk_2_W_in ( p1590 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7292 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7293 ) ,
+ .prog_clk_3_W_in ( p1910 ) , .prog_clk_3_E_in ( p1564 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7294 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7295 ) ,
+ .clk_1_W_in ( clk_1_wires[204] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7296 ) ,
+ .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) ,
+ .clk_2_E_in ( p1466 ) , .clk_2_W_in ( p1738 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7297 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p1910 ) ,
+ .clk_3_E_in ( p2360 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7300 ) ) ;
+cbx_1__1_ cbx_11__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7301 } ) ,
+ .chanx_left_in ( sb_1__1__99_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__110_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__110_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__110_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__110_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) ,
+ .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1736 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7302 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[110] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[110] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7303 ) ,
+ .pReset_W_in ( pResetWires[102] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7304 ) ,
+ .pReset_S_out ( pResetWires[104] ) , .pReset_E_out ( pResetWires[103] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[408] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7305 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7306 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[212] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[213] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p2702 ) ,
+ .prog_clk_2_W_in ( p628 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7307 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7308 ) ,
+ .prog_clk_3_W_in ( p1417 ) , .prog_clk_3_E_in ( p2044 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7309 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7310 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7311 ) ,
+ .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) ,
+ .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p2230 ) ,
+ .clk_2_W_in ( p1370 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p1417 ) ,
+ .clk_3_E_in ( p2566 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7315 ) ) ;
+cbx_1__1_ cbx_11__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7316 } ) ,
+ .chanx_left_in ( sb_1__1__100_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__111_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__111_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__111_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__111_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) ,
+ .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p1517 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7317 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[111] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[111] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7318 ) ,
+ .pReset_W_in ( pResetWires[151] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7319 ) ,
+ .pReset_S_out ( pResetWires[153] ) , .pReset_E_out ( pResetWires[152] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[411] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7320 ) ,
+ .prog_clk_1_W_in ( p1529 ) , .prog_clk_1_E_in ( p1006 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7321 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7322 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7323 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[114] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7324 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p1921 ) ,
+ .prog_clk_3_E_in ( p2334 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7325 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7326 ) , .clk_1_W_in ( p1794 ) ,
+ .clk_1_E_in ( p1369 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7327 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7328 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7329 ) ,
+ .clk_2_W_in ( clk_2_wires[114] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7330 ) ,
+ .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1921 ) ,
+ .clk_3_E_in ( p1233 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7332 ) ) ;
+cbx_1__1_ cbx_11__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7333 } ) ,
+ .chanx_left_in ( sb_1__1__101_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__112_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__112_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__112_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__112_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) ,
+ .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p1187 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7334 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[112] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[112] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7335 ) ,
+ .pReset_W_in ( pResetWires[200] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7336 ) ,
+ .pReset_S_out ( pResetWires[202] ) , .pReset_E_out ( pResetWires[201] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[414] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7337 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7338 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[219] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[220] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2611 ) ,
+ .prog_clk_2_W_in ( p869 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7339 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7340 ) ,
+ .prog_clk_3_W_in ( p1371 ) , .prog_clk_3_E_in ( p1778 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7341 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7342 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7343 ) ,
+ .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) ,
+ .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p1875 ) ,
+ .clk_2_W_in ( p1390 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p1371 ) ,
+ .clk_3_E_in ( p2569 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7347 ) ) ;
+cbx_1__1_ cbx_11__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7348 } ) ,
+ .chanx_left_in ( sb_1__1__102_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__113_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__113_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__113_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__113_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) ,
+ .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1775 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7349 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[113] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[113] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7350 ) ,
+ .pReset_W_in ( pResetWires[249] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7351 ) ,
+ .pReset_S_out ( pResetWires[251] ) , .pReset_E_out ( pResetWires[250] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[417] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7352 ) ,
+ .prog_clk_1_W_in ( p1125 ) , .prog_clk_1_E_in ( p1688 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7353 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7354 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7355 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[119] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7356 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1125 ) ,
+ .prog_clk_3_E_in ( p1339 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7357 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7358 ) , .clk_1_W_in ( p1125 ) ,
+ .clk_1_E_in ( p1798 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7359 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7360 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7361 ) ,
+ .clk_2_W_in ( clk_2_wires[119] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7362 ) ,
+ .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1125 ) ,
+ .clk_3_E_in ( p1103 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7364 ) ) ;
+cbx_1__1_ cbx_11__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7365 } ) ,
+ .chanx_left_in ( sb_1__1__103_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__114_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__114_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__114_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__114_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) ,
+ .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p1566 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7366 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[114] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[114] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7367 ) ,
+ .pReset_W_in ( pResetWires[298] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7368 ) ,
+ .pReset_S_out ( pResetWires[300] ) , .pReset_E_out ( pResetWires[299] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[420] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7369 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7370 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[226] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[227] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p2447 ) ,
+ .prog_clk_2_W_in ( p381 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7371 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7372 ) ,
+ .prog_clk_3_W_in ( p1575 ) , .prog_clk_3_E_in ( p1814 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7373 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7374 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7375 ) ,
+ .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) ,
+ .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p1516 ) ,
+ .clk_2_W_in ( p1256 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p1575 ) ,
+ .clk_3_E_in ( p2346 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7379 ) ) ;
+cbx_1__1_ cbx_11__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7380 } ) ,
+ .chanx_left_in ( sb_1__1__104_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__115_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__115_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__115_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__115_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) ,
+ .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p1227 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7381 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[115] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[115] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7382 ) ,
+ .pReset_W_in ( pResetWires[347] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7383 ) ,
+ .pReset_S_out ( pResetWires[349] ) , .pReset_E_out ( pResetWires[348] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[423] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7384 ) ,
+ .prog_clk_1_W_in ( p1238 ) , .prog_clk_1_E_in ( p1615 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7385 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7386 ) ,
+ .prog_clk_2_E_in ( p2836 ) , .prog_clk_2_W_in ( p928 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7387 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7388 ) ,
+ .prog_clk_3_W_in ( p2141 ) , .prog_clk_3_E_in ( p2363 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7389 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_1_W_in ( p2144 ) ,
+ .clk_1_E_in ( p1863 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7391 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_2_E_in ( p2452 ) ,
+ .clk_2_W_in ( p2033 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2141 ) ,
+ .clk_3_E_in ( p2772 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7396 ) ) ;
+cbx_1__1_ cbx_11__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7397 } ) ,
+ .chanx_left_in ( sb_1__1__105_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__116_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__116_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__116_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__116_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) ,
+ .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1479 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7398 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[116] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[116] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7399 ) ,
+ .pReset_W_in ( pResetWires[396] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7400 ) ,
+ .pReset_S_out ( pResetWires[398] ) , .pReset_E_out ( pResetWires[397] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[426] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7401 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7402 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[233] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[234] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p3339 ) ,
+ .prog_clk_2_W_in ( p655 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7403 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7404 ) ,
+ .prog_clk_3_W_in ( p1554 ) , .prog_clk_3_E_in ( p1018 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7405 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7406 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7407 ) ,
+ .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) ,
+ .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p851 ) ,
+ .clk_2_W_in ( p1343 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p1554 ) ,
+ .clk_3_E_in ( p3332 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7411 ) ) ;
+cbx_1__1_ cbx_11__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7412 } ) ,
+ .chanx_left_in ( sb_1__1__106_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__117_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__117_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__117_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__117_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) ,
+ .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p1459 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7413 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[117] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[117] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7414 ) ,
+ .pReset_W_in ( pResetWires[445] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7415 ) ,
+ .pReset_S_out ( pResetWires[447] ) , .pReset_E_out ( pResetWires[446] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[429] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7416 ) ,
+ .prog_clk_1_W_in ( p1178 ) , .prog_clk_1_E_in ( p1179 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7417 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7418 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7419 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[126] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7420 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1178 ) ,
+ .prog_clk_3_E_in ( p1365 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7421 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7422 ) , .clk_1_W_in ( p1178 ) ,
+ .clk_1_E_in ( p1340 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7423 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7424 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7425 ) ,
+ .clk_2_W_in ( clk_2_wires[126] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7426 ) ,
+ .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1178 ) ,
+ .clk_3_E_in ( p895 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7428 ) ) ;
+cbx_1__1_ cbx_11__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7429 } ) ,
+ .chanx_left_in ( sb_1__1__107_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__118_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__118_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__118_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__118_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) ,
+ .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p1425 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7430 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[118] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[118] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7431 ) ,
+ .pReset_W_in ( pResetWires[494] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7432 ) ,
+ .pReset_S_out ( pResetWires[496] ) , .pReset_E_out ( pResetWires[495] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[432] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7433 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7434 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[240] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[241] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p3207 ) ,
+ .prog_clk_2_W_in ( p1071 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7435 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7436 ) ,
+ .prog_clk_3_W_in ( p2135 ) , .prog_clk_3_E_in ( p2362 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7437 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7438 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7439 ) ,
+ .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) ,
+ .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p2372 ) ,
+ .clk_2_W_in ( p2023 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p2135 ) ,
+ .clk_3_E_in ( p3164 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7443 ) ) ;
+cbx_1__1_ cbx_11__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7444 } ) ,
+ .chanx_left_in ( sb_1__1__108_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__119_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__119_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__119_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__119_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) ,
+ .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p1854 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7445 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[119] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[119] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7446 ) ,
+ .pReset_W_in ( pResetWires[543] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7447 ) ,
+ .pReset_S_out ( pResetWires[545] ) , .pReset_E_out ( pResetWires[544] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[435] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7448 ) ,
+ .prog_clk_1_W_in ( p1097 ) , .prog_clk_1_E_in ( p1565 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7449 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7450 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7451 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[133] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7452 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1513 ) ,
+ .prog_clk_3_E_in ( p2025 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7453 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7454 ) , .clk_1_W_in ( p1513 ) ,
+ .clk_1_E_in ( p1706 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7455 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7456 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7457 ) ,
+ .clk_2_W_in ( clk_2_wires[133] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7458 ) ,
+ .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1513 ) ,
+ .clk_3_E_in ( p1413 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7460 ) ) ;
+cbx_1__1_ cbx_11__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7461 } ) ,
+ .chanx_left_in ( sb_1__1__109_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__120_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__120_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__120_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__120_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) ,
+ .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1467 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7462 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[120] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[120] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7463 ) ,
+ .pReset_W_in ( pResetWires[592] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7464 ) ,
+ .pReset_S_out ( pResetWires[594] ) , .pReset_E_out ( pResetWires[593] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[438] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7465 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7466 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[247] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[248] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p2089 ) ,
+ .prog_clk_2_W_in ( p1162 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7467 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7468 ) ,
+ .prog_clk_3_W_in ( p2703 ) , .prog_clk_3_E_in ( p1796 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7469 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7470 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7471 ) ,
+ .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) ,
+ .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p1861 ) ,
+ .clk_2_W_in ( p2584 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p2703 ) ,
+ .clk_3_E_in ( p2029 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7475 ) ) ;
+cbx_1__1_ cbx_12__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7476 } ) ,
+ .chanx_left_in ( sb_1__1__110_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__121_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__121_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p1523 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7477 ) ,
+ .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[121] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[121] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[121] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7478 ) ,
+ .pReset_W_in ( pResetWires[106] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7479 ) ,
+ .pReset_S_out ( pResetWires[108] ) , .pReset_E_out ( pResetWires[107] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[446] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7480 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[211] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7481 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[215] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p3206 ) ,
+ .prog_clk_2_W_in ( p490 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7482 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7483 ) ,
+ .prog_clk_3_W_in ( p2793 ) , .prog_clk_3_E_in ( p1356 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7484 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7485 ) ,
+ .clk_1_W_in ( clk_1_wires[211] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7486 ) ,
+ .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) ,
+ .clk_2_E_in ( p1499 ) , .clk_2_W_in ( p2736 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7487 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p2793 ) ,
+ .clk_3_E_in ( p3169 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7490 ) ) ;
+cbx_1__1_ cbx_12__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7491 } ) ,
+ .chanx_left_in ( sb_1__1__111_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__1_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__122_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__122_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p2088 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7492 ) ,
+ .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[122] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[122] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[122] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7493 ) ,
+ .pReset_W_in ( pResetWires[155] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7494 ) ,
+ .pReset_S_out ( pResetWires[157] ) , .pReset_E_out ( pResetWires[156] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[449] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7495 ) ,
+ .prog_clk_1_W_in ( p1855 ) , .prog_clk_1_E_in ( p1405 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7496 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7497 ) ,
+ .prog_clk_2_E_in ( p2682 ) , .prog_clk_2_W_in ( p1020 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7498 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7499 ) ,
+ .prog_clk_3_W_in ( p2449 ) , .prog_clk_3_E_in ( p2012 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7500 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_1_W_in ( p2146 ) ,
+ .clk_1_E_in ( p1303 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7502 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_2_E_in ( p2043 ) ,
+ .clk_2_W_in ( p2323 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p2449 ) ,
+ .clk_3_E_in ( p2513 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7507 ) ) ;
+cbx_1__1_ cbx_12__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7508 } ) ,
+ .chanx_left_in ( sb_1__1__112_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__2_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__123_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__123_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p2180 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7509 ) ,
+ .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[123] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[123] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[123] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7510 ) ,
+ .pReset_W_in ( pResetWires[204] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7511 ) ,
+ .pReset_S_out ( pResetWires[206] ) , .pReset_E_out ( pResetWires[205] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[452] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7512 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[218] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7513 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[222] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p2945 ) ,
+ .prog_clk_2_W_in ( p446 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7514 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7515 ) ,
+ .prog_clk_3_W_in ( p1470 ) , .prog_clk_3_E_in ( p1802 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7516 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7517 ) ,
+ .clk_1_W_in ( clk_1_wires[218] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7518 ) ,
+ .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) ,
+ .clk_2_E_in ( p1867 ) , .clk_2_W_in ( p1351 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7519 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p1470 ) ,
+ .clk_3_E_in ( p2919 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7522 ) ) ;
+cbx_1__1_ cbx_12__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7523 } ) ,
+ .chanx_left_in ( sb_1__1__113_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__3_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__124_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__124_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1573 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7524 ) ,
+ .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[124] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[124] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[124] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7525 ) ,
+ .pReset_W_in ( pResetWires[253] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7526 ) ,
+ .pReset_S_out ( pResetWires[255] ) , .pReset_E_out ( pResetWires[254] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[455] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7527 ) ,
+ .prog_clk_1_W_in ( p1494 ) , .prog_clk_1_E_in ( p1327 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7528 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7529 ) ,
+ .prog_clk_2_E_in ( p2946 ) , .prog_clk_2_W_in ( p1008 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7530 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7531 ) ,
+ .prog_clk_3_W_in ( p2796 ) , .prog_clk_3_E_in ( p2248 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7532 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_1_W_in ( p1382 ) ,
+ .clk_1_E_in ( p1550 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7534 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_2_E_in ( p2420 ) ,
+ .clk_2_W_in ( p2743 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2796 ) ,
+ .clk_3_E_in ( p2918 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7539 ) ) ;
+cbx_1__1_ cbx_12__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7540 } ) ,
+ .chanx_left_in ( sb_1__1__114_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__4_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__125_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__125_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p1779 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7541 ) ,
+ .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[125] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[125] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[125] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7542 ) ,
+ .pReset_W_in ( pResetWires[302] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7543 ) ,
+ .pReset_S_out ( pResetWires[304] ) , .pReset_E_out ( pResetWires[303] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[458] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7544 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[225] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7545 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[229] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p3113 ) ,
+ .prog_clk_2_W_in ( p591 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7546 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7547 ) ,
+ .prog_clk_3_W_in ( p2404 ) , .prog_clk_3_E_in ( p2028 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7548 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7549 ) ,
+ .clk_1_W_in ( clk_1_wires[225] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7550 ) ,
+ .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) ,
+ .clk_2_E_in ( p2243 ) , .clk_2_W_in ( p2316 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7551 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2404 ) ,
+ .clk_3_E_in ( p3049 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7554 ) ) ;
+cbx_1__1_ cbx_12__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7555 } ) ,
+ .chanx_left_in ( sb_1__1__115_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__5_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__126_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__126_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p1412 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7556 ) ,
+ .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[126] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[126] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[126] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7557 ) ,
+ .pReset_W_in ( pResetWires[351] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7558 ) ,
+ .pReset_S_out ( pResetWires[353] ) , .pReset_E_out ( pResetWires[352] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[461] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7559 ) ,
+ .prog_clk_1_W_in ( p1363 ) , .prog_clk_1_E_in ( p1435 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7560 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7561 ) ,
+ .prog_clk_2_E_in ( p2785 ) , .prog_clk_2_W_in ( p986 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7562 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7563 ) ,
+ .prog_clk_3_W_in ( p2632 ) , .prog_clk_3_E_in ( p1437 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7564 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_1_W_in ( p2635 ) ,
+ .clk_1_E_in ( p1297 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7566 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_2_E_in ( p1465 ) ,
+ .clk_2_W_in ( p2525 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p2632 ) ,
+ .clk_3_E_in ( p2716 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7571 ) ) ;
+cbx_1__1_ cbx_12__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7572 } ) ,
+ .chanx_left_in ( sb_1__1__116_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__6_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__127_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__127_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p1422 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7573 ) ,
+ .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[127] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[127] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[127] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7574 ) ,
+ .pReset_W_in ( pResetWires[400] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7575 ) ,
+ .pReset_S_out ( pResetWires[402] ) , .pReset_E_out ( pResetWires[401] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[464] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7576 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[232] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7577 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[236] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2679 ) ,
+ .prog_clk_2_W_in ( p1037 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7578 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7579 ) ,
+ .prog_clk_3_W_in ( p1827 ) , .prog_clk_3_E_in ( p1781 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7580 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7581 ) ,
+ .clk_1_W_in ( clk_1_wires[232] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7582 ) ,
+ .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) ,
+ .clk_2_E_in ( p1747 ) , .clk_2_W_in ( p1711 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7583 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p1827 ) ,
+ .clk_3_E_in ( p2504 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7586 ) ) ;
+cbx_1__1_ cbx_12__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7587 } ) ,
+ .chanx_left_in ( sb_1__1__117_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__7_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__128_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__128_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p1084 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7588 ) ,
+ .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[128] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[128] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[128] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7589 ) ,
+ .pReset_W_in ( pResetWires[449] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7590 ) ,
+ .pReset_S_out ( pResetWires[451] ) , .pReset_E_out ( pResetWires[450] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[467] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7591 ) ,
+ .prog_clk_1_W_in ( p1583 ) , .prog_clk_1_E_in ( p1077 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7592 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7593 ) ,
+ .prog_clk_2_E_in ( p2491 ) , .prog_clk_2_W_in ( p696 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7594 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7595 ) ,
+ .prog_clk_3_W_in ( p1805 ) , .prog_clk_3_E_in ( p2272 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7596 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_1_W_in ( p1805 ) ,
+ .clk_1_E_in ( p321 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7598 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_2_E_in ( p2448 ) ,
+ .clk_2_W_in ( p1693 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p1805 ) ,
+ .clk_3_E_in ( p2344 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7603 ) ) ;
+cbx_1__1_ cbx_12__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7604 } ) ,
+ .chanx_left_in ( sb_1__1__118_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__8_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__129_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__129_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p2142 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7605 ) ,
+ .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[129] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[129] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[129] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7606 ) ,
+ .pReset_W_in ( pResetWires[498] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7607 ) ,
+ .pReset_S_out ( pResetWires[500] ) , .pReset_E_out ( pResetWires[499] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[470] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7608 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[239] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7609 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[243] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p2944 ) ,
+ .prog_clk_2_W_in ( p676 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7610 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7611 ) ,
+ .prog_clk_3_W_in ( p2482 ) , .prog_clk_3_E_in ( p1984 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7612 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7613 ) ,
+ .clk_1_W_in ( clk_1_wires[239] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7614 ) ,
+ .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) ,
+ .clk_2_E_in ( p2076 ) , .clk_2_W_in ( p2338 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7615 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p2442 ) ,
+ .clk_3_E_in ( p2928 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7618 ) ) ;
+cbx_1__1_ cbx_12__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7619 } ) ,
+ .chanx_left_in ( sb_1__1__119_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__9_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__130_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__130_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p1411 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7620 ) ,
+ .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[130] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[130] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[130] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7621 ) ,
+ .pReset_W_in ( pResetWires[547] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7622 ) ,
+ .pReset_S_out ( pResetWires[549] ) , .pReset_E_out ( pResetWires[548] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[473] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7623 ) ,
+ .prog_clk_1_W_in ( p1870 ) , .prog_clk_1_E_in ( p1336 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7624 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7625 ) ,
+ .prog_clk_2_E_in ( p3211 ) , .prog_clk_2_W_in ( p556 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7626 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7627 ) ,
+ .prog_clk_3_W_in ( p2226 ) , .prog_clk_3_E_in ( p2595 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7628 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_1_W_in ( p1801 ) ,
+ .clk_1_E_in ( p1447 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7630 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_2_E_in ( p2634 ) ,
+ .clk_2_W_in ( p2034 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p2226 ) ,
+ .clk_3_E_in ( p3160 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7635 ) ) ;
+cbx_1__1_ cbx_12__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7636 } ) ,
+ .chanx_left_in ( sb_1__1__120_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__10_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__131_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__131_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p1463 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7637 ) ,
+ .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[131] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[131] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[131] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7638 ) ,
+ .pReset_W_in ( pResetWires[596] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7639 ) ,
+ .pReset_S_out ( pResetWires[598] ) , .pReset_E_out ( pResetWires[597] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[476] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7640 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[246] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7641 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[250] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p2461 ) ,
+ .prog_clk_2_W_in ( p1193 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7642 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7643 ) ,
+ .prog_clk_3_W_in ( p2390 ) , .prog_clk_3_E_in ( p2058 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7644 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7645 ) ,
+ .clk_1_W_in ( clk_1_wires[246] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7646 ) ,
+ .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) ,
+ .clk_2_E_in ( p2245 ) , .clk_2_W_in ( p2249 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7647 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p2390 ) ,
+ .clk_3_E_in ( p2281 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7650 ) ) ;
+cbx_1__2_ cbx_1__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7651 } ) ,
+ .chanx_left_in ( sb_0__12__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__0_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) ,
+ .SC_IN_BOT ( p1095 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7652 ) ,
+ .pReset_E_in ( pResetWires[601] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7653 ) ,
+ .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7654 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[59] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[62] ) ) ;
+cbx_1__2_ cbx_2__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7655 } ) ,
+ .chanx_left_in ( sb_1__12__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__1_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p2090 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7656 ) ,
+ .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) ,
+ .pReset_E_in ( pResetWires[605] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7657 ) ,
+ .pReset_W_out ( pResetWires[604] ) , .pReset_S_out ( pResetWires[606] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7658 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[99] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7659 ) ) ;
+cbx_1__2_ cbx_3__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7660 } ) ,
+ .chanx_left_in ( sb_1__12__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__2_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) ,
+ .SC_IN_BOT ( p1884 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7661 ) ,
+ .pReset_E_in ( pResetWires[608] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7662 ) ,
+ .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7663 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[137] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7664 ) ) ;
+cbx_1__2_ cbx_4__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7665 } ) ,
+ .chanx_left_in ( sb_1__12__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__3_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p878 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7666 ) ,
+ .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) ,
+ .pReset_E_in ( pResetWires[611] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7667 ) ,
+ .pReset_W_out ( pResetWires[610] ) , .pReset_S_out ( pResetWires[612] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7668 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[175] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7669 ) ) ;
+cbx_1__2_ cbx_5__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7670 } ) ,
+ .chanx_left_in ( sb_1__12__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__4_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) ,
+ .SC_IN_BOT ( p1183 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7671 ) ,
+ .pReset_E_in ( pResetWires[614] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7672 ) ,
+ .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7673 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[213] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7674 ) ) ;
+cbx_1__2_ cbx_6__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7675 } ) ,
+ .chanx_left_in ( sb_1__12__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__5_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1767 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7676 ) ,
+ .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) ,
+ .pReset_E_in ( pResetWires[617] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7677 ) ,
+ .pReset_W_out ( pResetWires[616] ) , .pReset_S_out ( pResetWires[618] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7678 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[251] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7679 ) ) ;
+cbx_1__2_ cbx_7__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7680 } ) ,
+ .chanx_left_in ( sb_1__12__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__6_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) ,
+ .SC_IN_BOT ( p1180 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7681 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7682 ) ,
+ .pReset_W_in ( pResetWires[619] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7683 ) ,
+ .pReset_S_out ( pResetWires[621] ) , .pReset_E_out ( pResetWires[620] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[289] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7684 ) ) ;
+cbx_1__2_ cbx_8__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7685 } ) ,
+ .chanx_left_in ( sb_1__12__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__7_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p2121 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7686 ) ,
+ .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7687 ) ,
+ .pReset_W_in ( pResetWires[622] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7688 ) ,
+ .pReset_S_out ( pResetWires[624] ) , .pReset_E_out ( pResetWires[623] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[327] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7689 ) ) ;
+cbx_1__2_ cbx_9__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7690 } ) ,
+ .chanx_left_in ( sb_1__12__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__8_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) ,
+ .SC_IN_BOT ( p823 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7691 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7692 ) ,
+ .pReset_W_in ( pResetWires[625] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7693 ) ,
+ .pReset_S_out ( pResetWires[627] ) , .pReset_E_out ( pResetWires[626] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[365] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7694 ) ) ;
+cbx_1__2_ cbx_10__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7695 } ) ,
+ .chanx_left_in ( sb_1__12__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__9_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1512 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7696 ) ,
+ .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7697 ) ,
+ .pReset_W_in ( pResetWires[628] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7698 ) ,
+ .pReset_S_out ( pResetWires[630] ) , .pReset_E_out ( pResetWires[629] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[403] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7699 ) ) ;
+cbx_1__2_ cbx_11__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7700 } ) ,
+ .chanx_left_in ( sb_1__12__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__10_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) ,
+ .SC_IN_BOT ( p1832 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7701 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7702 ) ,
+ .pReset_W_in ( pResetWires[631] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7703 ) ,
+ .pReset_S_out ( pResetWires[633] ) , .pReset_E_out ( pResetWires[632] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[441] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7704 ) ) ;
+cbx_1__2_ cbx_12__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7705 } ) ,
+ .chanx_left_in ( sb_1__12__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__12__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__12__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__11_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p2166 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7706 ) ,
+ .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7707 ) ,
+ .pReset_W_in ( pResetWires[634] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7708 ) ,
+ .pReset_S_out ( pResetWires[636] ) , .pReset_E_out ( pResetWires[635] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[479] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7709 ) ) ;
+cby_0__1_ cby_0__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7710 } ) ,
+ .chany_bottom_in ( sb_0__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__0_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__0_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__0_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[64] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[3] ) ) ;
+cby_0__1_ cby_0__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7711 } ) ,
+ .chany_bottom_in ( sb_0__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__1_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__1_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__1_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[113] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[9] ) ) ;
+cby_0__1_ cby_0__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7712 } ) ,
+ .chany_bottom_in ( sb_0__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__2_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__2_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__2_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[162] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[14] ) ) ;
+cby_0__1_ cby_0__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7713 } ) ,
+ .chany_bottom_in ( sb_0__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__3_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__3_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__3_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[211] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[19] ) ) ;
+cby_0__1_ cby_0__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7714 } ) ,
+ .chany_bottom_in ( sb_0__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__4_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__4_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__4_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[260] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[24] ) ) ;
+cby_0__1_ cby_0__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7715 } ) ,
+ .chany_bottom_in ( sb_0__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__5_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__5_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__5_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[309] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[29] ) ) ;
+cby_0__1_ cby_0__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7716 } ) ,
+ .chany_bottom_in ( sb_0__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__6_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__6_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__6_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[358] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[34] ) ) ;
+cby_0__1_ cby_0__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7717 } ) ,
+ .chany_bottom_in ( sb_0__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__7_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__7_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__7_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[407] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[39] ) ) ;
+cby_0__1_ cby_0__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7718 } ) ,
+ .chany_bottom_in ( sb_0__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__8_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__8_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__8_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[456] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[44] ) ) ;
+cby_0__1_ cby_0__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7719 } ) ,
+ .chany_bottom_in ( sb_0__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__9_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__9_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__9_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[505] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[49] ) ) ;
+cby_0__1_ cby_0__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7720 } ) ,
+ .chany_bottom_in ( sb_0__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__10_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__10_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__10_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[554] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[54] ) ) ;
+cby_0__1_ cby_0__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7721 } ) ,
+ .chany_bottom_in ( sb_0__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_0__12__0_chany_bottom_out ) ,
+ .ccff_head ( sb_0__12__0_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__11_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[603] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[61] ) ) ;
+cby_1__1_ cby_1__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7722 } ) ,
+ .chany_bottom_in ( sb_1__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_0_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__0_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__0_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7723 ) ,
+ .Test_en_E_in ( Test_enWires[26] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7724 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7725 ) ,
+ .Test_en_W_out ( Test_enWires[24] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7726 ) ,
+ .pReset_S_in ( pResetWires[27] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7727 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7728 ) ,
+ .Reset_E_in ( ResetWires[26] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7729 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7730 ) ,
+ .Reset_W_out ( ResetWires[24] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7731 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[1] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[2] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7732 ) ,
+ .prog_clk_2_N_in ( p1434 ) , .prog_clk_2_S_in ( p3230 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7733 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7734 ) ,
+ .prog_clk_3_S_in ( p3295 ) , .prog_clk_3_N_in ( p2298 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7735 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_2_N_in ( p2366 ) ,
+ .clk_2_S_in ( p2347 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p2466 ) ,
+ .clk_3_N_in ( p935 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7740 ) ) ;
+cby_1__1_ cby_1__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7741 } ) ,
+ .chany_bottom_in ( sb_1__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_1_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__1_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__1_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7742 ) ,
+ .Test_en_E_in ( Test_enWires[48] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7743 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7744 ) ,
+ .Test_en_W_out ( Test_enWires[46] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7745 ) ,
+ .pReset_S_in ( pResetWires[65] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7746 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7747 ) ,
+ .Reset_E_in ( ResetWires[48] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7748 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7749 ) ,
+ .Reset_W_out ( ResetWires[46] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7750 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[7] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[8] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7751 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[3] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7752 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[4] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7753 ) ,
+ .prog_clk_3_S_in ( p2459 ) , .prog_clk_3_N_in ( p401 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7754 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7755 ) ,
+ .clk_2_N_in ( clk_2_wires[3] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7756 ) ,
+ .clk_2_S_out ( clk_2_wires[4] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p2459 ) ,
+ .clk_3_N_in ( p687 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7759 ) ) ;
+cby_1__1_ cby_1__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7760 } ) ,
+ .chany_bottom_in ( sb_1__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_2_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__2_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__2_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7761 ) ,
+ .Test_en_E_in ( Test_enWires[70] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7762 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7763 ) ,
+ .Test_en_W_out ( Test_enWires[68] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7764 ) ,
+ .pReset_S_in ( pResetWires[114] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7765 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7766 ) ,
+ .Reset_E_in ( ResetWires[70] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7767 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7768 ) ,
+ .Reset_W_out ( ResetWires[68] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7769 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[12] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[13] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7770 ) ,
+ .prog_clk_2_N_in ( p2689 ) , .prog_clk_2_S_in ( p1752 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7771 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7772 ) ,
+ .prog_clk_3_S_in ( p1622 ) , .prog_clk_3_N_in ( p3059 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7773 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_2_N_in ( p3127 ) ,
+ .clk_2_S_in ( p3138 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p3212 ) ,
+ .clk_3_N_in ( p1158 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7778 ) ) ;
+cby_1__1_ cby_1__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7779 } ) ,
+ .chany_bottom_in ( sb_1__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_3_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__3_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__3_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7780 ) ,
+ .Test_en_E_in ( Test_enWires[92] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7781 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7782 ) ,
+ .Test_en_W_out ( Test_enWires[90] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7783 ) ,
+ .pReset_S_in ( pResetWires[163] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7784 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7785 ) ,
+ .Reset_E_in ( ResetWires[92] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7786 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7787 ) ,
+ .Reset_W_out ( ResetWires[90] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7788 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[17] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[18] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7789 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[10] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7790 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[11] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7791 ) ,
+ .prog_clk_3_S_in ( p1772 ) , .prog_clk_3_N_in ( p858 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7792 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7793 ) ,
+ .clk_2_N_in ( clk_2_wires[10] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7794 ) ,
+ .clk_2_S_out ( clk_2_wires[11] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p1772 ) ,
+ .clk_3_N_in ( p306 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7797 ) ) ;
+cby_1__1_ cby_1__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7798 } ) ,
+ .chany_bottom_in ( sb_1__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_4_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__4_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__4_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7799 ) ,
+ .Test_en_E_in ( Test_enWires[114] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7800 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7801 ) ,
+ .Test_en_W_out ( Test_enWires[112] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7802 ) ,
+ .pReset_S_in ( pResetWires[212] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7803 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7804 ) ,
+ .Reset_E_in ( ResetWires[114] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7805 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7806 ) ,
+ .Reset_W_out ( ResetWires[112] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7807 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[22] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[23] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7808 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7809 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[8] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7810 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p1869 ) ,
+ .prog_clk_3_N_in ( p327 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7811 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7812 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7813 ) ,
+ .clk_2_S_in ( clk_2_wires[8] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7814 ) ,
+ .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p1869 ) ,
+ .clk_3_N_in ( p478 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7816 ) ) ;
+cby_1__1_ cby_1__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7817 } ) ,
+ .chany_bottom_in ( sb_1__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_5_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__5_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__5_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7818 ) ,
+ .Test_en_E_in ( Test_enWires[136] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7819 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7820 ) ,
+ .Test_en_W_out ( Test_enWires[134] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7821 ) ,
+ .pReset_S_in ( pResetWires[261] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7822 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7823 ) ,
+ .Reset_E_in ( ResetWires[136] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7824 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7825 ) ,
+ .Reset_W_out ( ResetWires[134] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7826 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[27] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[28] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7827 ) ,
+ .prog_clk_2_N_in ( p2419 ) , .prog_clk_2_S_in ( p3137 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7828 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7829 ) ,
+ .prog_clk_3_S_in ( p3182 ) , .prog_clk_3_N_in ( p2555 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7830 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_2_N_in ( p2603 ) ,
+ .clk_2_S_in ( p2775 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p2859 ) ,
+ .clk_3_N_in ( p571 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7835 ) ) ;
+cby_1__1_ cby_1__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7836 } ) ,
+ .chany_bottom_in ( sb_1__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_6_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__6_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__6_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7837 ) ,
+ .Test_en_E_in ( Test_enWires[158] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7838 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7839 ) ,
+ .Test_en_W_out ( Test_enWires[156] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7840 ) ,
+ .pReset_S_in ( pResetWires[310] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7841 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7842 ) ,
+ .Reset_E_in ( ResetWires[158] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7843 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7844 ) ,
+ .Reset_W_out ( ResetWires[156] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7845 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[32] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[33] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7846 ) ,
+ .prog_clk_2_N_in ( p3338 ) , .prog_clk_2_S_in ( p2267 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7847 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7848 ) ,
+ .prog_clk_3_S_in ( p2473 ) , .prog_clk_3_N_in ( p3313 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7849 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_2_N_in ( p2829 ) ,
+ .clk_2_S_in ( p2559 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p2619 ) ,
+ .clk_3_N_in ( p624 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7854 ) ) ;
+cby_1__1_ cby_1__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7855 } ) ,
+ .chany_bottom_in ( sb_1__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_7_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__7_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__7_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7856 ) ,
+ .Test_en_E_in ( Test_enWires[180] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7857 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7858 ) ,
+ .Test_en_W_out ( Test_enWires[178] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7859 ) ,
+ .pReset_S_in ( pResetWires[359] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7860 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7861 ) ,
+ .Reset_E_in ( ResetWires[180] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7862 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7863 ) ,
+ .Reset_W_out ( ResetWires[178] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7864 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[37] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[38] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7865 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[17] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7866 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[18] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7867 ) ,
+ .prog_clk_3_S_in ( p2184 ) , .prog_clk_3_N_in ( p100 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7868 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7869 ) ,
+ .clk_2_N_in ( clk_2_wires[17] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7870 ) ,
+ .clk_2_S_out ( clk_2_wires[18] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p2184 ) ,
+ .clk_3_N_in ( p840 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7873 ) ) ;
+cby_1__1_ cby_1__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7874 } ) ,
+ .chany_bottom_in ( sb_1__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_8_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__8_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__8_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7875 ) ,
+ .Test_en_E_in ( Test_enWires[202] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7876 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7877 ) ,
+ .Test_en_W_out ( Test_enWires[200] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7878 ) ,
+ .pReset_S_in ( pResetWires[408] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7879 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7880 ) ,
+ .Reset_E_in ( ResetWires[202] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7881 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7882 ) ,
+ .Reset_W_out ( ResetWires[200] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7883 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[42] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[43] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7884 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7885 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[15] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7886 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1588 ) ,
+ .prog_clk_3_N_in ( p399 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7887 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7888 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7889 ) ,
+ .clk_2_S_in ( clk_2_wires[15] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7890 ) ,
+ .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1588 ) ,
+ .clk_3_N_in ( p844 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7892 ) ) ;
+cby_1__1_ cby_1__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7893 } ) ,
+ .chany_bottom_in ( sb_1__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_9_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__9_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__9_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7894 ) ,
+ .Test_en_E_in ( Test_enWires[224] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7895 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7896 ) ,
+ .Test_en_W_out ( Test_enWires[222] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7897 ) ,
+ .pReset_S_in ( pResetWires[457] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7898 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7899 ) ,
+ .Reset_E_in ( ResetWires[224] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7900 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7901 ) ,
+ .Reset_W_out ( ResetWires[222] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7902 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[47] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[48] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7903 ) ,
+ .prog_clk_2_N_in ( p2966 ) , .prog_clk_2_S_in ( p2324 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7904 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7905 ) ,
+ .prog_clk_3_S_in ( p2500 ) , .prog_clk_3_N_in ( p2891 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7906 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_2_N_in ( p2098 ) ,
+ .clk_2_S_in ( p1732 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p1880 ) ,
+ .clk_3_N_in ( p386 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7911 ) ) ;
+cby_1__1_ cby_1__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7912 } ) ,
+ .chany_bottom_in ( sb_1__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_10_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__10_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__10_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7913 ) ,
+ .Test_en_E_in ( Test_enWires[246] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7914 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7915 ) ,
+ .Test_en_W_out ( Test_enWires[244] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7916 ) ,
+ .pReset_S_in ( pResetWires[506] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7917 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7918 ) ,
+ .Reset_E_in ( ResetWires[246] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7919 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7920 ) ,
+ .Reset_W_out ( ResetWires[244] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7921 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[52] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[53] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7922 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7923 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[22] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7924 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1868 ) ,
+ .prog_clk_3_N_in ( p93 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7925 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7926 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7927 ) ,
+ .clk_2_S_in ( clk_2_wires[22] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7928 ) ,
+ .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1868 ) ,
+ .clk_3_N_in ( p921 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7930 ) ) ;
+cby_1__1_ cby_1__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7931 } ) ,
+ .chany_bottom_in ( sb_1__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_11_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__11_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__11_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7932 ) ,
+ .Test_en_E_in ( Test_enWires[268] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7933 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7934 ) ,
+ .Test_en_W_out ( Test_enWires[266] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7935 ) ,
+ .pReset_S_in ( pResetWires[555] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7936 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7937 ) ,
+ .Reset_E_in ( ResetWires[268] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7938 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7939 ) ,
+ .Reset_W_out ( ResetWires[266] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7940 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[57] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[58] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p1552 ) ,
+ .prog_clk_2_S_in ( p2327 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7941 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7942 ) ,
+ .prog_clk_3_S_in ( p2458 ) , .prog_clk_3_N_in ( p2744 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7943 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_2_N_in ( p2839 ) ,
+ .clk_2_S_in ( p2923 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p2973 ) ,
+ .clk_3_N_in ( p2008 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7948 ) ) ;
+cby_1__1_ cby_2__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7949 } ) ,
+ .chany_bottom_in ( sb_1__0__1_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__11_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_12_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__12_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__12_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__12_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7950 ) ,
+ .Test_en_E_in ( Test_enWires[28] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7951 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7952 ) ,
+ .Test_en_W_out ( Test_enWires[25] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7953 ) ,
+ .pReset_S_in ( pResetWires[30] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7954 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7955 ) ,
+ .Reset_E_in ( ResetWires[28] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7956 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7957 ) ,
+ .Reset_W_out ( ResetWires[25] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7958 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[64] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[65] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7959 ) ,
+ .prog_clk_2_N_in ( p1742 ) , .prog_clk_2_S_in ( p2260 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7960 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7961 ) ,
+ .prog_clk_3_S_in ( p2358 ) , .prog_clk_3_N_in ( p2337 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7962 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_2_N_in ( p2389 ) ,
+ .clk_2_S_in ( p3143 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p3181 ) ,
+ .clk_3_N_in ( p1280 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7967 ) ) ;
+cby_1__1_ cby_2__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7968 } ) ,
+ .chany_bottom_in ( sb_1__1__11_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__12_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_13_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__13_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__13_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__13_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7969 ) ,
+ .Test_en_E_in ( Test_enWires[50] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7970 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7971 ) ,
+ .Test_en_W_out ( Test_enWires[47] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7972 ) ,
+ .pReset_S_in ( pResetWires[69] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7973 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7974 ) ,
+ .Reset_E_in ( ResetWires[50] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7975 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7976 ) ,
+ .Reset_W_out ( ResetWires[47] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7977 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[67] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[68] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7978 ) ,
+ .prog_clk_2_N_in ( p3185 ) , .prog_clk_2_S_in ( p2931 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7979 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7980 ) ,
+ .prog_clk_3_S_in ( p2989 ) , .prog_clk_3_N_in ( p3327 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7981 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_2_N_in ( p3337 ) ,
+ .clk_2_S_in ( p2917 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p2947 ) ,
+ .clk_3_N_in ( p1 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7986 ) ) ;
+cby_1__1_ cby_2__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7987 } ) ,
+ .chany_bottom_in ( sb_1__1__12_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__13_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_14_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__14_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__14_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__14_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7988 ) ,
+ .Test_en_E_in ( Test_enWires[72] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7989 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7990 ) ,
+ .Test_en_W_out ( Test_enWires[69] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7991 ) ,
+ .pReset_S_in ( pResetWires[118] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7992 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7993 ) ,
+ .Reset_E_in ( ResetWires[72] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7994 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7995 ) ,
+ .Reset_W_out ( ResetWires[69] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7996 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[70] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[71] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7997 ) ,
+ .prog_clk_2_N_in ( p1377 ) , .prog_clk_2_S_in ( p444 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7998 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7999 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8000 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[68] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8001 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1377 ) ,
+ .clk_2_S_in ( p254 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8002 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8003 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8004 ) ,
+ .clk_3_N_in ( clk_3_wires[68] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8005 ) ,
+ .clk_3_S_out ( clk_3_wires[69] ) ) ;
+cby_1__1_ cby_2__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8006 } ) ,
+ .chany_bottom_in ( sb_1__1__13_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__14_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_15_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__15_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__15_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__15_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8007 ) ,
+ .Test_en_E_in ( Test_enWires[94] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8008 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8009 ) ,
+ .Test_en_W_out ( Test_enWires[91] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8010 ) ,
+ .pReset_S_in ( pResetWires[167] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8011 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8012 ) ,
+ .Reset_E_in ( ResetWires[94] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8013 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8014 ) ,
+ .Reset_W_out ( ResetWires[91] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8015 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[73] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[74] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8016 ) ,
+ .prog_clk_2_N_in ( p1060 ) , .prog_clk_2_S_in ( p1957 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8017 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8018 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8019 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[64] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8020 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1060 ) ,
+ .clk_2_S_in ( p2041 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8021 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8022 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8023 ) ,
+ .clk_3_N_in ( clk_3_wires[64] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8024 ) ,
+ .clk_3_S_out ( clk_3_wires[65] ) ) ;
+cby_1__1_ cby_2__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8025 } ) ,
+ .chany_bottom_in ( sb_1__1__14_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__15_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_16_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__16_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__16_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__16_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8026 ) ,
+ .Test_en_E_in ( Test_enWires[116] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8027 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8028 ) ,
+ .Test_en_W_out ( Test_enWires[113] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8029 ) ,
+ .pReset_S_in ( pResetWires[216] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8030 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8031 ) ,
+ .Reset_E_in ( ResetWires[116] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8032 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8033 ) ,
+ .Reset_W_out ( ResetWires[113] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8034 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[76] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[77] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8035 ) ,
+ .prog_clk_2_N_in ( p1873 ) , .prog_clk_2_S_in ( p72 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8036 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8037 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8038 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[58] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8039 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p1873 ) ,
+ .clk_2_S_in ( p583 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8040 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8041 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8042 ) ,
+ .clk_3_N_in ( clk_3_wires[58] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8043 ) ,
+ .clk_3_S_out ( clk_3_wires[59] ) ) ;
+cby_1__1_ cby_2__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8044 } ) ,
+ .chany_bottom_in ( sb_1__1__15_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__16_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_17_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__17_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__17_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__17_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8045 ) ,
+ .Test_en_E_in ( Test_enWires[138] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8046 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8047 ) ,
+ .Test_en_W_out ( Test_enWires[135] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8048 ) ,
+ .pReset_S_in ( pResetWires[265] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8049 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8050 ) ,
+ .Reset_E_in ( ResetWires[138] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8051 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8052 ) ,
+ .Reset_W_out ( ResetWires[135] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8053 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[79] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[80] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8054 ) ,
+ .prog_clk_2_N_in ( p2213 ) , .prog_clk_2_S_in ( p1350 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8055 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8056 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8057 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[54] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8058 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p2100 ) ,
+ .clk_2_S_in ( p1276 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8059 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8060 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8061 ) ,
+ .clk_3_N_in ( clk_3_wires[54] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8062 ) ,
+ .clk_3_S_out ( clk_3_wires[55] ) ) ;
+cby_1__1_ cby_2__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8063 } ) ,
+ .chany_bottom_in ( sb_1__1__16_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__17_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_18_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__18_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__18_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__18_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8064 ) ,
+ .Test_en_E_in ( Test_enWires[160] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8065 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8066 ) ,
+ .Test_en_W_out ( Test_enWires[157] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8067 ) ,
+ .pReset_S_in ( pResetWires[314] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8068 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8069 ) ,
+ .Reset_E_in ( ResetWires[160] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8070 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8071 ) ,
+ .Reset_W_out ( ResetWires[157] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8072 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[82] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[83] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8073 ) ,
+ .prog_clk_2_N_in ( p1857 ) , .prog_clk_2_S_in ( p1368 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8074 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8075 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[52] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8076 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[53] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8077 ) , .clk_2_N_in ( p1857 ) ,
+ .clk_2_S_in ( p2251 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8078 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8079 ) ,
+ .clk_3_S_in ( clk_3_wires[52] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8080 ) ,
+ .clk_3_N_out ( clk_3_wires[53] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8081 ) ) ;
+cby_1__1_ cby_2__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8082 } ) ,
+ .chany_bottom_in ( sb_1__1__17_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__18_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_19_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__19_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__19_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__19_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8083 ) ,
+ .Test_en_E_in ( Test_enWires[182] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8084 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8085 ) ,
+ .Test_en_W_out ( Test_enWires[179] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8086 ) ,
+ .pReset_S_in ( pResetWires[363] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8087 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8088 ) ,
+ .Reset_E_in ( ResetWires[182] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8089 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8090 ) ,
+ .Reset_W_out ( ResetWires[179] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8091 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[85] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[86] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8092 ) ,
+ .prog_clk_2_N_in ( p1225 ) , .prog_clk_2_S_in ( p2050 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8093 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8094 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[56] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8095 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[57] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , .clk_2_N_in ( p1225 ) ,
+ .clk_2_S_in ( p2745 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8097 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8098 ) ,
+ .clk_3_S_in ( clk_3_wires[56] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8099 ) ,
+ .clk_3_N_out ( clk_3_wires[57] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8100 ) ) ;
+cby_1__1_ cby_2__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8101 } ) ,
+ .chany_bottom_in ( sb_1__1__18_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__19_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_20_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__20_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__20_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__20_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8102 ) ,
+ .Test_en_E_in ( Test_enWires[204] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8103 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8104 ) ,
+ .Test_en_W_out ( Test_enWires[201] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8105 ) ,
+ .pReset_S_in ( pResetWires[412] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8106 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8107 ) ,
+ .Reset_E_in ( ResetWires[204] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8108 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8109 ) ,
+ .Reset_W_out ( ResetWires[201] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8110 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[88] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[89] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8111 ) ,
+ .prog_clk_2_N_in ( p1885 ) , .prog_clk_2_S_in ( p1263 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8112 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8113 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[62] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8114 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[63] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8115 ) , .clk_2_N_in ( p1885 ) ,
+ .clk_2_S_in ( p1150 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8116 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8117 ) ,
+ .clk_3_S_in ( clk_3_wires[62] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8118 ) ,
+ .clk_3_N_out ( clk_3_wires[63] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8119 ) ) ;
+cby_1__1_ cby_2__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8120 } ) ,
+ .chany_bottom_in ( sb_1__1__19_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__20_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_21_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__21_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__21_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__21_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8121 ) ,
+ .Test_en_E_in ( Test_enWires[226] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8122 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8123 ) ,
+ .Test_en_W_out ( Test_enWires[223] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8124 ) ,
+ .pReset_S_in ( pResetWires[461] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8125 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8126 ) ,
+ .Reset_E_in ( ResetWires[226] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8127 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8128 ) ,
+ .Reset_W_out ( ResetWires[223] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8129 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[91] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[92] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8130 ) ,
+ .prog_clk_2_N_in ( p1592 ) , .prog_clk_2_S_in ( p1360 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8131 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8132 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[66] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8133 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[67] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8134 ) , .clk_2_N_in ( p1592 ) ,
+ .clk_2_S_in ( p1980 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8135 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8136 ) ,
+ .clk_3_S_in ( clk_3_wires[66] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8137 ) ,
+ .clk_3_N_out ( clk_3_wires[67] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8138 ) ) ;
+cby_1__1_ cby_2__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8139 } ) ,
+ .chany_bottom_in ( sb_1__1__20_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__21_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_22_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__22_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__22_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__22_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8140 ) ,
+ .Test_en_E_in ( Test_enWires[248] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8141 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8142 ) ,
+ .Test_en_W_out ( Test_enWires[245] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8143 ) ,
+ .pReset_S_in ( pResetWires[510] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8144 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8145 ) ,
+ .Reset_E_in ( ResetWires[248] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8146 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8147 ) ,
+ .Reset_W_out ( ResetWires[245] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8148 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[94] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[95] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8149 ) ,
+ .prog_clk_2_N_in ( p2375 ) , .prog_clk_2_S_in ( p2753 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8150 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8151 ) ,
+ .prog_clk_3_S_in ( p2802 ) , .prog_clk_3_N_in ( p2332 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8152 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_2_N_in ( p1907 ) ,
+ .clk_2_S_in ( p3166 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p3210 ) ,
+ .clk_3_N_in ( p859 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8157 ) ) ;
+cby_1__1_ cby_2__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8158 } ) ,
+ .chany_bottom_in ( sb_1__1__21_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_23_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__23_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__23_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__23_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8159 ) ,
+ .Test_en_E_in ( Test_enWires[270] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8160 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8161 ) ,
+ .Test_en_W_out ( Test_enWires[267] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8162 ) ,
+ .pReset_S_in ( pResetWires[559] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8163 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8164 ) ,
+ .Reset_E_in ( ResetWires[270] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8165 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8166 ) ,
+ .Reset_W_out ( ResetWires[267] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8167 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[97] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[98] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p2980 ) ,
+ .prog_clk_2_S_in ( p2760 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8168 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8169 ) ,
+ .prog_clk_3_S_in ( p2831 ) , .prog_clk_3_N_in ( p3306 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8170 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_2_N_in ( p3366 ) ,
+ .clk_2_S_in ( p1971 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p2218 ) ,
+ .clk_3_N_in ( p1740 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8175 ) ) ;
+cby_1__1_ cby_3__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8176 } ) ,
+ .chany_bottom_in ( sb_1__0__2_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__22_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_24_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__24_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__24_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__24_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8177 ) ,
+ .Test_en_E_in ( Test_enWires[30] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8178 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8179 ) ,
+ .Test_en_W_out ( Test_enWires[27] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8180 ) ,
+ .pReset_S_in ( pResetWires[33] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8181 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8182 ) ,
+ .Reset_E_in ( ResetWires[30] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8183 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8184 ) ,
+ .Reset_W_out ( ResetWires[27] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8185 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[102] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[103] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8186 ) ,
+ .prog_clk_2_N_in ( p2968 ) , .prog_clk_2_S_in ( p2253 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8187 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8188 ) ,
+ .prog_clk_3_S_in ( p2443 ) , .prog_clk_3_N_in ( p2922 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8189 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_2_N_in ( p2402 ) ,
+ .clk_2_S_in ( p2514 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p2670 ) ,
+ .clk_3_N_in ( p36 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8194 ) ) ;
+cby_1__1_ cby_3__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8195 } ) ,
+ .chany_bottom_in ( sb_1__1__22_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__23_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_25_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__25_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__25_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__25_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8196 ) ,
+ .Test_en_E_in ( Test_enWires[52] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8197 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8198 ) ,
+ .Test_en_W_out ( Test_enWires[49] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8199 ) ,
+ .pReset_S_in ( pResetWires[73] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8200 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8201 ) ,
+ .Reset_E_in ( ResetWires[52] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8202 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8203 ) ,
+ .Reset_W_out ( ResetWires[49] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8204 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[105] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[106] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8205 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[29] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8206 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[30] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8207 ) ,
+ .prog_clk_3_S_in ( p1845 ) , .prog_clk_3_N_in ( p522 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8208 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8209 ) ,
+ .clk_2_N_in ( clk_2_wires[29] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8210 ) ,
+ .clk_2_S_out ( clk_2_wires[30] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p1762 ) ,
+ .clk_3_N_in ( p84 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8213 ) ) ;
+cby_1__1_ cby_3__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8214 } ) ,
+ .chany_bottom_in ( sb_1__1__23_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__24_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_26_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__26_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__26_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__26_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8215 ) ,
+ .Test_en_E_in ( Test_enWires[74] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8216 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8217 ) ,
+ .Test_en_W_out ( Test_enWires[71] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8218 ) ,
+ .pReset_S_in ( pResetWires[122] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8219 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8220 ) ,
+ .Reset_E_in ( ResetWires[74] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8221 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8222 ) ,
+ .Reset_W_out ( ResetWires[71] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8223 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[108] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[109] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8224 ) ,
+ .prog_clk_2_N_in ( p2652 ) , .prog_clk_2_S_in ( p2721 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8225 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8226 ) ,
+ .prog_clk_3_S_in ( p2846 ) , .prog_clk_3_N_in ( p2551 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8227 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_2_N_in ( p2189 ) ,
+ .clk_2_S_in ( p2042 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p2196 ) ,
+ .clk_3_N_in ( p436 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8232 ) ) ;
+cby_1__1_ cby_3__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8233 } ) ,
+ .chany_bottom_in ( sb_1__1__24_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__25_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_27_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__27_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__27_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__27_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8234 ) ,
+ .Test_en_E_in ( Test_enWires[96] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8235 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8236 ) ,
+ .Test_en_W_out ( Test_enWires[93] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8237 ) ,
+ .pReset_S_in ( pResetWires[171] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8238 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8239 ) ,
+ .Reset_E_in ( ResetWires[96] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8240 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8241 ) ,
+ .Reset_W_out ( ResetWires[93] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8242 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[111] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[112] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8243 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[40] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8244 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[41] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8245 ) ,
+ .prog_clk_3_S_in ( p1860 ) , .prog_clk_3_N_in ( p68 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8246 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8247 ) ,
+ .clk_2_N_in ( clk_2_wires[40] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8248 ) ,
+ .clk_2_S_out ( clk_2_wires[41] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p1860 ) ,
+ .clk_3_N_in ( p484 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8251 ) ) ;
+cby_1__1_ cby_3__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8252 } ) ,
+ .chany_bottom_in ( sb_1__1__25_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__26_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_28_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__28_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__28_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__28_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8253 ) ,
+ .Test_en_E_in ( Test_enWires[118] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8254 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8255 ) ,
+ .Test_en_W_out ( Test_enWires[115] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8256 ) ,
+ .pReset_S_in ( pResetWires[220] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8257 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8258 ) ,
+ .Reset_E_in ( ResetWires[118] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8259 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8260 ) ,
+ .Reset_W_out ( ResetWires[115] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8261 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[114] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[115] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8262 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8263 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[38] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8264 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p1839 ) ,
+ .prog_clk_3_N_in ( p293 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8265 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8266 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8267 ) ,
+ .clk_2_S_in ( clk_2_wires[38] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8268 ) ,
+ .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p1839 ) ,
+ .clk_3_N_in ( p988 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8270 ) ) ;
+cby_1__1_ cby_3__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8271 } ) ,
+ .chany_bottom_in ( sb_1__1__26_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__27_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_29_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__29_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__29_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__29_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8272 ) ,
+ .Test_en_E_in ( Test_enWires[140] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8273 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8274 ) ,
+ .Test_en_W_out ( Test_enWires[137] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8275 ) ,
+ .pReset_S_in ( pResetWires[269] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8276 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8277 ) ,
+ .Reset_E_in ( ResetWires[140] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8278 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8279 ) ,
+ .Reset_W_out ( ResetWires[137] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8280 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[117] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[118] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8281 ) ,
+ .prog_clk_2_N_in ( p3180 ) , .prog_clk_2_S_in ( p2568 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8282 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8283 ) ,
+ .prog_clk_3_S_in ( p2690 ) , .prog_clk_3_N_in ( p3152 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8284 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_2_N_in ( p2438 ) ,
+ .clk_2_S_in ( p2722 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p2833 ) ,
+ .clk_3_N_in ( p439 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8289 ) ) ;
+cby_1__1_ cby_3__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8290 } ) ,
+ .chany_bottom_in ( sb_1__1__27_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__28_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_30_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__30_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__30_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__30_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8291 ) ,
+ .Test_en_E_in ( Test_enWires[162] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8292 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8293 ) ,
+ .Test_en_W_out ( Test_enWires[159] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8294 ) ,
+ .pReset_S_in ( pResetWires[318] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8295 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8296 ) ,
+ .Reset_E_in ( ResetWires[162] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8297 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8298 ) ,
+ .Reset_W_out ( ResetWires[159] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8299 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[120] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[121] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8300 ) ,
+ .prog_clk_2_N_in ( p3222 ) , .prog_clk_2_S_in ( p2577 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8301 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8302 ) ,
+ .prog_clk_3_S_in ( p2655 ) , .prog_clk_3_N_in ( p3233 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8303 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_2_N_in ( p3276 ) ,
+ .clk_2_S_in ( p2519 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p2499 ) ,
+ .clk_3_N_in ( p612 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8308 ) ) ;
+cby_1__1_ cby_3__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8309 } ) ,
+ .chany_bottom_in ( sb_1__1__28_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__29_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_31_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__31_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__31_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__31_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8310 ) ,
+ .Test_en_E_in ( Test_enWires[184] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8311 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8312 ) ,
+ .Test_en_W_out ( Test_enWires[181] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8313 ) ,
+ .pReset_S_in ( pResetWires[367] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8314 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8315 ) ,
+ .Reset_E_in ( ResetWires[184] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8316 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8317 ) ,
+ .Reset_W_out ( ResetWires[181] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8318 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[123] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[124] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8319 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[53] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8320 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[54] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8321 ) ,
+ .prog_clk_3_S_in ( p2133 ) , .prog_clk_3_N_in ( p647 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8322 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8323 ) ,
+ .clk_2_N_in ( clk_2_wires[53] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8324 ) ,
+ .clk_2_S_out ( clk_2_wires[54] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p2133 ) ,
+ .clk_3_N_in ( p342 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8327 ) ) ;
+cby_1__1_ cby_3__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8328 } ) ,
+ .chany_bottom_in ( sb_1__1__29_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__30_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_32_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__32_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__32_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__32_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8329 ) ,
+ .Test_en_E_in ( Test_enWires[206] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8330 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8331 ) ,
+ .Test_en_W_out ( Test_enWires[203] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8332 ) ,
+ .pReset_S_in ( pResetWires[416] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8333 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8334 ) ,
+ .Reset_E_in ( ResetWires[206] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8335 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8336 ) ,
+ .Reset_W_out ( ResetWires[203] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8337 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[126] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[127] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8338 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8339 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[51] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8340 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p1909 ) ,
+ .prog_clk_3_N_in ( p802 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8341 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8342 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8343 ) ,
+ .clk_2_S_in ( clk_2_wires[51] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8344 ) ,
+ .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p1909 ) ,
+ .clk_3_N_in ( p510 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8346 ) ) ;
+cby_1__1_ cby_3__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8347 } ) ,
+ .chany_bottom_in ( sb_1__1__30_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__31_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_33_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__33_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__33_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__33_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8348 ) ,
+ .Test_en_E_in ( Test_enWires[228] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8349 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8350 ) ,
+ .Test_en_W_out ( Test_enWires[225] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8351 ) ,
+ .pReset_S_in ( pResetWires[465] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8352 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8353 ) ,
+ .Reset_E_in ( ResetWires[228] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8354 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8355 ) ,
+ .Reset_W_out ( ResetWires[225] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8356 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[129] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[130] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8357 ) ,
+ .prog_clk_2_N_in ( p3086 ) , .prog_clk_2_S_in ( p2727 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8358 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8359 ) ,
+ .prog_clk_3_S_in ( p2804 ) , .prog_clk_3_N_in ( p3018 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8360 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_2_N_in ( p2224 ) ,
+ .clk_2_S_in ( p2503 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p2609 ) ,
+ .clk_3_N_in ( p336 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8365 ) ) ;
+cby_1__1_ cby_3__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8366 } ) ,
+ .chany_bottom_in ( sb_1__1__31_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__32_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_34_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__34_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__34_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__34_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8367 ) ,
+ .Test_en_E_in ( Test_enWires[250] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8368 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8369 ) ,
+ .Test_en_W_out ( Test_enWires[247] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8370 ) ,
+ .pReset_S_in ( pResetWires[514] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8371 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8372 ) ,
+ .Reset_E_in ( ResetWires[250] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8373 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8374 ) ,
+ .Reset_W_out ( ResetWires[247] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8375 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[132] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[133] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8376 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8377 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[64] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8378 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p1433 ) ,
+ .prog_clk_3_N_in ( p438 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8379 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8380 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8381 ) ,
+ .clk_2_S_in ( clk_2_wires[64] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8382 ) ,
+ .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p1433 ) ,
+ .clk_3_N_in ( p356 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8384 ) ) ;
+cby_1__1_ cby_3__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8385 } ) ,
+ .chany_bottom_in ( sb_1__1__32_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_35_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__35_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__35_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__35_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8386 ) ,
+ .Test_en_E_in ( Test_enWires[272] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8387 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8388 ) ,
+ .Test_en_W_out ( Test_enWires[269] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8389 ) ,
+ .pReset_S_in ( pResetWires[563] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8390 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8391 ) ,
+ .Reset_E_in ( ResetWires[272] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8392 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8393 ) ,
+ .Reset_W_out ( ResetWires[269] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8394 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[135] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[136] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p2850 ) ,
+ .prog_clk_2_S_in ( p2887 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8395 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8396 ) ,
+ .prog_clk_3_S_in ( p2964 ) , .prog_clk_3_N_in ( p2730 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8397 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_2_N_in ( p2179 ) ,
+ .clk_2_S_in ( p2330 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p2426 ) ,
+ .clk_3_N_in ( p341 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8402 ) ) ;
+cby_1__1_ cby_4__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8403 } ) ,
+ .chany_bottom_in ( sb_1__0__3_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__33_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_36_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__36_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__36_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__36_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8404 ) ,
+ .Test_en_E_in ( Test_enWires[32] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8405 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8406 ) ,
+ .Test_en_W_out ( Test_enWires[29] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8407 ) ,
+ .pReset_S_in ( pResetWires[36] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8408 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8409 ) ,
+ .Reset_E_in ( ResetWires[32] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8410 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8411 ) ,
+ .Reset_W_out ( ResetWires[29] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8412 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[140] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[141] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8413 ) ,
+ .prog_clk_2_N_in ( p2688 ) , .prog_clk_2_S_in ( p2518 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8414 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8415 ) ,
+ .prog_clk_3_S_in ( p2677 ) , .prog_clk_3_N_in ( p2749 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8416 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_2_N_in ( p2780 ) ,
+ .clk_2_S_in ( p2735 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p2792 ) ,
+ .clk_3_N_in ( p357 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8421 ) ) ;
+cby_1__1_ cby_4__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8422 } ) ,
+ .chany_bottom_in ( sb_1__1__33_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__34_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_37_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__37_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__37_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__37_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8423 ) ,
+ .Test_en_E_in ( Test_enWires[54] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8424 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8425 ) ,
+ .Test_en_W_out ( Test_enWires[51] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8426 ) ,
+ .pReset_S_in ( pResetWires[77] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8427 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8428 ) ,
+ .Reset_E_in ( ResetWires[54] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8429 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8430 ) ,
+ .Reset_W_out ( ResetWires[51] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8431 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[143] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[144] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8432 ) ,
+ .prog_clk_2_N_in ( p2699 ) , .prog_clk_2_S_in ( p2764 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8433 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8434 ) ,
+ .prog_clk_3_S_in ( p2778 ) , .prog_clk_3_N_in ( p2521 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8435 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_2_N_in ( p2684 ) ,
+ .clk_2_S_in ( p2586 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p2620 ) ,
+ .clk_3_N_in ( p101 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8440 ) ) ;
+cby_1__1_ cby_4__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8441 } ) ,
+ .chany_bottom_in ( sb_1__1__34_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__35_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_38_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__38_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__38_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__38_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8442 ) ,
+ .Test_en_E_in ( Test_enWires[76] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8443 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8444 ) ,
+ .Test_en_W_out ( Test_enWires[73] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8445 ) ,
+ .pReset_S_in ( pResetWires[126] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8446 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8447 ) ,
+ .Reset_E_in ( ResetWires[76] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8448 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8449 ) ,
+ .Reset_W_out ( ResetWires[73] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8450 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[146] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[147] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8451 ) ,
+ .prog_clk_2_N_in ( p2159 ) , .prog_clk_2_S_in ( p434 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8452 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8453 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8454 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[24] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8455 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p2159 ) ,
+ .clk_2_S_in ( p914 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8456 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8457 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8458 ) ,
+ .clk_3_N_in ( clk_3_wires[24] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8459 ) ,
+ .clk_3_S_out ( clk_3_wires[25] ) ) ;
+cby_1__1_ cby_4__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8460 } ) ,
+ .chany_bottom_in ( sb_1__1__35_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__36_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_39_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__39_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__39_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__39_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8461 ) ,
+ .Test_en_E_in ( Test_enWires[98] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8462 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8463 ) ,
+ .Test_en_W_out ( Test_enWires[95] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8464 ) ,
+ .pReset_S_in ( pResetWires[175] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8465 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8466 ) ,
+ .Reset_E_in ( ResetWires[98] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8467 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8468 ) ,
+ .Reset_W_out ( ResetWires[95] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8469 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[149] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[150] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8470 ) ,
+ .prog_clk_2_N_in ( p1373 ) , .prog_clk_2_S_in ( p2262 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8471 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8472 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8473 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[20] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8474 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1373 ) ,
+ .clk_2_S_in ( p2328 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8475 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8476 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8477 ) ,
+ .clk_3_N_in ( clk_3_wires[20] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8478 ) ,
+ .clk_3_S_out ( clk_3_wires[21] ) ) ;
+cby_1__1_ cby_4__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8479 } ) ,
+ .chany_bottom_in ( sb_1__1__36_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__37_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_40_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__40_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__40_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__40_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8480 ) ,
+ .Test_en_E_in ( Test_enWires[120] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8481 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8482 ) ,
+ .Test_en_W_out ( Test_enWires[117] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8483 ) ,
+ .pReset_S_in ( pResetWires[224] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8484 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8485 ) ,
+ .Reset_E_in ( ResetWires[120] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8486 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8487 ) ,
+ .Reset_W_out ( ResetWires[117] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8488 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[152] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[153] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8489 ) ,
+ .prog_clk_2_N_in ( p1481 ) , .prog_clk_2_S_in ( p1270 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8490 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8491 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8492 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[14] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8493 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1481 ) ,
+ .clk_2_S_in ( p997 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8494 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8495 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8496 ) ,
+ .clk_3_N_in ( clk_3_wires[14] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8497 ) ,
+ .clk_3_S_out ( clk_3_wires[15] ) ) ;
+cby_1__1_ cby_4__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8498 } ) ,
+ .chany_bottom_in ( sb_1__1__37_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__38_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_41_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__41_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__41_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__41_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8499 ) ,
+ .Test_en_E_in ( Test_enWires[142] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8500 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8501 ) ,
+ .Test_en_W_out ( Test_enWires[139] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8502 ) ,
+ .pReset_S_in ( pResetWires[273] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8503 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8504 ) ,
+ .Reset_E_in ( ResetWires[142] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8505 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8506 ) ,
+ .Reset_W_out ( ResetWires[139] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8507 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[155] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[156] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8508 ) ,
+ .prog_clk_2_N_in ( p1492 ) , .prog_clk_2_S_in ( p1302 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8509 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8510 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8511 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[10] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8512 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p1492 ) ,
+ .clk_2_S_in ( p1392 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8513 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8514 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8515 ) ,
+ .clk_3_N_in ( clk_3_wires[10] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8516 ) ,
+ .clk_3_S_out ( clk_3_wires[11] ) ) ;
+cby_1__1_ cby_4__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8517 } ) ,
+ .chany_bottom_in ( sb_1__1__38_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__39_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_42_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__42_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__42_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__42_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8518 ) ,
+ .Test_en_E_in ( Test_enWires[164] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8519 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8520 ) ,
+ .Test_en_W_out ( Test_enWires[161] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8521 ) ,
+ .pReset_S_in ( pResetWires[322] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8522 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8523 ) ,
+ .Reset_E_in ( ResetWires[164] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8524 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8525 ) ,
+ .Reset_W_out ( ResetWires[161] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8526 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[158] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[159] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8527 ) ,
+ .prog_clk_2_N_in ( p1560 ) , .prog_clk_2_S_in ( p1734 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8528 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8529 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[8] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8530 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[9] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8531 ) , .clk_2_N_in ( p1560 ) ,
+ .clk_2_S_in ( p2509 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8532 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8533 ) ,
+ .clk_3_S_in ( clk_3_wires[8] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8534 ) ,
+ .clk_3_N_out ( clk_3_wires[9] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8535 ) ) ;
+cby_1__1_ cby_4__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8536 } ) ,
+ .chany_bottom_in ( sb_1__1__39_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__40_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_43_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__43_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__43_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__43_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8537 ) ,
+ .Test_en_E_in ( Test_enWires[186] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8538 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8539 ) ,
+ .Test_en_W_out ( Test_enWires[183] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8540 ) ,
+ .pReset_S_in ( pResetWires[371] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8541 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8542 ) ,
+ .Reset_E_in ( ResetWires[186] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8543 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8544 ) ,
+ .Reset_W_out ( ResetWires[183] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8545 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[161] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[162] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8546 ) ,
+ .prog_clk_2_N_in ( p1140 ) , .prog_clk_2_S_in ( p2340 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8547 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8548 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[12] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8549 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[13] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , .clk_2_N_in ( p1140 ) ,
+ .clk_2_S_in ( p2276 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8551 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8552 ) ,
+ .clk_3_S_in ( clk_3_wires[12] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8553 ) ,
+ .clk_3_N_out ( clk_3_wires[13] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8554 ) ) ;
+cby_1__1_ cby_4__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8555 } ) ,
+ .chany_bottom_in ( sb_1__1__40_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__41_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_44_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__44_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__44_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__44_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8556 ) ,
+ .Test_en_E_in ( Test_enWires[208] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8557 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8558 ) ,
+ .Test_en_W_out ( Test_enWires[205] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8559 ) ,
+ .pReset_S_in ( pResetWires[420] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8560 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8561 ) ,
+ .Reset_E_in ( ResetWires[208] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8562 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8563 ) ,
+ .Reset_W_out ( ResetWires[205] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8564 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[164] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[165] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8565 ) ,
+ .prog_clk_2_N_in ( p1864 ) , .prog_clk_2_S_in ( p873 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8566 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8567 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[18] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8568 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[19] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8569 ) , .clk_2_N_in ( p1864 ) ,
+ .clk_2_S_in ( p114 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8570 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8571 ) ,
+ .clk_3_S_in ( clk_3_wires[18] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8572 ) ,
+ .clk_3_N_out ( clk_3_wires[19] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8573 ) ) ;
+cby_1__1_ cby_4__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8574 } ) ,
+ .chany_bottom_in ( sb_1__1__41_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__42_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_45_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__45_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__45_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__45_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8575 ) ,
+ .Test_en_E_in ( Test_enWires[230] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8576 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8577 ) ,
+ .Test_en_W_out ( Test_enWires[227] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8578 ) ,
+ .pReset_S_in ( pResetWires[469] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8579 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8580 ) ,
+ .Reset_E_in ( ResetWires[230] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8581 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8582 ) ,
+ .Reset_W_out ( ResetWires[227] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8583 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[167] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[168] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8584 ) ,
+ .prog_clk_2_N_in ( p1878 ) , .prog_clk_2_S_in ( p2014 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8585 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8586 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[22] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8587 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[23] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8588 ) , .clk_2_N_in ( p1878 ) ,
+ .clk_2_S_in ( p2299 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8589 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8590 ) ,
+ .clk_3_S_in ( clk_3_wires[22] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8591 ) ,
+ .clk_3_N_out ( clk_3_wires[23] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8592 ) ) ;
+cby_1__1_ cby_4__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8593 } ) ,
+ .chany_bottom_in ( sb_1__1__42_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__43_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_46_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__46_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__46_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__46_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8594 ) ,
+ .Test_en_E_in ( Test_enWires[252] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8595 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8596 ) ,
+ .Test_en_W_out ( Test_enWires[249] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8597 ) ,
+ .pReset_S_in ( pResetWires[518] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8598 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8599 ) ,
+ .Reset_E_in ( ResetWires[252] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8600 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8601 ) ,
+ .Reset_W_out ( ResetWires[249] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8602 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[170] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[171] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8603 ) ,
+ .prog_clk_2_N_in ( p2675 ) , .prog_clk_2_S_in ( p3240 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8604 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8605 ) ,
+ .prog_clk_3_S_in ( p3292 ) , .prog_clk_3_N_in ( p2726 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8606 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_2_N_in ( p2787 ) ,
+ .clk_2_S_in ( p2269 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p2496 ) ,
+ .clk_3_N_in ( p1652 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8611 ) ) ;
+cby_1__1_ cby_4__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8612 } ) ,
+ .chany_bottom_in ( sb_1__1__43_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_47_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__47_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__47_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__47_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8613 ) ,
+ .Test_en_E_in ( Test_enWires[274] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8614 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8615 ) ,
+ .Test_en_W_out ( Test_enWires[271] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8616 ) ,
+ .pReset_S_in ( pResetWires[567] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8617 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8618 ) ,
+ .Reset_E_in ( ResetWires[274] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8619 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8620 ) ,
+ .Reset_W_out ( ResetWires[271] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8621 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[173] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[174] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p2938 ) ,
+ .prog_clk_2_S_in ( p2501 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8622 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8623 ) ,
+ .prog_clk_3_S_in ( p2696 ) , .prog_clk_3_N_in ( p2896 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8624 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_2_N_in ( p2986 ) ,
+ .clk_2_S_in ( p2719 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p2800 ) ,
+ .clk_3_N_in ( p412 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8629 ) ) ;
+cby_1__1_ cby_5__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8630 } ) ,
+ .chany_bottom_in ( sb_1__0__4_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__44_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_48_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__48_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__48_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__48_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8631 ) ,
+ .Test_en_E_in ( Test_enWires[34] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8632 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8633 ) ,
+ .Test_en_W_out ( Test_enWires[31] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8634 ) ,
+ .pReset_S_in ( pResetWires[39] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8635 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8636 ) ,
+ .Reset_E_in ( ResetWires[34] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8637 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8638 ) ,
+ .Reset_W_out ( ResetWires[31] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8639 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[178] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[179] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8640 ) ,
+ .prog_clk_2_N_in ( p3262 ) , .prog_clk_2_S_in ( p2507 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8641 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8642 ) ,
+ .prog_clk_3_S_in ( p2618 ) , .prog_clk_3_N_in ( p3236 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8643 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_2_N_in ( p3225 ) ,
+ .clk_2_S_in ( p1999 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2217 ) ,
+ .clk_3_N_in ( p902 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8648 ) ) ;
+cby_1__1_ cby_5__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8649 } ) ,
+ .chany_bottom_in ( sb_1__1__44_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__45_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_49_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__49_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__49_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__49_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8650 ) ,
+ .Test_en_E_in ( Test_enWires[56] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8651 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8652 ) ,
+ .Test_en_W_out ( Test_enWires[53] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8653 ) ,
+ .pReset_S_in ( pResetWires[81] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8654 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8655 ) ,
+ .Reset_E_in ( ResetWires[56] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8656 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8657 ) ,
+ .Reset_W_out ( ResetWires[53] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8658 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[181] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[182] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8659 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[31] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8660 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[32] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8661 ) ,
+ .prog_clk_3_S_in ( p1792 ) , .prog_clk_3_N_in ( p698 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8662 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8663 ) ,
+ .clk_2_N_in ( clk_2_wires[31] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8664 ) ,
+ .clk_2_S_out ( clk_2_wires[32] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p1792 ) ,
+ .clk_3_N_in ( p418 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8667 ) ) ;
+cby_1__1_ cby_5__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8668 } ) ,
+ .chany_bottom_in ( sb_1__1__45_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__46_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_50_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__50_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__50_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__50_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8669 ) ,
+ .Test_en_E_in ( Test_enWires[78] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8670 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8671 ) ,
+ .Test_en_W_out ( Test_enWires[75] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8672 ) ,
+ .pReset_S_in ( pResetWires[130] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8673 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8674 ) ,
+ .Reset_E_in ( ResetWires[78] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8675 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8676 ) ,
+ .Reset_W_out ( ResetWires[75] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8677 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[184] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[185] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8678 ) ,
+ .prog_clk_2_N_in ( p3264 ) , .prog_clk_2_S_in ( p3022 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8679 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8680 ) ,
+ .prog_clk_3_S_in ( p3082 ) , .prog_clk_3_N_in ( p3234 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8681 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_2_N_in ( p3089 ) ,
+ .clk_2_S_in ( p2933 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p2948 ) ,
+ .clk_3_N_in ( p1019 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8686 ) ) ;
+cby_1__1_ cby_5__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8687 } ) ,
+ .chany_bottom_in ( sb_1__1__46_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__47_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_51_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__51_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__51_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__51_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8688 ) ,
+ .Test_en_E_in ( Test_enWires[100] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8689 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8690 ) ,
+ .Test_en_W_out ( Test_enWires[97] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8691 ) ,
+ .pReset_S_in ( pResetWires[179] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8692 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8693 ) ,
+ .Reset_E_in ( ResetWires[100] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8694 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8695 ) ,
+ .Reset_W_out ( ResetWires[97] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8696 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[187] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[188] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8697 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[44] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8698 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[45] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8699 ) ,
+ .prog_clk_3_S_in ( p1504 ) , .prog_clk_3_N_in ( p983 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8700 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8701 ) ,
+ .clk_2_N_in ( clk_2_wires[44] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8702 ) ,
+ .clk_2_S_out ( clk_2_wires[45] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1504 ) ,
+ .clk_3_N_in ( p310 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8705 ) ) ;
+cby_1__1_ cby_5__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8706 } ) ,
+ .chany_bottom_in ( sb_1__1__47_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__48_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_52_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__52_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__52_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__52_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8707 ) ,
+ .Test_en_E_in ( Test_enWires[122] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8708 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8709 ) ,
+ .Test_en_W_out ( Test_enWires[119] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8710 ) ,
+ .pReset_S_in ( pResetWires[228] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8711 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8712 ) ,
+ .Reset_E_in ( ResetWires[122] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8713 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8714 ) ,
+ .Reset_W_out ( ResetWires[119] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8715 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[190] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[191] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8716 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8717 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[42] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8718 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p2396 ) ,
+ .prog_clk_3_N_in ( p351 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8719 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8720 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8721 ) ,
+ .clk_2_S_in ( clk_2_wires[42] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8722 ) ,
+ .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p2396 ) ,
+ .clk_3_N_in ( p683 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8724 ) ) ;
+cby_1__1_ cby_5__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8725 } ) ,
+ .chany_bottom_in ( sb_1__1__48_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__49_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_53_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__53_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__53_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__53_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8726 ) ,
+ .Test_en_E_in ( Test_enWires[144] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8727 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8728 ) ,
+ .Test_en_W_out ( Test_enWires[141] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8729 ) ,
+ .pReset_S_in ( pResetWires[277] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8730 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8731 ) ,
+ .Reset_E_in ( ResetWires[144] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8732 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8733 ) ,
+ .Reset_W_out ( ResetWires[141] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8734 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[193] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[194] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8735 ) ,
+ .prog_clk_2_N_in ( p2112 ) , .prog_clk_2_S_in ( p2565 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8736 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8737 ) ,
+ .prog_clk_3_S_in ( p2709 ) , .prog_clk_3_N_in ( p3372 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8738 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_2_N_in ( p3416 ) ,
+ .clk_2_S_in ( p2579 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p2625 ) ,
+ .clk_3_N_in ( p534 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8743 ) ) ;
+cby_1__1_ cby_5__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8744 } ) ,
+ .chany_bottom_in ( sb_1__1__49_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__50_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_54_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__54_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__54_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__54_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8745 ) ,
+ .Test_en_E_in ( Test_enWires[166] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8746 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8747 ) ,
+ .Test_en_W_out ( Test_enWires[163] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8748 ) ,
+ .pReset_S_in ( pResetWires[326] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8749 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8750 ) ,
+ .Reset_E_in ( ResetWires[166] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8751 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8752 ) ,
+ .Reset_W_out ( ResetWires[163] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8753 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[196] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[197] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8754 ) ,
+ .prog_clk_2_N_in ( p3342 ) , .prog_clk_2_S_in ( p3310 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8755 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8756 ) ,
+ .prog_clk_3_S_in ( p3351 ) , .prog_clk_3_N_in ( p3312 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8757 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_2_N_in ( p2235 ) ,
+ .clk_2_S_in ( p2587 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2593 ) ,
+ .clk_3_N_in ( p96 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8762 ) ) ;
+cby_1__1_ cby_5__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8763 } ) ,
+ .chany_bottom_in ( sb_1__1__50_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__51_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_55_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__55_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__55_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__55_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8764 ) ,
+ .Test_en_E_in ( Test_enWires[188] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8765 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8766 ) ,
+ .Test_en_W_out ( Test_enWires[185] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8767 ) ,
+ .pReset_S_in ( pResetWires[375] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8768 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8769 ) ,
+ .Reset_E_in ( ResetWires[188] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8770 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8771 ) ,
+ .Reset_W_out ( ResetWires[185] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8772 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[199] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[200] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8773 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[57] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8774 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[58] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8775 ) ,
+ .prog_clk_3_S_in ( p1054 ) , .prog_clk_3_N_in ( p15 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8776 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8777 ) ,
+ .clk_2_N_in ( clk_2_wires[57] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8778 ) ,
+ .clk_2_S_out ( clk_2_wires[58] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1054 ) ,
+ .clk_3_N_in ( p154 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8781 ) ) ;
+cby_1__1_ cby_5__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8782 } ) ,
+ .chany_bottom_in ( sb_1__1__51_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__52_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_56_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__56_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__56_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__56_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8783 ) ,
+ .Test_en_E_in ( Test_enWires[210] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8784 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8785 ) ,
+ .Test_en_W_out ( Test_enWires[207] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8786 ) ,
+ .pReset_S_in ( pResetWires[424] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8787 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8788 ) ,
+ .Reset_E_in ( ResetWires[210] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8789 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8790 ) ,
+ .Reset_W_out ( ResetWires[207] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8791 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[202] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[203] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8792 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8793 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[55] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8794 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1808 ) ,
+ .prog_clk_3_N_in ( p995 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8795 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8796 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8797 ) ,
+ .clk_2_S_in ( clk_2_wires[55] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8798 ) ,
+ .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1808 ) ,
+ .clk_3_N_in ( p279 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8800 ) ) ;
+cby_1__1_ cby_5__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8801 } ) ,
+ .chany_bottom_in ( sb_1__1__52_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__53_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_57_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__57_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__57_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__57_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8802 ) ,
+ .Test_en_E_in ( Test_enWires[232] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8803 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8804 ) ,
+ .Test_en_W_out ( Test_enWires[229] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8805 ) ,
+ .pReset_S_in ( pResetWires[473] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8806 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8807 ) ,
+ .Reset_E_in ( ResetWires[232] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8808 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8809 ) ,
+ .Reset_W_out ( ResetWires[229] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8810 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[205] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[206] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8811 ) ,
+ .prog_clk_2_N_in ( p2977 ) , .prog_clk_2_S_in ( p2529 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8812 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8813 ) ,
+ .prog_clk_3_S_in ( p2707 ) , .prog_clk_3_N_in ( p2899 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8814 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_2_N_in ( p1585 ) ,
+ .clk_2_S_in ( p2913 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p3012 ) ,
+ .clk_3_N_in ( p894 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8819 ) ) ;
+cby_1__1_ cby_5__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8820 } ) ,
+ .chany_bottom_in ( sb_1__1__53_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__54_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_58_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__58_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__58_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__58_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8821 ) ,
+ .Test_en_E_in ( Test_enWires[254] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8822 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8823 ) ,
+ .Test_en_W_out ( Test_enWires[251] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8824 ) ,
+ .pReset_S_in ( pResetWires[522] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8825 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8826 ) ,
+ .Reset_E_in ( ResetWires[254] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8827 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8828 ) ,
+ .Reset_W_out ( ResetWires[251] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8829 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[208] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[209] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8830 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8831 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[66] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8832 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p2097 ) ,
+ .prog_clk_3_N_in ( p920 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8833 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8834 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8835 ) ,
+ .clk_2_S_in ( clk_2_wires[66] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8836 ) ,
+ .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p2241 ) ,
+ .clk_3_N_in ( p53 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8838 ) ) ;
+cby_1__1_ cby_5__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8839 } ) ,
+ .chany_bottom_in ( sb_1__1__54_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_59_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__59_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__59_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__59_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8840 ) ,
+ .Test_en_E_in ( Test_enWires[276] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8841 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8842 ) ,
+ .Test_en_W_out ( Test_enWires[273] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8843 ) ,
+ .pReset_S_in ( pResetWires[571] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8844 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8845 ) ,
+ .Reset_E_in ( ResetWires[276] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8846 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8847 ) ,
+ .Reset_W_out ( ResetWires[273] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8848 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[211] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[212] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p2807 ) ,
+ .prog_clk_2_S_in ( p3140 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8849 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8850 ) ,
+ .prog_clk_3_S_in ( p3178 ) , .prog_clk_3_N_in ( p2737 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8851 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_2_N_in ( p2094 ) ,
+ .clk_2_S_in ( p2005 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p2161 ) ,
+ .clk_3_N_in ( p1717 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8856 ) ) ;
+cby_1__1_ cby_6__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8857 } ) ,
+ .chany_bottom_in ( sb_1__0__5_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__55_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_60_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__60_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__60_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__60_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[1] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8858 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8859 ) ,
+ .Test_en_N_out ( Test_enWires[2] ) , .Test_en_W_out ( Test_enWires[33] ) ,
+ .Test_en_E_out ( Test_enWires[35] ) , .pReset_S_in ( pResetWires[42] ) ,
+ .pReset_N_out ( pResetWires[2] ) , .Reset_S_in ( ResetWires[1] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8860 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8861 ) ,
+ .Reset_N_out ( ResetWires[2] ) , .Reset_W_out ( ResetWires[33] ) ,
+ .Reset_E_out ( ResetWires[35] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[216] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[217] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8862 ) ,
+ .prog_clk_2_N_in ( p1527 ) , .prog_clk_2_S_in ( p1385 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8863 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8864 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[90] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8865 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[89] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8866 ) , .clk_2_N_in ( p1527 ) ,
+ .clk_2_S_in ( p1269 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8867 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8868 ) ,
+ .clk_3_S_in ( clk_3_wires[90] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8869 ) ,
+ .clk_3_N_out ( clk_3_wires[89] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8870 ) ) ;
+cby_1__1_ cby_6__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8871 } ) ,
+ .chany_bottom_in ( sb_1__1__55_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__56_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_61_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__61_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__61_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__61_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[3] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8872 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8873 ) ,
+ .Test_en_N_out ( Test_enWires[4] ) , .Test_en_W_out ( Test_enWires[55] ) ,
+ .Test_en_E_out ( Test_enWires[57] ) , .pReset_S_in ( pResetWires[85] ) ,
+ .pReset_N_out ( pResetWires[4] ) , .Reset_S_in ( ResetWires[3] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8874 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8875 ) ,
+ .Reset_N_out ( ResetWires[4] ) , .Reset_W_out ( ResetWires[55] ) ,
+ .Reset_E_out ( ResetWires[57] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[219] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[220] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8876 ) ,
+ .prog_clk_2_N_in ( p1911 ) , .prog_clk_2_S_in ( p1380 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8877 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8878 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[92] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8879 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[91] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8880 ) , .clk_2_N_in ( p1911 ) ,
+ .clk_2_S_in ( p2543 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8881 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8882 ) ,
+ .clk_3_S_in ( clk_3_wires[92] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8883 ) ,
+ .clk_3_N_out ( clk_3_wires[91] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8884 ) ) ;
+cby_1__1_ cby_6__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8885 } ) ,
+ .chany_bottom_in ( sb_1__1__56_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__57_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_62_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__62_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__62_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__62_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[5] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8886 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8887 ) ,
+ .Test_en_N_out ( Test_enWires[6] ) , .Test_en_W_out ( Test_enWires[77] ) ,
+ .Test_en_E_out ( Test_enWires[79] ) , .pReset_S_in ( pResetWires[134] ) ,
+ .pReset_N_out ( pResetWires[6] ) , .Reset_S_in ( ResetWires[5] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8888 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8889 ) ,
+ .Reset_N_out ( ResetWires[6] ) , .Reset_W_out ( ResetWires[77] ) ,
+ .Reset_E_out ( ResetWires[79] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[222] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[223] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8890 ) ,
+ .prog_clk_2_N_in ( p1169 ) , .prog_clk_2_S_in ( p1972 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8891 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8892 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[94] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8893 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[93] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8894 ) , .clk_2_N_in ( p1169 ) ,
+ .clk_2_S_in ( p2052 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8895 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8896 ) ,
+ .clk_3_S_in ( clk_3_wires[94] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8897 ) ,
+ .clk_3_N_out ( clk_3_wires[93] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8898 ) ) ;
+cby_1__1_ cby_6__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8899 } ) ,
+ .chany_bottom_in ( sb_1__1__57_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__58_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_63_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__63_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__63_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__63_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[7] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8900 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8901 ) ,
+ .Test_en_N_out ( Test_enWires[8] ) , .Test_en_W_out ( Test_enWires[99] ) ,
+ .Test_en_E_out ( Test_enWires[101] ) , .pReset_S_in ( pResetWires[183] ) ,
+ .pReset_N_out ( pResetWires[8] ) , .Reset_S_in ( ResetWires[7] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8902 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8903 ) ,
+ .Reset_N_out ( ResetWires[8] ) , .Reset_W_out ( ResetWires[99] ) ,
+ .Reset_E_out ( ResetWires[101] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[225] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[226] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8904 ) ,
+ .prog_clk_2_N_in ( p1786 ) , .prog_clk_2_S_in ( p1958 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8905 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8906 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[96] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8907 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[95] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8908 ) , .clk_2_N_in ( p1786 ) ,
+ .clk_2_S_in ( p2264 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8909 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8910 ) ,
+ .clk_3_S_in ( clk_3_wires[96] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8911 ) ,
+ .clk_3_N_out ( clk_3_wires[95] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8912 ) ) ;
+cby_1__1_ cby_6__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8913 } ) ,
+ .chany_bottom_in ( sb_1__1__58_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__59_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_64_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__64_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__64_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__64_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[9] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8914 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8915 ) ,
+ .Test_en_N_out ( Test_enWires[10] ) ,
+ .Test_en_W_out ( Test_enWires[121] ) ,
+ .Test_en_E_out ( Test_enWires[123] ) , .pReset_S_in ( pResetWires[232] ) ,
+ .pReset_N_out ( pResetWires[10] ) , .Reset_S_in ( ResetWires[9] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8916 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8917 ) ,
+ .Reset_N_out ( ResetWires[10] ) , .Reset_W_out ( ResetWires[121] ) ,
+ .Reset_E_out ( ResetWires[123] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[228] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[229] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8918 ) ,
+ .prog_clk_2_N_in ( p1933 ) , .prog_clk_2_S_in ( p2309 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8919 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8920 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[98] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8921 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[97] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8922 ) , .clk_2_N_in ( p2046 ) ,
+ .clk_2_S_in ( p2295 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8923 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8924 ) ,
+ .clk_3_S_in ( clk_3_wires[98] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8925 ) ,
+ .clk_3_N_out ( clk_3_wires[97] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8926 ) ) ;
+cby_1__1_ cby_6__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8927 } ) ,
+ .chany_bottom_in ( sb_1__1__59_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__60_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_65_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__65_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__65_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__65_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[11] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8928 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8929 ) ,
+ .Test_en_N_out ( Test_enWires[12] ) ,
+ .Test_en_W_out ( Test_enWires[143] ) ,
+ .Test_en_E_out ( Test_enWires[145] ) , .pReset_S_in ( pResetWires[281] ) ,
+ .pReset_N_out ( pResetWires[12] ) , .Reset_S_in ( ResetWires[11] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8930 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8931 ) ,
+ .Reset_N_out ( ResetWires[12] ) , .Reset_W_out ( ResetWires[143] ) ,
+ .Reset_E_out ( ResetWires[145] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[231] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[232] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8932 ) ,
+ .prog_clk_2_N_in ( p1582 ) , .prog_clk_2_S_in ( p2055 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8933 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8934 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[100] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8935 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[99] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8936 ) , .clk_2_N_in ( p1582 ) ,
+ .clk_2_S_in ( p1960 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8937 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8938 ) ,
+ .clk_3_S_in ( clk_3_wires[100] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8939 ) ,
+ .clk_3_N_out ( clk_3_wires[99] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8940 ) ) ;
+cby_1__1_ cby_6__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8941 } ) ,
+ .chany_bottom_in ( sb_1__1__60_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__61_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_66_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__66_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__66_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__66_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[13] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8942 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8943 ) ,
+ .Test_en_N_out ( Test_enWires[14] ) ,
+ .Test_en_W_out ( Test_enWires[165] ) ,
+ .Test_en_E_out ( Test_enWires[167] ) , .pReset_S_in ( pResetWires[330] ) ,
+ .pReset_N_out ( pResetWires[14] ) , .Reset_S_in ( ResetWires[13] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8944 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8945 ) ,
+ .Reset_N_out ( ResetWires[14] ) , .Reset_W_out ( ResetWires[165] ) ,
+ .Reset_E_out ( ResetWires[167] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[234] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[235] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8946 ) ,
+ .prog_clk_2_N_in ( p3203 ) , .prog_clk_2_S_in ( p1962 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8947 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8948 ) ,
+ .prog_clk_3_S_in ( p2129 ) , .prog_clk_3_N_in ( p3155 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8949 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_2_N_in ( p1929 ) ,
+ .clk_2_S_in ( p2060 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p1475 ) ,
+ .clk_3_N_in ( p481 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8954 ) ) ;
+cby_1__1_ cby_6__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8955 } ) ,
+ .chany_bottom_in ( sb_1__1__61_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__62_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_67_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__67_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__67_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__67_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[15] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8956 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8957 ) ,
+ .Test_en_N_out ( Test_enWires[16] ) ,
+ .Test_en_W_out ( Test_enWires[187] ) ,
+ .Test_en_E_out ( Test_enWires[189] ) , .pReset_S_in ( pResetWires[379] ) ,
+ .pReset_N_out ( pResetWires[16] ) , .Reset_S_in ( ResetWires[15] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8958 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8959 ) ,
+ .Reset_N_out ( ResetWires[16] ) , .Reset_W_out ( ResetWires[187] ) ,
+ .Reset_E_out ( ResetWires[189] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[237] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[238] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8960 ) ,
+ .prog_clk_2_N_in ( p1833 ) , .prog_clk_2_S_in ( p1708 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8961 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8962 ) ,
+ .prog_clk_3_S_in ( p1829 ) , .prog_clk_3_N_in ( p2728 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8963 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_2_N_in ( p2805 ) ,
+ .clk_2_S_in ( p2257 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p2457 ) ,
+ .clk_3_N_in ( p768 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8968 ) ) ;
+cby_1__1_ cby_6__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8969 } ) ,
+ .chany_bottom_in ( sb_1__1__62_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__63_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_68_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__68_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__68_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__68_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[17] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8970 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8971 ) ,
+ .Test_en_N_out ( Test_enWires[18] ) ,
+ .Test_en_W_out ( Test_enWires[209] ) ,
+ .Test_en_E_out ( Test_enWires[211] ) , .pReset_S_in ( pResetWires[428] ) ,
+ .pReset_N_out ( pResetWires[18] ) , .Reset_S_in ( ResetWires[17] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8972 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8973 ) ,
+ .Reset_N_out ( ResetWires[18] ) , .Reset_W_out ( ResetWires[209] ) ,
+ .Reset_E_out ( ResetWires[211] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[240] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[241] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8974 ) ,
+ .prog_clk_2_N_in ( p3223 ) , .prog_clk_2_S_in ( p2574 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8975 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8976 ) ,
+ .prog_clk_3_S_in ( p2627 ) , .prog_clk_3_N_in ( p3153 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8977 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_2_N_in ( p2678 ) ,
+ .clk_2_S_in ( p2765 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p2810 ) ,
+ .clk_3_N_in ( p1042 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8982 ) ) ;
+cby_1__1_ cby_6__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8983 } ) ,
+ .chany_bottom_in ( sb_1__1__63_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__64_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_69_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__69_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__69_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__69_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[19] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8984 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8985 ) ,
+ .Test_en_N_out ( Test_enWires[20] ) ,
+ .Test_en_W_out ( Test_enWires[231] ) ,
+ .Test_en_E_out ( Test_enWires[233] ) , .pReset_S_in ( pResetWires[477] ) ,
+ .pReset_N_out ( pResetWires[20] ) , .Reset_S_in ( ResetWires[19] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8986 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8987 ) ,
+ .Reset_N_out ( ResetWires[20] ) , .Reset_W_out ( ResetWires[231] ) ,
+ .Reset_E_out ( ResetWires[233] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[243] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[244] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8988 ) ,
+ .prog_clk_2_N_in ( p3215 ) , .prog_clk_2_S_in ( p2536 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8989 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8990 ) ,
+ .prog_clk_3_S_in ( p2672 ) , .prog_clk_3_N_in ( p3228 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8991 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_2_N_in ( p3287 ) ,
+ .clk_2_S_in ( p2888 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p2937 ) ,
+ .clk_3_N_in ( p497 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8996 ) ) ;
+cby_1__1_ cby_6__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8997 } ) ,
+ .chany_bottom_in ( sb_1__1__64_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__65_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_70_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__70_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__70_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__70_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[21] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8998 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8999 ) ,
+ .Test_en_N_out ( Test_enWires[22] ) ,
+ .Test_en_W_out ( Test_enWires[253] ) ,
+ .Test_en_E_out ( Test_enWires[255] ) , .pReset_S_in ( pResetWires[526] ) ,
+ .pReset_N_out ( pResetWires[22] ) , .Reset_S_in ( ResetWires[21] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9000 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_9001 ) ,
+ .Reset_N_out ( ResetWires[22] ) , .Reset_W_out ( ResetWires[253] ) ,
+ .Reset_E_out ( ResetWires[255] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[246] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[247] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9002 ) ,
+ .prog_clk_2_N_in ( p2953 ) , .prog_clk_2_S_in ( p3068 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9003 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9004 ) ,
+ .prog_clk_3_S_in ( p3081 ) , .prog_clk_3_N_in ( p2898 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9005 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_2_N_in ( p2972 ) ,
+ .clk_2_S_in ( p2266 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p2397 ) ,
+ .clk_3_N_in ( p1272 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9010 ) ) ;
+cby_1__1_ cby_6__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9011 } ) ,
+ .chany_bottom_in ( sb_1__1__65_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_71_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__71_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__71_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__71_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[23] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9012 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9013 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9014 ) ,
+ .Test_en_W_out ( Test_enWires[275] ) ,
+ .Test_en_E_out ( Test_enWires[277] ) , .pReset_S_in ( pResetWires[575] ) ,
+ .pReset_N_out ( pResetWires[24] ) , .Reset_S_in ( ResetWires[23] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9015 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_9016 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9017 ) ,
+ .Reset_W_out ( ResetWires[275] ) , .Reset_E_out ( ResetWires[277] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[249] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[250] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2864 ) ,
+ .prog_clk_2_S_in ( p3468 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9018 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9019 ) ,
+ .prog_clk_3_S_in ( p3486 ) , .prog_clk_3_N_in ( p2711 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9020 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_2_N_in ( p2220 ) ,
+ .clk_2_S_in ( p2562 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p2511 ) ,
+ .clk_3_N_in ( p214 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9025 ) ) ;
+cby_1__1_ cby_7__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9026 } ) ,
+ .chany_bottom_in ( sb_1__0__6_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__66_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_72_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__72_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__72_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__72_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9027 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9028 ) ,
+ .Test_en_W_in ( Test_enWires[36] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9029 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9030 ) ,
+ .Test_en_E_out ( Test_enWires[37] ) , .pReset_S_in ( pResetWires[45] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9031 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9032 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9033 ) ,
+ .Reset_W_in ( ResetWires[36] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9034 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9035 ) ,
+ .Reset_E_out ( ResetWires[37] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[254] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[255] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9036 ) ,
+ .prog_clk_2_N_in ( p3013 ) , .prog_clk_2_S_in ( p2255 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9037 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9038 ) ,
+ .prog_clk_3_S_in ( p2398 ) , .prog_clk_3_N_in ( p2921 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9039 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_2_N_in ( p2429 ) ,
+ .clk_2_S_in ( p3038 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p3083 ) ,
+ .clk_3_N_in ( p393 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9044 ) ) ;
+cby_1__1_ cby_7__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9045 } ) ,
+ .chany_bottom_in ( sb_1__1__66_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__67_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_73_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__73_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__73_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__73_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9046 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9047 ) ,
+ .Test_en_W_in ( Test_enWires[58] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9048 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9049 ) ,
+ .Test_en_E_out ( Test_enWires[59] ) , .pReset_S_in ( pResetWires[89] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9050 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9051 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9052 ) ,
+ .Reset_W_in ( ResetWires[58] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9053 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9054 ) ,
+ .Reset_E_out ( ResetWires[59] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[257] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[258] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9055 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[73] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9056 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[74] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9057 ) ,
+ .prog_clk_3_S_in ( p1890 ) , .prog_clk_3_N_in ( p275 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9058 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9059 ) ,
+ .clk_2_N_in ( clk_2_wires[73] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9060 ) ,
+ .clk_2_S_out ( clk_2_wires[74] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1890 ) ,
+ .clk_3_N_in ( p379 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9063 ) ) ;
+cby_1__1_ cby_7__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9064 } ) ,
+ .chany_bottom_in ( sb_1__1__67_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__68_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_74_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__74_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__74_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__74_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9065 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9066 ) ,
+ .Test_en_W_in ( Test_enWires[80] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9067 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9068 ) ,
+ .Test_en_E_out ( Test_enWires[81] ) , .pReset_S_in ( pResetWires[138] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9069 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9070 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9071 ) ,
+ .Reset_W_in ( ResetWires[80] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9072 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9073 ) ,
+ .Reset_E_out ( ResetWires[81] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[260] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[261] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9074 ) ,
+ .prog_clk_2_N_in ( p2421 ) , .prog_clk_2_S_in ( p1959 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9075 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9076 ) ,
+ .prog_clk_3_S_in ( p2205 ) , .prog_clk_3_N_in ( p2312 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9077 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_2_N_in ( p2119 ) ,
+ .clk_2_S_in ( p2302 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2399 ) ,
+ .clk_3_N_in ( p1007 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9082 ) ) ;
+cby_1__1_ cby_7__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9083 } ) ,
+ .chany_bottom_in ( sb_1__1__68_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__69_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_75_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__75_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__75_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__75_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9084 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9085 ) ,
+ .Test_en_W_in ( Test_enWires[102] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9086 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9087 ) ,
+ .Test_en_E_out ( Test_enWires[103] ) , .pReset_S_in ( pResetWires[187] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9088 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9089 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9090 ) ,
+ .Reset_W_in ( ResetWires[102] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9091 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9092 ) ,
+ .Reset_E_out ( ResetWires[103] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[263] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[264] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9093 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[84] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9094 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[85] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9095 ) ,
+ .prog_clk_3_S_in ( p2216 ) , .prog_clk_3_N_in ( p256 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9096 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9097 ) ,
+ .clk_2_N_in ( clk_2_wires[84] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9098 ) ,
+ .clk_2_S_out ( clk_2_wires[85] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p2216 ) ,
+ .clk_3_N_in ( p765 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9101 ) ) ;
+cby_1__1_ cby_7__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9102 } ) ,
+ .chany_bottom_in ( sb_1__1__69_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__70_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_76_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__76_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__76_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__76_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9103 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9104 ) ,
+ .Test_en_W_in ( Test_enWires[124] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9105 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9106 ) ,
+ .Test_en_E_out ( Test_enWires[125] ) , .pReset_S_in ( pResetWires[236] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9107 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9108 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9109 ) ,
+ .Reset_W_in ( ResetWires[124] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9110 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9111 ) ,
+ .Reset_E_out ( ResetWires[125] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[266] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[267] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9112 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9113 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[82] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9114 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p1164 ) ,
+ .prog_clk_3_N_in ( p528 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9115 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9116 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9117 ) ,
+ .clk_2_S_in ( clk_2_wires[82] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9118 ) ,
+ .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p1164 ) ,
+ .clk_3_N_in ( p24 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9120 ) ) ;
+cby_1__1_ cby_7__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9121 } ) ,
+ .chany_bottom_in ( sb_1__1__70_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__71_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_77_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__77_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__77_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__77_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9122 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9123 ) ,
+ .Test_en_W_in ( Test_enWires[146] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9124 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9125 ) ,
+ .Test_en_E_out ( Test_enWires[147] ) , .pReset_S_in ( pResetWires[285] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9126 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9127 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9128 ) ,
+ .Reset_W_in ( ResetWires[146] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9129 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9130 ) ,
+ .Reset_E_out ( ResetWires[147] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[269] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[270] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9131 ) ,
+ .prog_clk_2_N_in ( p3006 ) , .prog_clk_2_S_in ( p2911 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9132 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9133 ) ,
+ .prog_clk_3_S_in ( p2943 ) , .prog_clk_3_N_in ( p2883 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9134 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_2_N_in ( p3004 ) ,
+ .clk_2_S_in ( p1712 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p1836 ) ,
+ .clk_3_N_in ( p1094 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9139 ) ) ;
+cby_1__1_ cby_7__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9140 } ) ,
+ .chany_bottom_in ( sb_1__1__71_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__72_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_78_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__78_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__78_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__78_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9141 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9142 ) ,
+ .Test_en_W_in ( Test_enWires[168] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9143 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9144 ) ,
+ .Test_en_E_out ( Test_enWires[169] ) , .pReset_S_in ( pResetWires[334] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9145 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9146 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9147 ) ,
+ .Reset_W_in ( ResetWires[168] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9148 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9149 ) ,
+ .Reset_E_out ( ResetWires[169] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[272] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[273] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9150 ) ,
+ .prog_clk_2_N_in ( p3406 ) , .prog_clk_2_S_in ( p3044 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9151 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9152 ) ,
+ .prog_clk_3_S_in ( p3118 ) , .prog_clk_3_N_in ( p3395 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9153 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_2_N_in ( p2847 ) ,
+ .clk_2_S_in ( p2932 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p2817 ) ,
+ .clk_3_N_in ( p794 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9158 ) ) ;
+cby_1__1_ cby_7__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9159 } ) ,
+ .chany_bottom_in ( sb_1__1__72_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__73_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_79_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__79_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__79_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__79_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9160 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9161 ) ,
+ .Test_en_W_in ( Test_enWires[190] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9162 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9163 ) ,
+ .Test_en_E_out ( Test_enWires[191] ) , .pReset_S_in ( pResetWires[383] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9164 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9165 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9166 ) ,
+ .Reset_W_in ( ResetWires[190] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9167 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9168 ) ,
+ .Reset_E_out ( ResetWires[191] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[275] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[276] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9169 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[97] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9170 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[98] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9171 ) ,
+ .prog_clk_3_S_in ( p1821 ) , .prog_clk_3_N_in ( p237 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9172 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9173 ) ,
+ .clk_2_N_in ( clk_2_wires[97] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9174 ) ,
+ .clk_2_S_out ( clk_2_wires[98] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p1821 ) ,
+ .clk_3_N_in ( p970 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9177 ) ) ;
+cby_1__1_ cby_7__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9178 } ) ,
+ .chany_bottom_in ( sb_1__1__73_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__74_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_80_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__80_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__80_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__80_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9179 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9180 ) ,
+ .Test_en_W_in ( Test_enWires[212] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9181 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9182 ) ,
+ .Test_en_E_out ( Test_enWires[213] ) , .pReset_S_in ( pResetWires[432] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9183 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9184 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9185 ) ,
+ .Reset_W_in ( ResetWires[212] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9186 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9187 ) ,
+ .Reset_E_out ( ResetWires[213] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[278] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[279] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9188 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9189 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[95] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9190 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p2450 ) ,
+ .prog_clk_3_N_in ( p513 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9191 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9192 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9193 ) ,
+ .clk_2_S_in ( clk_2_wires[95] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9194 ) ,
+ .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p2352 ) ,
+ .clk_3_N_in ( p122 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9196 ) ) ;
+cby_1__1_ cby_7__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9197 } ) ,
+ .chany_bottom_in ( sb_1__1__74_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__75_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_81_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__81_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__81_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__81_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9198 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9199 ) ,
+ .Test_en_W_in ( Test_enWires[234] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9200 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9201 ) ,
+ .Test_en_E_out ( Test_enWires[235] ) , .pReset_S_in ( pResetWires[481] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9202 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9203 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9204 ) ,
+ .Reset_W_in ( ResetWires[234] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9205 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9206 ) ,
+ .Reset_E_out ( ResetWires[235] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[281] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[282] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9207 ) ,
+ .prog_clk_2_N_in ( p2604 ) , .prog_clk_2_S_in ( p2732 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9208 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9209 ) ,
+ .prog_clk_3_S_in ( p2825 ) , .prog_clk_3_N_in ( p2567 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9210 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_2_N_in ( p2662 ) ,
+ .clk_2_S_in ( p3260 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p3261 ) ,
+ .clk_3_N_in ( p382 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9215 ) ) ;
+cby_1__1_ cby_7__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9216 } ) ,
+ .chany_bottom_in ( sb_1__1__75_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__76_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_82_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__82_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__82_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__82_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9217 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9218 ) ,
+ .Test_en_W_in ( Test_enWires[256] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9219 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9220 ) ,
+ .Test_en_E_out ( Test_enWires[257] ) , .pReset_S_in ( pResetWires[530] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9221 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9222 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9223 ) ,
+ .Reset_W_in ( ResetWires[256] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9224 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9225 ) ,
+ .Reset_E_out ( ResetWires[257] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[284] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[285] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9226 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9227 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[108] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9228 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1818 ) ,
+ .prog_clk_3_N_in ( p40 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9229 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9230 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9231 ) ,
+ .clk_2_S_in ( clk_2_wires[108] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9232 ) ,
+ .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1818 ) ,
+ .clk_3_N_in ( p960 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9234 ) ) ;
+cby_1__1_ cby_7__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9235 } ) ,
+ .chany_bottom_in ( sb_1__1__76_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_83_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__83_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__83_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__83_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9236 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9237 ) ,
+ .Test_en_W_in ( Test_enWires[278] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9238 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9239 ) ,
+ .Test_en_E_out ( Test_enWires[279] ) , .pReset_S_in ( pResetWires[579] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9240 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9241 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9242 ) ,
+ .Reset_W_in ( ResetWires[278] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9243 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9244 ) ,
+ .Reset_E_out ( ResetWires[279] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[287] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[288] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p2497 ) ,
+ .prog_clk_2_S_in ( p2273 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9245 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9246 ) ,
+ .prog_clk_3_S_in ( p2463 ) , .prog_clk_3_N_in ( p2289 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9247 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_2_N_in ( p2170 ) ,
+ .clk_2_S_in ( p2336 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p2388 ) ,
+ .clk_3_N_in ( p1956 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9252 ) ) ;
+cby_1__1_ cby_8__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9253 } ) ,
+ .chany_bottom_in ( sb_1__0__7_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__77_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_84_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__84_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__84_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__84_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9254 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9255 ) ,
+ .Test_en_W_in ( Test_enWires[38] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9256 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9257 ) ,
+ .Test_en_E_out ( Test_enWires[39] ) , .pReset_S_in ( pResetWires[48] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9258 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9259 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9260 ) ,
+ .Reset_W_in ( ResetWires[38] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9261 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9262 ) ,
+ .Reset_E_out ( ResetWires[39] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[292] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[293] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9263 ) ,
+ .prog_clk_2_N_in ( p2838 ) , .prog_clk_2_S_in ( p2769 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9264 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9265 ) ,
+ .prog_clk_3_S_in ( p2830 ) , .prog_clk_3_N_in ( p2758 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9266 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_2_N_in ( p2163 ) ,
+ .clk_2_S_in ( p3034 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p3088 ) ,
+ .clk_3_N_in ( p1677 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9271 ) ) ;
+cby_1__1_ cby_8__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9272 } ) ,
+ .chany_bottom_in ( sb_1__1__77_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__78_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_85_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__85_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__85_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__85_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9273 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9274 ) ,
+ .Test_en_W_in ( Test_enWires[60] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9275 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9276 ) ,
+ .Test_en_E_out ( Test_enWires[61] ) , .pReset_S_in ( pResetWires[93] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9277 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9278 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9279 ) ,
+ .Reset_W_in ( ResetWires[60] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9280 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9281 ) ,
+ .Reset_E_out ( ResetWires[61] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[295] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[296] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9282 ) ,
+ .prog_clk_2_N_in ( p2996 ) , .prog_clk_2_S_in ( p2246 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9283 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9284 ) ,
+ .prog_clk_3_S_in ( p2409 ) , .prog_clk_3_N_in ( p2880 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9285 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_2_N_in ( p2999 ) ,
+ .clk_2_S_in ( p1729 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p1784 ) ,
+ .clk_3_N_in ( p338 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9290 ) ) ;
+cby_1__1_ cby_8__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9291 } ) ,
+ .chany_bottom_in ( sb_1__1__78_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__79_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_86_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__86_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__86_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__86_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9292 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9293 ) ,
+ .Test_en_W_in ( Test_enWires[82] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9294 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9295 ) ,
+ .Test_en_E_out ( Test_enWires[83] ) , .pReset_S_in ( pResetWires[142] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9296 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9297 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9298 ) ,
+ .Reset_W_in ( ResetWires[82] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9299 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9300 ) ,
+ .Reset_E_out ( ResetWires[83] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[298] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[299] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9301 ) ,
+ .prog_clk_2_N_in ( p829 ) , .prog_clk_2_S_in ( p443 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9302 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9303 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9304 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[42] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9305 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p829 ) ,
+ .clk_2_S_in ( p648 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9307 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9308 ) ,
+ .clk_3_N_in ( clk_3_wires[42] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9309 ) ,
+ .clk_3_S_out ( clk_3_wires[43] ) ) ;
+cby_1__1_ cby_8__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9310 } ) ,
+ .chany_bottom_in ( sb_1__1__79_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__80_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_87_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__87_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__87_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__87_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9311 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9312 ) ,
+ .Test_en_W_in ( Test_enWires[104] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9313 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9314 ) ,
+ .Test_en_E_out ( Test_enWires[105] ) , .pReset_S_in ( pResetWires[191] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9315 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9316 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9317 ) ,
+ .Reset_W_in ( ResetWires[104] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9318 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9319 ) ,
+ .Reset_E_out ( ResetWires[105] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[301] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[302] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9320 ) ,
+ .prog_clk_2_N_in ( p1235 ) , .prog_clk_2_S_in ( p1651 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9321 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9322 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9323 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[38] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9324 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1235 ) ,
+ .clk_2_S_in ( p2278 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9325 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9326 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9327 ) ,
+ .clk_3_N_in ( clk_3_wires[38] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9328 ) ,
+ .clk_3_S_out ( clk_3_wires[39] ) ) ;
+cby_1__1_ cby_8__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9329 } ) ,
+ .chany_bottom_in ( sb_1__1__80_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__81_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_88_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__88_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__88_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__88_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9330 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9331 ) ,
+ .Test_en_W_in ( Test_enWires[126] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9332 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9333 ) ,
+ .Test_en_E_out ( Test_enWires[127] ) , .pReset_S_in ( pResetWires[240] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9334 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9335 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9336 ) ,
+ .Reset_W_in ( ResetWires[126] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9337 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9338 ) ,
+ .Reset_E_out ( ResetWires[127] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[304] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[305] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9339 ) ,
+ .prog_clk_2_N_in ( p1406 ) , .prog_clk_2_S_in ( p1636 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9340 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9341 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9342 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[32] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9343 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p1406 ) ,
+ .clk_2_S_in ( p801 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9344 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9345 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9346 ) ,
+ .clk_3_N_in ( clk_3_wires[32] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9347 ) ,
+ .clk_3_S_out ( clk_3_wires[33] ) ) ;
+cby_1__1_ cby_8__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9348 } ) ,
+ .chany_bottom_in ( sb_1__1__81_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__82_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_89_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__89_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__89_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__89_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9349 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9350 ) ,
+ .Test_en_W_in ( Test_enWires[148] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9351 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9352 ) ,
+ .Test_en_E_out ( Test_enWires[149] ) , .pReset_S_in ( pResetWires[289] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9353 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9354 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9355 ) ,
+ .Reset_W_in ( ResetWires[148] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9356 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9357 ) ,
+ .Reset_E_out ( ResetWires[149] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[307] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[308] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9358 ) ,
+ .prog_clk_2_N_in ( p1496 ) , .prog_clk_2_S_in ( p1970 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9359 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9360 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9361 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[28] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9362 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p1496 ) ,
+ .clk_2_S_in ( p2256 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9364 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9365 ) ,
+ .clk_3_N_in ( clk_3_wires[28] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9366 ) ,
+ .clk_3_S_out ( clk_3_wires[29] ) ) ;
+cby_1__1_ cby_8__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9367 } ) ,
+ .chany_bottom_in ( sb_1__1__82_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__83_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_90_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__90_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__90_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__90_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9368 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9369 ) ,
+ .Test_en_W_in ( Test_enWires[170] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9370 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9371 ) ,
+ .Test_en_E_out ( Test_enWires[171] ) , .pReset_S_in ( pResetWires[338] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9372 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9373 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9374 ) ,
+ .Reset_W_in ( ResetWires[170] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9375 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9376 ) ,
+ .Reset_E_out ( ResetWires[171] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[310] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[311] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9377 ) ,
+ .prog_clk_2_N_in ( p1601 ) , .prog_clk_2_S_in ( p2341 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9378 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9379 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[26] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9380 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[27] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9381 ) , .clk_2_N_in ( p1601 ) ,
+ .clk_2_S_in ( p2538 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9382 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9383 ) ,
+ .clk_3_S_in ( clk_3_wires[26] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9384 ) ,
+ .clk_3_N_out ( clk_3_wires[27] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9385 ) ) ;
+cby_1__1_ cby_8__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9386 } ) ,
+ .chany_bottom_in ( sb_1__1__83_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__84_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_91_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__91_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__91_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__91_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9387 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9388 ) ,
+ .Test_en_W_in ( Test_enWires[192] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9389 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9390 ) ,
+ .Test_en_E_out ( Test_enWires[193] ) , .pReset_S_in ( pResetWires[387] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9391 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9392 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9393 ) ,
+ .Reset_W_in ( ResetWires[192] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9394 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9395 ) ,
+ .Reset_E_out ( ResetWires[193] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[313] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[314] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9396 ) ,
+ .prog_clk_2_N_in ( p1600 ) , .prog_clk_2_S_in ( p2040 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9397 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9398 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[30] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9399 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[31] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9400 ) , .clk_2_N_in ( p1600 ) ,
+ .clk_2_S_in ( p2288 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9401 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9402 ) ,
+ .clk_3_S_in ( clk_3_wires[30] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9403 ) ,
+ .clk_3_N_out ( clk_3_wires[31] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9404 ) ) ;
+cby_1__1_ cby_8__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9405 } ) ,
+ .chany_bottom_in ( sb_1__1__84_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__85_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_92_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__92_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__92_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__92_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9406 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9407 ) ,
+ .Test_en_W_in ( Test_enWires[214] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9408 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9409 ) ,
+ .Test_en_E_out ( Test_enWires[215] ) , .pReset_S_in ( pResetWires[436] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9410 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9411 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9412 ) ,
+ .Reset_W_in ( ResetWires[214] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9413 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9414 ) ,
+ .Reset_E_out ( ResetWires[215] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[316] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[317] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9415 ) ,
+ .prog_clk_2_N_in ( p2156 ) , .prog_clk_2_S_in ( p1641 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9416 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9417 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[36] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9418 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[37] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9419 ) , .clk_2_N_in ( p2206 ) ,
+ .clk_2_S_in ( p164 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9420 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9421 ) ,
+ .clk_3_S_in ( clk_3_wires[36] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9422 ) ,
+ .clk_3_N_out ( clk_3_wires[37] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9423 ) ) ;
+cby_1__1_ cby_8__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9424 } ) ,
+ .chany_bottom_in ( sb_1__1__85_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__86_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_93_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__93_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__93_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__93_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9425 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9426 ) ,
+ .Test_en_W_in ( Test_enWires[236] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9427 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9428 ) ,
+ .Test_en_E_out ( Test_enWires[237] ) , .pReset_S_in ( pResetWires[485] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9429 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9430 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9431 ) ,
+ .Reset_W_in ( ResetWires[236] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9432 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9433 ) ,
+ .Reset_E_out ( ResetWires[237] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[319] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[320] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9434 ) ,
+ .prog_clk_2_N_in ( p1806 ) , .prog_clk_2_S_in ( p2035 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9435 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9436 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[40] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9437 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[41] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9438 ) , .clk_2_N_in ( p1806 ) ,
+ .clk_2_S_in ( p2003 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9439 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9440 ) ,
+ .clk_3_S_in ( clk_3_wires[40] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9441 ) ,
+ .clk_3_N_out ( clk_3_wires[41] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9442 ) ) ;
+cby_1__1_ cby_8__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9443 } ) ,
+ .chany_bottom_in ( sb_1__1__86_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__87_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_94_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__94_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__94_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__94_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9444 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9445 ) ,
+ .Test_en_W_in ( Test_enWires[258] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9446 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9447 ) ,
+ .Test_en_E_out ( Test_enWires[259] ) , .pReset_S_in ( pResetWires[534] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9448 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9449 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9450 ) ,
+ .Reset_W_in ( ResetWires[258] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9451 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9452 ) ,
+ .Reset_E_out ( ResetWires[259] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[322] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[323] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9453 ) ,
+ .prog_clk_2_N_in ( p1937 ) , .prog_clk_2_S_in ( p2725 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9454 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9455 ) ,
+ .prog_clk_3_S_in ( p2824 ) , .prog_clk_3_N_in ( p2265 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9456 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_2_N_in ( p2417 ) ,
+ .clk_2_S_in ( p2889 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2969 ) ,
+ .clk_3_N_in ( p1283 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9461 ) ) ;
+cby_1__1_ cby_8__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9462 } ) ,
+ .chany_bottom_in ( sb_1__1__87_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_95_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__95_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__95_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__95_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9463 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9464 ) ,
+ .Test_en_W_in ( Test_enWires[280] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9465 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9466 ) ,
+ .Test_en_E_out ( Test_enWires[281] ) , .pReset_S_in ( pResetWires[583] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9467 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9468 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9469 ) ,
+ .Reset_W_in ( ResetWires[280] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9470 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9471 ) ,
+ .Reset_E_out ( ResetWires[281] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[325] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[326] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p2664 ) ,
+ .prog_clk_2_S_in ( p2274 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9472 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9473 ) ,
+ .prog_clk_3_S_in ( p2414 ) , .prog_clk_3_N_in ( p2712 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9474 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_2_N_in ( p2779 ) ,
+ .clk_2_S_in ( p2924 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p2936 ) ,
+ .clk_3_N_in ( p137 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9479 ) ) ;
+cby_1__1_ cby_9__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9480 } ) ,
+ .chany_bottom_in ( sb_1__0__8_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__88_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_96_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__96_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__96_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__96_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9481 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9482 ) ,
+ .Test_en_W_in ( Test_enWires[40] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9483 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9484 ) ,
+ .Test_en_E_out ( Test_enWires[41] ) , .pReset_S_in ( pResetWires[51] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9485 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9486 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9487 ) ,
+ .Reset_W_in ( ResetWires[40] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9488 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9489 ) ,
+ .Reset_E_out ( ResetWires[41] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[330] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[331] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9490 ) ,
+ .prog_clk_2_N_in ( p2233 ) , .prog_clk_2_S_in ( p2510 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9491 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9492 ) ,
+ .prog_clk_3_S_in ( p2642 ) , .prog_clk_3_N_in ( p2000 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9493 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_2_N_in ( p1026 ) ,
+ .clk_2_S_in ( p1285 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p1410 ) ,
+ .clk_3_N_in ( p303 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9498 ) ) ;
+cby_1__1_ cby_9__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9499 } ) ,
+ .chany_bottom_in ( sb_1__1__88_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__89_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_97_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__97_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__97_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__97_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9500 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9501 ) ,
+ .Test_en_W_in ( Test_enWires[62] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9502 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9503 ) ,
+ .Test_en_E_out ( Test_enWires[63] ) , .pReset_S_in ( pResetWires[97] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9504 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9505 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9506 ) ,
+ .Reset_W_in ( ResetWires[62] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9507 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9508 ) ,
+ .Reset_E_out ( ResetWires[63] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[333] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[334] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9509 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[75] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9510 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[76] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9511 ) ,
+ .prog_clk_3_S_in ( p2081 ) , .prog_clk_3_N_in ( p366 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9512 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9513 ) ,
+ .clk_2_N_in ( clk_2_wires[75] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9514 ) ,
+ .clk_2_S_out ( clk_2_wires[76] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p2081 ) ,
+ .clk_3_N_in ( p643 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9517 ) ) ;
+cby_1__1_ cby_9__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9518 } ) ,
+ .chany_bottom_in ( sb_1__1__89_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__90_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_98_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__98_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__98_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__98_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9519 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9520 ) ,
+ .Test_en_W_in ( Test_enWires[84] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9521 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9522 ) ,
+ .Test_en_E_out ( Test_enWires[85] ) , .pReset_S_in ( pResetWires[146] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9523 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9524 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9525 ) ,
+ .Reset_W_in ( ResetWires[84] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9526 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9527 ) ,
+ .Reset_E_out ( ResetWires[85] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[336] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[337] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9528 ) ,
+ .prog_clk_2_N_in ( p2788 ) , .prog_clk_2_S_in ( p2548 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9529 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9530 ) ,
+ .prog_clk_3_S_in ( p2598 ) , .prog_clk_3_N_in ( p2734 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9531 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_2_N_in ( p1189 ) ,
+ .clk_2_S_in ( p1284 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p1581 ) ,
+ .clk_3_N_in ( p625 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9536 ) ) ;
+cby_1__1_ cby_9__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9537 } ) ,
+ .chany_bottom_in ( sb_1__1__90_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__91_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_99_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__99_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__99_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__99_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9538 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9539 ) ,
+ .Test_en_W_in ( Test_enWires[106] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9540 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9541 ) ,
+ .Test_en_E_out ( Test_enWires[107] ) , .pReset_S_in ( pResetWires[195] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9542 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9543 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9544 ) ,
+ .Reset_W_in ( ResetWires[106] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9545 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9546 ) ,
+ .Reset_E_out ( ResetWires[107] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[339] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[340] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9547 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[88] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9548 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[89] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9549 ) ,
+ .prog_clk_3_S_in ( p2188 ) , .prog_clk_3_N_in ( p728 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9550 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9551 ) ,
+ .clk_2_N_in ( clk_2_wires[88] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9552 ) ,
+ .clk_2_S_out ( clk_2_wires[89] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p2188 ) ,
+ .clk_3_N_in ( p59 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9555 ) ) ;
+cby_1__1_ cby_9__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9556 } ) ,
+ .chany_bottom_in ( sb_1__1__91_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__92_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_100_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__100_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__100_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__100_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9557 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9558 ) ,
+ .Test_en_W_in ( Test_enWires[128] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9559 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9560 ) ,
+ .Test_en_E_out ( Test_enWires[129] ) , .pReset_S_in ( pResetWires[244] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9561 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9562 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9563 ) ,
+ .Reset_W_in ( ResetWires[128] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9564 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9565 ) ,
+ .Reset_E_out ( ResetWires[129] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[342] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[343] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9566 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9567 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[86] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9568 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p2439 ) ,
+ .prog_clk_3_N_in ( p307 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9569 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9570 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9571 ) ,
+ .clk_2_S_in ( clk_2_wires[86] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9572 ) ,
+ .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p2439 ) ,
+ .clk_3_N_in ( p937 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9574 ) ) ;
+cby_1__1_ cby_9__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9575 } ) ,
+ .chany_bottom_in ( sb_1__1__92_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__93_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_101_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__101_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__101_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__101_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9576 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9577 ) ,
+ .Test_en_W_in ( Test_enWires[150] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9578 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9579 ) ,
+ .Test_en_E_out ( Test_enWires[151] ) , .pReset_S_in ( pResetWires[293] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9580 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9581 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9582 ) ,
+ .Reset_W_in ( ResetWires[150] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9583 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9584 ) ,
+ .Reset_E_out ( ResetWires[151] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[345] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[346] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9585 ) ,
+ .prog_clk_2_N_in ( p2624 ) , .prog_clk_2_S_in ( p3142 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9586 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9587 ) ,
+ .prog_clk_3_S_in ( p3179 ) , .prog_clk_3_N_in ( p2742 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9588 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_2_N_in ( p2844 ) ,
+ .clk_2_S_in ( p2581 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2606 ) ,
+ .clk_3_N_in ( p10 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9593 ) ) ;
+cby_1__1_ cby_9__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9594 } ) ,
+ .chany_bottom_in ( sb_1__1__93_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__94_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_102_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__102_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__102_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__102_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9595 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9596 ) ,
+ .Test_en_W_in ( Test_enWires[172] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9597 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9598 ) ,
+ .Test_en_E_out ( Test_enWires[173] ) , .pReset_S_in ( pResetWires[342] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9599 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9600 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9601 ) ,
+ .Reset_W_in ( ResetWires[172] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9602 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9603 ) ,
+ .Reset_E_out ( ResetWires[173] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[348] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[349] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9604 ) ,
+ .prog_clk_2_N_in ( p2694 ) , .prog_clk_2_S_in ( p2774 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9605 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9606 ) ,
+ .prog_clk_3_S_in ( p2783 ) , .prog_clk_3_N_in ( p3159 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9607 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_2_N_in ( p3191 ) ,
+ .clk_2_S_in ( p2902 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p2993 ) ,
+ .clk_3_N_in ( p739 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9612 ) ) ;
+cby_1__1_ cby_9__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9613 } ) ,
+ .chany_bottom_in ( sb_1__1__94_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__95_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_103_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__103_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__103_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__103_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9614 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9615 ) ,
+ .Test_en_W_in ( Test_enWires[194] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9616 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9617 ) ,
+ .Test_en_E_out ( Test_enWires[195] ) , .pReset_S_in ( pResetWires[391] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9618 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9619 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9620 ) ,
+ .Reset_W_in ( ResetWires[194] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9621 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9622 ) ,
+ .Reset_E_out ( ResetWires[195] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[351] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[352] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9623 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[101] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9624 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[102] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9625 ) ,
+ .prog_clk_3_S_in ( p1925 ) , .prog_clk_3_N_in ( p54 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9626 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9627 ) ,
+ .clk_2_N_in ( clk_2_wires[101] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9628 ) ,
+ .clk_2_S_out ( clk_2_wires[102] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1925 ) ,
+ .clk_3_N_in ( p406 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9631 ) ) ;
+cby_1__1_ cby_9__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9632 } ) ,
+ .chany_bottom_in ( sb_1__1__95_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__96_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_104_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__104_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__104_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__104_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9633 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9634 ) ,
+ .Test_en_W_in ( Test_enWires[216] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9635 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9636 ) ,
+ .Test_en_E_out ( Test_enWires[217] ) , .pReset_S_in ( pResetWires[440] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9637 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9638 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9639 ) ,
+ .Reset_W_in ( ResetWires[216] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9640 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9641 ) ,
+ .Reset_E_out ( ResetWires[217] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[354] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[355] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9642 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9643 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[99] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9644 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1474 ) ,
+ .prog_clk_3_N_in ( p1038 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9645 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9646 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9647 ) ,
+ .clk_2_S_in ( clk_2_wires[99] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9648 ) ,
+ .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1474 ) ,
+ .clk_3_N_in ( p347 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9650 ) ) ;
+cby_1__1_ cby_9__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9651 } ) ,
+ .chany_bottom_in ( sb_1__1__96_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__97_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_105_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__105_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__105_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__105_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9652 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9653 ) ,
+ .Test_en_W_in ( Test_enWires[238] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9654 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9655 ) ,
+ .Test_en_E_out ( Test_enWires[239] ) , .pReset_S_in ( pResetWires[489] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9656 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9657 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9658 ) ,
+ .Reset_W_in ( ResetWires[238] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9659 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9660 ) ,
+ .Reset_E_out ( ResetWires[239] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[357] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[358] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9661 ) ,
+ .prog_clk_2_N_in ( p2110 ) , .prog_clk_2_S_in ( p2748 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9662 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9663 ) ,
+ .prog_clk_3_S_in ( p2862 ) , .prog_clk_3_N_in ( p2561 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9664 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_2_N_in ( p2665 ) ,
+ .clk_2_S_in ( p2515 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2643 ) ,
+ .clk_3_N_in ( p958 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9669 ) ) ;
+cby_1__1_ cby_9__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9670 } ) ,
+ .chany_bottom_in ( sb_1__1__97_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__98_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_106_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__106_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__106_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__106_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9671 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9672 ) ,
+ .Test_en_W_in ( Test_enWires[260] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9673 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9674 ) ,
+ .Test_en_E_out ( Test_enWires[261] ) , .pReset_S_in ( pResetWires[538] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9675 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9676 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9677 ) ,
+ .Reset_W_in ( ResetWires[260] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9678 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9679 ) ,
+ .Reset_E_out ( ResetWires[261] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[360] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[361] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9680 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9681 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[110] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9682 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1822 ) ,
+ .prog_clk_3_N_in ( p707 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9683 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9684 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9685 ) ,
+ .clk_2_S_in ( clk_2_wires[110] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9686 ) ,
+ .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p1822 ) ,
+ .clk_3_N_in ( p371 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9688 ) ) ;
+cby_1__1_ cby_9__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9689 } ) ,
+ .chany_bottom_in ( sb_1__1__98_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_107_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__107_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__107_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__107_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9690 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9691 ) ,
+ .Test_en_W_in ( Test_enWires[282] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9692 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9693 ) ,
+ .Test_en_E_out ( Test_enWires[283] ) , .pReset_S_in ( pResetWires[587] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9694 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9695 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9696 ) ,
+ .Reset_W_in ( ResetWires[282] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9697 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9698 ) ,
+ .Reset_E_out ( ResetWires[283] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[363] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[364] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p2861 ) ,
+ .prog_clk_2_S_in ( p3333 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9699 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9700 ) ,
+ .prog_clk_3_S_in ( p3360 ) , .prog_clk_3_N_in ( p2750 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9701 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_2_N_in ( p2801 ) ,
+ .clk_2_S_in ( p2036 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p2164 ) ,
+ .clk_3_N_in ( p1367 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9706 ) ) ;
+cby_1__1_ cby_10__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9707 } ) ,
+ .chany_bottom_in ( sb_1__0__9_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__99_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_108_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__108_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__108_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__108_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9708 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9709 ) ,
+ .Test_en_W_in ( Test_enWires[42] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9710 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9711 ) ,
+ .Test_en_E_out ( Test_enWires[43] ) , .pReset_S_in ( pResetWires[54] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9712 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9713 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9714 ) ,
+ .Reset_W_in ( ResetWires[42] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9715 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9716 ) ,
+ .Reset_E_out ( ResetWires[43] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[368] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[369] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9717 ) ,
+ .prog_clk_2_N_in ( p1196 ) , .prog_clk_2_S_in ( p1967 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9718 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9719 ) ,
+ .prog_clk_3_S_in ( p2116 ) , .prog_clk_3_N_in ( p2761 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9720 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_2_N_in ( p2835 ) ,
+ .clk_2_S_in ( p1281 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p1404 ) ,
+ .clk_3_N_in ( p1745 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9725 ) ) ;
+cby_1__1_ cby_10__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9726 } ) ,
+ .chany_bottom_in ( sb_1__1__99_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__100_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_109_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__109_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__109_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__109_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9727 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9728 ) ,
+ .Test_en_W_in ( Test_enWires[64] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9729 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9730 ) ,
+ .Test_en_E_out ( Test_enWires[65] ) , .pReset_S_in ( pResetWires[101] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9731 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9732 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9733 ) ,
+ .Reset_W_in ( ResetWires[64] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9734 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9735 ) ,
+ .Reset_E_out ( ResetWires[65] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[371] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[372] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9736 ) ,
+ .prog_clk_2_N_in ( p3349 ) , .prog_clk_2_S_in ( p3139 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9737 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9738 ) ,
+ .prog_clk_3_S_in ( p3214 ) , .prog_clk_3_N_in ( p3330 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9739 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_2_N_in ( p2613 ) ,
+ .clk_2_S_in ( p2571 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p2683 ) ,
+ .clk_3_N_in ( p66 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9744 ) ) ;
+cby_1__1_ cby_10__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9745 } ) ,
+ .chany_bottom_in ( sb_1__1__100_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__101_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_110_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__110_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__110_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__110_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9746 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9747 ) ,
+ .Test_en_W_in ( Test_enWires[86] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9748 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9749 ) ,
+ .Test_en_E_out ( Test_enWires[87] ) , .pReset_S_in ( pResetWires[150] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9750 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9751 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9752 ) ,
+ .Reset_W_in ( ResetWires[86] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9753 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9754 ) ,
+ .Reset_E_out ( ResetWires[87] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[374] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[375] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9755 ) ,
+ .prog_clk_2_N_in ( p1143 ) , .prog_clk_2_S_in ( p437 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9756 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9757 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9758 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[86] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9759 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p1143 ) ,
+ .clk_2_S_in ( p560 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9760 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9761 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9762 ) ,
+ .clk_3_N_in ( clk_3_wires[86] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9763 ) ,
+ .clk_3_S_out ( clk_3_wires[87] ) ) ;
+cby_1__1_ cby_10__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9764 } ) ,
+ .chany_bottom_in ( sb_1__1__101_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__102_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_111_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__111_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__111_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__111_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9765 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9766 ) ,
+ .Test_en_W_in ( Test_enWires[108] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9767 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9768 ) ,
+ .Test_en_E_out ( Test_enWires[109] ) , .pReset_S_in ( pResetWires[199] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9769 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9770 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9771 ) ,
+ .Reset_W_in ( ResetWires[108] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9772 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9773 ) ,
+ .Reset_E_out ( ResetWires[109] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[377] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[378] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9774 ) ,
+ .prog_clk_2_N_in ( p1213 ) , .prog_clk_2_S_in ( p1977 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9775 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9776 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9777 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[82] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9778 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( p1213 ) ,
+ .clk_2_S_in ( p2048 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9779 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9780 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9781 ) ,
+ .clk_3_N_in ( clk_3_wires[82] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9782 ) ,
+ .clk_3_S_out ( clk_3_wires[83] ) ) ;
+cby_1__1_ cby_10__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9783 } ) ,
+ .chany_bottom_in ( sb_1__1__102_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__103_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_112_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__112_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__112_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__112_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9784 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9785 ) ,
+ .Test_en_W_in ( Test_enWires[130] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9786 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9787 ) ,
+ .Test_en_E_out ( Test_enWires[131] ) , .pReset_S_in ( pResetWires[248] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9788 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9789 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9790 ) ,
+ .Reset_W_in ( ResetWires[130] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9791 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9792 ) ,
+ .Reset_E_out ( ResetWires[131] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[380] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[381] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9793 ) ,
+ .prog_clk_2_N_in ( p1761 ) , .prog_clk_2_S_in ( p678 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9794 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9795 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9796 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[76] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9797 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1761 ) ,
+ .clk_2_S_in ( p209 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9798 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9799 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9800 ) ,
+ .clk_3_N_in ( clk_3_wires[76] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9801 ) ,
+ .clk_3_S_out ( clk_3_wires[77] ) ) ;
+cby_1__1_ cby_10__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9802 } ) ,
+ .chany_bottom_in ( sb_1__1__103_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__104_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_113_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__113_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__113_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__113_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9803 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9804 ) ,
+ .Test_en_W_in ( Test_enWires[152] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9805 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9806 ) ,
+ .Test_en_E_out ( Test_enWires[153] ) , .pReset_S_in ( pResetWires[297] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9807 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9808 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9809 ) ,
+ .Reset_W_in ( ResetWires[152] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9810 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9811 ) ,
+ .Reset_E_out ( ResetWires[153] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[383] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[384] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9812 ) ,
+ .prog_clk_2_N_in ( p1454 ) , .prog_clk_2_S_in ( p1995 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9813 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9814 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9815 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[72] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9816 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p1454 ) ,
+ .clk_2_S_in ( p2540 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9817 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9818 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9819 ) ,
+ .clk_3_N_in ( clk_3_wires[72] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9820 ) ,
+ .clk_3_S_out ( clk_3_wires[73] ) ) ;
+cby_1__1_ cby_10__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9821 } ) ,
+ .chany_bottom_in ( sb_1__1__104_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__105_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_114_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__114_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__114_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__114_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9822 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9823 ) ,
+ .Test_en_W_in ( Test_enWires[174] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9824 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9825 ) ,
+ .Test_en_E_out ( Test_enWires[175] ) , .pReset_S_in ( pResetWires[346] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9826 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9827 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9828 ) ,
+ .Reset_W_in ( ResetWires[174] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9829 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9830 ) ,
+ .Reset_E_out ( ResetWires[175] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[386] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[387] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9831 ) ,
+ .prog_clk_2_N_in ( p1464 ) , .prog_clk_2_S_in ( p1338 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9832 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9833 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[70] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9834 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[71] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9835 ) , .clk_2_N_in ( p1464 ) ,
+ .clk_2_S_in ( p2502 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9836 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9837 ) ,
+ .clk_3_S_in ( clk_3_wires[70] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9838 ) ,
+ .clk_3_N_out ( clk_3_wires[71] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9839 ) ) ;
+cby_1__1_ cby_10__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9840 } ) ,
+ .chany_bottom_in ( sb_1__1__105_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__106_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_115_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__115_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__115_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__115_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9841 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9842 ) ,
+ .Test_en_W_in ( Test_enWires[196] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9843 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9844 ) ,
+ .Test_en_E_out ( Test_enWires[197] ) , .pReset_S_in ( pResetWires[395] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9845 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9846 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9847 ) ,
+ .Reset_W_in ( ResetWires[196] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9848 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9849 ) ,
+ .Reset_E_out ( ResetWires[197] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[389] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[390] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9850 ) ,
+ .prog_clk_2_N_in ( p799 ) , .prog_clk_2_S_in ( p1964 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9851 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9852 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[74] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9853 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[75] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , .clk_2_N_in ( p799 ) ,
+ .clk_2_S_in ( p2741 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9855 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9856 ) ,
+ .clk_3_S_in ( clk_3_wires[74] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9857 ) ,
+ .clk_3_N_out ( clk_3_wires[75] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9858 ) ) ;
+cby_1__1_ cby_10__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9859 } ) ,
+ .chany_bottom_in ( sb_1__1__106_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__107_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_116_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__116_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__116_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__116_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9860 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9861 ) ,
+ .Test_en_W_in ( Test_enWires[218] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9862 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9863 ) ,
+ .Test_en_E_out ( Test_enWires[219] ) , .pReset_S_in ( pResetWires[444] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9864 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9865 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9866 ) ,
+ .Reset_W_in ( ResetWires[218] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9867 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9868 ) ,
+ .Reset_E_out ( ResetWires[219] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[392] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[393] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9869 ) ,
+ .prog_clk_2_N_in ( p1384 ) , .prog_clk_2_S_in ( p1663 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9870 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9871 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[80] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9872 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[81] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9873 ) , .clk_2_N_in ( p1384 ) ,
+ .clk_2_S_in ( p180 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9874 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9875 ) ,
+ .clk_3_S_in ( clk_3_wires[80] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9876 ) ,
+ .clk_3_N_out ( clk_3_wires[81] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9877 ) ) ;
+cby_1__1_ cby_10__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9878 } ) ,
+ .chany_bottom_in ( sb_1__1__107_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__108_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_117_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__117_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__117_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__117_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9879 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9880 ) ,
+ .Test_en_W_in ( Test_enWires[240] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9881 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9882 ) ,
+ .Test_en_E_out ( Test_enWires[241] ) , .pReset_S_in ( pResetWires[493] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9883 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9884 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9885 ) ,
+ .Reset_W_in ( ResetWires[240] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9886 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9887 ) ,
+ .Reset_E_out ( ResetWires[241] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[395] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[396] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9888 ) ,
+ .prog_clk_2_N_in ( p1811 ) , .prog_clk_2_S_in ( p1620 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9889 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9890 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[84] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9891 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[85] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9892 ) , .clk_2_N_in ( p1811 ) ,
+ .clk_2_S_in ( p1723 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9893 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9894 ) ,
+ .clk_3_S_in ( clk_3_wires[84] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9895 ) ,
+ .clk_3_N_out ( clk_3_wires[85] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9896 ) ) ;
+cby_1__1_ cby_10__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9897 } ) ,
+ .chany_bottom_in ( sb_1__1__108_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__109_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_118_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__118_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__118_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__118_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9898 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9899 ) ,
+ .Test_en_W_in ( Test_enWires[262] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9900 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9901 ) ,
+ .Test_en_E_out ( Test_enWires[263] ) , .pReset_S_in ( pResetWires[542] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9902 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9903 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9904 ) ,
+ .Reset_W_in ( ResetWires[262] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9905 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9906 ) ,
+ .Reset_E_out ( ResetWires[263] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[398] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[399] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9907 ) ,
+ .prog_clk_2_N_in ( p3201 ) , .prog_clk_2_S_in ( p1735 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9908 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9909 ) ,
+ .prog_clk_3_S_in ( p1871 ) , .prog_clk_3_N_in ( p3162 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9910 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_2_N_in ( p3078 ) ,
+ .clk_2_S_in ( p2920 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p2988 ) ,
+ .clk_3_N_in ( p1274 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9915 ) ) ;
+cby_1__1_ cby_10__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9916 } ) ,
+ .chany_bottom_in ( sb_1__1__109_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_119_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__119_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__119_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__119_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9917 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9918 ) ,
+ .Test_en_W_in ( Test_enWires[284] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9919 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9920 ) ,
+ .Test_en_E_out ( Test_enWires[285] ) , .pReset_S_in ( pResetWires[591] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9921 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9922 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9923 ) ,
+ .Reset_W_in ( ResetWires[284] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9924 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9925 ) ,
+ .Reset_E_out ( ResetWires[285] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[401] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[402] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p1897 ) ,
+ .prog_clk_2_S_in ( p2037 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9926 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9927 ) ,
+ .prog_clk_3_S_in ( p2122 ) , .prog_clk_3_N_in ( p2271 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9928 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_2_N_in ( p2364 ) ,
+ .clk_2_S_in ( p2926 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p2994 ) ,
+ .clk_3_N_in ( p1631 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9933 ) ) ;
+cby_1__1_ cby_11__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9934 } ) ,
+ .chany_bottom_in ( sb_1__0__10_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__110_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_120_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__120_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__120_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__120_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9935 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9936 ) ,
+ .Test_en_W_in ( Test_enWires[44] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9937 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9938 ) ,
+ .Test_en_E_out ( Test_enWires[45] ) , .pReset_S_in ( pResetWires[57] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9939 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9940 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9941 ) ,
+ .Reset_W_in ( ResetWires[44] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9942 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9943 ) ,
+ .Reset_E_out ( ResetWires[45] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[406] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[407] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9944 ) ,
+ .prog_clk_2_N_in ( p2153 ) , .prog_clk_2_S_in ( p1639 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9945 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9946 ) ,
+ .prog_clk_3_S_in ( p1842 ) , .prog_clk_3_N_in ( p2718 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9947 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_2_N_in ( p2841 ) ,
+ .clk_2_S_in ( p608 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p1002 ) ,
+ .clk_3_N_in ( p218 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9952 ) ) ;
+cby_1__1_ cby_11__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9953 } ) ,
+ .chany_bottom_in ( sb_1__1__110_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__111_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_121_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__121_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__121_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__121_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9954 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9955 ) ,
+ .Test_en_W_in ( Test_enWires[66] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9956 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9957 ) ,
+ .Test_en_E_out ( Test_enWires[67] ) , .pReset_S_in ( pResetWires[105] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9958 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9959 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9960 ) ,
+ .Reset_W_in ( ResetWires[66] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9961 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9962 ) ,
+ .Reset_E_out ( ResetWires[67] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[409] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[410] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9963 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[115] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9964 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[116] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9965 ) ,
+ .prog_clk_3_S_in ( p1414 ) , .prog_clk_3_N_in ( p810 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9966 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9967 ) ,
+ .clk_2_N_in ( clk_2_wires[115] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9968 ) ,
+ .clk_2_S_out ( clk_2_wires[116] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p1414 ) ,
+ .clk_3_N_in ( p33 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9971 ) ) ;
+cby_1__1_ cby_11__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9972 } ) ,
+ .chany_bottom_in ( sb_1__1__111_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__112_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_122_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__122_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__122_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__122_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9973 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9974 ) ,
+ .Test_en_W_in ( Test_enWires[88] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9975 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9976 ) ,
+ .Test_en_E_out ( Test_enWires[89] ) , .pReset_S_in ( pResetWires[154] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9977 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9978 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9979 ) ,
+ .Reset_W_in ( ResetWires[88] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9980 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9981 ) ,
+ .Reset_E_out ( ResetWires[89] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[412] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[413] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9982 ) ,
+ .prog_clk_2_N_in ( p2638 ) , .prog_clk_2_S_in ( p2935 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9983 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9984 ) ,
+ .prog_clk_3_S_in ( p3001 ) , .prog_clk_3_N_in ( p2904 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9985 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_2_N_in ( p2976 ) ,
+ .clk_2_S_in ( p3163 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p3219 ) ,
+ .clk_3_N_in ( p16 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9990 ) ) ;
+cby_1__1_ cby_11__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9991 } ) ,
+ .chany_bottom_in ( sb_1__1__112_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__113_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_123_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__123_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__123_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__123_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9992 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9993 ) ,
+ .Test_en_W_in ( Test_enWires[110] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9994 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9995 ) ,
+ .Test_en_E_out ( Test_enWires[111] ) , .pReset_S_in ( pResetWires[203] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9996 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9997 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9998 ) ,
+ .Reset_W_in ( ResetWires[110] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9999 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10000 ) ,
+ .Reset_E_out ( ResetWires[111] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[415] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[416] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10001 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[122] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10002 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[123] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10003 ) ,
+ .prog_clk_3_S_in ( p1510 ) , .prog_clk_3_N_in ( p786 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10004 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10005 ) ,
+ .clk_2_N_in ( clk_2_wires[122] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10006 ) ,
+ .clk_2_S_out ( clk_2_wires[123] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1510 ) ,
+ .clk_3_N_in ( p291 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10009 ) ) ;
+cby_1__1_ cby_11__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10010 } ) ,
+ .chany_bottom_in ( sb_1__1__113_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__114_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_124_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__124_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__124_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__124_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10011 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10012 ) ,
+ .Test_en_W_in ( Test_enWires[132] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10013 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10014 ) ,
+ .Test_en_E_out ( Test_enWires[133] ) , .pReset_S_in ( pResetWires[252] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10015 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10016 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10017 ) ,
+ .Reset_W_in ( ResetWires[132] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10018 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10019 ) ,
+ .Reset_E_out ( ResetWires[133] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[418] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[419] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10020 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10021 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[120] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10022 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1661 ) ,
+ .prog_clk_3_N_in ( p535 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10023 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10024 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10025 ) ,
+ .clk_2_S_in ( clk_2_wires[120] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10026 ) ,
+ .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1661 ) ,
+ .clk_3_N_in ( p1064 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10028 ) ) ;
+cby_1__1_ cby_11__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10029 } ) ,
+ .chany_bottom_in ( sb_1__1__114_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__115_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_125_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__125_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__125_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__125_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10030 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10031 ) ,
+ .Test_en_W_in ( Test_enWires[154] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10032 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10033 ) ,
+ .Test_en_E_out ( Test_enWires[155] ) , .pReset_S_in ( pResetWires[301] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10034 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10035 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10036 ) ,
+ .Reset_W_in ( ResetWires[154] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10037 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10038 ) ,
+ .Reset_E_out ( ResetWires[155] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[421] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[422] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10039 ) ,
+ .prog_clk_2_N_in ( p3098 ) , .prog_clk_2_S_in ( p2580 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10040 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10041 ) ,
+ .prog_clk_3_S_in ( p2615 ) , .prog_clk_3_N_in ( p3019 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10042 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_2_N_in ( p2464 ) ,
+ .clk_2_S_in ( p2770 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p2786 ) ,
+ .clk_3_N_in ( p917 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10047 ) ) ;
+cby_1__1_ cby_11__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10048 } ) ,
+ .chany_bottom_in ( sb_1__1__115_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__116_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_126_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__126_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__126_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__126_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10049 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10050 ) ,
+ .Test_en_W_in ( Test_enWires[176] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10051 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10052 ) ,
+ .Test_en_E_out ( Test_enWires[177] ) , .pReset_S_in ( pResetWires[350] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10053 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10054 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10055 ) ,
+ .Reset_W_in ( ResetWires[176] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10056 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10057 ) ,
+ .Reset_E_out ( ResetWires[177] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[424] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[425] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10058 ) ,
+ .prog_clk_2_N_in ( p3403 ) , .prog_clk_2_S_in ( p2350 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10059 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10060 ) ,
+ .prog_clk_3_S_in ( p2489 ) , .prog_clk_3_N_in ( p3375 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10061 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_2_N_in ( p2354 ) ,
+ .clk_2_S_in ( p2578 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p2698 ) ,
+ .clk_3_N_in ( p221 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10066 ) ) ;
+cby_1__1_ cby_11__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10067 } ) ,
+ .chany_bottom_in ( sb_1__1__116_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__117_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_127_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__127_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__127_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__127_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10068 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10069 ) ,
+ .Test_en_W_in ( Test_enWires[198] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10070 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10071 ) ,
+ .Test_en_E_out ( Test_enWires[199] ) , .pReset_S_in ( pResetWires[399] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10072 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10073 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10074 ) ,
+ .Reset_W_in ( ResetWires[198] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10075 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10076 ) ,
+ .Reset_E_out ( ResetWires[199] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[427] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[428] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10077 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[129] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10078 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[130] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10079 ) ,
+ .prog_clk_3_S_in ( p1927 ) , .prog_clk_3_N_in ( p1129 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10080 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10081 ) ,
+ .clk_2_N_in ( clk_2_wires[129] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10082 ) ,
+ .clk_2_S_out ( clk_2_wires[130] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p1927 ) ,
+ .clk_3_N_in ( p273 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10085 ) ) ;
+cby_1__1_ cby_11__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10086 } ) ,
+ .chany_bottom_in ( sb_1__1__117_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__118_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_128_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__128_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__128_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__128_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10087 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10088 ) ,
+ .Test_en_W_in ( Test_enWires[220] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10089 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10090 ) ,
+ .Test_en_E_out ( Test_enWires[221] ) , .pReset_S_in ( pResetWires[448] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10091 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10092 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10093 ) ,
+ .Reset_W_in ( ResetWires[220] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10094 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10095 ) ,
+ .Reset_E_out ( ResetWires[221] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[430] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[431] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10096 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10097 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[127] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10098 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1539 ) ,
+ .prog_clk_3_N_in ( p741 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10099 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10100 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10101 ) ,
+ .clk_2_S_in ( clk_2_wires[127] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10102 ) ,
+ .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1539 ) ,
+ .clk_3_N_in ( p389 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10104 ) ) ;
+cby_1__1_ cby_11__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10105 } ) ,
+ .chany_bottom_in ( sb_1__1__118_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__119_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_129_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__129_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__129_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__129_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10106 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10107 ) ,
+ .Test_en_W_in ( Test_enWires[242] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10108 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10109 ) ,
+ .Test_en_E_out ( Test_enWires[243] ) , .pReset_S_in ( pResetWires[497] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10110 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10111 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10112 ) ,
+ .Reset_W_in ( ResetWires[242] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10113 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10114 ) ,
+ .Reset_E_out ( ResetWires[243] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[433] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[434] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10115 ) ,
+ .prog_clk_2_N_in ( p2852 ) , .prog_clk_2_S_in ( p3173 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10116 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10117 ) ,
+ .prog_clk_3_S_in ( p3194 ) , .prog_clk_3_N_in ( p2763 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10118 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_2_N_in ( p2353 ) ,
+ .clk_2_S_in ( p2573 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p2681 ) ,
+ .clk_3_N_in ( p562 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10123 ) ) ;
+cby_1__1_ cby_11__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10124 } ) ,
+ .chany_bottom_in ( sb_1__1__119_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__120_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_130_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__130_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__130_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__130_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10125 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10126 ) ,
+ .Test_en_W_in ( Test_enWires[264] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10127 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10128 ) ,
+ .Test_en_E_out ( Test_enWires[265] ) , .pReset_S_in ( pResetWires[546] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10129 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10130 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10131 ) ,
+ .Reset_W_in ( ResetWires[264] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10132 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10133 ) ,
+ .Reset_E_out ( ResetWires[265] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[436] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[437] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10134 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10135 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[134] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10136 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1923 ) ,
+ .prog_clk_3_N_in ( p843 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10137 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10138 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10139 ) ,
+ .clk_2_S_in ( clk_2_wires[134] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10140 ) ,
+ .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1923 ) ,
+ .clk_3_N_in ( p449 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10142 ) ) ;
+cby_1__1_ cby_11__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10143 } ) ,
+ .chany_bottom_in ( sb_1__1__120_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_131_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__131_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__131_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__131_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10144 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10145 ) ,
+ .Test_en_W_in ( Test_enWires[286] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10146 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10147 ) ,
+ .Test_en_E_out ( Test_enWires[287] ) , .pReset_S_in ( pResetWires[595] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10148 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10149 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10150 ) ,
+ .Reset_W_in ( ResetWires[286] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10151 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10152 ) ,
+ .Reset_E_out ( ResetWires[287] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[439] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[440] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p2140 ) ,
+ .prog_clk_2_S_in ( p2884 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10153 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10154 ) ,
+ .prog_clk_3_S_in ( p2949 ) , .prog_clk_3_N_in ( p2557 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10155 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_2_N_in ( p2686 ) ,
+ .clk_2_S_in ( p1699 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p1931 ) ,
+ .clk_3_N_in ( p1968 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10160 ) ) ;
+cby_2__1_ cby_12__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10161 } ) ,
+ .chany_bottom_in ( sb_12__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_132_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__0_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[60] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[444] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[445] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10162 ) ) ;
+cby_2__1_ cby_12__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10163 } ) ,
+ .chany_bottom_in ( sb_12__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_133_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__1_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[109] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[447] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[448] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10164 ) ) ;
+cby_2__1_ cby_12__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10165 } ) ,
+ .chany_bottom_in ( sb_12__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_134_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__2_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[158] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[450] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[451] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10166 ) ) ;
+cby_2__1_ cby_12__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10167 } ) ,
+ .chany_bottom_in ( sb_12__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_135_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__3_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[207] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[453] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[454] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10168 ) ) ;
+cby_2__1_ cby_12__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10169 } ) ,
+ .chany_bottom_in ( sb_12__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_136_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__4_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[256] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[456] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[457] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10170 ) ) ;
+cby_2__1_ cby_12__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10171 } ) ,
+ .chany_bottom_in ( sb_12__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_137_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__5_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[305] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[459] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[460] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10172 ) ) ;
+cby_2__1_ cby_12__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10173 } ) ,
+ .chany_bottom_in ( sb_12__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_138_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__6_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[354] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[462] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[463] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10174 ) ) ;
+cby_2__1_ cby_12__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10175 } ) ,
+ .chany_bottom_in ( sb_12__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_139_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__7_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[403] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[465] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[466] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10176 ) ) ;
+cby_2__1_ cby_12__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10177 } ) ,
+ .chany_bottom_in ( sb_12__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_140_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__8_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[452] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[468] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[469] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10178 ) ) ;
+cby_2__1_ cby_12__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10179 } ) ,
+ .chany_bottom_in ( sb_12__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_141_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__9_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[501] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[471] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[472] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10180 ) ) ;
+cby_2__1_ cby_12__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10181 } ) ,
+ .chany_bottom_in ( sb_12__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_142_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__10_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[550] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[474] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[475] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10182 ) ) ;
+cby_2__1_ cby_12__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10183 } ) ,
+ .chany_bottom_in ( sb_12__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_12__12__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_143_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__11_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[599] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[477] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[478] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[480] ) ) ;
+endmodule
+
+
+module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 ,
+ vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i ,
+ wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in ,
+ la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ ,
+ analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ ,
+ analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ ,
+ analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ ,
+ analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ ,
+ analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ ,
+ analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ ,
+ analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ ,
+ analog_io_9_ , user_clock2 ) ;
+inout vdda1 ;
+inout vdda2 ;
+inout vssa1 ;
+inout vssa2 ;
+inout vccd1 ;
+inout vccd2 ;
+inout vssd1 ;
+inout vssd2 ;
+input wb_clk_i ;
+input wb_rst_i ;
+input wbs_stb_i ;
+input wbs_cyc_i ;
+input wbs_we_i ;
+input [3:0] wbs_sel_i ;
+input [31:0] wbs_dat_i ;
+input [31:0] wbs_adr_i ;
+output wbs_ack_o ;
+output [31:0] wbs_dat_o ;
+input [127:0] la_data_in ;
+output [127:0] la_data_out ;
+input [127:0] la_oen ;
+input [37:0] io_in ;
+output [37:0] io_out ;
+output [37:0] io_oeb ;
+inout analog_io_0_ ;
+inout analog_io_10_ ;
+inout analog_io_11_ ;
+inout analog_io_12_ ;
+inout analog_io_13_ ;
+inout analog_io_14_ ;
+inout analog_io_15_ ;
+inout analog_io_16_ ;
+inout analog_io_17_ ;
+inout analog_io_18_ ;
+inout analog_io_19_ ;
+inout analog_io_1_ ;
+inout analog_io_20_ ;
+inout analog_io_21_ ;
+inout analog_io_22_ ;
+inout analog_io_23_ ;
+inout analog_io_24_ ;
+inout analog_io_25_ ;
+inout analog_io_26_ ;
+inout analog_io_27_ ;
+inout analog_io_28_ ;
+inout analog_io_29_ ;
+inout analog_io_2_ ;
+inout analog_io_30_ ;
+inout analog_io_3_ ;
+inout analog_io_4_ ;
+inout analog_io_5_ ;
+inout analog_io_6_ ;
+inout analog_io_7_ ;
+inout analog_io_8_ ;
+inout analog_io_9_ ;
+input user_clock2 ;
+
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+wire ccff_head ;
+wire sc_tail ;
+wire pReset ;
+wire Reset ;
+wire IO_ISOL_N ;
+wire Test_en ;
+wire prog_clk ;
+wire clk ;
+wire ccff_tail ;
+wire sc_head ;
+wire wb_la_switch ;
+
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ;
+assign ccff_head = io_in[12] ;
+assign sc_tail = io_out[11] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ;
+assign pReset = io_in[3] ;
+assign Reset = io_in[2] ;
+assign IO_ISOL_N = io_in[1] ;
+assign Test_en = io_in[0] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = la_data_out[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = la_data_out[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[84] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[83] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[82] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[81] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[80] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[79] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[78] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[77] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[76] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[75] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[74] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[73] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[72] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[71] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[70] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[69] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[68] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[67] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[66] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[65] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[64] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[63] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[62] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[61] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[60] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[59] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[58] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[57] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[56] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[55] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[54] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[53] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[52] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[51] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[50] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[49] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[48] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[47] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[46] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[45] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[44] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[43] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[42] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[41] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[40] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[39] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[38] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[37] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[36] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[26] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[25] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[12] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[11] ;
+assign prog_clk = io_in[37] ;
+assign clk = io_in[36] ;
+assign ccff_tail = io_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ;
+assign sc_head = io_in[26] ;
+assign wb_la_switch = io_in[25] ;
+
+sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) ,
+ .Y ( wb_la_switch_b ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[0] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[116] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[1] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[115] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[2] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[114] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[3] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[113] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[4] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[112] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[5] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[111] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[6] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[110] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[7] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[109] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[8] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[108] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[9] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[107] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[10] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[106] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[11] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[105] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[12] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[104] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[13] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[103] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[14] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[102] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[15] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[101] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[16] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[100] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[17] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[99] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[18] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[98] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[19] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[97] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[20] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[96] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[21] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[95] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[22] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[94] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[23] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[93] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[24] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[92] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[25] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[91] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[26] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[90] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[27] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[89] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[28] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[88] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[29] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[87] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[30] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[86] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[31] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) ,
+ .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) ,
+ .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) ,
+ .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) ,
+ .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) ,
+ .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) ,
+ .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) ,
+ .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) ,
+ .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) ,
+ .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) ,
+ .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) ,
+ .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) ,
+ .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) ,
+ .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) ,
+ .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) ,
+ .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) ,
+ .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) ,
+ .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) ,
+ .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) ,
+ .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) ,
+ .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) ,
+ .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) ,
+ .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) ,
+ .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) ,
+ .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) ,
+ .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) ,
+ .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) ,
+ .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) ,
+ .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) ,
+ .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) ,
+ .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) ,
+ .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) ,
+ .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) ,
+ .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) ,
+ .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) ,
+ .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) ,
+ .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) ,
+ .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) ,
+ .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) ,
+ .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) ,
+ .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) ,
+ .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) ,
+ .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) ,
+ .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) ,
+ .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) ,
+ .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) ,
+ .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) ,
+ .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) ,
+ .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) ,
+ .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) ,
+ .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) ,
+ .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) ,
+ .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) ,
+ .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) ,
+ .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) ,
+ .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) ,
+ .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) ,
+ .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) ,
+ .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) ,
+ .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) ,
+ .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) ,
+ .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) ,
+ .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) ,
+ .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) ,
+ .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) ,
+ .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) ,
+ .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) ,
+ .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) ,
+ .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) ,
+ .A1 ( wbs_we_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) ,
+ .A1 ( wbs_stb_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) ,
+ .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_ack_o ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[13] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) ,
+ .A1 ( wb_rst_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) ,
+ .A1 ( wb_clk_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ;
+fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) ,
+ .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) ,
+ .Reset ( io_in[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] ,
+ io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] ,
+ io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] ,
+ io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] ,
+ la_data_in[127] , la_data_in[126] , la_data_in[125] ,
+ la_data_in[124] , la_data_in[123] , la_data_in[122] ,
+ la_data_in[121] , la_data_in[120] , la_data_in[119] ,
+ la_data_in[118] , la_data_in[117] , la_data_in[116] ,
+ la_data_in[115] , la_data_in[114] , la_data_in[113] ,
+ la_data_in[112] , la_data_in[111] , la_data_in[110] ,
+ la_data_in[109] , la_data_in[108] , la_data_in[107] ,
+ la_data_in[106] , la_data_in[105] , la_data_in[104] ,
+ la_data_in[103] , la_data_in[102] , la_data_in[101] ,
+ la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] ,
+ la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] ,
+ la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] ,
+ la_data_in[88] , la_data_in[87] , la_data_in[86] , la_data_in[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[13] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] ,
+ io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] ,
+ io_in[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] ,
+ io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] ,
+ io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] ,
+ io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] ,
+ io_out[5] , io_out[4] , la_data_out[127] , la_data_out[126] ,
+ la_data_out[125] , la_data_out[124] , la_data_out[123] ,
+ la_data_out[122] , la_data_out[121] , la_data_out[120] ,
+ la_data_out[119] , la_data_out[118] , la_data_out[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[84] ,
+ la_data_out[83] , la_data_out[82] , la_data_out[81] ,
+ la_data_out[80] , la_data_out[79] , la_data_out[78] ,
+ la_data_out[77] , la_data_out[76] , la_data_out[75] ,
+ la_data_out[74] , la_data_out[73] , la_data_out[72] ,
+ la_data_out[71] , la_data_out[70] , la_data_out[69] ,
+ la_data_out[68] , la_data_out[67] , la_data_out[66] ,
+ la_data_out[65] , la_data_out[64] , la_data_out[63] ,
+ la_data_out[62] , la_data_out[61] , la_data_out[60] ,
+ la_data_out[59] , la_data_out[58] , la_data_out[57] ,
+ la_data_out[56] , la_data_out[55] , la_data_out[54] ,
+ la_data_out[53] , la_data_out[52] , la_data_out[51] ,
+ la_data_out[50] , la_data_out[49] , la_data_out[48] ,
+ la_data_out[47] , la_data_out[46] , la_data_out[45] ,
+ la_data_out[44] , la_data_out[43] , la_data_out[42] ,
+ la_data_out[41] , la_data_out[40] , la_data_out[39] ,
+ la_data_out[38] , la_data_out[37] , la_data_out[36] ,
+ la_data_out[35] , la_data_out[34] , la_data_out[33] ,
+ la_data_out[32] , la_data_out[31] , la_data_out[30] ,
+ la_data_out[29] , la_data_out[28] , la_data_out[27] ,
+ la_data_out[26] , la_data_out[25] , la_data_out[24] ,
+ la_data_out[23] , la_data_out[22] , la_data_out[21] ,
+ la_data_out[20] , la_data_out[19] , la_data_out[18] ,
+ la_data_out[17] , la_data_out[16] , la_data_out[15] ,
+ la_data_out[14] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ,
+ la_data_out[12] , la_data_out[11] , io_out[34] , io_out[33] ,
+ io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] ,
+ io_out[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] ,
+ io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] ,
+ io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] ,
+ io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] ,
+ io_oeb[5] , io_oeb[4] , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] ,
+ io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] ,
+ io_oeb[27] } ) ,
+ .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) ,
+ .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) ,
+ .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , .p0 ( optlc_net_20 ) ,
+ .p1 ( optlc_net_21 ) , .p2 ( optlc_net_22 ) , .p3 ( optlc_net_23 ) ,
+ .p4 ( optlc_net_24 ) , .p5 ( optlc_net_25 ) , .p6 ( optlc_net_26 ) ,
+ .p7 ( optlc_net_27 ) , .p8 ( optlc_net_28 ) , .p9 ( optlc_net_29 ) ,
+ .p10 ( optlc_net_30 ) , .p11 ( optlc_net_31 ) , .p12 ( optlc_net_32 ) ,
+ .p13 ( optlc_net_33 ) , .p14 ( optlc_net_34 ) , .p15 ( optlc_net_35 ) ,
+ .p16 ( optlc_net_36 ) , .p17 ( optlc_net_37 ) , .p18 ( optlc_net_38 ) ,
+ .p19 ( optlc_net_39 ) , .p20 ( optlc_net_40 ) , .p21 ( optlc_net_41 ) ,
+ .p22 ( optlc_net_42 ) , .p23 ( optlc_net_43 ) , .p24 ( optlc_net_44 ) ,
+ .p25 ( optlc_net_45 ) , .p26 ( optlc_net_46 ) , .p27 ( optlc_net_47 ) ,
+ .p28 ( optlc_net_48 ) , .p29 ( optlc_net_49 ) , .p30 ( optlc_net_50 ) ,
+ .p31 ( optlc_net_51 ) , .p32 ( optlc_net_52 ) , .p33 ( optlc_net_53 ) ,
+ .p34 ( optlc_net_54 ) , .p35 ( optlc_net_55 ) , .p36 ( optlc_net_56 ) ,
+ .p37 ( optlc_net_57 ) , .p38 ( optlc_net_58 ) , .p39 ( optlc_net_59 ) ,
+ .p40 ( optlc_net_60 ) , .p41 ( optlc_net_61 ) , .p42 ( optlc_net_62 ) ,
+ .p43 ( optlc_net_63 ) , .p44 ( optlc_net_64 ) , .p45 ( optlc_net_65 ) ,
+ .p46 ( optlc_net_66 ) , .p47 ( optlc_net_67 ) , .p48 ( optlc_net_68 ) ,
+ .p49 ( optlc_net_69 ) , .p50 ( optlc_net_70 ) , .p51 ( optlc_net_71 ) ,
+ .p52 ( optlc_net_72 ) , .p53 ( optlc_net_73 ) , .p54 ( optlc_net_74 ) ,
+ .p55 ( optlc_net_75 ) , .p56 ( optlc_net_76 ) , .p57 ( optlc_net_77 ) ,
+ .p58 ( optlc_net_78 ) , .p59 ( optlc_net_79 ) , .p60 ( optlc_net_80 ) ,
+ .p61 ( optlc_net_81 ) , .p62 ( optlc_net_82 ) , .p63 ( optlc_net_83 ) ,
+ .p64 ( optlc_net_84 ) , .p65 ( optlc_net_85 ) , .p66 ( optlc_net_86 ) ,
+ .p67 ( optlc_net_87 ) , .p68 ( optlc_net_88 ) , .p69 ( optlc_net_89 ) ,
+ .p70 ( optlc_net_90 ) , .p71 ( optlc_net_91 ) , .p72 ( optlc_net_92 ) ,
+ .p73 ( optlc_net_93 ) , .p74 ( optlc_net_94 ) , .p75 ( optlc_net_95 ) ,
+ .p76 ( optlc_net_96 ) , .p77 ( optlc_net_97 ) , .p78 ( optlc_net_98 ) ,
+ .p79 ( optlc_net_99 ) , .p80 ( optlc_net_100 ) , .p81 ( optlc_net_101 ) ,
+ .p82 ( optlc_net_102 ) , .p83 ( optlc_net_103 ) , .p84 ( optlc_net_104 ) ,
+ .p85 ( optlc_net_105 ) , .p86 ( optlc_net_106 ) , .p87 ( optlc_net_107 ) ,
+ .p88 ( optlc_net_108 ) , .p89 ( optlc_net_109 ) , .p90 ( optlc_net_110 ) ,
+ .p91 ( optlc_net_111 ) , .p92 ( optlc_net_112 ) , .p93 ( optlc_net_113 ) ,
+ .p94 ( optlc_net_114 ) , .p95 ( optlc_net_115 ) , .p96 ( optlc_net_116 ) ,
+ .p97 ( optlc_net_117 ) , .p98 ( optlc_net_118 ) , .p99 ( optlc_net_119 ) ,
+ .p100 ( optlc_net_120 ) , .p101 ( optlc_net_121 ) ,
+ .p102 ( optlc_net_122 ) , .p103 ( optlc_net_123 ) ,
+ .p104 ( optlc_net_124 ) , .p105 ( optlc_net_125 ) ,
+ .p106 ( optlc_net_126 ) , .p107 ( optlc_net_127 ) ,
+ .p108 ( optlc_net_128 ) , .p109 ( optlc_net_129 ) ,
+ .p110 ( optlc_net_130 ) , .p111 ( optlc_net_131 ) ,
+ .p112 ( optlc_net_132 ) , .p113 ( optlc_net_133 ) ,
+ .p114 ( optlc_net_134 ) , .p115 ( optlc_net_135 ) ,
+ .p116 ( optlc_net_136 ) , .p117 ( optlc_net_137 ) ,
+ .p118 ( optlc_net_138 ) , .p119 ( optlc_net_139 ) ,
+ .p120 ( optlc_net_140 ) , .p121 ( optlc_net_141 ) ,
+ .p122 ( optlc_net_142 ) , .p123 ( optlc_net_143 ) ,
+ .p124 ( optlc_net_144 ) , .p125 ( optlc_net_145 ) ,
+ .p126 ( optlc_net_146 ) , .p127 ( optlc_net_147 ) ,
+ .p128 ( optlc_net_148 ) , .p129 ( optlc_net_149 ) ,
+ .p130 ( optlc_net_150 ) , .p131 ( optlc_net_151 ) ,
+ .p132 ( optlc_net_152 ) , .p133 ( optlc_net_153 ) ,
+ .p134 ( optlc_net_154 ) , .p135 ( optlc_net_155 ) ,
+ .p136 ( optlc_net_156 ) , .p137 ( optlc_net_157 ) ,
+ .p138 ( optlc_net_158 ) , .p139 ( optlc_net_159 ) ,
+ .p140 ( optlc_net_160 ) , .p141 ( optlc_net_161 ) ,
+ .p142 ( optlc_net_162 ) , .p143 ( optlc_net_163 ) ,
+ .p144 ( optlc_net_164 ) , .p145 ( optlc_net_165 ) ,
+ .p146 ( optlc_net_166 ) , .p147 ( optlc_net_167 ) ,
+ .p148 ( optlc_net_168 ) , .p149 ( optlc_net_169 ) ,
+ .p150 ( optlc_net_170 ) , .p151 ( optlc_net_171 ) ,
+ .p152 ( optlc_net_172 ) , .p153 ( optlc_net_173 ) ,
+ .p154 ( optlc_net_174 ) , .p155 ( optlc_net_175 ) ,
+ .p156 ( optlc_net_176 ) , .p157 ( optlc_net_177 ) ,
+ .p158 ( optlc_net_178 ) , .p159 ( optlc_net_179 ) ,
+ .p160 ( optlc_net_180 ) , .p161 ( optlc_net_181 ) ,
+ .p162 ( optlc_net_182 ) , .p163 ( optlc_net_183 ) ,
+ .p164 ( optlc_net_184 ) , .p165 ( optlc_net_185 ) ,
+ .p166 ( optlc_net_186 ) , .p167 ( optlc_net_187 ) ,
+ .p168 ( optlc_net_188 ) , .p169 ( optlc_net_189 ) ,
+ .p170 ( optlc_net_190 ) , .p171 ( optlc_net_191 ) ,
+ .p172 ( optlc_net_192 ) , .p173 ( optlc_net_193 ) ,
+ .p174 ( optlc_net_194 ) , .p175 ( optlc_net_195 ) ,
+ .p176 ( optlc_net_196 ) , .p177 ( optlc_net_197 ) ,
+ .p178 ( optlc_net_198 ) , .p179 ( optlc_net_199 ) ,
+ .p180 ( optlc_net_200 ) , .p181 ( optlc_net_201 ) ,
+ .p182 ( optlc_net_202 ) , .p183 ( optlc_net_203 ) ,
+ .p184 ( optlc_net_204 ) , .p185 ( optlc_net_205 ) ,
+ .p186 ( optlc_net_206 ) , .p187 ( optlc_net_207 ) ,
+ .p188 ( optlc_net_208 ) , .p189 ( optlc_net_209 ) ,
+ .p190 ( optlc_net_210 ) , .p191 ( optlc_net_211 ) ,
+ .p192 ( optlc_net_212 ) , .p193 ( optlc_net_213 ) ,
+ .p194 ( optlc_net_214 ) , .p195 ( optlc_net_215 ) ,
+ .p196 ( optlc_net_216 ) , .p197 ( optlc_net_217 ) ,
+ .p198 ( optlc_net_218 ) , .p199 ( optlc_net_219 ) ,
+ .p200 ( optlc_net_220 ) , .p201 ( optlc_net_221 ) ,
+ .p202 ( optlc_net_222 ) , .p203 ( optlc_net_223 ) ,
+ .p204 ( optlc_net_224 ) , .p205 ( optlc_net_225 ) ,
+ .p206 ( optlc_net_226 ) , .p207 ( optlc_net_227 ) ,
+ .p208 ( optlc_net_228 ) , .p209 ( optlc_net_229 ) ,
+ .p210 ( optlc_net_230 ) , .p211 ( optlc_net_231 ) ,
+ .p212 ( optlc_net_232 ) , .p213 ( optlc_net_233 ) ,
+ .p214 ( optlc_net_234 ) , .p215 ( optlc_net_235 ) ,
+ .p216 ( optlc_net_236 ) , .p217 ( optlc_net_237 ) ,
+ .p218 ( optlc_net_238 ) , .p219 ( optlc_net_239 ) ,
+ .p220 ( optlc_net_240 ) , .p221 ( optlc_net_241 ) ,
+ .p222 ( optlc_net_242 ) , .p223 ( optlc_net_243 ) ,
+ .p224 ( optlc_net_244 ) , .p225 ( optlc_net_245 ) ,
+ .p226 ( optlc_net_246 ) , .p227 ( optlc_net_247 ) ,
+ .p228 ( optlc_net_248 ) , .p229 ( optlc_net_249 ) ,
+ .p230 ( optlc_net_250 ) , .p231 ( optlc_net_251 ) ,
+ .p232 ( optlc_net_252 ) , .p233 ( optlc_net_253 ) ,
+ .p234 ( optlc_net_254 ) , .p235 ( optlc_net_255 ) ,
+ .p236 ( optlc_net_256 ) , .p237 ( optlc_net_257 ) ,
+ .p238 ( optlc_net_258 ) , .p239 ( optlc_net_259 ) ,
+ .p240 ( optlc_net_260 ) , .p241 ( optlc_net_261 ) ,
+ .p242 ( optlc_net_262 ) , .p243 ( optlc_net_263 ) ,
+ .p244 ( optlc_net_264 ) , .p245 ( optlc_net_265 ) ,
+ .p246 ( optlc_net_266 ) , .p247 ( optlc_net_267 ) ,
+ .p248 ( optlc_net_268 ) , .p249 ( optlc_net_269 ) ,
+ .p250 ( optlc_net_270 ) , .p251 ( optlc_net_271 ) ,
+ .p252 ( optlc_net_272 ) , .p253 ( optlc_net_273 ) ,
+ .p254 ( optlc_net_274 ) , .p255 ( optlc_net_275 ) ,
+ .p256 ( optlc_net_276 ) , .p257 ( optlc_net_277 ) ,
+ .p258 ( optlc_net_278 ) , .p259 ( optlc_net_279 ) ,
+ .p260 ( optlc_net_280 ) , .p261 ( optlc_net_281 ) ,
+ .p262 ( optlc_net_282 ) , .p263 ( optlc_net_283 ) ,
+ .p264 ( optlc_net_284 ) , .p265 ( optlc_net_285 ) ,
+ .p266 ( optlc_net_286 ) , .p267 ( optlc_net_287 ) ,
+ .p268 ( optlc_net_288 ) , .p269 ( optlc_net_289 ) ,
+ .p270 ( optlc_net_290 ) , .p271 ( optlc_net_291 ) ,
+ .p272 ( optlc_net_292 ) , .p273 ( optlc_net_293 ) ,
+ .p274 ( optlc_net_294 ) , .p275 ( optlc_net_295 ) ,
+ .p276 ( optlc_net_296 ) , .p277 ( optlc_net_297 ) ,
+ .p278 ( optlc_net_298 ) , .p279 ( optlc_net_299 ) ,
+ .p280 ( optlc_net_300 ) , .p281 ( optlc_net_301 ) ,
+ .p282 ( optlc_net_302 ) , .p283 ( optlc_net_303 ) ,
+ .p284 ( optlc_net_304 ) , .p285 ( optlc_net_305 ) ,
+ .p286 ( optlc_net_306 ) , .p287 ( optlc_net_307 ) ,
+ .p288 ( optlc_net_308 ) , .p289 ( optlc_net_309 ) ,
+ .p290 ( optlc_net_310 ) , .p291 ( optlc_net_311 ) ,
+ .p292 ( optlc_net_312 ) , .p293 ( optlc_net_313 ) ,
+ .p294 ( optlc_net_314 ) , .p295 ( optlc_net_315 ) ,
+ .p296 ( optlc_net_316 ) , .p297 ( optlc_net_317 ) ,
+ .p298 ( optlc_net_318 ) , .p299 ( optlc_net_319 ) ,
+ .p300 ( optlc_net_320 ) , .p301 ( optlc_net_321 ) ,
+ .p302 ( optlc_net_322 ) , .p303 ( optlc_net_323 ) ,
+ .p304 ( optlc_net_324 ) , .p305 ( optlc_net_325 ) ,
+ .p306 ( optlc_net_326 ) , .p307 ( optlc_net_327 ) ,
+ .p308 ( optlc_net_328 ) , .p309 ( optlc_net_329 ) ,
+ .p310 ( optlc_net_330 ) , .p311 ( optlc_net_331 ) ,
+ .p312 ( optlc_net_332 ) , .p313 ( optlc_net_333 ) ,
+ .p314 ( optlc_net_334 ) , .p315 ( optlc_net_335 ) ,
+ .p316 ( optlc_net_336 ) , .p317 ( optlc_net_337 ) ,
+ .p318 ( optlc_net_338 ) , .p319 ( optlc_net_339 ) ,
+ .p320 ( optlc_net_340 ) , .p321 ( optlc_net_341 ) ,
+ .p322 ( optlc_net_342 ) , .p323 ( optlc_net_343 ) ,
+ .p324 ( optlc_net_344 ) , .p325 ( optlc_net_345 ) ,
+ .p326 ( optlc_net_346 ) , .p327 ( optlc_net_347 ) ,
+ .p328 ( optlc_net_348 ) , .p329 ( optlc_net_349 ) ,
+ .p330 ( optlc_net_350 ) , .p331 ( optlc_net_351 ) ,
+ .p332 ( optlc_net_352 ) , .p333 ( optlc_net_353 ) ,
+ .p334 ( optlc_net_354 ) , .p335 ( optlc_net_355 ) ,
+ .p336 ( optlc_net_356 ) , .p337 ( optlc_net_357 ) ,
+ .p338 ( optlc_net_358 ) , .p339 ( optlc_net_359 ) ,
+ .p340 ( optlc_net_360 ) , .p341 ( optlc_net_361 ) ,
+ .p342 ( optlc_net_362 ) , .p343 ( optlc_net_363 ) ,
+ .p344 ( optlc_net_364 ) , .p345 ( optlc_net_365 ) ,
+ .p346 ( optlc_net_366 ) , .p347 ( optlc_net_367 ) ,
+ .p348 ( optlc_net_368 ) , .p349 ( optlc_net_369 ) ,
+ .p350 ( optlc_net_370 ) , .p351 ( optlc_net_371 ) ,
+ .p352 ( optlc_net_372 ) , .p353 ( optlc_net_373 ) ,
+ .p354 ( optlc_net_374 ) , .p355 ( optlc_net_375 ) ,
+ .p356 ( optlc_net_376 ) , .p357 ( optlc_net_377 ) ,
+ .p358 ( optlc_net_378 ) , .p359 ( optlc_net_379 ) ,
+ .p360 ( optlc_net_380 ) , .p361 ( optlc_net_381 ) ,
+ .p362 ( optlc_net_382 ) , .p363 ( optlc_net_383 ) ,
+ .p364 ( optlc_net_384 ) , .p365 ( optlc_net_385 ) ,
+ .p366 ( optlc_net_386 ) , .p367 ( optlc_net_387 ) ,
+ .p368 ( optlc_net_388 ) , .p369 ( optlc_net_389 ) ,
+ .p370 ( optlc_net_390 ) , .p371 ( optlc_net_391 ) ,
+ .p372 ( optlc_net_392 ) , .p373 ( optlc_net_393 ) ,
+ .p374 ( optlc_net_394 ) , .p375 ( optlc_net_395 ) ,
+ .p376 ( optlc_net_396 ) , .p377 ( optlc_net_397 ) ,
+ .p378 ( optlc_net_398 ) , .p379 ( optlc_net_399 ) ,
+ .p380 ( optlc_net_400 ) , .p381 ( optlc_net_401 ) ,
+ .p382 ( optlc_net_402 ) , .p383 ( optlc_net_403 ) ,
+ .p384 ( optlc_net_404 ) , .p385 ( optlc_net_405 ) ,
+ .p386 ( optlc_net_406 ) , .p387 ( optlc_net_407 ) ,
+ .p388 ( optlc_net_408 ) , .p389 ( optlc_net_409 ) ,
+ .p390 ( optlc_net_410 ) , .p391 ( optlc_net_411 ) ,
+ .p392 ( optlc_net_412 ) , .p393 ( optlc_net_413 ) ,
+ .p394 ( optlc_net_414 ) , .p395 ( optlc_net_415 ) ,
+ .p396 ( optlc_net_416 ) , .p397 ( optlc_net_417 ) ,
+ .p398 ( optlc_net_418 ) , .p399 ( optlc_net_419 ) ,
+ .p400 ( optlc_net_420 ) , .p401 ( optlc_net_421 ) ,
+ .p402 ( optlc_net_422 ) , .p403 ( optlc_net_423 ) ,
+ .p404 ( optlc_net_424 ) , .p405 ( optlc_net_425 ) ,
+ .p406 ( optlc_net_426 ) , .p407 ( optlc_net_427 ) ,
+ .p408 ( optlc_net_428 ) , .p409 ( optlc_net_429 ) ,
+ .p410 ( optlc_net_430 ) , .p411 ( optlc_net_431 ) ,
+ .p412 ( optlc_net_432 ) , .p413 ( optlc_net_433 ) ,
+ .p414 ( optlc_net_434 ) , .p415 ( optlc_net_435 ) ,
+ .p416 ( optlc_net_436 ) , .p417 ( optlc_net_437 ) ,
+ .p418 ( optlc_net_438 ) , .p419 ( optlc_net_439 ) ,
+ .p420 ( optlc_net_440 ) , .p421 ( optlc_net_441 ) ,
+ .p422 ( optlc_net_442 ) , .p423 ( optlc_net_443 ) ,
+ .p424 ( optlc_net_444 ) , .p425 ( optlc_net_445 ) ,
+ .p426 ( optlc_net_446 ) , .p427 ( optlc_net_447 ) ,
+ .p428 ( optlc_net_448 ) , .p429 ( optlc_net_449 ) ,
+ .p430 ( optlc_net_450 ) , .p431 ( optlc_net_451 ) ,
+ .p432 ( optlc_net_452 ) , .p433 ( optlc_net_453 ) ,
+ .p434 ( optlc_net_454 ) , .p435 ( optlc_net_455 ) ,
+ .p436 ( optlc_net_456 ) , .p437 ( optlc_net_457 ) ,
+ .p438 ( optlc_net_458 ) , .p439 ( optlc_net_459 ) ,
+ .p440 ( optlc_net_460 ) , .p441 ( optlc_net_461 ) ,
+ .p442 ( optlc_net_462 ) , .p443 ( optlc_net_463 ) ,
+ .p444 ( optlc_net_464 ) , .p445 ( optlc_net_465 ) ,
+ .p446 ( optlc_net_466 ) , .p447 ( optlc_net_467 ) ,
+ .p448 ( optlc_net_468 ) , .p449 ( optlc_net_469 ) ,
+ .p450 ( optlc_net_470 ) , .p451 ( optlc_net_471 ) ,
+ .p452 ( optlc_net_472 ) , .p453 ( optlc_net_473 ) ,
+ .p454 ( optlc_net_474 ) , .p455 ( optlc_net_475 ) ,
+ .p456 ( optlc_net_476 ) , .p457 ( optlc_net_477 ) ,
+ .p458 ( optlc_net_478 ) , .p459 ( optlc_net_479 ) ,
+ .p460 ( optlc_net_480 ) , .p461 ( optlc_net_481 ) ,
+ .p462 ( optlc_net_482 ) , .p463 ( optlc_net_483 ) ,
+ .p464 ( optlc_net_484 ) , .p465 ( optlc_net_485 ) ,
+ .p466 ( optlc_net_486 ) , .p467 ( optlc_net_487 ) ,
+ .p468 ( optlc_net_488 ) , .p469 ( optlc_net_489 ) ,
+ .p470 ( optlc_net_490 ) , .p471 ( optlc_net_491 ) ,
+ .p472 ( optlc_net_492 ) , .p473 ( optlc_net_493 ) ,
+ .p474 ( optlc_net_494 ) , .p475 ( optlc_net_495 ) ,
+ .p476 ( optlc_net_496 ) , .p477 ( optlc_net_497 ) ,
+ .p478 ( optlc_net_498 ) , .p479 ( optlc_net_499 ) ,
+ .p480 ( optlc_net_500 ) , .p481 ( optlc_net_501 ) ,
+ .p482 ( optlc_net_502 ) , .p483 ( optlc_net_503 ) ,
+ .p484 ( optlc_net_504 ) , .p485 ( optlc_net_505 ) ,
+ .p486 ( optlc_net_506 ) , .p487 ( optlc_net_507 ) ,
+ .p488 ( optlc_net_508 ) , .p489 ( optlc_net_509 ) ,
+ .p490 ( optlc_net_510 ) , .p491 ( optlc_net_511 ) ,
+ .p492 ( optlc_net_512 ) , .p493 ( optlc_net_513 ) ,
+ .p494 ( optlc_net_514 ) , .p495 ( optlc_net_515 ) ,
+ .p496 ( optlc_net_516 ) , .p497 ( optlc_net_517 ) ,
+ .p498 ( optlc_net_518 ) , .p499 ( optlc_net_519 ) ,
+ .p500 ( optlc_net_520 ) , .p501 ( optlc_net_521 ) ,
+ .p502 ( optlc_net_522 ) , .p503 ( optlc_net_523 ) ,
+ .p504 ( optlc_net_524 ) , .p505 ( optlc_net_525 ) ,
+ .p506 ( optlc_net_526 ) , .p507 ( optlc_net_527 ) ,
+ .p508 ( optlc_net_528 ) , .p509 ( optlc_net_529 ) ,
+ .p510 ( optlc_net_530 ) , .p511 ( optlc_net_531 ) ,
+ .p512 ( optlc_net_532 ) , .p513 ( optlc_net_533 ) ,
+ .p514 ( optlc_net_534 ) , .p515 ( optlc_net_535 ) ,
+ .p516 ( optlc_net_536 ) , .p517 ( optlc_net_537 ) ,
+ .p518 ( optlc_net_538 ) , .p519 ( optlc_net_539 ) ,
+ .p520 ( optlc_net_540 ) , .p521 ( optlc_net_541 ) ,
+ .p522 ( optlc_net_542 ) , .p523 ( optlc_net_543 ) ,
+ .p524 ( optlc_net_544 ) , .p525 ( optlc_net_545 ) ,
+ .p526 ( optlc_net_546 ) , .p527 ( optlc_net_547 ) ,
+ .p528 ( optlc_net_548 ) , .p529 ( optlc_net_549 ) ,
+ .p530 ( optlc_net_550 ) , .p531 ( optlc_net_551 ) ,
+ .p532 ( optlc_net_552 ) , .p533 ( optlc_net_553 ) ,
+ .p534 ( optlc_net_554 ) , .p535 ( optlc_net_555 ) ,
+ .p536 ( optlc_net_556 ) , .p537 ( optlc_net_557 ) ,
+ .p538 ( optlc_net_558 ) , .p539 ( optlc_net_559 ) ,
+ .p540 ( optlc_net_560 ) , .p541 ( optlc_net_561 ) ,
+ .p542 ( optlc_net_562 ) , .p543 ( optlc_net_563 ) ,
+ .p544 ( optlc_net_564 ) , .p545 ( optlc_net_565 ) ,
+ .p546 ( optlc_net_566 ) , .p547 ( optlc_net_567 ) ,
+ .p548 ( optlc_net_568 ) , .p549 ( optlc_net_569 ) ,
+ .p550 ( optlc_net_570 ) , .p551 ( optlc_net_571 ) ,
+ .p552 ( optlc_net_572 ) , .p553 ( optlc_net_573 ) ,
+ .p554 ( optlc_net_574 ) , .p555 ( optlc_net_575 ) ,
+ .p556 ( optlc_net_576 ) , .p557 ( optlc_net_577 ) ,
+ .p558 ( optlc_net_578 ) , .p559 ( optlc_net_579 ) ,
+ .p560 ( optlc_net_580 ) , .p561 ( optlc_net_581 ) ,
+ .p562 ( optlc_net_582 ) , .p563 ( optlc_net_583 ) ,
+ .p564 ( optlc_net_584 ) , .p565 ( optlc_net_585 ) ,
+ .p566 ( optlc_net_586 ) , .p567 ( optlc_net_587 ) ,
+ .p568 ( optlc_net_588 ) , .p569 ( optlc_net_589 ) ,
+ .p570 ( optlc_net_590 ) , .p571 ( optlc_net_591 ) ,
+ .p572 ( optlc_net_592 ) , .p573 ( optlc_net_593 ) ,
+ .p574 ( optlc_net_594 ) , .p575 ( optlc_net_595 ) ,
+ .p576 ( optlc_net_596 ) , .p577 ( optlc_net_597 ) ,
+ .p578 ( optlc_net_598 ) , .p579 ( optlc_net_599 ) ,
+ .p580 ( optlc_net_600 ) , .p581 ( optlc_net_601 ) ,
+ .p582 ( optlc_net_602 ) , .p583 ( optlc_net_603 ) ,
+ .p584 ( optlc_net_604 ) , .p585 ( optlc_net_605 ) ,
+ .p586 ( optlc_net_606 ) , .p587 ( optlc_net_607 ) ,
+ .p588 ( optlc_net_608 ) , .p589 ( optlc_net_609 ) ,
+ .p590 ( optlc_net_610 ) , .p591 ( optlc_net_611 ) ,
+ .p592 ( optlc_net_612 ) , .p593 ( optlc_net_613 ) ,
+ .p594 ( optlc_net_614 ) , .p595 ( optlc_net_615 ) ,
+ .p596 ( optlc_net_616 ) , .p597 ( optlc_net_617 ) ,
+ .p598 ( optlc_net_618 ) , .p599 ( optlc_net_619 ) ,
+ .p600 ( optlc_net_620 ) , .p601 ( optlc_net_621 ) ,
+ .p602 ( optlc_net_622 ) , .p603 ( optlc_net_623 ) ,
+ .p604 ( optlc_net_624 ) , .p605 ( optlc_net_625 ) ,
+ .p606 ( optlc_net_626 ) , .p607 ( optlc_net_627 ) ,
+ .p608 ( optlc_net_628 ) , .p609 ( optlc_net_629 ) ,
+ .p610 ( optlc_net_630 ) , .p611 ( optlc_net_631 ) ,
+ .p612 ( optlc_net_632 ) , .p613 ( optlc_net_633 ) ,
+ .p614 ( optlc_net_634 ) , .p615 ( optlc_net_635 ) ,
+ .p616 ( optlc_net_636 ) , .p617 ( optlc_net_637 ) ,
+ .p618 ( optlc_net_638 ) , .p619 ( optlc_net_639 ) ,
+ .p620 ( optlc_net_640 ) , .p621 ( optlc_net_641 ) ,
+ .p622 ( optlc_net_642 ) , .p623 ( optlc_net_643 ) ,
+ .p624 ( optlc_net_644 ) , .p625 ( optlc_net_645 ) ,
+ .p626 ( optlc_net_646 ) , .p627 ( optlc_net_647 ) ,
+ .p628 ( optlc_net_648 ) , .p629 ( optlc_net_649 ) ,
+ .p630 ( optlc_net_650 ) , .p631 ( optlc_net_651 ) ,
+ .p632 ( optlc_net_652 ) , .p633 ( optlc_net_653 ) ,
+ .p634 ( optlc_net_654 ) , .p635 ( optlc_net_655 ) ,
+ .p636 ( optlc_net_656 ) , .p637 ( optlc_net_657 ) ,
+ .p638 ( optlc_net_658 ) , .p639 ( optlc_net_659 ) ,
+ .p640 ( optlc_net_660 ) , .p641 ( optlc_net_661 ) ,
+ .p642 ( optlc_net_662 ) , .p643 ( optlc_net_663 ) ,
+ .p644 ( optlc_net_664 ) , .p645 ( optlc_net_665 ) ,
+ .p646 ( optlc_net_666 ) , .p647 ( optlc_net_667 ) ,
+ .p648 ( optlc_net_668 ) , .p649 ( optlc_net_669 ) ,
+ .p650 ( optlc_net_670 ) , .p651 ( optlc_net_671 ) ,
+ .p652 ( optlc_net_672 ) , .p653 ( optlc_net_673 ) ,
+ .p654 ( optlc_net_674 ) , .p655 ( optlc_net_675 ) ,
+ .p656 ( optlc_net_676 ) , .p657 ( optlc_net_677 ) ,
+ .p658 ( optlc_net_678 ) , .p659 ( optlc_net_679 ) ,
+ .p660 ( optlc_net_680 ) , .p661 ( optlc_net_681 ) ,
+ .p662 ( optlc_net_682 ) , .p663 ( optlc_net_683 ) ,
+ .p664 ( optlc_net_684 ) , .p665 ( optlc_net_685 ) ,
+ .p666 ( optlc_net_686 ) , .p667 ( optlc_net_687 ) ,
+ .p668 ( optlc_net_688 ) , .p669 ( optlc_net_689 ) ,
+ .p670 ( optlc_net_690 ) , .p671 ( optlc_net_691 ) ,
+ .p672 ( optlc_net_692 ) , .p673 ( optlc_net_693 ) ,
+ .p674 ( optlc_net_694 ) , .p675 ( optlc_net_695 ) ,
+ .p676 ( optlc_net_696 ) , .p677 ( optlc_net_697 ) ,
+ .p678 ( optlc_net_698 ) , .p679 ( optlc_net_699 ) ,
+ .p680 ( optlc_net_700 ) , .p681 ( optlc_net_701 ) ,
+ .p682 ( optlc_net_702 ) , .p683 ( optlc_net_703 ) ,
+ .p684 ( optlc_net_704 ) , .p685 ( optlc_net_705 ) ,
+ .p686 ( optlc_net_706 ) , .p687 ( optlc_net_707 ) ,
+ .p688 ( optlc_net_708 ) , .p689 ( optlc_net_709 ) ,
+ .p690 ( optlc_net_710 ) , .p691 ( optlc_net_711 ) ,
+ .p692 ( optlc_net_712 ) , .p693 ( optlc_net_713 ) ,
+ .p694 ( optlc_net_714 ) , .p695 ( optlc_net_715 ) ,
+ .p696 ( optlc_net_716 ) , .p697 ( optlc_net_717 ) ,
+ .p698 ( optlc_net_718 ) , .p699 ( optlc_net_719 ) ,
+ .p700 ( optlc_net_720 ) , .p701 ( optlc_net_721 ) ,
+ .p702 ( optlc_net_722 ) , .p703 ( optlc_net_723 ) ,
+ .p704 ( optlc_net_724 ) , .p705 ( optlc_net_725 ) ,
+ .p706 ( optlc_net_726 ) , .p707 ( optlc_net_727 ) ,
+ .p708 ( optlc_net_728 ) , .p709 ( optlc_net_729 ) ,
+ .p710 ( optlc_net_730 ) , .p711 ( optlc_net_731 ) ,
+ .p712 ( optlc_net_732 ) , .p713 ( optlc_net_733 ) ,
+ .p714 ( optlc_net_734 ) , .p715 ( optlc_net_735 ) ,
+ .p716 ( optlc_net_736 ) , .p717 ( optlc_net_737 ) ,
+ .p718 ( optlc_net_738 ) , .p719 ( optlc_net_739 ) ,
+ .p720 ( optlc_net_740 ) , .p721 ( optlc_net_741 ) ,
+ .p722 ( optlc_net_742 ) , .p723 ( optlc_net_743 ) ,
+ .p724 ( optlc_net_744 ) , .p725 ( optlc_net_745 ) ,
+ .p726 ( optlc_net_746 ) , .p727 ( optlc_net_747 ) ,
+ .p728 ( optlc_net_748 ) , .p729 ( optlc_net_749 ) ,
+ .p730 ( optlc_net_750 ) , .p731 ( optlc_net_751 ) ,
+ .p732 ( optlc_net_752 ) , .p733 ( optlc_net_753 ) ,
+ .p734 ( optlc_net_754 ) , .p735 ( optlc_net_755 ) ,
+ .p736 ( optlc_net_756 ) , .p737 ( optlc_net_757 ) ,
+ .p738 ( optlc_net_758 ) , .p739 ( optlc_net_759 ) ,
+ .p740 ( optlc_net_760 ) , .p741 ( optlc_net_761 ) ,
+ .p742 ( optlc_net_762 ) , .p743 ( optlc_net_763 ) ,
+ .p744 ( optlc_net_764 ) , .p745 ( optlc_net_765 ) ,
+ .p746 ( optlc_net_766 ) , .p747 ( optlc_net_767 ) ,
+ .p748 ( optlc_net_768 ) , .p749 ( optlc_net_769 ) ,
+ .p750 ( optlc_net_770 ) , .p751 ( optlc_net_771 ) ,
+ .p752 ( optlc_net_772 ) , .p753 ( optlc_net_773 ) ,
+ .p754 ( optlc_net_774 ) , .p755 ( optlc_net_775 ) ,
+ .p756 ( optlc_net_776 ) , .p757 ( optlc_net_777 ) ,
+ .p758 ( optlc_net_778 ) , .p759 ( optlc_net_779 ) ,
+ .p760 ( optlc_net_780 ) , .p761 ( optlc_net_781 ) ,
+ .p762 ( optlc_net_782 ) , .p763 ( optlc_net_783 ) ,
+ .p764 ( optlc_net_784 ) , .p765 ( optlc_net_785 ) ,
+ .p766 ( optlc_net_786 ) , .p767 ( optlc_net_787 ) ,
+ .p768 ( optlc_net_788 ) , .p769 ( optlc_net_789 ) ,
+ .p770 ( optlc_net_790 ) , .p771 ( optlc_net_791 ) ,
+ .p772 ( optlc_net_792 ) , .p773 ( optlc_net_793 ) ,
+ .p774 ( optlc_net_794 ) , .p775 ( optlc_net_795 ) ,
+ .p776 ( optlc_net_796 ) , .p777 ( optlc_net_797 ) ,
+ .p778 ( optlc_net_798 ) , .p779 ( optlc_net_799 ) ,
+ .p780 ( optlc_net_800 ) , .p781 ( optlc_net_801 ) ,
+ .p782 ( optlc_net_802 ) , .p783 ( optlc_net_803 ) ,
+ .p784 ( optlc_net_804 ) , .p785 ( optlc_net_805 ) ,
+ .p786 ( optlc_net_806 ) , .p787 ( optlc_net_807 ) ,
+ .p788 ( optlc_net_808 ) , .p789 ( optlc_net_809 ) ,
+ .p790 ( optlc_net_810 ) , .p791 ( optlc_net_811 ) ,
+ .p792 ( optlc_net_812 ) , .p793 ( optlc_net_813 ) ,
+ .p794 ( optlc_net_814 ) , .p795 ( optlc_net_815 ) ,
+ .p796 ( optlc_net_816 ) , .p797 ( optlc_net_817 ) ,
+ .p798 ( optlc_net_818 ) , .p799 ( optlc_net_819 ) ,
+ .p800 ( optlc_net_820 ) , .p801 ( optlc_net_821 ) ,
+ .p802 ( optlc_net_822 ) , .p803 ( optlc_net_823 ) ,
+ .p804 ( optlc_net_824 ) , .p805 ( optlc_net_825 ) ,
+ .p806 ( optlc_net_826 ) , .p807 ( optlc_net_827 ) ,
+ .p808 ( optlc_net_828 ) , .p809 ( optlc_net_829 ) ,
+ .p810 ( optlc_net_830 ) , .p811 ( optlc_net_831 ) ,
+ .p812 ( optlc_net_832 ) , .p813 ( optlc_net_833 ) ,
+ .p814 ( optlc_net_834 ) , .p815 ( optlc_net_835 ) ,
+ .p816 ( optlc_net_836 ) , .p817 ( optlc_net_837 ) ,
+ .p818 ( optlc_net_838 ) , .p819 ( optlc_net_839 ) ,
+ .p820 ( optlc_net_840 ) , .p821 ( optlc_net_841 ) ,
+ .p822 ( optlc_net_842 ) , .p823 ( optlc_net_843 ) ,
+ .p824 ( optlc_net_844 ) , .p825 ( optlc_net_845 ) ,
+ .p826 ( optlc_net_846 ) , .p827 ( optlc_net_847 ) ,
+ .p828 ( optlc_net_848 ) , .p829 ( optlc_net_849 ) ,
+ .p830 ( optlc_net_850 ) , .p831 ( optlc_net_851 ) ,
+ .p832 ( optlc_net_852 ) , .p833 ( optlc_net_853 ) ,
+ .p834 ( optlc_net_854 ) , .p835 ( optlc_net_855 ) ,
+ .p836 ( optlc_net_856 ) , .p837 ( optlc_net_857 ) ,
+ .p838 ( optlc_net_858 ) , .p839 ( optlc_net_859 ) ,
+ .p840 ( optlc_net_860 ) , .p841 ( optlc_net_861 ) ,
+ .p842 ( optlc_net_862 ) , .p843 ( optlc_net_863 ) ,
+ .p844 ( optlc_net_864 ) , .p845 ( optlc_net_865 ) ,
+ .p846 ( optlc_net_866 ) , .p847 ( optlc_net_867 ) ,
+ .p848 ( optlc_net_868 ) , .p849 ( optlc_net_869 ) ,
+ .p850 ( optlc_net_870 ) , .p851 ( optlc_net_871 ) ,
+ .p852 ( optlc_net_872 ) , .p853 ( optlc_net_873 ) ,
+ .p854 ( optlc_net_874 ) , .p855 ( optlc_net_875 ) ,
+ .p856 ( optlc_net_876 ) , .p857 ( optlc_net_877 ) ,
+ .p858 ( optlc_net_878 ) , .p859 ( optlc_net_879 ) ,
+ .p860 ( optlc_net_880 ) , .p861 ( optlc_net_881 ) ,
+ .p862 ( optlc_net_882 ) , .p863 ( optlc_net_883 ) ,
+ .p864 ( optlc_net_884 ) , .p865 ( optlc_net_885 ) ,
+ .p866 ( optlc_net_886 ) , .p867 ( optlc_net_887 ) ,
+ .p868 ( optlc_net_888 ) , .p869 ( optlc_net_889 ) ,
+ .p870 ( optlc_net_890 ) , .p871 ( optlc_net_891 ) ,
+ .p872 ( optlc_net_892 ) , .p873 ( optlc_net_893 ) ,
+ .p874 ( optlc_net_894 ) , .p875 ( optlc_net_895 ) ,
+ .p876 ( optlc_net_896 ) , .p877 ( optlc_net_897 ) ,
+ .p878 ( optlc_net_898 ) , .p879 ( optlc_net_899 ) ,
+ .p880 ( optlc_net_900 ) , .p881 ( optlc_net_901 ) ,
+ .p882 ( optlc_net_902 ) , .p883 ( optlc_net_903 ) ,
+ .p884 ( optlc_net_904 ) , .p885 ( optlc_net_905 ) ,
+ .p886 ( optlc_net_906 ) , .p887 ( optlc_net_907 ) ,
+ .p888 ( optlc_net_908 ) , .p889 ( optlc_net_909 ) ,
+ .p890 ( optlc_net_910 ) , .p891 ( optlc_net_911 ) ,
+ .p892 ( optlc_net_912 ) , .p893 ( optlc_net_913 ) ,
+ .p894 ( optlc_net_914 ) , .p895 ( optlc_net_915 ) ,
+ .p896 ( optlc_net_916 ) , .p897 ( optlc_net_917 ) ,
+ .p898 ( optlc_net_918 ) , .p899 ( optlc_net_919 ) ,
+ .p900 ( optlc_net_920 ) , .p901 ( optlc_net_921 ) ,
+ .p902 ( optlc_net_922 ) , .p903 ( optlc_net_923 ) ,
+ .p904 ( optlc_net_924 ) , .p905 ( optlc_net_925 ) ,
+ .p906 ( optlc_net_926 ) , .p907 ( optlc_net_927 ) ,
+ .p908 ( optlc_net_928 ) , .p909 ( optlc_net_929 ) ,
+ .p910 ( optlc_net_930 ) , .p911 ( optlc_net_931 ) ,
+ .p912 ( optlc_net_932 ) , .p913 ( optlc_net_933 ) ,
+ .p914 ( optlc_net_934 ) , .p915 ( optlc_net_935 ) ,
+ .p916 ( optlc_net_936 ) , .p917 ( optlc_net_937 ) ,
+ .p918 ( optlc_net_938 ) , .p919 ( optlc_net_939 ) ,
+ .p920 ( optlc_net_940 ) , .p921 ( optlc_net_941 ) ,
+ .p922 ( optlc_net_942 ) , .p923 ( optlc_net_943 ) ,
+ .p924 ( optlc_net_944 ) , .p925 ( optlc_net_945 ) ,
+ .p926 ( optlc_net_946 ) , .p927 ( optlc_net_947 ) ,
+ .p928 ( optlc_net_948 ) , .p929 ( optlc_net_949 ) ,
+ .p930 ( optlc_net_950 ) , .p931 ( optlc_net_951 ) ,
+ .p932 ( optlc_net_952 ) , .p933 ( optlc_net_953 ) ,
+ .p934 ( optlc_net_954 ) , .p935 ( optlc_net_955 ) ,
+ .p936 ( optlc_net_956 ) , .p937 ( optlc_net_957 ) ,
+ .p938 ( optlc_net_958 ) , .p939 ( optlc_net_959 ) ,
+ .p940 ( optlc_net_960 ) , .p941 ( optlc_net_961 ) ,
+ .p942 ( optlc_net_962 ) , .p943 ( optlc_net_963 ) ,
+ .p944 ( optlc_net_964 ) , .p945 ( optlc_net_965 ) ,
+ .p946 ( optlc_net_966 ) , .p947 ( optlc_net_967 ) ,
+ .p948 ( optlc_net_968 ) , .p949 ( optlc_net_969 ) ,
+ .p950 ( optlc_net_970 ) , .p951 ( optlc_net_971 ) ,
+ .p952 ( optlc_net_972 ) , .p953 ( optlc_net_973 ) ,
+ .p954 ( optlc_net_974 ) , .p955 ( optlc_net_975 ) ,
+ .p956 ( optlc_net_976 ) , .p957 ( optlc_net_977 ) ,
+ .p958 ( optlc_net_978 ) , .p959 ( optlc_net_979 ) ,
+ .p960 ( optlc_net_980 ) , .p961 ( optlc_net_981 ) ,
+ .p962 ( optlc_net_982 ) , .p963 ( optlc_net_983 ) ,
+ .p964 ( optlc_net_984 ) , .p965 ( optlc_net_985 ) ,
+ .p966 ( optlc_net_986 ) , .p967 ( optlc_net_987 ) ,
+ .p968 ( optlc_net_988 ) , .p969 ( optlc_net_989 ) ,
+ .p970 ( optlc_net_990 ) , .p971 ( optlc_net_991 ) ,
+ .p972 ( optlc_net_992 ) , .p973 ( optlc_net_993 ) ,
+ .p974 ( optlc_net_994 ) , .p975 ( optlc_net_995 ) ,
+ .p976 ( optlc_net_996 ) , .p977 ( optlc_net_997 ) ,
+ .p978 ( optlc_net_998 ) , .p979 ( optlc_net_999 ) ,
+ .p980 ( optlc_net_1000 ) , .p981 ( optlc_net_1001 ) ,
+ .p982 ( optlc_net_1002 ) , .p983 ( optlc_net_1003 ) ,
+ .p984 ( optlc_net_1004 ) , .p985 ( optlc_net_1005 ) ,
+ .p986 ( optlc_net_1006 ) , .p987 ( optlc_net_1007 ) ,
+ .p988 ( optlc_net_1008 ) , .p989 ( optlc_net_1009 ) ,
+ .p990 ( optlc_net_1010 ) , .p991 ( optlc_net_1011 ) ,
+ .p992 ( optlc_net_1012 ) , .p993 ( optlc_net_1013 ) ,
+ .p994 ( optlc_net_1014 ) , .p995 ( optlc_net_1015 ) ,
+ .p996 ( optlc_net_1016 ) , .p997 ( optlc_net_1017 ) ,
+ .p998 ( optlc_net_1018 ) , .p999 ( optlc_net_1019 ) ,
+ .p1000 ( optlc_net_1020 ) , .p1001 ( optlc_net_1021 ) ,
+ .p1002 ( optlc_net_1022 ) , .p1003 ( optlc_net_1023 ) ,
+ .p1004 ( optlc_net_1024 ) , .p1005 ( optlc_net_1025 ) ,
+ .p1006 ( optlc_net_1026 ) , .p1007 ( optlc_net_1027 ) ,
+ .p1008 ( optlc_net_1028 ) , .p1009 ( optlc_net_1029 ) ,
+ .p1010 ( optlc_net_1030 ) , .p1011 ( optlc_net_1031 ) ,
+ .p1012 ( optlc_net_1032 ) , .p1013 ( optlc_net_1033 ) ,
+ .p1014 ( optlc_net_1034 ) , .p1015 ( optlc_net_1035 ) ,
+ .p1016 ( optlc_net_1036 ) , .p1017 ( optlc_net_1037 ) ,
+ .p1018 ( optlc_net_1038 ) , .p1019 ( optlc_net_1039 ) ,
+ .p1020 ( optlc_net_1040 ) , .p1021 ( optlc_net_1041 ) ,
+ .p1022 ( optlc_net_1042 ) , .p1023 ( optlc_net_1043 ) ,
+ .p1024 ( optlc_net_1044 ) , .p1025 ( optlc_net_1045 ) ,
+ .p1026 ( optlc_net_1046 ) , .p1027 ( optlc_net_1047 ) ,
+ .p1028 ( optlc_net_1048 ) , .p1029 ( optlc_net_1049 ) ,
+ .p1030 ( optlc_net_1050 ) , .p1031 ( optlc_net_1051 ) ,
+ .p1032 ( optlc_net_1052 ) , .p1033 ( optlc_net_1053 ) ,
+ .p1034 ( optlc_net_1054 ) , .p1035 ( optlc_net_1055 ) ,
+ .p1036 ( optlc_net_1056 ) , .p1037 ( optlc_net_1057 ) ,
+ .p1038 ( optlc_net_1058 ) , .p1039 ( optlc_net_1059 ) ,
+ .p1040 ( optlc_net_1060 ) , .p1041 ( optlc_net_1061 ) ,
+ .p1042 ( optlc_net_1062 ) , .p1043 ( optlc_net_1063 ) ,
+ .p1044 ( optlc_net_1064 ) , .p1045 ( optlc_net_1065 ) ,
+ .p1046 ( optlc_net_1066 ) , .p1047 ( optlc_net_1067 ) ,
+ .p1048 ( optlc_net_1068 ) , .p1049 ( optlc_net_1069 ) ,
+ .p1050 ( optlc_net_1070 ) , .p1051 ( optlc_net_1071 ) ,
+ .p1052 ( optlc_net_1072 ) , .p1053 ( optlc_net_1073 ) ,
+ .p1054 ( optlc_net_1074 ) , .p1055 ( optlc_net_1075 ) ,
+ .p1056 ( optlc_net_1076 ) , .p1057 ( optlc_net_1077 ) ,
+ .p1058 ( optlc_net_1078 ) , .p1059 ( optlc_net_1079 ) ,
+ .p1060 ( optlc_net_1080 ) , .p1061 ( optlc_net_1081 ) ,
+ .p1062 ( optlc_net_1082 ) , .p1063 ( optlc_net_1083 ) ,
+ .p1064 ( optlc_net_1084 ) , .p1065 ( optlc_net_1085 ) ,
+ .p1066 ( optlc_net_1086 ) , .p1067 ( optlc_net_1087 ) ,
+ .p1068 ( optlc_net_1088 ) , .p1069 ( optlc_net_1089 ) ,
+ .p1070 ( optlc_net_1090 ) , .p1071 ( optlc_net_1091 ) ,
+ .p1072 ( optlc_net_1092 ) , .p1073 ( optlc_net_1093 ) ,
+ .p1074 ( optlc_net_1094 ) , .p1075 ( optlc_net_1095 ) ,
+ .p1076 ( optlc_net_1096 ) , .p1077 ( optlc_net_1097 ) ,
+ .p1078 ( optlc_net_1098 ) , .p1079 ( optlc_net_1099 ) ,
+ .p1080 ( optlc_net_1100 ) , .p1081 ( optlc_net_1101 ) ,
+ .p1082 ( optlc_net_1102 ) , .p1083 ( optlc_net_1103 ) ,
+ .p1084 ( optlc_net_1104 ) , .p1085 ( optlc_net_1105 ) ,
+ .p1086 ( optlc_net_1106 ) , .p1087 ( optlc_net_1107 ) ,
+ .p1088 ( optlc_net_1108 ) , .p1089 ( optlc_net_1109 ) ,
+ .p1090 ( optlc_net_1110 ) , .p1091 ( optlc_net_1111 ) ,
+ .p1092 ( optlc_net_1112 ) , .p1093 ( optlc_net_1113 ) ,
+ .p1094 ( optlc_net_1114 ) , .p1095 ( optlc_net_1115 ) ,
+ .p1096 ( optlc_net_1116 ) , .p1097 ( optlc_net_1117 ) ,
+ .p1098 ( optlc_net_1118 ) , .p1099 ( optlc_net_1119 ) ,
+ .p1100 ( optlc_net_1120 ) , .p1101 ( optlc_net_1121 ) ,
+ .p1102 ( optlc_net_1122 ) , .p1103 ( optlc_net_1123 ) ,
+ .p1104 ( optlc_net_1124 ) , .p1105 ( optlc_net_1125 ) ,
+ .p1106 ( optlc_net_1126 ) , .p1107 ( optlc_net_1127 ) ,
+ .p1108 ( optlc_net_1128 ) , .p1109 ( optlc_net_1129 ) ,
+ .p1110 ( optlc_net_1130 ) , .p1111 ( optlc_net_1131 ) ,
+ .p1112 ( optlc_net_1132 ) , .p1113 ( optlc_net_1133 ) ,
+ .p1114 ( optlc_net_1134 ) , .p1115 ( optlc_net_1135 ) ,
+ .p1116 ( optlc_net_1136 ) , .p1117 ( optlc_net_1137 ) ,
+ .p1118 ( optlc_net_1138 ) , .p1119 ( optlc_net_1139 ) ,
+ .p1120 ( optlc_net_1140 ) , .p1121 ( optlc_net_1141 ) ,
+ .p1122 ( optlc_net_1142 ) , .p1123 ( optlc_net_1143 ) ,
+ .p1124 ( optlc_net_1144 ) , .p1125 ( optlc_net_1145 ) ,
+ .p1126 ( optlc_net_1146 ) , .p1127 ( optlc_net_1147 ) ,
+ .p1128 ( optlc_net_1148 ) , .p1129 ( optlc_net_1149 ) ,
+ .p1130 ( optlc_net_1150 ) , .p1131 ( optlc_net_1151 ) ,
+ .p1132 ( optlc_net_1152 ) , .p1133 ( optlc_net_1153 ) ,
+ .p1134 ( optlc_net_1154 ) , .p1135 ( optlc_net_1155 ) ,
+ .p1136 ( optlc_net_1156 ) , .p1137 ( optlc_net_1157 ) ,
+ .p1138 ( optlc_net_1158 ) , .p1139 ( optlc_net_1159 ) ,
+ .p1140 ( optlc_net_1160 ) , .p1141 ( optlc_net_1161 ) ,
+ .p1142 ( optlc_net_1162 ) , .p1143 ( optlc_net_1163 ) ,
+ .p1144 ( optlc_net_1164 ) , .p1145 ( optlc_net_1165 ) ,
+ .p1146 ( optlc_net_1166 ) , .p1147 ( optlc_net_1167 ) ,
+ .p1148 ( optlc_net_1168 ) , .p1149 ( optlc_net_1169 ) ,
+ .p1150 ( optlc_net_1170 ) , .p1151 ( optlc_net_1171 ) ,
+ .p1152 ( optlc_net_1172 ) , .p1153 ( optlc_net_1173 ) ,
+ .p1154 ( optlc_net_1174 ) , .p1155 ( optlc_net_1175 ) ,
+ .p1156 ( optlc_net_1176 ) , .p1157 ( optlc_net_1177 ) ,
+ .p1158 ( optlc_net_1178 ) , .p1159 ( optlc_net_1179 ) ,
+ .p1160 ( optlc_net_1180 ) , .p1161 ( optlc_net_1181 ) ,
+ .p1162 ( optlc_net_1182 ) , .p1163 ( optlc_net_1183 ) ,
+ .p1164 ( optlc_net_1184 ) , .p1165 ( optlc_net_1185 ) ,
+ .p1166 ( optlc_net_1186 ) , .p1167 ( optlc_net_1187 ) ,
+ .p1168 ( optlc_net_1188 ) , .p1169 ( optlc_net_1189 ) ,
+ .p1170 ( optlc_net_1190 ) , .p1171 ( optlc_net_1191 ) ,
+ .p1172 ( optlc_net_1192 ) , .p1173 ( optlc_net_1193 ) ,
+ .p1174 ( optlc_net_1194 ) , .p1175 ( optlc_net_1195 ) ,
+ .p1176 ( optlc_net_1196 ) , .p1177 ( optlc_net_1197 ) ,
+ .p1178 ( optlc_net_1198 ) , .p1179 ( optlc_net_1199 ) ,
+ .p1180 ( optlc_net_1200 ) , .p1181 ( optlc_net_1201 ) ,
+ .p1182 ( optlc_net_1202 ) , .p1183 ( optlc_net_1203 ) ,
+ .p1184 ( optlc_net_1204 ) , .p1185 ( optlc_net_1205 ) ,
+ .p1186 ( optlc_net_1206 ) , .p1187 ( optlc_net_1207 ) ,
+ .p1188 ( optlc_net_1208 ) , .p1189 ( optlc_net_1209 ) ,
+ .p1190 ( optlc_net_1210 ) , .p1191 ( optlc_net_1211 ) ,
+ .p1192 ( optlc_net_1212 ) , .p1193 ( optlc_net_1213 ) ,
+ .p1194 ( optlc_net_1214 ) , .p1195 ( optlc_net_1215 ) ,
+ .p1196 ( optlc_net_1216 ) , .p1197 ( optlc_net_1217 ) ,
+ .p1198 ( optlc_net_1218 ) , .p1199 ( optlc_net_1219 ) ,
+ .p1200 ( optlc_net_1220 ) , .p1201 ( optlc_net_1221 ) ,
+ .p1202 ( optlc_net_1222 ) , .p1203 ( optlc_net_1223 ) ,
+ .p1204 ( optlc_net_1224 ) , .p1205 ( optlc_net_1225 ) ,
+ .p1206 ( optlc_net_1226 ) , .p1207 ( optlc_net_1227 ) ,
+ .p1208 ( optlc_net_1228 ) , .p1209 ( optlc_net_1229 ) ,
+ .p1210 ( optlc_net_1230 ) , .p1211 ( optlc_net_1231 ) ,
+ .p1212 ( optlc_net_1232 ) , .p1213 ( optlc_net_1233 ) ,
+ .p1214 ( optlc_net_1234 ) , .p1215 ( optlc_net_1235 ) ,
+ .p1216 ( optlc_net_1236 ) , .p1217 ( optlc_net_1237 ) ,
+ .p1218 ( optlc_net_1238 ) , .p1219 ( optlc_net_1239 ) ,
+ .p1220 ( optlc_net_1240 ) , .p1221 ( optlc_net_1241 ) ,
+ .p1222 ( optlc_net_1242 ) , .p1223 ( optlc_net_1243 ) ,
+ .p1224 ( optlc_net_1244 ) , .p1225 ( optlc_net_1245 ) ,
+ .p1226 ( optlc_net_1246 ) , .p1227 ( optlc_net_1247 ) ,
+ .p1228 ( optlc_net_1248 ) , .p1229 ( optlc_net_1249 ) ,
+ .p1230 ( optlc_net_1250 ) , .p1231 ( optlc_net_1251 ) ,
+ .p1232 ( optlc_net_1252 ) , .p1233 ( optlc_net_1253 ) ,
+ .p1234 ( optlc_net_1254 ) , .p1235 ( optlc_net_1255 ) ,
+ .p1236 ( optlc_net_1256 ) , .p1237 ( optlc_net_1257 ) ,
+ .p1238 ( optlc_net_1258 ) , .p1239 ( optlc_net_1259 ) ,
+ .p1240 ( optlc_net_1260 ) , .p1241 ( optlc_net_1261 ) ,
+ .p1242 ( optlc_net_1262 ) , .p1243 ( optlc_net_1263 ) ,
+ .p1244 ( optlc_net_1264 ) , .p1245 ( optlc_net_1265 ) ,
+ .p1246 ( optlc_net_1266 ) , .p1247 ( optlc_net_1267 ) ,
+ .p1248 ( optlc_net_1268 ) , .p1249 ( optlc_net_1269 ) ,
+ .p1250 ( optlc_net_1270 ) , .p1251 ( optlc_net_1271 ) ,
+ .p1252 ( optlc_net_1272 ) , .p1253 ( optlc_net_1273 ) ,
+ .p1254 ( optlc_net_1274 ) , .p1255 ( optlc_net_1275 ) ,
+ .p1256 ( optlc_net_1276 ) , .p1257 ( optlc_net_1277 ) ,
+ .p1258 ( optlc_net_1278 ) , .p1259 ( optlc_net_1279 ) ,
+ .p1260 ( optlc_net_1280 ) , .p1261 ( optlc_net_1281 ) ,
+ .p1262 ( optlc_net_1282 ) , .p1263 ( optlc_net_1283 ) ,
+ .p1264 ( optlc_net_1284 ) , .p1265 ( optlc_net_1285 ) ,
+ .p1266 ( optlc_net_1286 ) , .p1267 ( optlc_net_1287 ) ,
+ .p1268 ( optlc_net_1288 ) , .p1269 ( optlc_net_1289 ) ,
+ .p1270 ( optlc_net_1290 ) , .p1271 ( optlc_net_1291 ) ,
+ .p1272 ( optlc_net_1292 ) , .p1273 ( optlc_net_1293 ) ,
+ .p1274 ( optlc_net_1294 ) , .p1275 ( optlc_net_1295 ) ,
+ .p1276 ( optlc_net_1296 ) , .p1277 ( optlc_net_1297 ) ,
+ .p1278 ( optlc_net_1298 ) , .p1279 ( optlc_net_1299 ) ,
+ .p1280 ( optlc_net_1300 ) , .p1281 ( optlc_net_1301 ) ,
+ .p1282 ( optlc_net_1302 ) , .p1283 ( optlc_net_1303 ) ,
+ .p1284 ( optlc_net_1304 ) , .p1285 ( optlc_net_1305 ) ,
+ .p1286 ( optlc_net_1306 ) , .p1287 ( optlc_net_1307 ) ,
+ .p1288 ( optlc_net_1308 ) , .p1289 ( optlc_net_1309 ) ,
+ .p1290 ( optlc_net_1310 ) , .p1291 ( optlc_net_1311 ) ,
+ .p1292 ( optlc_net_1312 ) , .p1293 ( optlc_net_1313 ) ,
+ .p1294 ( optlc_net_1314 ) , .p1295 ( optlc_net_1315 ) ,
+ .p1296 ( optlc_net_1316 ) , .p1297 ( optlc_net_1317 ) ,
+ .p1298 ( optlc_net_1318 ) , .p1299 ( optlc_net_1319 ) ,
+ .p1300 ( optlc_net_1320 ) , .p1301 ( optlc_net_1321 ) ,
+ .p1302 ( optlc_net_1322 ) , .p1303 ( optlc_net_1323 ) ,
+ .p1304 ( optlc_net_1324 ) , .p1305 ( optlc_net_1325 ) ,
+ .p1306 ( optlc_net_1326 ) , .p1307 ( optlc_net_1327 ) ,
+ .p1308 ( optlc_net_1328 ) , .p1309 ( optlc_net_1329 ) ,
+ .p1310 ( optlc_net_1330 ) , .p1311 ( optlc_net_1331 ) ,
+ .p1312 ( optlc_net_1332 ) , .p1313 ( optlc_net_1333 ) ,
+ .p1314 ( optlc_net_1334 ) , .p1315 ( optlc_net_1335 ) ,
+ .p1316 ( optlc_net_1336 ) , .p1317 ( optlc_net_1337 ) ,
+ .p1318 ( optlc_net_1338 ) , .p1319 ( optlc_net_1339 ) ,
+ .p1320 ( optlc_net_1340 ) , .p1321 ( optlc_net_1341 ) ,
+ .p1322 ( optlc_net_1342 ) , .p1323 ( optlc_net_1343 ) ,
+ .p1324 ( optlc_net_1344 ) , .p1325 ( optlc_net_1345 ) ,
+ .p1326 ( optlc_net_1346 ) , .p1327 ( optlc_net_1347 ) ,
+ .p1328 ( optlc_net_1348 ) , .p1329 ( optlc_net_1349 ) ,
+ .p1330 ( optlc_net_1350 ) , .p1331 ( optlc_net_1351 ) ,
+ .p1332 ( optlc_net_1352 ) , .p1333 ( optlc_net_1353 ) ,
+ .p1334 ( optlc_net_1354 ) , .p1335 ( optlc_net_1355 ) ,
+ .p1336 ( optlc_net_1356 ) , .p1337 ( optlc_net_1357 ) ,
+ .p1338 ( optlc_net_1358 ) , .p1339 ( optlc_net_1359 ) ,
+ .p1340 ( optlc_net_1360 ) , .p1341 ( optlc_net_1361 ) ,
+ .p1342 ( optlc_net_1362 ) , .p1343 ( optlc_net_1363 ) ,
+ .p1344 ( optlc_net_1364 ) , .p1345 ( optlc_net_1365 ) ,
+ .p1346 ( optlc_net_1366 ) , .p1347 ( optlc_net_1367 ) ,
+ .p1348 ( optlc_net_1368 ) , .p1349 ( optlc_net_1369 ) ,
+ .p1350 ( optlc_net_1370 ) , .p1351 ( optlc_net_1371 ) ,
+ .p1352 ( optlc_net_1372 ) , .p1353 ( optlc_net_1373 ) ,
+ .p1354 ( optlc_net_1374 ) , .p1355 ( optlc_net_1375 ) ,
+ .p1356 ( optlc_net_1376 ) , .p1357 ( optlc_net_1377 ) ,
+ .p1358 ( optlc_net_1378 ) , .p1359 ( optlc_net_1379 ) ,
+ .p1360 ( optlc_net_1380 ) , .p1361 ( optlc_net_1381 ) ,
+ .p1362 ( optlc_net_1382 ) , .p1363 ( optlc_net_1383 ) ,
+ .p1364 ( optlc_net_1384 ) , .p1365 ( optlc_net_1385 ) ,
+ .p1366 ( optlc_net_1386 ) , .p1367 ( optlc_net_1387 ) ,
+ .p1368 ( optlc_net_1388 ) , .p1369 ( optlc_net_1389 ) ,
+ .p1370 ( optlc_net_1390 ) , .p1371 ( optlc_net_1391 ) ,
+ .p1372 ( optlc_net_1392 ) , .p1373 ( optlc_net_1393 ) ,
+ .p1374 ( optlc_net_1394 ) , .p1375 ( optlc_net_1395 ) ,
+ .p1376 ( optlc_net_1396 ) , .p1377 ( optlc_net_1397 ) ,
+ .p1378 ( optlc_net_1398 ) , .p1379 ( optlc_net_1399 ) ,
+ .p1380 ( optlc_net_1400 ) , .p1381 ( optlc_net_1401 ) ,
+ .p1382 ( optlc_net_1402 ) , .p1383 ( optlc_net_1403 ) ,
+ .p1384 ( optlc_net_1404 ) , .p1385 ( optlc_net_1405 ) ,
+ .p1386 ( optlc_net_1406 ) , .p1387 ( optlc_net_1407 ) ,
+ .p1388 ( optlc_net_1408 ) , .p1389 ( optlc_net_1409 ) ,
+ .p1390 ( optlc_net_1410 ) , .p1391 ( optlc_net_1411 ) ,
+ .p1392 ( optlc_net_1412 ) , .p1393 ( optlc_net_1413 ) ,
+ .p1394 ( optlc_net_1414 ) , .p1395 ( optlc_net_1415 ) ,
+ .p1396 ( optlc_net_1416 ) , .p1397 ( optlc_net_1417 ) ,
+ .p1398 ( optlc_net_1418 ) , .p1399 ( optlc_net_1419 ) ,
+ .p1400 ( optlc_net_1420 ) , .p1401 ( optlc_net_1421 ) ,
+ .p1402 ( optlc_net_1422 ) , .p1403 ( optlc_net_1423 ) ,
+ .p1404 ( optlc_net_1424 ) , .p1405 ( optlc_net_1425 ) ,
+ .p1406 ( optlc_net_1426 ) , .p1407 ( optlc_net_1427 ) ,
+ .p1408 ( optlc_net_1428 ) , .p1409 ( optlc_net_1429 ) ,
+ .p1410 ( optlc_net_1430 ) , .p1411 ( optlc_net_1431 ) ,
+ .p1412 ( optlc_net_1432 ) , .p1413 ( optlc_net_1433 ) ,
+ .p1414 ( optlc_net_1434 ) , .p1415 ( optlc_net_1435 ) ,
+ .p1416 ( optlc_net_1436 ) , .p1417 ( optlc_net_1437 ) ,
+ .p1418 ( optlc_net_1438 ) , .p1419 ( optlc_net_1439 ) ,
+ .p1420 ( optlc_net_1440 ) , .p1421 ( optlc_net_1441 ) ,
+ .p1422 ( optlc_net_1442 ) , .p1423 ( optlc_net_1443 ) ,
+ .p1424 ( optlc_net_1444 ) , .p1425 ( optlc_net_1445 ) ,
+ .p1426 ( optlc_net_1446 ) , .p1427 ( optlc_net_1447 ) ,
+ .p1428 ( optlc_net_1448 ) , .p1429 ( optlc_net_1449 ) ,
+ .p1430 ( optlc_net_1450 ) , .p1431 ( optlc_net_1451 ) ,
+ .p1432 ( optlc_net_1452 ) , .p1433 ( optlc_net_1453 ) ,
+ .p1434 ( optlc_net_1454 ) , .p1435 ( optlc_net_1455 ) ,
+ .p1436 ( optlc_net_1456 ) , .p1437 ( optlc_net_1457 ) ,
+ .p1438 ( optlc_net_1458 ) , .p1439 ( optlc_net_1459 ) ,
+ .p1440 ( optlc_net_1460 ) , .p1441 ( optlc_net_1461 ) ,
+ .p1442 ( optlc_net_1462 ) , .p1443 ( optlc_net_1463 ) ,
+ .p1444 ( optlc_net_1464 ) , .p1445 ( optlc_net_1465 ) ,
+ .p1446 ( optlc_net_1466 ) , .p1447 ( optlc_net_1467 ) ,
+ .p1448 ( optlc_net_1468 ) , .p1449 ( optlc_net_1469 ) ,
+ .p1450 ( optlc_net_1470 ) , .p1451 ( optlc_net_1471 ) ,
+ .p1452 ( optlc_net_1472 ) , .p1453 ( optlc_net_1473 ) ,
+ .p1454 ( optlc_net_1474 ) , .p1455 ( optlc_net_1475 ) ,
+ .p1456 ( optlc_net_1476 ) , .p1457 ( optlc_net_1477 ) ,
+ .p1458 ( optlc_net_1478 ) , .p1459 ( optlc_net_1479 ) ,
+ .p1460 ( optlc_net_1480 ) , .p1461 ( optlc_net_1481 ) ,
+ .p1462 ( optlc_net_1482 ) , .p1463 ( optlc_net_1483 ) ,
+ .p1464 ( optlc_net_1484 ) , .p1465 ( optlc_net_1485 ) ,
+ .p1466 ( optlc_net_1486 ) , .p1467 ( optlc_net_1487 ) ,
+ .p1468 ( optlc_net_1488 ) , .p1469 ( optlc_net_1489 ) ,
+ .p1470 ( optlc_net_1490 ) , .p1471 ( optlc_net_1491 ) ,
+ .p1472 ( optlc_net_1492 ) , .p1473 ( optlc_net_1493 ) ,
+ .p1474 ( optlc_net_1494 ) , .p1475 ( optlc_net_1495 ) ,
+ .p1476 ( optlc_net_1496 ) , .p1477 ( optlc_net_1497 ) ,
+ .p1478 ( optlc_net_1498 ) , .p1479 ( optlc_net_1499 ) ,
+ .p1480 ( optlc_net_1500 ) , .p1481 ( optlc_net_1501 ) ,
+ .p1482 ( optlc_net_1502 ) , .p1483 ( optlc_net_1503 ) ,
+ .p1484 ( optlc_net_1504 ) , .p1485 ( optlc_net_1505 ) ,
+ .p1486 ( optlc_net_1506 ) , .p1487 ( optlc_net_1507 ) ,
+ .p1488 ( optlc_net_1508 ) , .p1489 ( optlc_net_1509 ) ,
+ .p1490 ( optlc_net_1510 ) , .p1491 ( optlc_net_1511 ) ,
+ .p1492 ( optlc_net_1512 ) , .p1493 ( optlc_net_1513 ) ,
+ .p1494 ( optlc_net_1514 ) , .p1495 ( optlc_net_1515 ) ,
+ .p1496 ( optlc_net_1516 ) , .p1497 ( optlc_net_1517 ) ,
+ .p1498 ( optlc_net_1518 ) , .p1499 ( optlc_net_1519 ) ,
+ .p1500 ( optlc_net_1520 ) , .p1501 ( optlc_net_1521 ) ,
+ .p1502 ( optlc_net_1522 ) , .p1503 ( optlc_net_1523 ) ,
+ .p1504 ( optlc_net_1524 ) , .p1505 ( optlc_net_1525 ) ,
+ .p1506 ( optlc_net_1526 ) , .p1507 ( optlc_net_1527 ) ,
+ .p1508 ( optlc_net_1528 ) , .p1509 ( optlc_net_1529 ) ,
+ .p1510 ( optlc_net_1530 ) , .p1511 ( optlc_net_1531 ) ,
+ .p1512 ( optlc_net_1532 ) , .p1513 ( optlc_net_1533 ) ,
+ .p1514 ( optlc_net_1534 ) , .p1515 ( optlc_net_1535 ) ,
+ .p1516 ( optlc_net_1536 ) , .p1517 ( optlc_net_1537 ) ,
+ .p1518 ( optlc_net_1538 ) , .p1519 ( optlc_net_1539 ) ,
+ .p1520 ( optlc_net_1540 ) , .p1521 ( optlc_net_1541 ) ,
+ .p1522 ( optlc_net_1542 ) , .p1523 ( optlc_net_1543 ) ,
+ .p1524 ( optlc_net_1544 ) , .p1525 ( optlc_net_1545 ) ,
+ .p1526 ( optlc_net_1546 ) , .p1527 ( optlc_net_1547 ) ,
+ .p1528 ( optlc_net_1548 ) , .p1529 ( optlc_net_1549 ) ,
+ .p1530 ( optlc_net_1550 ) , .p1531 ( optlc_net_1551 ) ,
+ .p1532 ( optlc_net_1552 ) , .p1533 ( optlc_net_1553 ) ,
+ .p1534 ( optlc_net_1554 ) , .p1535 ( optlc_net_1555 ) ,
+ .p1536 ( optlc_net_1556 ) , .p1537 ( optlc_net_1557 ) ,
+ .p1538 ( optlc_net_1558 ) , .p1539 ( optlc_net_1559 ) ,
+ .p1540 ( optlc_net_1560 ) , .p1541 ( optlc_net_1561 ) ,
+ .p1542 ( optlc_net_1562 ) , .p1543 ( optlc_net_1563 ) ,
+ .p1544 ( optlc_net_1564 ) , .p1545 ( optlc_net_1565 ) ,
+ .p1546 ( optlc_net_1566 ) , .p1547 ( optlc_net_1567 ) ,
+ .p1548 ( optlc_net_1568 ) , .p1549 ( optlc_net_1569 ) ,
+ .p1550 ( optlc_net_1570 ) , .p1551 ( optlc_net_1571 ) ,
+ .p1552 ( optlc_net_1572 ) , .p1553 ( optlc_net_1573 ) ,
+ .p1554 ( optlc_net_1574 ) , .p1555 ( optlc_net_1575 ) ,
+ .p1556 ( optlc_net_1576 ) , .p1557 ( optlc_net_1577 ) ,
+ .p1558 ( optlc_net_1578 ) , .p1559 ( optlc_net_1579 ) ,
+ .p1560 ( optlc_net_1580 ) , .p1561 ( optlc_net_1581 ) ,
+ .p1562 ( optlc_net_1582 ) , .p1563 ( optlc_net_1583 ) ,
+ .p1564 ( optlc_net_1584 ) , .p1565 ( optlc_net_1585 ) ,
+ .p1566 ( optlc_net_1586 ) , .p1567 ( optlc_net_1587 ) ,
+ .p1568 ( optlc_net_1588 ) , .p1569 ( optlc_net_1589 ) ,
+ .p1570 ( optlc_net_1590 ) , .p1571 ( optlc_net_1591 ) ,
+ .p1572 ( optlc_net_1592 ) , .p1573 ( optlc_net_1593 ) ,
+ .p1574 ( optlc_net_1594 ) , .p1575 ( optlc_net_1595 ) ,
+ .p1576 ( optlc_net_1596 ) , .p1577 ( optlc_net_1597 ) ,
+ .p1578 ( optlc_net_1598 ) , .p1579 ( optlc_net_1599 ) ,
+ .p1580 ( optlc_net_1600 ) , .p1581 ( optlc_net_1601 ) ,
+ .p1582 ( optlc_net_1602 ) , .p1583 ( optlc_net_1603 ) ,
+ .p1584 ( optlc_net_1604 ) , .p1585 ( optlc_net_1605 ) ,
+ .p1586 ( optlc_net_1606 ) , .p1587 ( optlc_net_1607 ) ,
+ .p1588 ( optlc_net_1608 ) , .p1589 ( optlc_net_1609 ) ,
+ .p1590 ( optlc_net_1610 ) , .p1591 ( optlc_net_1611 ) ,
+ .p1592 ( optlc_net_1612 ) , .p1593 ( optlc_net_1613 ) ,
+ .p1594 ( optlc_net_1614 ) , .p1595 ( optlc_net_1615 ) ,
+ .p1596 ( optlc_net_1616 ) , .p1597 ( optlc_net_1617 ) ,
+ .p1598 ( optlc_net_1618 ) , .p1599 ( optlc_net_1619 ) ,
+ .p1600 ( optlc_net_1620 ) , .p1601 ( optlc_net_1621 ) ,
+ .p1602 ( optlc_net_1622 ) , .p1603 ( optlc_net_1623 ) ,
+ .p1604 ( optlc_net_1624 ) , .p1605 ( optlc_net_1625 ) ,
+ .p1606 ( optlc_net_1626 ) , .p1607 ( optlc_net_1627 ) ,
+ .p1608 ( optlc_net_1628 ) , .p1609 ( optlc_net_1629 ) ,
+ .p1610 ( optlc_net_1630 ) , .p1611 ( optlc_net_1631 ) ,
+ .p1612 ( optlc_net_1632 ) , .p1613 ( optlc_net_1633 ) ,
+ .p1614 ( optlc_net_1634 ) , .p1615 ( optlc_net_1635 ) ,
+ .p1616 ( optlc_net_1636 ) , .p1617 ( optlc_net_1637 ) ,
+ .p1618 ( optlc_net_1638 ) , .p1619 ( optlc_net_1639 ) ,
+ .p1620 ( optlc_net_1640 ) , .p1621 ( optlc_net_1641 ) ,
+ .p1622 ( optlc_net_1642 ) , .p1623 ( optlc_net_1643 ) ,
+ .p1624 ( optlc_net_1644 ) , .p1625 ( optlc_net_1645 ) ,
+ .p1626 ( optlc_net_1646 ) , .p1627 ( optlc_net_1647 ) ,
+ .p1628 ( optlc_net_1648 ) , .p1629 ( optlc_net_1649 ) ,
+ .p1630 ( optlc_net_1650 ) , .p1631 ( optlc_net_1651 ) ,
+ .p1632 ( optlc_net_1652 ) , .p1633 ( optlc_net_1653 ) ,
+ .p1634 ( optlc_net_1654 ) , .p1635 ( optlc_net_1655 ) ,
+ .p1636 ( optlc_net_1656 ) , .p1637 ( optlc_net_1657 ) ,
+ .p1638 ( optlc_net_1658 ) , .p1639 ( optlc_net_1659 ) ,
+ .p1640 ( optlc_net_1660 ) , .p1641 ( optlc_net_1661 ) ,
+ .p1642 ( optlc_net_1662 ) , .p1643 ( optlc_net_1663 ) ,
+ .p1644 ( optlc_net_1664 ) , .p1645 ( optlc_net_1665 ) ,
+ .p1646 ( optlc_net_1666 ) , .p1647 ( optlc_net_1667 ) ,
+ .p1648 ( optlc_net_1668 ) , .p1649 ( optlc_net_1669 ) ,
+ .p1650 ( optlc_net_1670 ) , .p1651 ( optlc_net_1671 ) ,
+ .p1652 ( optlc_net_1672 ) , .p1653 ( optlc_net_1673 ) ,
+ .p1654 ( optlc_net_1674 ) , .p1655 ( optlc_net_1675 ) ,
+ .p1656 ( optlc_net_1676 ) , .p1657 ( optlc_net_1677 ) ,
+ .p1658 ( optlc_net_1678 ) , .p1659 ( optlc_net_1679 ) ,
+ .p1660 ( optlc_net_1680 ) , .p1661 ( optlc_net_1681 ) ,
+ .p1662 ( optlc_net_1682 ) , .p1663 ( optlc_net_1683 ) ,
+ .p1664 ( optlc_net_1684 ) , .p1665 ( optlc_net_1685 ) ,
+ .p1666 ( optlc_net_1686 ) , .p1667 ( optlc_net_1687 ) ,
+ .p1668 ( optlc_net_1688 ) , .p1669 ( optlc_net_1689 ) ,
+ .p1670 ( optlc_net_1690 ) , .p1671 ( optlc_net_1691 ) ,
+ .p1672 ( optlc_net_1692 ) , .p1673 ( optlc_net_1693 ) ,
+ .p1674 ( optlc_net_1694 ) , .p1675 ( optlc_net_1695 ) ,
+ .p1676 ( optlc_net_1696 ) , .p1677 ( optlc_net_1697 ) ,
+ .p1678 ( optlc_net_1698 ) , .p1679 ( optlc_net_1699 ) ,
+ .p1680 ( optlc_net_1700 ) , .p1681 ( optlc_net_1701 ) ,
+ .p1682 ( optlc_net_1702 ) , .p1683 ( optlc_net_1703 ) ,
+ .p1684 ( optlc_net_1704 ) , .p1685 ( optlc_net_1705 ) ,
+ .p1686 ( optlc_net_1706 ) , .p1687 ( optlc_net_1707 ) ,
+ .p1688 ( optlc_net_1708 ) , .p1689 ( optlc_net_1709 ) ,
+ .p1690 ( optlc_net_1710 ) , .p1691 ( optlc_net_1711 ) ,
+ .p1692 ( optlc_net_1712 ) , .p1693 ( optlc_net_1713 ) ,
+ .p1694 ( optlc_net_1714 ) , .p1695 ( optlc_net_1715 ) ,
+ .p1696 ( optlc_net_1716 ) , .p1697 ( optlc_net_1717 ) ,
+ .p1698 ( optlc_net_1718 ) , .p1699 ( optlc_net_1719 ) ,
+ .p1700 ( optlc_net_1720 ) , .p1701 ( optlc_net_1721 ) ,
+ .p1702 ( optlc_net_1722 ) , .p1703 ( optlc_net_1723 ) ,
+ .p1704 ( optlc_net_1724 ) , .p1705 ( optlc_net_1725 ) ,
+ .p1706 ( optlc_net_1726 ) , .p1707 ( optlc_net_1727 ) ,
+ .p1708 ( optlc_net_1728 ) , .p1709 ( optlc_net_1729 ) ,
+ .p1710 ( optlc_net_1730 ) , .p1711 ( optlc_net_1731 ) ,
+ .p1712 ( optlc_net_1732 ) , .p1713 ( optlc_net_1733 ) ,
+ .p1714 ( optlc_net_1734 ) , .p1715 ( optlc_net_1735 ) ,
+ .p1716 ( optlc_net_1736 ) , .p1717 ( optlc_net_1737 ) ,
+ .p1718 ( optlc_net_1738 ) , .p1719 ( optlc_net_1739 ) ,
+ .p1720 ( optlc_net_1740 ) , .p1721 ( optlc_net_1741 ) ,
+ .p1722 ( optlc_net_1742 ) , .p1723 ( optlc_net_1743 ) ,
+ .p1724 ( optlc_net_1744 ) , .p1725 ( optlc_net_1745 ) ,
+ .p1726 ( optlc_net_1746 ) , .p1727 ( optlc_net_1747 ) ,
+ .p1728 ( optlc_net_1748 ) , .p1729 ( optlc_net_1749 ) ,
+ .p1730 ( optlc_net_1750 ) , .p1731 ( optlc_net_1751 ) ,
+ .p1732 ( optlc_net_1752 ) , .p1733 ( optlc_net_1753 ) ,
+ .p1734 ( optlc_net_1754 ) , .p1735 ( optlc_net_1755 ) ,
+ .p1736 ( optlc_net_1756 ) , .p1737 ( optlc_net_1757 ) ,
+ .p1738 ( optlc_net_1758 ) , .p1739 ( optlc_net_1759 ) ,
+ .p1740 ( optlc_net_1760 ) , .p1741 ( optlc_net_1761 ) ,
+ .p1742 ( optlc_net_1762 ) , .p1743 ( optlc_net_1763 ) ,
+ .p1744 ( optlc_net_1764 ) , .p1745 ( optlc_net_1765 ) ,
+ .p1746 ( optlc_net_1766 ) , .p1747 ( optlc_net_1767 ) ,
+ .p1748 ( optlc_net_1768 ) , .p1749 ( optlc_net_1769 ) ,
+ .p1750 ( optlc_net_1770 ) , .p1751 ( optlc_net_1771 ) ,
+ .p1752 ( optlc_net_1772 ) , .p1753 ( optlc_net_1773 ) ,
+ .p1754 ( optlc_net_1774 ) , .p1755 ( optlc_net_1775 ) ,
+ .p1756 ( optlc_net_1776 ) , .p1757 ( optlc_net_1777 ) ,
+ .p1758 ( optlc_net_1778 ) , .p1759 ( optlc_net_1779 ) ,
+ .p1760 ( optlc_net_1780 ) , .p1761 ( optlc_net_1781 ) ,
+ .p1762 ( optlc_net_1782 ) , .p1763 ( optlc_net_1783 ) ,
+ .p1764 ( optlc_net_1784 ) , .p1765 ( optlc_net_1785 ) ,
+ .p1766 ( optlc_net_1786 ) , .p1767 ( optlc_net_1787 ) ,
+ .p1768 ( optlc_net_1788 ) , .p1769 ( optlc_net_1789 ) ,
+ .p1770 ( optlc_net_1790 ) , .p1771 ( optlc_net_1791 ) ,
+ .p1772 ( optlc_net_1792 ) , .p1773 ( optlc_net_1793 ) ,
+ .p1774 ( optlc_net_1794 ) , .p1775 ( optlc_net_1795 ) ,
+ .p1776 ( optlc_net_1796 ) , .p1777 ( optlc_net_1797 ) ,
+ .p1778 ( optlc_net_1798 ) , .p1779 ( optlc_net_1799 ) ,
+ .p1780 ( optlc_net_1800 ) , .p1781 ( optlc_net_1801 ) ,
+ .p1782 ( optlc_net_1802 ) , .p1783 ( optlc_net_1803 ) ,
+ .p1784 ( optlc_net_1804 ) , .p1785 ( optlc_net_1805 ) ,
+ .p1786 ( optlc_net_1806 ) , .p1787 ( optlc_net_1807 ) ,
+ .p1788 ( optlc_net_1808 ) , .p1789 ( optlc_net_1809 ) ,
+ .p1790 ( optlc_net_1810 ) , .p1791 ( optlc_net_1811 ) ,
+ .p1792 ( optlc_net_1812 ) , .p1793 ( optlc_net_1813 ) ,
+ .p1794 ( optlc_net_1814 ) , .p1795 ( optlc_net_1815 ) ,
+ .p1796 ( optlc_net_1816 ) , .p1797 ( optlc_net_1817 ) ,
+ .p1798 ( optlc_net_1818 ) , .p1799 ( optlc_net_1819 ) ,
+ .p1800 ( optlc_net_1820 ) , .p1801 ( optlc_net_1821 ) ,
+ .p1802 ( optlc_net_1822 ) , .p1803 ( optlc_net_1823 ) ,
+ .p1804 ( optlc_net_1824 ) , .p1805 ( optlc_net_1825 ) ,
+ .p1806 ( optlc_net_1826 ) , .p1807 ( optlc_net_1827 ) ,
+ .p1808 ( optlc_net_1828 ) , .p1809 ( optlc_net_1829 ) ,
+ .p1810 ( optlc_net_1830 ) , .p1811 ( optlc_net_1831 ) ,
+ .p1812 ( optlc_net_1832 ) , .p1813 ( optlc_net_1833 ) ,
+ .p1814 ( optlc_net_1834 ) , .p1815 ( optlc_net_1835 ) ,
+ .p1816 ( optlc_net_1836 ) , .p1817 ( optlc_net_1837 ) ,
+ .p1818 ( optlc_net_1838 ) , .p1819 ( optlc_net_1839 ) ,
+ .p1820 ( optlc_net_1840 ) , .p1821 ( optlc_net_1841 ) ,
+ .p1822 ( optlc_net_1842 ) , .p1823 ( optlc_net_1843 ) ,
+ .p1824 ( optlc_net_1844 ) , .p1825 ( optlc_net_1845 ) ,
+ .p1826 ( optlc_net_1846 ) , .p1827 ( optlc_net_1847 ) ,
+ .p1828 ( optlc_net_1848 ) , .p1829 ( optlc_net_1849 ) ,
+ .p1830 ( optlc_net_1850 ) , .p1831 ( optlc_net_1851 ) ,
+ .p1832 ( optlc_net_1852 ) , .p1833 ( optlc_net_1853 ) ,
+ .p1834 ( optlc_net_1854 ) , .p1835 ( optlc_net_1855 ) ,
+ .p1836 ( optlc_net_1856 ) , .p1837 ( optlc_net_1857 ) ,
+ .p1838 ( optlc_net_1858 ) , .p1839 ( optlc_net_1859 ) ,
+ .p1840 ( optlc_net_1860 ) , .p1841 ( optlc_net_1861 ) ,
+ .p1842 ( optlc_net_1862 ) , .p1843 ( optlc_net_1863 ) ,
+ .p1844 ( optlc_net_1864 ) , .p1845 ( optlc_net_1865 ) ,
+ .p1846 ( optlc_net_1866 ) , .p1847 ( optlc_net_1867 ) ,
+ .p1848 ( optlc_net_1868 ) , .p1849 ( optlc_net_1869 ) ,
+ .p1850 ( optlc_net_1870 ) , .p1851 ( optlc_net_1871 ) ,
+ .p1852 ( optlc_net_1872 ) , .p1853 ( optlc_net_1873 ) ,
+ .p1854 ( optlc_net_1874 ) , .p1855 ( optlc_net_1875 ) ,
+ .p1856 ( optlc_net_1876 ) , .p1857 ( optlc_net_1877 ) ,
+ .p1858 ( optlc_net_1878 ) , .p1859 ( optlc_net_1879 ) ,
+ .p1860 ( optlc_net_1880 ) , .p1861 ( optlc_net_1881 ) ,
+ .p1862 ( optlc_net_1882 ) , .p1863 ( optlc_net_1883 ) ,
+ .p1864 ( optlc_net_1884 ) , .p1865 ( optlc_net_1885 ) ,
+ .p1866 ( optlc_net_1886 ) , .p1867 ( optlc_net_1887 ) ,
+ .p1868 ( optlc_net_1888 ) , .p1869 ( optlc_net_1889 ) ,
+ .p1870 ( optlc_net_1890 ) , .p1871 ( optlc_net_1891 ) ,
+ .p1872 ( optlc_net_1892 ) , .p1873 ( optlc_net_1893 ) ,
+ .p1874 ( optlc_net_1894 ) , .p1875 ( optlc_net_1895 ) ,
+ .p1876 ( optlc_net_1896 ) , .p1877 ( optlc_net_1897 ) ,
+ .p1878 ( optlc_net_1898 ) , .p1879 ( optlc_net_1899 ) ,
+ .p1880 ( optlc_net_1900 ) , .p1881 ( optlc_net_1901 ) ,
+ .p1882 ( optlc_net_1902 ) , .p1883 ( optlc_net_1903 ) ,
+ .p1884 ( optlc_net_1904 ) , .p1885 ( optlc_net_1905 ) ,
+ .p1886 ( optlc_net_1906 ) , .p1887 ( optlc_net_1907 ) ,
+ .p1888 ( optlc_net_1908 ) , .p1889 ( optlc_net_1909 ) ,
+ .p1890 ( optlc_net_1910 ) , .p1891 ( optlc_net_1911 ) ,
+ .p1892 ( optlc_net_1912 ) , .p1893 ( optlc_net_1913 ) ,
+ .p1894 ( optlc_net_1914 ) , .p1895 ( optlc_net_1915 ) ,
+ .p1896 ( optlc_net_1916 ) , .p1897 ( optlc_net_1917 ) ,
+ .p1898 ( optlc_net_1918 ) , .p1899 ( optlc_net_1919 ) ,
+ .p1900 ( optlc_net_1920 ) , .p1901 ( optlc_net_1921 ) ,
+ .p1902 ( optlc_net_1922 ) , .p1903 ( optlc_net_1923 ) ,
+ .p1904 ( optlc_net_1924 ) , .p1905 ( optlc_net_1925 ) ,
+ .p1906 ( optlc_net_1926 ) , .p1907 ( optlc_net_1927 ) ,
+ .p1908 ( optlc_net_1928 ) , .p1909 ( optlc_net_1929 ) ,
+ .p1910 ( optlc_net_1930 ) , .p1911 ( optlc_net_1931 ) ,
+ .p1912 ( optlc_net_1932 ) , .p1913 ( optlc_net_1933 ) ,
+ .p1914 ( optlc_net_1934 ) , .p1915 ( optlc_net_1935 ) ,
+ .p1916 ( optlc_net_1936 ) , .p1917 ( optlc_net_1937 ) ,
+ .p1918 ( optlc_net_1938 ) , .p1919 ( optlc_net_1939 ) ,
+ .p1920 ( optlc_net_1940 ) , .p1921 ( optlc_net_1941 ) ,
+ .p1922 ( optlc_net_1942 ) , .p1923 ( optlc_net_1943 ) ,
+ .p1924 ( optlc_net_1944 ) , .p1925 ( optlc_net_1945 ) ,
+ .p1926 ( optlc_net_1946 ) , .p1927 ( optlc_net_1947 ) ,
+ .p1928 ( optlc_net_1948 ) , .p1929 ( optlc_net_1949 ) ,
+ .p1930 ( optlc_net_1950 ) , .p1931 ( optlc_net_1951 ) ,
+ .p1932 ( optlc_net_1952 ) , .p1933 ( optlc_net_1953 ) ,
+ .p1934 ( optlc_net_1954 ) , .p1935 ( optlc_net_1955 ) ,
+ .p1936 ( optlc_net_1956 ) , .p1937 ( optlc_net_1957 ) ,
+ .p1938 ( optlc_net_1958 ) , .p1939 ( optlc_net_1959 ) ,
+ .p1940 ( optlc_net_1960 ) , .p1941 ( optlc_net_1961 ) ,
+ .p1942 ( optlc_net_1962 ) , .p1943 ( optlc_net_1963 ) ,
+ .p1944 ( optlc_net_1964 ) , .p1945 ( optlc_net_1965 ) ,
+ .p1946 ( optlc_net_1966 ) , .p1947 ( optlc_net_1967 ) ,
+ .p1948 ( optlc_net_1968 ) , .p1949 ( optlc_net_1969 ) ,
+ .p1950 ( optlc_net_1970 ) , .p1951 ( optlc_net_1971 ) ,
+ .p1952 ( optlc_net_1972 ) , .p1953 ( optlc_net_1973 ) ,
+ .p1954 ( optlc_net_1974 ) , .p1955 ( optlc_net_1975 ) ,
+ .p1956 ( optlc_net_1976 ) , .p1957 ( optlc_net_1977 ) ,
+ .p1958 ( optlc_net_1978 ) , .p1959 ( optlc_net_1979 ) ,
+ .p1960 ( optlc_net_1980 ) , .p1961 ( optlc_net_1981 ) ,
+ .p1962 ( optlc_net_1982 ) , .p1963 ( optlc_net_1983 ) ,
+ .p1964 ( optlc_net_1984 ) , .p1965 ( optlc_net_1985 ) ,
+ .p1966 ( optlc_net_1986 ) , .p1967 ( optlc_net_1987 ) ,
+ .p1968 ( optlc_net_1988 ) , .p1969 ( optlc_net_1989 ) ,
+ .p1970 ( optlc_net_1990 ) , .p1971 ( optlc_net_1991 ) ,
+ .p1972 ( optlc_net_1992 ) , .p1973 ( optlc_net_1993 ) ,
+ .p1974 ( optlc_net_1994 ) , .p1975 ( optlc_net_1995 ) ,
+ .p1976 ( optlc_net_1996 ) , .p1977 ( optlc_net_1997 ) ,
+ .p1978 ( optlc_net_1998 ) , .p1979 ( optlc_net_1999 ) ,
+ .p1980 ( optlc_net_2000 ) , .p1981 ( optlc_net_2001 ) ,
+ .p1982 ( optlc_net_2002 ) , .p1983 ( optlc_net_2003 ) ,
+ .p1984 ( optlc_net_2004 ) , .p1985 ( optlc_net_2005 ) ,
+ .p1986 ( optlc_net_2006 ) , .p1987 ( optlc_net_2007 ) ,
+ .p1988 ( optlc_net_2008 ) , .p1989 ( optlc_net_2009 ) ,
+ .p1990 ( optlc_net_2010 ) , .p1991 ( optlc_net_2011 ) ,
+ .p1992 ( optlc_net_2012 ) , .p1993 ( optlc_net_2013 ) ,
+ .p1994 ( optlc_net_2014 ) , .p1995 ( optlc_net_2015 ) ,
+ .p1996 ( optlc_net_2016 ) , .p1997 ( optlc_net_2017 ) ,
+ .p1998 ( optlc_net_2018 ) , .p1999 ( optlc_net_2019 ) ,
+ .p2000 ( optlc_net_2020 ) , .p2001 ( optlc_net_2021 ) ,
+ .p2002 ( optlc_net_2022 ) , .p2003 ( optlc_net_2023 ) ,
+ .p2004 ( optlc_net_2024 ) , .p2005 ( optlc_net_2025 ) ,
+ .p2006 ( optlc_net_2026 ) , .p2007 ( optlc_net_2027 ) ,
+ .p2008 ( optlc_net_2028 ) , .p2009 ( optlc_net_2029 ) ,
+ .p2010 ( optlc_net_2030 ) , .p2011 ( optlc_net_2031 ) ,
+ .p2012 ( optlc_net_2032 ) , .p2013 ( optlc_net_2033 ) ,
+ .p2014 ( optlc_net_2034 ) , .p2015 ( optlc_net_2035 ) ,
+ .p2016 ( optlc_net_2036 ) , .p2017 ( optlc_net_2037 ) ,
+ .p2018 ( optlc_net_2038 ) , .p2019 ( optlc_net_2039 ) ,
+ .p2020 ( optlc_net_2040 ) , .p2021 ( optlc_net_2041 ) ,
+ .p2022 ( optlc_net_2042 ) , .p2023 ( optlc_net_2043 ) ,
+ .p2024 ( optlc_net_2044 ) , .p2025 ( optlc_net_2045 ) ,
+ .p2026 ( optlc_net_2046 ) , .p2027 ( optlc_net_2047 ) ,
+ .p2028 ( optlc_net_2048 ) , .p2029 ( optlc_net_2049 ) ,
+ .p2030 ( optlc_net_2050 ) , .p2031 ( optlc_net_2051 ) ,
+ .p2032 ( optlc_net_2052 ) , .p2033 ( optlc_net_2053 ) ,
+ .p2034 ( optlc_net_2054 ) , .p2035 ( optlc_net_2055 ) ,
+ .p2036 ( optlc_net_2056 ) , .p2037 ( optlc_net_2057 ) ,
+ .p2038 ( optlc_net_2058 ) , .p2039 ( optlc_net_2059 ) ,
+ .p2040 ( optlc_net_2060 ) , .p2041 ( optlc_net_2061 ) ,
+ .p2042 ( optlc_net_2062 ) , .p2043 ( optlc_net_2063 ) ,
+ .p2044 ( optlc_net_2064 ) , .p2045 ( optlc_net_2065 ) ,
+ .p2046 ( optlc_net_2066 ) , .p2047 ( optlc_net_2067 ) ,
+ .p2048 ( optlc_net_2068 ) , .p2049 ( optlc_net_2069 ) ,
+ .p2050 ( optlc_net_2070 ) , .p2051 ( optlc_net_2071 ) ,
+ .p2052 ( optlc_net_2072 ) , .p2053 ( optlc_net_2073 ) ,
+ .p2054 ( optlc_net_2074 ) , .p2055 ( optlc_net_2075 ) ,
+ .p2056 ( optlc_net_2076 ) , .p2057 ( optlc_net_2077 ) ,
+ .p2058 ( optlc_net_2078 ) , .p2059 ( optlc_net_2079 ) ,
+ .p2060 ( optlc_net_2080 ) , .p2061 ( optlc_net_2081 ) ,
+ .p2062 ( optlc_net_2082 ) , .p2063 ( optlc_net_2083 ) ,
+ .p2064 ( optlc_net_2084 ) , .p2065 ( optlc_net_2085 ) ,
+ .p2066 ( optlc_net_2086 ) , .p2067 ( optlc_net_2087 ) ,
+ .p2068 ( optlc_net_2088 ) , .p2069 ( optlc_net_2089 ) ,
+ .p2070 ( optlc_net_2090 ) , .p2071 ( optlc_net_2091 ) ,
+ .p2072 ( optlc_net_2092 ) , .p2073 ( optlc_net_2093 ) ,
+ .p2074 ( optlc_net_2094 ) , .p2075 ( optlc_net_2095 ) ,
+ .p2076 ( optlc_net_2096 ) , .p2077 ( optlc_net_2097 ) ,
+ .p2078 ( optlc_net_2098 ) , .p2079 ( optlc_net_2099 ) ,
+ .p2080 ( optlc_net_2100 ) , .p2081 ( optlc_net_2101 ) ,
+ .p2082 ( optlc_net_2102 ) , .p2083 ( optlc_net_2103 ) ,
+ .p2084 ( optlc_net_2104 ) , .p2085 ( optlc_net_2105 ) ,
+ .p2086 ( optlc_net_2106 ) , .p2087 ( optlc_net_2107 ) ,
+ .p2088 ( optlc_net_2108 ) , .p2089 ( optlc_net_2109 ) ,
+ .p2090 ( optlc_net_2110 ) , .p2091 ( optlc_net_2111 ) ,
+ .p2092 ( optlc_net_2112 ) , .p2093 ( optlc_net_2113 ) ,
+ .p2094 ( optlc_net_2114 ) , .p2095 ( optlc_net_2115 ) ,
+ .p2096 ( optlc_net_2116 ) , .p2097 ( optlc_net_2117 ) ,
+ .p2098 ( optlc_net_2118 ) , .p2099 ( optlc_net_2119 ) ,
+ .p2100 ( optlc_net_2120 ) , .p2101 ( optlc_net_2121 ) ,
+ .p2102 ( optlc_net_2122 ) , .p2103 ( optlc_net_2123 ) ,
+ .p2104 ( optlc_net_2124 ) , .p2105 ( optlc_net_2125 ) ,
+ .p2106 ( optlc_net_2126 ) , .p2107 ( optlc_net_2127 ) ,
+ .p2108 ( optlc_net_2128 ) , .p2109 ( optlc_net_2129 ) ,
+ .p2110 ( optlc_net_2130 ) , .p2111 ( optlc_net_2131 ) ,
+ .p2112 ( optlc_net_2132 ) , .p2113 ( optlc_net_2133 ) ,
+ .p2114 ( optlc_net_2134 ) , .p2115 ( optlc_net_2135 ) ,
+ .p2116 ( optlc_net_2136 ) , .p2117 ( optlc_net_2137 ) ,
+ .p2118 ( optlc_net_2138 ) , .p2119 ( optlc_net_2139 ) ,
+ .p2120 ( optlc_net_2140 ) , .p2121 ( optlc_net_2141 ) ,
+ .p2122 ( optlc_net_2142 ) , .p2123 ( optlc_net_2143 ) ,
+ .p2124 ( optlc_net_2144 ) , .p2125 ( optlc_net_2145 ) ,
+ .p2126 ( optlc_net_2146 ) , .p2127 ( optlc_net_2147 ) ,
+ .p2128 ( optlc_net_2148 ) , .p2129 ( optlc_net_2149 ) ,
+ .p2130 ( optlc_net_2150 ) , .p2131 ( optlc_net_2151 ) ,
+ .p2132 ( optlc_net_2152 ) , .p2133 ( optlc_net_2153 ) ,
+ .p2134 ( optlc_net_2154 ) , .p2135 ( optlc_net_2155 ) ,
+ .p2136 ( optlc_net_2156 ) , .p2137 ( optlc_net_2157 ) ,
+ .p2138 ( optlc_net_2158 ) , .p2139 ( optlc_net_2159 ) ,
+ .p2140 ( optlc_net_2160 ) , .p2141 ( optlc_net_2161 ) ,
+ .p2142 ( optlc_net_2162 ) , .p2143 ( optlc_net_2163 ) ,
+ .p2144 ( optlc_net_2164 ) , .p2145 ( optlc_net_2165 ) ,
+ .p2146 ( optlc_net_2166 ) , .p2147 ( optlc_net_2167 ) ,
+ .p2148 ( optlc_net_2168 ) , .p2149 ( optlc_net_2169 ) ,
+ .p2150 ( optlc_net_2170 ) , .p2151 ( optlc_net_2171 ) ,
+ .p2152 ( optlc_net_2172 ) , .p2153 ( optlc_net_2173 ) ,
+ .p2154 ( optlc_net_2174 ) , .p2155 ( optlc_net_2175 ) ,
+ .p2156 ( optlc_net_2176 ) , .p2157 ( optlc_net_2177 ) ,
+ .p2158 ( optlc_net_2178 ) , .p2159 ( optlc_net_2179 ) ,
+ .p2160 ( optlc_net_2180 ) , .p2161 ( optlc_net_2181 ) ,
+ .p2162 ( optlc_net_2182 ) , .p2163 ( optlc_net_2183 ) ,
+ .p2164 ( optlc_net_2184 ) , .p2165 ( optlc_net_2185 ) ,
+ .p2166 ( optlc_net_2186 ) , .p2167 ( optlc_net_2187 ) ,
+ .p2168 ( optlc_net_2188 ) , .p2169 ( optlc_net_2189 ) ,
+ .p2170 ( optlc_net_2190 ) , .p2171 ( optlc_net_2191 ) ,
+ .p2172 ( optlc_net_2192 ) , .p2173 ( optlc_net_2193 ) ,
+ .p2174 ( optlc_net_2194 ) , .p2175 ( optlc_net_2195 ) ,
+ .p2176 ( optlc_net_2196 ) , .p2177 ( optlc_net_2197 ) ,
+ .p2178 ( optlc_net_2198 ) , .p2179 ( optlc_net_2199 ) ,
+ .p2180 ( optlc_net_2200 ) , .p2181 ( optlc_net_2201 ) ,
+ .p2182 ( optlc_net_2202 ) , .p2183 ( optlc_net_2203 ) ,
+ .p2184 ( optlc_net_2204 ) , .p2185 ( optlc_net_2205 ) ,
+ .p2186 ( optlc_net_2206 ) , .p2187 ( optlc_net_2207 ) ,
+ .p2188 ( optlc_net_2208 ) , .p2189 ( optlc_net_2209 ) ,
+ .p2190 ( optlc_net_2210 ) , .p2191 ( optlc_net_2211 ) ,
+ .p2192 ( optlc_net_2212 ) , .p2193 ( optlc_net_2213 ) ,
+ .p2194 ( optlc_net_2214 ) , .p2195 ( optlc_net_2215 ) ,
+ .p2196 ( optlc_net_2216 ) , .p2197 ( optlc_net_2217 ) ,
+ .p2198 ( optlc_net_2218 ) , .p2199 ( optlc_net_2219 ) ,
+ .p2200 ( optlc_net_2220 ) , .p2201 ( optlc_net_2221 ) ,
+ .p2202 ( optlc_net_2222 ) , .p2203 ( optlc_net_2223 ) ,
+ .p2204 ( optlc_net_2224 ) , .p2205 ( optlc_net_2225 ) ,
+ .p2206 ( optlc_net_2226 ) , .p2207 ( optlc_net_2227 ) ,
+ .p2208 ( optlc_net_2228 ) , .p2209 ( optlc_net_2229 ) ,
+ .p2210 ( optlc_net_2230 ) , .p2211 ( optlc_net_2231 ) ,
+ .p2212 ( optlc_net_2232 ) , .p2213 ( optlc_net_2233 ) ,
+ .p2214 ( optlc_net_2234 ) , .p2215 ( optlc_net_2235 ) ,
+ .p2216 ( optlc_net_2236 ) , .p2217 ( optlc_net_2237 ) ,
+ .p2218 ( optlc_net_2238 ) , .p2219 ( optlc_net_2239 ) ,
+ .p2220 ( optlc_net_2240 ) , .p2221 ( optlc_net_2241 ) ,
+ .p2222 ( optlc_net_2242 ) , .p2223 ( optlc_net_2243 ) ,
+ .p2224 ( optlc_net_2244 ) , .p2225 ( optlc_net_2245 ) ,
+ .p2226 ( optlc_net_2246 ) , .p2227 ( optlc_net_2247 ) ,
+ .p2228 ( optlc_net_2248 ) , .p2229 ( optlc_net_2249 ) ,
+ .p2230 ( optlc_net_2250 ) , .p2231 ( optlc_net_2251 ) ,
+ .p2232 ( optlc_net_2252 ) , .p2233 ( optlc_net_2253 ) ,
+ .p2234 ( optlc_net_2254 ) , .p2235 ( optlc_net_2255 ) ,
+ .p2236 ( optlc_net_2256 ) , .p2237 ( optlc_net_2257 ) ,
+ .p2238 ( optlc_net_2258 ) , .p2239 ( optlc_net_2259 ) ,
+ .p2240 ( optlc_net_2260 ) , .p2241 ( optlc_net_2261 ) ,
+ .p2242 ( optlc_net_2262 ) , .p2243 ( optlc_net_2263 ) ,
+ .p2244 ( optlc_net_2264 ) , .p2245 ( optlc_net_2265 ) ,
+ .p2246 ( optlc_net_2266 ) , .p2247 ( optlc_net_2267 ) ,
+ .p2248 ( optlc_net_2268 ) , .p2249 ( optlc_net_2269 ) ,
+ .p2250 ( optlc_net_2270 ) , .p2251 ( optlc_net_2271 ) ,
+ .p2252 ( optlc_net_2272 ) , .p2253 ( optlc_net_2273 ) ,
+ .p2254 ( optlc_net_2274 ) , .p2255 ( optlc_net_2275 ) ,
+ .p2256 ( optlc_net_2276 ) , .p2257 ( optlc_net_2277 ) ,
+ .p2258 ( optlc_net_2278 ) , .p2259 ( optlc_net_2279 ) ,
+ .p2260 ( optlc_net_2280 ) , .p2261 ( optlc_net_2281 ) ,
+ .p2262 ( optlc_net_2282 ) , .p2263 ( optlc_net_2283 ) ,
+ .p2264 ( optlc_net_2284 ) , .p2265 ( optlc_net_2285 ) ,
+ .p2266 ( optlc_net_2286 ) , .p2267 ( optlc_net_2287 ) ,
+ .p2268 ( optlc_net_2288 ) , .p2269 ( optlc_net_2289 ) ,
+ .p2270 ( optlc_net_2290 ) , .p2271 ( optlc_net_2291 ) ,
+ .p2272 ( optlc_net_2292 ) , .p2273 ( optlc_net_2293 ) ,
+ .p2274 ( optlc_net_2294 ) , .p2275 ( optlc_net_2295 ) ,
+ .p2276 ( optlc_net_2296 ) , .p2277 ( optlc_net_2297 ) ,
+ .p2278 ( optlc_net_2298 ) , .p2279 ( optlc_net_2299 ) ,
+ .p2280 ( optlc_net_2300 ) , .p2281 ( optlc_net_2301 ) ,
+ .p2282 ( optlc_net_2302 ) , .p2283 ( optlc_net_2303 ) ,
+ .p2284 ( optlc_net_2304 ) , .p2285 ( optlc_net_2305 ) ,
+ .p2286 ( optlc_net_2306 ) , .p2287 ( optlc_net_2307 ) ,
+ .p2288 ( optlc_net_2308 ) , .p2289 ( optlc_net_2309 ) ,
+ .p2290 ( optlc_net_2310 ) , .p2291 ( optlc_net_2311 ) ,
+ .p2292 ( optlc_net_2312 ) , .p2293 ( optlc_net_2313 ) ,
+ .p2294 ( optlc_net_2314 ) , .p2295 ( optlc_net_2315 ) ,
+ .p2296 ( optlc_net_2316 ) , .p2297 ( optlc_net_2317 ) ,
+ .p2298 ( optlc_net_2318 ) , .p2299 ( optlc_net_2319 ) ,
+ .p2300 ( optlc_net_2320 ) , .p2301 ( optlc_net_2321 ) ,
+ .p2302 ( optlc_net_2322 ) , .p2303 ( optlc_net_2323 ) ,
+ .p2304 ( optlc_net_2324 ) , .p2305 ( optlc_net_2325 ) ,
+ .p2306 ( optlc_net_2326 ) , .p2307 ( optlc_net_2327 ) ,
+ .p2308 ( optlc_net_2328 ) , .p2309 ( optlc_net_2329 ) ,
+ .p2310 ( optlc_net_2330 ) , .p2311 ( optlc_net_2331 ) ,
+ .p2312 ( optlc_net_2332 ) , .p2313 ( optlc_net_2333 ) ,
+ .p2314 ( optlc_net_2334 ) , .p2315 ( optlc_net_2335 ) ,
+ .p2316 ( optlc_net_2336 ) , .p2317 ( optlc_net_2337 ) ,
+ .p2318 ( optlc_net_2338 ) , .p2319 ( optlc_net_2339 ) ,
+ .p2320 ( optlc_net_2340 ) , .p2321 ( optlc_net_2341 ) ,
+ .p2322 ( optlc_net_2342 ) , .p2323 ( optlc_net_2343 ) ,
+ .p2324 ( optlc_net_2344 ) , .p2325 ( optlc_net_2345 ) ,
+ .p2326 ( optlc_net_2346 ) , .p2327 ( optlc_net_2347 ) ,
+ .p2328 ( optlc_net_2348 ) , .p2329 ( optlc_net_2349 ) ,
+ .p2330 ( optlc_net_2350 ) , .p2331 ( optlc_net_2351 ) ,
+ .p2332 ( optlc_net_2352 ) , .p2333 ( optlc_net_2353 ) ,
+ .p2334 ( optlc_net_2354 ) , .p2335 ( optlc_net_2355 ) ,
+ .p2336 ( optlc_net_2356 ) , .p2337 ( optlc_net_2357 ) ,
+ .p2338 ( optlc_net_2358 ) , .p2339 ( optlc_net_2359 ) ,
+ .p2340 ( optlc_net_2360 ) , .p2341 ( optlc_net_2361 ) ,
+ .p2342 ( optlc_net_2362 ) , .p2343 ( optlc_net_2363 ) ,
+ .p2344 ( optlc_net_2364 ) , .p2345 ( optlc_net_2365 ) ,
+ .p2346 ( optlc_net_2366 ) , .p2347 ( optlc_net_2367 ) ,
+ .p2348 ( optlc_net_2368 ) , .p2349 ( optlc_net_2369 ) ,
+ .p2350 ( optlc_net_2370 ) , .p2351 ( optlc_net_2371 ) ,
+ .p2352 ( optlc_net_2372 ) , .p2353 ( optlc_net_2373 ) ,
+ .p2354 ( optlc_net_2374 ) , .p2355 ( optlc_net_2375 ) ,
+ .p2356 ( optlc_net_2376 ) , .p2357 ( optlc_net_2377 ) ,
+ .p2358 ( optlc_net_2378 ) , .p2359 ( optlc_net_2379 ) ,
+ .p2360 ( optlc_net_2380 ) , .p2361 ( optlc_net_2381 ) ,
+ .p2362 ( optlc_net_2382 ) , .p2363 ( optlc_net_2383 ) ,
+ .p2364 ( optlc_net_2384 ) , .p2365 ( optlc_net_2385 ) ,
+ .p2366 ( optlc_net_2386 ) , .p2367 ( optlc_net_2387 ) ,
+ .p2368 ( optlc_net_2388 ) , .p2369 ( optlc_net_2389 ) ,
+ .p2370 ( optlc_net_2390 ) , .p2371 ( optlc_net_2391 ) ,
+ .p2372 ( optlc_net_2392 ) , .p2373 ( optlc_net_2393 ) ,
+ .p2374 ( optlc_net_2394 ) , .p2375 ( optlc_net_2395 ) ,
+ .p2376 ( optlc_net_2396 ) , .p2377 ( optlc_net_2397 ) ,
+ .p2378 ( optlc_net_2398 ) , .p2379 ( optlc_net_2399 ) ,
+ .p2380 ( optlc_net_2400 ) , .p2381 ( optlc_net_2401 ) ,
+ .p2382 ( optlc_net_2402 ) , .p2383 ( optlc_net_2403 ) ,
+ .p2384 ( optlc_net_2404 ) , .p2385 ( optlc_net_2405 ) ,
+ .p2386 ( optlc_net_2406 ) , .p2387 ( optlc_net_2407 ) ,
+ .p2388 ( optlc_net_2408 ) , .p2389 ( optlc_net_2409 ) ,
+ .p2390 ( optlc_net_2410 ) , .p2391 ( optlc_net_2411 ) ,
+ .p2392 ( optlc_net_2412 ) , .p2393 ( optlc_net_2413 ) ,
+ .p2394 ( optlc_net_2414 ) , .p2395 ( optlc_net_2415 ) ,
+ .p2396 ( optlc_net_2416 ) , .p2397 ( optlc_net_2417 ) ,
+ .p2398 ( optlc_net_2418 ) , .p2399 ( optlc_net_2419 ) ,
+ .p2400 ( optlc_net_2420 ) , .p2401 ( optlc_net_2421 ) ,
+ .p2402 ( optlc_net_2422 ) , .p2403 ( optlc_net_2423 ) ,
+ .p2404 ( optlc_net_2424 ) , .p2405 ( optlc_net_2425 ) ,
+ .p2406 ( optlc_net_2426 ) , .p2407 ( optlc_net_2427 ) ,
+ .p2408 ( optlc_net_2428 ) , .p2409 ( optlc_net_2429 ) ,
+ .p2410 ( optlc_net_2430 ) , .p2411 ( optlc_net_2431 ) ,
+ .p2412 ( optlc_net_2432 ) , .p2413 ( optlc_net_2433 ) ,
+ .p2414 ( optlc_net_2434 ) , .p2415 ( optlc_net_2435 ) ,
+ .p2416 ( optlc_net_2436 ) , .p2417 ( optlc_net_2437 ) ,
+ .p2418 ( optlc_net_2438 ) , .p2419 ( optlc_net_2439 ) ,
+ .p2420 ( optlc_net_2440 ) , .p2421 ( optlc_net_2441 ) ,
+ .p2422 ( optlc_net_2442 ) , .p2423 ( optlc_net_2443 ) ,
+ .p2424 ( optlc_net_2444 ) , .p2425 ( optlc_net_2445 ) ,
+ .p2426 ( optlc_net_2446 ) , .p2427 ( optlc_net_2447 ) ,
+ .p2428 ( optlc_net_2448 ) , .p2429 ( optlc_net_2449 ) ,
+ .p2430 ( optlc_net_2450 ) , .p2431 ( optlc_net_2451 ) ,
+ .p2432 ( optlc_net_2452 ) , .p2433 ( optlc_net_2453 ) ,
+ .p2434 ( optlc_net_2454 ) , .p2435 ( optlc_net_2455 ) ,
+ .p2436 ( optlc_net_2456 ) , .p2437 ( optlc_net_2457 ) ,
+ .p2438 ( optlc_net_2458 ) , .p2439 ( optlc_net_2459 ) ,
+ .p2440 ( optlc_net_2460 ) , .p2441 ( optlc_net_2461 ) ,
+ .p2442 ( optlc_net_2462 ) , .p2443 ( optlc_net_2463 ) ,
+ .p2444 ( optlc_net_2464 ) , .p2445 ( optlc_net_2465 ) ,
+ .p2446 ( optlc_net_2466 ) , .p2447 ( optlc_net_2467 ) ,
+ .p2448 ( optlc_net_2468 ) , .p2449 ( optlc_net_2469 ) ,
+ .p2450 ( optlc_net_2470 ) , .p2451 ( optlc_net_2471 ) ,
+ .p2452 ( optlc_net_2472 ) , .p2453 ( optlc_net_2473 ) ,
+ .p2454 ( optlc_net_2474 ) , .p2455 ( optlc_net_2475 ) ,
+ .p2456 ( optlc_net_2476 ) , .p2457 ( optlc_net_2477 ) ,
+ .p2458 ( optlc_net_2478 ) , .p2459 ( optlc_net_2479 ) ,
+ .p2460 ( optlc_net_2480 ) , .p2461 ( optlc_net_2481 ) ,
+ .p2462 ( optlc_net_2482 ) , .p2463 ( optlc_net_2483 ) ,
+ .p2464 ( optlc_net_2484 ) , .p2465 ( optlc_net_2485 ) ,
+ .p2466 ( optlc_net_2486 ) , .p2467 ( optlc_net_2487 ) ,
+ .p2468 ( optlc_net_2488 ) , .p2469 ( optlc_net_2489 ) ,
+ .p2470 ( optlc_net_2490 ) , .p2471 ( optlc_net_2491 ) ,
+ .p2472 ( optlc_net_2492 ) , .p2473 ( optlc_net_2493 ) ,
+ .p2474 ( optlc_net_2494 ) , .p2475 ( optlc_net_2495 ) ,
+ .p2476 ( optlc_net_2496 ) , .p2477 ( optlc_net_2497 ) ,
+ .p2478 ( optlc_net_2498 ) , .p2479 ( optlc_net_2499 ) ,
+ .p2480 ( optlc_net_2500 ) , .p2481 ( optlc_net_2501 ) ,
+ .p2482 ( optlc_net_2502 ) , .p2483 ( optlc_net_2503 ) ,
+ .p2484 ( optlc_net_2504 ) , .p2485 ( optlc_net_2505 ) ,
+ .p2486 ( optlc_net_2506 ) , .p2487 ( optlc_net_2507 ) ,
+ .p2488 ( optlc_net_2508 ) , .p2489 ( optlc_net_2509 ) ,
+ .p2490 ( optlc_net_2510 ) , .p2491 ( optlc_net_2511 ) ,
+ .p2492 ( optlc_net_2512 ) , .p2493 ( optlc_net_2513 ) ,
+ .p2494 ( optlc_net_2514 ) , .p2495 ( optlc_net_2515 ) ,
+ .p2496 ( optlc_net_2516 ) , .p2497 ( optlc_net_2517 ) ,
+ .p2498 ( optlc_net_2518 ) , .p2499 ( optlc_net_2519 ) ,
+ .p2500 ( optlc_net_2520 ) , .p2501 ( optlc_net_2521 ) ,
+ .p2502 ( optlc_net_2522 ) , .p2503 ( optlc_net_2523 ) ,
+ .p2504 ( optlc_net_2524 ) , .p2505 ( optlc_net_2525 ) ,
+ .p2506 ( optlc_net_2526 ) , .p2507 ( optlc_net_2527 ) ,
+ .p2508 ( optlc_net_2528 ) , .p2509 ( optlc_net_2529 ) ,
+ .p2510 ( optlc_net_2530 ) , .p2511 ( optlc_net_2531 ) ,
+ .p2512 ( optlc_net_2532 ) , .p2513 ( optlc_net_2533 ) ,
+ .p2514 ( optlc_net_2534 ) , .p2515 ( optlc_net_2535 ) ,
+ .p2516 ( optlc_net_2536 ) , .p2517 ( optlc_net_2537 ) ,
+ .p2518 ( optlc_net_2538 ) , .p2519 ( optlc_net_2539 ) ,
+ .p2520 ( optlc_net_2540 ) , .p2521 ( optlc_net_2541 ) ,
+ .p2522 ( optlc_net_2542 ) , .p2523 ( optlc_net_2543 ) ,
+ .p2524 ( optlc_net_2544 ) , .p2525 ( optlc_net_2545 ) ,
+ .p2526 ( optlc_net_2546 ) , .p2527 ( optlc_net_2547 ) ,
+ .p2528 ( optlc_net_2548 ) , .p2529 ( optlc_net_2549 ) ,
+ .p2530 ( optlc_net_2550 ) , .p2531 ( optlc_net_2551 ) ,
+ .p2532 ( optlc_net_2552 ) , .p2533 ( optlc_net_2553 ) ,
+ .p2534 ( optlc_net_2554 ) , .p2535 ( optlc_net_2555 ) ,
+ .p2536 ( optlc_net_2556 ) , .p2537 ( optlc_net_2557 ) ,
+ .p2538 ( optlc_net_2558 ) , .p2539 ( optlc_net_2559 ) ,
+ .p2540 ( optlc_net_2560 ) , .p2541 ( optlc_net_2561 ) ,
+ .p2542 ( optlc_net_2562 ) , .p2543 ( optlc_net_2563 ) ,
+ .p2544 ( optlc_net_2564 ) , .p2545 ( optlc_net_2565 ) ,
+ .p2546 ( optlc_net_2566 ) , .p2547 ( optlc_net_2567 ) ,
+ .p2548 ( optlc_net_2568 ) , .p2549 ( optlc_net_2569 ) ,
+ .p2550 ( optlc_net_2570 ) , .p2551 ( optlc_net_2571 ) ,
+ .p2552 ( optlc_net_2572 ) , .p2553 ( optlc_net_2573 ) ,
+ .p2554 ( optlc_net_2574 ) , .p2555 ( optlc_net_2575 ) ,
+ .p2556 ( optlc_net_2576 ) , .p2557 ( optlc_net_2577 ) ,
+ .p2558 ( optlc_net_2578 ) , .p2559 ( optlc_net_2579 ) ,
+ .p2560 ( optlc_net_2580 ) , .p2561 ( optlc_net_2581 ) ,
+ .p2562 ( optlc_net_2582 ) , .p2563 ( optlc_net_2583 ) ,
+ .p2564 ( optlc_net_2584 ) , .p2565 ( optlc_net_2585 ) ,
+ .p2566 ( optlc_net_2586 ) , .p2567 ( optlc_net_2587 ) ,
+ .p2568 ( optlc_net_2588 ) , .p2569 ( optlc_net_2589 ) ,
+ .p2570 ( optlc_net_2590 ) , .p2571 ( optlc_net_2591 ) ,
+ .p2572 ( optlc_net_2592 ) , .p2573 ( optlc_net_2593 ) ,
+ .p2574 ( optlc_net_2594 ) , .p2575 ( optlc_net_2595 ) ,
+ .p2576 ( optlc_net_2596 ) , .p2577 ( optlc_net_2597 ) ,
+ .p2578 ( optlc_net_2598 ) , .p2579 ( optlc_net_2599 ) ,
+ .p2580 ( optlc_net_2600 ) , .p2581 ( optlc_net_2601 ) ,
+ .p2582 ( optlc_net_2602 ) , .p2583 ( optlc_net_2603 ) ,
+ .p2584 ( optlc_net_2604 ) , .p2585 ( optlc_net_2605 ) ,
+ .p2586 ( optlc_net_2606 ) , .p2587 ( optlc_net_2607 ) ,
+ .p2588 ( optlc_net_2608 ) , .p2589 ( optlc_net_2609 ) ,
+ .p2590 ( optlc_net_2610 ) , .p2591 ( optlc_net_2611 ) ,
+ .p2592 ( optlc_net_2612 ) , .p2593 ( optlc_net_2613 ) ,
+ .p2594 ( optlc_net_2614 ) , .p2595 ( optlc_net_2615 ) ,
+ .p2596 ( optlc_net_2616 ) , .p2597 ( optlc_net_2617 ) ,
+ .p2598 ( optlc_net_2618 ) , .p2599 ( optlc_net_2619 ) ,
+ .p2600 ( optlc_net_2620 ) , .p2601 ( optlc_net_2621 ) ,
+ .p2602 ( optlc_net_2622 ) , .p2603 ( optlc_net_2623 ) ,
+ .p2604 ( optlc_net_2624 ) , .p2605 ( optlc_net_2625 ) ,
+ .p2606 ( optlc_net_2626 ) , .p2607 ( optlc_net_2627 ) ,
+ .p2608 ( optlc_net_2628 ) , .p2609 ( optlc_net_2629 ) ,
+ .p2610 ( optlc_net_2630 ) , .p2611 ( optlc_net_2631 ) ,
+ .p2612 ( optlc_net_2632 ) , .p2613 ( optlc_net_2633 ) ,
+ .p2614 ( optlc_net_2634 ) , .p2615 ( optlc_net_2635 ) ,
+ .p2616 ( optlc_net_2636 ) , .p2617 ( optlc_net_2637 ) ,
+ .p2618 ( optlc_net_2638 ) , .p2619 ( optlc_net_2639 ) ,
+ .p2620 ( optlc_net_2640 ) , .p2621 ( optlc_net_2641 ) ,
+ .p2622 ( optlc_net_2642 ) , .p2623 ( optlc_net_2643 ) ,
+ .p2624 ( optlc_net_2644 ) , .p2625 ( optlc_net_2645 ) ,
+ .p2626 ( optlc_net_2646 ) , .p2627 ( optlc_net_2647 ) ,
+ .p2628 ( optlc_net_2648 ) , .p2629 ( optlc_net_2649 ) ,
+ .p2630 ( optlc_net_2650 ) , .p2631 ( optlc_net_2651 ) ,
+ .p2632 ( optlc_net_2652 ) , .p2633 ( optlc_net_2653 ) ,
+ .p2634 ( optlc_net_2654 ) , .p2635 ( optlc_net_2655 ) ,
+ .p2636 ( optlc_net_2656 ) , .p2637 ( optlc_net_2657 ) ,
+ .p2638 ( optlc_net_2658 ) , .p2639 ( optlc_net_2659 ) ,
+ .p2640 ( optlc_net_2660 ) , .p2641 ( optlc_net_2661 ) ,
+ .p2642 ( optlc_net_2662 ) , .p2643 ( optlc_net_2663 ) ,
+ .p2644 ( optlc_net_2664 ) , .p2645 ( optlc_net_2665 ) ,
+ .p2646 ( optlc_net_2666 ) , .p2647 ( optlc_net_2667 ) ,
+ .p2648 ( optlc_net_2668 ) , .p2649 ( optlc_net_2669 ) ,
+ .p2650 ( optlc_net_2670 ) , .p2651 ( optlc_net_2671 ) ,
+ .p2652 ( optlc_net_2672 ) , .p2653 ( optlc_net_2673 ) ,
+ .p2654 ( optlc_net_2674 ) , .p2655 ( optlc_net_2675 ) ,
+ .p2656 ( optlc_net_2676 ) , .p2657 ( optlc_net_2677 ) ,
+ .p2658 ( optlc_net_2678 ) , .p2659 ( optlc_net_2679 ) ,
+ .p2660 ( optlc_net_2680 ) , .p2661 ( optlc_net_2681 ) ,
+ .p2662 ( optlc_net_2682 ) , .p2663 ( optlc_net_2683 ) ,
+ .p2664 ( optlc_net_2684 ) , .p2665 ( optlc_net_2685 ) ,
+ .p2666 ( optlc_net_2686 ) , .p2667 ( optlc_net_2687 ) ,
+ .p2668 ( optlc_net_2688 ) , .p2669 ( optlc_net_2689 ) ,
+ .p2670 ( optlc_net_2690 ) , .p2671 ( optlc_net_2691 ) ,
+ .p2672 ( optlc_net_2692 ) , .p2673 ( optlc_net_2693 ) ,
+ .p2674 ( optlc_net_2694 ) , .p2675 ( optlc_net_2695 ) ,
+ .p2676 ( optlc_net_2696 ) , .p2677 ( optlc_net_2697 ) ,
+ .p2678 ( optlc_net_2698 ) , .p2679 ( optlc_net_2699 ) ,
+ .p2680 ( optlc_net_2700 ) , .p2681 ( optlc_net_2701 ) ,
+ .p2682 ( optlc_net_2702 ) , .p2683 ( optlc_net_2703 ) ,
+ .p2684 ( optlc_net_2704 ) , .p2685 ( optlc_net_2705 ) ,
+ .p2686 ( optlc_net_2706 ) , .p2687 ( optlc_net_2707 ) ,
+ .p2688 ( optlc_net_2708 ) , .p2689 ( optlc_net_2709 ) ,
+ .p2690 ( optlc_net_2710 ) , .p2691 ( optlc_net_2711 ) ,
+ .p2692 ( optlc_net_2712 ) , .p2693 ( optlc_net_2713 ) ,
+ .p2694 ( optlc_net_2714 ) , .p2695 ( optlc_net_2715 ) ,
+ .p2696 ( optlc_net_2716 ) , .p2697 ( optlc_net_2717 ) ,
+ .p2698 ( optlc_net_2718 ) , .p2699 ( optlc_net_2719 ) ,
+ .p2700 ( optlc_net_2720 ) , .p2701 ( optlc_net_2721 ) ,
+ .p2702 ( optlc_net_2722 ) , .p2703 ( optlc_net_2723 ) ,
+ .p2704 ( optlc_net_2724 ) , .p2705 ( optlc_net_2725 ) ,
+ .p2706 ( optlc_net_2726 ) , .p2707 ( optlc_net_2727 ) ,
+ .p2708 ( optlc_net_2728 ) , .p2709 ( optlc_net_2729 ) ,
+ .p2710 ( optlc_net_2730 ) , .p2711 ( optlc_net_2731 ) ,
+ .p2712 ( optlc_net_2732 ) , .p2713 ( optlc_net_2733 ) ,
+ .p2714 ( optlc_net_2734 ) , .p2715 ( optlc_net_2735 ) ,
+ .p2716 ( optlc_net_2736 ) , .p2717 ( optlc_net_2737 ) ,
+ .p2718 ( optlc_net_2738 ) , .p2719 ( optlc_net_2739 ) ,
+ .p2720 ( optlc_net_2740 ) , .p2721 ( optlc_net_2741 ) ,
+ .p2722 ( optlc_net_2742 ) , .p2723 ( optlc_net_2743 ) ,
+ .p2724 ( optlc_net_2744 ) , .p2725 ( optlc_net_2745 ) ,
+ .p2726 ( optlc_net_2746 ) , .p2727 ( optlc_net_2747 ) ,
+ .p2728 ( optlc_net_2748 ) , .p2729 ( optlc_net_2749 ) ,
+ .p2730 ( optlc_net_2750 ) , .p2731 ( optlc_net_2751 ) ,
+ .p2732 ( optlc_net_2752 ) , .p2733 ( optlc_net_2753 ) ,
+ .p2734 ( optlc_net_2754 ) , .p2735 ( optlc_net_2755 ) ,
+ .p2736 ( optlc_net_2756 ) , .p2737 ( optlc_net_2757 ) ,
+ .p2738 ( optlc_net_2758 ) , .p2739 ( optlc_net_2759 ) ,
+ .p2740 ( optlc_net_2760 ) , .p2741 ( optlc_net_2761 ) ,
+ .p2742 ( optlc_net_2762 ) , .p2743 ( optlc_net_2763 ) ,
+ .p2744 ( optlc_net_2764 ) , .p2745 ( optlc_net_2765 ) ,
+ .p2746 ( optlc_net_2766 ) , .p2747 ( optlc_net_2767 ) ,
+ .p2748 ( optlc_net_2768 ) , .p2749 ( optlc_net_2769 ) ,
+ .p2750 ( optlc_net_2770 ) , .p2751 ( optlc_net_2771 ) ,
+ .p2752 ( optlc_net_2772 ) , .p2753 ( optlc_net_2773 ) ,
+ .p2754 ( optlc_net_2774 ) , .p2755 ( optlc_net_2775 ) ,
+ .p2756 ( optlc_net_2776 ) , .p2757 ( optlc_net_2777 ) ,
+ .p2758 ( optlc_net_2778 ) , .p2759 ( optlc_net_2779 ) ,
+ .p2760 ( optlc_net_2780 ) , .p2761 ( optlc_net_2781 ) ,
+ .p2762 ( optlc_net_2782 ) , .p2763 ( optlc_net_2783 ) ,
+ .p2764 ( optlc_net_2784 ) , .p2765 ( optlc_net_2785 ) ,
+ .p2766 ( optlc_net_2786 ) , .p2767 ( optlc_net_2787 ) ,
+ .p2768 ( optlc_net_2788 ) , .p2769 ( optlc_net_2789 ) ,
+ .p2770 ( optlc_net_2790 ) , .p2771 ( optlc_net_2791 ) ,
+ .p2772 ( optlc_net_2792 ) , .p2773 ( optlc_net_2793 ) ,
+ .p2774 ( optlc_net_2794 ) , .p2775 ( optlc_net_2795 ) ,
+ .p2776 ( optlc_net_2796 ) , .p2777 ( optlc_net_2797 ) ,
+ .p2778 ( optlc_net_2798 ) , .p2779 ( optlc_net_2799 ) ,
+ .p2780 ( optlc_net_2800 ) , .p2781 ( optlc_net_2801 ) ,
+ .p2782 ( optlc_net_2802 ) , .p2783 ( optlc_net_2803 ) ,
+ .p2784 ( optlc_net_2804 ) , .p2785 ( optlc_net_2805 ) ,
+ .p2786 ( optlc_net_2806 ) , .p2787 ( optlc_net_2807 ) ,
+ .p2788 ( optlc_net_2808 ) , .p2789 ( optlc_net_2809 ) ,
+ .p2790 ( optlc_net_2810 ) , .p2791 ( optlc_net_2811 ) ,
+ .p2792 ( optlc_net_2812 ) , .p2793 ( optlc_net_2813 ) ,
+ .p2794 ( optlc_net_2814 ) , .p2795 ( optlc_net_2815 ) ,
+ .p2796 ( optlc_net_2816 ) , .p2797 ( optlc_net_2817 ) ,
+ .p2798 ( optlc_net_2818 ) , .p2799 ( optlc_net_2819 ) ,
+ .p2800 ( optlc_net_2820 ) , .p2801 ( optlc_net_2821 ) ,
+ .p2802 ( optlc_net_2822 ) , .p2803 ( optlc_net_2823 ) ,
+ .p2804 ( optlc_net_2824 ) , .p2805 ( optlc_net_2825 ) ,
+ .p2806 ( optlc_net_2826 ) , .p2807 ( optlc_net_2827 ) ,
+ .p2808 ( optlc_net_2828 ) , .p2809 ( optlc_net_2829 ) ,
+ .p2810 ( optlc_net_2830 ) , .p2811 ( optlc_net_2831 ) ,
+ .p2812 ( optlc_net_2832 ) , .p2813 ( optlc_net_2833 ) ,
+ .p2814 ( optlc_net_2834 ) , .p2815 ( optlc_net_2835 ) ,
+ .p2816 ( optlc_net_2836 ) , .p2817 ( optlc_net_2837 ) ,
+ .p2818 ( optlc_net_2838 ) , .p2819 ( optlc_net_2839 ) ,
+ .p2820 ( optlc_net_2840 ) , .p2821 ( optlc_net_2841 ) ,
+ .p2822 ( optlc_net_2842 ) , .p2823 ( optlc_net_2843 ) ,
+ .p2824 ( optlc_net_2844 ) , .p2825 ( optlc_net_2845 ) ,
+ .p2826 ( optlc_net_2846 ) , .p2827 ( optlc_net_2847 ) ,
+ .p2828 ( optlc_net_2848 ) , .p2829 ( optlc_net_2849 ) ,
+ .p2830 ( optlc_net_2850 ) , .p2831 ( optlc_net_2851 ) ,
+ .p2832 ( optlc_net_2852 ) , .p2833 ( optlc_net_2853 ) ,
+ .p2834 ( optlc_net_2854 ) , .p2835 ( optlc_net_2855 ) ,
+ .p2836 ( optlc_net_2856 ) , .p2837 ( optlc_net_2857 ) ,
+ .p2838 ( optlc_net_2858 ) , .p2839 ( optlc_net_2859 ) ,
+ .p2840 ( optlc_net_2860 ) , .p2841 ( optlc_net_2861 ) ,
+ .p2842 ( optlc_net_2862 ) , .p2843 ( optlc_net_2863 ) ,
+ .p2844 ( optlc_net_2864 ) , .p2845 ( optlc_net_2865 ) ,
+ .p2846 ( optlc_net_2866 ) , .p2847 ( optlc_net_2867 ) ,
+ .p2848 ( optlc_net_2868 ) , .p2849 ( optlc_net_2869 ) ,
+ .p2850 ( optlc_net_2870 ) , .p2851 ( optlc_net_2871 ) ,
+ .p2852 ( optlc_net_2872 ) , .p2853 ( optlc_net_2873 ) ,
+ .p2854 ( optlc_net_2874 ) , .p2855 ( optlc_net_2875 ) ,
+ .p2856 ( optlc_net_2876 ) , .p2857 ( optlc_net_2877 ) ,
+ .p2858 ( optlc_net_2878 ) , .p2859 ( optlc_net_2879 ) ,
+ .p2860 ( optlc_net_2880 ) , .p2861 ( optlc_net_2881 ) ,
+ .p2862 ( optlc_net_2882 ) , .p2863 ( optlc_net_2883 ) ,
+ .p2864 ( optlc_net_2884 ) , .p2865 ( optlc_net_2885 ) ,
+ .p2866 ( optlc_net_2886 ) , .p2867 ( optlc_net_2887 ) ,
+ .p2868 ( optlc_net_2888 ) , .p2869 ( optlc_net_2889 ) ,
+ .p2870 ( optlc_net_2890 ) , .p2871 ( optlc_net_2891 ) ,
+ .p2872 ( optlc_net_2892 ) , .p2873 ( optlc_net_2893 ) ,
+ .p2874 ( optlc_net_2894 ) , .p2875 ( optlc_net_2895 ) ,
+ .p2876 ( optlc_net_2896 ) , .p2877 ( optlc_net_2897 ) ,
+ .p2878 ( optlc_net_2898 ) , .p2879 ( optlc_net_2899 ) ,
+ .p2880 ( optlc_net_2900 ) , .p2881 ( optlc_net_2901 ) ,
+ .p2882 ( optlc_net_2902 ) , .p2883 ( optlc_net_2903 ) ,
+ .p2884 ( optlc_net_2904 ) , .p2885 ( optlc_net_2905 ) ,
+ .p2886 ( optlc_net_2906 ) , .p2887 ( optlc_net_2907 ) ,
+ .p2888 ( optlc_net_2908 ) , .p2889 ( optlc_net_2909 ) ,
+ .p2890 ( optlc_net_2910 ) , .p2891 ( optlc_net_2911 ) ,
+ .p2892 ( optlc_net_2912 ) , .p2893 ( optlc_net_2913 ) ,
+ .p2894 ( optlc_net_2914 ) , .p2895 ( optlc_net_2915 ) ,
+ .p2896 ( optlc_net_2916 ) , .p2897 ( optlc_net_2917 ) ,
+ .p2898 ( optlc_net_2918 ) , .p2899 ( optlc_net_2919 ) ,
+ .p2900 ( optlc_net_2920 ) , .p2901 ( optlc_net_2921 ) ,
+ .p2902 ( optlc_net_2922 ) , .p2903 ( optlc_net_2923 ) ,
+ .p2904 ( optlc_net_2924 ) , .p2905 ( optlc_net_2925 ) ,
+ .p2906 ( optlc_net_2926 ) , .p2907 ( optlc_net_2927 ) ,
+ .p2908 ( optlc_net_2928 ) , .p2909 ( optlc_net_2929 ) ,
+ .p2910 ( optlc_net_2930 ) , .p2911 ( optlc_net_2931 ) ,
+ .p2912 ( optlc_net_2932 ) , .p2913 ( optlc_net_2933 ) ,
+ .p2914 ( optlc_net_2934 ) , .p2915 ( optlc_net_2935 ) ,
+ .p2916 ( optlc_net_2936 ) , .p2917 ( optlc_net_2937 ) ,
+ .p2918 ( optlc_net_2938 ) , .p2919 ( optlc_net_2939 ) ,
+ .p2920 ( optlc_net_2940 ) , .p2921 ( optlc_net_2941 ) ,
+ .p2922 ( optlc_net_2942 ) , .p2923 ( optlc_net_2943 ) ,
+ .p2924 ( optlc_net_2944 ) , .p2925 ( optlc_net_2945 ) ,
+ .p2926 ( optlc_net_2946 ) , .p2927 ( optlc_net_2947 ) ,
+ .p2928 ( optlc_net_2948 ) , .p2929 ( optlc_net_2949 ) ,
+ .p2930 ( optlc_net_2950 ) , .p2931 ( optlc_net_2951 ) ,
+ .p2932 ( optlc_net_2952 ) , .p2933 ( optlc_net_2953 ) ,
+ .p2934 ( optlc_net_2954 ) , .p2935 ( optlc_net_2955 ) ,
+ .p2936 ( optlc_net_2956 ) , .p2937 ( optlc_net_2957 ) ,
+ .p2938 ( optlc_net_2958 ) , .p2939 ( optlc_net_2959 ) ,
+ .p2940 ( optlc_net_2960 ) , .p2941 ( optlc_net_2961 ) ,
+ .p2942 ( optlc_net_2962 ) , .p2943 ( optlc_net_2963 ) ,
+ .p2944 ( optlc_net_2964 ) , .p2945 ( optlc_net_2965 ) ,
+ .p2946 ( optlc_net_2966 ) , .p2947 ( optlc_net_2967 ) ,
+ .p2948 ( optlc_net_2968 ) , .p2949 ( optlc_net_2969 ) ,
+ .p2950 ( optlc_net_2970 ) , .p2951 ( optlc_net_2971 ) ,
+ .p2952 ( optlc_net_2972 ) , .p2953 ( optlc_net_2973 ) ,
+ .p2954 ( optlc_net_2974 ) , .p2955 ( optlc_net_2975 ) ,
+ .p2956 ( optlc_net_2976 ) , .p2957 ( optlc_net_2977 ) ,
+ .p2958 ( optlc_net_2978 ) , .p2959 ( optlc_net_2979 ) ,
+ .p2960 ( optlc_net_2980 ) , .p2961 ( optlc_net_2981 ) ,
+ .p2962 ( optlc_net_2982 ) , .p2963 ( optlc_net_2983 ) ,
+ .p2964 ( optlc_net_2984 ) , .p2965 ( optlc_net_2985 ) ,
+ .p2966 ( optlc_net_2986 ) , .p2967 ( optlc_net_2987 ) ,
+ .p2968 ( optlc_net_2988 ) , .p2969 ( optlc_net_2989 ) ,
+ .p2970 ( optlc_net_2990 ) , .p2971 ( optlc_net_2991 ) ,
+ .p2972 ( optlc_net_2992 ) , .p2973 ( optlc_net_2993 ) ,
+ .p2974 ( optlc_net_2994 ) , .p2975 ( optlc_net_2995 ) ,
+ .p2976 ( optlc_net_2996 ) , .p2977 ( optlc_net_2997 ) ,
+ .p2978 ( optlc_net_2998 ) , .p2979 ( optlc_net_2999 ) ,
+ .p2980 ( optlc_net_3000 ) , .p2981 ( optlc_net_3001 ) ,
+ .p2982 ( optlc_net_3002 ) , .p2983 ( optlc_net_3003 ) ,
+ .p2984 ( optlc_net_3004 ) , .p2985 ( optlc_net_3005 ) ,
+ .p2986 ( optlc_net_3006 ) , .p2987 ( optlc_net_3007 ) ,
+ .p2988 ( optlc_net_3008 ) , .p2989 ( optlc_net_3009 ) ,
+ .p2990 ( optlc_net_3010 ) , .p2991 ( optlc_net_3011 ) ,
+ .p2992 ( optlc_net_3012 ) , .p2993 ( optlc_net_3013 ) ,
+ .p2994 ( optlc_net_3014 ) , .p2995 ( optlc_net_3015 ) ,
+ .p2996 ( optlc_net_3016 ) , .p2997 ( optlc_net_3017 ) ,
+ .p2998 ( optlc_net_3018 ) , .p2999 ( optlc_net_3019 ) ,
+ .p3000 ( optlc_net_3020 ) , .p3001 ( optlc_net_3021 ) ,
+ .p3002 ( optlc_net_3022 ) , .p3003 ( optlc_net_3023 ) ,
+ .p3004 ( optlc_net_3024 ) , .p3005 ( optlc_net_3025 ) ,
+ .p3006 ( optlc_net_3026 ) , .p3007 ( optlc_net_3027 ) ,
+ .p3008 ( optlc_net_3028 ) , .p3009 ( optlc_net_3029 ) ,
+ .p3010 ( optlc_net_3030 ) , .p3011 ( optlc_net_3031 ) ,
+ .p3012 ( optlc_net_3032 ) , .p3013 ( optlc_net_3033 ) ,
+ .p3014 ( optlc_net_3034 ) , .p3015 ( optlc_net_3035 ) ,
+ .p3016 ( optlc_net_3036 ) , .p3017 ( optlc_net_3037 ) ,
+ .p3018 ( optlc_net_3038 ) , .p3019 ( optlc_net_3039 ) ,
+ .p3020 ( optlc_net_3040 ) , .p3021 ( optlc_net_3041 ) ,
+ .p3022 ( optlc_net_3042 ) , .p3023 ( optlc_net_3043 ) ,
+ .p3024 ( optlc_net_3044 ) , .p3025 ( optlc_net_3045 ) ,
+ .p3026 ( optlc_net_3046 ) , .p3027 ( optlc_net_3047 ) ,
+ .p3028 ( optlc_net_3048 ) , .p3029 ( optlc_net_3049 ) ,
+ .p3030 ( optlc_net_3050 ) , .p3031 ( optlc_net_3051 ) ,
+ .p3032 ( optlc_net_3052 ) , .p3033 ( optlc_net_3053 ) ,
+ .p3034 ( optlc_net_3054 ) , .p3035 ( optlc_net_3055 ) ,
+ .p3036 ( optlc_net_3056 ) , .p3037 ( optlc_net_3057 ) ,
+ .p3038 ( optlc_net_3058 ) , .p3039 ( optlc_net_3059 ) ,
+ .p3040 ( optlc_net_3060 ) , .p3041 ( optlc_net_3061 ) ,
+ .p3042 ( optlc_net_3062 ) , .p3043 ( optlc_net_3063 ) ,
+ .p3044 ( optlc_net_3064 ) , .p3045 ( optlc_net_3065 ) ,
+ .p3046 ( optlc_net_3066 ) , .p3047 ( optlc_net_3067 ) ,
+ .p3048 ( optlc_net_3068 ) , .p3049 ( optlc_net_3069 ) ,
+ .p3050 ( optlc_net_3070 ) , .p3051 ( optlc_net_3071 ) ,
+ .p3052 ( optlc_net_3072 ) , .p3053 ( optlc_net_3073 ) ,
+ .p3054 ( optlc_net_3074 ) , .p3055 ( optlc_net_3075 ) ,
+ .p3056 ( optlc_net_3076 ) , .p3057 ( optlc_net_3077 ) ,
+ .p3058 ( optlc_net_3078 ) , .p3059 ( optlc_net_3079 ) ,
+ .p3060 ( optlc_net_3080 ) , .p3061 ( optlc_net_3081 ) ,
+ .p3062 ( optlc_net_3082 ) , .p3063 ( optlc_net_3083 ) ,
+ .p3064 ( optlc_net_3084 ) , .p3065 ( optlc_net_3085 ) ,
+ .p3066 ( optlc_net_3086 ) , .p3067 ( optlc_net_3087 ) ,
+ .p3068 ( optlc_net_3088 ) , .p3069 ( optlc_net_3089 ) ,
+ .p3070 ( optlc_net_3090 ) , .p3071 ( optlc_net_3091 ) ,
+ .p3072 ( optlc_net_3092 ) , .p3073 ( optlc_net_3093 ) ,
+ .p3074 ( optlc_net_3094 ) , .p3075 ( optlc_net_3095 ) ,
+ .p3076 ( optlc_net_3096 ) , .p3077 ( optlc_net_3097 ) ,
+ .p3078 ( optlc_net_3098 ) , .p3079 ( optlc_net_3099 ) ,
+ .p3080 ( optlc_net_3100 ) , .p3081 ( optlc_net_3101 ) ,
+ .p3082 ( optlc_net_3102 ) , .p3083 ( optlc_net_3103 ) ,
+ .p3084 ( optlc_net_3104 ) , .p3085 ( optlc_net_3105 ) ,
+ .p3086 ( optlc_net_3106 ) , .p3087 ( optlc_net_3107 ) ,
+ .p3088 ( optlc_net_3108 ) , .p3089 ( optlc_net_3109 ) ,
+ .p3090 ( optlc_net_3110 ) , .p3091 ( optlc_net_3111 ) ,
+ .p3092 ( optlc_net_3112 ) , .p3093 ( optlc_net_3113 ) ,
+ .p3094 ( optlc_net_3114 ) , .p3095 ( optlc_net_3115 ) ,
+ .p3096 ( optlc_net_3116 ) , .p3097 ( optlc_net_3117 ) ,
+ .p3098 ( optlc_net_3118 ) , .p3099 ( optlc_net_3119 ) ,
+ .p3100 ( optlc_net_3120 ) , .p3101 ( optlc_net_3121 ) ,
+ .p3102 ( optlc_net_3122 ) , .p3103 ( optlc_net_3123 ) ,
+ .p3104 ( optlc_net_3124 ) , .p3105 ( optlc_net_3125 ) ,
+ .p3106 ( optlc_net_3126 ) , .p3107 ( optlc_net_3127 ) ,
+ .p3108 ( optlc_net_3128 ) , .p3109 ( optlc_net_3129 ) ,
+ .p3110 ( optlc_net_3130 ) , .p3111 ( optlc_net_3131 ) ,
+ .p3112 ( optlc_net_3132 ) , .p3113 ( optlc_net_3133 ) ,
+ .p3114 ( optlc_net_3134 ) , .p3115 ( optlc_net_3135 ) ,
+ .p3116 ( optlc_net_3136 ) , .p3117 ( optlc_net_3137 ) ,
+ .p3118 ( optlc_net_3138 ) , .p3119 ( optlc_net_3139 ) ,
+ .p3120 ( optlc_net_3140 ) , .p3121 ( optlc_net_3141 ) ,
+ .p3122 ( optlc_net_3142 ) , .p3123 ( optlc_net_3143 ) ,
+ .p3124 ( optlc_net_3144 ) , .p3125 ( optlc_net_3145 ) ,
+ .p3126 ( optlc_net_3146 ) , .p3127 ( optlc_net_3147 ) ,
+ .p3128 ( optlc_net_3148 ) , .p3129 ( optlc_net_3149 ) ,
+ .p3130 ( optlc_net_3150 ) , .p3131 ( optlc_net_3151 ) ,
+ .p3132 ( optlc_net_3152 ) , .p3133 ( optlc_net_3153 ) ,
+ .p3134 ( optlc_net_3154 ) , .p3135 ( optlc_net_3155 ) ,
+ .p3136 ( optlc_net_3156 ) , .p3137 ( optlc_net_3157 ) ,
+ .p3138 ( optlc_net_3158 ) , .p3139 ( optlc_net_3159 ) ,
+ .p3140 ( optlc_net_3160 ) , .p3141 ( optlc_net_3161 ) ,
+ .p3142 ( optlc_net_3162 ) , .p3143 ( optlc_net_3163 ) ,
+ .p3144 ( optlc_net_3164 ) , .p3145 ( optlc_net_3165 ) ,
+ .p3146 ( optlc_net_3166 ) , .p3147 ( optlc_net_3167 ) ,
+ .p3148 ( optlc_net_3168 ) , .p3149 ( optlc_net_3169 ) ,
+ .p3150 ( optlc_net_3170 ) , .p3151 ( optlc_net_3171 ) ,
+ .p3152 ( optlc_net_3172 ) , .p3153 ( optlc_net_3173 ) ,
+ .p3154 ( optlc_net_3174 ) , .p3155 ( optlc_net_3175 ) ,
+ .p3156 ( optlc_net_3176 ) , .p3157 ( optlc_net_3177 ) ,
+ .p3158 ( optlc_net_3178 ) , .p3159 ( optlc_net_3179 ) ,
+ .p3160 ( optlc_net_3180 ) , .p3161 ( optlc_net_3181 ) ,
+ .p3162 ( optlc_net_3182 ) , .p3163 ( optlc_net_3183 ) ,
+ .p3164 ( optlc_net_3184 ) , .p3165 ( optlc_net_3185 ) ,
+ .p3166 ( optlc_net_3186 ) , .p3167 ( optlc_net_3187 ) ,
+ .p3168 ( optlc_net_3188 ) , .p3169 ( optlc_net_3189 ) ,
+ .p3170 ( optlc_net_3190 ) , .p3171 ( optlc_net_3191 ) ,
+ .p3172 ( optlc_net_3192 ) , .p3173 ( optlc_net_3193 ) ,
+ .p3174 ( optlc_net_3194 ) , .p3175 ( optlc_net_3195 ) ,
+ .p3176 ( optlc_net_3196 ) , .p3177 ( optlc_net_3197 ) ,
+ .p3178 ( optlc_net_3198 ) , .p3179 ( optlc_net_3199 ) ,
+ .p3180 ( optlc_net_3200 ) , .p3181 ( optlc_net_3201 ) ,
+ .p3182 ( optlc_net_3202 ) , .p3183 ( optlc_net_3203 ) ,
+ .p3184 ( optlc_net_3204 ) , .p3185 ( optlc_net_3205 ) ,
+ .p3186 ( optlc_net_3206 ) , .p3187 ( optlc_net_3207 ) ,
+ .p3188 ( optlc_net_3208 ) , .p3189 ( optlc_net_3209 ) ,
+ .p3190 ( optlc_net_3210 ) , .p3191 ( optlc_net_3211 ) ,
+ .p3192 ( optlc_net_3212 ) , .p3193 ( optlc_net_3213 ) ,
+ .p3194 ( optlc_net_3214 ) , .p3195 ( optlc_net_3215 ) ,
+ .p3196 ( optlc_net_3216 ) , .p3197 ( optlc_net_3217 ) ,
+ .p3198 ( optlc_net_3218 ) , .p3199 ( optlc_net_3219 ) ,
+ .p3200 ( optlc_net_3220 ) , .p3201 ( optlc_net_3221 ) ,
+ .p3202 ( optlc_net_3222 ) , .p3203 ( optlc_net_3223 ) ,
+ .p3204 ( optlc_net_3224 ) , .p3205 ( optlc_net_3225 ) ,
+ .p3206 ( optlc_net_3226 ) , .p3207 ( optlc_net_3227 ) ,
+ .p3208 ( optlc_net_3228 ) , .p3209 ( optlc_net_3229 ) ,
+ .p3210 ( optlc_net_3230 ) , .p3211 ( optlc_net_3231 ) ,
+ .p3212 ( optlc_net_3232 ) , .p3213 ( optlc_net_3233 ) ,
+ .p3214 ( optlc_net_3234 ) , .p3215 ( optlc_net_3235 ) ,
+ .p3216 ( optlc_net_3236 ) , .p3217 ( optlc_net_3237 ) ,
+ .p3218 ( optlc_net_3238 ) , .p3219 ( optlc_net_3239 ) ,
+ .p3220 ( optlc_net_3240 ) , .p3221 ( optlc_net_3241 ) ,
+ .p3222 ( optlc_net_3242 ) , .p3223 ( optlc_net_3243 ) ,
+ .p3224 ( optlc_net_3244 ) , .p3225 ( optlc_net_3245 ) ,
+ .p3226 ( optlc_net_3246 ) , .p3227 ( optlc_net_3247 ) ,
+ .p3228 ( optlc_net_3248 ) , .p3229 ( optlc_net_3249 ) ,
+ .p3230 ( optlc_net_3250 ) , .p3231 ( optlc_net_3251 ) ,
+ .p3232 ( optlc_net_3252 ) , .p3233 ( optlc_net_3253 ) ,
+ .p3234 ( optlc_net_3254 ) , .p3235 ( optlc_net_3255 ) ,
+ .p3236 ( optlc_net_3256 ) , .p3237 ( optlc_net_3257 ) ,
+ .p3238 ( optlc_net_3258 ) , .p3239 ( optlc_net_3259 ) ,
+ .p3240 ( optlc_net_3260 ) , .p3241 ( optlc_net_3261 ) ,
+ .p3242 ( optlc_net_3262 ) , .p3243 ( optlc_net_3263 ) ,
+ .p3244 ( optlc_net_3264 ) , .p3245 ( optlc_net_3265 ) ,
+ .p3246 ( optlc_net_3266 ) , .p3247 ( optlc_net_3267 ) ,
+ .p3248 ( optlc_net_3268 ) , .p3249 ( optlc_net_3269 ) ,
+ .p3250 ( optlc_net_3270 ) , .p3251 ( optlc_net_3271 ) ,
+ .p3252 ( optlc_net_3272 ) , .p3253 ( optlc_net_3273 ) ,
+ .p3254 ( optlc_net_3274 ) , .p3255 ( optlc_net_3275 ) ,
+ .p3256 ( optlc_net_3276 ) , .p3257 ( optlc_net_3277 ) ,
+ .p3258 ( optlc_net_3278 ) , .p3259 ( optlc_net_3279 ) ,
+ .p3260 ( optlc_net_3280 ) , .p3261 ( optlc_net_3281 ) ,
+ .p3262 ( optlc_net_3282 ) , .p3263 ( optlc_net_3283 ) ,
+ .p3264 ( optlc_net_3284 ) , .p3265 ( optlc_net_3285 ) ,
+ .p3266 ( optlc_net_3286 ) , .p3267 ( optlc_net_3287 ) ,
+ .p3268 ( optlc_net_3288 ) , .p3269 ( optlc_net_3289 ) ,
+ .p3270 ( optlc_net_3290 ) , .p3271 ( optlc_net_3291 ) ,
+ .p3272 ( optlc_net_3292 ) , .p3273 ( optlc_net_3293 ) ,
+ .p3274 ( optlc_net_3294 ) , .p3275 ( optlc_net_3295 ) ,
+ .p3276 ( optlc_net_3296 ) , .p3277 ( optlc_net_3297 ) ,
+ .p3278 ( optlc_net_3298 ) , .p3279 ( optlc_net_3299 ) ,
+ .p3280 ( optlc_net_3300 ) , .p3281 ( optlc_net_3301 ) ,
+ .p3282 ( optlc_net_3302 ) , .p3283 ( optlc_net_3303 ) ,
+ .p3284 ( optlc_net_3304 ) , .p3285 ( optlc_net_3305 ) ,
+ .p3286 ( optlc_net_3306 ) , .p3287 ( optlc_net_3307 ) ,
+ .p3288 ( optlc_net_3308 ) , .p3289 ( optlc_net_3309 ) ,
+ .p3290 ( optlc_net_3310 ) , .p3291 ( optlc_net_3311 ) ,
+ .p3292 ( optlc_net_3312 ) , .p3293 ( optlc_net_3313 ) ,
+ .p3294 ( optlc_net_3314 ) , .p3295 ( optlc_net_3315 ) ,
+ .p3296 ( optlc_net_3316 ) , .p3297 ( optlc_net_3317 ) ,
+ .p3298 ( optlc_net_3318 ) , .p3299 ( optlc_net_3319 ) ,
+ .p3300 ( optlc_net_3320 ) , .p3301 ( optlc_net_3321 ) ,
+ .p3302 ( optlc_net_3322 ) , .p3303 ( optlc_net_3323 ) ,
+ .p3304 ( optlc_net_3324 ) , .p3305 ( optlc_net_3325 ) ,
+ .p3306 ( optlc_net_3326 ) , .p3307 ( optlc_net_3327 ) ,
+ .p3308 ( optlc_net_3328 ) , .p3309 ( optlc_net_3329 ) ,
+ .p3310 ( optlc_net_3330 ) , .p3311 ( optlc_net_3331 ) ,
+ .p3312 ( optlc_net_3332 ) , .p3313 ( optlc_net_3333 ) ,
+ .p3314 ( optlc_net_3334 ) , .p3315 ( optlc_net_3335 ) ,
+ .p3316 ( optlc_net_3336 ) , .p3317 ( optlc_net_3337 ) ,
+ .p3318 ( optlc_net_3338 ) , .p3319 ( optlc_net_3339 ) ,
+ .p3320 ( optlc_net_3340 ) , .p3321 ( optlc_net_3341 ) ,
+ .p3322 ( optlc_net_3342 ) , .p3323 ( optlc_net_3343 ) ,
+ .p3324 ( optlc_net_3344 ) , .p3325 ( optlc_net_3345 ) ,
+ .p3326 ( optlc_net_3346 ) , .p3327 ( optlc_net_3347 ) ,
+ .p3328 ( optlc_net_3348 ) , .p3329 ( optlc_net_3349 ) ,
+ .p3330 ( optlc_net_3350 ) , .p3331 ( optlc_net_3351 ) ,
+ .p3332 ( optlc_net_3352 ) , .p3333 ( optlc_net_3353 ) ,
+ .p3334 ( optlc_net_3354 ) , .p3335 ( optlc_net_3355 ) ,
+ .p3336 ( optlc_net_3356 ) , .p3337 ( optlc_net_3357 ) ,
+ .p3338 ( optlc_net_3358 ) , .p3339 ( optlc_net_3359 ) ,
+ .p3340 ( optlc_net_3360 ) , .p3341 ( optlc_net_3361 ) ,
+ .p3342 ( optlc_net_3362 ) , .p3343 ( optlc_net_3363 ) ,
+ .p3344 ( optlc_net_3364 ) , .p3345 ( optlc_net_3365 ) ,
+ .p3346 ( optlc_net_3366 ) , .p3347 ( optlc_net_3367 ) ,
+ .p3348 ( optlc_net_3368 ) , .p3349 ( optlc_net_3369 ) ,
+ .p3350 ( optlc_net_3370 ) , .p3351 ( optlc_net_3371 ) ,
+ .p3352 ( optlc_net_3372 ) , .p3353 ( optlc_net_3373 ) ,
+ .p3354 ( optlc_net_3374 ) , .p3355 ( optlc_net_3375 ) ,
+ .p3356 ( optlc_net_3376 ) , .p3357 ( optlc_net_3377 ) ,
+ .p3358 ( optlc_net_3378 ) , .p3359 ( optlc_net_3379 ) ,
+ .p3360 ( optlc_net_3380 ) , .p3361 ( optlc_net_3381 ) ,
+ .p3362 ( optlc_net_3382 ) , .p3363 ( optlc_net_3383 ) ,
+ .p3364 ( optlc_net_3384 ) , .p3365 ( optlc_net_3385 ) ,
+ .p3366 ( optlc_net_3386 ) , .p3367 ( optlc_net_3387 ) ,
+ .p3368 ( optlc_net_3388 ) , .p3369 ( optlc_net_3389 ) ,
+ .p3370 ( optlc_net_3390 ) , .p3371 ( optlc_net_3391 ) ,
+ .p3372 ( optlc_net_3392 ) , .p3373 ( optlc_net_3393 ) ,
+ .p3374 ( optlc_net_3394 ) , .p3375 ( optlc_net_3395 ) ,
+ .p3376 ( optlc_net_3396 ) , .p3377 ( optlc_net_3397 ) ,
+ .p3378 ( optlc_net_3398 ) , .p3379 ( optlc_net_3399 ) ,
+ .p3380 ( optlc_net_3400 ) , .p3381 ( optlc_net_3401 ) ,
+ .p3382 ( optlc_net_3402 ) , .p3383 ( optlc_net_3403 ) ,
+ .p3384 ( optlc_net_3404 ) , .p3385 ( optlc_net_3405 ) ,
+ .p3386 ( optlc_net_3406 ) , .p3387 ( optlc_net_3407 ) ,
+ .p3388 ( optlc_net_3408 ) , .p3389 ( optlc_net_3409 ) ,
+ .p3390 ( optlc_net_3410 ) , .p3391 ( optlc_net_3411 ) ,
+ .p3392 ( optlc_net_3412 ) , .p3393 ( optlc_net_3413 ) ,
+ .p3394 ( optlc_net_3414 ) , .p3395 ( optlc_net_3415 ) ,
+ .p3396 ( optlc_net_3416 ) , .p3397 ( optlc_net_3417 ) ,
+ .p3398 ( optlc_net_3418 ) , .p3399 ( optlc_net_3419 ) ,
+ .p3400 ( optlc_net_3420 ) , .p3401 ( optlc_net_3421 ) ,
+ .p3402 ( optlc_net_3422 ) , .p3403 ( optlc_net_3423 ) ,
+ .p3404 ( optlc_net_3424 ) , .p3405 ( optlc_net_3425 ) ,
+ .p3406 ( optlc_net_3426 ) , .p3407 ( optlc_net_3427 ) ,
+ .p3408 ( optlc_net_3428 ) , .p3409 ( optlc_net_3429 ) ,
+ .p3410 ( optlc_net_3430 ) , .p3411 ( optlc_net_3431 ) ,
+ .p3412 ( optlc_net_3432 ) , .p3413 ( optlc_net_3433 ) ,
+ .p3414 ( optlc_net_3434 ) , .p3415 ( optlc_net_3435 ) ,
+ .p3416 ( optlc_net_3436 ) , .p3417 ( optlc_net_3437 ) ,
+ .p3418 ( optlc_net_3438 ) , .p3419 ( optlc_net_3439 ) ,
+ .p3420 ( optlc_net_3440 ) , .p3421 ( optlc_net_3441 ) ,
+ .p3422 ( optlc_net_3442 ) , .p3423 ( optlc_net_3443 ) ,
+ .p3424 ( optlc_net_3444 ) , .p3425 ( optlc_net_3445 ) ,
+ .p3426 ( optlc_net_3446 ) , .p3427 ( optlc_net_3447 ) ,
+ .p3428 ( optlc_net_3448 ) , .p3429 ( optlc_net_3449 ) ,
+ .p3430 ( optlc_net_3450 ) , .p3431 ( optlc_net_3451 ) ,
+ .p3432 ( optlc_net_3452 ) , .p3433 ( optlc_net_3453 ) ,
+ .p3434 ( optlc_net_3454 ) , .p3435 ( optlc_net_3455 ) ,
+ .p3436 ( optlc_net_3456 ) , .p3437 ( optlc_net_3457 ) ,
+ .p3438 ( optlc_net_3458 ) , .p3439 ( optlc_net_3459 ) ,
+ .p3440 ( optlc_net_3460 ) , .p3441 ( optlc_net_3461 ) ,
+ .p3442 ( optlc_net_3462 ) , .p3443 ( optlc_net_3463 ) ,
+ .p3444 ( optlc_net_3464 ) , .p3445 ( optlc_net_3465 ) ,
+ .p3446 ( optlc_net_3466 ) , .p3447 ( optlc_net_3467 ) ,
+ .p3448 ( optlc_net_3468 ) , .p3449 ( optlc_net_3469 ) ,
+ .p3450 ( optlc_net_3470 ) , .p3451 ( optlc_net_3471 ) ,
+ .p3452 ( optlc_net_3472 ) , .p3453 ( optlc_net_3473 ) ,
+ .p3454 ( optlc_net_3474 ) , .p3455 ( optlc_net_3475 ) ,
+ .p3456 ( optlc_net_3476 ) , .p3457 ( optlc_net_3477 ) ,
+ .p3458 ( optlc_net_3478 ) , .p3459 ( optlc_net_3479 ) ,
+ .p3460 ( optlc_net_3480 ) , .p3461 ( optlc_net_3481 ) ,
+ .p3462 ( optlc_net_3482 ) , .p3463 ( optlc_net_3483 ) ,
+ .p3464 ( optlc_net_3484 ) , .p3465 ( optlc_net_3485 ) ,
+ .p3466 ( optlc_net_3486 ) , .p3467 ( optlc_net_3487 ) ,
+ .p3468 ( optlc_net_3488 ) , .p3469 ( optlc_net_3489 ) ,
+ .p3470 ( optlc_net_3490 ) , .p3471 ( optlc_net_3491 ) ,
+ .p3472 ( optlc_net_3492 ) , .p3473 ( optlc_net_3493 ) ,
+ .p3474 ( optlc_net_3494 ) , .p3475 ( optlc_net_3495 ) ,
+ .p3476 ( optlc_net_3496 ) , .p3477 ( optlc_net_3497 ) ,
+ .p3478 ( optlc_net_3498 ) , .p3479 ( optlc_net_3499 ) ,
+ .p3480 ( optlc_net_3500 ) , .p3481 ( optlc_net_3501 ) ,
+ .p3482 ( optlc_net_3502 ) , .p3483 ( optlc_net_3503 ) ,
+ .p3484 ( optlc_net_3504 ) , .p3485 ( optlc_net_3505 ) ,
+ .p3486 ( optlc_net_3506 ) , .p3487 ( optlc_net_3507 ) ,
+ .p3488 ( optlc_net_3508 ) , .p3489 ( optlc_net_3509 ) ,
+ .p3490 ( optlc_net_3510 ) , .p3491 ( optlc_net_3511 ) ,
+ .p3492 ( optlc_net_3512 ) , .p3493 ( optlc_net_3513 ) ,
+ .p3494 ( optlc_net_3514 ) , .p3495 ( optlc_net_3515 ) ,
+ .p3496 ( optlc_net_3516 ) , .p3497 ( optlc_net_3517 ) ,
+ .p3498 ( optlc_net_3518 ) , .p3499 ( optlc_net_3519 ) ,
+ .p3500 ( optlc_net_3520 ) , .p3501 ( optlc_net_3521 ) ,
+ .p3502 ( optlc_net_3522 ) , .p3503 ( optlc_net_3523 ) ,
+ .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) ,
+ .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) ,
+ .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) ,
+ .p3510 ( optlc_net_3530 ) , .p3511 ( optlc_net_3531 ) ,
+ .p3512 ( optlc_net_3532 ) , .p3513 ( optlc_net_3533 ) ,
+ .p3514 ( optlc_net_3534 ) , .p3515 ( optlc_net_3535 ) ,
+ .p3516 ( optlc_net_3536 ) , .p3517 ( optlc_net_3537 ) ,
+ .p3518 ( optlc_net_3538 ) , .p3519 ( optlc_net_3539 ) ,
+ .p3520 ( optlc_net_3540 ) , .p3521 ( optlc_net_3541 ) ,
+ .p3522 ( optlc_net_3542 ) , .p3523 ( optlc_net_3543 ) ,
+ .p3524 ( optlc_net_3544 ) , .p3525 ( optlc_net_3545 ) ,
+ .p3526 ( optlc_net_3546 ) , .p3527 ( optlc_net_3547 ) ,
+ .p3528 ( optlc_net_3548 ) , .p3529 ( optlc_net_3549 ) ,
+ .p3530 ( optlc_net_3550 ) , .p3531 ( optlc_net_3551 ) ,
+ .p3532 ( optlc_net_3552 ) , .p3533 ( optlc_net_3553 ) ,
+ .p3534 ( optlc_net_3554 ) , .p3535 ( optlc_net_3555 ) ,
+ .p3536 ( optlc_net_3556 ) , .p3537 ( optlc_net_3557 ) ,
+ .p3538 ( optlc_net_3558 ) , .p3539 ( optlc_net_3559 ) ,
+ .p3540 ( optlc_net_3560 ) , .p3541 ( optlc_net_3561 ) ,
+ .p3542 ( optlc_net_3562 ) , .p3543 ( optlc_net_3563 ) ,
+ .p3544 ( optlc_net_3564 ) , .p3545 ( optlc_net_3565 ) ,
+ .p3546 ( optlc_net_3566 ) , .p3547 ( optlc_net_3567 ) ,
+ .p3548 ( optlc_net_3568 ) , .p3549 ( optlc_net_3569 ) ,
+ .p3550 ( optlc_net_3570 ) , .p3551 ( optlc_net_3571 ) ,
+ .p3552 ( optlc_net_3572 ) , .p3553 ( optlc_net_3573 ) ,
+ .p3554 ( optlc_net_3574 ) , .p3555 ( optlc_net_3575 ) ,
+ .p3556 ( optlc_net_3576 ) , .p3557 ( optlc_net_3577 ) ,
+ .p3558 ( optlc_net_3578 ) , .p3559 ( optlc_net_3579 ) ,
+ .p3560 ( optlc_net_3580 ) , .p3561 ( optlc_net_3581 ) ,
+ .p3562 ( optlc_net_3582 ) , .p3563 ( optlc_net_3583 ) ,
+ .p3564 ( optlc_net_3584 ) , .p3565 ( optlc_net_3585 ) ,
+ .p3566 ( optlc_net_3586 ) , .p3567 ( optlc_net_3587 ) ,
+ .p3568 ( optlc_net_3588 ) , .p3569 ( optlc_net_3589 ) ,
+ .p3570 ( optlc_net_3590 ) , .p3571 ( optlc_net_3591 ) ,
+ .p3572 ( optlc_net_3592 ) , .p3573 ( optlc_net_3593 ) ,
+ .p3574 ( optlc_net_3594 ) , .p3575 ( optlc_net_3595 ) ,
+ .p3576 ( optlc_net_3596 ) , .p3577 ( optlc_net_3597 ) ,
+ .p3578 ( optlc_net_3598 ) , .p3579 ( optlc_net_3599 ) ,
+ .p3580 ( optlc_net_3600 ) , .p3581 ( optlc_net_3601 ) ,
+ .p3582 ( optlc_net_3602 ) , .p3583 ( optlc_net_3603 ) ,
+ .p3584 ( optlc_net_3604 ) , .p3585 ( optlc_net_3605 ) ,
+ .p3586 ( optlc_net_3606 ) , .p3587 ( optlc_net_3607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( io_oeb[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( io_oeb[1] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( io_oeb[2] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( io_oeb[3] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .HI ( io_oeb[12] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .HI ( io_oeb[25] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .HI ( io_oeb[26] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) ,
+ .HI ( io_oeb[36] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_10 ) ,
+ .HI ( io_oeb[37] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_39 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_40 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_41 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_42 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_43 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_44 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_46 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_47 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_48 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_74 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( optlc_net_75 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( optlc_net_76 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( optlc_net_77 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_79 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( optlc_net_78 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_80 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( optlc_net_79 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_81 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( optlc_net_80 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_82 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( optlc_net_81 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( optlc_net_82 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( optlc_net_83 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( optlc_net_84 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_86 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( optlc_net_85 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_87 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_87 ( .LO ( optlc_net_86 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( optlc_net_87 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( optlc_net_88 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( optlc_net_89 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( optlc_net_90 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( optlc_net_91 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( optlc_net_92 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( optlc_net_93 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( optlc_net_94 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( optlc_net_95 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( optlc_net_96 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( optlc_net_97 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( optlc_net_98 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( optlc_net_99 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( optlc_net_100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( optlc_net_101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( optlc_net_102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( optlc_net_103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( optlc_net_104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( optlc_net_105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( optlc_net_106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( optlc_net_107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( optlc_net_108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( optlc_net_109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( optlc_net_110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( optlc_net_111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( optlc_net_112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( optlc_net_113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( optlc_net_114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( optlc_net_115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( optlc_net_116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( optlc_net_117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( optlc_net_118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( optlc_net_119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( optlc_net_120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( optlc_net_121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( optlc_net_122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( optlc_net_123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( optlc_net_124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( optlc_net_125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( optlc_net_126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( optlc_net_127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( optlc_net_128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( optlc_net_129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( optlc_net_130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( optlc_net_131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( optlc_net_132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( optlc_net_133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( optlc_net_134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( optlc_net_135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( optlc_net_136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( optlc_net_137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( optlc_net_138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( optlc_net_139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( optlc_net_140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( optlc_net_141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( optlc_net_142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( optlc_net_143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( optlc_net_144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( optlc_net_145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( optlc_net_146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( optlc_net_147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( optlc_net_148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( optlc_net_149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( optlc_net_150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( optlc_net_151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( optlc_net_152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( optlc_net_153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( optlc_net_154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( optlc_net_155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( optlc_net_156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( optlc_net_157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( optlc_net_158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( optlc_net_159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( optlc_net_160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( optlc_net_161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_163 ( .LO ( optlc_net_162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( optlc_net_163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( optlc_net_164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( optlc_net_165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( optlc_net_166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( optlc_net_167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_169 ( .LO ( optlc_net_168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( optlc_net_169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( optlc_net_170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( optlc_net_171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( optlc_net_172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( optlc_net_173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( optlc_net_174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( optlc_net_175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( optlc_net_176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( optlc_net_177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( optlc_net_178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( optlc_net_179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( optlc_net_180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( optlc_net_181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_183 ( .LO ( optlc_net_182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( optlc_net_183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( optlc_net_184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( optlc_net_185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( optlc_net_186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( optlc_net_187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( optlc_net_188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( optlc_net_189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( optlc_net_190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( optlc_net_191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( optlc_net_192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( optlc_net_193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( optlc_net_194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( optlc_net_195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( optlc_net_196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_198 ( .LO ( optlc_net_197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( optlc_net_198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( optlc_net_199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( optlc_net_200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( optlc_net_201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( optlc_net_202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( optlc_net_203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( optlc_net_204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( optlc_net_205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( optlc_net_206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( optlc_net_207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( optlc_net_208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( optlc_net_209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( optlc_net_210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( optlc_net_211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( optlc_net_212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( optlc_net_213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( optlc_net_214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( optlc_net_215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( optlc_net_216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( optlc_net_217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( optlc_net_218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( optlc_net_219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( optlc_net_220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( optlc_net_221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( optlc_net_222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( optlc_net_223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( optlc_net_224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( optlc_net_225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( optlc_net_226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( optlc_net_227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( optlc_net_228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( optlc_net_229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_231 ( .LO ( optlc_net_230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( optlc_net_231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( optlc_net_232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_234 ( .LO ( optlc_net_233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( optlc_net_234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_236 ( .LO ( optlc_net_235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( optlc_net_236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_238 ( .LO ( optlc_net_237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( optlc_net_238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_240 ( .LO ( optlc_net_239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_241 ( .LO ( optlc_net_240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_242 ( .LO ( optlc_net_241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_243 ( .LO ( optlc_net_242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_244 ( .LO ( optlc_net_243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_245 ( .LO ( optlc_net_244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_246 ( .LO ( optlc_net_245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_247 ( .LO ( optlc_net_246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_248 ( .LO ( optlc_net_247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_249 ( .LO ( optlc_net_248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_250 ( .LO ( optlc_net_249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_251 ( .LO ( optlc_net_250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_252 ( .LO ( optlc_net_251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_253 ( .LO ( optlc_net_252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_254 ( .LO ( optlc_net_253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_255 ( .LO ( optlc_net_254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_256 ( .LO ( optlc_net_255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_257 ( .LO ( optlc_net_256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_258 ( .LO ( optlc_net_257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_259 ( .LO ( optlc_net_258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_260 ( .LO ( optlc_net_259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_261 ( .LO ( optlc_net_260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_262 ( .LO ( optlc_net_261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_263 ( .LO ( optlc_net_262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_264 ( .LO ( optlc_net_263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_265 ( .LO ( optlc_net_264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_266 ( .LO ( optlc_net_265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_267 ( .LO ( optlc_net_266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_268 ( .LO ( optlc_net_267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_269 ( .LO ( optlc_net_268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_274 ( .LO ( optlc_net_273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_280 ( .LO ( optlc_net_279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_284 ( .LO ( optlc_net_283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_295 ( .LO ( optlc_net_294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_298 ( .LO ( optlc_net_297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_311 ( .LO ( optlc_net_310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_313 ( .LO ( optlc_net_312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_315 ( .LO ( optlc_net_314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_327 ( .LO ( optlc_net_326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_330 ( .LO ( optlc_net_329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_334 ( .LO ( optlc_net_333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_336 ( .LO ( optlc_net_335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_342 ( .LO ( optlc_net_341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_351 ( .LO ( optlc_net_350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_353 ( .LO ( optlc_net_352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_355 ( .LO ( optlc_net_354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_365 ( .LO ( optlc_net_363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_367 ( .LO ( optlc_net_365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_401 ( .LO ( optlc_net_399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_403 ( .LO ( optlc_net_401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_413 ( .LO ( optlc_net_411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_415 ( .LO ( optlc_net_413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_773 ( .LO ( optlc_net_767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_935 ( .LO ( optlc_net_926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_943 ( .LO ( optlc_net_932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_960 ( .LO ( optlc_net_948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_966 ( .LO ( optlc_net_954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_967 ( .LO ( optlc_net_955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_971 ( .LO ( optlc_net_959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_986 ( .LO ( optlc_net_972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_996 ( .LO ( optlc_net_981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1009 ( .LO ( optlc_net_992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1011 ( .LO ( optlc_net_994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1012 ( .LO ( optlc_net_995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1014 ( .LO ( optlc_net_997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1015 ( .LO ( optlc_net_998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1016 ( .LO ( optlc_net_999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1017 ( .LO ( optlc_net_1000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1018 ( .LO ( optlc_net_1001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1019 ( .LO ( optlc_net_1002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1020 ( .LO ( optlc_net_1003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1021 ( .LO ( optlc_net_1004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1022 ( .LO ( optlc_net_1005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1023 ( .LO ( optlc_net_1006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1024 ( .LO ( optlc_net_1007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1025 ( .LO ( optlc_net_1008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1026 ( .LO ( optlc_net_1009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1027 ( .LO ( optlc_net_1010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1028 ( .LO ( optlc_net_1011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1029 ( .LO ( optlc_net_1012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1030 ( .LO ( optlc_net_1013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1031 ( .LO ( optlc_net_1014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1032 ( .LO ( optlc_net_1015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1033 ( .LO ( optlc_net_1016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1034 ( .LO ( optlc_net_1017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1035 ( .LO ( optlc_net_1018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1036 ( .LO ( optlc_net_1019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1037 ( .LO ( optlc_net_1020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1038 ( .LO ( optlc_net_1021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1039 ( .LO ( optlc_net_1022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1040 ( .LO ( optlc_net_1023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1041 ( .LO ( optlc_net_1024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1042 ( .LO ( optlc_net_1025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1043 ( .LO ( optlc_net_1026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1044 ( .LO ( optlc_net_1027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1045 ( .LO ( optlc_net_1028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1046 ( .LO ( optlc_net_1029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1047 ( .LO ( optlc_net_1030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1048 ( .LO ( optlc_net_1031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1049 ( .LO ( optlc_net_1032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1050 ( .LO ( optlc_net_1033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1051 ( .LO ( optlc_net_1034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1052 ( .LO ( optlc_net_1035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1053 ( .LO ( optlc_net_1036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1054 ( .LO ( optlc_net_1037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1055 ( .LO ( optlc_net_1038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1056 ( .LO ( optlc_net_1039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1057 ( .LO ( optlc_net_1040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1058 ( .LO ( optlc_net_1041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1059 ( .LO ( optlc_net_1042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1060 ( .LO ( optlc_net_1043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1061 ( .LO ( optlc_net_1044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1062 ( .LO ( optlc_net_1045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1063 ( .LO ( optlc_net_1046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1065 ( .LO ( optlc_net_1047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1066 ( .LO ( optlc_net_1048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1067 ( .LO ( optlc_net_1049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1068 ( .LO ( optlc_net_1050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1069 ( .LO ( optlc_net_1051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1070 ( .LO ( optlc_net_1052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1071 ( .LO ( optlc_net_1053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1072 ( .LO ( optlc_net_1054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1073 ( .LO ( optlc_net_1055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1074 ( .LO ( optlc_net_1056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1075 ( .LO ( optlc_net_1057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1076 ( .LO ( optlc_net_1058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1077 ( .LO ( optlc_net_1059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1078 ( .LO ( optlc_net_1060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1079 ( .LO ( optlc_net_1061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1080 ( .LO ( optlc_net_1062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1081 ( .LO ( optlc_net_1063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1082 ( .LO ( optlc_net_1064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1083 ( .LO ( optlc_net_1065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1084 ( .LO ( optlc_net_1066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1085 ( .LO ( optlc_net_1067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1086 ( .LO ( optlc_net_1068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1087 ( .LO ( optlc_net_1069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1088 ( .LO ( optlc_net_1070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1089 ( .LO ( optlc_net_1071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1090 ( .LO ( optlc_net_1072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1091 ( .LO ( optlc_net_1073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1093 ( .LO ( optlc_net_1074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1094 ( .LO ( optlc_net_1075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1095 ( .LO ( optlc_net_1076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1096 ( .LO ( optlc_net_1077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1097 ( .LO ( optlc_net_1078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1098 ( .LO ( optlc_net_1079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1100 ( .LO ( optlc_net_1080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1101 ( .LO ( optlc_net_1081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1102 ( .LO ( optlc_net_1082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1103 ( .LO ( optlc_net_1083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1104 ( .LO ( optlc_net_1084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1105 ( .LO ( optlc_net_1085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1106 ( .LO ( optlc_net_1086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1108 ( .LO ( optlc_net_1087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1109 ( .LO ( optlc_net_1088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1110 ( .LO ( optlc_net_1089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1111 ( .LO ( optlc_net_1090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1112 ( .LO ( optlc_net_1091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1113 ( .LO ( optlc_net_1092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1114 ( .LO ( optlc_net_1093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1115 ( .LO ( optlc_net_1094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1116 ( .LO ( optlc_net_1095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1117 ( .LO ( optlc_net_1096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1118 ( .LO ( optlc_net_1097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1119 ( .LO ( optlc_net_1098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1120 ( .LO ( optlc_net_1099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1121 ( .LO ( optlc_net_1100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1122 ( .LO ( optlc_net_1101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1123 ( .LO ( optlc_net_1102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1124 ( .LO ( optlc_net_1103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1125 ( .LO ( optlc_net_1104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1126 ( .LO ( optlc_net_1105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1127 ( .LO ( optlc_net_1106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1128 ( .LO ( optlc_net_1107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1129 ( .LO ( optlc_net_1108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1130 ( .LO ( optlc_net_1109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1131 ( .LO ( optlc_net_1110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1132 ( .LO ( optlc_net_1111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1133 ( .LO ( optlc_net_1112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1134 ( .LO ( optlc_net_1113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1135 ( .LO ( optlc_net_1114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1137 ( .LO ( optlc_net_1115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1138 ( .LO ( optlc_net_1116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1139 ( .LO ( optlc_net_1117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1140 ( .LO ( optlc_net_1118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1141 ( .LO ( optlc_net_1119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1142 ( .LO ( optlc_net_1120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1143 ( .LO ( optlc_net_1121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1144 ( .LO ( optlc_net_1122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1145 ( .LO ( optlc_net_1123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1146 ( .LO ( optlc_net_1124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1147 ( .LO ( optlc_net_1125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1149 ( .LO ( optlc_net_1126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1150 ( .LO ( optlc_net_1127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1151 ( .LO ( optlc_net_1128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1152 ( .LO ( optlc_net_1129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1153 ( .LO ( optlc_net_1130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1154 ( .LO ( optlc_net_1131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1155 ( .LO ( optlc_net_1132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1156 ( .LO ( optlc_net_1133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1157 ( .LO ( optlc_net_1134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1158 ( .LO ( optlc_net_1135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1160 ( .LO ( optlc_net_1136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1161 ( .LO ( optlc_net_1137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1162 ( .LO ( optlc_net_1138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1164 ( .LO ( optlc_net_1139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1165 ( .LO ( optlc_net_1140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1166 ( .LO ( optlc_net_1141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1167 ( .LO ( optlc_net_1142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1168 ( .LO ( optlc_net_1143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1169 ( .LO ( optlc_net_1144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1171 ( .LO ( optlc_net_1145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1173 ( .LO ( optlc_net_1146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1174 ( .LO ( optlc_net_1147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1175 ( .LO ( optlc_net_1148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1176 ( .LO ( optlc_net_1149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1177 ( .LO ( optlc_net_1150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1178 ( .LO ( optlc_net_1151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1179 ( .LO ( optlc_net_1152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1180 ( .LO ( optlc_net_1153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1181 ( .LO ( optlc_net_1154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1182 ( .LO ( optlc_net_1155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1183 ( .LO ( optlc_net_1156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1184 ( .LO ( optlc_net_1157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1185 ( .LO ( optlc_net_1158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1186 ( .LO ( optlc_net_1159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1188 ( .LO ( optlc_net_1160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1190 ( .LO ( optlc_net_1161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1191 ( .LO ( optlc_net_1162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1193 ( .LO ( optlc_net_1163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1194 ( .LO ( optlc_net_1164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1195 ( .LO ( optlc_net_1165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1196 ( .LO ( optlc_net_1166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1197 ( .LO ( optlc_net_1167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1198 ( .LO ( optlc_net_1168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1200 ( .LO ( optlc_net_1169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1201 ( .LO ( optlc_net_1170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1202 ( .LO ( optlc_net_1171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1203 ( .LO ( optlc_net_1172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1204 ( .LO ( optlc_net_1173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1205 ( .LO ( optlc_net_1174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1206 ( .LO ( optlc_net_1175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1207 ( .LO ( optlc_net_1176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1208 ( .LO ( optlc_net_1177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1210 ( .LO ( optlc_net_1178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1211 ( .LO ( optlc_net_1179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1213 ( .LO ( optlc_net_1180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1214 ( .LO ( optlc_net_1181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1215 ( .LO ( optlc_net_1182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1216 ( .LO ( optlc_net_1183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1218 ( .LO ( optlc_net_1184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1219 ( .LO ( optlc_net_1185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1220 ( .LO ( optlc_net_1186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1221 ( .LO ( optlc_net_1187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1222 ( .LO ( optlc_net_1188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1224 ( .LO ( optlc_net_1189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1225 ( .LO ( optlc_net_1190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1226 ( .LO ( optlc_net_1191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1227 ( .LO ( optlc_net_1192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1228 ( .LO ( optlc_net_1193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1229 ( .LO ( optlc_net_1194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1230 ( .LO ( optlc_net_1195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1232 ( .LO ( optlc_net_1196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1233 ( .LO ( optlc_net_1197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1235 ( .LO ( optlc_net_1198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1236 ( .LO ( optlc_net_1199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1238 ( .LO ( optlc_net_1200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1240 ( .LO ( optlc_net_1201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1241 ( .LO ( optlc_net_1202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1242 ( .LO ( optlc_net_1203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1244 ( .LO ( optlc_net_1204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1245 ( .LO ( optlc_net_1205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1246 ( .LO ( optlc_net_1206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1247 ( .LO ( optlc_net_1207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1248 ( .LO ( optlc_net_1208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1249 ( .LO ( optlc_net_1209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1250 ( .LO ( optlc_net_1210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1252 ( .LO ( optlc_net_1211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1253 ( .LO ( optlc_net_1212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1254 ( .LO ( optlc_net_1213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1256 ( .LO ( optlc_net_1214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1257 ( .LO ( optlc_net_1215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1258 ( .LO ( optlc_net_1216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1259 ( .LO ( optlc_net_1217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1260 ( .LO ( optlc_net_1218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1261 ( .LO ( optlc_net_1219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1263 ( .LO ( optlc_net_1220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1265 ( .LO ( optlc_net_1221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1266 ( .LO ( optlc_net_1222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1267 ( .LO ( optlc_net_1223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1269 ( .LO ( optlc_net_1224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1271 ( .LO ( optlc_net_1225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1272 ( .LO ( optlc_net_1226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1274 ( .LO ( optlc_net_1227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1275 ( .LO ( optlc_net_1228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1276 ( .LO ( optlc_net_1229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1277 ( .LO ( optlc_net_1230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1279 ( .LO ( optlc_net_1231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1280 ( .LO ( optlc_net_1232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1282 ( .LO ( optlc_net_1233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1284 ( .LO ( optlc_net_1234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1286 ( .LO ( optlc_net_1235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1288 ( .LO ( optlc_net_1236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1289 ( .LO ( optlc_net_1237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1290 ( .LO ( optlc_net_1238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1291 ( .LO ( optlc_net_1239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1292 ( .LO ( optlc_net_1240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1293 ( .LO ( optlc_net_1241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1295 ( .LO ( optlc_net_1242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1297 ( .LO ( optlc_net_1243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1298 ( .LO ( optlc_net_1244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1300 ( .LO ( optlc_net_1245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1301 ( .LO ( optlc_net_1246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1302 ( .LO ( optlc_net_1247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1304 ( .LO ( optlc_net_1248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1305 ( .LO ( optlc_net_1249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1307 ( .LO ( optlc_net_1250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1308 ( .LO ( optlc_net_1251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1309 ( .LO ( optlc_net_1252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1310 ( .LO ( optlc_net_1253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1311 ( .LO ( optlc_net_1254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1313 ( .LO ( optlc_net_1255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1315 ( .LO ( optlc_net_1256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1316 ( .LO ( optlc_net_1257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1317 ( .LO ( optlc_net_1258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1319 ( .LO ( optlc_net_1259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1321 ( .LO ( optlc_net_1260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1323 ( .LO ( optlc_net_1261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1324 ( .LO ( optlc_net_1262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1326 ( .LO ( optlc_net_1263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1327 ( .LO ( optlc_net_1264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1329 ( .LO ( optlc_net_1265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1330 ( .LO ( optlc_net_1266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1331 ( .LO ( optlc_net_1267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1333 ( .LO ( optlc_net_1268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1335 ( .LO ( optlc_net_1269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1337 ( .LO ( optlc_net_1270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1338 ( .LO ( optlc_net_1271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1339 ( .LO ( optlc_net_1272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1341 ( .LO ( optlc_net_1273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1342 ( .LO ( optlc_net_1274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1343 ( .LO ( optlc_net_1275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1344 ( .LO ( optlc_net_1276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1345 ( .LO ( optlc_net_1277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1346 ( .LO ( optlc_net_1278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1347 ( .LO ( optlc_net_1279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1348 ( .LO ( optlc_net_1280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1349 ( .LO ( optlc_net_1281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1350 ( .LO ( optlc_net_1282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1351 ( .LO ( optlc_net_1283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1352 ( .LO ( optlc_net_1284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1353 ( .LO ( optlc_net_1285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1354 ( .LO ( optlc_net_1286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1355 ( .LO ( optlc_net_1287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1356 ( .LO ( optlc_net_1288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1357 ( .LO ( optlc_net_1289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1358 ( .LO ( optlc_net_1290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1359 ( .LO ( optlc_net_1291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1360 ( .LO ( optlc_net_1292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1361 ( .LO ( optlc_net_1293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1362 ( .LO ( optlc_net_1294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1363 ( .LO ( optlc_net_1295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1364 ( .LO ( optlc_net_1296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1365 ( .LO ( optlc_net_1297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1366 ( .LO ( optlc_net_1298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1367 ( .LO ( optlc_net_1299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1368 ( .LO ( optlc_net_1300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1369 ( .LO ( optlc_net_1301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1370 ( .LO ( optlc_net_1302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1371 ( .LO ( optlc_net_1303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1372 ( .LO ( optlc_net_1304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1373 ( .LO ( optlc_net_1305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1374 ( .LO ( optlc_net_1306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1375 ( .LO ( optlc_net_1307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1376 ( .LO ( optlc_net_1308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1377 ( .LO ( optlc_net_1309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1378 ( .LO ( optlc_net_1310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1379 ( .LO ( optlc_net_1311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1380 ( .LO ( optlc_net_1312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1381 ( .LO ( optlc_net_1313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1382 ( .LO ( optlc_net_1314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1383 ( .LO ( optlc_net_1315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1384 ( .LO ( optlc_net_1316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1385 ( .LO ( optlc_net_1317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1386 ( .LO ( optlc_net_1318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1387 ( .LO ( optlc_net_1319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1388 ( .LO ( optlc_net_1320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1389 ( .LO ( optlc_net_1321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1390 ( .LO ( optlc_net_1322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1391 ( .LO ( optlc_net_1323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1392 ( .LO ( optlc_net_1324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1393 ( .LO ( optlc_net_1325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1394 ( .LO ( optlc_net_1326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1395 ( .LO ( optlc_net_1327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1396 ( .LO ( optlc_net_1328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1397 ( .LO ( optlc_net_1329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1398 ( .LO ( optlc_net_1330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1399 ( .LO ( optlc_net_1331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1400 ( .LO ( optlc_net_1332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1401 ( .LO ( optlc_net_1333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1402 ( .LO ( optlc_net_1334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1403 ( .LO ( optlc_net_1335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1404 ( .LO ( optlc_net_1336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1405 ( .LO ( optlc_net_1337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1406 ( .LO ( optlc_net_1338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1407 ( .LO ( optlc_net_1339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1408 ( .LO ( optlc_net_1340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1409 ( .LO ( optlc_net_1341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1410 ( .LO ( optlc_net_1342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1411 ( .LO ( optlc_net_1343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1412 ( .LO ( optlc_net_1344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1413 ( .LO ( optlc_net_1345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1414 ( .LO ( optlc_net_1346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1415 ( .LO ( optlc_net_1347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1416 ( .LO ( optlc_net_1348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1417 ( .LO ( optlc_net_1349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1418 ( .LO ( optlc_net_1350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1419 ( .LO ( optlc_net_1351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1420 ( .LO ( optlc_net_1352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1421 ( .LO ( optlc_net_1353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1422 ( .LO ( optlc_net_1354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1423 ( .LO ( optlc_net_1355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1424 ( .LO ( optlc_net_1356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1426 ( .LO ( optlc_net_1357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1427 ( .LO ( optlc_net_1358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1428 ( .LO ( optlc_net_1359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1429 ( .LO ( optlc_net_1360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1430 ( .LO ( optlc_net_1361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1431 ( .LO ( optlc_net_1362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1432 ( .LO ( optlc_net_1363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1433 ( .LO ( optlc_net_1364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1434 ( .LO ( optlc_net_1365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1435 ( .LO ( optlc_net_1366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1436 ( .LO ( optlc_net_1367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1437 ( .LO ( optlc_net_1368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1438 ( .LO ( optlc_net_1369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1439 ( .LO ( optlc_net_1370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1440 ( .LO ( optlc_net_1371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1441 ( .LO ( optlc_net_1372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1442 ( .LO ( optlc_net_1373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1443 ( .LO ( optlc_net_1374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1444 ( .LO ( optlc_net_1375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1445 ( .LO ( optlc_net_1376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1446 ( .LO ( optlc_net_1377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1447 ( .LO ( optlc_net_1378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1448 ( .LO ( optlc_net_1379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1449 ( .LO ( optlc_net_1380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1450 ( .LO ( optlc_net_1381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1451 ( .LO ( optlc_net_1382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1452 ( .LO ( optlc_net_1383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1453 ( .LO ( optlc_net_1384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1454 ( .LO ( optlc_net_1385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1455 ( .LO ( optlc_net_1386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1456 ( .LO ( optlc_net_1387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1457 ( .LO ( optlc_net_1388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1458 ( .LO ( optlc_net_1389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1459 ( .LO ( optlc_net_1390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1461 ( .LO ( optlc_net_1391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1466 ( .LO ( optlc_net_1395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1467 ( .LO ( optlc_net_1396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1469 ( .LO ( optlc_net_1397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1470 ( .LO ( optlc_net_1398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1471 ( .LO ( optlc_net_1399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1473 ( .LO ( optlc_net_1401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1474 ( .LO ( optlc_net_1402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1475 ( .LO ( optlc_net_1403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1477 ( .LO ( optlc_net_1404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1478 ( .LO ( optlc_net_1405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1479 ( .LO ( optlc_net_1406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1480 ( .LO ( optlc_net_1407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1481 ( .LO ( optlc_net_1408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1482 ( .LO ( optlc_net_1409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1485 ( .LO ( optlc_net_1412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1487 ( .LO ( optlc_net_1413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1488 ( .LO ( optlc_net_1414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1491 ( .LO ( optlc_net_1417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1492 ( .LO ( optlc_net_1418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1494 ( .LO ( optlc_net_1419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1495 ( .LO ( optlc_net_1420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1496 ( .LO ( optlc_net_1421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1497 ( .LO ( optlc_net_1422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1498 ( .LO ( optlc_net_1423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1500 ( .LO ( optlc_net_1424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1501 ( .LO ( optlc_net_1425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1503 ( .LO ( optlc_net_1426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1504 ( .LO ( optlc_net_1427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1505 ( .LO ( optlc_net_1428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1507 ( .LO ( optlc_net_1429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1508 ( .LO ( optlc_net_1430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1509 ( .LO ( optlc_net_1431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1510 ( .LO ( optlc_net_1432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1511 ( .LO ( optlc_net_1433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1513 ( .LO ( optlc_net_1434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1514 ( .LO ( optlc_net_1435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1515 ( .LO ( optlc_net_1436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1517 ( .LO ( optlc_net_1437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1518 ( .LO ( optlc_net_1438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1519 ( .LO ( optlc_net_1439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1521 ( .LO ( optlc_net_1440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1522 ( .LO ( optlc_net_1441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1523 ( .LO ( optlc_net_1442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1524 ( .LO ( optlc_net_1443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1525 ( .LO ( optlc_net_1444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1526 ( .LO ( optlc_net_1445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1527 ( .LO ( optlc_net_1446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1528 ( .LO ( optlc_net_1447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1529 ( .LO ( optlc_net_1448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1531 ( .LO ( optlc_net_1449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1532 ( .LO ( optlc_net_1450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1533 ( .LO ( optlc_net_1451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1534 ( .LO ( optlc_net_1452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1536 ( .LO ( optlc_net_1453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1537 ( .LO ( optlc_net_1454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1538 ( .LO ( optlc_net_1455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1539 ( .LO ( optlc_net_1456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1540 ( .LO ( optlc_net_1457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1541 ( .LO ( optlc_net_1458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1543 ( .LO ( optlc_net_1459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1545 ( .LO ( optlc_net_1460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1547 ( .LO ( optlc_net_1461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1549 ( .LO ( optlc_net_1462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1550 ( .LO ( optlc_net_1463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1551 ( .LO ( optlc_net_1464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1553 ( .LO ( optlc_net_1465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1555 ( .LO ( optlc_net_1466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1556 ( .LO ( optlc_net_1467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1558 ( .LO ( optlc_net_1468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1560 ( .LO ( optlc_net_1469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1562 ( .LO ( optlc_net_1470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1563 ( .LO ( optlc_net_1471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1564 ( .LO ( optlc_net_1472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1565 ( .LO ( optlc_net_1473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1567 ( .LO ( optlc_net_1474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1568 ( .LO ( optlc_net_1475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1569 ( .LO ( optlc_net_1476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1570 ( .LO ( optlc_net_1477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1571 ( .LO ( optlc_net_1478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1572 ( .LO ( optlc_net_1479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1574 ( .LO ( optlc_net_1480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1575 ( .LO ( optlc_net_1481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1576 ( .LO ( optlc_net_1482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1577 ( .LO ( optlc_net_1483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1579 ( .LO ( optlc_net_1484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1580 ( .LO ( optlc_net_1485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1581 ( .LO ( optlc_net_1486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1582 ( .LO ( optlc_net_1487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1584 ( .LO ( optlc_net_1488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1585 ( .LO ( optlc_net_1489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1587 ( .LO ( optlc_net_1490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1588 ( .LO ( optlc_net_1491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1590 ( .LO ( optlc_net_1492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1592 ( .LO ( optlc_net_1493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1594 ( .LO ( optlc_net_1494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1595 ( .LO ( optlc_net_1495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1597 ( .LO ( optlc_net_1496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1599 ( .LO ( optlc_net_1497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1600 ( .LO ( optlc_net_1498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1601 ( .LO ( optlc_net_1499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1602 ( .LO ( optlc_net_1500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1604 ( .LO ( optlc_net_1501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1605 ( .LO ( optlc_net_1502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1607 ( .LO ( optlc_net_1503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1608 ( .LO ( optlc_net_1504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1610 ( .LO ( optlc_net_1505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1611 ( .LO ( optlc_net_1506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1613 ( .LO ( optlc_net_1507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1614 ( .LO ( optlc_net_1508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1615 ( .LO ( optlc_net_1509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1616 ( .LO ( optlc_net_1510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1619 ( .LO ( optlc_net_1511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1621 ( .LO ( optlc_net_1512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1622 ( .LO ( optlc_net_1513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1623 ( .LO ( optlc_net_1514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1624 ( .LO ( optlc_net_1515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1626 ( .LO ( optlc_net_1516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1627 ( .LO ( optlc_net_1517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1629 ( .LO ( optlc_net_1518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1630 ( .LO ( optlc_net_1519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1631 ( .LO ( optlc_net_1520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1632 ( .LO ( optlc_net_1521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1633 ( .LO ( optlc_net_1522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1634 ( .LO ( optlc_net_1523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1636 ( .LO ( optlc_net_1524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1637 ( .LO ( optlc_net_1525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1639 ( .LO ( optlc_net_1526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1641 ( .LO ( optlc_net_1527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1642 ( .LO ( optlc_net_1528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1644 ( .LO ( optlc_net_1529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1646 ( .LO ( optlc_net_1530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1647 ( .LO ( optlc_net_1531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1648 ( .LO ( optlc_net_1532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1650 ( .LO ( optlc_net_1533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1651 ( .LO ( optlc_net_1534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1652 ( .LO ( optlc_net_1535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1653 ( .LO ( optlc_net_1536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1654 ( .LO ( optlc_net_1537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1655 ( .LO ( optlc_net_1538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1657 ( .LO ( optlc_net_1539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1659 ( .LO ( optlc_net_1540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1660 ( .LO ( optlc_net_1541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1662 ( .LO ( optlc_net_1542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1663 ( .LO ( optlc_net_1543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1665 ( .LO ( optlc_net_1544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1666 ( .LO ( optlc_net_1545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1668 ( .LO ( optlc_net_1546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1670 ( .LO ( optlc_net_1547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1672 ( .LO ( optlc_net_1548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1673 ( .LO ( optlc_net_1549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1675 ( .LO ( optlc_net_1550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1677 ( .LO ( optlc_net_1551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1679 ( .LO ( optlc_net_1552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1681 ( .LO ( optlc_net_1553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1682 ( .LO ( optlc_net_1554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1683 ( .LO ( optlc_net_1555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1685 ( .LO ( optlc_net_1556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1686 ( .LO ( optlc_net_1557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1687 ( .LO ( optlc_net_1558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1689 ( .LO ( optlc_net_1559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1690 ( .LO ( optlc_net_1560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1691 ( .LO ( optlc_net_1561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1692 ( .LO ( optlc_net_1562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1693 ( .LO ( optlc_net_1563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1695 ( .LO ( optlc_net_1564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1697 ( .LO ( optlc_net_1565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1699 ( .LO ( optlc_net_1566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1701 ( .LO ( optlc_net_1567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1703 ( .LO ( optlc_net_1568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1704 ( .LO ( optlc_net_1569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1705 ( .LO ( optlc_net_1570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1706 ( .LO ( optlc_net_1571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1707 ( .LO ( optlc_net_1572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1709 ( .LO ( optlc_net_1573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1711 ( .LO ( optlc_net_1574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1712 ( .LO ( optlc_net_1575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1714 ( .LO ( optlc_net_1576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1715 ( .LO ( optlc_net_1577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1716 ( .LO ( optlc_net_1578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1717 ( .LO ( optlc_net_1579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1719 ( .LO ( optlc_net_1580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1720 ( .LO ( optlc_net_1581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1721 ( .LO ( optlc_net_1582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1723 ( .LO ( optlc_net_1583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1724 ( .LO ( optlc_net_1584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1725 ( .LO ( optlc_net_1585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1726 ( .LO ( optlc_net_1586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1728 ( .LO ( optlc_net_1587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1730 ( .LO ( optlc_net_1588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1732 ( .LO ( optlc_net_1589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1733 ( .LO ( optlc_net_1590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1735 ( .LO ( optlc_net_1591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1737 ( .LO ( optlc_net_1592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1738 ( .LO ( optlc_net_1593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1739 ( .LO ( optlc_net_1594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1741 ( .LO ( optlc_net_1595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1742 ( .LO ( optlc_net_1596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1744 ( .LO ( optlc_net_1597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1746 ( .LO ( optlc_net_1598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1748 ( .LO ( optlc_net_1599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1750 ( .LO ( optlc_net_1600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1751 ( .LO ( optlc_net_1601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1753 ( .LO ( optlc_net_1602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1754 ( .LO ( optlc_net_1603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1755 ( .LO ( optlc_net_1604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1756 ( .LO ( optlc_net_1605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1757 ( .LO ( optlc_net_1606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1758 ( .LO ( optlc_net_1607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1760 ( .LO ( optlc_net_1608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1761 ( .LO ( optlc_net_1609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1762 ( .LO ( optlc_net_1610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1764 ( .LO ( optlc_net_1611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1766 ( .LO ( optlc_net_1612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1767 ( .LO ( optlc_net_1613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1769 ( .LO ( optlc_net_1614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1771 ( .LO ( optlc_net_1615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1772 ( .LO ( optlc_net_1616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1774 ( .LO ( optlc_net_1617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1775 ( .LO ( optlc_net_1618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1777 ( .LO ( optlc_net_1619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1779 ( .LO ( optlc_net_1620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1781 ( .LO ( optlc_net_1621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1783 ( .LO ( optlc_net_1622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1784 ( .LO ( optlc_net_1623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1785 ( .LO ( optlc_net_1624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1786 ( .LO ( optlc_net_1625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1787 ( .LO ( optlc_net_1626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1788 ( .LO ( optlc_net_1627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1789 ( .LO ( optlc_net_1628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1790 ( .LO ( optlc_net_1629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1792 ( .LO ( optlc_net_1630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1794 ( .LO ( optlc_net_1631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1796 ( .LO ( optlc_net_1632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1797 ( .LO ( optlc_net_1633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1798 ( .LO ( optlc_net_1634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1799 ( .LO ( optlc_net_1635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1800 ( .LO ( optlc_net_1636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1801 ( .LO ( optlc_net_1637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1802 ( .LO ( optlc_net_1638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1803 ( .LO ( optlc_net_1639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1804 ( .LO ( optlc_net_1640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1805 ( .LO ( optlc_net_1641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1806 ( .LO ( optlc_net_1642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1807 ( .LO ( optlc_net_1643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1808 ( .LO ( optlc_net_1644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1809 ( .LO ( optlc_net_1645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1810 ( .LO ( optlc_net_1646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1811 ( .LO ( optlc_net_1647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1812 ( .LO ( optlc_net_1648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1813 ( .LO ( optlc_net_1649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1814 ( .LO ( optlc_net_1650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1815 ( .LO ( optlc_net_1651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1816 ( .LO ( optlc_net_1652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1817 ( .LO ( optlc_net_1653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1818 ( .LO ( optlc_net_1654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1819 ( .LO ( optlc_net_1655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1820 ( .LO ( optlc_net_1656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1821 ( .LO ( optlc_net_1657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1822 ( .LO ( optlc_net_1658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1823 ( .LO ( optlc_net_1659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1824 ( .LO ( optlc_net_1660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1825 ( .LO ( optlc_net_1661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1826 ( .LO ( optlc_net_1662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1827 ( .LO ( optlc_net_1663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1828 ( .LO ( optlc_net_1664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1829 ( .LO ( optlc_net_1665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1830 ( .LO ( optlc_net_1666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1831 ( .LO ( optlc_net_1667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1832 ( .LO ( optlc_net_1668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1833 ( .LO ( optlc_net_1669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1834 ( .LO ( optlc_net_1670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1835 ( .LO ( optlc_net_1671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1836 ( .LO ( optlc_net_1672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1837 ( .LO ( optlc_net_1673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1838 ( .LO ( optlc_net_1674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1839 ( .LO ( optlc_net_1675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1840 ( .LO ( optlc_net_1676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1841 ( .LO ( optlc_net_1677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1842 ( .LO ( optlc_net_1678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1843 ( .LO ( optlc_net_1679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1844 ( .LO ( optlc_net_1680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1846 ( .LO ( optlc_net_1681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1847 ( .LO ( optlc_net_1682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1848 ( .LO ( optlc_net_1683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1849 ( .LO ( optlc_net_1684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1850 ( .LO ( optlc_net_1685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1851 ( .LO ( optlc_net_1686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1852 ( .LO ( optlc_net_1687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1853 ( .LO ( optlc_net_1688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1854 ( .LO ( optlc_net_1689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1855 ( .LO ( optlc_net_1690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1856 ( .LO ( optlc_net_1691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1857 ( .LO ( optlc_net_1692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1858 ( .LO ( optlc_net_1693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1859 ( .LO ( optlc_net_1694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1860 ( .LO ( optlc_net_1695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1861 ( .LO ( optlc_net_1696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1862 ( .LO ( optlc_net_1697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1863 ( .LO ( optlc_net_1698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1864 ( .LO ( optlc_net_1699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1865 ( .LO ( optlc_net_1700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1866 ( .LO ( optlc_net_1701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1867 ( .LO ( optlc_net_1702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1868 ( .LO ( optlc_net_1703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1869 ( .LO ( optlc_net_1704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1870 ( .LO ( optlc_net_1705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1871 ( .LO ( optlc_net_1706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1872 ( .LO ( optlc_net_1707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1873 ( .LO ( optlc_net_1708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1874 ( .LO ( optlc_net_1709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1875 ( .LO ( optlc_net_1710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1876 ( .LO ( optlc_net_1711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1877 ( .LO ( optlc_net_1712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1878 ( .LO ( optlc_net_1713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1879 ( .LO ( optlc_net_1714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1880 ( .LO ( optlc_net_1715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1881 ( .LO ( optlc_net_1716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1882 ( .LO ( optlc_net_1717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1883 ( .LO ( optlc_net_1718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1884 ( .LO ( optlc_net_1719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1885 ( .LO ( optlc_net_1720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1886 ( .LO ( optlc_net_1721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1887 ( .LO ( optlc_net_1722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1888 ( .LO ( optlc_net_1723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1889 ( .LO ( optlc_net_1724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1890 ( .LO ( optlc_net_1725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1891 ( .LO ( optlc_net_1726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1892 ( .LO ( optlc_net_1727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1893 ( .LO ( optlc_net_1728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1894 ( .LO ( optlc_net_1729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1895 ( .LO ( optlc_net_1730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1896 ( .LO ( optlc_net_1731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1897 ( .LO ( optlc_net_1732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1898 ( .LO ( optlc_net_1733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1899 ( .LO ( optlc_net_1734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1900 ( .LO ( optlc_net_1735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1901 ( .LO ( optlc_net_1736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1902 ( .LO ( optlc_net_1737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1903 ( .LO ( optlc_net_1738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1904 ( .LO ( optlc_net_1739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1905 ( .LO ( optlc_net_1740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1906 ( .LO ( optlc_net_1741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1907 ( .LO ( optlc_net_1742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1908 ( .LO ( optlc_net_1743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1910 ( .LO ( optlc_net_1744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1911 ( .LO ( optlc_net_1745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1912 ( .LO ( optlc_net_1746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1913 ( .LO ( optlc_net_1747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1915 ( .LO ( optlc_net_1748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1916 ( .LO ( optlc_net_1749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1917 ( .LO ( optlc_net_1750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1919 ( .LO ( optlc_net_1751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1920 ( .LO ( optlc_net_1752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1922 ( .LO ( optlc_net_1753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1923 ( .LO ( optlc_net_1754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1924 ( .LO ( optlc_net_1755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1925 ( .LO ( optlc_net_1756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1926 ( .LO ( optlc_net_1757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1927 ( .LO ( optlc_net_1758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1928 ( .LO ( optlc_net_1759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1929 ( .LO ( optlc_net_1760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1930 ( .LO ( optlc_net_1761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1931 ( .LO ( optlc_net_1762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1932 ( .LO ( optlc_net_1763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1933 ( .LO ( optlc_net_1764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1934 ( .LO ( optlc_net_1765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1935 ( .LO ( optlc_net_1766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1936 ( .LO ( optlc_net_1767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1937 ( .LO ( optlc_net_1768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1939 ( .LO ( optlc_net_1769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1940 ( .LO ( optlc_net_1770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1941 ( .LO ( optlc_net_1771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1942 ( .LO ( optlc_net_1772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1943 ( .LO ( optlc_net_1773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1945 ( .LO ( optlc_net_1774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1947 ( .LO ( optlc_net_1775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1948 ( .LO ( optlc_net_1776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1949 ( .LO ( optlc_net_1777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1951 ( .LO ( optlc_net_1778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1953 ( .LO ( optlc_net_1779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1954 ( .LO ( optlc_net_1780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1956 ( .LO ( optlc_net_1781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1957 ( .LO ( optlc_net_1782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1958 ( .LO ( optlc_net_1783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1959 ( .LO ( optlc_net_1784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1960 ( .LO ( optlc_net_1785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1962 ( .LO ( optlc_net_1786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1963 ( .LO ( optlc_net_1787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1964 ( .LO ( optlc_net_1788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1965 ( .LO ( optlc_net_1789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1967 ( .LO ( optlc_net_1790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1969 ( .LO ( optlc_net_1791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1971 ( .LO ( optlc_net_1792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1973 ( .LO ( optlc_net_1793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1974 ( .LO ( optlc_net_1794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1975 ( .LO ( optlc_net_1795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1976 ( .LO ( optlc_net_1796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1977 ( .LO ( optlc_net_1797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1978 ( .LO ( optlc_net_1798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1979 ( .LO ( optlc_net_1799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1980 ( .LO ( optlc_net_1800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1981 ( .LO ( optlc_net_1801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1983 ( .LO ( optlc_net_1802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1984 ( .LO ( optlc_net_1803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1985 ( .LO ( optlc_net_1804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1986 ( .LO ( optlc_net_1805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1988 ( .LO ( optlc_net_1806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1990 ( .LO ( optlc_net_1807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1991 ( .LO ( optlc_net_1808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1993 ( .LO ( optlc_net_1809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1994 ( .LO ( optlc_net_1810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1995 ( .LO ( optlc_net_1811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1997 ( .LO ( optlc_net_1812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1998 ( .LO ( optlc_net_1813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1999 ( .LO ( optlc_net_1814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2001 ( .LO ( optlc_net_1815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2002 ( .LO ( optlc_net_1816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2004 ( .LO ( optlc_net_1817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2005 ( .LO ( optlc_net_1818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2007 ( .LO ( optlc_net_1819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2009 ( .LO ( optlc_net_1820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2010 ( .LO ( optlc_net_1821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2011 ( .LO ( optlc_net_1822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2012 ( .LO ( optlc_net_1823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2014 ( .LO ( optlc_net_1824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2016 ( .LO ( optlc_net_1825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2018 ( .LO ( optlc_net_1826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2019 ( .LO ( optlc_net_1827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2021 ( .LO ( optlc_net_1828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2022 ( .LO ( optlc_net_1829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2024 ( .LO ( optlc_net_1830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2026 ( .LO ( optlc_net_1831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2028 ( .LO ( optlc_net_1832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2030 ( .LO ( optlc_net_1833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2031 ( .LO ( optlc_net_1834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2032 ( .LO ( optlc_net_1835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2033 ( .LO ( optlc_net_1836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2035 ( .LO ( optlc_net_1837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2037 ( .LO ( optlc_net_1838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2040 ( .LO ( optlc_net_1839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2041 ( .LO ( optlc_net_1840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2043 ( .LO ( optlc_net_1841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2045 ( .LO ( optlc_net_1842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2046 ( .LO ( optlc_net_1843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2047 ( .LO ( optlc_net_1844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2049 ( .LO ( optlc_net_1845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2051 ( .LO ( optlc_net_1846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2053 ( .LO ( optlc_net_1847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2055 ( .LO ( optlc_net_1848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2056 ( .LO ( optlc_net_1849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2057 ( .LO ( optlc_net_1850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2058 ( .LO ( optlc_net_1851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2059 ( .LO ( optlc_net_1852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2060 ( .LO ( optlc_net_1853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2061 ( .LO ( optlc_net_1854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2063 ( .LO ( optlc_net_1855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2064 ( .LO ( optlc_net_1856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2066 ( .LO ( optlc_net_1857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2067 ( .LO ( optlc_net_1858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2069 ( .LO ( optlc_net_1859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2071 ( .LO ( optlc_net_1860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2073 ( .LO ( optlc_net_1861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2074 ( .LO ( optlc_net_1862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2076 ( .LO ( optlc_net_1863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2077 ( .LO ( optlc_net_1864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2078 ( .LO ( optlc_net_1865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2080 ( .LO ( optlc_net_1866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2081 ( .LO ( optlc_net_1867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2083 ( .LO ( optlc_net_1868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2085 ( .LO ( optlc_net_1869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2087 ( .LO ( optlc_net_1870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2088 ( .LO ( optlc_net_1871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2090 ( .LO ( optlc_net_1872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2091 ( .LO ( optlc_net_1873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2092 ( .LO ( optlc_net_1874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2093 ( .LO ( optlc_net_1875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2095 ( .LO ( optlc_net_1876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2097 ( .LO ( optlc_net_1877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2098 ( .LO ( optlc_net_1878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2099 ( .LO ( optlc_net_1879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2101 ( .LO ( optlc_net_1880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2102 ( .LO ( optlc_net_1881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2103 ( .LO ( optlc_net_1882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2104 ( .LO ( optlc_net_1883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2106 ( .LO ( optlc_net_1884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2107 ( .LO ( optlc_net_1885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2108 ( .LO ( optlc_net_1886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2109 ( .LO ( optlc_net_1887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2111 ( .LO ( optlc_net_1888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2113 ( .LO ( optlc_net_1889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2114 ( .LO ( optlc_net_1890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2115 ( .LO ( optlc_net_1891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2116 ( .LO ( optlc_net_1892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2118 ( .LO ( optlc_net_1893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2120 ( .LO ( optlc_net_1894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2121 ( .LO ( optlc_net_1895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2122 ( .LO ( optlc_net_1896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2124 ( .LO ( optlc_net_1897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2126 ( .LO ( optlc_net_1898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2128 ( .LO ( optlc_net_1899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2129 ( .LO ( optlc_net_1900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2132 ( .LO ( optlc_net_1902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2134 ( .LO ( optlc_net_1904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2140 ( .LO ( optlc_net_1908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2142 ( .LO ( optlc_net_1909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2144 ( .LO ( optlc_net_1910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2147 ( .LO ( optlc_net_1912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2149 ( .LO ( optlc_net_1914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2154 ( .LO ( optlc_net_1918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2156 ( .LO ( optlc_net_1919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2158 ( .LO ( optlc_net_1920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2160 ( .LO ( optlc_net_1921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2168 ( .LO ( optlc_net_1927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2182 ( .LO ( optlc_net_1936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2203 ( .LO ( optlc_net_1948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2208 ( .LO ( optlc_net_1953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_1959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_1960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_1961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2221 ( .LO ( optlc_net_1962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_1963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_1964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_1965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_1966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2227 ( .LO ( optlc_net_1967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2228 ( .LO ( optlc_net_1968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2230 ( .LO ( optlc_net_1969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2232 ( .LO ( optlc_net_1970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_1971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2234 ( .LO ( optlc_net_1972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_1973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_1974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_1975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_1976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_1977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_1978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2241 ( .LO ( optlc_net_1979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_1980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_1981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2244 ( .LO ( optlc_net_1982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2245 ( .LO ( optlc_net_1983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2246 ( .LO ( optlc_net_1984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_1985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_1986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2249 ( .LO ( optlc_net_1987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2250 ( .LO ( optlc_net_1988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2251 ( .LO ( optlc_net_1989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2252 ( .LO ( optlc_net_1990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2253 ( .LO ( optlc_net_1991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2254 ( .LO ( optlc_net_1992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2255 ( .LO ( optlc_net_1993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2256 ( .LO ( optlc_net_1994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2257 ( .LO ( optlc_net_1995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2258 ( .LO ( optlc_net_1996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2259 ( .LO ( optlc_net_1997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2260 ( .LO ( optlc_net_1998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2261 ( .LO ( optlc_net_1999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2262 ( .LO ( optlc_net_2000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2263 ( .LO ( optlc_net_2001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2264 ( .LO ( optlc_net_2002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2265 ( .LO ( optlc_net_2003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2266 ( .LO ( optlc_net_2004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2267 ( .LO ( optlc_net_2005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2268 ( .LO ( optlc_net_2006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2269 ( .LO ( optlc_net_2007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2270 ( .LO ( optlc_net_2008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2271 ( .LO ( optlc_net_2009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2272 ( .LO ( optlc_net_2010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2273 ( .LO ( optlc_net_2011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2274 ( .LO ( optlc_net_2012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2275 ( .LO ( optlc_net_2013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2276 ( .LO ( optlc_net_2014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2277 ( .LO ( optlc_net_2015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2278 ( .LO ( optlc_net_2016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2279 ( .LO ( optlc_net_2017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2280 ( .LO ( optlc_net_2018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2281 ( .LO ( optlc_net_2019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2282 ( .LO ( optlc_net_2020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2283 ( .LO ( optlc_net_2021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2284 ( .LO ( optlc_net_2022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2285 ( .LO ( optlc_net_2023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2286 ( .LO ( optlc_net_2024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2287 ( .LO ( optlc_net_2025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2288 ( .LO ( optlc_net_2026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2289 ( .LO ( optlc_net_2027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2290 ( .LO ( optlc_net_2028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2291 ( .LO ( optlc_net_2029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2292 ( .LO ( optlc_net_2030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2293 ( .LO ( optlc_net_2031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2294 ( .LO ( optlc_net_2032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2295 ( .LO ( optlc_net_2033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2296 ( .LO ( optlc_net_2034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2297 ( .LO ( optlc_net_2035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2298 ( .LO ( optlc_net_2036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2299 ( .LO ( optlc_net_2037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2300 ( .LO ( optlc_net_2038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2301 ( .LO ( optlc_net_2039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2302 ( .LO ( optlc_net_2040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2304 ( .LO ( optlc_net_2041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2305 ( .LO ( optlc_net_2042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2306 ( .LO ( optlc_net_2043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2307 ( .LO ( optlc_net_2044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2308 ( .LO ( optlc_net_2045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2309 ( .LO ( optlc_net_2046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2310 ( .LO ( optlc_net_2047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2311 ( .LO ( optlc_net_2048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2312 ( .LO ( optlc_net_2049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2313 ( .LO ( optlc_net_2050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2314 ( .LO ( optlc_net_2051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2315 ( .LO ( optlc_net_2052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2316 ( .LO ( optlc_net_2053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2317 ( .LO ( optlc_net_2054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2318 ( .LO ( optlc_net_2055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2319 ( .LO ( optlc_net_2056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2320 ( .LO ( optlc_net_2057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2321 ( .LO ( optlc_net_2058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2322 ( .LO ( optlc_net_2059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2323 ( .LO ( optlc_net_2060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2324 ( .LO ( optlc_net_2061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2325 ( .LO ( optlc_net_2062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2326 ( .LO ( optlc_net_2063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2327 ( .LO ( optlc_net_2064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2328 ( .LO ( optlc_net_2065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2329 ( .LO ( optlc_net_2066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2330 ( .LO ( optlc_net_2067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2331 ( .LO ( optlc_net_2068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2332 ( .LO ( optlc_net_2069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2333 ( .LO ( optlc_net_2070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2334 ( .LO ( optlc_net_2071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2335 ( .LO ( optlc_net_2072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2336 ( .LO ( optlc_net_2073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2337 ( .LO ( optlc_net_2074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2338 ( .LO ( optlc_net_2075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2339 ( .LO ( optlc_net_2076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2340 ( .LO ( optlc_net_2077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2341 ( .LO ( optlc_net_2078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2343 ( .LO ( optlc_net_2079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2344 ( .LO ( optlc_net_2080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2346 ( .LO ( optlc_net_2081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2347 ( .LO ( optlc_net_2082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2348 ( .LO ( optlc_net_2083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2349 ( .LO ( optlc_net_2084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2350 ( .LO ( optlc_net_2085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2351 ( .LO ( optlc_net_2086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2352 ( .LO ( optlc_net_2087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2353 ( .LO ( optlc_net_2088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2354 ( .LO ( optlc_net_2089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2355 ( .LO ( optlc_net_2090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2356 ( .LO ( optlc_net_2091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2358 ( .LO ( optlc_net_2092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2359 ( .LO ( optlc_net_2093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2360 ( .LO ( optlc_net_2094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2362 ( .LO ( optlc_net_2095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2363 ( .LO ( optlc_net_2096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2364 ( .LO ( optlc_net_2097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2365 ( .LO ( optlc_net_2098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2366 ( .LO ( optlc_net_2099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2368 ( .LO ( optlc_net_2100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2370 ( .LO ( optlc_net_2101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2371 ( .LO ( optlc_net_2102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2372 ( .LO ( optlc_net_2103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2373 ( .LO ( optlc_net_2104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2374 ( .LO ( optlc_net_2105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2375 ( .LO ( optlc_net_2106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2376 ( .LO ( optlc_net_2107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2377 ( .LO ( optlc_net_2108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2378 ( .LO ( optlc_net_2109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2379 ( .LO ( optlc_net_2110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2380 ( .LO ( optlc_net_2111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2381 ( .LO ( optlc_net_2112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2382 ( .LO ( optlc_net_2113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2383 ( .LO ( optlc_net_2114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2385 ( .LO ( optlc_net_2115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2386 ( .LO ( optlc_net_2116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2387 ( .LO ( optlc_net_2117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2388 ( .LO ( optlc_net_2118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2389 ( .LO ( optlc_net_2119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2390 ( .LO ( optlc_net_2120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2391 ( .LO ( optlc_net_2121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2393 ( .LO ( optlc_net_2122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2395 ( .LO ( optlc_net_2123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2397 ( .LO ( optlc_net_2124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2398 ( .LO ( optlc_net_2125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2400 ( .LO ( optlc_net_2126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2401 ( .LO ( optlc_net_2127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2403 ( .LO ( optlc_net_2128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2404 ( .LO ( optlc_net_2129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2405 ( .LO ( optlc_net_2130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2407 ( .LO ( optlc_net_2131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2408 ( .LO ( optlc_net_2132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2409 ( .LO ( optlc_net_2133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2410 ( .LO ( optlc_net_2134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2412 ( .LO ( optlc_net_2135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2413 ( .LO ( optlc_net_2136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2415 ( .LO ( optlc_net_2137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2416 ( .LO ( optlc_net_2138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2417 ( .LO ( optlc_net_2139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2418 ( .LO ( optlc_net_2140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2419 ( .LO ( optlc_net_2141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2420 ( .LO ( optlc_net_2142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2421 ( .LO ( optlc_net_2143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2422 ( .LO ( optlc_net_2144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2423 ( .LO ( optlc_net_2145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2425 ( .LO ( optlc_net_2146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2426 ( .LO ( optlc_net_2147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2427 ( .LO ( optlc_net_2148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2428 ( .LO ( optlc_net_2149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2429 ( .LO ( optlc_net_2150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2430 ( .LO ( optlc_net_2151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2431 ( .LO ( optlc_net_2152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2433 ( .LO ( optlc_net_2153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2434 ( .LO ( optlc_net_2154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2436 ( .LO ( optlc_net_2155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2438 ( .LO ( optlc_net_2156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2439 ( .LO ( optlc_net_2157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2441 ( .LO ( optlc_net_2158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2442 ( .LO ( optlc_net_2159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2443 ( .LO ( optlc_net_2160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2445 ( .LO ( optlc_net_2161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2446 ( .LO ( optlc_net_2162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2447 ( .LO ( optlc_net_2163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2448 ( .LO ( optlc_net_2164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2449 ( .LO ( optlc_net_2165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2450 ( .LO ( optlc_net_2166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2451 ( .LO ( optlc_net_2167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2452 ( .LO ( optlc_net_2168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2454 ( .LO ( optlc_net_2169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2455 ( .LO ( optlc_net_2170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2456 ( .LO ( optlc_net_2171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2457 ( .LO ( optlc_net_2172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2458 ( .LO ( optlc_net_2173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2459 ( .LO ( optlc_net_2174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2460 ( .LO ( optlc_net_2175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2461 ( .LO ( optlc_net_2176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2462 ( .LO ( optlc_net_2177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2463 ( .LO ( optlc_net_2178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2465 ( .LO ( optlc_net_2179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2466 ( .LO ( optlc_net_2180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2467 ( .LO ( optlc_net_2181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2468 ( .LO ( optlc_net_2182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2469 ( .LO ( optlc_net_2183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2470 ( .LO ( optlc_net_2184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2472 ( .LO ( optlc_net_2185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2473 ( .LO ( optlc_net_2186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2474 ( .LO ( optlc_net_2187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2475 ( .LO ( optlc_net_2188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2476 ( .LO ( optlc_net_2189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2477 ( .LO ( optlc_net_2190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2479 ( .LO ( optlc_net_2191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2481 ( .LO ( optlc_net_2192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2483 ( .LO ( optlc_net_2193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2484 ( .LO ( optlc_net_2194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2485 ( .LO ( optlc_net_2195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2486 ( .LO ( optlc_net_2196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2488 ( .LO ( optlc_net_2197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2489 ( .LO ( optlc_net_2198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2490 ( .LO ( optlc_net_2199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2491 ( .LO ( optlc_net_2200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2492 ( .LO ( optlc_net_2201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2494 ( .LO ( optlc_net_2202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2495 ( .LO ( optlc_net_2203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2497 ( .LO ( optlc_net_2204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2498 ( .LO ( optlc_net_2205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2499 ( .LO ( optlc_net_2206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2500 ( .LO ( optlc_net_2207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2502 ( .LO ( optlc_net_2208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2503 ( .LO ( optlc_net_2209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2504 ( .LO ( optlc_net_2210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2505 ( .LO ( optlc_net_2211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2507 ( .LO ( optlc_net_2212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2509 ( .LO ( optlc_net_2213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2510 ( .LO ( optlc_net_2214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2511 ( .LO ( optlc_net_2215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2512 ( .LO ( optlc_net_2216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2513 ( .LO ( optlc_net_2217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2515 ( .LO ( optlc_net_2218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2517 ( .LO ( optlc_net_2219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2519 ( .LO ( optlc_net_2220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2521 ( .LO ( optlc_net_2221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2522 ( .LO ( optlc_net_2222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2523 ( .LO ( optlc_net_2223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2524 ( .LO ( optlc_net_2224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2525 ( .LO ( optlc_net_2225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2526 ( .LO ( optlc_net_2226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2527 ( .LO ( optlc_net_2227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2528 ( .LO ( optlc_net_2228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2529 ( .LO ( optlc_net_2229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2530 ( .LO ( optlc_net_2230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2531 ( .LO ( optlc_net_2231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2533 ( .LO ( optlc_net_2232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2534 ( .LO ( optlc_net_2233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2535 ( .LO ( optlc_net_2234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2536 ( .LO ( optlc_net_2235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2538 ( .LO ( optlc_net_2236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2539 ( .LO ( optlc_net_2237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2540 ( .LO ( optlc_net_2238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2541 ( .LO ( optlc_net_2239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2542 ( .LO ( optlc_net_2240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2543 ( .LO ( optlc_net_2241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2544 ( .LO ( optlc_net_2242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2545 ( .LO ( optlc_net_2243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2546 ( .LO ( optlc_net_2244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2547 ( .LO ( optlc_net_2245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2549 ( .LO ( optlc_net_2246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2550 ( .LO ( optlc_net_2247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2552 ( .LO ( optlc_net_2248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2553 ( .LO ( optlc_net_2249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2554 ( .LO ( optlc_net_2250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2556 ( .LO ( optlc_net_2251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2557 ( .LO ( optlc_net_2252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2558 ( .LO ( optlc_net_2253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2559 ( .LO ( optlc_net_2254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2560 ( .LO ( optlc_net_2255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2562 ( .LO ( optlc_net_2256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2563 ( .LO ( optlc_net_2257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2564 ( .LO ( optlc_net_2258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2566 ( .LO ( optlc_net_2259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2568 ( .LO ( optlc_net_2260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2569 ( .LO ( optlc_net_2261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2570 ( .LO ( optlc_net_2262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2571 ( .LO ( optlc_net_2263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2572 ( .LO ( optlc_net_2264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2573 ( .LO ( optlc_net_2265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2574 ( .LO ( optlc_net_2266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2575 ( .LO ( optlc_net_2267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2576 ( .LO ( optlc_net_2268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2577 ( .LO ( optlc_net_2269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2578 ( .LO ( optlc_net_2270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2579 ( .LO ( optlc_net_2271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2580 ( .LO ( optlc_net_2272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2581 ( .LO ( optlc_net_2273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2582 ( .LO ( optlc_net_2274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2583 ( .LO ( optlc_net_2275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2584 ( .LO ( optlc_net_2276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2585 ( .LO ( optlc_net_2277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2586 ( .LO ( optlc_net_2278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2587 ( .LO ( optlc_net_2279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2588 ( .LO ( optlc_net_2280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2589 ( .LO ( optlc_net_2281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2590 ( .LO ( optlc_net_2282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2591 ( .LO ( optlc_net_2283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2592 ( .LO ( optlc_net_2284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2593 ( .LO ( optlc_net_2285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2594 ( .LO ( optlc_net_2286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2595 ( .LO ( optlc_net_2287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2596 ( .LO ( optlc_net_2288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2597 ( .LO ( optlc_net_2289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2598 ( .LO ( optlc_net_2290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2599 ( .LO ( optlc_net_2291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2600 ( .LO ( optlc_net_2292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2601 ( .LO ( optlc_net_2293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2602 ( .LO ( optlc_net_2294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2603 ( .LO ( optlc_net_2295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2604 ( .LO ( optlc_net_2296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2605 ( .LO ( optlc_net_2297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2606 ( .LO ( optlc_net_2298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2607 ( .LO ( optlc_net_2299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2608 ( .LO ( optlc_net_2300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2609 ( .LO ( optlc_net_2301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2610 ( .LO ( optlc_net_2302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2611 ( .LO ( optlc_net_2303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2612 ( .LO ( optlc_net_2304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2613 ( .LO ( optlc_net_2305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2614 ( .LO ( optlc_net_2306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2615 ( .LO ( optlc_net_2307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2616 ( .LO ( optlc_net_2308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2617 ( .LO ( optlc_net_2309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2618 ( .LO ( optlc_net_2310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2619 ( .LO ( optlc_net_2311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2620 ( .LO ( optlc_net_2312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2621 ( .LO ( optlc_net_2313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2622 ( .LO ( optlc_net_2314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2623 ( .LO ( optlc_net_2315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2624 ( .LO ( optlc_net_2316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2625 ( .LO ( optlc_net_2317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2626 ( .LO ( optlc_net_2318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2627 ( .LO ( optlc_net_2319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2628 ( .LO ( optlc_net_2320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2629 ( .LO ( optlc_net_2321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2630 ( .LO ( optlc_net_2322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2631 ( .LO ( optlc_net_2323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2632 ( .LO ( optlc_net_2324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2633 ( .LO ( optlc_net_2325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2634 ( .LO ( optlc_net_2326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2635 ( .LO ( optlc_net_2327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2636 ( .LO ( optlc_net_2328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2637 ( .LO ( optlc_net_2329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2638 ( .LO ( optlc_net_2330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2639 ( .LO ( optlc_net_2331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2640 ( .LO ( optlc_net_2332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2641 ( .LO ( optlc_net_2333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2642 ( .LO ( optlc_net_2334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2643 ( .LO ( optlc_net_2335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2644 ( .LO ( optlc_net_2336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2645 ( .LO ( optlc_net_2337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2646 ( .LO ( optlc_net_2338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2647 ( .LO ( optlc_net_2339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2648 ( .LO ( optlc_net_2340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2649 ( .LO ( optlc_net_2341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2650 ( .LO ( optlc_net_2342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2651 ( .LO ( optlc_net_2343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2652 ( .LO ( optlc_net_2344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2653 ( .LO ( optlc_net_2345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2654 ( .LO ( optlc_net_2346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2655 ( .LO ( optlc_net_2347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2656 ( .LO ( optlc_net_2348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2657 ( .LO ( optlc_net_2349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2658 ( .LO ( optlc_net_2350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2659 ( .LO ( optlc_net_2351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2660 ( .LO ( optlc_net_2352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2661 ( .LO ( optlc_net_2353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2662 ( .LO ( optlc_net_2354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2663 ( .LO ( optlc_net_2355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2664 ( .LO ( optlc_net_2356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2665 ( .LO ( optlc_net_2357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2666 ( .LO ( optlc_net_2358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2667 ( .LO ( optlc_net_2359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2668 ( .LO ( optlc_net_2360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2669 ( .LO ( optlc_net_2361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2670 ( .LO ( optlc_net_2362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2671 ( .LO ( optlc_net_2363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2672 ( .LO ( optlc_net_2364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2673 ( .LO ( optlc_net_2365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2674 ( .LO ( optlc_net_2366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2675 ( .LO ( optlc_net_2367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2676 ( .LO ( optlc_net_2368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2677 ( .LO ( optlc_net_2369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2678 ( .LO ( optlc_net_2370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2680 ( .LO ( optlc_net_2371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2681 ( .LO ( optlc_net_2372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2682 ( .LO ( optlc_net_2373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2683 ( .LO ( optlc_net_2374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2685 ( .LO ( optlc_net_2375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2686 ( .LO ( optlc_net_2376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2687 ( .LO ( optlc_net_2377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2688 ( .LO ( optlc_net_2378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2689 ( .LO ( optlc_net_2379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2690 ( .LO ( optlc_net_2380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2692 ( .LO ( optlc_net_2381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2693 ( .LO ( optlc_net_2382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2694 ( .LO ( optlc_net_2383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2695 ( .LO ( optlc_net_2384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2697 ( .LO ( optlc_net_2385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2698 ( .LO ( optlc_net_2386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2699 ( .LO ( optlc_net_2387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2700 ( .LO ( optlc_net_2388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2702 ( .LO ( optlc_net_2389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2704 ( .LO ( optlc_net_2390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2705 ( .LO ( optlc_net_2391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2706 ( .LO ( optlc_net_2392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2707 ( .LO ( optlc_net_2393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2708 ( .LO ( optlc_net_2394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2709 ( .LO ( optlc_net_2395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2710 ( .LO ( optlc_net_2396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2711 ( .LO ( optlc_net_2397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2712 ( .LO ( optlc_net_2398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2713 ( .LO ( optlc_net_2399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2714 ( .LO ( optlc_net_2400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2715 ( .LO ( optlc_net_2401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2717 ( .LO ( optlc_net_2402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2719 ( .LO ( optlc_net_2403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2721 ( .LO ( optlc_net_2404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2722 ( .LO ( optlc_net_2405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2724 ( .LO ( optlc_net_2406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2725 ( .LO ( optlc_net_2407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2726 ( .LO ( optlc_net_2408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2727 ( .LO ( optlc_net_2409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2729 ( .LO ( optlc_net_2410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2730 ( .LO ( optlc_net_2411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2731 ( .LO ( optlc_net_2412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2733 ( .LO ( optlc_net_2413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2735 ( .LO ( optlc_net_2414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2736 ( .LO ( optlc_net_2415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2738 ( .LO ( optlc_net_2416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2739 ( .LO ( optlc_net_2417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2740 ( .LO ( optlc_net_2418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2741 ( .LO ( optlc_net_2419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2743 ( .LO ( optlc_net_2420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2745 ( .LO ( optlc_net_2421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2746 ( .LO ( optlc_net_2422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2747 ( .LO ( optlc_net_2423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2749 ( .LO ( optlc_net_2424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2750 ( .LO ( optlc_net_2425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2752 ( .LO ( optlc_net_2426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2753 ( .LO ( optlc_net_2427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2754 ( .LO ( optlc_net_2428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2755 ( .LO ( optlc_net_2429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2756 ( .LO ( optlc_net_2430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2757 ( .LO ( optlc_net_2431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2759 ( .LO ( optlc_net_2432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2760 ( .LO ( optlc_net_2433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2761 ( .LO ( optlc_net_2434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2762 ( .LO ( optlc_net_2435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2763 ( .LO ( optlc_net_2436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2764 ( .LO ( optlc_net_2437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2765 ( .LO ( optlc_net_2438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2766 ( .LO ( optlc_net_2439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2767 ( .LO ( optlc_net_2440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2768 ( .LO ( optlc_net_2441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2769 ( .LO ( optlc_net_2442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2770 ( .LO ( optlc_net_2443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2771 ( .LO ( optlc_net_2444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2773 ( .LO ( optlc_net_2445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2774 ( .LO ( optlc_net_2446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2775 ( .LO ( optlc_net_2447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2776 ( .LO ( optlc_net_2448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2777 ( .LO ( optlc_net_2449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2779 ( .LO ( optlc_net_2450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2780 ( .LO ( optlc_net_2451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2781 ( .LO ( optlc_net_2452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2782 ( .LO ( optlc_net_2453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2783 ( .LO ( optlc_net_2454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2784 ( .LO ( optlc_net_2455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2785 ( .LO ( optlc_net_2456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2786 ( .LO ( optlc_net_2457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2787 ( .LO ( optlc_net_2458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2789 ( .LO ( optlc_net_2459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2791 ( .LO ( optlc_net_2460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2792 ( .LO ( optlc_net_2461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2793 ( .LO ( optlc_net_2462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2794 ( .LO ( optlc_net_2463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2795 ( .LO ( optlc_net_2464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2796 ( .LO ( optlc_net_2465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2797 ( .LO ( optlc_net_2466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2798 ( .LO ( optlc_net_2467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2799 ( .LO ( optlc_net_2468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2801 ( .LO ( optlc_net_2469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2802 ( .LO ( optlc_net_2470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2803 ( .LO ( optlc_net_2471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2804 ( .LO ( optlc_net_2472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2805 ( .LO ( optlc_net_2473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2806 ( .LO ( optlc_net_2474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2807 ( .LO ( optlc_net_2475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2808 ( .LO ( optlc_net_2476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2809 ( .LO ( optlc_net_2477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2810 ( .LO ( optlc_net_2478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2812 ( .LO ( optlc_net_2479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2813 ( .LO ( optlc_net_2480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2814 ( .LO ( optlc_net_2481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2815 ( .LO ( optlc_net_2482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2816 ( .LO ( optlc_net_2483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2817 ( .LO ( optlc_net_2484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2818 ( .LO ( optlc_net_2485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2819 ( .LO ( optlc_net_2486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2820 ( .LO ( optlc_net_2487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2822 ( .LO ( optlc_net_2488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2823 ( .LO ( optlc_net_2489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2824 ( .LO ( optlc_net_2490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2825 ( .LO ( optlc_net_2491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2826 ( .LO ( optlc_net_2492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2827 ( .LO ( optlc_net_2493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2829 ( .LO ( optlc_net_2494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2830 ( .LO ( optlc_net_2495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2832 ( .LO ( optlc_net_2496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2833 ( .LO ( optlc_net_2497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2834 ( .LO ( optlc_net_2498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2835 ( .LO ( optlc_net_2499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2836 ( .LO ( optlc_net_2500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2837 ( .LO ( optlc_net_2501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2838 ( .LO ( optlc_net_2502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2839 ( .LO ( optlc_net_2503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2841 ( .LO ( optlc_net_2504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2842 ( .LO ( optlc_net_2505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2843 ( .LO ( optlc_net_2506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2844 ( .LO ( optlc_net_2507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2845 ( .LO ( optlc_net_2508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2846 ( .LO ( optlc_net_2509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2847 ( .LO ( optlc_net_2510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2848 ( .LO ( optlc_net_2511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2850 ( .LO ( optlc_net_2512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2851 ( .LO ( optlc_net_2513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2852 ( .LO ( optlc_net_2514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2853 ( .LO ( optlc_net_2515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2854 ( .LO ( optlc_net_2516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2855 ( .LO ( optlc_net_2517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2856 ( .LO ( optlc_net_2518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2857 ( .LO ( optlc_net_2519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2858 ( .LO ( optlc_net_2520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2859 ( .LO ( optlc_net_2521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2860 ( .LO ( optlc_net_2522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2861 ( .LO ( optlc_net_2523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2862 ( .LO ( optlc_net_2524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2863 ( .LO ( optlc_net_2525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2864 ( .LO ( optlc_net_2526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2865 ( .LO ( optlc_net_2527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2866 ( .LO ( optlc_net_2528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2867 ( .LO ( optlc_net_2529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2868 ( .LO ( optlc_net_2530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2869 ( .LO ( optlc_net_2531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2870 ( .LO ( optlc_net_2532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2871 ( .LO ( optlc_net_2533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2872 ( .LO ( optlc_net_2534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2873 ( .LO ( optlc_net_2535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2874 ( .LO ( optlc_net_2536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2875 ( .LO ( optlc_net_2537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2876 ( .LO ( optlc_net_2538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2877 ( .LO ( optlc_net_2539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2878 ( .LO ( optlc_net_2540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2879 ( .LO ( optlc_net_2541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2880 ( .LO ( optlc_net_2542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2881 ( .LO ( optlc_net_2543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2882 ( .LO ( optlc_net_2544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2883 ( .LO ( optlc_net_2545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2884 ( .LO ( optlc_net_2546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2885 ( .LO ( optlc_net_2547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2886 ( .LO ( optlc_net_2548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2887 ( .LO ( optlc_net_2549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2888 ( .LO ( optlc_net_2550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2889 ( .LO ( optlc_net_2551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2890 ( .LO ( optlc_net_2552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2891 ( .LO ( optlc_net_2553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2892 ( .LO ( optlc_net_2554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2893 ( .LO ( optlc_net_2555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2894 ( .LO ( optlc_net_2556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2895 ( .LO ( optlc_net_2557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2896 ( .LO ( optlc_net_2558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2897 ( .LO ( optlc_net_2559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2898 ( .LO ( optlc_net_2560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2899 ( .LO ( optlc_net_2561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2900 ( .LO ( optlc_net_2562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2901 ( .LO ( optlc_net_2563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2902 ( .LO ( optlc_net_2564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2903 ( .LO ( optlc_net_2565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2904 ( .LO ( optlc_net_2566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2905 ( .LO ( optlc_net_2567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2906 ( .LO ( optlc_net_2568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2907 ( .LO ( optlc_net_2569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2908 ( .LO ( optlc_net_2570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2909 ( .LO ( optlc_net_2571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2910 ( .LO ( optlc_net_2572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2911 ( .LO ( optlc_net_2573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2912 ( .LO ( optlc_net_2574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2913 ( .LO ( optlc_net_2575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2914 ( .LO ( optlc_net_2576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2915 ( .LO ( optlc_net_2577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2916 ( .LO ( optlc_net_2578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2917 ( .LO ( optlc_net_2579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2918 ( .LO ( optlc_net_2580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2919 ( .LO ( optlc_net_2581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2920 ( .LO ( optlc_net_2582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2921 ( .LO ( optlc_net_2583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2922 ( .LO ( optlc_net_2584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2923 ( .LO ( optlc_net_2585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2924 ( .LO ( optlc_net_2586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2925 ( .LO ( optlc_net_2587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2926 ( .LO ( optlc_net_2588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2927 ( .LO ( optlc_net_2589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2928 ( .LO ( optlc_net_2590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2929 ( .LO ( optlc_net_2591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2930 ( .LO ( optlc_net_2592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2931 ( .LO ( optlc_net_2593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2932 ( .LO ( optlc_net_2594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2933 ( .LO ( optlc_net_2595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2934 ( .LO ( optlc_net_2596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2935 ( .LO ( optlc_net_2597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2936 ( .LO ( optlc_net_2598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2937 ( .LO ( optlc_net_2599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2938 ( .LO ( optlc_net_2600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2939 ( .LO ( optlc_net_2601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2940 ( .LO ( optlc_net_2602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2941 ( .LO ( optlc_net_2603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2942 ( .LO ( optlc_net_2604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2943 ( .LO ( optlc_net_2605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2944 ( .LO ( optlc_net_2606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2945 ( .LO ( optlc_net_2607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2946 ( .LO ( optlc_net_2608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2947 ( .LO ( optlc_net_2609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2948 ( .LO ( optlc_net_2610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2949 ( .LO ( optlc_net_2611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2951 ( .LO ( optlc_net_2612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2952 ( .LO ( optlc_net_2613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2953 ( .LO ( optlc_net_2614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2954 ( .LO ( optlc_net_2615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2955 ( .LO ( optlc_net_2616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2956 ( .LO ( optlc_net_2617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2957 ( .LO ( optlc_net_2618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2958 ( .LO ( optlc_net_2619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2959 ( .LO ( optlc_net_2620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2960 ( .LO ( optlc_net_2621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2962 ( .LO ( optlc_net_2622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2963 ( .LO ( optlc_net_2623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2964 ( .LO ( optlc_net_2624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2965 ( .LO ( optlc_net_2625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2966 ( .LO ( optlc_net_2626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2967 ( .LO ( optlc_net_2627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2968 ( .LO ( optlc_net_2628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2969 ( .LO ( optlc_net_2629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2970 ( .LO ( optlc_net_2630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2971 ( .LO ( optlc_net_2631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2973 ( .LO ( optlc_net_2632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2974 ( .LO ( optlc_net_2633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2975 ( .LO ( optlc_net_2634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2976 ( .LO ( optlc_net_2635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2977 ( .LO ( optlc_net_2636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2978 ( .LO ( optlc_net_2637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2979 ( .LO ( optlc_net_2638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2980 ( .LO ( optlc_net_2639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2981 ( .LO ( optlc_net_2640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2982 ( .LO ( optlc_net_2641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2983 ( .LO ( optlc_net_2642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2985 ( .LO ( optlc_net_2643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2986 ( .LO ( optlc_net_2644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2987 ( .LO ( optlc_net_2645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2988 ( .LO ( optlc_net_2646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2989 ( .LO ( optlc_net_2647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2990 ( .LO ( optlc_net_2648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2991 ( .LO ( optlc_net_2649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2992 ( .LO ( optlc_net_2650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2993 ( .LO ( optlc_net_2651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2995 ( .LO ( optlc_net_2652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2997 ( .LO ( optlc_net_2653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2998 ( .LO ( optlc_net_2654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2999 ( .LO ( optlc_net_2655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3000 ( .LO ( optlc_net_2656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3001 ( .LO ( optlc_net_2657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3002 ( .LO ( optlc_net_2658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3003 ( .LO ( optlc_net_2659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3004 ( .LO ( optlc_net_2660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3005 ( .LO ( optlc_net_2661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3006 ( .LO ( optlc_net_2662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3007 ( .LO ( optlc_net_2663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3008 ( .LO ( optlc_net_2664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3009 ( .LO ( optlc_net_2665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3010 ( .LO ( optlc_net_2666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3011 ( .LO ( optlc_net_2667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3013 ( .LO ( optlc_net_2668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3014 ( .LO ( optlc_net_2669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3015 ( .LO ( optlc_net_2670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3016 ( .LO ( optlc_net_2671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3017 ( .LO ( optlc_net_2672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3019 ( .LO ( optlc_net_2673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3020 ( .LO ( optlc_net_2674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3021 ( .LO ( optlc_net_2675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3022 ( .LO ( optlc_net_2676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3023 ( .LO ( optlc_net_2677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3024 ( .LO ( optlc_net_2678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3025 ( .LO ( optlc_net_2679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3026 ( .LO ( optlc_net_2680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3027 ( .LO ( optlc_net_2681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3028 ( .LO ( optlc_net_2682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3030 ( .LO ( optlc_net_2683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3031 ( .LO ( optlc_net_2684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3032 ( .LO ( optlc_net_2685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3034 ( .LO ( optlc_net_2686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3035 ( .LO ( optlc_net_2687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3037 ( .LO ( optlc_net_2688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3038 ( .LO ( optlc_net_2689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3039 ( .LO ( optlc_net_2690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3040 ( .LO ( optlc_net_2691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3041 ( .LO ( optlc_net_2692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3042 ( .LO ( optlc_net_2693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3043 ( .LO ( optlc_net_2694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3044 ( .LO ( optlc_net_2695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3045 ( .LO ( optlc_net_2696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3046 ( .LO ( optlc_net_2697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3047 ( .LO ( optlc_net_2698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3048 ( .LO ( optlc_net_2699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3049 ( .LO ( optlc_net_2700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3050 ( .LO ( optlc_net_2701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3051 ( .LO ( optlc_net_2702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3052 ( .LO ( optlc_net_2703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3053 ( .LO ( optlc_net_2704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3054 ( .LO ( optlc_net_2705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3055 ( .LO ( optlc_net_2706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3056 ( .LO ( optlc_net_2707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3057 ( .LO ( optlc_net_2708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3058 ( .LO ( optlc_net_2709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3059 ( .LO ( optlc_net_2710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3060 ( .LO ( optlc_net_2711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3061 ( .LO ( optlc_net_2712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3062 ( .LO ( optlc_net_2713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3063 ( .LO ( optlc_net_2714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3064 ( .LO ( optlc_net_2715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3065 ( .LO ( optlc_net_2716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3066 ( .LO ( optlc_net_2717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3067 ( .LO ( optlc_net_2718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3068 ( .LO ( optlc_net_2719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3069 ( .LO ( optlc_net_2720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3070 ( .LO ( optlc_net_2721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3071 ( .LO ( optlc_net_2722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3073 ( .LO ( optlc_net_2723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3074 ( .LO ( optlc_net_2724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3075 ( .LO ( optlc_net_2725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3076 ( .LO ( optlc_net_2726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3077 ( .LO ( optlc_net_2727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3079 ( .LO ( optlc_net_2728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3080 ( .LO ( optlc_net_2729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3081 ( .LO ( optlc_net_2730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3082 ( .LO ( optlc_net_2731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3083 ( .LO ( optlc_net_2732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3084 ( .LO ( optlc_net_2733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3085 ( .LO ( optlc_net_2734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3086 ( .LO ( optlc_net_2735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3087 ( .LO ( optlc_net_2736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3088 ( .LO ( optlc_net_2737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3089 ( .LO ( optlc_net_2738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3090 ( .LO ( optlc_net_2739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3091 ( .LO ( optlc_net_2740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3092 ( .LO ( optlc_net_2741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3093 ( .LO ( optlc_net_2742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3094 ( .LO ( optlc_net_2743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3095 ( .LO ( optlc_net_2744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3096 ( .LO ( optlc_net_2745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3097 ( .LO ( optlc_net_2746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3098 ( .LO ( optlc_net_2747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3099 ( .LO ( optlc_net_2748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3100 ( .LO ( optlc_net_2749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3101 ( .LO ( optlc_net_2750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3102 ( .LO ( optlc_net_2751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3103 ( .LO ( optlc_net_2752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3104 ( .LO ( optlc_net_2753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3105 ( .LO ( optlc_net_2754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3106 ( .LO ( optlc_net_2755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3107 ( .LO ( optlc_net_2756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3108 ( .LO ( optlc_net_2757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3109 ( .LO ( optlc_net_2758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3110 ( .LO ( optlc_net_2759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3111 ( .LO ( optlc_net_2760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3112 ( .LO ( optlc_net_2761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3113 ( .LO ( optlc_net_2762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3114 ( .LO ( optlc_net_2763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3115 ( .LO ( optlc_net_2764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3116 ( .LO ( optlc_net_2765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3117 ( .LO ( optlc_net_2766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3118 ( .LO ( optlc_net_2767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3119 ( .LO ( optlc_net_2768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3120 ( .LO ( optlc_net_2769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3121 ( .LO ( optlc_net_2770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3122 ( .LO ( optlc_net_2771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3123 ( .LO ( optlc_net_2772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3124 ( .LO ( optlc_net_2773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3125 ( .LO ( optlc_net_2774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3126 ( .LO ( optlc_net_2775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3127 ( .LO ( optlc_net_2776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3128 ( .LO ( optlc_net_2777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3129 ( .LO ( optlc_net_2778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3130 ( .LO ( optlc_net_2779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3131 ( .LO ( optlc_net_2780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3132 ( .LO ( optlc_net_2781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3133 ( .LO ( optlc_net_2782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3134 ( .LO ( optlc_net_2783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3135 ( .LO ( optlc_net_2784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3136 ( .LO ( optlc_net_2785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3137 ( .LO ( optlc_net_2786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3138 ( .LO ( optlc_net_2787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3139 ( .LO ( optlc_net_2788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3140 ( .LO ( optlc_net_2789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3141 ( .LO ( optlc_net_2790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3142 ( .LO ( optlc_net_2791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3143 ( .LO ( optlc_net_2792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3144 ( .LO ( optlc_net_2793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3145 ( .LO ( optlc_net_2794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3146 ( .LO ( optlc_net_2795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3147 ( .LO ( optlc_net_2796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3148 ( .LO ( optlc_net_2797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3149 ( .LO ( optlc_net_2798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3150 ( .LO ( optlc_net_2799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3151 ( .LO ( optlc_net_2800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3152 ( .LO ( optlc_net_2801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3153 ( .LO ( optlc_net_2802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3154 ( .LO ( optlc_net_2803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3156 ( .LO ( optlc_net_2804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3157 ( .LO ( optlc_net_2805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3158 ( .LO ( optlc_net_2806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3159 ( .LO ( optlc_net_2807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3160 ( .LO ( optlc_net_2808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3161 ( .LO ( optlc_net_2809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3162 ( .LO ( optlc_net_2810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3163 ( .LO ( optlc_net_2811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3164 ( .LO ( optlc_net_2812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3166 ( .LO ( optlc_net_2813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3167 ( .LO ( optlc_net_2814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3168 ( .LO ( optlc_net_2815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3170 ( .LO ( optlc_net_2816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3171 ( .LO ( optlc_net_2817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3172 ( .LO ( optlc_net_2818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3173 ( .LO ( optlc_net_2819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3174 ( .LO ( optlc_net_2820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3175 ( .LO ( optlc_net_2821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3176 ( .LO ( optlc_net_2822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3177 ( .LO ( optlc_net_2823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3178 ( .LO ( optlc_net_2824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3179 ( .LO ( optlc_net_2825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3180 ( .LO ( optlc_net_2826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3181 ( .LO ( optlc_net_2827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3182 ( .LO ( optlc_net_2828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3183 ( .LO ( optlc_net_2829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3184 ( .LO ( optlc_net_2830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3185 ( .LO ( optlc_net_2831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3186 ( .LO ( optlc_net_2832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3187 ( .LO ( optlc_net_2833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3188 ( .LO ( optlc_net_2834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3190 ( .LO ( optlc_net_2835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3191 ( .LO ( optlc_net_2836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3192 ( .LO ( optlc_net_2837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3193 ( .LO ( optlc_net_2838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3194 ( .LO ( optlc_net_2839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3195 ( .LO ( optlc_net_2840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3196 ( .LO ( optlc_net_2841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3197 ( .LO ( optlc_net_2842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3198 ( .LO ( optlc_net_2843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3199 ( .LO ( optlc_net_2844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3200 ( .LO ( optlc_net_2845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3201 ( .LO ( optlc_net_2846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3202 ( .LO ( optlc_net_2847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3204 ( .LO ( optlc_net_2848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3205 ( .LO ( optlc_net_2849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3206 ( .LO ( optlc_net_2850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3207 ( .LO ( optlc_net_2851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3208 ( .LO ( optlc_net_2852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3209 ( .LO ( optlc_net_2853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3210 ( .LO ( optlc_net_2854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3211 ( .LO ( optlc_net_2855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3212 ( .LO ( optlc_net_2856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3213 ( .LO ( optlc_net_2857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3214 ( .LO ( optlc_net_2858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3215 ( .LO ( optlc_net_2859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3216 ( .LO ( optlc_net_2860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3217 ( .LO ( optlc_net_2861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3218 ( .LO ( optlc_net_2862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3219 ( .LO ( optlc_net_2863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3220 ( .LO ( optlc_net_2864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3221 ( .LO ( optlc_net_2865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3222 ( .LO ( optlc_net_2866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3223 ( .LO ( optlc_net_2867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3224 ( .LO ( optlc_net_2868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3225 ( .LO ( optlc_net_2869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3226 ( .LO ( optlc_net_2870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3227 ( .LO ( optlc_net_2871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3228 ( .LO ( optlc_net_2872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3229 ( .LO ( optlc_net_2873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3230 ( .LO ( optlc_net_2874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3231 ( .LO ( optlc_net_2875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3232 ( .LO ( optlc_net_2876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3233 ( .LO ( optlc_net_2877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3234 ( .LO ( optlc_net_2878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3235 ( .LO ( optlc_net_2879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3236 ( .LO ( optlc_net_2880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3237 ( .LO ( optlc_net_2881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3238 ( .LO ( optlc_net_2882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3240 ( .LO ( optlc_net_2883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3241 ( .LO ( optlc_net_2884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3242 ( .LO ( optlc_net_2885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3243 ( .LO ( optlc_net_2886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3244 ( .LO ( optlc_net_2887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3245 ( .LO ( optlc_net_2888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3246 ( .LO ( optlc_net_2889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3247 ( .LO ( optlc_net_2890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3248 ( .LO ( optlc_net_2891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3249 ( .LO ( optlc_net_2892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3250 ( .LO ( optlc_net_2893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3251 ( .LO ( optlc_net_2894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3252 ( .LO ( optlc_net_2895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3253 ( .LO ( optlc_net_2896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3254 ( .LO ( optlc_net_2897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3255 ( .LO ( optlc_net_2898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3256 ( .LO ( optlc_net_2899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3257 ( .LO ( optlc_net_2900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3258 ( .LO ( optlc_net_2901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3259 ( .LO ( optlc_net_2902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3260 ( .LO ( optlc_net_2903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3261 ( .LO ( optlc_net_2904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3262 ( .LO ( optlc_net_2905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3263 ( .LO ( optlc_net_2906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3264 ( .LO ( optlc_net_2907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3265 ( .LO ( optlc_net_2908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3266 ( .LO ( optlc_net_2909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3267 ( .LO ( optlc_net_2910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3268 ( .LO ( optlc_net_2911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3269 ( .LO ( optlc_net_2912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3270 ( .LO ( optlc_net_2913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3271 ( .LO ( optlc_net_2914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3272 ( .LO ( optlc_net_2915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3273 ( .LO ( optlc_net_2916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3274 ( .LO ( optlc_net_2917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3275 ( .LO ( optlc_net_2918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3276 ( .LO ( optlc_net_2919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3277 ( .LO ( optlc_net_2920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3278 ( .LO ( optlc_net_2921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3279 ( .LO ( optlc_net_2922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3280 ( .LO ( optlc_net_2923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3281 ( .LO ( optlc_net_2924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3282 ( .LO ( optlc_net_2925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3283 ( .LO ( optlc_net_2926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3284 ( .LO ( optlc_net_2927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3285 ( .LO ( optlc_net_2928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3286 ( .LO ( optlc_net_2929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3287 ( .LO ( optlc_net_2930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3288 ( .LO ( optlc_net_2931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3289 ( .LO ( optlc_net_2932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3290 ( .LO ( optlc_net_2933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3291 ( .LO ( optlc_net_2934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3292 ( .LO ( optlc_net_2935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3293 ( .LO ( optlc_net_2936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3294 ( .LO ( optlc_net_2937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3295 ( .LO ( optlc_net_2938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3296 ( .LO ( optlc_net_2939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3297 ( .LO ( optlc_net_2940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3298 ( .LO ( optlc_net_2941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3299 ( .LO ( optlc_net_2942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3300 ( .LO ( optlc_net_2943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3301 ( .LO ( optlc_net_2944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3302 ( .LO ( optlc_net_2945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3303 ( .LO ( optlc_net_2946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3304 ( .LO ( optlc_net_2947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3305 ( .LO ( optlc_net_2948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3306 ( .LO ( optlc_net_2949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3307 ( .LO ( optlc_net_2950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3308 ( .LO ( optlc_net_2951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3309 ( .LO ( optlc_net_2952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3310 ( .LO ( optlc_net_2953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3311 ( .LO ( optlc_net_2954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3312 ( .LO ( optlc_net_2955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3313 ( .LO ( optlc_net_2956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3314 ( .LO ( optlc_net_2957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3315 ( .LO ( optlc_net_2958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3316 ( .LO ( optlc_net_2959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3317 ( .LO ( optlc_net_2960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3318 ( .LO ( optlc_net_2961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3319 ( .LO ( optlc_net_2962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3320 ( .LO ( optlc_net_2963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3321 ( .LO ( optlc_net_2964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3322 ( .LO ( optlc_net_2965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3323 ( .LO ( optlc_net_2966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3324 ( .LO ( optlc_net_2967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3325 ( .LO ( optlc_net_2968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3326 ( .LO ( optlc_net_2969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3327 ( .LO ( optlc_net_2970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3328 ( .LO ( optlc_net_2971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3329 ( .LO ( optlc_net_2972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3330 ( .LO ( optlc_net_2973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3331 ( .LO ( optlc_net_2974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3332 ( .LO ( optlc_net_2975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3333 ( .LO ( optlc_net_2976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3334 ( .LO ( optlc_net_2977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3335 ( .LO ( optlc_net_2978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3336 ( .LO ( optlc_net_2979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3337 ( .LO ( optlc_net_2980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3338 ( .LO ( optlc_net_2981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3339 ( .LO ( optlc_net_2982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3340 ( .LO ( optlc_net_2983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3341 ( .LO ( optlc_net_2984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3342 ( .LO ( optlc_net_2985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3343 ( .LO ( optlc_net_2986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3344 ( .LO ( optlc_net_2987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3345 ( .LO ( optlc_net_2988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3346 ( .LO ( optlc_net_2989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3347 ( .LO ( optlc_net_2990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3348 ( .LO ( optlc_net_2991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3349 ( .LO ( optlc_net_2992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3350 ( .LO ( optlc_net_2993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3351 ( .LO ( optlc_net_2994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3352 ( .LO ( optlc_net_2995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3353 ( .LO ( optlc_net_2996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3354 ( .LO ( optlc_net_2997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3355 ( .LO ( optlc_net_2998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3356 ( .LO ( optlc_net_2999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3357 ( .LO ( optlc_net_3000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3358 ( .LO ( optlc_net_3001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3359 ( .LO ( optlc_net_3002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3360 ( .LO ( optlc_net_3003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3361 ( .LO ( optlc_net_3004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3362 ( .LO ( optlc_net_3005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3363 ( .LO ( optlc_net_3006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3364 ( .LO ( optlc_net_3007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3365 ( .LO ( optlc_net_3008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3366 ( .LO ( optlc_net_3009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3367 ( .LO ( optlc_net_3010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3368 ( .LO ( optlc_net_3011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3369 ( .LO ( optlc_net_3012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3370 ( .LO ( optlc_net_3013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3371 ( .LO ( optlc_net_3014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3372 ( .LO ( optlc_net_3015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3373 ( .LO ( optlc_net_3016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3374 ( .LO ( optlc_net_3017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3375 ( .LO ( optlc_net_3018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3376 ( .LO ( optlc_net_3019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3377 ( .LO ( optlc_net_3020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3378 ( .LO ( optlc_net_3021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3379 ( .LO ( optlc_net_3022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3380 ( .LO ( optlc_net_3023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3381 ( .LO ( optlc_net_3024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3382 ( .LO ( optlc_net_3025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3383 ( .LO ( optlc_net_3026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3384 ( .LO ( optlc_net_3027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3385 ( .LO ( optlc_net_3028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3386 ( .LO ( optlc_net_3029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3387 ( .LO ( optlc_net_3030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3388 ( .LO ( optlc_net_3031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3389 ( .LO ( optlc_net_3032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3390 ( .LO ( optlc_net_3033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3391 ( .LO ( optlc_net_3034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3392 ( .LO ( optlc_net_3035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3393 ( .LO ( optlc_net_3036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3394 ( .LO ( optlc_net_3037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3395 ( .LO ( optlc_net_3038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3396 ( .LO ( optlc_net_3039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3397 ( .LO ( optlc_net_3040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3398 ( .LO ( optlc_net_3041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3399 ( .LO ( optlc_net_3042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3400 ( .LO ( optlc_net_3043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3401 ( .LO ( optlc_net_3044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3402 ( .LO ( optlc_net_3045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3403 ( .LO ( optlc_net_3046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3404 ( .LO ( optlc_net_3047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3405 ( .LO ( optlc_net_3048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3406 ( .LO ( optlc_net_3049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3407 ( .LO ( optlc_net_3050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3408 ( .LO ( optlc_net_3051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3409 ( .LO ( optlc_net_3052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3410 ( .LO ( optlc_net_3053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3411 ( .LO ( optlc_net_3054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3412 ( .LO ( optlc_net_3055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3413 ( .LO ( optlc_net_3056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3414 ( .LO ( optlc_net_3057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3415 ( .LO ( optlc_net_3058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3416 ( .LO ( optlc_net_3059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3417 ( .LO ( optlc_net_3060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3418 ( .LO ( optlc_net_3061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3419 ( .LO ( optlc_net_3062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3420 ( .LO ( optlc_net_3063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3421 ( .LO ( optlc_net_3064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3422 ( .LO ( optlc_net_3065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3423 ( .LO ( optlc_net_3066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3424 ( .LO ( optlc_net_3067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3425 ( .LO ( optlc_net_3068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3426 ( .LO ( optlc_net_3069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3427 ( .LO ( optlc_net_3070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3428 ( .LO ( optlc_net_3071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3429 ( .LO ( optlc_net_3072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3430 ( .LO ( optlc_net_3073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3431 ( .LO ( optlc_net_3074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3432 ( .LO ( optlc_net_3075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3433 ( .LO ( optlc_net_3076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3434 ( .LO ( optlc_net_3077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3435 ( .LO ( optlc_net_3078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3436 ( .LO ( optlc_net_3079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3437 ( .LO ( optlc_net_3080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3438 ( .LO ( optlc_net_3081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3439 ( .LO ( optlc_net_3082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3440 ( .LO ( optlc_net_3083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3441 ( .LO ( optlc_net_3084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3442 ( .LO ( optlc_net_3085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3443 ( .LO ( optlc_net_3086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3444 ( .LO ( optlc_net_3087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3445 ( .LO ( optlc_net_3088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3446 ( .LO ( optlc_net_3089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3447 ( .LO ( optlc_net_3090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3448 ( .LO ( optlc_net_3091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3449 ( .LO ( optlc_net_3092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3450 ( .LO ( optlc_net_3093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3451 ( .LO ( optlc_net_3094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3452 ( .LO ( optlc_net_3095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3453 ( .LO ( optlc_net_3096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3454 ( .LO ( optlc_net_3097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3455 ( .LO ( optlc_net_3098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3456 ( .LO ( optlc_net_3099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3457 ( .LO ( optlc_net_3100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3458 ( .LO ( optlc_net_3101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3459 ( .LO ( optlc_net_3102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3460 ( .LO ( optlc_net_3103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3461 ( .LO ( optlc_net_3104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3462 ( .LO ( optlc_net_3105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3463 ( .LO ( optlc_net_3106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3464 ( .LO ( optlc_net_3107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3465 ( .LO ( optlc_net_3108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3466 ( .LO ( optlc_net_3109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3467 ( .LO ( optlc_net_3110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3468 ( .LO ( optlc_net_3111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3469 ( .LO ( optlc_net_3112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3470 ( .LO ( optlc_net_3113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3471 ( .LO ( optlc_net_3114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3472 ( .LO ( optlc_net_3115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3473 ( .LO ( optlc_net_3116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3474 ( .LO ( optlc_net_3117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3475 ( .LO ( optlc_net_3118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3476 ( .LO ( optlc_net_3119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3477 ( .LO ( optlc_net_3120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3478 ( .LO ( optlc_net_3121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3479 ( .LO ( optlc_net_3122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3480 ( .LO ( optlc_net_3123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3481 ( .LO ( optlc_net_3124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3482 ( .LO ( optlc_net_3125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3483 ( .LO ( optlc_net_3126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3484 ( .LO ( optlc_net_3127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3485 ( .LO ( optlc_net_3128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3486 ( .LO ( optlc_net_3129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3487 ( .LO ( optlc_net_3130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3488 ( .LO ( optlc_net_3131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3489 ( .LO ( optlc_net_3132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3490 ( .LO ( optlc_net_3133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3491 ( .LO ( optlc_net_3134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3492 ( .LO ( optlc_net_3135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3493 ( .LO ( optlc_net_3136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3494 ( .LO ( optlc_net_3137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3495 ( .LO ( optlc_net_3138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3496 ( .LO ( optlc_net_3139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3497 ( .LO ( optlc_net_3140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3498 ( .LO ( optlc_net_3141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3499 ( .LO ( optlc_net_3142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3500 ( .LO ( optlc_net_3143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3501 ( .LO ( optlc_net_3144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3502 ( .LO ( optlc_net_3145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3503 ( .LO ( optlc_net_3146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3504 ( .LO ( optlc_net_3147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3505 ( .LO ( optlc_net_3148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3506 ( .LO ( optlc_net_3149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3507 ( .LO ( optlc_net_3150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3509 ( .LO ( optlc_net_3151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3510 ( .LO ( optlc_net_3152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3511 ( .LO ( optlc_net_3153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3512 ( .LO ( optlc_net_3154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3513 ( .LO ( optlc_net_3155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3514 ( .LO ( optlc_net_3156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3515 ( .LO ( optlc_net_3157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3516 ( .LO ( optlc_net_3158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3517 ( .LO ( optlc_net_3159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3518 ( .LO ( optlc_net_3160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3519 ( .LO ( optlc_net_3161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3520 ( .LO ( optlc_net_3162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3521 ( .LO ( optlc_net_3163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3522 ( .LO ( optlc_net_3164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3523 ( .LO ( optlc_net_3165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3524 ( .LO ( optlc_net_3166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3525 ( .LO ( optlc_net_3167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3526 ( .LO ( optlc_net_3168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3527 ( .LO ( optlc_net_3169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3528 ( .LO ( optlc_net_3170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3529 ( .LO ( optlc_net_3171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3530 ( .LO ( optlc_net_3172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3531 ( .LO ( optlc_net_3173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3532 ( .LO ( optlc_net_3174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3533 ( .LO ( optlc_net_3175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3534 ( .LO ( optlc_net_3176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3535 ( .LO ( optlc_net_3177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3536 ( .LO ( optlc_net_3178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3537 ( .LO ( optlc_net_3179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3538 ( .LO ( optlc_net_3180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3539 ( .LO ( optlc_net_3181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3540 ( .LO ( optlc_net_3182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3541 ( .LO ( optlc_net_3183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3542 ( .LO ( optlc_net_3184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3543 ( .LO ( optlc_net_3185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3544 ( .LO ( optlc_net_3186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3545 ( .LO ( optlc_net_3187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3546 ( .LO ( optlc_net_3188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3547 ( .LO ( optlc_net_3189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3548 ( .LO ( optlc_net_3190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3549 ( .LO ( optlc_net_3191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3550 ( .LO ( optlc_net_3192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3551 ( .LO ( optlc_net_3193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3552 ( .LO ( optlc_net_3194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3553 ( .LO ( optlc_net_3195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3554 ( .LO ( optlc_net_3196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3555 ( .LO ( optlc_net_3197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3556 ( .LO ( optlc_net_3198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3557 ( .LO ( optlc_net_3199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3558 ( .LO ( optlc_net_3200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3559 ( .LO ( optlc_net_3201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3560 ( .LO ( optlc_net_3202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3561 ( .LO ( optlc_net_3203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3562 ( .LO ( optlc_net_3204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3563 ( .LO ( optlc_net_3205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3564 ( .LO ( optlc_net_3206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3565 ( .LO ( optlc_net_3207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3566 ( .LO ( optlc_net_3208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3567 ( .LO ( optlc_net_3209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3568 ( .LO ( optlc_net_3210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3569 ( .LO ( optlc_net_3211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3570 ( .LO ( optlc_net_3212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3571 ( .LO ( optlc_net_3213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3572 ( .LO ( optlc_net_3214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3573 ( .LO ( optlc_net_3215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3574 ( .LO ( optlc_net_3216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3575 ( .LO ( optlc_net_3217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3576 ( .LO ( optlc_net_3218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3577 ( .LO ( optlc_net_3219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3578 ( .LO ( optlc_net_3220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3579 ( .LO ( optlc_net_3221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3580 ( .LO ( optlc_net_3222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3581 ( .LO ( optlc_net_3223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3582 ( .LO ( optlc_net_3224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3583 ( .LO ( optlc_net_3225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3584 ( .LO ( optlc_net_3226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3585 ( .LO ( optlc_net_3227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3586 ( .LO ( optlc_net_3228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3587 ( .LO ( optlc_net_3229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3588 ( .LO ( optlc_net_3230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3589 ( .LO ( optlc_net_3231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3590 ( .LO ( optlc_net_3232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3591 ( .LO ( optlc_net_3233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3592 ( .LO ( optlc_net_3234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3593 ( .LO ( optlc_net_3235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3594 ( .LO ( optlc_net_3236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3595 ( .LO ( optlc_net_3237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3596 ( .LO ( optlc_net_3238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3597 ( .LO ( optlc_net_3239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3598 ( .LO ( optlc_net_3240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3599 ( .LO ( optlc_net_3241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3600 ( .LO ( optlc_net_3242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3601 ( .LO ( optlc_net_3243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3602 ( .LO ( optlc_net_3244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3603 ( .LO ( optlc_net_3245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3604 ( .LO ( optlc_net_3246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3605 ( .LO ( optlc_net_3247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3606 ( .LO ( optlc_net_3248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3607 ( .LO ( optlc_net_3249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3608 ( .LO ( optlc_net_3250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3609 ( .LO ( optlc_net_3251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3610 ( .LO ( optlc_net_3252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3611 ( .LO ( optlc_net_3253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3612 ( .LO ( optlc_net_3254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3613 ( .LO ( optlc_net_3255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3614 ( .LO ( optlc_net_3256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3615 ( .LO ( optlc_net_3257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3616 ( .LO ( optlc_net_3258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3617 ( .LO ( optlc_net_3259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3618 ( .LO ( optlc_net_3260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3619 ( .LO ( optlc_net_3261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3620 ( .LO ( optlc_net_3262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3621 ( .LO ( optlc_net_3263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3622 ( .LO ( optlc_net_3264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3623 ( .LO ( optlc_net_3265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3624 ( .LO ( optlc_net_3266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3625 ( .LO ( optlc_net_3267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3626 ( .LO ( optlc_net_3268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3627 ( .LO ( optlc_net_3269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3628 ( .LO ( optlc_net_3270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3629 ( .LO ( optlc_net_3271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3630 ( .LO ( optlc_net_3272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3631 ( .LO ( optlc_net_3273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3632 ( .LO ( optlc_net_3274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3633 ( .LO ( optlc_net_3275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3634 ( .LO ( optlc_net_3276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3635 ( .LO ( optlc_net_3277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3636 ( .LO ( optlc_net_3278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3637 ( .LO ( optlc_net_3279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3638 ( .LO ( optlc_net_3280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3639 ( .LO ( optlc_net_3281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3640 ( .LO ( optlc_net_3282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3641 ( .LO ( optlc_net_3283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3642 ( .LO ( optlc_net_3284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3643 ( .LO ( optlc_net_3285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3644 ( .LO ( optlc_net_3286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3645 ( .LO ( optlc_net_3287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3646 ( .LO ( optlc_net_3288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3647 ( .LO ( optlc_net_3289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3648 ( .LO ( optlc_net_3290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3649 ( .LO ( optlc_net_3291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3650 ( .LO ( optlc_net_3292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3651 ( .LO ( optlc_net_3293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3652 ( .LO ( optlc_net_3294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3653 ( .LO ( optlc_net_3295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3654 ( .LO ( optlc_net_3296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3655 ( .LO ( optlc_net_3297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3656 ( .LO ( optlc_net_3298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3657 ( .LO ( optlc_net_3299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3658 ( .LO ( optlc_net_3300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3659 ( .LO ( optlc_net_3301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3660 ( .LO ( optlc_net_3302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3661 ( .LO ( optlc_net_3303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3662 ( .LO ( optlc_net_3304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3663 ( .LO ( optlc_net_3305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3664 ( .LO ( optlc_net_3306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3665 ( .LO ( optlc_net_3307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3666 ( .LO ( optlc_net_3308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3667 ( .LO ( optlc_net_3309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3668 ( .LO ( optlc_net_3310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3669 ( .LO ( optlc_net_3311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3670 ( .LO ( optlc_net_3312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3671 ( .LO ( optlc_net_3313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3672 ( .LO ( optlc_net_3314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3673 ( .LO ( optlc_net_3315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3674 ( .LO ( optlc_net_3316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3675 ( .LO ( optlc_net_3317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3676 ( .LO ( optlc_net_3318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3677 ( .LO ( optlc_net_3319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3678 ( .LO ( optlc_net_3320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3679 ( .LO ( optlc_net_3321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3680 ( .LO ( optlc_net_3322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3681 ( .LO ( optlc_net_3323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3682 ( .LO ( optlc_net_3324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3683 ( .LO ( optlc_net_3325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3684 ( .LO ( optlc_net_3326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3685 ( .LO ( optlc_net_3327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3686 ( .LO ( optlc_net_3328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3687 ( .LO ( optlc_net_3329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3688 ( .LO ( optlc_net_3330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3689 ( .LO ( optlc_net_3331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3690 ( .LO ( optlc_net_3332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3691 ( .LO ( optlc_net_3333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3692 ( .LO ( optlc_net_3334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3693 ( .LO ( optlc_net_3335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3694 ( .LO ( optlc_net_3336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3695 ( .LO ( optlc_net_3337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3696 ( .LO ( optlc_net_3338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3697 ( .LO ( optlc_net_3339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3698 ( .LO ( optlc_net_3340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3699 ( .LO ( optlc_net_3341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3700 ( .LO ( optlc_net_3342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3701 ( .LO ( optlc_net_3343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3702 ( .LO ( optlc_net_3344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3703 ( .LO ( optlc_net_3345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3704 ( .LO ( optlc_net_3346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3705 ( .LO ( optlc_net_3347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3706 ( .LO ( optlc_net_3348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3707 ( .LO ( optlc_net_3349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3708 ( .LO ( optlc_net_3350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3709 ( .LO ( optlc_net_3351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3710 ( .LO ( optlc_net_3352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3711 ( .LO ( optlc_net_3353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3712 ( .LO ( optlc_net_3354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3713 ( .LO ( optlc_net_3355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3714 ( .LO ( optlc_net_3356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3715 ( .LO ( optlc_net_3357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3716 ( .LO ( optlc_net_3358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3717 ( .LO ( optlc_net_3359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3718 ( .LO ( optlc_net_3360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3719 ( .LO ( optlc_net_3361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3720 ( .LO ( optlc_net_3362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3721 ( .LO ( optlc_net_3363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3722 ( .LO ( optlc_net_3364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3723 ( .LO ( optlc_net_3365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3724 ( .LO ( optlc_net_3366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3725 ( .LO ( optlc_net_3367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3726 ( .LO ( optlc_net_3368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3727 ( .LO ( optlc_net_3369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3728 ( .LO ( optlc_net_3370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3729 ( .LO ( optlc_net_3371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3730 ( .LO ( optlc_net_3372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3731 ( .LO ( optlc_net_3373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3732 ( .LO ( optlc_net_3374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3733 ( .LO ( optlc_net_3375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3734 ( .LO ( optlc_net_3376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3735 ( .LO ( optlc_net_3377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3736 ( .LO ( optlc_net_3378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3737 ( .LO ( optlc_net_3379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3738 ( .LO ( optlc_net_3380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3739 ( .LO ( optlc_net_3381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3740 ( .LO ( optlc_net_3382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3741 ( .LO ( optlc_net_3383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3742 ( .LO ( optlc_net_3384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3743 ( .LO ( optlc_net_3385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3744 ( .LO ( optlc_net_3386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3745 ( .LO ( optlc_net_3387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3746 ( .LO ( optlc_net_3388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3747 ( .LO ( optlc_net_3389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3748 ( .LO ( optlc_net_3390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3749 ( .LO ( optlc_net_3391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3750 ( .LO ( optlc_net_3392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3751 ( .LO ( optlc_net_3393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3752 ( .LO ( optlc_net_3394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3753 ( .LO ( optlc_net_3395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3754 ( .LO ( optlc_net_3396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3755 ( .LO ( optlc_net_3397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3756 ( .LO ( optlc_net_3398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3757 ( .LO ( optlc_net_3399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3758 ( .LO ( optlc_net_3400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3759 ( .LO ( optlc_net_3401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3760 ( .LO ( optlc_net_3402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3761 ( .LO ( optlc_net_3403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3762 ( .LO ( optlc_net_3404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3763 ( .LO ( optlc_net_3405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3764 ( .LO ( optlc_net_3406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3765 ( .LO ( optlc_net_3407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3766 ( .LO ( optlc_net_3408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3767 ( .LO ( optlc_net_3409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3768 ( .LO ( optlc_net_3410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3769 ( .LO ( optlc_net_3411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3770 ( .LO ( optlc_net_3412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3771 ( .LO ( optlc_net_3413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3772 ( .LO ( optlc_net_3414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3773 ( .LO ( optlc_net_3415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3774 ( .LO ( optlc_net_3416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3775 ( .LO ( optlc_net_3417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3776 ( .LO ( optlc_net_3418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3777 ( .LO ( optlc_net_3419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3778 ( .LO ( optlc_net_3420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3779 ( .LO ( optlc_net_3421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3780 ( .LO ( optlc_net_3422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3781 ( .LO ( optlc_net_3423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3782 ( .LO ( optlc_net_3424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3783 ( .LO ( optlc_net_3425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3784 ( .LO ( optlc_net_3426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3785 ( .LO ( optlc_net_3427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3786 ( .LO ( optlc_net_3428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3787 ( .LO ( optlc_net_3429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3788 ( .LO ( optlc_net_3430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3789 ( .LO ( optlc_net_3431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3790 ( .LO ( optlc_net_3432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3791 ( .LO ( optlc_net_3433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3792 ( .LO ( optlc_net_3434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3793 ( .LO ( optlc_net_3435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3794 ( .LO ( optlc_net_3436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3795 ( .LO ( optlc_net_3437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3796 ( .LO ( optlc_net_3438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3797 ( .LO ( optlc_net_3439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3798 ( .LO ( optlc_net_3440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3799 ( .LO ( optlc_net_3441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3800 ( .LO ( optlc_net_3442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3801 ( .LO ( optlc_net_3443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3802 ( .LO ( optlc_net_3444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3803 ( .LO ( optlc_net_3445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3804 ( .LO ( optlc_net_3446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3805 ( .LO ( optlc_net_3447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3806 ( .LO ( optlc_net_3448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3807 ( .LO ( optlc_net_3449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3808 ( .LO ( optlc_net_3450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3809 ( .LO ( optlc_net_3451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3810 ( .LO ( optlc_net_3452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3811 ( .LO ( optlc_net_3453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3812 ( .LO ( optlc_net_3454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3813 ( .LO ( optlc_net_3455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3814 ( .LO ( optlc_net_3456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3815 ( .LO ( optlc_net_3457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3816 ( .LO ( optlc_net_3458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3817 ( .LO ( optlc_net_3459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3818 ( .LO ( optlc_net_3460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3819 ( .LO ( optlc_net_3461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3820 ( .LO ( optlc_net_3462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3821 ( .LO ( optlc_net_3463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3822 ( .LO ( optlc_net_3464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3823 ( .LO ( optlc_net_3465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3824 ( .LO ( optlc_net_3466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3825 ( .LO ( optlc_net_3467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3826 ( .LO ( optlc_net_3468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3827 ( .LO ( optlc_net_3469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3828 ( .LO ( optlc_net_3470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3829 ( .LO ( optlc_net_3471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3830 ( .LO ( optlc_net_3472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3831 ( .LO ( optlc_net_3473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3832 ( .LO ( optlc_net_3474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3833 ( .LO ( optlc_net_3475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3834 ( .LO ( optlc_net_3476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3835 ( .LO ( optlc_net_3477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3836 ( .LO ( optlc_net_3478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3837 ( .LO ( optlc_net_3479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3838 ( .LO ( optlc_net_3480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3839 ( .LO ( optlc_net_3481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3840 ( .LO ( optlc_net_3482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3841 ( .LO ( optlc_net_3483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3842 ( .LO ( optlc_net_3484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3843 ( .LO ( optlc_net_3485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3844 ( .LO ( optlc_net_3486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3845 ( .LO ( optlc_net_3487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3846 ( .LO ( optlc_net_3488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3847 ( .LO ( optlc_net_3489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3848 ( .LO ( optlc_net_3490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3849 ( .LO ( optlc_net_3491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3850 ( .LO ( optlc_net_3492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3851 ( .LO ( optlc_net_3493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3852 ( .LO ( optlc_net_3494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3853 ( .LO ( optlc_net_3495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3854 ( .LO ( optlc_net_3496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3855 ( .LO ( optlc_net_3497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3856 ( .LO ( optlc_net_3498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3857 ( .LO ( optlc_net_3499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3858 ( .LO ( optlc_net_3500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3859 ( .LO ( optlc_net_3501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3860 ( .LO ( optlc_net_3502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3861 ( .LO ( optlc_net_3503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3862 ( .LO ( optlc_net_3504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3863 ( .LO ( optlc_net_3505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3864 ( .LO ( optlc_net_3506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3865 ( .LO ( optlc_net_3507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3866 ( .LO ( optlc_net_3508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3867 ( .LO ( optlc_net_3509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3868 ( .LO ( optlc_net_3510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3869 ( .LO ( optlc_net_3511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3870 ( .LO ( optlc_net_3512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3871 ( .LO ( optlc_net_3513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3872 ( .LO ( optlc_net_3514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3873 ( .LO ( optlc_net_3515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3874 ( .LO ( optlc_net_3516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3609 ) ) ;
+endmodule
+
+
diff --git a/SOFA_CHD/fpga_top/fpga_top_icv_in_design.top_only.pt.v b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..60eeec2
--- /dev/null
+++ b/SOFA_CHD/fpga_top/fpga_top_icv_in_design.top_only.pt.v
@@ -0,0 +1,10014 @@
+//
+//
+//
+//
+//
+//
+module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 ,
+ vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i ,
+ wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in ,
+ la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ ,
+ analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ ,
+ analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ ,
+ analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ ,
+ analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ ,
+ analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ ,
+ analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ ,
+ analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ ,
+ analog_io_9_ , user_clock2 ) ;
+inout vdda1 ;
+inout vdda2 ;
+inout vssa1 ;
+inout vssa2 ;
+inout vccd1 ;
+inout vccd2 ;
+inout vssd1 ;
+inout vssd2 ;
+input wb_clk_i ;
+input wb_rst_i ;
+input wbs_stb_i ;
+input wbs_cyc_i ;
+input wbs_we_i ;
+input [3:0] wbs_sel_i ;
+input [31:0] wbs_dat_i ;
+input [31:0] wbs_adr_i ;
+output wbs_ack_o ;
+output [31:0] wbs_dat_o ;
+input [127:0] la_data_in ;
+output [127:0] la_data_out ;
+input [127:0] la_oen ;
+input [37:0] io_in ;
+output [37:0] io_out ;
+output [37:0] io_oeb ;
+inout analog_io_0_ ;
+inout analog_io_10_ ;
+inout analog_io_11_ ;
+inout analog_io_12_ ;
+inout analog_io_13_ ;
+inout analog_io_14_ ;
+inout analog_io_15_ ;
+inout analog_io_16_ ;
+inout analog_io_17_ ;
+inout analog_io_18_ ;
+inout analog_io_19_ ;
+inout analog_io_1_ ;
+inout analog_io_20_ ;
+inout analog_io_21_ ;
+inout analog_io_22_ ;
+inout analog_io_23_ ;
+inout analog_io_24_ ;
+inout analog_io_25_ ;
+inout analog_io_26_ ;
+inout analog_io_27_ ;
+inout analog_io_28_ ;
+inout analog_io_29_ ;
+inout analog_io_2_ ;
+inout analog_io_30_ ;
+inout analog_io_3_ ;
+inout analog_io_4_ ;
+inout analog_io_5_ ;
+inout analog_io_6_ ;
+inout analog_io_7_ ;
+inout analog_io_8_ ;
+inout analog_io_9_ ;
+input user_clock2 ;
+
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+wire ccff_head ;
+wire sc_tail ;
+wire pReset ;
+wire Reset ;
+wire IO_ISOL_N ;
+wire Test_en ;
+wire prog_clk ;
+wire clk ;
+wire ccff_tail ;
+wire sc_head ;
+wire wb_la_switch ;
+
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ;
+assign ccff_head = io_in[12] ;
+assign sc_tail = io_out[11] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ;
+assign pReset = io_in[3] ;
+assign Reset = io_in[2] ;
+assign IO_ISOL_N = io_in[1] ;
+assign Test_en = io_in[0] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = la_data_out[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = la_data_out[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[84] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[83] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[82] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[81] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[80] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[79] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[78] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[77] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[76] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[75] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[74] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[73] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[72] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[71] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[70] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[69] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[68] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[67] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[66] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[65] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[64] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[63] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[62] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[61] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[60] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[59] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[58] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[57] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[56] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[55] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[54] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[53] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[52] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[51] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[50] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[49] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[48] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[47] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[46] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[45] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[44] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[43] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[42] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[41] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[40] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[39] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[38] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[37] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[36] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[26] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[25] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[12] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[11] ;
+assign prog_clk = io_in[37] ;
+assign clk = io_in[36] ;
+assign ccff_tail = io_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ;
+assign sc_head = io_in[26] ;
+assign wb_la_switch = io_in[25] ;
+
+sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) ,
+ .Y ( wb_la_switch_b ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[0] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[116] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[1] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[115] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[2] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[114] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[3] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[113] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[4] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[112] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[5] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[111] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[6] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[110] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[7] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[109] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[8] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[108] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[9] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[107] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[10] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[106] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[11] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[105] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[12] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[104] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[13] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[103] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[14] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[102] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[15] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[101] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[16] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[100] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[17] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[99] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[18] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[98] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[19] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[97] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[20] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[96] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[21] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[95] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[22] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[94] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[23] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[93] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[24] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[92] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[25] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[91] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[26] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[90] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[27] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[89] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[28] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[88] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[29] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[87] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[30] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[86] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[31] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) ,
+ .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) ,
+ .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) ,
+ .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) ,
+ .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) ,
+ .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) ,
+ .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) ,
+ .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) ,
+ .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) ,
+ .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) ,
+ .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) ,
+ .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) ,
+ .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) ,
+ .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) ,
+ .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) ,
+ .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) ,
+ .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) ,
+ .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) ,
+ .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) ,
+ .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) ,
+ .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) ,
+ .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) ,
+ .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) ,
+ .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) ,
+ .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) ,
+ .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) ,
+ .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) ,
+ .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) ,
+ .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) ,
+ .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) ,
+ .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) ,
+ .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) ,
+ .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) ,
+ .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) ,
+ .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) ,
+ .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) ,
+ .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) ,
+ .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) ,
+ .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) ,
+ .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) ,
+ .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) ,
+ .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) ,
+ .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) ,
+ .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) ,
+ .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) ,
+ .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) ,
+ .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) ,
+ .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) ,
+ .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) ,
+ .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) ,
+ .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) ,
+ .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) ,
+ .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) ,
+ .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) ,
+ .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) ,
+ .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) ,
+ .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) ,
+ .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) ,
+ .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) ,
+ .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) ,
+ .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) ,
+ .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) ,
+ .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) ,
+ .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) ,
+ .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) ,
+ .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) ,
+ .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) ,
+ .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) ,
+ .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) ,
+ .A1 ( wbs_we_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) ,
+ .A1 ( wbs_stb_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) ,
+ .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_ack_o ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[13] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) ,
+ .A1 ( wb_rst_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) ,
+ .A1 ( wb_clk_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ;
+fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) ,
+ .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) ,
+ .Reset ( io_in[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] ,
+ io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] ,
+ io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] ,
+ io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] ,
+ la_data_in[127] , la_data_in[126] , la_data_in[125] ,
+ la_data_in[124] , la_data_in[123] , la_data_in[122] ,
+ la_data_in[121] , la_data_in[120] , la_data_in[119] ,
+ la_data_in[118] , la_data_in[117] , la_data_in[116] ,
+ la_data_in[115] , la_data_in[114] , la_data_in[113] ,
+ la_data_in[112] , la_data_in[111] , la_data_in[110] ,
+ la_data_in[109] , la_data_in[108] , la_data_in[107] ,
+ la_data_in[106] , la_data_in[105] , la_data_in[104] ,
+ la_data_in[103] , la_data_in[102] , la_data_in[101] ,
+ la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] ,
+ la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] ,
+ la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] ,
+ la_data_in[88] , la_data_in[87] , la_data_in[86] , la_data_in[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[13] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] ,
+ io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] ,
+ io_in[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] ,
+ io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] ,
+ io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] ,
+ io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] ,
+ io_out[5] , io_out[4] , la_data_out[127] , la_data_out[126] ,
+ la_data_out[125] , la_data_out[124] , la_data_out[123] ,
+ la_data_out[122] , la_data_out[121] , la_data_out[120] ,
+ la_data_out[119] , la_data_out[118] , la_data_out[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[84] ,
+ la_data_out[83] , la_data_out[82] , la_data_out[81] ,
+ la_data_out[80] , la_data_out[79] , la_data_out[78] ,
+ la_data_out[77] , la_data_out[76] , la_data_out[75] ,
+ la_data_out[74] , la_data_out[73] , la_data_out[72] ,
+ la_data_out[71] , la_data_out[70] , la_data_out[69] ,
+ la_data_out[68] , la_data_out[67] , la_data_out[66] ,
+ la_data_out[65] , la_data_out[64] , la_data_out[63] ,
+ la_data_out[62] , la_data_out[61] , la_data_out[60] ,
+ la_data_out[59] , la_data_out[58] , la_data_out[57] ,
+ la_data_out[56] , la_data_out[55] , la_data_out[54] ,
+ la_data_out[53] , la_data_out[52] , la_data_out[51] ,
+ la_data_out[50] , la_data_out[49] , la_data_out[48] ,
+ la_data_out[47] , la_data_out[46] , la_data_out[45] ,
+ la_data_out[44] , la_data_out[43] , la_data_out[42] ,
+ la_data_out[41] , la_data_out[40] , la_data_out[39] ,
+ la_data_out[38] , la_data_out[37] , la_data_out[36] ,
+ la_data_out[35] , la_data_out[34] , la_data_out[33] ,
+ la_data_out[32] , la_data_out[31] , la_data_out[30] ,
+ la_data_out[29] , la_data_out[28] , la_data_out[27] ,
+ la_data_out[26] , la_data_out[25] , la_data_out[24] ,
+ la_data_out[23] , la_data_out[22] , la_data_out[21] ,
+ la_data_out[20] , la_data_out[19] , la_data_out[18] ,
+ la_data_out[17] , la_data_out[16] , la_data_out[15] ,
+ la_data_out[14] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ,
+ la_data_out[12] , la_data_out[11] , io_out[34] , io_out[33] ,
+ io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] ,
+ io_out[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] ,
+ io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] ,
+ io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] ,
+ io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] ,
+ io_oeb[5] , io_oeb[4] , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] ,
+ io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] ,
+ io_oeb[27] } ) ,
+ .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) ,
+ .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) ,
+ .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , .p0 ( optlc_net_20 ) ,
+ .p1 ( optlc_net_21 ) , .p2 ( optlc_net_22 ) , .p3 ( optlc_net_23 ) ,
+ .p4 ( optlc_net_24 ) , .p5 ( optlc_net_25 ) , .p6 ( optlc_net_26 ) ,
+ .p7 ( optlc_net_27 ) , .p8 ( optlc_net_28 ) , .p9 ( optlc_net_29 ) ,
+ .p10 ( optlc_net_30 ) , .p11 ( optlc_net_31 ) , .p12 ( optlc_net_32 ) ,
+ .p13 ( optlc_net_33 ) , .p14 ( optlc_net_34 ) , .p15 ( optlc_net_35 ) ,
+ .p16 ( optlc_net_36 ) , .p17 ( optlc_net_37 ) , .p18 ( optlc_net_38 ) ,
+ .p19 ( optlc_net_39 ) , .p20 ( optlc_net_40 ) , .p21 ( optlc_net_41 ) ,
+ .p22 ( optlc_net_42 ) , .p23 ( optlc_net_43 ) , .p24 ( optlc_net_44 ) ,
+ .p25 ( optlc_net_45 ) , .p26 ( optlc_net_46 ) , .p27 ( optlc_net_47 ) ,
+ .p28 ( optlc_net_48 ) , .p29 ( optlc_net_49 ) , .p30 ( optlc_net_50 ) ,
+ .p31 ( optlc_net_51 ) , .p32 ( optlc_net_52 ) , .p33 ( optlc_net_53 ) ,
+ .p34 ( optlc_net_54 ) , .p35 ( optlc_net_55 ) , .p36 ( optlc_net_56 ) ,
+ .p37 ( optlc_net_57 ) , .p38 ( optlc_net_58 ) , .p39 ( optlc_net_59 ) ,
+ .p40 ( optlc_net_60 ) , .p41 ( optlc_net_61 ) , .p42 ( optlc_net_62 ) ,
+ .p43 ( optlc_net_63 ) , .p44 ( optlc_net_64 ) , .p45 ( optlc_net_65 ) ,
+ .p46 ( optlc_net_66 ) , .p47 ( optlc_net_67 ) , .p48 ( optlc_net_68 ) ,
+ .p49 ( optlc_net_69 ) , .p50 ( optlc_net_70 ) , .p51 ( optlc_net_71 ) ,
+ .p52 ( optlc_net_72 ) , .p53 ( optlc_net_73 ) , .p54 ( optlc_net_74 ) ,
+ .p55 ( optlc_net_75 ) , .p56 ( optlc_net_76 ) , .p57 ( optlc_net_77 ) ,
+ .p58 ( optlc_net_78 ) , .p59 ( optlc_net_79 ) , .p60 ( optlc_net_80 ) ,
+ .p61 ( optlc_net_81 ) , .p62 ( optlc_net_82 ) , .p63 ( optlc_net_83 ) ,
+ .p64 ( optlc_net_84 ) , .p65 ( optlc_net_85 ) , .p66 ( optlc_net_86 ) ,
+ .p67 ( optlc_net_87 ) , .p68 ( optlc_net_88 ) , .p69 ( optlc_net_89 ) ,
+ .p70 ( optlc_net_90 ) , .p71 ( optlc_net_91 ) , .p72 ( optlc_net_92 ) ,
+ .p73 ( optlc_net_93 ) , .p74 ( optlc_net_94 ) , .p75 ( optlc_net_95 ) ,
+ .p76 ( optlc_net_96 ) , .p77 ( optlc_net_97 ) , .p78 ( optlc_net_98 ) ,
+ .p79 ( optlc_net_99 ) , .p80 ( optlc_net_100 ) , .p81 ( optlc_net_101 ) ,
+ .p82 ( optlc_net_102 ) , .p83 ( optlc_net_103 ) , .p84 ( optlc_net_104 ) ,
+ .p85 ( optlc_net_105 ) , .p86 ( optlc_net_106 ) , .p87 ( optlc_net_107 ) ,
+ .p88 ( optlc_net_108 ) , .p89 ( optlc_net_109 ) , .p90 ( optlc_net_110 ) ,
+ .p91 ( optlc_net_111 ) , .p92 ( optlc_net_112 ) , .p93 ( optlc_net_113 ) ,
+ .p94 ( optlc_net_114 ) , .p95 ( optlc_net_115 ) , .p96 ( optlc_net_116 ) ,
+ .p97 ( optlc_net_117 ) , .p98 ( optlc_net_118 ) , .p99 ( optlc_net_119 ) ,
+ .p100 ( optlc_net_120 ) , .p101 ( optlc_net_121 ) ,
+ .p102 ( optlc_net_122 ) , .p103 ( optlc_net_123 ) ,
+ .p104 ( optlc_net_124 ) , .p105 ( optlc_net_125 ) ,
+ .p106 ( optlc_net_126 ) , .p107 ( optlc_net_127 ) ,
+ .p108 ( optlc_net_128 ) , .p109 ( optlc_net_129 ) ,
+ .p110 ( optlc_net_130 ) , .p111 ( optlc_net_131 ) ,
+ .p112 ( optlc_net_132 ) , .p113 ( optlc_net_133 ) ,
+ .p114 ( optlc_net_134 ) , .p115 ( optlc_net_135 ) ,
+ .p116 ( optlc_net_136 ) , .p117 ( optlc_net_137 ) ,
+ .p118 ( optlc_net_138 ) , .p119 ( optlc_net_139 ) ,
+ .p120 ( optlc_net_140 ) , .p121 ( optlc_net_141 ) ,
+ .p122 ( optlc_net_142 ) , .p123 ( optlc_net_143 ) ,
+ .p124 ( optlc_net_144 ) , .p125 ( optlc_net_145 ) ,
+ .p126 ( optlc_net_146 ) , .p127 ( optlc_net_147 ) ,
+ .p128 ( optlc_net_148 ) , .p129 ( optlc_net_149 ) ,
+ .p130 ( optlc_net_150 ) , .p131 ( optlc_net_151 ) ,
+ .p132 ( optlc_net_152 ) , .p133 ( optlc_net_153 ) ,
+ .p134 ( optlc_net_154 ) , .p135 ( optlc_net_155 ) ,
+ .p136 ( optlc_net_156 ) , .p137 ( optlc_net_157 ) ,
+ .p138 ( optlc_net_158 ) , .p139 ( optlc_net_159 ) ,
+ .p140 ( optlc_net_160 ) , .p141 ( optlc_net_161 ) ,
+ .p142 ( optlc_net_162 ) , .p143 ( optlc_net_163 ) ,
+ .p144 ( optlc_net_164 ) , .p145 ( optlc_net_165 ) ,
+ .p146 ( optlc_net_166 ) , .p147 ( optlc_net_167 ) ,
+ .p148 ( optlc_net_168 ) , .p149 ( optlc_net_169 ) ,
+ .p150 ( optlc_net_170 ) , .p151 ( optlc_net_171 ) ,
+ .p152 ( optlc_net_172 ) , .p153 ( optlc_net_173 ) ,
+ .p154 ( optlc_net_174 ) , .p155 ( optlc_net_175 ) ,
+ .p156 ( optlc_net_176 ) , .p157 ( optlc_net_177 ) ,
+ .p158 ( optlc_net_178 ) , .p159 ( optlc_net_179 ) ,
+ .p160 ( optlc_net_180 ) , .p161 ( optlc_net_181 ) ,
+ .p162 ( optlc_net_182 ) , .p163 ( optlc_net_183 ) ,
+ .p164 ( optlc_net_184 ) , .p165 ( optlc_net_185 ) ,
+ .p166 ( optlc_net_186 ) , .p167 ( optlc_net_187 ) ,
+ .p168 ( optlc_net_188 ) , .p169 ( optlc_net_189 ) ,
+ .p170 ( optlc_net_190 ) , .p171 ( optlc_net_191 ) ,
+ .p172 ( optlc_net_192 ) , .p173 ( optlc_net_193 ) ,
+ .p174 ( optlc_net_194 ) , .p175 ( optlc_net_195 ) ,
+ .p176 ( optlc_net_196 ) , .p177 ( optlc_net_197 ) ,
+ .p178 ( optlc_net_198 ) , .p179 ( optlc_net_199 ) ,
+ .p180 ( optlc_net_200 ) , .p181 ( optlc_net_201 ) ,
+ .p182 ( optlc_net_202 ) , .p183 ( optlc_net_203 ) ,
+ .p184 ( optlc_net_204 ) , .p185 ( optlc_net_205 ) ,
+ .p186 ( optlc_net_206 ) , .p187 ( optlc_net_207 ) ,
+ .p188 ( optlc_net_208 ) , .p189 ( optlc_net_209 ) ,
+ .p190 ( optlc_net_210 ) , .p191 ( optlc_net_211 ) ,
+ .p192 ( optlc_net_212 ) , .p193 ( optlc_net_213 ) ,
+ .p194 ( optlc_net_214 ) , .p195 ( optlc_net_215 ) ,
+ .p196 ( optlc_net_216 ) , .p197 ( optlc_net_217 ) ,
+ .p198 ( optlc_net_218 ) , .p199 ( optlc_net_219 ) ,
+ .p200 ( optlc_net_220 ) , .p201 ( optlc_net_221 ) ,
+ .p202 ( optlc_net_222 ) , .p203 ( optlc_net_223 ) ,
+ .p204 ( optlc_net_224 ) , .p205 ( optlc_net_225 ) ,
+ .p206 ( optlc_net_226 ) , .p207 ( optlc_net_227 ) ,
+ .p208 ( optlc_net_228 ) , .p209 ( optlc_net_229 ) ,
+ .p210 ( optlc_net_230 ) , .p211 ( optlc_net_231 ) ,
+ .p212 ( optlc_net_232 ) , .p213 ( optlc_net_233 ) ,
+ .p214 ( optlc_net_234 ) , .p215 ( optlc_net_235 ) ,
+ .p216 ( optlc_net_236 ) , .p217 ( optlc_net_237 ) ,
+ .p218 ( optlc_net_238 ) , .p219 ( optlc_net_239 ) ,
+ .p220 ( optlc_net_240 ) , .p221 ( optlc_net_241 ) ,
+ .p222 ( optlc_net_242 ) , .p223 ( optlc_net_243 ) ,
+ .p224 ( optlc_net_244 ) , .p225 ( optlc_net_245 ) ,
+ .p226 ( optlc_net_246 ) , .p227 ( optlc_net_247 ) ,
+ .p228 ( optlc_net_248 ) , .p229 ( optlc_net_249 ) ,
+ .p230 ( optlc_net_250 ) , .p231 ( optlc_net_251 ) ,
+ .p232 ( optlc_net_252 ) , .p233 ( optlc_net_253 ) ,
+ .p234 ( optlc_net_254 ) , .p235 ( optlc_net_255 ) ,
+ .p236 ( optlc_net_256 ) , .p237 ( optlc_net_257 ) ,
+ .p238 ( optlc_net_258 ) , .p239 ( optlc_net_259 ) ,
+ .p240 ( optlc_net_260 ) , .p241 ( optlc_net_261 ) ,
+ .p242 ( optlc_net_262 ) , .p243 ( optlc_net_263 ) ,
+ .p244 ( optlc_net_264 ) , .p245 ( optlc_net_265 ) ,
+ .p246 ( optlc_net_266 ) , .p247 ( optlc_net_267 ) ,
+ .p248 ( optlc_net_268 ) , .p249 ( optlc_net_269 ) ,
+ .p250 ( optlc_net_270 ) , .p251 ( optlc_net_271 ) ,
+ .p252 ( optlc_net_272 ) , .p253 ( optlc_net_273 ) ,
+ .p254 ( optlc_net_274 ) , .p255 ( optlc_net_275 ) ,
+ .p256 ( optlc_net_276 ) , .p257 ( optlc_net_277 ) ,
+ .p258 ( optlc_net_278 ) , .p259 ( optlc_net_279 ) ,
+ .p260 ( optlc_net_280 ) , .p261 ( optlc_net_281 ) ,
+ .p262 ( optlc_net_282 ) , .p263 ( optlc_net_283 ) ,
+ .p264 ( optlc_net_284 ) , .p265 ( optlc_net_285 ) ,
+ .p266 ( optlc_net_286 ) , .p267 ( optlc_net_287 ) ,
+ .p268 ( optlc_net_288 ) , .p269 ( optlc_net_289 ) ,
+ .p270 ( optlc_net_290 ) , .p271 ( optlc_net_291 ) ,
+ .p272 ( optlc_net_292 ) , .p273 ( optlc_net_293 ) ,
+ .p274 ( optlc_net_294 ) , .p275 ( optlc_net_295 ) ,
+ .p276 ( optlc_net_296 ) , .p277 ( optlc_net_297 ) ,
+ .p278 ( optlc_net_298 ) , .p279 ( optlc_net_299 ) ,
+ .p280 ( optlc_net_300 ) , .p281 ( optlc_net_301 ) ,
+ .p282 ( optlc_net_302 ) , .p283 ( optlc_net_303 ) ,
+ .p284 ( optlc_net_304 ) , .p285 ( optlc_net_305 ) ,
+ .p286 ( optlc_net_306 ) , .p287 ( optlc_net_307 ) ,
+ .p288 ( optlc_net_308 ) , .p289 ( optlc_net_309 ) ,
+ .p290 ( optlc_net_310 ) , .p291 ( optlc_net_311 ) ,
+ .p292 ( optlc_net_312 ) , .p293 ( optlc_net_313 ) ,
+ .p294 ( optlc_net_314 ) , .p295 ( optlc_net_315 ) ,
+ .p296 ( optlc_net_316 ) , .p297 ( optlc_net_317 ) ,
+ .p298 ( optlc_net_318 ) , .p299 ( optlc_net_319 ) ,
+ .p300 ( optlc_net_320 ) , .p301 ( optlc_net_321 ) ,
+ .p302 ( optlc_net_322 ) , .p303 ( optlc_net_323 ) ,
+ .p304 ( optlc_net_324 ) , .p305 ( optlc_net_325 ) ,
+ .p306 ( optlc_net_326 ) , .p307 ( optlc_net_327 ) ,
+ .p308 ( optlc_net_328 ) , .p309 ( optlc_net_329 ) ,
+ .p310 ( optlc_net_330 ) , .p311 ( optlc_net_331 ) ,
+ .p312 ( optlc_net_332 ) , .p313 ( optlc_net_333 ) ,
+ .p314 ( optlc_net_334 ) , .p315 ( optlc_net_335 ) ,
+ .p316 ( optlc_net_336 ) , .p317 ( optlc_net_337 ) ,
+ .p318 ( optlc_net_338 ) , .p319 ( optlc_net_339 ) ,
+ .p320 ( optlc_net_340 ) , .p321 ( optlc_net_341 ) ,
+ .p322 ( optlc_net_342 ) , .p323 ( optlc_net_343 ) ,
+ .p324 ( optlc_net_344 ) , .p325 ( optlc_net_345 ) ,
+ .p326 ( optlc_net_346 ) , .p327 ( optlc_net_347 ) ,
+ .p328 ( optlc_net_348 ) , .p329 ( optlc_net_349 ) ,
+ .p330 ( optlc_net_350 ) , .p331 ( optlc_net_351 ) ,
+ .p332 ( optlc_net_352 ) , .p333 ( optlc_net_353 ) ,
+ .p334 ( optlc_net_354 ) , .p335 ( optlc_net_355 ) ,
+ .p336 ( optlc_net_356 ) , .p337 ( optlc_net_357 ) ,
+ .p338 ( optlc_net_358 ) , .p339 ( optlc_net_359 ) ,
+ .p340 ( optlc_net_360 ) , .p341 ( optlc_net_361 ) ,
+ .p342 ( optlc_net_362 ) , .p343 ( optlc_net_363 ) ,
+ .p344 ( optlc_net_364 ) , .p345 ( optlc_net_365 ) ,
+ .p346 ( optlc_net_366 ) , .p347 ( optlc_net_367 ) ,
+ .p348 ( optlc_net_368 ) , .p349 ( optlc_net_369 ) ,
+ .p350 ( optlc_net_370 ) , .p351 ( optlc_net_371 ) ,
+ .p352 ( optlc_net_372 ) , .p353 ( optlc_net_373 ) ,
+ .p354 ( optlc_net_374 ) , .p355 ( optlc_net_375 ) ,
+ .p356 ( optlc_net_376 ) , .p357 ( optlc_net_377 ) ,
+ .p358 ( optlc_net_378 ) , .p359 ( optlc_net_379 ) ,
+ .p360 ( optlc_net_380 ) , .p361 ( optlc_net_381 ) ,
+ .p362 ( optlc_net_382 ) , .p363 ( optlc_net_383 ) ,
+ .p364 ( optlc_net_384 ) , .p365 ( optlc_net_385 ) ,
+ .p366 ( optlc_net_386 ) , .p367 ( optlc_net_387 ) ,
+ .p368 ( optlc_net_388 ) , .p369 ( optlc_net_389 ) ,
+ .p370 ( optlc_net_390 ) , .p371 ( optlc_net_391 ) ,
+ .p372 ( optlc_net_392 ) , .p373 ( optlc_net_393 ) ,
+ .p374 ( optlc_net_394 ) , .p375 ( optlc_net_395 ) ,
+ .p376 ( optlc_net_396 ) , .p377 ( optlc_net_397 ) ,
+ .p378 ( optlc_net_398 ) , .p379 ( optlc_net_399 ) ,
+ .p380 ( optlc_net_400 ) , .p381 ( optlc_net_401 ) ,
+ .p382 ( optlc_net_402 ) , .p383 ( optlc_net_403 ) ,
+ .p384 ( optlc_net_404 ) , .p385 ( optlc_net_405 ) ,
+ .p386 ( optlc_net_406 ) , .p387 ( optlc_net_407 ) ,
+ .p388 ( optlc_net_408 ) , .p389 ( optlc_net_409 ) ,
+ .p390 ( optlc_net_410 ) , .p391 ( optlc_net_411 ) ,
+ .p392 ( optlc_net_412 ) , .p393 ( optlc_net_413 ) ,
+ .p394 ( optlc_net_414 ) , .p395 ( optlc_net_415 ) ,
+ .p396 ( optlc_net_416 ) , .p397 ( optlc_net_417 ) ,
+ .p398 ( optlc_net_418 ) , .p399 ( optlc_net_419 ) ,
+ .p400 ( optlc_net_420 ) , .p401 ( optlc_net_421 ) ,
+ .p402 ( optlc_net_422 ) , .p403 ( optlc_net_423 ) ,
+ .p404 ( optlc_net_424 ) , .p405 ( optlc_net_425 ) ,
+ .p406 ( optlc_net_426 ) , .p407 ( optlc_net_427 ) ,
+ .p408 ( optlc_net_428 ) , .p409 ( optlc_net_429 ) ,
+ .p410 ( optlc_net_430 ) , .p411 ( optlc_net_431 ) ,
+ .p412 ( optlc_net_432 ) , .p413 ( optlc_net_433 ) ,
+ .p414 ( optlc_net_434 ) , .p415 ( optlc_net_435 ) ,
+ .p416 ( optlc_net_436 ) , .p417 ( optlc_net_437 ) ,
+ .p418 ( optlc_net_438 ) , .p419 ( optlc_net_439 ) ,
+ .p420 ( optlc_net_440 ) , .p421 ( optlc_net_441 ) ,
+ .p422 ( optlc_net_442 ) , .p423 ( optlc_net_443 ) ,
+ .p424 ( optlc_net_444 ) , .p425 ( optlc_net_445 ) ,
+ .p426 ( optlc_net_446 ) , .p427 ( optlc_net_447 ) ,
+ .p428 ( optlc_net_448 ) , .p429 ( optlc_net_449 ) ,
+ .p430 ( optlc_net_450 ) , .p431 ( optlc_net_451 ) ,
+ .p432 ( optlc_net_452 ) , .p433 ( optlc_net_453 ) ,
+ .p434 ( optlc_net_454 ) , .p435 ( optlc_net_455 ) ,
+ .p436 ( optlc_net_456 ) , .p437 ( optlc_net_457 ) ,
+ .p438 ( optlc_net_458 ) , .p439 ( optlc_net_459 ) ,
+ .p440 ( optlc_net_460 ) , .p441 ( optlc_net_461 ) ,
+ .p442 ( optlc_net_462 ) , .p443 ( optlc_net_463 ) ,
+ .p444 ( optlc_net_464 ) , .p445 ( optlc_net_465 ) ,
+ .p446 ( optlc_net_466 ) , .p447 ( optlc_net_467 ) ,
+ .p448 ( optlc_net_468 ) , .p449 ( optlc_net_469 ) ,
+ .p450 ( optlc_net_470 ) , .p451 ( optlc_net_471 ) ,
+ .p452 ( optlc_net_472 ) , .p453 ( optlc_net_473 ) ,
+ .p454 ( optlc_net_474 ) , .p455 ( optlc_net_475 ) ,
+ .p456 ( optlc_net_476 ) , .p457 ( optlc_net_477 ) ,
+ .p458 ( optlc_net_478 ) , .p459 ( optlc_net_479 ) ,
+ .p460 ( optlc_net_480 ) , .p461 ( optlc_net_481 ) ,
+ .p462 ( optlc_net_482 ) , .p463 ( optlc_net_483 ) ,
+ .p464 ( optlc_net_484 ) , .p465 ( optlc_net_485 ) ,
+ .p466 ( optlc_net_486 ) , .p467 ( optlc_net_487 ) ,
+ .p468 ( optlc_net_488 ) , .p469 ( optlc_net_489 ) ,
+ .p470 ( optlc_net_490 ) , .p471 ( optlc_net_491 ) ,
+ .p472 ( optlc_net_492 ) , .p473 ( optlc_net_493 ) ,
+ .p474 ( optlc_net_494 ) , .p475 ( optlc_net_495 ) ,
+ .p476 ( optlc_net_496 ) , .p477 ( optlc_net_497 ) ,
+ .p478 ( optlc_net_498 ) , .p479 ( optlc_net_499 ) ,
+ .p480 ( optlc_net_500 ) , .p481 ( optlc_net_501 ) ,
+ .p482 ( optlc_net_502 ) , .p483 ( optlc_net_503 ) ,
+ .p484 ( optlc_net_504 ) , .p485 ( optlc_net_505 ) ,
+ .p486 ( optlc_net_506 ) , .p487 ( optlc_net_507 ) ,
+ .p488 ( optlc_net_508 ) , .p489 ( optlc_net_509 ) ,
+ .p490 ( optlc_net_510 ) , .p491 ( optlc_net_511 ) ,
+ .p492 ( optlc_net_512 ) , .p493 ( optlc_net_513 ) ,
+ .p494 ( optlc_net_514 ) , .p495 ( optlc_net_515 ) ,
+ .p496 ( optlc_net_516 ) , .p497 ( optlc_net_517 ) ,
+ .p498 ( optlc_net_518 ) , .p499 ( optlc_net_519 ) ,
+ .p500 ( optlc_net_520 ) , .p501 ( optlc_net_521 ) ,
+ .p502 ( optlc_net_522 ) , .p503 ( optlc_net_523 ) ,
+ .p504 ( optlc_net_524 ) , .p505 ( optlc_net_525 ) ,
+ .p506 ( optlc_net_526 ) , .p507 ( optlc_net_527 ) ,
+ .p508 ( optlc_net_528 ) , .p509 ( optlc_net_529 ) ,
+ .p510 ( optlc_net_530 ) , .p511 ( optlc_net_531 ) ,
+ .p512 ( optlc_net_532 ) , .p513 ( optlc_net_533 ) ,
+ .p514 ( optlc_net_534 ) , .p515 ( optlc_net_535 ) ,
+ .p516 ( optlc_net_536 ) , .p517 ( optlc_net_537 ) ,
+ .p518 ( optlc_net_538 ) , .p519 ( optlc_net_539 ) ,
+ .p520 ( optlc_net_540 ) , .p521 ( optlc_net_541 ) ,
+ .p522 ( optlc_net_542 ) , .p523 ( optlc_net_543 ) ,
+ .p524 ( optlc_net_544 ) , .p525 ( optlc_net_545 ) ,
+ .p526 ( optlc_net_546 ) , .p527 ( optlc_net_547 ) ,
+ .p528 ( optlc_net_548 ) , .p529 ( optlc_net_549 ) ,
+ .p530 ( optlc_net_550 ) , .p531 ( optlc_net_551 ) ,
+ .p532 ( optlc_net_552 ) , .p533 ( optlc_net_553 ) ,
+ .p534 ( optlc_net_554 ) , .p535 ( optlc_net_555 ) ,
+ .p536 ( optlc_net_556 ) , .p537 ( optlc_net_557 ) ,
+ .p538 ( optlc_net_558 ) , .p539 ( optlc_net_559 ) ,
+ .p540 ( optlc_net_560 ) , .p541 ( optlc_net_561 ) ,
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+ .p544 ( optlc_net_564 ) , .p545 ( optlc_net_565 ) ,
+ .p546 ( optlc_net_566 ) , .p547 ( optlc_net_567 ) ,
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+ .p550 ( optlc_net_570 ) , .p551 ( optlc_net_571 ) ,
+ .p552 ( optlc_net_572 ) , .p553 ( optlc_net_573 ) ,
+ .p554 ( optlc_net_574 ) , .p555 ( optlc_net_575 ) ,
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+ .p570 ( optlc_net_590 ) , .p571 ( optlc_net_591 ) ,
+ .p572 ( optlc_net_592 ) , .p573 ( optlc_net_593 ) ,
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+ .p590 ( optlc_net_610 ) , .p591 ( optlc_net_611 ) ,
+ .p592 ( optlc_net_612 ) , .p593 ( optlc_net_613 ) ,
+ .p594 ( optlc_net_614 ) , .p595 ( optlc_net_615 ) ,
+ .p596 ( optlc_net_616 ) , .p597 ( optlc_net_617 ) ,
+ .p598 ( optlc_net_618 ) , .p599 ( optlc_net_619 ) ,
+ .p600 ( optlc_net_620 ) , .p601 ( optlc_net_621 ) ,
+ .p602 ( optlc_net_622 ) , .p603 ( optlc_net_623 ) ,
+ .p604 ( optlc_net_624 ) , .p605 ( optlc_net_625 ) ,
+ .p606 ( optlc_net_626 ) , .p607 ( optlc_net_627 ) ,
+ .p608 ( optlc_net_628 ) , .p609 ( optlc_net_629 ) ,
+ .p610 ( optlc_net_630 ) , .p611 ( optlc_net_631 ) ,
+ .p612 ( optlc_net_632 ) , .p613 ( optlc_net_633 ) ,
+ .p614 ( optlc_net_634 ) , .p615 ( optlc_net_635 ) ,
+ .p616 ( optlc_net_636 ) , .p617 ( optlc_net_637 ) ,
+ .p618 ( optlc_net_638 ) , .p619 ( optlc_net_639 ) ,
+ .p620 ( optlc_net_640 ) , .p621 ( optlc_net_641 ) ,
+ .p622 ( optlc_net_642 ) , .p623 ( optlc_net_643 ) ,
+ .p624 ( optlc_net_644 ) , .p625 ( optlc_net_645 ) ,
+ .p626 ( optlc_net_646 ) , .p627 ( optlc_net_647 ) ,
+ .p628 ( optlc_net_648 ) , .p629 ( optlc_net_649 ) ,
+ .p630 ( optlc_net_650 ) , .p631 ( optlc_net_651 ) ,
+ .p632 ( optlc_net_652 ) , .p633 ( optlc_net_653 ) ,
+ .p634 ( optlc_net_654 ) , .p635 ( optlc_net_655 ) ,
+ .p636 ( optlc_net_656 ) , .p637 ( optlc_net_657 ) ,
+ .p638 ( optlc_net_658 ) , .p639 ( optlc_net_659 ) ,
+ .p640 ( optlc_net_660 ) , .p641 ( optlc_net_661 ) ,
+ .p642 ( optlc_net_662 ) , .p643 ( optlc_net_663 ) ,
+ .p644 ( optlc_net_664 ) , .p645 ( optlc_net_665 ) ,
+ .p646 ( optlc_net_666 ) , .p647 ( optlc_net_667 ) ,
+ .p648 ( optlc_net_668 ) , .p649 ( optlc_net_669 ) ,
+ .p650 ( optlc_net_670 ) , .p651 ( optlc_net_671 ) ,
+ .p652 ( optlc_net_672 ) , .p653 ( optlc_net_673 ) ,
+ .p654 ( optlc_net_674 ) , .p655 ( optlc_net_675 ) ,
+ .p656 ( optlc_net_676 ) , .p657 ( optlc_net_677 ) ,
+ .p658 ( optlc_net_678 ) , .p659 ( optlc_net_679 ) ,
+ .p660 ( optlc_net_680 ) , .p661 ( optlc_net_681 ) ,
+ .p662 ( optlc_net_682 ) , .p663 ( optlc_net_683 ) ,
+ .p664 ( optlc_net_684 ) , .p665 ( optlc_net_685 ) ,
+ .p666 ( optlc_net_686 ) , .p667 ( optlc_net_687 ) ,
+ .p668 ( optlc_net_688 ) , .p669 ( optlc_net_689 ) ,
+ .p670 ( optlc_net_690 ) , .p671 ( optlc_net_691 ) ,
+ .p672 ( optlc_net_692 ) , .p673 ( optlc_net_693 ) ,
+ .p674 ( optlc_net_694 ) , .p675 ( optlc_net_695 ) ,
+ .p676 ( optlc_net_696 ) , .p677 ( optlc_net_697 ) ,
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+ .p682 ( optlc_net_702 ) , .p683 ( optlc_net_703 ) ,
+ .p684 ( optlc_net_704 ) , .p685 ( optlc_net_705 ) ,
+ .p686 ( optlc_net_706 ) , .p687 ( optlc_net_707 ) ,
+ .p688 ( optlc_net_708 ) , .p689 ( optlc_net_709 ) ,
+ .p690 ( optlc_net_710 ) , .p691 ( optlc_net_711 ) ,
+ .p692 ( optlc_net_712 ) , .p693 ( optlc_net_713 ) ,
+ .p694 ( optlc_net_714 ) , .p695 ( optlc_net_715 ) ,
+ .p696 ( optlc_net_716 ) , .p697 ( optlc_net_717 ) ,
+ .p698 ( optlc_net_718 ) , .p699 ( optlc_net_719 ) ,
+ .p700 ( optlc_net_720 ) , .p701 ( optlc_net_721 ) ,
+ .p702 ( optlc_net_722 ) , .p703 ( optlc_net_723 ) ,
+ .p704 ( optlc_net_724 ) , .p705 ( optlc_net_725 ) ,
+ .p706 ( optlc_net_726 ) , .p707 ( optlc_net_727 ) ,
+ .p708 ( optlc_net_728 ) , .p709 ( optlc_net_729 ) ,
+ .p710 ( optlc_net_730 ) , .p711 ( optlc_net_731 ) ,
+ .p712 ( optlc_net_732 ) , .p713 ( optlc_net_733 ) ,
+ .p714 ( optlc_net_734 ) , .p715 ( optlc_net_735 ) ,
+ .p716 ( optlc_net_736 ) , .p717 ( optlc_net_737 ) ,
+ .p718 ( optlc_net_738 ) , .p719 ( optlc_net_739 ) ,
+ .p720 ( optlc_net_740 ) , .p721 ( optlc_net_741 ) ,
+ .p722 ( optlc_net_742 ) , .p723 ( optlc_net_743 ) ,
+ .p724 ( optlc_net_744 ) , .p725 ( optlc_net_745 ) ,
+ .p726 ( optlc_net_746 ) , .p727 ( optlc_net_747 ) ,
+ .p728 ( optlc_net_748 ) , .p729 ( optlc_net_749 ) ,
+ .p730 ( optlc_net_750 ) , .p731 ( optlc_net_751 ) ,
+ .p732 ( optlc_net_752 ) , .p733 ( optlc_net_753 ) ,
+ .p734 ( optlc_net_754 ) , .p735 ( optlc_net_755 ) ,
+ .p736 ( optlc_net_756 ) , .p737 ( optlc_net_757 ) ,
+ .p738 ( optlc_net_758 ) , .p739 ( optlc_net_759 ) ,
+ .p740 ( optlc_net_760 ) , .p741 ( optlc_net_761 ) ,
+ .p742 ( optlc_net_762 ) , .p743 ( optlc_net_763 ) ,
+ .p744 ( optlc_net_764 ) , .p745 ( optlc_net_765 ) ,
+ .p746 ( optlc_net_766 ) , .p747 ( optlc_net_767 ) ,
+ .p748 ( optlc_net_768 ) , .p749 ( optlc_net_769 ) ,
+ .p750 ( optlc_net_770 ) , .p751 ( optlc_net_771 ) ,
+ .p752 ( optlc_net_772 ) , .p753 ( optlc_net_773 ) ,
+ .p754 ( optlc_net_774 ) , .p755 ( optlc_net_775 ) ,
+ .p756 ( optlc_net_776 ) , .p757 ( optlc_net_777 ) ,
+ .p758 ( optlc_net_778 ) , .p759 ( optlc_net_779 ) ,
+ .p760 ( optlc_net_780 ) , .p761 ( optlc_net_781 ) ,
+ .p762 ( optlc_net_782 ) , .p763 ( optlc_net_783 ) ,
+ .p764 ( optlc_net_784 ) , .p765 ( optlc_net_785 ) ,
+ .p766 ( optlc_net_786 ) , .p767 ( optlc_net_787 ) ,
+ .p768 ( optlc_net_788 ) , .p769 ( optlc_net_789 ) ,
+ .p770 ( optlc_net_790 ) , .p771 ( optlc_net_791 ) ,
+ .p772 ( optlc_net_792 ) , .p773 ( optlc_net_793 ) ,
+ .p774 ( optlc_net_794 ) , .p775 ( optlc_net_795 ) ,
+ .p776 ( optlc_net_796 ) , .p777 ( optlc_net_797 ) ,
+ .p778 ( optlc_net_798 ) , .p779 ( optlc_net_799 ) ,
+ .p780 ( optlc_net_800 ) , .p781 ( optlc_net_801 ) ,
+ .p782 ( optlc_net_802 ) , .p783 ( optlc_net_803 ) ,
+ .p784 ( optlc_net_804 ) , .p785 ( optlc_net_805 ) ,
+ .p786 ( optlc_net_806 ) , .p787 ( optlc_net_807 ) ,
+ .p788 ( optlc_net_808 ) , .p789 ( optlc_net_809 ) ,
+ .p790 ( optlc_net_810 ) , .p791 ( optlc_net_811 ) ,
+ .p792 ( optlc_net_812 ) , .p793 ( optlc_net_813 ) ,
+ .p794 ( optlc_net_814 ) , .p795 ( optlc_net_815 ) ,
+ .p796 ( optlc_net_816 ) , .p797 ( optlc_net_817 ) ,
+ .p798 ( optlc_net_818 ) , .p799 ( optlc_net_819 ) ,
+ .p800 ( optlc_net_820 ) , .p801 ( optlc_net_821 ) ,
+ .p802 ( optlc_net_822 ) , .p803 ( optlc_net_823 ) ,
+ .p804 ( optlc_net_824 ) , .p805 ( optlc_net_825 ) ,
+ .p806 ( optlc_net_826 ) , .p807 ( optlc_net_827 ) ,
+ .p808 ( optlc_net_828 ) , .p809 ( optlc_net_829 ) ,
+ .p810 ( optlc_net_830 ) , .p811 ( optlc_net_831 ) ,
+ .p812 ( optlc_net_832 ) , .p813 ( optlc_net_833 ) ,
+ .p814 ( optlc_net_834 ) , .p815 ( optlc_net_835 ) ,
+ .p816 ( optlc_net_836 ) , .p817 ( optlc_net_837 ) ,
+ .p818 ( optlc_net_838 ) , .p819 ( optlc_net_839 ) ,
+ .p820 ( optlc_net_840 ) , .p821 ( optlc_net_841 ) ,
+ .p822 ( optlc_net_842 ) , .p823 ( optlc_net_843 ) ,
+ .p824 ( optlc_net_844 ) , .p825 ( optlc_net_845 ) ,
+ .p826 ( optlc_net_846 ) , .p827 ( optlc_net_847 ) ,
+ .p828 ( optlc_net_848 ) , .p829 ( optlc_net_849 ) ,
+ .p830 ( optlc_net_850 ) , .p831 ( optlc_net_851 ) ,
+ .p832 ( optlc_net_852 ) , .p833 ( optlc_net_853 ) ,
+ .p834 ( optlc_net_854 ) , .p835 ( optlc_net_855 ) ,
+ .p836 ( optlc_net_856 ) , .p837 ( optlc_net_857 ) ,
+ .p838 ( optlc_net_858 ) , .p839 ( optlc_net_859 ) ,
+ .p840 ( optlc_net_860 ) , .p841 ( optlc_net_861 ) ,
+ .p842 ( optlc_net_862 ) , .p843 ( optlc_net_863 ) ,
+ .p844 ( optlc_net_864 ) , .p845 ( optlc_net_865 ) ,
+ .p846 ( optlc_net_866 ) , .p847 ( optlc_net_867 ) ,
+ .p848 ( optlc_net_868 ) , .p849 ( optlc_net_869 ) ,
+ .p850 ( optlc_net_870 ) , .p851 ( optlc_net_871 ) ,
+ .p852 ( optlc_net_872 ) , .p853 ( optlc_net_873 ) ,
+ .p854 ( optlc_net_874 ) , .p855 ( optlc_net_875 ) ,
+ .p856 ( optlc_net_876 ) , .p857 ( optlc_net_877 ) ,
+ .p858 ( optlc_net_878 ) , .p859 ( optlc_net_879 ) ,
+ .p860 ( optlc_net_880 ) , .p861 ( optlc_net_881 ) ,
+ .p862 ( optlc_net_882 ) , .p863 ( optlc_net_883 ) ,
+ .p864 ( optlc_net_884 ) , .p865 ( optlc_net_885 ) ,
+ .p866 ( optlc_net_886 ) , .p867 ( optlc_net_887 ) ,
+ .p868 ( optlc_net_888 ) , .p869 ( optlc_net_889 ) ,
+ .p870 ( optlc_net_890 ) , .p871 ( optlc_net_891 ) ,
+ .p872 ( optlc_net_892 ) , .p873 ( optlc_net_893 ) ,
+ .p874 ( optlc_net_894 ) , .p875 ( optlc_net_895 ) ,
+ .p876 ( optlc_net_896 ) , .p877 ( optlc_net_897 ) ,
+ .p878 ( optlc_net_898 ) , .p879 ( optlc_net_899 ) ,
+ .p880 ( optlc_net_900 ) , .p881 ( optlc_net_901 ) ,
+ .p882 ( optlc_net_902 ) , .p883 ( optlc_net_903 ) ,
+ .p884 ( optlc_net_904 ) , .p885 ( optlc_net_905 ) ,
+ .p886 ( optlc_net_906 ) , .p887 ( optlc_net_907 ) ,
+ .p888 ( optlc_net_908 ) , .p889 ( optlc_net_909 ) ,
+ .p890 ( optlc_net_910 ) , .p891 ( optlc_net_911 ) ,
+ .p892 ( optlc_net_912 ) , .p893 ( optlc_net_913 ) ,
+ .p894 ( optlc_net_914 ) , .p895 ( optlc_net_915 ) ,
+ .p896 ( optlc_net_916 ) , .p897 ( optlc_net_917 ) ,
+ .p898 ( optlc_net_918 ) , .p899 ( optlc_net_919 ) ,
+ .p900 ( optlc_net_920 ) , .p901 ( optlc_net_921 ) ,
+ .p902 ( optlc_net_922 ) , .p903 ( optlc_net_923 ) ,
+ .p904 ( optlc_net_924 ) , .p905 ( optlc_net_925 ) ,
+ .p906 ( optlc_net_926 ) , .p907 ( optlc_net_927 ) ,
+ .p908 ( optlc_net_928 ) , .p909 ( optlc_net_929 ) ,
+ .p910 ( optlc_net_930 ) , .p911 ( optlc_net_931 ) ,
+ .p912 ( optlc_net_932 ) , .p913 ( optlc_net_933 ) ,
+ .p914 ( optlc_net_934 ) , .p915 ( optlc_net_935 ) ,
+ .p916 ( optlc_net_936 ) , .p917 ( optlc_net_937 ) ,
+ .p918 ( optlc_net_938 ) , .p919 ( optlc_net_939 ) ,
+ .p920 ( optlc_net_940 ) , .p921 ( optlc_net_941 ) ,
+ .p922 ( optlc_net_942 ) , .p923 ( optlc_net_943 ) ,
+ .p924 ( optlc_net_944 ) , .p925 ( optlc_net_945 ) ,
+ .p926 ( optlc_net_946 ) , .p927 ( optlc_net_947 ) ,
+ .p928 ( optlc_net_948 ) , .p929 ( optlc_net_949 ) ,
+ .p930 ( optlc_net_950 ) , .p931 ( optlc_net_951 ) ,
+ .p932 ( optlc_net_952 ) , .p933 ( optlc_net_953 ) ,
+ .p934 ( optlc_net_954 ) , .p935 ( optlc_net_955 ) ,
+ .p936 ( optlc_net_956 ) , .p937 ( optlc_net_957 ) ,
+ .p938 ( optlc_net_958 ) , .p939 ( optlc_net_959 ) ,
+ .p940 ( optlc_net_960 ) , .p941 ( optlc_net_961 ) ,
+ .p942 ( optlc_net_962 ) , .p943 ( optlc_net_963 ) ,
+ .p944 ( optlc_net_964 ) , .p945 ( optlc_net_965 ) ,
+ .p946 ( optlc_net_966 ) , .p947 ( optlc_net_967 ) ,
+ .p948 ( optlc_net_968 ) , .p949 ( optlc_net_969 ) ,
+ .p950 ( optlc_net_970 ) , .p951 ( optlc_net_971 ) ,
+ .p952 ( optlc_net_972 ) , .p953 ( optlc_net_973 ) ,
+ .p954 ( optlc_net_974 ) , .p955 ( optlc_net_975 ) ,
+ .p956 ( optlc_net_976 ) , .p957 ( optlc_net_977 ) ,
+ .p958 ( optlc_net_978 ) , .p959 ( optlc_net_979 ) ,
+ .p960 ( optlc_net_980 ) , .p961 ( optlc_net_981 ) ,
+ .p962 ( optlc_net_982 ) , .p963 ( optlc_net_983 ) ,
+ .p964 ( optlc_net_984 ) , .p965 ( optlc_net_985 ) ,
+ .p966 ( optlc_net_986 ) , .p967 ( optlc_net_987 ) ,
+ .p968 ( optlc_net_988 ) , .p969 ( optlc_net_989 ) ,
+ .p970 ( optlc_net_990 ) , .p971 ( optlc_net_991 ) ,
+ .p972 ( optlc_net_992 ) , .p973 ( optlc_net_993 ) ,
+ .p974 ( optlc_net_994 ) , .p975 ( optlc_net_995 ) ,
+ .p976 ( optlc_net_996 ) , .p977 ( optlc_net_997 ) ,
+ .p978 ( optlc_net_998 ) , .p979 ( optlc_net_999 ) ,
+ .p980 ( optlc_net_1000 ) , .p981 ( optlc_net_1001 ) ,
+ .p982 ( optlc_net_1002 ) , .p983 ( optlc_net_1003 ) ,
+ .p984 ( optlc_net_1004 ) , .p985 ( optlc_net_1005 ) ,
+ .p986 ( optlc_net_1006 ) , .p987 ( optlc_net_1007 ) ,
+ .p988 ( optlc_net_1008 ) , .p989 ( optlc_net_1009 ) ,
+ .p990 ( optlc_net_1010 ) , .p991 ( optlc_net_1011 ) ,
+ .p992 ( optlc_net_1012 ) , .p993 ( optlc_net_1013 ) ,
+ .p994 ( optlc_net_1014 ) , .p995 ( optlc_net_1015 ) ,
+ .p996 ( optlc_net_1016 ) , .p997 ( optlc_net_1017 ) ,
+ .p998 ( optlc_net_1018 ) , .p999 ( optlc_net_1019 ) ,
+ .p1000 ( optlc_net_1020 ) , .p1001 ( optlc_net_1021 ) ,
+ .p1002 ( optlc_net_1022 ) , .p1003 ( optlc_net_1023 ) ,
+ .p1004 ( optlc_net_1024 ) , .p1005 ( optlc_net_1025 ) ,
+ .p1006 ( optlc_net_1026 ) , .p1007 ( optlc_net_1027 ) ,
+ .p1008 ( optlc_net_1028 ) , .p1009 ( optlc_net_1029 ) ,
+ .p1010 ( optlc_net_1030 ) , .p1011 ( optlc_net_1031 ) ,
+ .p1012 ( optlc_net_1032 ) , .p1013 ( optlc_net_1033 ) ,
+ .p1014 ( optlc_net_1034 ) , .p1015 ( optlc_net_1035 ) ,
+ .p1016 ( optlc_net_1036 ) , .p1017 ( optlc_net_1037 ) ,
+ .p1018 ( optlc_net_1038 ) , .p1019 ( optlc_net_1039 ) ,
+ .p1020 ( optlc_net_1040 ) , .p1021 ( optlc_net_1041 ) ,
+ .p1022 ( optlc_net_1042 ) , .p1023 ( optlc_net_1043 ) ,
+ .p1024 ( optlc_net_1044 ) , .p1025 ( optlc_net_1045 ) ,
+ .p1026 ( optlc_net_1046 ) , .p1027 ( optlc_net_1047 ) ,
+ .p1028 ( optlc_net_1048 ) , .p1029 ( optlc_net_1049 ) ,
+ .p1030 ( optlc_net_1050 ) , .p1031 ( optlc_net_1051 ) ,
+ .p1032 ( optlc_net_1052 ) , .p1033 ( optlc_net_1053 ) ,
+ .p1034 ( optlc_net_1054 ) , .p1035 ( optlc_net_1055 ) ,
+ .p1036 ( optlc_net_1056 ) , .p1037 ( optlc_net_1057 ) ,
+ .p1038 ( optlc_net_1058 ) , .p1039 ( optlc_net_1059 ) ,
+ .p1040 ( optlc_net_1060 ) , .p1041 ( optlc_net_1061 ) ,
+ .p1042 ( optlc_net_1062 ) , .p1043 ( optlc_net_1063 ) ,
+ .p1044 ( optlc_net_1064 ) , .p1045 ( optlc_net_1065 ) ,
+ .p1046 ( optlc_net_1066 ) , .p1047 ( optlc_net_1067 ) ,
+ .p1048 ( optlc_net_1068 ) , .p1049 ( optlc_net_1069 ) ,
+ .p1050 ( optlc_net_1070 ) , .p1051 ( optlc_net_1071 ) ,
+ .p1052 ( optlc_net_1072 ) , .p1053 ( optlc_net_1073 ) ,
+ .p1054 ( optlc_net_1074 ) , .p1055 ( optlc_net_1075 ) ,
+ .p1056 ( optlc_net_1076 ) , .p1057 ( optlc_net_1077 ) ,
+ .p1058 ( optlc_net_1078 ) , .p1059 ( optlc_net_1079 ) ,
+ .p1060 ( optlc_net_1080 ) , .p1061 ( optlc_net_1081 ) ,
+ .p1062 ( optlc_net_1082 ) , .p1063 ( optlc_net_1083 ) ,
+ .p1064 ( optlc_net_1084 ) , .p1065 ( optlc_net_1085 ) ,
+ .p1066 ( optlc_net_1086 ) , .p1067 ( optlc_net_1087 ) ,
+ .p1068 ( optlc_net_1088 ) , .p1069 ( optlc_net_1089 ) ,
+ .p1070 ( optlc_net_1090 ) , .p1071 ( optlc_net_1091 ) ,
+ .p1072 ( optlc_net_1092 ) , .p1073 ( optlc_net_1093 ) ,
+ .p1074 ( optlc_net_1094 ) , .p1075 ( optlc_net_1095 ) ,
+ .p1076 ( optlc_net_1096 ) , .p1077 ( optlc_net_1097 ) ,
+ .p1078 ( optlc_net_1098 ) , .p1079 ( optlc_net_1099 ) ,
+ .p1080 ( optlc_net_1100 ) , .p1081 ( optlc_net_1101 ) ,
+ .p1082 ( optlc_net_1102 ) , .p1083 ( optlc_net_1103 ) ,
+ .p1084 ( optlc_net_1104 ) , .p1085 ( optlc_net_1105 ) ,
+ .p1086 ( optlc_net_1106 ) , .p1087 ( optlc_net_1107 ) ,
+ .p1088 ( optlc_net_1108 ) , .p1089 ( optlc_net_1109 ) ,
+ .p1090 ( optlc_net_1110 ) , .p1091 ( optlc_net_1111 ) ,
+ .p1092 ( optlc_net_1112 ) , .p1093 ( optlc_net_1113 ) ,
+ .p1094 ( optlc_net_1114 ) , .p1095 ( optlc_net_1115 ) ,
+ .p1096 ( optlc_net_1116 ) , .p1097 ( optlc_net_1117 ) ,
+ .p1098 ( optlc_net_1118 ) , .p1099 ( optlc_net_1119 ) ,
+ .p1100 ( optlc_net_1120 ) , .p1101 ( optlc_net_1121 ) ,
+ .p1102 ( optlc_net_1122 ) , .p1103 ( optlc_net_1123 ) ,
+ .p1104 ( optlc_net_1124 ) , .p1105 ( optlc_net_1125 ) ,
+ .p1106 ( optlc_net_1126 ) , .p1107 ( optlc_net_1127 ) ,
+ .p1108 ( optlc_net_1128 ) , .p1109 ( optlc_net_1129 ) ,
+ .p1110 ( optlc_net_1130 ) , .p1111 ( optlc_net_1131 ) ,
+ .p1112 ( optlc_net_1132 ) , .p1113 ( optlc_net_1133 ) ,
+ .p1114 ( optlc_net_1134 ) , .p1115 ( optlc_net_1135 ) ,
+ .p1116 ( optlc_net_1136 ) , .p1117 ( optlc_net_1137 ) ,
+ .p1118 ( optlc_net_1138 ) , .p1119 ( optlc_net_1139 ) ,
+ .p1120 ( optlc_net_1140 ) , .p1121 ( optlc_net_1141 ) ,
+ .p1122 ( optlc_net_1142 ) , .p1123 ( optlc_net_1143 ) ,
+ .p1124 ( optlc_net_1144 ) , .p1125 ( optlc_net_1145 ) ,
+ .p1126 ( optlc_net_1146 ) , .p1127 ( optlc_net_1147 ) ,
+ .p1128 ( optlc_net_1148 ) , .p1129 ( optlc_net_1149 ) ,
+ .p1130 ( optlc_net_1150 ) , .p1131 ( optlc_net_1151 ) ,
+ .p1132 ( optlc_net_1152 ) , .p1133 ( optlc_net_1153 ) ,
+ .p1134 ( optlc_net_1154 ) , .p1135 ( optlc_net_1155 ) ,
+ .p1136 ( optlc_net_1156 ) , .p1137 ( optlc_net_1157 ) ,
+ .p1138 ( optlc_net_1158 ) , .p1139 ( optlc_net_1159 ) ,
+ .p1140 ( optlc_net_1160 ) , .p1141 ( optlc_net_1161 ) ,
+ .p1142 ( optlc_net_1162 ) , .p1143 ( optlc_net_1163 ) ,
+ .p1144 ( optlc_net_1164 ) , .p1145 ( optlc_net_1165 ) ,
+ .p1146 ( optlc_net_1166 ) , .p1147 ( optlc_net_1167 ) ,
+ .p1148 ( optlc_net_1168 ) , .p1149 ( optlc_net_1169 ) ,
+ .p1150 ( optlc_net_1170 ) , .p1151 ( optlc_net_1171 ) ,
+ .p1152 ( optlc_net_1172 ) , .p1153 ( optlc_net_1173 ) ,
+ .p1154 ( optlc_net_1174 ) , .p1155 ( optlc_net_1175 ) ,
+ .p1156 ( optlc_net_1176 ) , .p1157 ( optlc_net_1177 ) ,
+ .p1158 ( optlc_net_1178 ) , .p1159 ( optlc_net_1179 ) ,
+ .p1160 ( optlc_net_1180 ) , .p1161 ( optlc_net_1181 ) ,
+ .p1162 ( optlc_net_1182 ) , .p1163 ( optlc_net_1183 ) ,
+ .p1164 ( optlc_net_1184 ) , .p1165 ( optlc_net_1185 ) ,
+ .p1166 ( optlc_net_1186 ) , .p1167 ( optlc_net_1187 ) ,
+ .p1168 ( optlc_net_1188 ) , .p1169 ( optlc_net_1189 ) ,
+ .p1170 ( optlc_net_1190 ) , .p1171 ( optlc_net_1191 ) ,
+ .p1172 ( optlc_net_1192 ) , .p1173 ( optlc_net_1193 ) ,
+ .p1174 ( optlc_net_1194 ) , .p1175 ( optlc_net_1195 ) ,
+ .p1176 ( optlc_net_1196 ) , .p1177 ( optlc_net_1197 ) ,
+ .p1178 ( optlc_net_1198 ) , .p1179 ( optlc_net_1199 ) ,
+ .p1180 ( optlc_net_1200 ) , .p1181 ( optlc_net_1201 ) ,
+ .p1182 ( optlc_net_1202 ) , .p1183 ( optlc_net_1203 ) ,
+ .p1184 ( optlc_net_1204 ) , .p1185 ( optlc_net_1205 ) ,
+ .p1186 ( optlc_net_1206 ) , .p1187 ( optlc_net_1207 ) ,
+ .p1188 ( optlc_net_1208 ) , .p1189 ( optlc_net_1209 ) ,
+ .p1190 ( optlc_net_1210 ) , .p1191 ( optlc_net_1211 ) ,
+ .p1192 ( optlc_net_1212 ) , .p1193 ( optlc_net_1213 ) ,
+ .p1194 ( optlc_net_1214 ) , .p1195 ( optlc_net_1215 ) ,
+ .p1196 ( optlc_net_1216 ) , .p1197 ( optlc_net_1217 ) ,
+ .p1198 ( optlc_net_1218 ) , .p1199 ( optlc_net_1219 ) ,
+ .p1200 ( optlc_net_1220 ) , .p1201 ( optlc_net_1221 ) ,
+ .p1202 ( optlc_net_1222 ) , .p1203 ( optlc_net_1223 ) ,
+ .p1204 ( optlc_net_1224 ) , .p1205 ( optlc_net_1225 ) ,
+ .p1206 ( optlc_net_1226 ) , .p1207 ( optlc_net_1227 ) ,
+ .p1208 ( optlc_net_1228 ) , .p1209 ( optlc_net_1229 ) ,
+ .p1210 ( optlc_net_1230 ) , .p1211 ( optlc_net_1231 ) ,
+ .p1212 ( optlc_net_1232 ) , .p1213 ( optlc_net_1233 ) ,
+ .p1214 ( optlc_net_1234 ) , .p1215 ( optlc_net_1235 ) ,
+ .p1216 ( optlc_net_1236 ) , .p1217 ( optlc_net_1237 ) ,
+ .p1218 ( optlc_net_1238 ) , .p1219 ( optlc_net_1239 ) ,
+ .p1220 ( optlc_net_1240 ) , .p1221 ( optlc_net_1241 ) ,
+ .p1222 ( optlc_net_1242 ) , .p1223 ( optlc_net_1243 ) ,
+ .p1224 ( optlc_net_1244 ) , .p1225 ( optlc_net_1245 ) ,
+ .p1226 ( optlc_net_1246 ) , .p1227 ( optlc_net_1247 ) ,
+ .p1228 ( optlc_net_1248 ) , .p1229 ( optlc_net_1249 ) ,
+ .p1230 ( optlc_net_1250 ) , .p1231 ( optlc_net_1251 ) ,
+ .p1232 ( optlc_net_1252 ) , .p1233 ( optlc_net_1253 ) ,
+ .p1234 ( optlc_net_1254 ) , .p1235 ( optlc_net_1255 ) ,
+ .p1236 ( optlc_net_1256 ) , .p1237 ( optlc_net_1257 ) ,
+ .p1238 ( optlc_net_1258 ) , .p1239 ( optlc_net_1259 ) ,
+ .p1240 ( optlc_net_1260 ) , .p1241 ( optlc_net_1261 ) ,
+ .p1242 ( optlc_net_1262 ) , .p1243 ( optlc_net_1263 ) ,
+ .p1244 ( optlc_net_1264 ) , .p1245 ( optlc_net_1265 ) ,
+ .p1246 ( optlc_net_1266 ) , .p1247 ( optlc_net_1267 ) ,
+ .p1248 ( optlc_net_1268 ) , .p1249 ( optlc_net_1269 ) ,
+ .p1250 ( optlc_net_1270 ) , .p1251 ( optlc_net_1271 ) ,
+ .p1252 ( optlc_net_1272 ) , .p1253 ( optlc_net_1273 ) ,
+ .p1254 ( optlc_net_1274 ) , .p1255 ( optlc_net_1275 ) ,
+ .p1256 ( optlc_net_1276 ) , .p1257 ( optlc_net_1277 ) ,
+ .p1258 ( optlc_net_1278 ) , .p1259 ( optlc_net_1279 ) ,
+ .p1260 ( optlc_net_1280 ) , .p1261 ( optlc_net_1281 ) ,
+ .p1262 ( optlc_net_1282 ) , .p1263 ( optlc_net_1283 ) ,
+ .p1264 ( optlc_net_1284 ) , .p1265 ( optlc_net_1285 ) ,
+ .p1266 ( optlc_net_1286 ) , .p1267 ( optlc_net_1287 ) ,
+ .p1268 ( optlc_net_1288 ) , .p1269 ( optlc_net_1289 ) ,
+ .p1270 ( optlc_net_1290 ) , .p1271 ( optlc_net_1291 ) ,
+ .p1272 ( optlc_net_1292 ) , .p1273 ( optlc_net_1293 ) ,
+ .p1274 ( optlc_net_1294 ) , .p1275 ( optlc_net_1295 ) ,
+ .p1276 ( optlc_net_1296 ) , .p1277 ( optlc_net_1297 ) ,
+ .p1278 ( optlc_net_1298 ) , .p1279 ( optlc_net_1299 ) ,
+ .p1280 ( optlc_net_1300 ) , .p1281 ( optlc_net_1301 ) ,
+ .p1282 ( optlc_net_1302 ) , .p1283 ( optlc_net_1303 ) ,
+ .p1284 ( optlc_net_1304 ) , .p1285 ( optlc_net_1305 ) ,
+ .p1286 ( optlc_net_1306 ) , .p1287 ( optlc_net_1307 ) ,
+ .p1288 ( optlc_net_1308 ) , .p1289 ( optlc_net_1309 ) ,
+ .p1290 ( optlc_net_1310 ) , .p1291 ( optlc_net_1311 ) ,
+ .p1292 ( optlc_net_1312 ) , .p1293 ( optlc_net_1313 ) ,
+ .p1294 ( optlc_net_1314 ) , .p1295 ( optlc_net_1315 ) ,
+ .p1296 ( optlc_net_1316 ) , .p1297 ( optlc_net_1317 ) ,
+ .p1298 ( optlc_net_1318 ) , .p1299 ( optlc_net_1319 ) ,
+ .p1300 ( optlc_net_1320 ) , .p1301 ( optlc_net_1321 ) ,
+ .p1302 ( optlc_net_1322 ) , .p1303 ( optlc_net_1323 ) ,
+ .p1304 ( optlc_net_1324 ) , .p1305 ( optlc_net_1325 ) ,
+ .p1306 ( optlc_net_1326 ) , .p1307 ( optlc_net_1327 ) ,
+ .p1308 ( optlc_net_1328 ) , .p1309 ( optlc_net_1329 ) ,
+ .p1310 ( optlc_net_1330 ) , .p1311 ( optlc_net_1331 ) ,
+ .p1312 ( optlc_net_1332 ) , .p1313 ( optlc_net_1333 ) ,
+ .p1314 ( optlc_net_1334 ) , .p1315 ( optlc_net_1335 ) ,
+ .p1316 ( optlc_net_1336 ) , .p1317 ( optlc_net_1337 ) ,
+ .p1318 ( optlc_net_1338 ) , .p1319 ( optlc_net_1339 ) ,
+ .p1320 ( optlc_net_1340 ) , .p1321 ( optlc_net_1341 ) ,
+ .p1322 ( optlc_net_1342 ) , .p1323 ( optlc_net_1343 ) ,
+ .p1324 ( optlc_net_1344 ) , .p1325 ( optlc_net_1345 ) ,
+ .p1326 ( optlc_net_1346 ) , .p1327 ( optlc_net_1347 ) ,
+ .p1328 ( optlc_net_1348 ) , .p1329 ( optlc_net_1349 ) ,
+ .p1330 ( optlc_net_1350 ) , .p1331 ( optlc_net_1351 ) ,
+ .p1332 ( optlc_net_1352 ) , .p1333 ( optlc_net_1353 ) ,
+ .p1334 ( optlc_net_1354 ) , .p1335 ( optlc_net_1355 ) ,
+ .p1336 ( optlc_net_1356 ) , .p1337 ( optlc_net_1357 ) ,
+ .p1338 ( optlc_net_1358 ) , .p1339 ( optlc_net_1359 ) ,
+ .p1340 ( optlc_net_1360 ) , .p1341 ( optlc_net_1361 ) ,
+ .p1342 ( optlc_net_1362 ) , .p1343 ( optlc_net_1363 ) ,
+ .p1344 ( optlc_net_1364 ) , .p1345 ( optlc_net_1365 ) ,
+ .p1346 ( optlc_net_1366 ) , .p1347 ( optlc_net_1367 ) ,
+ .p1348 ( optlc_net_1368 ) , .p1349 ( optlc_net_1369 ) ,
+ .p1350 ( optlc_net_1370 ) , .p1351 ( optlc_net_1371 ) ,
+ .p1352 ( optlc_net_1372 ) , .p1353 ( optlc_net_1373 ) ,
+ .p1354 ( optlc_net_1374 ) , .p1355 ( optlc_net_1375 ) ,
+ .p1356 ( optlc_net_1376 ) , .p1357 ( optlc_net_1377 ) ,
+ .p1358 ( optlc_net_1378 ) , .p1359 ( optlc_net_1379 ) ,
+ .p1360 ( optlc_net_1380 ) , .p1361 ( optlc_net_1381 ) ,
+ .p1362 ( optlc_net_1382 ) , .p1363 ( optlc_net_1383 ) ,
+ .p1364 ( optlc_net_1384 ) , .p1365 ( optlc_net_1385 ) ,
+ .p1366 ( optlc_net_1386 ) , .p1367 ( optlc_net_1387 ) ,
+ .p1368 ( optlc_net_1388 ) , .p1369 ( optlc_net_1389 ) ,
+ .p1370 ( optlc_net_1390 ) , .p1371 ( optlc_net_1391 ) ,
+ .p1372 ( optlc_net_1392 ) , .p1373 ( optlc_net_1393 ) ,
+ .p1374 ( optlc_net_1394 ) , .p1375 ( optlc_net_1395 ) ,
+ .p1376 ( optlc_net_1396 ) , .p1377 ( optlc_net_1397 ) ,
+ .p1378 ( optlc_net_1398 ) , .p1379 ( optlc_net_1399 ) ,
+ .p1380 ( optlc_net_1400 ) , .p1381 ( optlc_net_1401 ) ,
+ .p1382 ( optlc_net_1402 ) , .p1383 ( optlc_net_1403 ) ,
+ .p1384 ( optlc_net_1404 ) , .p1385 ( optlc_net_1405 ) ,
+ .p1386 ( optlc_net_1406 ) , .p1387 ( optlc_net_1407 ) ,
+ .p1388 ( optlc_net_1408 ) , .p1389 ( optlc_net_1409 ) ,
+ .p1390 ( optlc_net_1410 ) , .p1391 ( optlc_net_1411 ) ,
+ .p1392 ( optlc_net_1412 ) , .p1393 ( optlc_net_1413 ) ,
+ .p1394 ( optlc_net_1414 ) , .p1395 ( optlc_net_1415 ) ,
+ .p1396 ( optlc_net_1416 ) , .p1397 ( optlc_net_1417 ) ,
+ .p1398 ( optlc_net_1418 ) , .p1399 ( optlc_net_1419 ) ,
+ .p1400 ( optlc_net_1420 ) , .p1401 ( optlc_net_1421 ) ,
+ .p1402 ( optlc_net_1422 ) , .p1403 ( optlc_net_1423 ) ,
+ .p1404 ( optlc_net_1424 ) , .p1405 ( optlc_net_1425 ) ,
+ .p1406 ( optlc_net_1426 ) , .p1407 ( optlc_net_1427 ) ,
+ .p1408 ( optlc_net_1428 ) , .p1409 ( optlc_net_1429 ) ,
+ .p1410 ( optlc_net_1430 ) , .p1411 ( optlc_net_1431 ) ,
+ .p1412 ( optlc_net_1432 ) , .p1413 ( optlc_net_1433 ) ,
+ .p1414 ( optlc_net_1434 ) , .p1415 ( optlc_net_1435 ) ,
+ .p1416 ( optlc_net_1436 ) , .p1417 ( optlc_net_1437 ) ,
+ .p1418 ( optlc_net_1438 ) , .p1419 ( optlc_net_1439 ) ,
+ .p1420 ( optlc_net_1440 ) , .p1421 ( optlc_net_1441 ) ,
+ .p1422 ( optlc_net_1442 ) , .p1423 ( optlc_net_1443 ) ,
+ .p1424 ( optlc_net_1444 ) , .p1425 ( optlc_net_1445 ) ,
+ .p1426 ( optlc_net_1446 ) , .p1427 ( optlc_net_1447 ) ,
+ .p1428 ( optlc_net_1448 ) , .p1429 ( optlc_net_1449 ) ,
+ .p1430 ( optlc_net_1450 ) , .p1431 ( optlc_net_1451 ) ,
+ .p1432 ( optlc_net_1452 ) , .p1433 ( optlc_net_1453 ) ,
+ .p1434 ( optlc_net_1454 ) , .p1435 ( optlc_net_1455 ) ,
+ .p1436 ( optlc_net_1456 ) , .p1437 ( optlc_net_1457 ) ,
+ .p1438 ( optlc_net_1458 ) , .p1439 ( optlc_net_1459 ) ,
+ .p1440 ( optlc_net_1460 ) , .p1441 ( optlc_net_1461 ) ,
+ .p1442 ( optlc_net_1462 ) , .p1443 ( optlc_net_1463 ) ,
+ .p1444 ( optlc_net_1464 ) , .p1445 ( optlc_net_1465 ) ,
+ .p1446 ( optlc_net_1466 ) , .p1447 ( optlc_net_1467 ) ,
+ .p1448 ( optlc_net_1468 ) , .p1449 ( optlc_net_1469 ) ,
+ .p1450 ( optlc_net_1470 ) , .p1451 ( optlc_net_1471 ) ,
+ .p1452 ( optlc_net_1472 ) , .p1453 ( optlc_net_1473 ) ,
+ .p1454 ( optlc_net_1474 ) , .p1455 ( optlc_net_1475 ) ,
+ .p1456 ( optlc_net_1476 ) , .p1457 ( optlc_net_1477 ) ,
+ .p1458 ( optlc_net_1478 ) , .p1459 ( optlc_net_1479 ) ,
+ .p1460 ( optlc_net_1480 ) , .p1461 ( optlc_net_1481 ) ,
+ .p1462 ( optlc_net_1482 ) , .p1463 ( optlc_net_1483 ) ,
+ .p1464 ( optlc_net_1484 ) , .p1465 ( optlc_net_1485 ) ,
+ .p1466 ( optlc_net_1486 ) , .p1467 ( optlc_net_1487 ) ,
+ .p1468 ( optlc_net_1488 ) , .p1469 ( optlc_net_1489 ) ,
+ .p1470 ( optlc_net_1490 ) , .p1471 ( optlc_net_1491 ) ,
+ .p1472 ( optlc_net_1492 ) , .p1473 ( optlc_net_1493 ) ,
+ .p1474 ( optlc_net_1494 ) , .p1475 ( optlc_net_1495 ) ,
+ .p1476 ( optlc_net_1496 ) , .p1477 ( optlc_net_1497 ) ,
+ .p1478 ( optlc_net_1498 ) , .p1479 ( optlc_net_1499 ) ,
+ .p1480 ( optlc_net_1500 ) , .p1481 ( optlc_net_1501 ) ,
+ .p1482 ( optlc_net_1502 ) , .p1483 ( optlc_net_1503 ) ,
+ .p1484 ( optlc_net_1504 ) , .p1485 ( optlc_net_1505 ) ,
+ .p1486 ( optlc_net_1506 ) , .p1487 ( optlc_net_1507 ) ,
+ .p1488 ( optlc_net_1508 ) , .p1489 ( optlc_net_1509 ) ,
+ .p1490 ( optlc_net_1510 ) , .p1491 ( optlc_net_1511 ) ,
+ .p1492 ( optlc_net_1512 ) , .p1493 ( optlc_net_1513 ) ,
+ .p1494 ( optlc_net_1514 ) , .p1495 ( optlc_net_1515 ) ,
+ .p1496 ( optlc_net_1516 ) , .p1497 ( optlc_net_1517 ) ,
+ .p1498 ( optlc_net_1518 ) , .p1499 ( optlc_net_1519 ) ,
+ .p1500 ( optlc_net_1520 ) , .p1501 ( optlc_net_1521 ) ,
+ .p1502 ( optlc_net_1522 ) , .p1503 ( optlc_net_1523 ) ,
+ .p1504 ( optlc_net_1524 ) , .p1505 ( optlc_net_1525 ) ,
+ .p1506 ( optlc_net_1526 ) , .p1507 ( optlc_net_1527 ) ,
+ .p1508 ( optlc_net_1528 ) , .p1509 ( optlc_net_1529 ) ,
+ .p1510 ( optlc_net_1530 ) , .p1511 ( optlc_net_1531 ) ,
+ .p1512 ( optlc_net_1532 ) , .p1513 ( optlc_net_1533 ) ,
+ .p1514 ( optlc_net_1534 ) , .p1515 ( optlc_net_1535 ) ,
+ .p1516 ( optlc_net_1536 ) , .p1517 ( optlc_net_1537 ) ,
+ .p1518 ( optlc_net_1538 ) , .p1519 ( optlc_net_1539 ) ,
+ .p1520 ( optlc_net_1540 ) , .p1521 ( optlc_net_1541 ) ,
+ .p1522 ( optlc_net_1542 ) , .p1523 ( optlc_net_1543 ) ,
+ .p1524 ( optlc_net_1544 ) , .p1525 ( optlc_net_1545 ) ,
+ .p1526 ( optlc_net_1546 ) , .p1527 ( optlc_net_1547 ) ,
+ .p1528 ( optlc_net_1548 ) , .p1529 ( optlc_net_1549 ) ,
+ .p1530 ( optlc_net_1550 ) , .p1531 ( optlc_net_1551 ) ,
+ .p1532 ( optlc_net_1552 ) , .p1533 ( optlc_net_1553 ) ,
+ .p1534 ( optlc_net_1554 ) , .p1535 ( optlc_net_1555 ) ,
+ .p1536 ( optlc_net_1556 ) , .p1537 ( optlc_net_1557 ) ,
+ .p1538 ( optlc_net_1558 ) , .p1539 ( optlc_net_1559 ) ,
+ .p1540 ( optlc_net_1560 ) , .p1541 ( optlc_net_1561 ) ,
+ .p1542 ( optlc_net_1562 ) , .p1543 ( optlc_net_1563 ) ,
+ .p1544 ( optlc_net_1564 ) , .p1545 ( optlc_net_1565 ) ,
+ .p1546 ( optlc_net_1566 ) , .p1547 ( optlc_net_1567 ) ,
+ .p1548 ( optlc_net_1568 ) , .p1549 ( optlc_net_1569 ) ,
+ .p1550 ( optlc_net_1570 ) , .p1551 ( optlc_net_1571 ) ,
+ .p1552 ( optlc_net_1572 ) , .p1553 ( optlc_net_1573 ) ,
+ .p1554 ( optlc_net_1574 ) , .p1555 ( optlc_net_1575 ) ,
+ .p1556 ( optlc_net_1576 ) , .p1557 ( optlc_net_1577 ) ,
+ .p1558 ( optlc_net_1578 ) , .p1559 ( optlc_net_1579 ) ,
+ .p1560 ( optlc_net_1580 ) , .p1561 ( optlc_net_1581 ) ,
+ .p1562 ( optlc_net_1582 ) , .p1563 ( optlc_net_1583 ) ,
+ .p1564 ( optlc_net_1584 ) , .p1565 ( optlc_net_1585 ) ,
+ .p1566 ( optlc_net_1586 ) , .p1567 ( optlc_net_1587 ) ,
+ .p1568 ( optlc_net_1588 ) , .p1569 ( optlc_net_1589 ) ,
+ .p1570 ( optlc_net_1590 ) , .p1571 ( optlc_net_1591 ) ,
+ .p1572 ( optlc_net_1592 ) , .p1573 ( optlc_net_1593 ) ,
+ .p1574 ( optlc_net_1594 ) , .p1575 ( optlc_net_1595 ) ,
+ .p1576 ( optlc_net_1596 ) , .p1577 ( optlc_net_1597 ) ,
+ .p1578 ( optlc_net_1598 ) , .p1579 ( optlc_net_1599 ) ,
+ .p1580 ( optlc_net_1600 ) , .p1581 ( optlc_net_1601 ) ,
+ .p1582 ( optlc_net_1602 ) , .p1583 ( optlc_net_1603 ) ,
+ .p1584 ( optlc_net_1604 ) , .p1585 ( optlc_net_1605 ) ,
+ .p1586 ( optlc_net_1606 ) , .p1587 ( optlc_net_1607 ) ,
+ .p1588 ( optlc_net_1608 ) , .p1589 ( optlc_net_1609 ) ,
+ .p1590 ( optlc_net_1610 ) , .p1591 ( optlc_net_1611 ) ,
+ .p1592 ( optlc_net_1612 ) , .p1593 ( optlc_net_1613 ) ,
+ .p1594 ( optlc_net_1614 ) , .p1595 ( optlc_net_1615 ) ,
+ .p1596 ( optlc_net_1616 ) , .p1597 ( optlc_net_1617 ) ,
+ .p1598 ( optlc_net_1618 ) , .p1599 ( optlc_net_1619 ) ,
+ .p1600 ( optlc_net_1620 ) , .p1601 ( optlc_net_1621 ) ,
+ .p1602 ( optlc_net_1622 ) , .p1603 ( optlc_net_1623 ) ,
+ .p1604 ( optlc_net_1624 ) , .p1605 ( optlc_net_1625 ) ,
+ .p1606 ( optlc_net_1626 ) , .p1607 ( optlc_net_1627 ) ,
+ .p1608 ( optlc_net_1628 ) , .p1609 ( optlc_net_1629 ) ,
+ .p1610 ( optlc_net_1630 ) , .p1611 ( optlc_net_1631 ) ,
+ .p1612 ( optlc_net_1632 ) , .p1613 ( optlc_net_1633 ) ,
+ .p1614 ( optlc_net_1634 ) , .p1615 ( optlc_net_1635 ) ,
+ .p1616 ( optlc_net_1636 ) , .p1617 ( optlc_net_1637 ) ,
+ .p1618 ( optlc_net_1638 ) , .p1619 ( optlc_net_1639 ) ,
+ .p1620 ( optlc_net_1640 ) , .p1621 ( optlc_net_1641 ) ,
+ .p1622 ( optlc_net_1642 ) , .p1623 ( optlc_net_1643 ) ,
+ .p1624 ( optlc_net_1644 ) , .p1625 ( optlc_net_1645 ) ,
+ .p1626 ( optlc_net_1646 ) , .p1627 ( optlc_net_1647 ) ,
+ .p1628 ( optlc_net_1648 ) , .p1629 ( optlc_net_1649 ) ,
+ .p1630 ( optlc_net_1650 ) , .p1631 ( optlc_net_1651 ) ,
+ .p1632 ( optlc_net_1652 ) , .p1633 ( optlc_net_1653 ) ,
+ .p1634 ( optlc_net_1654 ) , .p1635 ( optlc_net_1655 ) ,
+ .p1636 ( optlc_net_1656 ) , .p1637 ( optlc_net_1657 ) ,
+ .p1638 ( optlc_net_1658 ) , .p1639 ( optlc_net_1659 ) ,
+ .p1640 ( optlc_net_1660 ) , .p1641 ( optlc_net_1661 ) ,
+ .p1642 ( optlc_net_1662 ) , .p1643 ( optlc_net_1663 ) ,
+ .p1644 ( optlc_net_1664 ) , .p1645 ( optlc_net_1665 ) ,
+ .p1646 ( optlc_net_1666 ) , .p1647 ( optlc_net_1667 ) ,
+ .p1648 ( optlc_net_1668 ) , .p1649 ( optlc_net_1669 ) ,
+ .p1650 ( optlc_net_1670 ) , .p1651 ( optlc_net_1671 ) ,
+ .p1652 ( optlc_net_1672 ) , .p1653 ( optlc_net_1673 ) ,
+ .p1654 ( optlc_net_1674 ) , .p1655 ( optlc_net_1675 ) ,
+ .p1656 ( optlc_net_1676 ) , .p1657 ( optlc_net_1677 ) ,
+ .p1658 ( optlc_net_1678 ) , .p1659 ( optlc_net_1679 ) ,
+ .p1660 ( optlc_net_1680 ) , .p1661 ( optlc_net_1681 ) ,
+ .p1662 ( optlc_net_1682 ) , .p1663 ( optlc_net_1683 ) ,
+ .p1664 ( optlc_net_1684 ) , .p1665 ( optlc_net_1685 ) ,
+ .p1666 ( optlc_net_1686 ) , .p1667 ( optlc_net_1687 ) ,
+ .p1668 ( optlc_net_1688 ) , .p1669 ( optlc_net_1689 ) ,
+ .p1670 ( optlc_net_1690 ) , .p1671 ( optlc_net_1691 ) ,
+ .p1672 ( optlc_net_1692 ) , .p1673 ( optlc_net_1693 ) ,
+ .p1674 ( optlc_net_1694 ) , .p1675 ( optlc_net_1695 ) ,
+ .p1676 ( optlc_net_1696 ) , .p1677 ( optlc_net_1697 ) ,
+ .p1678 ( optlc_net_1698 ) , .p1679 ( optlc_net_1699 ) ,
+ .p1680 ( optlc_net_1700 ) , .p1681 ( optlc_net_1701 ) ,
+ .p1682 ( optlc_net_1702 ) , .p1683 ( optlc_net_1703 ) ,
+ .p1684 ( optlc_net_1704 ) , .p1685 ( optlc_net_1705 ) ,
+ .p1686 ( optlc_net_1706 ) , .p1687 ( optlc_net_1707 ) ,
+ .p1688 ( optlc_net_1708 ) , .p1689 ( optlc_net_1709 ) ,
+ .p1690 ( optlc_net_1710 ) , .p1691 ( optlc_net_1711 ) ,
+ .p1692 ( optlc_net_1712 ) , .p1693 ( optlc_net_1713 ) ,
+ .p1694 ( optlc_net_1714 ) , .p1695 ( optlc_net_1715 ) ,
+ .p1696 ( optlc_net_1716 ) , .p1697 ( optlc_net_1717 ) ,
+ .p1698 ( optlc_net_1718 ) , .p1699 ( optlc_net_1719 ) ,
+ .p1700 ( optlc_net_1720 ) , .p1701 ( optlc_net_1721 ) ,
+ .p1702 ( optlc_net_1722 ) , .p1703 ( optlc_net_1723 ) ,
+ .p1704 ( optlc_net_1724 ) , .p1705 ( optlc_net_1725 ) ,
+ .p1706 ( optlc_net_1726 ) , .p1707 ( optlc_net_1727 ) ,
+ .p1708 ( optlc_net_1728 ) , .p1709 ( optlc_net_1729 ) ,
+ .p1710 ( optlc_net_1730 ) , .p1711 ( optlc_net_1731 ) ,
+ .p1712 ( optlc_net_1732 ) , .p1713 ( optlc_net_1733 ) ,
+ .p1714 ( optlc_net_1734 ) , .p1715 ( optlc_net_1735 ) ,
+ .p1716 ( optlc_net_1736 ) , .p1717 ( optlc_net_1737 ) ,
+ .p1718 ( optlc_net_1738 ) , .p1719 ( optlc_net_1739 ) ,
+ .p1720 ( optlc_net_1740 ) , .p1721 ( optlc_net_1741 ) ,
+ .p1722 ( optlc_net_1742 ) , .p1723 ( optlc_net_1743 ) ,
+ .p1724 ( optlc_net_1744 ) , .p1725 ( optlc_net_1745 ) ,
+ .p1726 ( optlc_net_1746 ) , .p1727 ( optlc_net_1747 ) ,
+ .p1728 ( optlc_net_1748 ) , .p1729 ( optlc_net_1749 ) ,
+ .p1730 ( optlc_net_1750 ) , .p1731 ( optlc_net_1751 ) ,
+ .p1732 ( optlc_net_1752 ) , .p1733 ( optlc_net_1753 ) ,
+ .p1734 ( optlc_net_1754 ) , .p1735 ( optlc_net_1755 ) ,
+ .p1736 ( optlc_net_1756 ) , .p1737 ( optlc_net_1757 ) ,
+ .p1738 ( optlc_net_1758 ) , .p1739 ( optlc_net_1759 ) ,
+ .p1740 ( optlc_net_1760 ) , .p1741 ( optlc_net_1761 ) ,
+ .p1742 ( optlc_net_1762 ) , .p1743 ( optlc_net_1763 ) ,
+ .p1744 ( optlc_net_1764 ) , .p1745 ( optlc_net_1765 ) ,
+ .p1746 ( optlc_net_1766 ) , .p1747 ( optlc_net_1767 ) ,
+ .p1748 ( optlc_net_1768 ) , .p1749 ( optlc_net_1769 ) ,
+ .p1750 ( optlc_net_1770 ) , .p1751 ( optlc_net_1771 ) ,
+ .p1752 ( optlc_net_1772 ) , .p1753 ( optlc_net_1773 ) ,
+ .p1754 ( optlc_net_1774 ) , .p1755 ( optlc_net_1775 ) ,
+ .p1756 ( optlc_net_1776 ) , .p1757 ( optlc_net_1777 ) ,
+ .p1758 ( optlc_net_1778 ) , .p1759 ( optlc_net_1779 ) ,
+ .p1760 ( optlc_net_1780 ) , .p1761 ( optlc_net_1781 ) ,
+ .p1762 ( optlc_net_1782 ) , .p1763 ( optlc_net_1783 ) ,
+ .p1764 ( optlc_net_1784 ) , .p1765 ( optlc_net_1785 ) ,
+ .p1766 ( optlc_net_1786 ) , .p1767 ( optlc_net_1787 ) ,
+ .p1768 ( optlc_net_1788 ) , .p1769 ( optlc_net_1789 ) ,
+ .p1770 ( optlc_net_1790 ) , .p1771 ( optlc_net_1791 ) ,
+ .p1772 ( optlc_net_1792 ) , .p1773 ( optlc_net_1793 ) ,
+ .p1774 ( optlc_net_1794 ) , .p1775 ( optlc_net_1795 ) ,
+ .p1776 ( optlc_net_1796 ) , .p1777 ( optlc_net_1797 ) ,
+ .p1778 ( optlc_net_1798 ) , .p1779 ( optlc_net_1799 ) ,
+ .p1780 ( optlc_net_1800 ) , .p1781 ( optlc_net_1801 ) ,
+ .p1782 ( optlc_net_1802 ) , .p1783 ( optlc_net_1803 ) ,
+ .p1784 ( optlc_net_1804 ) , .p1785 ( optlc_net_1805 ) ,
+ .p1786 ( optlc_net_1806 ) , .p1787 ( optlc_net_1807 ) ,
+ .p1788 ( optlc_net_1808 ) , .p1789 ( optlc_net_1809 ) ,
+ .p1790 ( optlc_net_1810 ) , .p1791 ( optlc_net_1811 ) ,
+ .p1792 ( optlc_net_1812 ) , .p1793 ( optlc_net_1813 ) ,
+ .p1794 ( optlc_net_1814 ) , .p1795 ( optlc_net_1815 ) ,
+ .p1796 ( optlc_net_1816 ) , .p1797 ( optlc_net_1817 ) ,
+ .p1798 ( optlc_net_1818 ) , .p1799 ( optlc_net_1819 ) ,
+ .p1800 ( optlc_net_1820 ) , .p1801 ( optlc_net_1821 ) ,
+ .p1802 ( optlc_net_1822 ) , .p1803 ( optlc_net_1823 ) ,
+ .p1804 ( optlc_net_1824 ) , .p1805 ( optlc_net_1825 ) ,
+ .p1806 ( optlc_net_1826 ) , .p1807 ( optlc_net_1827 ) ,
+ .p1808 ( optlc_net_1828 ) , .p1809 ( optlc_net_1829 ) ,
+ .p1810 ( optlc_net_1830 ) , .p1811 ( optlc_net_1831 ) ,
+ .p1812 ( optlc_net_1832 ) , .p1813 ( optlc_net_1833 ) ,
+ .p1814 ( optlc_net_1834 ) , .p1815 ( optlc_net_1835 ) ,
+ .p1816 ( optlc_net_1836 ) , .p1817 ( optlc_net_1837 ) ,
+ .p1818 ( optlc_net_1838 ) , .p1819 ( optlc_net_1839 ) ,
+ .p1820 ( optlc_net_1840 ) , .p1821 ( optlc_net_1841 ) ,
+ .p1822 ( optlc_net_1842 ) , .p1823 ( optlc_net_1843 ) ,
+ .p1824 ( optlc_net_1844 ) , .p1825 ( optlc_net_1845 ) ,
+ .p1826 ( optlc_net_1846 ) , .p1827 ( optlc_net_1847 ) ,
+ .p1828 ( optlc_net_1848 ) , .p1829 ( optlc_net_1849 ) ,
+ .p1830 ( optlc_net_1850 ) , .p1831 ( optlc_net_1851 ) ,
+ .p1832 ( optlc_net_1852 ) , .p1833 ( optlc_net_1853 ) ,
+ .p1834 ( optlc_net_1854 ) , .p1835 ( optlc_net_1855 ) ,
+ .p1836 ( optlc_net_1856 ) , .p1837 ( optlc_net_1857 ) ,
+ .p1838 ( optlc_net_1858 ) , .p1839 ( optlc_net_1859 ) ,
+ .p1840 ( optlc_net_1860 ) , .p1841 ( optlc_net_1861 ) ,
+ .p1842 ( optlc_net_1862 ) , .p1843 ( optlc_net_1863 ) ,
+ .p1844 ( optlc_net_1864 ) , .p1845 ( optlc_net_1865 ) ,
+ .p1846 ( optlc_net_1866 ) , .p1847 ( optlc_net_1867 ) ,
+ .p1848 ( optlc_net_1868 ) , .p1849 ( optlc_net_1869 ) ,
+ .p1850 ( optlc_net_1870 ) , .p1851 ( optlc_net_1871 ) ,
+ .p1852 ( optlc_net_1872 ) , .p1853 ( optlc_net_1873 ) ,
+ .p1854 ( optlc_net_1874 ) , .p1855 ( optlc_net_1875 ) ,
+ .p1856 ( optlc_net_1876 ) , .p1857 ( optlc_net_1877 ) ,
+ .p1858 ( optlc_net_1878 ) , .p1859 ( optlc_net_1879 ) ,
+ .p1860 ( optlc_net_1880 ) , .p1861 ( optlc_net_1881 ) ,
+ .p1862 ( optlc_net_1882 ) , .p1863 ( optlc_net_1883 ) ,
+ .p1864 ( optlc_net_1884 ) , .p1865 ( optlc_net_1885 ) ,
+ .p1866 ( optlc_net_1886 ) , .p1867 ( optlc_net_1887 ) ,
+ .p1868 ( optlc_net_1888 ) , .p1869 ( optlc_net_1889 ) ,
+ .p1870 ( optlc_net_1890 ) , .p1871 ( optlc_net_1891 ) ,
+ .p1872 ( optlc_net_1892 ) , .p1873 ( optlc_net_1893 ) ,
+ .p1874 ( optlc_net_1894 ) , .p1875 ( optlc_net_1895 ) ,
+ .p1876 ( optlc_net_1896 ) , .p1877 ( optlc_net_1897 ) ,
+ .p1878 ( optlc_net_1898 ) , .p1879 ( optlc_net_1899 ) ,
+ .p1880 ( optlc_net_1900 ) , .p1881 ( optlc_net_1901 ) ,
+ .p1882 ( optlc_net_1902 ) , .p1883 ( optlc_net_1903 ) ,
+ .p1884 ( optlc_net_1904 ) , .p1885 ( optlc_net_1905 ) ,
+ .p1886 ( optlc_net_1906 ) , .p1887 ( optlc_net_1907 ) ,
+ .p1888 ( optlc_net_1908 ) , .p1889 ( optlc_net_1909 ) ,
+ .p1890 ( optlc_net_1910 ) , .p1891 ( optlc_net_1911 ) ,
+ .p1892 ( optlc_net_1912 ) , .p1893 ( optlc_net_1913 ) ,
+ .p1894 ( optlc_net_1914 ) , .p1895 ( optlc_net_1915 ) ,
+ .p1896 ( optlc_net_1916 ) , .p1897 ( optlc_net_1917 ) ,
+ .p1898 ( optlc_net_1918 ) , .p1899 ( optlc_net_1919 ) ,
+ .p1900 ( optlc_net_1920 ) , .p1901 ( optlc_net_1921 ) ,
+ .p1902 ( optlc_net_1922 ) , .p1903 ( optlc_net_1923 ) ,
+ .p1904 ( optlc_net_1924 ) , .p1905 ( optlc_net_1925 ) ,
+ .p1906 ( optlc_net_1926 ) , .p1907 ( optlc_net_1927 ) ,
+ .p1908 ( optlc_net_1928 ) , .p1909 ( optlc_net_1929 ) ,
+ .p1910 ( optlc_net_1930 ) , .p1911 ( optlc_net_1931 ) ,
+ .p1912 ( optlc_net_1932 ) , .p1913 ( optlc_net_1933 ) ,
+ .p1914 ( optlc_net_1934 ) , .p1915 ( optlc_net_1935 ) ,
+ .p1916 ( optlc_net_1936 ) , .p1917 ( optlc_net_1937 ) ,
+ .p1918 ( optlc_net_1938 ) , .p1919 ( optlc_net_1939 ) ,
+ .p1920 ( optlc_net_1940 ) , .p1921 ( optlc_net_1941 ) ,
+ .p1922 ( optlc_net_1942 ) , .p1923 ( optlc_net_1943 ) ,
+ .p1924 ( optlc_net_1944 ) , .p1925 ( optlc_net_1945 ) ,
+ .p1926 ( optlc_net_1946 ) , .p1927 ( optlc_net_1947 ) ,
+ .p1928 ( optlc_net_1948 ) , .p1929 ( optlc_net_1949 ) ,
+ .p1930 ( optlc_net_1950 ) , .p1931 ( optlc_net_1951 ) ,
+ .p1932 ( optlc_net_1952 ) , .p1933 ( optlc_net_1953 ) ,
+ .p1934 ( optlc_net_1954 ) , .p1935 ( optlc_net_1955 ) ,
+ .p1936 ( optlc_net_1956 ) , .p1937 ( optlc_net_1957 ) ,
+ .p1938 ( optlc_net_1958 ) , .p1939 ( optlc_net_1959 ) ,
+ .p1940 ( optlc_net_1960 ) , .p1941 ( optlc_net_1961 ) ,
+ .p1942 ( optlc_net_1962 ) , .p1943 ( optlc_net_1963 ) ,
+ .p1944 ( optlc_net_1964 ) , .p1945 ( optlc_net_1965 ) ,
+ .p1946 ( optlc_net_1966 ) , .p1947 ( optlc_net_1967 ) ,
+ .p1948 ( optlc_net_1968 ) , .p1949 ( optlc_net_1969 ) ,
+ .p1950 ( optlc_net_1970 ) , .p1951 ( optlc_net_1971 ) ,
+ .p1952 ( optlc_net_1972 ) , .p1953 ( optlc_net_1973 ) ,
+ .p1954 ( optlc_net_1974 ) , .p1955 ( optlc_net_1975 ) ,
+ .p1956 ( optlc_net_1976 ) , .p1957 ( optlc_net_1977 ) ,
+ .p1958 ( optlc_net_1978 ) , .p1959 ( optlc_net_1979 ) ,
+ .p1960 ( optlc_net_1980 ) , .p1961 ( optlc_net_1981 ) ,
+ .p1962 ( optlc_net_1982 ) , .p1963 ( optlc_net_1983 ) ,
+ .p1964 ( optlc_net_1984 ) , .p1965 ( optlc_net_1985 ) ,
+ .p1966 ( optlc_net_1986 ) , .p1967 ( optlc_net_1987 ) ,
+ .p1968 ( optlc_net_1988 ) , .p1969 ( optlc_net_1989 ) ,
+ .p1970 ( optlc_net_1990 ) , .p1971 ( optlc_net_1991 ) ,
+ .p1972 ( optlc_net_1992 ) , .p1973 ( optlc_net_1993 ) ,
+ .p1974 ( optlc_net_1994 ) , .p1975 ( optlc_net_1995 ) ,
+ .p1976 ( optlc_net_1996 ) , .p1977 ( optlc_net_1997 ) ,
+ .p1978 ( optlc_net_1998 ) , .p1979 ( optlc_net_1999 ) ,
+ .p1980 ( optlc_net_2000 ) , .p1981 ( optlc_net_2001 ) ,
+ .p1982 ( optlc_net_2002 ) , .p1983 ( optlc_net_2003 ) ,
+ .p1984 ( optlc_net_2004 ) , .p1985 ( optlc_net_2005 ) ,
+ .p1986 ( optlc_net_2006 ) , .p1987 ( optlc_net_2007 ) ,
+ .p1988 ( optlc_net_2008 ) , .p1989 ( optlc_net_2009 ) ,
+ .p1990 ( optlc_net_2010 ) , .p1991 ( optlc_net_2011 ) ,
+ .p1992 ( optlc_net_2012 ) , .p1993 ( optlc_net_2013 ) ,
+ .p1994 ( optlc_net_2014 ) , .p1995 ( optlc_net_2015 ) ,
+ .p1996 ( optlc_net_2016 ) , .p1997 ( optlc_net_2017 ) ,
+ .p1998 ( optlc_net_2018 ) , .p1999 ( optlc_net_2019 ) ,
+ .p2000 ( optlc_net_2020 ) , .p2001 ( optlc_net_2021 ) ,
+ .p2002 ( optlc_net_2022 ) , .p2003 ( optlc_net_2023 ) ,
+ .p2004 ( optlc_net_2024 ) , .p2005 ( optlc_net_2025 ) ,
+ .p2006 ( optlc_net_2026 ) , .p2007 ( optlc_net_2027 ) ,
+ .p2008 ( optlc_net_2028 ) , .p2009 ( optlc_net_2029 ) ,
+ .p2010 ( optlc_net_2030 ) , .p2011 ( optlc_net_2031 ) ,
+ .p2012 ( optlc_net_2032 ) , .p2013 ( optlc_net_2033 ) ,
+ .p2014 ( optlc_net_2034 ) , .p2015 ( optlc_net_2035 ) ,
+ .p2016 ( optlc_net_2036 ) , .p2017 ( optlc_net_2037 ) ,
+ .p2018 ( optlc_net_2038 ) , .p2019 ( optlc_net_2039 ) ,
+ .p2020 ( optlc_net_2040 ) , .p2021 ( optlc_net_2041 ) ,
+ .p2022 ( optlc_net_2042 ) , .p2023 ( optlc_net_2043 ) ,
+ .p2024 ( optlc_net_2044 ) , .p2025 ( optlc_net_2045 ) ,
+ .p2026 ( optlc_net_2046 ) , .p2027 ( optlc_net_2047 ) ,
+ .p2028 ( optlc_net_2048 ) , .p2029 ( optlc_net_2049 ) ,
+ .p2030 ( optlc_net_2050 ) , .p2031 ( optlc_net_2051 ) ,
+ .p2032 ( optlc_net_2052 ) , .p2033 ( optlc_net_2053 ) ,
+ .p2034 ( optlc_net_2054 ) , .p2035 ( optlc_net_2055 ) ,
+ .p2036 ( optlc_net_2056 ) , .p2037 ( optlc_net_2057 ) ,
+ .p2038 ( optlc_net_2058 ) , .p2039 ( optlc_net_2059 ) ,
+ .p2040 ( optlc_net_2060 ) , .p2041 ( optlc_net_2061 ) ,
+ .p2042 ( optlc_net_2062 ) , .p2043 ( optlc_net_2063 ) ,
+ .p2044 ( optlc_net_2064 ) , .p2045 ( optlc_net_2065 ) ,
+ .p2046 ( optlc_net_2066 ) , .p2047 ( optlc_net_2067 ) ,
+ .p2048 ( optlc_net_2068 ) , .p2049 ( optlc_net_2069 ) ,
+ .p2050 ( optlc_net_2070 ) , .p2051 ( optlc_net_2071 ) ,
+ .p2052 ( optlc_net_2072 ) , .p2053 ( optlc_net_2073 ) ,
+ .p2054 ( optlc_net_2074 ) , .p2055 ( optlc_net_2075 ) ,
+ .p2056 ( optlc_net_2076 ) , .p2057 ( optlc_net_2077 ) ,
+ .p2058 ( optlc_net_2078 ) , .p2059 ( optlc_net_2079 ) ,
+ .p2060 ( optlc_net_2080 ) , .p2061 ( optlc_net_2081 ) ,
+ .p2062 ( optlc_net_2082 ) , .p2063 ( optlc_net_2083 ) ,
+ .p2064 ( optlc_net_2084 ) , .p2065 ( optlc_net_2085 ) ,
+ .p2066 ( optlc_net_2086 ) , .p2067 ( optlc_net_2087 ) ,
+ .p2068 ( optlc_net_2088 ) , .p2069 ( optlc_net_2089 ) ,
+ .p2070 ( optlc_net_2090 ) , .p2071 ( optlc_net_2091 ) ,
+ .p2072 ( optlc_net_2092 ) , .p2073 ( optlc_net_2093 ) ,
+ .p2074 ( optlc_net_2094 ) , .p2075 ( optlc_net_2095 ) ,
+ .p2076 ( optlc_net_2096 ) , .p2077 ( optlc_net_2097 ) ,
+ .p2078 ( optlc_net_2098 ) , .p2079 ( optlc_net_2099 ) ,
+ .p2080 ( optlc_net_2100 ) , .p2081 ( optlc_net_2101 ) ,
+ .p2082 ( optlc_net_2102 ) , .p2083 ( optlc_net_2103 ) ,
+ .p2084 ( optlc_net_2104 ) , .p2085 ( optlc_net_2105 ) ,
+ .p2086 ( optlc_net_2106 ) , .p2087 ( optlc_net_2107 ) ,
+ .p2088 ( optlc_net_2108 ) , .p2089 ( optlc_net_2109 ) ,
+ .p2090 ( optlc_net_2110 ) , .p2091 ( optlc_net_2111 ) ,
+ .p2092 ( optlc_net_2112 ) , .p2093 ( optlc_net_2113 ) ,
+ .p2094 ( optlc_net_2114 ) , .p2095 ( optlc_net_2115 ) ,
+ .p2096 ( optlc_net_2116 ) , .p2097 ( optlc_net_2117 ) ,
+ .p2098 ( optlc_net_2118 ) , .p2099 ( optlc_net_2119 ) ,
+ .p2100 ( optlc_net_2120 ) , .p2101 ( optlc_net_2121 ) ,
+ .p2102 ( optlc_net_2122 ) , .p2103 ( optlc_net_2123 ) ,
+ .p2104 ( optlc_net_2124 ) , .p2105 ( optlc_net_2125 ) ,
+ .p2106 ( optlc_net_2126 ) , .p2107 ( optlc_net_2127 ) ,
+ .p2108 ( optlc_net_2128 ) , .p2109 ( optlc_net_2129 ) ,
+ .p2110 ( optlc_net_2130 ) , .p2111 ( optlc_net_2131 ) ,
+ .p2112 ( optlc_net_2132 ) , .p2113 ( optlc_net_2133 ) ,
+ .p2114 ( optlc_net_2134 ) , .p2115 ( optlc_net_2135 ) ,
+ .p2116 ( optlc_net_2136 ) , .p2117 ( optlc_net_2137 ) ,
+ .p2118 ( optlc_net_2138 ) , .p2119 ( optlc_net_2139 ) ,
+ .p2120 ( optlc_net_2140 ) , .p2121 ( optlc_net_2141 ) ,
+ .p2122 ( optlc_net_2142 ) , .p2123 ( optlc_net_2143 ) ,
+ .p2124 ( optlc_net_2144 ) , .p2125 ( optlc_net_2145 ) ,
+ .p2126 ( optlc_net_2146 ) , .p2127 ( optlc_net_2147 ) ,
+ .p2128 ( optlc_net_2148 ) , .p2129 ( optlc_net_2149 ) ,
+ .p2130 ( optlc_net_2150 ) , .p2131 ( optlc_net_2151 ) ,
+ .p2132 ( optlc_net_2152 ) , .p2133 ( optlc_net_2153 ) ,
+ .p2134 ( optlc_net_2154 ) , .p2135 ( optlc_net_2155 ) ,
+ .p2136 ( optlc_net_2156 ) , .p2137 ( optlc_net_2157 ) ,
+ .p2138 ( optlc_net_2158 ) , .p2139 ( optlc_net_2159 ) ,
+ .p2140 ( optlc_net_2160 ) , .p2141 ( optlc_net_2161 ) ,
+ .p2142 ( optlc_net_2162 ) , .p2143 ( optlc_net_2163 ) ,
+ .p2144 ( optlc_net_2164 ) , .p2145 ( optlc_net_2165 ) ,
+ .p2146 ( optlc_net_2166 ) , .p2147 ( optlc_net_2167 ) ,
+ .p2148 ( optlc_net_2168 ) , .p2149 ( optlc_net_2169 ) ,
+ .p2150 ( optlc_net_2170 ) , .p2151 ( optlc_net_2171 ) ,
+ .p2152 ( optlc_net_2172 ) , .p2153 ( optlc_net_2173 ) ,
+ .p2154 ( optlc_net_2174 ) , .p2155 ( optlc_net_2175 ) ,
+ .p2156 ( optlc_net_2176 ) , .p2157 ( optlc_net_2177 ) ,
+ .p2158 ( optlc_net_2178 ) , .p2159 ( optlc_net_2179 ) ,
+ .p2160 ( optlc_net_2180 ) , .p2161 ( optlc_net_2181 ) ,
+ .p2162 ( optlc_net_2182 ) , .p2163 ( optlc_net_2183 ) ,
+ .p2164 ( optlc_net_2184 ) , .p2165 ( optlc_net_2185 ) ,
+ .p2166 ( optlc_net_2186 ) , .p2167 ( optlc_net_2187 ) ,
+ .p2168 ( optlc_net_2188 ) , .p2169 ( optlc_net_2189 ) ,
+ .p2170 ( optlc_net_2190 ) , .p2171 ( optlc_net_2191 ) ,
+ .p2172 ( optlc_net_2192 ) , .p2173 ( optlc_net_2193 ) ,
+ .p2174 ( optlc_net_2194 ) , .p2175 ( optlc_net_2195 ) ,
+ .p2176 ( optlc_net_2196 ) , .p2177 ( optlc_net_2197 ) ,
+ .p2178 ( optlc_net_2198 ) , .p2179 ( optlc_net_2199 ) ,
+ .p2180 ( optlc_net_2200 ) , .p2181 ( optlc_net_2201 ) ,
+ .p2182 ( optlc_net_2202 ) , .p2183 ( optlc_net_2203 ) ,
+ .p2184 ( optlc_net_2204 ) , .p2185 ( optlc_net_2205 ) ,
+ .p2186 ( optlc_net_2206 ) , .p2187 ( optlc_net_2207 ) ,
+ .p2188 ( optlc_net_2208 ) , .p2189 ( optlc_net_2209 ) ,
+ .p2190 ( optlc_net_2210 ) , .p2191 ( optlc_net_2211 ) ,
+ .p2192 ( optlc_net_2212 ) , .p2193 ( optlc_net_2213 ) ,
+ .p2194 ( optlc_net_2214 ) , .p2195 ( optlc_net_2215 ) ,
+ .p2196 ( optlc_net_2216 ) , .p2197 ( optlc_net_2217 ) ,
+ .p2198 ( optlc_net_2218 ) , .p2199 ( optlc_net_2219 ) ,
+ .p2200 ( optlc_net_2220 ) , .p2201 ( optlc_net_2221 ) ,
+ .p2202 ( optlc_net_2222 ) , .p2203 ( optlc_net_2223 ) ,
+ .p2204 ( optlc_net_2224 ) , .p2205 ( optlc_net_2225 ) ,
+ .p2206 ( optlc_net_2226 ) , .p2207 ( optlc_net_2227 ) ,
+ .p2208 ( optlc_net_2228 ) , .p2209 ( optlc_net_2229 ) ,
+ .p2210 ( optlc_net_2230 ) , .p2211 ( optlc_net_2231 ) ,
+ .p2212 ( optlc_net_2232 ) , .p2213 ( optlc_net_2233 ) ,
+ .p2214 ( optlc_net_2234 ) , .p2215 ( optlc_net_2235 ) ,
+ .p2216 ( optlc_net_2236 ) , .p2217 ( optlc_net_2237 ) ,
+ .p2218 ( optlc_net_2238 ) , .p2219 ( optlc_net_2239 ) ,
+ .p2220 ( optlc_net_2240 ) , .p2221 ( optlc_net_2241 ) ,
+ .p2222 ( optlc_net_2242 ) , .p2223 ( optlc_net_2243 ) ,
+ .p2224 ( optlc_net_2244 ) , .p2225 ( optlc_net_2245 ) ,
+ .p2226 ( optlc_net_2246 ) , .p2227 ( optlc_net_2247 ) ,
+ .p2228 ( optlc_net_2248 ) , .p2229 ( optlc_net_2249 ) ,
+ .p2230 ( optlc_net_2250 ) , .p2231 ( optlc_net_2251 ) ,
+ .p2232 ( optlc_net_2252 ) , .p2233 ( optlc_net_2253 ) ,
+ .p2234 ( optlc_net_2254 ) , .p2235 ( optlc_net_2255 ) ,
+ .p2236 ( optlc_net_2256 ) , .p2237 ( optlc_net_2257 ) ,
+ .p2238 ( optlc_net_2258 ) , .p2239 ( optlc_net_2259 ) ,
+ .p2240 ( optlc_net_2260 ) , .p2241 ( optlc_net_2261 ) ,
+ .p2242 ( optlc_net_2262 ) , .p2243 ( optlc_net_2263 ) ,
+ .p2244 ( optlc_net_2264 ) , .p2245 ( optlc_net_2265 ) ,
+ .p2246 ( optlc_net_2266 ) , .p2247 ( optlc_net_2267 ) ,
+ .p2248 ( optlc_net_2268 ) , .p2249 ( optlc_net_2269 ) ,
+ .p2250 ( optlc_net_2270 ) , .p2251 ( optlc_net_2271 ) ,
+ .p2252 ( optlc_net_2272 ) , .p2253 ( optlc_net_2273 ) ,
+ .p2254 ( optlc_net_2274 ) , .p2255 ( optlc_net_2275 ) ,
+ .p2256 ( optlc_net_2276 ) , .p2257 ( optlc_net_2277 ) ,
+ .p2258 ( optlc_net_2278 ) , .p2259 ( optlc_net_2279 ) ,
+ .p2260 ( optlc_net_2280 ) , .p2261 ( optlc_net_2281 ) ,
+ .p2262 ( optlc_net_2282 ) , .p2263 ( optlc_net_2283 ) ,
+ .p2264 ( optlc_net_2284 ) , .p2265 ( optlc_net_2285 ) ,
+ .p2266 ( optlc_net_2286 ) , .p2267 ( optlc_net_2287 ) ,
+ .p2268 ( optlc_net_2288 ) , .p2269 ( optlc_net_2289 ) ,
+ .p2270 ( optlc_net_2290 ) , .p2271 ( optlc_net_2291 ) ,
+ .p2272 ( optlc_net_2292 ) , .p2273 ( optlc_net_2293 ) ,
+ .p2274 ( optlc_net_2294 ) , .p2275 ( optlc_net_2295 ) ,
+ .p2276 ( optlc_net_2296 ) , .p2277 ( optlc_net_2297 ) ,
+ .p2278 ( optlc_net_2298 ) , .p2279 ( optlc_net_2299 ) ,
+ .p2280 ( optlc_net_2300 ) , .p2281 ( optlc_net_2301 ) ,
+ .p2282 ( optlc_net_2302 ) , .p2283 ( optlc_net_2303 ) ,
+ .p2284 ( optlc_net_2304 ) , .p2285 ( optlc_net_2305 ) ,
+ .p2286 ( optlc_net_2306 ) , .p2287 ( optlc_net_2307 ) ,
+ .p2288 ( optlc_net_2308 ) , .p2289 ( optlc_net_2309 ) ,
+ .p2290 ( optlc_net_2310 ) , .p2291 ( optlc_net_2311 ) ,
+ .p2292 ( optlc_net_2312 ) , .p2293 ( optlc_net_2313 ) ,
+ .p2294 ( optlc_net_2314 ) , .p2295 ( optlc_net_2315 ) ,
+ .p2296 ( optlc_net_2316 ) , .p2297 ( optlc_net_2317 ) ,
+ .p2298 ( optlc_net_2318 ) , .p2299 ( optlc_net_2319 ) ,
+ .p2300 ( optlc_net_2320 ) , .p2301 ( optlc_net_2321 ) ,
+ .p2302 ( optlc_net_2322 ) , .p2303 ( optlc_net_2323 ) ,
+ .p2304 ( optlc_net_2324 ) , .p2305 ( optlc_net_2325 ) ,
+ .p2306 ( optlc_net_2326 ) , .p2307 ( optlc_net_2327 ) ,
+ .p2308 ( optlc_net_2328 ) , .p2309 ( optlc_net_2329 ) ,
+ .p2310 ( optlc_net_2330 ) , .p2311 ( optlc_net_2331 ) ,
+ .p2312 ( optlc_net_2332 ) , .p2313 ( optlc_net_2333 ) ,
+ .p2314 ( optlc_net_2334 ) , .p2315 ( optlc_net_2335 ) ,
+ .p2316 ( optlc_net_2336 ) , .p2317 ( optlc_net_2337 ) ,
+ .p2318 ( optlc_net_2338 ) , .p2319 ( optlc_net_2339 ) ,
+ .p2320 ( optlc_net_2340 ) , .p2321 ( optlc_net_2341 ) ,
+ .p2322 ( optlc_net_2342 ) , .p2323 ( optlc_net_2343 ) ,
+ .p2324 ( optlc_net_2344 ) , .p2325 ( optlc_net_2345 ) ,
+ .p2326 ( optlc_net_2346 ) , .p2327 ( optlc_net_2347 ) ,
+ .p2328 ( optlc_net_2348 ) , .p2329 ( optlc_net_2349 ) ,
+ .p2330 ( optlc_net_2350 ) , .p2331 ( optlc_net_2351 ) ,
+ .p2332 ( optlc_net_2352 ) , .p2333 ( optlc_net_2353 ) ,
+ .p2334 ( optlc_net_2354 ) , .p2335 ( optlc_net_2355 ) ,
+ .p2336 ( optlc_net_2356 ) , .p2337 ( optlc_net_2357 ) ,
+ .p2338 ( optlc_net_2358 ) , .p2339 ( optlc_net_2359 ) ,
+ .p2340 ( optlc_net_2360 ) , .p2341 ( optlc_net_2361 ) ,
+ .p2342 ( optlc_net_2362 ) , .p2343 ( optlc_net_2363 ) ,
+ .p2344 ( optlc_net_2364 ) , .p2345 ( optlc_net_2365 ) ,
+ .p2346 ( optlc_net_2366 ) , .p2347 ( optlc_net_2367 ) ,
+ .p2348 ( optlc_net_2368 ) , .p2349 ( optlc_net_2369 ) ,
+ .p2350 ( optlc_net_2370 ) , .p2351 ( optlc_net_2371 ) ,
+ .p2352 ( optlc_net_2372 ) , .p2353 ( optlc_net_2373 ) ,
+ .p2354 ( optlc_net_2374 ) , .p2355 ( optlc_net_2375 ) ,
+ .p2356 ( optlc_net_2376 ) , .p2357 ( optlc_net_2377 ) ,
+ .p2358 ( optlc_net_2378 ) , .p2359 ( optlc_net_2379 ) ,
+ .p2360 ( optlc_net_2380 ) , .p2361 ( optlc_net_2381 ) ,
+ .p2362 ( optlc_net_2382 ) , .p2363 ( optlc_net_2383 ) ,
+ .p2364 ( optlc_net_2384 ) , .p2365 ( optlc_net_2385 ) ,
+ .p2366 ( optlc_net_2386 ) , .p2367 ( optlc_net_2387 ) ,
+ .p2368 ( optlc_net_2388 ) , .p2369 ( optlc_net_2389 ) ,
+ .p2370 ( optlc_net_2390 ) , .p2371 ( optlc_net_2391 ) ,
+ .p2372 ( optlc_net_2392 ) , .p2373 ( optlc_net_2393 ) ,
+ .p2374 ( optlc_net_2394 ) , .p2375 ( optlc_net_2395 ) ,
+ .p2376 ( optlc_net_2396 ) , .p2377 ( optlc_net_2397 ) ,
+ .p2378 ( optlc_net_2398 ) , .p2379 ( optlc_net_2399 ) ,
+ .p2380 ( optlc_net_2400 ) , .p2381 ( optlc_net_2401 ) ,
+ .p2382 ( optlc_net_2402 ) , .p2383 ( optlc_net_2403 ) ,
+ .p2384 ( optlc_net_2404 ) , .p2385 ( optlc_net_2405 ) ,
+ .p2386 ( optlc_net_2406 ) , .p2387 ( optlc_net_2407 ) ,
+ .p2388 ( optlc_net_2408 ) , .p2389 ( optlc_net_2409 ) ,
+ .p2390 ( optlc_net_2410 ) , .p2391 ( optlc_net_2411 ) ,
+ .p2392 ( optlc_net_2412 ) , .p2393 ( optlc_net_2413 ) ,
+ .p2394 ( optlc_net_2414 ) , .p2395 ( optlc_net_2415 ) ,
+ .p2396 ( optlc_net_2416 ) , .p2397 ( optlc_net_2417 ) ,
+ .p2398 ( optlc_net_2418 ) , .p2399 ( optlc_net_2419 ) ,
+ .p2400 ( optlc_net_2420 ) , .p2401 ( optlc_net_2421 ) ,
+ .p2402 ( optlc_net_2422 ) , .p2403 ( optlc_net_2423 ) ,
+ .p2404 ( optlc_net_2424 ) , .p2405 ( optlc_net_2425 ) ,
+ .p2406 ( optlc_net_2426 ) , .p2407 ( optlc_net_2427 ) ,
+ .p2408 ( optlc_net_2428 ) , .p2409 ( optlc_net_2429 ) ,
+ .p2410 ( optlc_net_2430 ) , .p2411 ( optlc_net_2431 ) ,
+ .p2412 ( optlc_net_2432 ) , .p2413 ( optlc_net_2433 ) ,
+ .p2414 ( optlc_net_2434 ) , .p2415 ( optlc_net_2435 ) ,
+ .p2416 ( optlc_net_2436 ) , .p2417 ( optlc_net_2437 ) ,
+ .p2418 ( optlc_net_2438 ) , .p2419 ( optlc_net_2439 ) ,
+ .p2420 ( optlc_net_2440 ) , .p2421 ( optlc_net_2441 ) ,
+ .p2422 ( optlc_net_2442 ) , .p2423 ( optlc_net_2443 ) ,
+ .p2424 ( optlc_net_2444 ) , .p2425 ( optlc_net_2445 ) ,
+ .p2426 ( optlc_net_2446 ) , .p2427 ( optlc_net_2447 ) ,
+ .p2428 ( optlc_net_2448 ) , .p2429 ( optlc_net_2449 ) ,
+ .p2430 ( optlc_net_2450 ) , .p2431 ( optlc_net_2451 ) ,
+ .p2432 ( optlc_net_2452 ) , .p2433 ( optlc_net_2453 ) ,
+ .p2434 ( optlc_net_2454 ) , .p2435 ( optlc_net_2455 ) ,
+ .p2436 ( optlc_net_2456 ) , .p2437 ( optlc_net_2457 ) ,
+ .p2438 ( optlc_net_2458 ) , .p2439 ( optlc_net_2459 ) ,
+ .p2440 ( optlc_net_2460 ) , .p2441 ( optlc_net_2461 ) ,
+ .p2442 ( optlc_net_2462 ) , .p2443 ( optlc_net_2463 ) ,
+ .p2444 ( optlc_net_2464 ) , .p2445 ( optlc_net_2465 ) ,
+ .p2446 ( optlc_net_2466 ) , .p2447 ( optlc_net_2467 ) ,
+ .p2448 ( optlc_net_2468 ) , .p2449 ( optlc_net_2469 ) ,
+ .p2450 ( optlc_net_2470 ) , .p2451 ( optlc_net_2471 ) ,
+ .p2452 ( optlc_net_2472 ) , .p2453 ( optlc_net_2473 ) ,
+ .p2454 ( optlc_net_2474 ) , .p2455 ( optlc_net_2475 ) ,
+ .p2456 ( optlc_net_2476 ) , .p2457 ( optlc_net_2477 ) ,
+ .p2458 ( optlc_net_2478 ) , .p2459 ( optlc_net_2479 ) ,
+ .p2460 ( optlc_net_2480 ) , .p2461 ( optlc_net_2481 ) ,
+ .p2462 ( optlc_net_2482 ) , .p2463 ( optlc_net_2483 ) ,
+ .p2464 ( optlc_net_2484 ) , .p2465 ( optlc_net_2485 ) ,
+ .p2466 ( optlc_net_2486 ) , .p2467 ( optlc_net_2487 ) ,
+ .p2468 ( optlc_net_2488 ) , .p2469 ( optlc_net_2489 ) ,
+ .p2470 ( optlc_net_2490 ) , .p2471 ( optlc_net_2491 ) ,
+ .p2472 ( optlc_net_2492 ) , .p2473 ( optlc_net_2493 ) ,
+ .p2474 ( optlc_net_2494 ) , .p2475 ( optlc_net_2495 ) ,
+ .p2476 ( optlc_net_2496 ) , .p2477 ( optlc_net_2497 ) ,
+ .p2478 ( optlc_net_2498 ) , .p2479 ( optlc_net_2499 ) ,
+ .p2480 ( optlc_net_2500 ) , .p2481 ( optlc_net_2501 ) ,
+ .p2482 ( optlc_net_2502 ) , .p2483 ( optlc_net_2503 ) ,
+ .p2484 ( optlc_net_2504 ) , .p2485 ( optlc_net_2505 ) ,
+ .p2486 ( optlc_net_2506 ) , .p2487 ( optlc_net_2507 ) ,
+ .p2488 ( optlc_net_2508 ) , .p2489 ( optlc_net_2509 ) ,
+ .p2490 ( optlc_net_2510 ) , .p2491 ( optlc_net_2511 ) ,
+ .p2492 ( optlc_net_2512 ) , .p2493 ( optlc_net_2513 ) ,
+ .p2494 ( optlc_net_2514 ) , .p2495 ( optlc_net_2515 ) ,
+ .p2496 ( optlc_net_2516 ) , .p2497 ( optlc_net_2517 ) ,
+ .p2498 ( optlc_net_2518 ) , .p2499 ( optlc_net_2519 ) ,
+ .p2500 ( optlc_net_2520 ) , .p2501 ( optlc_net_2521 ) ,
+ .p2502 ( optlc_net_2522 ) , .p2503 ( optlc_net_2523 ) ,
+ .p2504 ( optlc_net_2524 ) , .p2505 ( optlc_net_2525 ) ,
+ .p2506 ( optlc_net_2526 ) , .p2507 ( optlc_net_2527 ) ,
+ .p2508 ( optlc_net_2528 ) , .p2509 ( optlc_net_2529 ) ,
+ .p2510 ( optlc_net_2530 ) , .p2511 ( optlc_net_2531 ) ,
+ .p2512 ( optlc_net_2532 ) , .p2513 ( optlc_net_2533 ) ,
+ .p2514 ( optlc_net_2534 ) , .p2515 ( optlc_net_2535 ) ,
+ .p2516 ( optlc_net_2536 ) , .p2517 ( optlc_net_2537 ) ,
+ .p2518 ( optlc_net_2538 ) , .p2519 ( optlc_net_2539 ) ,
+ .p2520 ( optlc_net_2540 ) , .p2521 ( optlc_net_2541 ) ,
+ .p2522 ( optlc_net_2542 ) , .p2523 ( optlc_net_2543 ) ,
+ .p2524 ( optlc_net_2544 ) , .p2525 ( optlc_net_2545 ) ,
+ .p2526 ( optlc_net_2546 ) , .p2527 ( optlc_net_2547 ) ,
+ .p2528 ( optlc_net_2548 ) , .p2529 ( optlc_net_2549 ) ,
+ .p2530 ( optlc_net_2550 ) , .p2531 ( optlc_net_2551 ) ,
+ .p2532 ( optlc_net_2552 ) , .p2533 ( optlc_net_2553 ) ,
+ .p2534 ( optlc_net_2554 ) , .p2535 ( optlc_net_2555 ) ,
+ .p2536 ( optlc_net_2556 ) , .p2537 ( optlc_net_2557 ) ,
+ .p2538 ( optlc_net_2558 ) , .p2539 ( optlc_net_2559 ) ,
+ .p2540 ( optlc_net_2560 ) , .p2541 ( optlc_net_2561 ) ,
+ .p2542 ( optlc_net_2562 ) , .p2543 ( optlc_net_2563 ) ,
+ .p2544 ( optlc_net_2564 ) , .p2545 ( optlc_net_2565 ) ,
+ .p2546 ( optlc_net_2566 ) , .p2547 ( optlc_net_2567 ) ,
+ .p2548 ( optlc_net_2568 ) , .p2549 ( optlc_net_2569 ) ,
+ .p2550 ( optlc_net_2570 ) , .p2551 ( optlc_net_2571 ) ,
+ .p2552 ( optlc_net_2572 ) , .p2553 ( optlc_net_2573 ) ,
+ .p2554 ( optlc_net_2574 ) , .p2555 ( optlc_net_2575 ) ,
+ .p2556 ( optlc_net_2576 ) , .p2557 ( optlc_net_2577 ) ,
+ .p2558 ( optlc_net_2578 ) , .p2559 ( optlc_net_2579 ) ,
+ .p2560 ( optlc_net_2580 ) , .p2561 ( optlc_net_2581 ) ,
+ .p2562 ( optlc_net_2582 ) , .p2563 ( optlc_net_2583 ) ,
+ .p2564 ( optlc_net_2584 ) , .p2565 ( optlc_net_2585 ) ,
+ .p2566 ( optlc_net_2586 ) , .p2567 ( optlc_net_2587 ) ,
+ .p2568 ( optlc_net_2588 ) , .p2569 ( optlc_net_2589 ) ,
+ .p2570 ( optlc_net_2590 ) , .p2571 ( optlc_net_2591 ) ,
+ .p2572 ( optlc_net_2592 ) , .p2573 ( optlc_net_2593 ) ,
+ .p2574 ( optlc_net_2594 ) , .p2575 ( optlc_net_2595 ) ,
+ .p2576 ( optlc_net_2596 ) , .p2577 ( optlc_net_2597 ) ,
+ .p2578 ( optlc_net_2598 ) , .p2579 ( optlc_net_2599 ) ,
+ .p2580 ( optlc_net_2600 ) , .p2581 ( optlc_net_2601 ) ,
+ .p2582 ( optlc_net_2602 ) , .p2583 ( optlc_net_2603 ) ,
+ .p2584 ( optlc_net_2604 ) , .p2585 ( optlc_net_2605 ) ,
+ .p2586 ( optlc_net_2606 ) , .p2587 ( optlc_net_2607 ) ,
+ .p2588 ( optlc_net_2608 ) , .p2589 ( optlc_net_2609 ) ,
+ .p2590 ( optlc_net_2610 ) , .p2591 ( optlc_net_2611 ) ,
+ .p2592 ( optlc_net_2612 ) , .p2593 ( optlc_net_2613 ) ,
+ .p2594 ( optlc_net_2614 ) , .p2595 ( optlc_net_2615 ) ,
+ .p2596 ( optlc_net_2616 ) , .p2597 ( optlc_net_2617 ) ,
+ .p2598 ( optlc_net_2618 ) , .p2599 ( optlc_net_2619 ) ,
+ .p2600 ( optlc_net_2620 ) , .p2601 ( optlc_net_2621 ) ,
+ .p2602 ( optlc_net_2622 ) , .p2603 ( optlc_net_2623 ) ,
+ .p2604 ( optlc_net_2624 ) , .p2605 ( optlc_net_2625 ) ,
+ .p2606 ( optlc_net_2626 ) , .p2607 ( optlc_net_2627 ) ,
+ .p2608 ( optlc_net_2628 ) , .p2609 ( optlc_net_2629 ) ,
+ .p2610 ( optlc_net_2630 ) , .p2611 ( optlc_net_2631 ) ,
+ .p2612 ( optlc_net_2632 ) , .p2613 ( optlc_net_2633 ) ,
+ .p2614 ( optlc_net_2634 ) , .p2615 ( optlc_net_2635 ) ,
+ .p2616 ( optlc_net_2636 ) , .p2617 ( optlc_net_2637 ) ,
+ .p2618 ( optlc_net_2638 ) , .p2619 ( optlc_net_2639 ) ,
+ .p2620 ( optlc_net_2640 ) , .p2621 ( optlc_net_2641 ) ,
+ .p2622 ( optlc_net_2642 ) , .p2623 ( optlc_net_2643 ) ,
+ .p2624 ( optlc_net_2644 ) , .p2625 ( optlc_net_2645 ) ,
+ .p2626 ( optlc_net_2646 ) , .p2627 ( optlc_net_2647 ) ,
+ .p2628 ( optlc_net_2648 ) , .p2629 ( optlc_net_2649 ) ,
+ .p2630 ( optlc_net_2650 ) , .p2631 ( optlc_net_2651 ) ,
+ .p2632 ( optlc_net_2652 ) , .p2633 ( optlc_net_2653 ) ,
+ .p2634 ( optlc_net_2654 ) , .p2635 ( optlc_net_2655 ) ,
+ .p2636 ( optlc_net_2656 ) , .p2637 ( optlc_net_2657 ) ,
+ .p2638 ( optlc_net_2658 ) , .p2639 ( optlc_net_2659 ) ,
+ .p2640 ( optlc_net_2660 ) , .p2641 ( optlc_net_2661 ) ,
+ .p2642 ( optlc_net_2662 ) , .p2643 ( optlc_net_2663 ) ,
+ .p2644 ( optlc_net_2664 ) , .p2645 ( optlc_net_2665 ) ,
+ .p2646 ( optlc_net_2666 ) , .p2647 ( optlc_net_2667 ) ,
+ .p2648 ( optlc_net_2668 ) , .p2649 ( optlc_net_2669 ) ,
+ .p2650 ( optlc_net_2670 ) , .p2651 ( optlc_net_2671 ) ,
+ .p2652 ( optlc_net_2672 ) , .p2653 ( optlc_net_2673 ) ,
+ .p2654 ( optlc_net_2674 ) , .p2655 ( optlc_net_2675 ) ,
+ .p2656 ( optlc_net_2676 ) , .p2657 ( optlc_net_2677 ) ,
+ .p2658 ( optlc_net_2678 ) , .p2659 ( optlc_net_2679 ) ,
+ .p2660 ( optlc_net_2680 ) , .p2661 ( optlc_net_2681 ) ,
+ .p2662 ( optlc_net_2682 ) , .p2663 ( optlc_net_2683 ) ,
+ .p2664 ( optlc_net_2684 ) , .p2665 ( optlc_net_2685 ) ,
+ .p2666 ( optlc_net_2686 ) , .p2667 ( optlc_net_2687 ) ,
+ .p2668 ( optlc_net_2688 ) , .p2669 ( optlc_net_2689 ) ,
+ .p2670 ( optlc_net_2690 ) , .p2671 ( optlc_net_2691 ) ,
+ .p2672 ( optlc_net_2692 ) , .p2673 ( optlc_net_2693 ) ,
+ .p2674 ( optlc_net_2694 ) , .p2675 ( optlc_net_2695 ) ,
+ .p2676 ( optlc_net_2696 ) , .p2677 ( optlc_net_2697 ) ,
+ .p2678 ( optlc_net_2698 ) , .p2679 ( optlc_net_2699 ) ,
+ .p2680 ( optlc_net_2700 ) , .p2681 ( optlc_net_2701 ) ,
+ .p2682 ( optlc_net_2702 ) , .p2683 ( optlc_net_2703 ) ,
+ .p2684 ( optlc_net_2704 ) , .p2685 ( optlc_net_2705 ) ,
+ .p2686 ( optlc_net_2706 ) , .p2687 ( optlc_net_2707 ) ,
+ .p2688 ( optlc_net_2708 ) , .p2689 ( optlc_net_2709 ) ,
+ .p2690 ( optlc_net_2710 ) , .p2691 ( optlc_net_2711 ) ,
+ .p2692 ( optlc_net_2712 ) , .p2693 ( optlc_net_2713 ) ,
+ .p2694 ( optlc_net_2714 ) , .p2695 ( optlc_net_2715 ) ,
+ .p2696 ( optlc_net_2716 ) , .p2697 ( optlc_net_2717 ) ,
+ .p2698 ( optlc_net_2718 ) , .p2699 ( optlc_net_2719 ) ,
+ .p2700 ( optlc_net_2720 ) , .p2701 ( optlc_net_2721 ) ,
+ .p2702 ( optlc_net_2722 ) , .p2703 ( optlc_net_2723 ) ,
+ .p2704 ( optlc_net_2724 ) , .p2705 ( optlc_net_2725 ) ,
+ .p2706 ( optlc_net_2726 ) , .p2707 ( optlc_net_2727 ) ,
+ .p2708 ( optlc_net_2728 ) , .p2709 ( optlc_net_2729 ) ,
+ .p2710 ( optlc_net_2730 ) , .p2711 ( optlc_net_2731 ) ,
+ .p2712 ( optlc_net_2732 ) , .p2713 ( optlc_net_2733 ) ,
+ .p2714 ( optlc_net_2734 ) , .p2715 ( optlc_net_2735 ) ,
+ .p2716 ( optlc_net_2736 ) , .p2717 ( optlc_net_2737 ) ,
+ .p2718 ( optlc_net_2738 ) , .p2719 ( optlc_net_2739 ) ,
+ .p2720 ( optlc_net_2740 ) , .p2721 ( optlc_net_2741 ) ,
+ .p2722 ( optlc_net_2742 ) , .p2723 ( optlc_net_2743 ) ,
+ .p2724 ( optlc_net_2744 ) , .p2725 ( optlc_net_2745 ) ,
+ .p2726 ( optlc_net_2746 ) , .p2727 ( optlc_net_2747 ) ,
+ .p2728 ( optlc_net_2748 ) , .p2729 ( optlc_net_2749 ) ,
+ .p2730 ( optlc_net_2750 ) , .p2731 ( optlc_net_2751 ) ,
+ .p2732 ( optlc_net_2752 ) , .p2733 ( optlc_net_2753 ) ,
+ .p2734 ( optlc_net_2754 ) , .p2735 ( optlc_net_2755 ) ,
+ .p2736 ( optlc_net_2756 ) , .p2737 ( optlc_net_2757 ) ,
+ .p2738 ( optlc_net_2758 ) , .p2739 ( optlc_net_2759 ) ,
+ .p2740 ( optlc_net_2760 ) , .p2741 ( optlc_net_2761 ) ,
+ .p2742 ( optlc_net_2762 ) , .p2743 ( optlc_net_2763 ) ,
+ .p2744 ( optlc_net_2764 ) , .p2745 ( optlc_net_2765 ) ,
+ .p2746 ( optlc_net_2766 ) , .p2747 ( optlc_net_2767 ) ,
+ .p2748 ( optlc_net_2768 ) , .p2749 ( optlc_net_2769 ) ,
+ .p2750 ( optlc_net_2770 ) , .p2751 ( optlc_net_2771 ) ,
+ .p2752 ( optlc_net_2772 ) , .p2753 ( optlc_net_2773 ) ,
+ .p2754 ( optlc_net_2774 ) , .p2755 ( optlc_net_2775 ) ,
+ .p2756 ( optlc_net_2776 ) , .p2757 ( optlc_net_2777 ) ,
+ .p2758 ( optlc_net_2778 ) , .p2759 ( optlc_net_2779 ) ,
+ .p2760 ( optlc_net_2780 ) , .p2761 ( optlc_net_2781 ) ,
+ .p2762 ( optlc_net_2782 ) , .p2763 ( optlc_net_2783 ) ,
+ .p2764 ( optlc_net_2784 ) , .p2765 ( optlc_net_2785 ) ,
+ .p2766 ( optlc_net_2786 ) , .p2767 ( optlc_net_2787 ) ,
+ .p2768 ( optlc_net_2788 ) , .p2769 ( optlc_net_2789 ) ,
+ .p2770 ( optlc_net_2790 ) , .p2771 ( optlc_net_2791 ) ,
+ .p2772 ( optlc_net_2792 ) , .p2773 ( optlc_net_2793 ) ,
+ .p2774 ( optlc_net_2794 ) , .p2775 ( optlc_net_2795 ) ,
+ .p2776 ( optlc_net_2796 ) , .p2777 ( optlc_net_2797 ) ,
+ .p2778 ( optlc_net_2798 ) , .p2779 ( optlc_net_2799 ) ,
+ .p2780 ( optlc_net_2800 ) , .p2781 ( optlc_net_2801 ) ,
+ .p2782 ( optlc_net_2802 ) , .p2783 ( optlc_net_2803 ) ,
+ .p2784 ( optlc_net_2804 ) , .p2785 ( optlc_net_2805 ) ,
+ .p2786 ( optlc_net_2806 ) , .p2787 ( optlc_net_2807 ) ,
+ .p2788 ( optlc_net_2808 ) , .p2789 ( optlc_net_2809 ) ,
+ .p2790 ( optlc_net_2810 ) , .p2791 ( optlc_net_2811 ) ,
+ .p2792 ( optlc_net_2812 ) , .p2793 ( optlc_net_2813 ) ,
+ .p2794 ( optlc_net_2814 ) , .p2795 ( optlc_net_2815 ) ,
+ .p2796 ( optlc_net_2816 ) , .p2797 ( optlc_net_2817 ) ,
+ .p2798 ( optlc_net_2818 ) , .p2799 ( optlc_net_2819 ) ,
+ .p2800 ( optlc_net_2820 ) , .p2801 ( optlc_net_2821 ) ,
+ .p2802 ( optlc_net_2822 ) , .p2803 ( optlc_net_2823 ) ,
+ .p2804 ( optlc_net_2824 ) , .p2805 ( optlc_net_2825 ) ,
+ .p2806 ( optlc_net_2826 ) , .p2807 ( optlc_net_2827 ) ,
+ .p2808 ( optlc_net_2828 ) , .p2809 ( optlc_net_2829 ) ,
+ .p2810 ( optlc_net_2830 ) , .p2811 ( optlc_net_2831 ) ,
+ .p2812 ( optlc_net_2832 ) , .p2813 ( optlc_net_2833 ) ,
+ .p2814 ( optlc_net_2834 ) , .p2815 ( optlc_net_2835 ) ,
+ .p2816 ( optlc_net_2836 ) , .p2817 ( optlc_net_2837 ) ,
+ .p2818 ( optlc_net_2838 ) , .p2819 ( optlc_net_2839 ) ,
+ .p2820 ( optlc_net_2840 ) , .p2821 ( optlc_net_2841 ) ,
+ .p2822 ( optlc_net_2842 ) , .p2823 ( optlc_net_2843 ) ,
+ .p2824 ( optlc_net_2844 ) , .p2825 ( optlc_net_2845 ) ,
+ .p2826 ( optlc_net_2846 ) , .p2827 ( optlc_net_2847 ) ,
+ .p2828 ( optlc_net_2848 ) , .p2829 ( optlc_net_2849 ) ,
+ .p2830 ( optlc_net_2850 ) , .p2831 ( optlc_net_2851 ) ,
+ .p2832 ( optlc_net_2852 ) , .p2833 ( optlc_net_2853 ) ,
+ .p2834 ( optlc_net_2854 ) , .p2835 ( optlc_net_2855 ) ,
+ .p2836 ( optlc_net_2856 ) , .p2837 ( optlc_net_2857 ) ,
+ .p2838 ( optlc_net_2858 ) , .p2839 ( optlc_net_2859 ) ,
+ .p2840 ( optlc_net_2860 ) , .p2841 ( optlc_net_2861 ) ,
+ .p2842 ( optlc_net_2862 ) , .p2843 ( optlc_net_2863 ) ,
+ .p2844 ( optlc_net_2864 ) , .p2845 ( optlc_net_2865 ) ,
+ .p2846 ( optlc_net_2866 ) , .p2847 ( optlc_net_2867 ) ,
+ .p2848 ( optlc_net_2868 ) , .p2849 ( optlc_net_2869 ) ,
+ .p2850 ( optlc_net_2870 ) , .p2851 ( optlc_net_2871 ) ,
+ .p2852 ( optlc_net_2872 ) , .p2853 ( optlc_net_2873 ) ,
+ .p2854 ( optlc_net_2874 ) , .p2855 ( optlc_net_2875 ) ,
+ .p2856 ( optlc_net_2876 ) , .p2857 ( optlc_net_2877 ) ,
+ .p2858 ( optlc_net_2878 ) , .p2859 ( optlc_net_2879 ) ,
+ .p2860 ( optlc_net_2880 ) , .p2861 ( optlc_net_2881 ) ,
+ .p2862 ( optlc_net_2882 ) , .p2863 ( optlc_net_2883 ) ,
+ .p2864 ( optlc_net_2884 ) , .p2865 ( optlc_net_2885 ) ,
+ .p2866 ( optlc_net_2886 ) , .p2867 ( optlc_net_2887 ) ,
+ .p2868 ( optlc_net_2888 ) , .p2869 ( optlc_net_2889 ) ,
+ .p2870 ( optlc_net_2890 ) , .p2871 ( optlc_net_2891 ) ,
+ .p2872 ( optlc_net_2892 ) , .p2873 ( optlc_net_2893 ) ,
+ .p2874 ( optlc_net_2894 ) , .p2875 ( optlc_net_2895 ) ,
+ .p2876 ( optlc_net_2896 ) , .p2877 ( optlc_net_2897 ) ,
+ .p2878 ( optlc_net_2898 ) , .p2879 ( optlc_net_2899 ) ,
+ .p2880 ( optlc_net_2900 ) , .p2881 ( optlc_net_2901 ) ,
+ .p2882 ( optlc_net_2902 ) , .p2883 ( optlc_net_2903 ) ,
+ .p2884 ( optlc_net_2904 ) , .p2885 ( optlc_net_2905 ) ,
+ .p2886 ( optlc_net_2906 ) , .p2887 ( optlc_net_2907 ) ,
+ .p2888 ( optlc_net_2908 ) , .p2889 ( optlc_net_2909 ) ,
+ .p2890 ( optlc_net_2910 ) , .p2891 ( optlc_net_2911 ) ,
+ .p2892 ( optlc_net_2912 ) , .p2893 ( optlc_net_2913 ) ,
+ .p2894 ( optlc_net_2914 ) , .p2895 ( optlc_net_2915 ) ,
+ .p2896 ( optlc_net_2916 ) , .p2897 ( optlc_net_2917 ) ,
+ .p2898 ( optlc_net_2918 ) , .p2899 ( optlc_net_2919 ) ,
+ .p2900 ( optlc_net_2920 ) , .p2901 ( optlc_net_2921 ) ,
+ .p2902 ( optlc_net_2922 ) , .p2903 ( optlc_net_2923 ) ,
+ .p2904 ( optlc_net_2924 ) , .p2905 ( optlc_net_2925 ) ,
+ .p2906 ( optlc_net_2926 ) , .p2907 ( optlc_net_2927 ) ,
+ .p2908 ( optlc_net_2928 ) , .p2909 ( optlc_net_2929 ) ,
+ .p2910 ( optlc_net_2930 ) , .p2911 ( optlc_net_2931 ) ,
+ .p2912 ( optlc_net_2932 ) , .p2913 ( optlc_net_2933 ) ,
+ .p2914 ( optlc_net_2934 ) , .p2915 ( optlc_net_2935 ) ,
+ .p2916 ( optlc_net_2936 ) , .p2917 ( optlc_net_2937 ) ,
+ .p2918 ( optlc_net_2938 ) , .p2919 ( optlc_net_2939 ) ,
+ .p2920 ( optlc_net_2940 ) , .p2921 ( optlc_net_2941 ) ,
+ .p2922 ( optlc_net_2942 ) , .p2923 ( optlc_net_2943 ) ,
+ .p2924 ( optlc_net_2944 ) , .p2925 ( optlc_net_2945 ) ,
+ .p2926 ( optlc_net_2946 ) , .p2927 ( optlc_net_2947 ) ,
+ .p2928 ( optlc_net_2948 ) , .p2929 ( optlc_net_2949 ) ,
+ .p2930 ( optlc_net_2950 ) , .p2931 ( optlc_net_2951 ) ,
+ .p2932 ( optlc_net_2952 ) , .p2933 ( optlc_net_2953 ) ,
+ .p2934 ( optlc_net_2954 ) , .p2935 ( optlc_net_2955 ) ,
+ .p2936 ( optlc_net_2956 ) , .p2937 ( optlc_net_2957 ) ,
+ .p2938 ( optlc_net_2958 ) , .p2939 ( optlc_net_2959 ) ,
+ .p2940 ( optlc_net_2960 ) , .p2941 ( optlc_net_2961 ) ,
+ .p2942 ( optlc_net_2962 ) , .p2943 ( optlc_net_2963 ) ,
+ .p2944 ( optlc_net_2964 ) , .p2945 ( optlc_net_2965 ) ,
+ .p2946 ( optlc_net_2966 ) , .p2947 ( optlc_net_2967 ) ,
+ .p2948 ( optlc_net_2968 ) , .p2949 ( optlc_net_2969 ) ,
+ .p2950 ( optlc_net_2970 ) , .p2951 ( optlc_net_2971 ) ,
+ .p2952 ( optlc_net_2972 ) , .p2953 ( optlc_net_2973 ) ,
+ .p2954 ( optlc_net_2974 ) , .p2955 ( optlc_net_2975 ) ,
+ .p2956 ( optlc_net_2976 ) , .p2957 ( optlc_net_2977 ) ,
+ .p2958 ( optlc_net_2978 ) , .p2959 ( optlc_net_2979 ) ,
+ .p2960 ( optlc_net_2980 ) , .p2961 ( optlc_net_2981 ) ,
+ .p2962 ( optlc_net_2982 ) , .p2963 ( optlc_net_2983 ) ,
+ .p2964 ( optlc_net_2984 ) , .p2965 ( optlc_net_2985 ) ,
+ .p2966 ( optlc_net_2986 ) , .p2967 ( optlc_net_2987 ) ,
+ .p2968 ( optlc_net_2988 ) , .p2969 ( optlc_net_2989 ) ,
+ .p2970 ( optlc_net_2990 ) , .p2971 ( optlc_net_2991 ) ,
+ .p2972 ( optlc_net_2992 ) , .p2973 ( optlc_net_2993 ) ,
+ .p2974 ( optlc_net_2994 ) , .p2975 ( optlc_net_2995 ) ,
+ .p2976 ( optlc_net_2996 ) , .p2977 ( optlc_net_2997 ) ,
+ .p2978 ( optlc_net_2998 ) , .p2979 ( optlc_net_2999 ) ,
+ .p2980 ( optlc_net_3000 ) , .p2981 ( optlc_net_3001 ) ,
+ .p2982 ( optlc_net_3002 ) , .p2983 ( optlc_net_3003 ) ,
+ .p2984 ( optlc_net_3004 ) , .p2985 ( optlc_net_3005 ) ,
+ .p2986 ( optlc_net_3006 ) , .p2987 ( optlc_net_3007 ) ,
+ .p2988 ( optlc_net_3008 ) , .p2989 ( optlc_net_3009 ) ,
+ .p2990 ( optlc_net_3010 ) , .p2991 ( optlc_net_3011 ) ,
+ .p2992 ( optlc_net_3012 ) , .p2993 ( optlc_net_3013 ) ,
+ .p2994 ( optlc_net_3014 ) , .p2995 ( optlc_net_3015 ) ,
+ .p2996 ( optlc_net_3016 ) , .p2997 ( optlc_net_3017 ) ,
+ .p2998 ( optlc_net_3018 ) , .p2999 ( optlc_net_3019 ) ,
+ .p3000 ( optlc_net_3020 ) , .p3001 ( optlc_net_3021 ) ,
+ .p3002 ( optlc_net_3022 ) , .p3003 ( optlc_net_3023 ) ,
+ .p3004 ( optlc_net_3024 ) , .p3005 ( optlc_net_3025 ) ,
+ .p3006 ( optlc_net_3026 ) , .p3007 ( optlc_net_3027 ) ,
+ .p3008 ( optlc_net_3028 ) , .p3009 ( optlc_net_3029 ) ,
+ .p3010 ( optlc_net_3030 ) , .p3011 ( optlc_net_3031 ) ,
+ .p3012 ( optlc_net_3032 ) , .p3013 ( optlc_net_3033 ) ,
+ .p3014 ( optlc_net_3034 ) , .p3015 ( optlc_net_3035 ) ,
+ .p3016 ( optlc_net_3036 ) , .p3017 ( optlc_net_3037 ) ,
+ .p3018 ( optlc_net_3038 ) , .p3019 ( optlc_net_3039 ) ,
+ .p3020 ( optlc_net_3040 ) , .p3021 ( optlc_net_3041 ) ,
+ .p3022 ( optlc_net_3042 ) , .p3023 ( optlc_net_3043 ) ,
+ .p3024 ( optlc_net_3044 ) , .p3025 ( optlc_net_3045 ) ,
+ .p3026 ( optlc_net_3046 ) , .p3027 ( optlc_net_3047 ) ,
+ .p3028 ( optlc_net_3048 ) , .p3029 ( optlc_net_3049 ) ,
+ .p3030 ( optlc_net_3050 ) , .p3031 ( optlc_net_3051 ) ,
+ .p3032 ( optlc_net_3052 ) , .p3033 ( optlc_net_3053 ) ,
+ .p3034 ( optlc_net_3054 ) , .p3035 ( optlc_net_3055 ) ,
+ .p3036 ( optlc_net_3056 ) , .p3037 ( optlc_net_3057 ) ,
+ .p3038 ( optlc_net_3058 ) , .p3039 ( optlc_net_3059 ) ,
+ .p3040 ( optlc_net_3060 ) , .p3041 ( optlc_net_3061 ) ,
+ .p3042 ( optlc_net_3062 ) , .p3043 ( optlc_net_3063 ) ,
+ .p3044 ( optlc_net_3064 ) , .p3045 ( optlc_net_3065 ) ,
+ .p3046 ( optlc_net_3066 ) , .p3047 ( optlc_net_3067 ) ,
+ .p3048 ( optlc_net_3068 ) , .p3049 ( optlc_net_3069 ) ,
+ .p3050 ( optlc_net_3070 ) , .p3051 ( optlc_net_3071 ) ,
+ .p3052 ( optlc_net_3072 ) , .p3053 ( optlc_net_3073 ) ,
+ .p3054 ( optlc_net_3074 ) , .p3055 ( optlc_net_3075 ) ,
+ .p3056 ( optlc_net_3076 ) , .p3057 ( optlc_net_3077 ) ,
+ .p3058 ( optlc_net_3078 ) , .p3059 ( optlc_net_3079 ) ,
+ .p3060 ( optlc_net_3080 ) , .p3061 ( optlc_net_3081 ) ,
+ .p3062 ( optlc_net_3082 ) , .p3063 ( optlc_net_3083 ) ,
+ .p3064 ( optlc_net_3084 ) , .p3065 ( optlc_net_3085 ) ,
+ .p3066 ( optlc_net_3086 ) , .p3067 ( optlc_net_3087 ) ,
+ .p3068 ( optlc_net_3088 ) , .p3069 ( optlc_net_3089 ) ,
+ .p3070 ( optlc_net_3090 ) , .p3071 ( optlc_net_3091 ) ,
+ .p3072 ( optlc_net_3092 ) , .p3073 ( optlc_net_3093 ) ,
+ .p3074 ( optlc_net_3094 ) , .p3075 ( optlc_net_3095 ) ,
+ .p3076 ( optlc_net_3096 ) , .p3077 ( optlc_net_3097 ) ,
+ .p3078 ( optlc_net_3098 ) , .p3079 ( optlc_net_3099 ) ,
+ .p3080 ( optlc_net_3100 ) , .p3081 ( optlc_net_3101 ) ,
+ .p3082 ( optlc_net_3102 ) , .p3083 ( optlc_net_3103 ) ,
+ .p3084 ( optlc_net_3104 ) , .p3085 ( optlc_net_3105 ) ,
+ .p3086 ( optlc_net_3106 ) , .p3087 ( optlc_net_3107 ) ,
+ .p3088 ( optlc_net_3108 ) , .p3089 ( optlc_net_3109 ) ,
+ .p3090 ( optlc_net_3110 ) , .p3091 ( optlc_net_3111 ) ,
+ .p3092 ( optlc_net_3112 ) , .p3093 ( optlc_net_3113 ) ,
+ .p3094 ( optlc_net_3114 ) , .p3095 ( optlc_net_3115 ) ,
+ .p3096 ( optlc_net_3116 ) , .p3097 ( optlc_net_3117 ) ,
+ .p3098 ( optlc_net_3118 ) , .p3099 ( optlc_net_3119 ) ,
+ .p3100 ( optlc_net_3120 ) , .p3101 ( optlc_net_3121 ) ,
+ .p3102 ( optlc_net_3122 ) , .p3103 ( optlc_net_3123 ) ,
+ .p3104 ( optlc_net_3124 ) , .p3105 ( optlc_net_3125 ) ,
+ .p3106 ( optlc_net_3126 ) , .p3107 ( optlc_net_3127 ) ,
+ .p3108 ( optlc_net_3128 ) , .p3109 ( optlc_net_3129 ) ,
+ .p3110 ( optlc_net_3130 ) , .p3111 ( optlc_net_3131 ) ,
+ .p3112 ( optlc_net_3132 ) , .p3113 ( optlc_net_3133 ) ,
+ .p3114 ( optlc_net_3134 ) , .p3115 ( optlc_net_3135 ) ,
+ .p3116 ( optlc_net_3136 ) , .p3117 ( optlc_net_3137 ) ,
+ .p3118 ( optlc_net_3138 ) , .p3119 ( optlc_net_3139 ) ,
+ .p3120 ( optlc_net_3140 ) , .p3121 ( optlc_net_3141 ) ,
+ .p3122 ( optlc_net_3142 ) , .p3123 ( optlc_net_3143 ) ,
+ .p3124 ( optlc_net_3144 ) , .p3125 ( optlc_net_3145 ) ,
+ .p3126 ( optlc_net_3146 ) , .p3127 ( optlc_net_3147 ) ,
+ .p3128 ( optlc_net_3148 ) , .p3129 ( optlc_net_3149 ) ,
+ .p3130 ( optlc_net_3150 ) , .p3131 ( optlc_net_3151 ) ,
+ .p3132 ( optlc_net_3152 ) , .p3133 ( optlc_net_3153 ) ,
+ .p3134 ( optlc_net_3154 ) , .p3135 ( optlc_net_3155 ) ,
+ .p3136 ( optlc_net_3156 ) , .p3137 ( optlc_net_3157 ) ,
+ .p3138 ( optlc_net_3158 ) , .p3139 ( optlc_net_3159 ) ,
+ .p3140 ( optlc_net_3160 ) , .p3141 ( optlc_net_3161 ) ,
+ .p3142 ( optlc_net_3162 ) , .p3143 ( optlc_net_3163 ) ,
+ .p3144 ( optlc_net_3164 ) , .p3145 ( optlc_net_3165 ) ,
+ .p3146 ( optlc_net_3166 ) , .p3147 ( optlc_net_3167 ) ,
+ .p3148 ( optlc_net_3168 ) , .p3149 ( optlc_net_3169 ) ,
+ .p3150 ( optlc_net_3170 ) , .p3151 ( optlc_net_3171 ) ,
+ .p3152 ( optlc_net_3172 ) , .p3153 ( optlc_net_3173 ) ,
+ .p3154 ( optlc_net_3174 ) , .p3155 ( optlc_net_3175 ) ,
+ .p3156 ( optlc_net_3176 ) , .p3157 ( optlc_net_3177 ) ,
+ .p3158 ( optlc_net_3178 ) , .p3159 ( optlc_net_3179 ) ,
+ .p3160 ( optlc_net_3180 ) , .p3161 ( optlc_net_3181 ) ,
+ .p3162 ( optlc_net_3182 ) , .p3163 ( optlc_net_3183 ) ,
+ .p3164 ( optlc_net_3184 ) , .p3165 ( optlc_net_3185 ) ,
+ .p3166 ( optlc_net_3186 ) , .p3167 ( optlc_net_3187 ) ,
+ .p3168 ( optlc_net_3188 ) , .p3169 ( optlc_net_3189 ) ,
+ .p3170 ( optlc_net_3190 ) , .p3171 ( optlc_net_3191 ) ,
+ .p3172 ( optlc_net_3192 ) , .p3173 ( optlc_net_3193 ) ,
+ .p3174 ( optlc_net_3194 ) , .p3175 ( optlc_net_3195 ) ,
+ .p3176 ( optlc_net_3196 ) , .p3177 ( optlc_net_3197 ) ,
+ .p3178 ( optlc_net_3198 ) , .p3179 ( optlc_net_3199 ) ,
+ .p3180 ( optlc_net_3200 ) , .p3181 ( optlc_net_3201 ) ,
+ .p3182 ( optlc_net_3202 ) , .p3183 ( optlc_net_3203 ) ,
+ .p3184 ( optlc_net_3204 ) , .p3185 ( optlc_net_3205 ) ,
+ .p3186 ( optlc_net_3206 ) , .p3187 ( optlc_net_3207 ) ,
+ .p3188 ( optlc_net_3208 ) , .p3189 ( optlc_net_3209 ) ,
+ .p3190 ( optlc_net_3210 ) , .p3191 ( optlc_net_3211 ) ,
+ .p3192 ( optlc_net_3212 ) , .p3193 ( optlc_net_3213 ) ,
+ .p3194 ( optlc_net_3214 ) , .p3195 ( optlc_net_3215 ) ,
+ .p3196 ( optlc_net_3216 ) , .p3197 ( optlc_net_3217 ) ,
+ .p3198 ( optlc_net_3218 ) , .p3199 ( optlc_net_3219 ) ,
+ .p3200 ( optlc_net_3220 ) , .p3201 ( optlc_net_3221 ) ,
+ .p3202 ( optlc_net_3222 ) , .p3203 ( optlc_net_3223 ) ,
+ .p3204 ( optlc_net_3224 ) , .p3205 ( optlc_net_3225 ) ,
+ .p3206 ( optlc_net_3226 ) , .p3207 ( optlc_net_3227 ) ,
+ .p3208 ( optlc_net_3228 ) , .p3209 ( optlc_net_3229 ) ,
+ .p3210 ( optlc_net_3230 ) , .p3211 ( optlc_net_3231 ) ,
+ .p3212 ( optlc_net_3232 ) , .p3213 ( optlc_net_3233 ) ,
+ .p3214 ( optlc_net_3234 ) , .p3215 ( optlc_net_3235 ) ,
+ .p3216 ( optlc_net_3236 ) , .p3217 ( optlc_net_3237 ) ,
+ .p3218 ( optlc_net_3238 ) , .p3219 ( optlc_net_3239 ) ,
+ .p3220 ( optlc_net_3240 ) , .p3221 ( optlc_net_3241 ) ,
+ .p3222 ( optlc_net_3242 ) , .p3223 ( optlc_net_3243 ) ,
+ .p3224 ( optlc_net_3244 ) , .p3225 ( optlc_net_3245 ) ,
+ .p3226 ( optlc_net_3246 ) , .p3227 ( optlc_net_3247 ) ,
+ .p3228 ( optlc_net_3248 ) , .p3229 ( optlc_net_3249 ) ,
+ .p3230 ( optlc_net_3250 ) , .p3231 ( optlc_net_3251 ) ,
+ .p3232 ( optlc_net_3252 ) , .p3233 ( optlc_net_3253 ) ,
+ .p3234 ( optlc_net_3254 ) , .p3235 ( optlc_net_3255 ) ,
+ .p3236 ( optlc_net_3256 ) , .p3237 ( optlc_net_3257 ) ,
+ .p3238 ( optlc_net_3258 ) , .p3239 ( optlc_net_3259 ) ,
+ .p3240 ( optlc_net_3260 ) , .p3241 ( optlc_net_3261 ) ,
+ .p3242 ( optlc_net_3262 ) , .p3243 ( optlc_net_3263 ) ,
+ .p3244 ( optlc_net_3264 ) , .p3245 ( optlc_net_3265 ) ,
+ .p3246 ( optlc_net_3266 ) , .p3247 ( optlc_net_3267 ) ,
+ .p3248 ( optlc_net_3268 ) , .p3249 ( optlc_net_3269 ) ,
+ .p3250 ( optlc_net_3270 ) , .p3251 ( optlc_net_3271 ) ,
+ .p3252 ( optlc_net_3272 ) , .p3253 ( optlc_net_3273 ) ,
+ .p3254 ( optlc_net_3274 ) , .p3255 ( optlc_net_3275 ) ,
+ .p3256 ( optlc_net_3276 ) , .p3257 ( optlc_net_3277 ) ,
+ .p3258 ( optlc_net_3278 ) , .p3259 ( optlc_net_3279 ) ,
+ .p3260 ( optlc_net_3280 ) , .p3261 ( optlc_net_3281 ) ,
+ .p3262 ( optlc_net_3282 ) , .p3263 ( optlc_net_3283 ) ,
+ .p3264 ( optlc_net_3284 ) , .p3265 ( optlc_net_3285 ) ,
+ .p3266 ( optlc_net_3286 ) , .p3267 ( optlc_net_3287 ) ,
+ .p3268 ( optlc_net_3288 ) , .p3269 ( optlc_net_3289 ) ,
+ .p3270 ( optlc_net_3290 ) , .p3271 ( optlc_net_3291 ) ,
+ .p3272 ( optlc_net_3292 ) , .p3273 ( optlc_net_3293 ) ,
+ .p3274 ( optlc_net_3294 ) , .p3275 ( optlc_net_3295 ) ,
+ .p3276 ( optlc_net_3296 ) , .p3277 ( optlc_net_3297 ) ,
+ .p3278 ( optlc_net_3298 ) , .p3279 ( optlc_net_3299 ) ,
+ .p3280 ( optlc_net_3300 ) , .p3281 ( optlc_net_3301 ) ,
+ .p3282 ( optlc_net_3302 ) , .p3283 ( optlc_net_3303 ) ,
+ .p3284 ( optlc_net_3304 ) , .p3285 ( optlc_net_3305 ) ,
+ .p3286 ( optlc_net_3306 ) , .p3287 ( optlc_net_3307 ) ,
+ .p3288 ( optlc_net_3308 ) , .p3289 ( optlc_net_3309 ) ,
+ .p3290 ( optlc_net_3310 ) , .p3291 ( optlc_net_3311 ) ,
+ .p3292 ( optlc_net_3312 ) , .p3293 ( optlc_net_3313 ) ,
+ .p3294 ( optlc_net_3314 ) , .p3295 ( optlc_net_3315 ) ,
+ .p3296 ( optlc_net_3316 ) , .p3297 ( optlc_net_3317 ) ,
+ .p3298 ( optlc_net_3318 ) , .p3299 ( optlc_net_3319 ) ,
+ .p3300 ( optlc_net_3320 ) , .p3301 ( optlc_net_3321 ) ,
+ .p3302 ( optlc_net_3322 ) , .p3303 ( optlc_net_3323 ) ,
+ .p3304 ( optlc_net_3324 ) , .p3305 ( optlc_net_3325 ) ,
+ .p3306 ( optlc_net_3326 ) , .p3307 ( optlc_net_3327 ) ,
+ .p3308 ( optlc_net_3328 ) , .p3309 ( optlc_net_3329 ) ,
+ .p3310 ( optlc_net_3330 ) , .p3311 ( optlc_net_3331 ) ,
+ .p3312 ( optlc_net_3332 ) , .p3313 ( optlc_net_3333 ) ,
+ .p3314 ( optlc_net_3334 ) , .p3315 ( optlc_net_3335 ) ,
+ .p3316 ( optlc_net_3336 ) , .p3317 ( optlc_net_3337 ) ,
+ .p3318 ( optlc_net_3338 ) , .p3319 ( optlc_net_3339 ) ,
+ .p3320 ( optlc_net_3340 ) , .p3321 ( optlc_net_3341 ) ,
+ .p3322 ( optlc_net_3342 ) , .p3323 ( optlc_net_3343 ) ,
+ .p3324 ( optlc_net_3344 ) , .p3325 ( optlc_net_3345 ) ,
+ .p3326 ( optlc_net_3346 ) , .p3327 ( optlc_net_3347 ) ,
+ .p3328 ( optlc_net_3348 ) , .p3329 ( optlc_net_3349 ) ,
+ .p3330 ( optlc_net_3350 ) , .p3331 ( optlc_net_3351 ) ,
+ .p3332 ( optlc_net_3352 ) , .p3333 ( optlc_net_3353 ) ,
+ .p3334 ( optlc_net_3354 ) , .p3335 ( optlc_net_3355 ) ,
+ .p3336 ( optlc_net_3356 ) , .p3337 ( optlc_net_3357 ) ,
+ .p3338 ( optlc_net_3358 ) , .p3339 ( optlc_net_3359 ) ,
+ .p3340 ( optlc_net_3360 ) , .p3341 ( optlc_net_3361 ) ,
+ .p3342 ( optlc_net_3362 ) , .p3343 ( optlc_net_3363 ) ,
+ .p3344 ( optlc_net_3364 ) , .p3345 ( optlc_net_3365 ) ,
+ .p3346 ( optlc_net_3366 ) , .p3347 ( optlc_net_3367 ) ,
+ .p3348 ( optlc_net_3368 ) , .p3349 ( optlc_net_3369 ) ,
+ .p3350 ( optlc_net_3370 ) , .p3351 ( optlc_net_3371 ) ,
+ .p3352 ( optlc_net_3372 ) , .p3353 ( optlc_net_3373 ) ,
+ .p3354 ( optlc_net_3374 ) , .p3355 ( optlc_net_3375 ) ,
+ .p3356 ( optlc_net_3376 ) , .p3357 ( optlc_net_3377 ) ,
+ .p3358 ( optlc_net_3378 ) , .p3359 ( optlc_net_3379 ) ,
+ .p3360 ( optlc_net_3380 ) , .p3361 ( optlc_net_3381 ) ,
+ .p3362 ( optlc_net_3382 ) , .p3363 ( optlc_net_3383 ) ,
+ .p3364 ( optlc_net_3384 ) , .p3365 ( optlc_net_3385 ) ,
+ .p3366 ( optlc_net_3386 ) , .p3367 ( optlc_net_3387 ) ,
+ .p3368 ( optlc_net_3388 ) , .p3369 ( optlc_net_3389 ) ,
+ .p3370 ( optlc_net_3390 ) , .p3371 ( optlc_net_3391 ) ,
+ .p3372 ( optlc_net_3392 ) , .p3373 ( optlc_net_3393 ) ,
+ .p3374 ( optlc_net_3394 ) , .p3375 ( optlc_net_3395 ) ,
+ .p3376 ( optlc_net_3396 ) , .p3377 ( optlc_net_3397 ) ,
+ .p3378 ( optlc_net_3398 ) , .p3379 ( optlc_net_3399 ) ,
+ .p3380 ( optlc_net_3400 ) , .p3381 ( optlc_net_3401 ) ,
+ .p3382 ( optlc_net_3402 ) , .p3383 ( optlc_net_3403 ) ,
+ .p3384 ( optlc_net_3404 ) , .p3385 ( optlc_net_3405 ) ,
+ .p3386 ( optlc_net_3406 ) , .p3387 ( optlc_net_3407 ) ,
+ .p3388 ( optlc_net_3408 ) , .p3389 ( optlc_net_3409 ) ,
+ .p3390 ( optlc_net_3410 ) , .p3391 ( optlc_net_3411 ) ,
+ .p3392 ( optlc_net_3412 ) , .p3393 ( optlc_net_3413 ) ,
+ .p3394 ( optlc_net_3414 ) , .p3395 ( optlc_net_3415 ) ,
+ .p3396 ( optlc_net_3416 ) , .p3397 ( optlc_net_3417 ) ,
+ .p3398 ( optlc_net_3418 ) , .p3399 ( optlc_net_3419 ) ,
+ .p3400 ( optlc_net_3420 ) , .p3401 ( optlc_net_3421 ) ,
+ .p3402 ( optlc_net_3422 ) , .p3403 ( optlc_net_3423 ) ,
+ .p3404 ( optlc_net_3424 ) , .p3405 ( optlc_net_3425 ) ,
+ .p3406 ( optlc_net_3426 ) , .p3407 ( optlc_net_3427 ) ,
+ .p3408 ( optlc_net_3428 ) , .p3409 ( optlc_net_3429 ) ,
+ .p3410 ( optlc_net_3430 ) , .p3411 ( optlc_net_3431 ) ,
+ .p3412 ( optlc_net_3432 ) , .p3413 ( optlc_net_3433 ) ,
+ .p3414 ( optlc_net_3434 ) , .p3415 ( optlc_net_3435 ) ,
+ .p3416 ( optlc_net_3436 ) , .p3417 ( optlc_net_3437 ) ,
+ .p3418 ( optlc_net_3438 ) , .p3419 ( optlc_net_3439 ) ,
+ .p3420 ( optlc_net_3440 ) , .p3421 ( optlc_net_3441 ) ,
+ .p3422 ( optlc_net_3442 ) , .p3423 ( optlc_net_3443 ) ,
+ .p3424 ( optlc_net_3444 ) , .p3425 ( optlc_net_3445 ) ,
+ .p3426 ( optlc_net_3446 ) , .p3427 ( optlc_net_3447 ) ,
+ .p3428 ( optlc_net_3448 ) , .p3429 ( optlc_net_3449 ) ,
+ .p3430 ( optlc_net_3450 ) , .p3431 ( optlc_net_3451 ) ,
+ .p3432 ( optlc_net_3452 ) , .p3433 ( optlc_net_3453 ) ,
+ .p3434 ( optlc_net_3454 ) , .p3435 ( optlc_net_3455 ) ,
+ .p3436 ( optlc_net_3456 ) , .p3437 ( optlc_net_3457 ) ,
+ .p3438 ( optlc_net_3458 ) , .p3439 ( optlc_net_3459 ) ,
+ .p3440 ( optlc_net_3460 ) , .p3441 ( optlc_net_3461 ) ,
+ .p3442 ( optlc_net_3462 ) , .p3443 ( optlc_net_3463 ) ,
+ .p3444 ( optlc_net_3464 ) , .p3445 ( optlc_net_3465 ) ,
+ .p3446 ( optlc_net_3466 ) , .p3447 ( optlc_net_3467 ) ,
+ .p3448 ( optlc_net_3468 ) , .p3449 ( optlc_net_3469 ) ,
+ .p3450 ( optlc_net_3470 ) , .p3451 ( optlc_net_3471 ) ,
+ .p3452 ( optlc_net_3472 ) , .p3453 ( optlc_net_3473 ) ,
+ .p3454 ( optlc_net_3474 ) , .p3455 ( optlc_net_3475 ) ,
+ .p3456 ( optlc_net_3476 ) , .p3457 ( optlc_net_3477 ) ,
+ .p3458 ( optlc_net_3478 ) , .p3459 ( optlc_net_3479 ) ,
+ .p3460 ( optlc_net_3480 ) , .p3461 ( optlc_net_3481 ) ,
+ .p3462 ( optlc_net_3482 ) , .p3463 ( optlc_net_3483 ) ,
+ .p3464 ( optlc_net_3484 ) , .p3465 ( optlc_net_3485 ) ,
+ .p3466 ( optlc_net_3486 ) , .p3467 ( optlc_net_3487 ) ,
+ .p3468 ( optlc_net_3488 ) , .p3469 ( optlc_net_3489 ) ,
+ .p3470 ( optlc_net_3490 ) , .p3471 ( optlc_net_3491 ) ,
+ .p3472 ( optlc_net_3492 ) , .p3473 ( optlc_net_3493 ) ,
+ .p3474 ( optlc_net_3494 ) , .p3475 ( optlc_net_3495 ) ,
+ .p3476 ( optlc_net_3496 ) , .p3477 ( optlc_net_3497 ) ,
+ .p3478 ( optlc_net_3498 ) , .p3479 ( optlc_net_3499 ) ,
+ .p3480 ( optlc_net_3500 ) , .p3481 ( optlc_net_3501 ) ,
+ .p3482 ( optlc_net_3502 ) , .p3483 ( optlc_net_3503 ) ,
+ .p3484 ( optlc_net_3504 ) , .p3485 ( optlc_net_3505 ) ,
+ .p3486 ( optlc_net_3506 ) , .p3487 ( optlc_net_3507 ) ,
+ .p3488 ( optlc_net_3508 ) , .p3489 ( optlc_net_3509 ) ,
+ .p3490 ( optlc_net_3510 ) , .p3491 ( optlc_net_3511 ) ,
+ .p3492 ( optlc_net_3512 ) , .p3493 ( optlc_net_3513 ) ,
+ .p3494 ( optlc_net_3514 ) , .p3495 ( optlc_net_3515 ) ,
+ .p3496 ( optlc_net_3516 ) , .p3497 ( optlc_net_3517 ) ,
+ .p3498 ( optlc_net_3518 ) , .p3499 ( optlc_net_3519 ) ,
+ .p3500 ( optlc_net_3520 ) , .p3501 ( optlc_net_3521 ) ,
+ .p3502 ( optlc_net_3522 ) , .p3503 ( optlc_net_3523 ) ,
+ .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) ,
+ .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) ,
+ .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) ,
+ .p3510 ( optlc_net_3530 ) , .p3511 ( optlc_net_3531 ) ,
+ .p3512 ( optlc_net_3532 ) , .p3513 ( optlc_net_3533 ) ,
+ .p3514 ( optlc_net_3534 ) , .p3515 ( optlc_net_3535 ) ,
+ .p3516 ( optlc_net_3536 ) , .p3517 ( optlc_net_3537 ) ,
+ .p3518 ( optlc_net_3538 ) , .p3519 ( optlc_net_3539 ) ,
+ .p3520 ( optlc_net_3540 ) , .p3521 ( optlc_net_3541 ) ,
+ .p3522 ( optlc_net_3542 ) , .p3523 ( optlc_net_3543 ) ,
+ .p3524 ( optlc_net_3544 ) , .p3525 ( optlc_net_3545 ) ,
+ .p3526 ( optlc_net_3546 ) , .p3527 ( optlc_net_3547 ) ,
+ .p3528 ( optlc_net_3548 ) , .p3529 ( optlc_net_3549 ) ,
+ .p3530 ( optlc_net_3550 ) , .p3531 ( optlc_net_3551 ) ,
+ .p3532 ( optlc_net_3552 ) , .p3533 ( optlc_net_3553 ) ,
+ .p3534 ( optlc_net_3554 ) , .p3535 ( optlc_net_3555 ) ,
+ .p3536 ( optlc_net_3556 ) , .p3537 ( optlc_net_3557 ) ,
+ .p3538 ( optlc_net_3558 ) , .p3539 ( optlc_net_3559 ) ,
+ .p3540 ( optlc_net_3560 ) , .p3541 ( optlc_net_3561 ) ,
+ .p3542 ( optlc_net_3562 ) , .p3543 ( optlc_net_3563 ) ,
+ .p3544 ( optlc_net_3564 ) , .p3545 ( optlc_net_3565 ) ,
+ .p3546 ( optlc_net_3566 ) , .p3547 ( optlc_net_3567 ) ,
+ .p3548 ( optlc_net_3568 ) , .p3549 ( optlc_net_3569 ) ,
+ .p3550 ( optlc_net_3570 ) , .p3551 ( optlc_net_3571 ) ,
+ .p3552 ( optlc_net_3572 ) , .p3553 ( optlc_net_3573 ) ,
+ .p3554 ( optlc_net_3574 ) , .p3555 ( optlc_net_3575 ) ,
+ .p3556 ( optlc_net_3576 ) , .p3557 ( optlc_net_3577 ) ,
+ .p3558 ( optlc_net_3578 ) , .p3559 ( optlc_net_3579 ) ,
+ .p3560 ( optlc_net_3580 ) , .p3561 ( optlc_net_3581 ) ,
+ .p3562 ( optlc_net_3582 ) , .p3563 ( optlc_net_3583 ) ,
+ .p3564 ( optlc_net_3584 ) , .p3565 ( optlc_net_3585 ) ,
+ .p3566 ( optlc_net_3586 ) , .p3567 ( optlc_net_3587 ) ,
+ .p3568 ( optlc_net_3588 ) , .p3569 ( optlc_net_3589 ) ,
+ .p3570 ( optlc_net_3590 ) , .p3571 ( optlc_net_3591 ) ,
+ .p3572 ( optlc_net_3592 ) , .p3573 ( optlc_net_3593 ) ,
+ .p3574 ( optlc_net_3594 ) , .p3575 ( optlc_net_3595 ) ,
+ .p3576 ( optlc_net_3596 ) , .p3577 ( optlc_net_3597 ) ,
+ .p3578 ( optlc_net_3598 ) , .p3579 ( optlc_net_3599 ) ,
+ .p3580 ( optlc_net_3600 ) , .p3581 ( optlc_net_3601 ) ,
+ .p3582 ( optlc_net_3602 ) , .p3583 ( optlc_net_3603 ) ,
+ .p3584 ( optlc_net_3604 ) , .p3585 ( optlc_net_3605 ) ,
+ .p3586 ( optlc_net_3606 ) , .p3587 ( optlc_net_3607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( io_oeb[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( io_oeb[1] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( io_oeb[2] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( io_oeb[3] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .HI ( io_oeb[12] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .HI ( io_oeb[25] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .HI ( io_oeb[26] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) ,
+ .HI ( io_oeb[36] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_10 ) ,
+ .HI ( io_oeb[37] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_39 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_40 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_41 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_42 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_43 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_44 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_46 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_47 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_48 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_74 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( optlc_net_75 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( optlc_net_76 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( optlc_net_77 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_79 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( optlc_net_78 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_80 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( optlc_net_79 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_81 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( optlc_net_80 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_82 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( optlc_net_81 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( optlc_net_82 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( optlc_net_83 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( optlc_net_84 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_86 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( optlc_net_85 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_87 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_87 ( .LO ( optlc_net_86 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( optlc_net_87 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( optlc_net_88 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( optlc_net_89 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( optlc_net_90 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( optlc_net_91 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( optlc_net_92 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( optlc_net_93 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( optlc_net_94 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( optlc_net_95 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( optlc_net_96 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( optlc_net_97 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( optlc_net_98 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( optlc_net_99 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( optlc_net_100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( optlc_net_101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( optlc_net_102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( optlc_net_103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( optlc_net_104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( optlc_net_105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( optlc_net_106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( optlc_net_107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( optlc_net_108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( optlc_net_109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( optlc_net_110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( optlc_net_111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( optlc_net_112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( optlc_net_113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( optlc_net_114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( optlc_net_115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( optlc_net_116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( optlc_net_117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( optlc_net_118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( optlc_net_119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( optlc_net_120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( optlc_net_121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( optlc_net_122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( optlc_net_123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( optlc_net_124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( optlc_net_125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( optlc_net_126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( optlc_net_127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( optlc_net_128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( optlc_net_129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( optlc_net_130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( optlc_net_131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( optlc_net_132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( optlc_net_133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( optlc_net_134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( optlc_net_135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( optlc_net_136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( optlc_net_137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( optlc_net_138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( optlc_net_139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( optlc_net_140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( optlc_net_141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( optlc_net_142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( optlc_net_143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( optlc_net_144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( optlc_net_145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( optlc_net_146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( optlc_net_147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( optlc_net_148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( optlc_net_149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( optlc_net_150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( optlc_net_151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( optlc_net_152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( optlc_net_153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( optlc_net_154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( optlc_net_155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( optlc_net_156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( optlc_net_157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( optlc_net_158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( optlc_net_159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( optlc_net_160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( optlc_net_161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_163 ( .LO ( optlc_net_162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( optlc_net_163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( optlc_net_164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( optlc_net_165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( optlc_net_166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( optlc_net_167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_169 ( .LO ( optlc_net_168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( optlc_net_169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( optlc_net_170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( optlc_net_171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( optlc_net_172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( optlc_net_173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( optlc_net_174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( optlc_net_175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( optlc_net_176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( optlc_net_177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( optlc_net_178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( optlc_net_179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( optlc_net_180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( optlc_net_181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_183 ( .LO ( optlc_net_182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( optlc_net_183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( optlc_net_184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( optlc_net_185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( optlc_net_186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( optlc_net_187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( optlc_net_188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( optlc_net_189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( optlc_net_190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( optlc_net_191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( optlc_net_192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( optlc_net_193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( optlc_net_194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( optlc_net_195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( optlc_net_196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_198 ( .LO ( optlc_net_197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( optlc_net_198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( optlc_net_199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( optlc_net_200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( optlc_net_201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( optlc_net_202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( optlc_net_203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( optlc_net_204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( optlc_net_205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( optlc_net_206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( optlc_net_207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( optlc_net_208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( optlc_net_209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( optlc_net_210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( optlc_net_211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( optlc_net_212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( optlc_net_213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( optlc_net_214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( optlc_net_215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( optlc_net_216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( optlc_net_217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( optlc_net_218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( optlc_net_219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( optlc_net_220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( optlc_net_221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( optlc_net_222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( optlc_net_223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( optlc_net_224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( optlc_net_225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( optlc_net_226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( optlc_net_227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( optlc_net_228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( optlc_net_229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_231 ( .LO ( optlc_net_230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( optlc_net_231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( optlc_net_232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_234 ( .LO ( optlc_net_233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( optlc_net_234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_236 ( .LO ( optlc_net_235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( optlc_net_236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_238 ( .LO ( optlc_net_237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( optlc_net_238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_240 ( .LO ( optlc_net_239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_241 ( .LO ( optlc_net_240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_242 ( .LO ( optlc_net_241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_243 ( .LO ( optlc_net_242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_244 ( .LO ( optlc_net_243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_245 ( .LO ( optlc_net_244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_246 ( .LO ( optlc_net_245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_247 ( .LO ( optlc_net_246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_248 ( .LO ( optlc_net_247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_249 ( .LO ( optlc_net_248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_250 ( .LO ( optlc_net_249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_251 ( .LO ( optlc_net_250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_252 ( .LO ( optlc_net_251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_253 ( .LO ( optlc_net_252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_254 ( .LO ( optlc_net_253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_255 ( .LO ( optlc_net_254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_256 ( .LO ( optlc_net_255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_257 ( .LO ( optlc_net_256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_258 ( .LO ( optlc_net_257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_259 ( .LO ( optlc_net_258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_260 ( .LO ( optlc_net_259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_261 ( .LO ( optlc_net_260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_262 ( .LO ( optlc_net_261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_263 ( .LO ( optlc_net_262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_264 ( .LO ( optlc_net_263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_265 ( .LO ( optlc_net_264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_266 ( .LO ( optlc_net_265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_267 ( .LO ( optlc_net_266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_268 ( .LO ( optlc_net_267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_269 ( .LO ( optlc_net_268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_274 ( .LO ( optlc_net_273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_280 ( .LO ( optlc_net_279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_284 ( .LO ( optlc_net_283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_295 ( .LO ( optlc_net_294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_298 ( .LO ( optlc_net_297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_311 ( .LO ( optlc_net_310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_313 ( .LO ( optlc_net_312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_315 ( .LO ( optlc_net_314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_327 ( .LO ( optlc_net_326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_330 ( .LO ( optlc_net_329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_334 ( .LO ( optlc_net_333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_336 ( .LO ( optlc_net_335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_342 ( .LO ( optlc_net_341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_351 ( .LO ( optlc_net_350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_353 ( .LO ( optlc_net_352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_355 ( .LO ( optlc_net_354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_365 ( .LO ( optlc_net_363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_367 ( .LO ( optlc_net_365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_401 ( .LO ( optlc_net_399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_403 ( .LO ( optlc_net_401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_413 ( .LO ( optlc_net_411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_415 ( .LO ( optlc_net_413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_773 ( .LO ( optlc_net_767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_935 ( .LO ( optlc_net_926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_943 ( .LO ( optlc_net_932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_960 ( .LO ( optlc_net_948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_966 ( .LO ( optlc_net_954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_967 ( .LO ( optlc_net_955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_971 ( .LO ( optlc_net_959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_986 ( .LO ( optlc_net_972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_996 ( .LO ( optlc_net_981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1009 ( .LO ( optlc_net_992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1011 ( .LO ( optlc_net_994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1012 ( .LO ( optlc_net_995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1014 ( .LO ( optlc_net_997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1015 ( .LO ( optlc_net_998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1016 ( .LO ( optlc_net_999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1017 ( .LO ( optlc_net_1000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1018 ( .LO ( optlc_net_1001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1019 ( .LO ( optlc_net_1002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1020 ( .LO ( optlc_net_1003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1021 ( .LO ( optlc_net_1004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1022 ( .LO ( optlc_net_1005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1023 ( .LO ( optlc_net_1006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1024 ( .LO ( optlc_net_1007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1025 ( .LO ( optlc_net_1008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1026 ( .LO ( optlc_net_1009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1027 ( .LO ( optlc_net_1010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1028 ( .LO ( optlc_net_1011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1029 ( .LO ( optlc_net_1012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1030 ( .LO ( optlc_net_1013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1031 ( .LO ( optlc_net_1014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1032 ( .LO ( optlc_net_1015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1033 ( .LO ( optlc_net_1016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1034 ( .LO ( optlc_net_1017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1035 ( .LO ( optlc_net_1018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1036 ( .LO ( optlc_net_1019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1037 ( .LO ( optlc_net_1020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1038 ( .LO ( optlc_net_1021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1039 ( .LO ( optlc_net_1022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1040 ( .LO ( optlc_net_1023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1041 ( .LO ( optlc_net_1024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1042 ( .LO ( optlc_net_1025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1043 ( .LO ( optlc_net_1026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1044 ( .LO ( optlc_net_1027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1045 ( .LO ( optlc_net_1028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1046 ( .LO ( optlc_net_1029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1047 ( .LO ( optlc_net_1030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1048 ( .LO ( optlc_net_1031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1049 ( .LO ( optlc_net_1032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1050 ( .LO ( optlc_net_1033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1051 ( .LO ( optlc_net_1034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1052 ( .LO ( optlc_net_1035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1053 ( .LO ( optlc_net_1036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1054 ( .LO ( optlc_net_1037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1055 ( .LO ( optlc_net_1038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1056 ( .LO ( optlc_net_1039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1057 ( .LO ( optlc_net_1040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1058 ( .LO ( optlc_net_1041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1059 ( .LO ( optlc_net_1042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1060 ( .LO ( optlc_net_1043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1061 ( .LO ( optlc_net_1044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1062 ( .LO ( optlc_net_1045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1063 ( .LO ( optlc_net_1046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1065 ( .LO ( optlc_net_1047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1066 ( .LO ( optlc_net_1048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1067 ( .LO ( optlc_net_1049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1068 ( .LO ( optlc_net_1050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1069 ( .LO ( optlc_net_1051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1070 ( .LO ( optlc_net_1052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1071 ( .LO ( optlc_net_1053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1072 ( .LO ( optlc_net_1054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1073 ( .LO ( optlc_net_1055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1074 ( .LO ( optlc_net_1056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1075 ( .LO ( optlc_net_1057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1076 ( .LO ( optlc_net_1058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1077 ( .LO ( optlc_net_1059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1078 ( .LO ( optlc_net_1060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1079 ( .LO ( optlc_net_1061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1080 ( .LO ( optlc_net_1062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1081 ( .LO ( optlc_net_1063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1082 ( .LO ( optlc_net_1064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1083 ( .LO ( optlc_net_1065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1084 ( .LO ( optlc_net_1066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1085 ( .LO ( optlc_net_1067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1086 ( .LO ( optlc_net_1068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1087 ( .LO ( optlc_net_1069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1088 ( .LO ( optlc_net_1070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1089 ( .LO ( optlc_net_1071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1090 ( .LO ( optlc_net_1072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1091 ( .LO ( optlc_net_1073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1093 ( .LO ( optlc_net_1074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1094 ( .LO ( optlc_net_1075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1095 ( .LO ( optlc_net_1076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1096 ( .LO ( optlc_net_1077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1097 ( .LO ( optlc_net_1078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1098 ( .LO ( optlc_net_1079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1100 ( .LO ( optlc_net_1080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1101 ( .LO ( optlc_net_1081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1102 ( .LO ( optlc_net_1082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1103 ( .LO ( optlc_net_1083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1104 ( .LO ( optlc_net_1084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1105 ( .LO ( optlc_net_1085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1106 ( .LO ( optlc_net_1086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1108 ( .LO ( optlc_net_1087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1109 ( .LO ( optlc_net_1088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1110 ( .LO ( optlc_net_1089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1111 ( .LO ( optlc_net_1090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1112 ( .LO ( optlc_net_1091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1113 ( .LO ( optlc_net_1092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1114 ( .LO ( optlc_net_1093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1115 ( .LO ( optlc_net_1094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1116 ( .LO ( optlc_net_1095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1117 ( .LO ( optlc_net_1096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1118 ( .LO ( optlc_net_1097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1119 ( .LO ( optlc_net_1098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1120 ( .LO ( optlc_net_1099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1121 ( .LO ( optlc_net_1100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1122 ( .LO ( optlc_net_1101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1123 ( .LO ( optlc_net_1102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1124 ( .LO ( optlc_net_1103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1125 ( .LO ( optlc_net_1104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1126 ( .LO ( optlc_net_1105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1127 ( .LO ( optlc_net_1106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1128 ( .LO ( optlc_net_1107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1129 ( .LO ( optlc_net_1108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1130 ( .LO ( optlc_net_1109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1131 ( .LO ( optlc_net_1110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1132 ( .LO ( optlc_net_1111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1133 ( .LO ( optlc_net_1112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1134 ( .LO ( optlc_net_1113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1135 ( .LO ( optlc_net_1114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1137 ( .LO ( optlc_net_1115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1138 ( .LO ( optlc_net_1116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1139 ( .LO ( optlc_net_1117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1140 ( .LO ( optlc_net_1118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1141 ( .LO ( optlc_net_1119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1142 ( .LO ( optlc_net_1120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1143 ( .LO ( optlc_net_1121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1144 ( .LO ( optlc_net_1122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1145 ( .LO ( optlc_net_1123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1146 ( .LO ( optlc_net_1124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1147 ( .LO ( optlc_net_1125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1149 ( .LO ( optlc_net_1126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1150 ( .LO ( optlc_net_1127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1151 ( .LO ( optlc_net_1128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1152 ( .LO ( optlc_net_1129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1153 ( .LO ( optlc_net_1130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1154 ( .LO ( optlc_net_1131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1155 ( .LO ( optlc_net_1132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1156 ( .LO ( optlc_net_1133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1157 ( .LO ( optlc_net_1134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1158 ( .LO ( optlc_net_1135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1160 ( .LO ( optlc_net_1136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1161 ( .LO ( optlc_net_1137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1162 ( .LO ( optlc_net_1138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1164 ( .LO ( optlc_net_1139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1165 ( .LO ( optlc_net_1140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1166 ( .LO ( optlc_net_1141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1167 ( .LO ( optlc_net_1142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1168 ( .LO ( optlc_net_1143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1169 ( .LO ( optlc_net_1144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1171 ( .LO ( optlc_net_1145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1173 ( .LO ( optlc_net_1146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1174 ( .LO ( optlc_net_1147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1175 ( .LO ( optlc_net_1148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1176 ( .LO ( optlc_net_1149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1177 ( .LO ( optlc_net_1150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1178 ( .LO ( optlc_net_1151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1179 ( .LO ( optlc_net_1152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1180 ( .LO ( optlc_net_1153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1181 ( .LO ( optlc_net_1154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1182 ( .LO ( optlc_net_1155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1183 ( .LO ( optlc_net_1156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1184 ( .LO ( optlc_net_1157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1185 ( .LO ( optlc_net_1158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1186 ( .LO ( optlc_net_1159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1188 ( .LO ( optlc_net_1160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1190 ( .LO ( optlc_net_1161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1191 ( .LO ( optlc_net_1162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1193 ( .LO ( optlc_net_1163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1194 ( .LO ( optlc_net_1164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1195 ( .LO ( optlc_net_1165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1196 ( .LO ( optlc_net_1166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1197 ( .LO ( optlc_net_1167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1198 ( .LO ( optlc_net_1168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1200 ( .LO ( optlc_net_1169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1201 ( .LO ( optlc_net_1170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1202 ( .LO ( optlc_net_1171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1203 ( .LO ( optlc_net_1172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1204 ( .LO ( optlc_net_1173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1205 ( .LO ( optlc_net_1174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1206 ( .LO ( optlc_net_1175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1207 ( .LO ( optlc_net_1176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1208 ( .LO ( optlc_net_1177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1210 ( .LO ( optlc_net_1178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1211 ( .LO ( optlc_net_1179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1213 ( .LO ( optlc_net_1180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1214 ( .LO ( optlc_net_1181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1215 ( .LO ( optlc_net_1182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1216 ( .LO ( optlc_net_1183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1218 ( .LO ( optlc_net_1184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1219 ( .LO ( optlc_net_1185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1220 ( .LO ( optlc_net_1186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1221 ( .LO ( optlc_net_1187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1222 ( .LO ( optlc_net_1188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1224 ( .LO ( optlc_net_1189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1225 ( .LO ( optlc_net_1190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1226 ( .LO ( optlc_net_1191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1227 ( .LO ( optlc_net_1192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1228 ( .LO ( optlc_net_1193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1229 ( .LO ( optlc_net_1194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1230 ( .LO ( optlc_net_1195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1232 ( .LO ( optlc_net_1196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1233 ( .LO ( optlc_net_1197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1235 ( .LO ( optlc_net_1198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1236 ( .LO ( optlc_net_1199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1238 ( .LO ( optlc_net_1200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1240 ( .LO ( optlc_net_1201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1241 ( .LO ( optlc_net_1202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1242 ( .LO ( optlc_net_1203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1244 ( .LO ( optlc_net_1204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1245 ( .LO ( optlc_net_1205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1246 ( .LO ( optlc_net_1206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1247 ( .LO ( optlc_net_1207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1248 ( .LO ( optlc_net_1208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1249 ( .LO ( optlc_net_1209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1250 ( .LO ( optlc_net_1210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1252 ( .LO ( optlc_net_1211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1253 ( .LO ( optlc_net_1212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1254 ( .LO ( optlc_net_1213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1256 ( .LO ( optlc_net_1214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1257 ( .LO ( optlc_net_1215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1258 ( .LO ( optlc_net_1216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1259 ( .LO ( optlc_net_1217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1260 ( .LO ( optlc_net_1218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1261 ( .LO ( optlc_net_1219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1263 ( .LO ( optlc_net_1220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1265 ( .LO ( optlc_net_1221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1266 ( .LO ( optlc_net_1222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1267 ( .LO ( optlc_net_1223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1269 ( .LO ( optlc_net_1224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1271 ( .LO ( optlc_net_1225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1272 ( .LO ( optlc_net_1226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1274 ( .LO ( optlc_net_1227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1275 ( .LO ( optlc_net_1228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1276 ( .LO ( optlc_net_1229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1277 ( .LO ( optlc_net_1230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1279 ( .LO ( optlc_net_1231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1280 ( .LO ( optlc_net_1232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1282 ( .LO ( optlc_net_1233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1284 ( .LO ( optlc_net_1234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1286 ( .LO ( optlc_net_1235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1288 ( .LO ( optlc_net_1236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1289 ( .LO ( optlc_net_1237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1290 ( .LO ( optlc_net_1238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1291 ( .LO ( optlc_net_1239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1292 ( .LO ( optlc_net_1240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1293 ( .LO ( optlc_net_1241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1295 ( .LO ( optlc_net_1242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1297 ( .LO ( optlc_net_1243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1298 ( .LO ( optlc_net_1244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1300 ( .LO ( optlc_net_1245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1301 ( .LO ( optlc_net_1246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1302 ( .LO ( optlc_net_1247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1304 ( .LO ( optlc_net_1248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1305 ( .LO ( optlc_net_1249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1307 ( .LO ( optlc_net_1250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1308 ( .LO ( optlc_net_1251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1309 ( .LO ( optlc_net_1252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1310 ( .LO ( optlc_net_1253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1311 ( .LO ( optlc_net_1254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1313 ( .LO ( optlc_net_1255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1315 ( .LO ( optlc_net_1256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1316 ( .LO ( optlc_net_1257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1317 ( .LO ( optlc_net_1258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1319 ( .LO ( optlc_net_1259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1321 ( .LO ( optlc_net_1260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1323 ( .LO ( optlc_net_1261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1324 ( .LO ( optlc_net_1262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1326 ( .LO ( optlc_net_1263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1327 ( .LO ( optlc_net_1264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1329 ( .LO ( optlc_net_1265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1330 ( .LO ( optlc_net_1266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1331 ( .LO ( optlc_net_1267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1333 ( .LO ( optlc_net_1268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1335 ( .LO ( optlc_net_1269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1337 ( .LO ( optlc_net_1270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1338 ( .LO ( optlc_net_1271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1339 ( .LO ( optlc_net_1272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1341 ( .LO ( optlc_net_1273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1342 ( .LO ( optlc_net_1274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1343 ( .LO ( optlc_net_1275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1344 ( .LO ( optlc_net_1276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1345 ( .LO ( optlc_net_1277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1346 ( .LO ( optlc_net_1278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1347 ( .LO ( optlc_net_1279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1348 ( .LO ( optlc_net_1280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1349 ( .LO ( optlc_net_1281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1350 ( .LO ( optlc_net_1282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1351 ( .LO ( optlc_net_1283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1352 ( .LO ( optlc_net_1284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1353 ( .LO ( optlc_net_1285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1354 ( .LO ( optlc_net_1286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1355 ( .LO ( optlc_net_1287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1356 ( .LO ( optlc_net_1288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1357 ( .LO ( optlc_net_1289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1358 ( .LO ( optlc_net_1290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1359 ( .LO ( optlc_net_1291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1360 ( .LO ( optlc_net_1292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1361 ( .LO ( optlc_net_1293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1362 ( .LO ( optlc_net_1294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1363 ( .LO ( optlc_net_1295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1364 ( .LO ( optlc_net_1296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1365 ( .LO ( optlc_net_1297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1366 ( .LO ( optlc_net_1298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1367 ( .LO ( optlc_net_1299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1368 ( .LO ( optlc_net_1300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1369 ( .LO ( optlc_net_1301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1370 ( .LO ( optlc_net_1302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1371 ( .LO ( optlc_net_1303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1372 ( .LO ( optlc_net_1304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1373 ( .LO ( optlc_net_1305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1374 ( .LO ( optlc_net_1306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1375 ( .LO ( optlc_net_1307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1376 ( .LO ( optlc_net_1308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1377 ( .LO ( optlc_net_1309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1378 ( .LO ( optlc_net_1310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1379 ( .LO ( optlc_net_1311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1380 ( .LO ( optlc_net_1312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1381 ( .LO ( optlc_net_1313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1382 ( .LO ( optlc_net_1314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1383 ( .LO ( optlc_net_1315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1384 ( .LO ( optlc_net_1316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1385 ( .LO ( optlc_net_1317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1386 ( .LO ( optlc_net_1318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1387 ( .LO ( optlc_net_1319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1388 ( .LO ( optlc_net_1320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1389 ( .LO ( optlc_net_1321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1390 ( .LO ( optlc_net_1322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1391 ( .LO ( optlc_net_1323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1392 ( .LO ( optlc_net_1324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1393 ( .LO ( optlc_net_1325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1394 ( .LO ( optlc_net_1326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1395 ( .LO ( optlc_net_1327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1396 ( .LO ( optlc_net_1328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1397 ( .LO ( optlc_net_1329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1398 ( .LO ( optlc_net_1330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1399 ( .LO ( optlc_net_1331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1400 ( .LO ( optlc_net_1332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1401 ( .LO ( optlc_net_1333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1402 ( .LO ( optlc_net_1334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1403 ( .LO ( optlc_net_1335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1404 ( .LO ( optlc_net_1336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1405 ( .LO ( optlc_net_1337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1406 ( .LO ( optlc_net_1338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1407 ( .LO ( optlc_net_1339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1408 ( .LO ( optlc_net_1340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1409 ( .LO ( optlc_net_1341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1410 ( .LO ( optlc_net_1342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1411 ( .LO ( optlc_net_1343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1412 ( .LO ( optlc_net_1344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1413 ( .LO ( optlc_net_1345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1414 ( .LO ( optlc_net_1346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1415 ( .LO ( optlc_net_1347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1416 ( .LO ( optlc_net_1348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1417 ( .LO ( optlc_net_1349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1418 ( .LO ( optlc_net_1350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1419 ( .LO ( optlc_net_1351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1420 ( .LO ( optlc_net_1352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1421 ( .LO ( optlc_net_1353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1422 ( .LO ( optlc_net_1354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1423 ( .LO ( optlc_net_1355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1424 ( .LO ( optlc_net_1356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1426 ( .LO ( optlc_net_1357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1427 ( .LO ( optlc_net_1358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1428 ( .LO ( optlc_net_1359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1429 ( .LO ( optlc_net_1360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1430 ( .LO ( optlc_net_1361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1431 ( .LO ( optlc_net_1362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1432 ( .LO ( optlc_net_1363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1433 ( .LO ( optlc_net_1364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1434 ( .LO ( optlc_net_1365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1435 ( .LO ( optlc_net_1366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1436 ( .LO ( optlc_net_1367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1437 ( .LO ( optlc_net_1368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1438 ( .LO ( optlc_net_1369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1439 ( .LO ( optlc_net_1370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1440 ( .LO ( optlc_net_1371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1441 ( .LO ( optlc_net_1372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1442 ( .LO ( optlc_net_1373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1443 ( .LO ( optlc_net_1374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1444 ( .LO ( optlc_net_1375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1445 ( .LO ( optlc_net_1376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1446 ( .LO ( optlc_net_1377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1447 ( .LO ( optlc_net_1378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1448 ( .LO ( optlc_net_1379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1449 ( .LO ( optlc_net_1380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1450 ( .LO ( optlc_net_1381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1451 ( .LO ( optlc_net_1382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1452 ( .LO ( optlc_net_1383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1453 ( .LO ( optlc_net_1384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1454 ( .LO ( optlc_net_1385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1455 ( .LO ( optlc_net_1386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1456 ( .LO ( optlc_net_1387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1457 ( .LO ( optlc_net_1388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1458 ( .LO ( optlc_net_1389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1459 ( .LO ( optlc_net_1390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1461 ( .LO ( optlc_net_1391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1466 ( .LO ( optlc_net_1395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1467 ( .LO ( optlc_net_1396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1469 ( .LO ( optlc_net_1397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1470 ( .LO ( optlc_net_1398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1471 ( .LO ( optlc_net_1399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1473 ( .LO ( optlc_net_1401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1474 ( .LO ( optlc_net_1402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1475 ( .LO ( optlc_net_1403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1477 ( .LO ( optlc_net_1404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1478 ( .LO ( optlc_net_1405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1479 ( .LO ( optlc_net_1406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1480 ( .LO ( optlc_net_1407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1481 ( .LO ( optlc_net_1408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1482 ( .LO ( optlc_net_1409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1485 ( .LO ( optlc_net_1412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1487 ( .LO ( optlc_net_1413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1488 ( .LO ( optlc_net_1414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1491 ( .LO ( optlc_net_1417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1492 ( .LO ( optlc_net_1418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1494 ( .LO ( optlc_net_1419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1495 ( .LO ( optlc_net_1420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1496 ( .LO ( optlc_net_1421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1497 ( .LO ( optlc_net_1422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1498 ( .LO ( optlc_net_1423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1500 ( .LO ( optlc_net_1424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1501 ( .LO ( optlc_net_1425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1503 ( .LO ( optlc_net_1426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1504 ( .LO ( optlc_net_1427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1505 ( .LO ( optlc_net_1428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1507 ( .LO ( optlc_net_1429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1508 ( .LO ( optlc_net_1430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1509 ( .LO ( optlc_net_1431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1510 ( .LO ( optlc_net_1432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1511 ( .LO ( optlc_net_1433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1513 ( .LO ( optlc_net_1434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1514 ( .LO ( optlc_net_1435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1515 ( .LO ( optlc_net_1436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1517 ( .LO ( optlc_net_1437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1518 ( .LO ( optlc_net_1438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1519 ( .LO ( optlc_net_1439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1521 ( .LO ( optlc_net_1440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1522 ( .LO ( optlc_net_1441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1523 ( .LO ( optlc_net_1442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1524 ( .LO ( optlc_net_1443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1525 ( .LO ( optlc_net_1444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1526 ( .LO ( optlc_net_1445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1527 ( .LO ( optlc_net_1446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1528 ( .LO ( optlc_net_1447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1529 ( .LO ( optlc_net_1448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1531 ( .LO ( optlc_net_1449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1532 ( .LO ( optlc_net_1450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1533 ( .LO ( optlc_net_1451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1534 ( .LO ( optlc_net_1452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1536 ( .LO ( optlc_net_1453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1537 ( .LO ( optlc_net_1454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1538 ( .LO ( optlc_net_1455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1539 ( .LO ( optlc_net_1456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1540 ( .LO ( optlc_net_1457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1541 ( .LO ( optlc_net_1458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1543 ( .LO ( optlc_net_1459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1545 ( .LO ( optlc_net_1460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1547 ( .LO ( optlc_net_1461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1549 ( .LO ( optlc_net_1462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1550 ( .LO ( optlc_net_1463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1551 ( .LO ( optlc_net_1464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1553 ( .LO ( optlc_net_1465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1555 ( .LO ( optlc_net_1466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1556 ( .LO ( optlc_net_1467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1558 ( .LO ( optlc_net_1468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1560 ( .LO ( optlc_net_1469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1562 ( .LO ( optlc_net_1470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1563 ( .LO ( optlc_net_1471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1564 ( .LO ( optlc_net_1472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1565 ( .LO ( optlc_net_1473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1567 ( .LO ( optlc_net_1474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1568 ( .LO ( optlc_net_1475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1569 ( .LO ( optlc_net_1476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1570 ( .LO ( optlc_net_1477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1571 ( .LO ( optlc_net_1478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1572 ( .LO ( optlc_net_1479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1574 ( .LO ( optlc_net_1480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1575 ( .LO ( optlc_net_1481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1576 ( .LO ( optlc_net_1482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1577 ( .LO ( optlc_net_1483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1579 ( .LO ( optlc_net_1484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1580 ( .LO ( optlc_net_1485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1581 ( .LO ( optlc_net_1486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1582 ( .LO ( optlc_net_1487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1584 ( .LO ( optlc_net_1488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1585 ( .LO ( optlc_net_1489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1587 ( .LO ( optlc_net_1490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1588 ( .LO ( optlc_net_1491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1590 ( .LO ( optlc_net_1492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1592 ( .LO ( optlc_net_1493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1594 ( .LO ( optlc_net_1494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1595 ( .LO ( optlc_net_1495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1597 ( .LO ( optlc_net_1496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1599 ( .LO ( optlc_net_1497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1600 ( .LO ( optlc_net_1498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1601 ( .LO ( optlc_net_1499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1602 ( .LO ( optlc_net_1500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1604 ( .LO ( optlc_net_1501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1605 ( .LO ( optlc_net_1502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1607 ( .LO ( optlc_net_1503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1608 ( .LO ( optlc_net_1504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1610 ( .LO ( optlc_net_1505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1611 ( .LO ( optlc_net_1506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1613 ( .LO ( optlc_net_1507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1614 ( .LO ( optlc_net_1508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1615 ( .LO ( optlc_net_1509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1616 ( .LO ( optlc_net_1510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1619 ( .LO ( optlc_net_1511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1621 ( .LO ( optlc_net_1512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1622 ( .LO ( optlc_net_1513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1623 ( .LO ( optlc_net_1514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1624 ( .LO ( optlc_net_1515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1626 ( .LO ( optlc_net_1516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1627 ( .LO ( optlc_net_1517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1629 ( .LO ( optlc_net_1518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1630 ( .LO ( optlc_net_1519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1631 ( .LO ( optlc_net_1520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1632 ( .LO ( optlc_net_1521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1633 ( .LO ( optlc_net_1522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1634 ( .LO ( optlc_net_1523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1636 ( .LO ( optlc_net_1524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1637 ( .LO ( optlc_net_1525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1639 ( .LO ( optlc_net_1526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1641 ( .LO ( optlc_net_1527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1642 ( .LO ( optlc_net_1528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1644 ( .LO ( optlc_net_1529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1646 ( .LO ( optlc_net_1530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1647 ( .LO ( optlc_net_1531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1648 ( .LO ( optlc_net_1532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1650 ( .LO ( optlc_net_1533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1651 ( .LO ( optlc_net_1534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1652 ( .LO ( optlc_net_1535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1653 ( .LO ( optlc_net_1536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1654 ( .LO ( optlc_net_1537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1655 ( .LO ( optlc_net_1538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1657 ( .LO ( optlc_net_1539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1659 ( .LO ( optlc_net_1540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1660 ( .LO ( optlc_net_1541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1662 ( .LO ( optlc_net_1542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1663 ( .LO ( optlc_net_1543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1665 ( .LO ( optlc_net_1544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1666 ( .LO ( optlc_net_1545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1668 ( .LO ( optlc_net_1546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1670 ( .LO ( optlc_net_1547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1672 ( .LO ( optlc_net_1548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1673 ( .LO ( optlc_net_1549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1675 ( .LO ( optlc_net_1550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1677 ( .LO ( optlc_net_1551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1679 ( .LO ( optlc_net_1552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1681 ( .LO ( optlc_net_1553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1682 ( .LO ( optlc_net_1554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1683 ( .LO ( optlc_net_1555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1685 ( .LO ( optlc_net_1556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1686 ( .LO ( optlc_net_1557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1687 ( .LO ( optlc_net_1558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1689 ( .LO ( optlc_net_1559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1690 ( .LO ( optlc_net_1560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1691 ( .LO ( optlc_net_1561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1692 ( .LO ( optlc_net_1562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1693 ( .LO ( optlc_net_1563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1695 ( .LO ( optlc_net_1564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1697 ( .LO ( optlc_net_1565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1699 ( .LO ( optlc_net_1566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1701 ( .LO ( optlc_net_1567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1703 ( .LO ( optlc_net_1568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1704 ( .LO ( optlc_net_1569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1705 ( .LO ( optlc_net_1570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1706 ( .LO ( optlc_net_1571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1707 ( .LO ( optlc_net_1572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1709 ( .LO ( optlc_net_1573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1711 ( .LO ( optlc_net_1574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1712 ( .LO ( optlc_net_1575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1714 ( .LO ( optlc_net_1576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1715 ( .LO ( optlc_net_1577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1716 ( .LO ( optlc_net_1578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1717 ( .LO ( optlc_net_1579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1719 ( .LO ( optlc_net_1580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1720 ( .LO ( optlc_net_1581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1721 ( .LO ( optlc_net_1582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1723 ( .LO ( optlc_net_1583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1724 ( .LO ( optlc_net_1584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1725 ( .LO ( optlc_net_1585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1726 ( .LO ( optlc_net_1586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1728 ( .LO ( optlc_net_1587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1730 ( .LO ( optlc_net_1588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1732 ( .LO ( optlc_net_1589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1733 ( .LO ( optlc_net_1590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1735 ( .LO ( optlc_net_1591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1737 ( .LO ( optlc_net_1592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1738 ( .LO ( optlc_net_1593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1739 ( .LO ( optlc_net_1594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1741 ( .LO ( optlc_net_1595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1742 ( .LO ( optlc_net_1596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1744 ( .LO ( optlc_net_1597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1746 ( .LO ( optlc_net_1598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1748 ( .LO ( optlc_net_1599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1750 ( .LO ( optlc_net_1600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1751 ( .LO ( optlc_net_1601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1753 ( .LO ( optlc_net_1602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1754 ( .LO ( optlc_net_1603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1755 ( .LO ( optlc_net_1604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1756 ( .LO ( optlc_net_1605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1757 ( .LO ( optlc_net_1606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1758 ( .LO ( optlc_net_1607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1760 ( .LO ( optlc_net_1608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1761 ( .LO ( optlc_net_1609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1762 ( .LO ( optlc_net_1610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1764 ( .LO ( optlc_net_1611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1766 ( .LO ( optlc_net_1612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1767 ( .LO ( optlc_net_1613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1769 ( .LO ( optlc_net_1614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1771 ( .LO ( optlc_net_1615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1772 ( .LO ( optlc_net_1616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1774 ( .LO ( optlc_net_1617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1775 ( .LO ( optlc_net_1618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1777 ( .LO ( optlc_net_1619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1779 ( .LO ( optlc_net_1620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1781 ( .LO ( optlc_net_1621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1783 ( .LO ( optlc_net_1622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1784 ( .LO ( optlc_net_1623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1785 ( .LO ( optlc_net_1624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1786 ( .LO ( optlc_net_1625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1787 ( .LO ( optlc_net_1626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1788 ( .LO ( optlc_net_1627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1789 ( .LO ( optlc_net_1628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1790 ( .LO ( optlc_net_1629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1792 ( .LO ( optlc_net_1630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1794 ( .LO ( optlc_net_1631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1796 ( .LO ( optlc_net_1632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1797 ( .LO ( optlc_net_1633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1798 ( .LO ( optlc_net_1634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1799 ( .LO ( optlc_net_1635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1800 ( .LO ( optlc_net_1636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1801 ( .LO ( optlc_net_1637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1802 ( .LO ( optlc_net_1638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1803 ( .LO ( optlc_net_1639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1804 ( .LO ( optlc_net_1640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1805 ( .LO ( optlc_net_1641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1806 ( .LO ( optlc_net_1642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1807 ( .LO ( optlc_net_1643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1808 ( .LO ( optlc_net_1644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1809 ( .LO ( optlc_net_1645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1810 ( .LO ( optlc_net_1646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1811 ( .LO ( optlc_net_1647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1812 ( .LO ( optlc_net_1648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1813 ( .LO ( optlc_net_1649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1814 ( .LO ( optlc_net_1650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1815 ( .LO ( optlc_net_1651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1816 ( .LO ( optlc_net_1652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1817 ( .LO ( optlc_net_1653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1818 ( .LO ( optlc_net_1654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1819 ( .LO ( optlc_net_1655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1820 ( .LO ( optlc_net_1656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1821 ( .LO ( optlc_net_1657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1822 ( .LO ( optlc_net_1658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1823 ( .LO ( optlc_net_1659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1824 ( .LO ( optlc_net_1660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1825 ( .LO ( optlc_net_1661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1826 ( .LO ( optlc_net_1662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1827 ( .LO ( optlc_net_1663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1828 ( .LO ( optlc_net_1664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1829 ( .LO ( optlc_net_1665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1830 ( .LO ( optlc_net_1666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1831 ( .LO ( optlc_net_1667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1832 ( .LO ( optlc_net_1668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1833 ( .LO ( optlc_net_1669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1834 ( .LO ( optlc_net_1670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1835 ( .LO ( optlc_net_1671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1836 ( .LO ( optlc_net_1672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1837 ( .LO ( optlc_net_1673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1838 ( .LO ( optlc_net_1674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1839 ( .LO ( optlc_net_1675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1840 ( .LO ( optlc_net_1676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1841 ( .LO ( optlc_net_1677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1842 ( .LO ( optlc_net_1678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1843 ( .LO ( optlc_net_1679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1844 ( .LO ( optlc_net_1680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1846 ( .LO ( optlc_net_1681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1847 ( .LO ( optlc_net_1682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1848 ( .LO ( optlc_net_1683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1849 ( .LO ( optlc_net_1684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1850 ( .LO ( optlc_net_1685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1851 ( .LO ( optlc_net_1686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1852 ( .LO ( optlc_net_1687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1853 ( .LO ( optlc_net_1688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1854 ( .LO ( optlc_net_1689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1855 ( .LO ( optlc_net_1690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1856 ( .LO ( optlc_net_1691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1857 ( .LO ( optlc_net_1692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1858 ( .LO ( optlc_net_1693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1859 ( .LO ( optlc_net_1694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1860 ( .LO ( optlc_net_1695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1861 ( .LO ( optlc_net_1696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1862 ( .LO ( optlc_net_1697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1863 ( .LO ( optlc_net_1698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1864 ( .LO ( optlc_net_1699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1865 ( .LO ( optlc_net_1700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1866 ( .LO ( optlc_net_1701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1867 ( .LO ( optlc_net_1702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1868 ( .LO ( optlc_net_1703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1869 ( .LO ( optlc_net_1704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1870 ( .LO ( optlc_net_1705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1871 ( .LO ( optlc_net_1706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1872 ( .LO ( optlc_net_1707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1873 ( .LO ( optlc_net_1708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1874 ( .LO ( optlc_net_1709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1875 ( .LO ( optlc_net_1710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1876 ( .LO ( optlc_net_1711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1877 ( .LO ( optlc_net_1712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1878 ( .LO ( optlc_net_1713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1879 ( .LO ( optlc_net_1714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1880 ( .LO ( optlc_net_1715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1881 ( .LO ( optlc_net_1716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1882 ( .LO ( optlc_net_1717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1883 ( .LO ( optlc_net_1718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1884 ( .LO ( optlc_net_1719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1885 ( .LO ( optlc_net_1720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1886 ( .LO ( optlc_net_1721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1887 ( .LO ( optlc_net_1722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1888 ( .LO ( optlc_net_1723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1889 ( .LO ( optlc_net_1724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1890 ( .LO ( optlc_net_1725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1891 ( .LO ( optlc_net_1726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1892 ( .LO ( optlc_net_1727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1893 ( .LO ( optlc_net_1728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1894 ( .LO ( optlc_net_1729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1895 ( .LO ( optlc_net_1730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1896 ( .LO ( optlc_net_1731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1897 ( .LO ( optlc_net_1732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1898 ( .LO ( optlc_net_1733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1899 ( .LO ( optlc_net_1734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1900 ( .LO ( optlc_net_1735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1901 ( .LO ( optlc_net_1736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1902 ( .LO ( optlc_net_1737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1903 ( .LO ( optlc_net_1738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1904 ( .LO ( optlc_net_1739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1905 ( .LO ( optlc_net_1740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1906 ( .LO ( optlc_net_1741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1907 ( .LO ( optlc_net_1742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1908 ( .LO ( optlc_net_1743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1910 ( .LO ( optlc_net_1744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1911 ( .LO ( optlc_net_1745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1912 ( .LO ( optlc_net_1746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1913 ( .LO ( optlc_net_1747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1915 ( .LO ( optlc_net_1748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1916 ( .LO ( optlc_net_1749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1917 ( .LO ( optlc_net_1750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1919 ( .LO ( optlc_net_1751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1920 ( .LO ( optlc_net_1752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1922 ( .LO ( optlc_net_1753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1923 ( .LO ( optlc_net_1754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1924 ( .LO ( optlc_net_1755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1925 ( .LO ( optlc_net_1756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1926 ( .LO ( optlc_net_1757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1927 ( .LO ( optlc_net_1758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1928 ( .LO ( optlc_net_1759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1929 ( .LO ( optlc_net_1760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1930 ( .LO ( optlc_net_1761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1931 ( .LO ( optlc_net_1762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1932 ( .LO ( optlc_net_1763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1933 ( .LO ( optlc_net_1764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1934 ( .LO ( optlc_net_1765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1935 ( .LO ( optlc_net_1766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1936 ( .LO ( optlc_net_1767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1937 ( .LO ( optlc_net_1768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1939 ( .LO ( optlc_net_1769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1940 ( .LO ( optlc_net_1770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1941 ( .LO ( optlc_net_1771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1942 ( .LO ( optlc_net_1772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1943 ( .LO ( optlc_net_1773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1945 ( .LO ( optlc_net_1774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1947 ( .LO ( optlc_net_1775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1948 ( .LO ( optlc_net_1776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1949 ( .LO ( optlc_net_1777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1951 ( .LO ( optlc_net_1778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1953 ( .LO ( optlc_net_1779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1954 ( .LO ( optlc_net_1780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1956 ( .LO ( optlc_net_1781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1957 ( .LO ( optlc_net_1782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1958 ( .LO ( optlc_net_1783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1959 ( .LO ( optlc_net_1784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1960 ( .LO ( optlc_net_1785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1962 ( .LO ( optlc_net_1786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1963 ( .LO ( optlc_net_1787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1964 ( .LO ( optlc_net_1788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1965 ( .LO ( optlc_net_1789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1967 ( .LO ( optlc_net_1790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1969 ( .LO ( optlc_net_1791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1971 ( .LO ( optlc_net_1792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1973 ( .LO ( optlc_net_1793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1974 ( .LO ( optlc_net_1794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1975 ( .LO ( optlc_net_1795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1976 ( .LO ( optlc_net_1796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1977 ( .LO ( optlc_net_1797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1978 ( .LO ( optlc_net_1798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1979 ( .LO ( optlc_net_1799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1980 ( .LO ( optlc_net_1800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1981 ( .LO ( optlc_net_1801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1983 ( .LO ( optlc_net_1802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1984 ( .LO ( optlc_net_1803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1985 ( .LO ( optlc_net_1804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1986 ( .LO ( optlc_net_1805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1988 ( .LO ( optlc_net_1806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1990 ( .LO ( optlc_net_1807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1991 ( .LO ( optlc_net_1808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1993 ( .LO ( optlc_net_1809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1994 ( .LO ( optlc_net_1810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1995 ( .LO ( optlc_net_1811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1997 ( .LO ( optlc_net_1812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1998 ( .LO ( optlc_net_1813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1999 ( .LO ( optlc_net_1814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2001 ( .LO ( optlc_net_1815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2002 ( .LO ( optlc_net_1816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2004 ( .LO ( optlc_net_1817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2005 ( .LO ( optlc_net_1818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2007 ( .LO ( optlc_net_1819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2009 ( .LO ( optlc_net_1820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2010 ( .LO ( optlc_net_1821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2011 ( .LO ( optlc_net_1822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2012 ( .LO ( optlc_net_1823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2014 ( .LO ( optlc_net_1824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2016 ( .LO ( optlc_net_1825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2018 ( .LO ( optlc_net_1826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2019 ( .LO ( optlc_net_1827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2021 ( .LO ( optlc_net_1828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2022 ( .LO ( optlc_net_1829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2024 ( .LO ( optlc_net_1830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2026 ( .LO ( optlc_net_1831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2028 ( .LO ( optlc_net_1832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2030 ( .LO ( optlc_net_1833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2031 ( .LO ( optlc_net_1834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2032 ( .LO ( optlc_net_1835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2033 ( .LO ( optlc_net_1836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2035 ( .LO ( optlc_net_1837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2037 ( .LO ( optlc_net_1838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2040 ( .LO ( optlc_net_1839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2041 ( .LO ( optlc_net_1840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2043 ( .LO ( optlc_net_1841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2045 ( .LO ( optlc_net_1842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2046 ( .LO ( optlc_net_1843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2047 ( .LO ( optlc_net_1844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2049 ( .LO ( optlc_net_1845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2051 ( .LO ( optlc_net_1846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2053 ( .LO ( optlc_net_1847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2055 ( .LO ( optlc_net_1848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2056 ( .LO ( optlc_net_1849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2057 ( .LO ( optlc_net_1850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2058 ( .LO ( optlc_net_1851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2059 ( .LO ( optlc_net_1852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2060 ( .LO ( optlc_net_1853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2061 ( .LO ( optlc_net_1854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2063 ( .LO ( optlc_net_1855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2064 ( .LO ( optlc_net_1856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2066 ( .LO ( optlc_net_1857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2067 ( .LO ( optlc_net_1858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2069 ( .LO ( optlc_net_1859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2071 ( .LO ( optlc_net_1860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2073 ( .LO ( optlc_net_1861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2074 ( .LO ( optlc_net_1862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2076 ( .LO ( optlc_net_1863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2077 ( .LO ( optlc_net_1864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2078 ( .LO ( optlc_net_1865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2080 ( .LO ( optlc_net_1866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2081 ( .LO ( optlc_net_1867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2083 ( .LO ( optlc_net_1868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2085 ( .LO ( optlc_net_1869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2087 ( .LO ( optlc_net_1870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2088 ( .LO ( optlc_net_1871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2090 ( .LO ( optlc_net_1872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2091 ( .LO ( optlc_net_1873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2092 ( .LO ( optlc_net_1874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2093 ( .LO ( optlc_net_1875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2095 ( .LO ( optlc_net_1876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2097 ( .LO ( optlc_net_1877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2098 ( .LO ( optlc_net_1878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2099 ( .LO ( optlc_net_1879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2101 ( .LO ( optlc_net_1880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2102 ( .LO ( optlc_net_1881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2103 ( .LO ( optlc_net_1882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2104 ( .LO ( optlc_net_1883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2106 ( .LO ( optlc_net_1884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2107 ( .LO ( optlc_net_1885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2108 ( .LO ( optlc_net_1886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2109 ( .LO ( optlc_net_1887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2111 ( .LO ( optlc_net_1888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2113 ( .LO ( optlc_net_1889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2114 ( .LO ( optlc_net_1890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2115 ( .LO ( optlc_net_1891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2116 ( .LO ( optlc_net_1892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2118 ( .LO ( optlc_net_1893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2120 ( .LO ( optlc_net_1894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2121 ( .LO ( optlc_net_1895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2122 ( .LO ( optlc_net_1896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2124 ( .LO ( optlc_net_1897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2126 ( .LO ( optlc_net_1898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2128 ( .LO ( optlc_net_1899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2129 ( .LO ( optlc_net_1900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2132 ( .LO ( optlc_net_1902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2134 ( .LO ( optlc_net_1904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2140 ( .LO ( optlc_net_1908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2142 ( .LO ( optlc_net_1909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2144 ( .LO ( optlc_net_1910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2147 ( .LO ( optlc_net_1912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2149 ( .LO ( optlc_net_1914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2154 ( .LO ( optlc_net_1918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2156 ( .LO ( optlc_net_1919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2158 ( .LO ( optlc_net_1920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2160 ( .LO ( optlc_net_1921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2168 ( .LO ( optlc_net_1927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2182 ( .LO ( optlc_net_1936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2203 ( .LO ( optlc_net_1948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2208 ( .LO ( optlc_net_1953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_1959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_1960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_1961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2221 ( .LO ( optlc_net_1962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_1963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_1964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_1965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_1966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2227 ( .LO ( optlc_net_1967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2228 ( .LO ( optlc_net_1968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2230 ( .LO ( optlc_net_1969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2232 ( .LO ( optlc_net_1970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_1971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2234 ( .LO ( optlc_net_1972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_1973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_1974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_1975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_1976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_1977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_1978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2241 ( .LO ( optlc_net_1979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_1980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_1981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2244 ( .LO ( optlc_net_1982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2245 ( .LO ( optlc_net_1983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2246 ( .LO ( optlc_net_1984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_1985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_1986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2249 ( .LO ( optlc_net_1987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2250 ( .LO ( optlc_net_1988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2251 ( .LO ( optlc_net_1989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2252 ( .LO ( optlc_net_1990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2253 ( .LO ( optlc_net_1991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2254 ( .LO ( optlc_net_1992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2255 ( .LO ( optlc_net_1993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2256 ( .LO ( optlc_net_1994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2257 ( .LO ( optlc_net_1995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2258 ( .LO ( optlc_net_1996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2259 ( .LO ( optlc_net_1997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2260 ( .LO ( optlc_net_1998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2261 ( .LO ( optlc_net_1999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2262 ( .LO ( optlc_net_2000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2263 ( .LO ( optlc_net_2001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2264 ( .LO ( optlc_net_2002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2265 ( .LO ( optlc_net_2003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2266 ( .LO ( optlc_net_2004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2267 ( .LO ( optlc_net_2005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2268 ( .LO ( optlc_net_2006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2269 ( .LO ( optlc_net_2007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2270 ( .LO ( optlc_net_2008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2271 ( .LO ( optlc_net_2009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2272 ( .LO ( optlc_net_2010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2273 ( .LO ( optlc_net_2011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2274 ( .LO ( optlc_net_2012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2275 ( .LO ( optlc_net_2013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2276 ( .LO ( optlc_net_2014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2277 ( .LO ( optlc_net_2015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2278 ( .LO ( optlc_net_2016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2279 ( .LO ( optlc_net_2017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2280 ( .LO ( optlc_net_2018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2281 ( .LO ( optlc_net_2019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2282 ( .LO ( optlc_net_2020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2283 ( .LO ( optlc_net_2021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2284 ( .LO ( optlc_net_2022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2285 ( .LO ( optlc_net_2023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2286 ( .LO ( optlc_net_2024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2287 ( .LO ( optlc_net_2025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2288 ( .LO ( optlc_net_2026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2289 ( .LO ( optlc_net_2027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2290 ( .LO ( optlc_net_2028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2291 ( .LO ( optlc_net_2029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2292 ( .LO ( optlc_net_2030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2293 ( .LO ( optlc_net_2031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2294 ( .LO ( optlc_net_2032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2295 ( .LO ( optlc_net_2033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2296 ( .LO ( optlc_net_2034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2297 ( .LO ( optlc_net_2035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2298 ( .LO ( optlc_net_2036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2299 ( .LO ( optlc_net_2037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2300 ( .LO ( optlc_net_2038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2301 ( .LO ( optlc_net_2039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2302 ( .LO ( optlc_net_2040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2304 ( .LO ( optlc_net_2041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2305 ( .LO ( optlc_net_2042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2306 ( .LO ( optlc_net_2043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2307 ( .LO ( optlc_net_2044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2308 ( .LO ( optlc_net_2045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2309 ( .LO ( optlc_net_2046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2310 ( .LO ( optlc_net_2047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2311 ( .LO ( optlc_net_2048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2312 ( .LO ( optlc_net_2049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2313 ( .LO ( optlc_net_2050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2314 ( .LO ( optlc_net_2051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2315 ( .LO ( optlc_net_2052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2316 ( .LO ( optlc_net_2053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2317 ( .LO ( optlc_net_2054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2318 ( .LO ( optlc_net_2055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2319 ( .LO ( optlc_net_2056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2320 ( .LO ( optlc_net_2057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2321 ( .LO ( optlc_net_2058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2322 ( .LO ( optlc_net_2059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2323 ( .LO ( optlc_net_2060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2324 ( .LO ( optlc_net_2061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2325 ( .LO ( optlc_net_2062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2326 ( .LO ( optlc_net_2063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2327 ( .LO ( optlc_net_2064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2328 ( .LO ( optlc_net_2065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2329 ( .LO ( optlc_net_2066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2330 ( .LO ( optlc_net_2067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2331 ( .LO ( optlc_net_2068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2332 ( .LO ( optlc_net_2069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2333 ( .LO ( optlc_net_2070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2334 ( .LO ( optlc_net_2071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2335 ( .LO ( optlc_net_2072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2336 ( .LO ( optlc_net_2073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2337 ( .LO ( optlc_net_2074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2338 ( .LO ( optlc_net_2075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2339 ( .LO ( optlc_net_2076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2340 ( .LO ( optlc_net_2077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2341 ( .LO ( optlc_net_2078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2343 ( .LO ( optlc_net_2079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2344 ( .LO ( optlc_net_2080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2346 ( .LO ( optlc_net_2081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2347 ( .LO ( optlc_net_2082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2348 ( .LO ( optlc_net_2083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2349 ( .LO ( optlc_net_2084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2350 ( .LO ( optlc_net_2085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2351 ( .LO ( optlc_net_2086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2352 ( .LO ( optlc_net_2087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2353 ( .LO ( optlc_net_2088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2354 ( .LO ( optlc_net_2089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2355 ( .LO ( optlc_net_2090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2356 ( .LO ( optlc_net_2091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2358 ( .LO ( optlc_net_2092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2359 ( .LO ( optlc_net_2093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2360 ( .LO ( optlc_net_2094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2362 ( .LO ( optlc_net_2095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2363 ( .LO ( optlc_net_2096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2364 ( .LO ( optlc_net_2097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2365 ( .LO ( optlc_net_2098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2366 ( .LO ( optlc_net_2099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2368 ( .LO ( optlc_net_2100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2370 ( .LO ( optlc_net_2101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2371 ( .LO ( optlc_net_2102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2372 ( .LO ( optlc_net_2103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2373 ( .LO ( optlc_net_2104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2374 ( .LO ( optlc_net_2105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2375 ( .LO ( optlc_net_2106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2376 ( .LO ( optlc_net_2107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2377 ( .LO ( optlc_net_2108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2378 ( .LO ( optlc_net_2109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2379 ( .LO ( optlc_net_2110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2380 ( .LO ( optlc_net_2111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2381 ( .LO ( optlc_net_2112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2382 ( .LO ( optlc_net_2113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2383 ( .LO ( optlc_net_2114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2385 ( .LO ( optlc_net_2115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2386 ( .LO ( optlc_net_2116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2387 ( .LO ( optlc_net_2117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2388 ( .LO ( optlc_net_2118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2389 ( .LO ( optlc_net_2119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2390 ( .LO ( optlc_net_2120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2391 ( .LO ( optlc_net_2121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2393 ( .LO ( optlc_net_2122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2395 ( .LO ( optlc_net_2123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2397 ( .LO ( optlc_net_2124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2398 ( .LO ( optlc_net_2125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2400 ( .LO ( optlc_net_2126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2401 ( .LO ( optlc_net_2127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2403 ( .LO ( optlc_net_2128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2404 ( .LO ( optlc_net_2129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2405 ( .LO ( optlc_net_2130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2407 ( .LO ( optlc_net_2131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2408 ( .LO ( optlc_net_2132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2409 ( .LO ( optlc_net_2133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2410 ( .LO ( optlc_net_2134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2412 ( .LO ( optlc_net_2135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2413 ( .LO ( optlc_net_2136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2415 ( .LO ( optlc_net_2137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2416 ( .LO ( optlc_net_2138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2417 ( .LO ( optlc_net_2139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2418 ( .LO ( optlc_net_2140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2419 ( .LO ( optlc_net_2141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2420 ( .LO ( optlc_net_2142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2421 ( .LO ( optlc_net_2143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2422 ( .LO ( optlc_net_2144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2423 ( .LO ( optlc_net_2145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2425 ( .LO ( optlc_net_2146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2426 ( .LO ( optlc_net_2147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2427 ( .LO ( optlc_net_2148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2428 ( .LO ( optlc_net_2149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2429 ( .LO ( optlc_net_2150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2430 ( .LO ( optlc_net_2151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2431 ( .LO ( optlc_net_2152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2433 ( .LO ( optlc_net_2153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2434 ( .LO ( optlc_net_2154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2436 ( .LO ( optlc_net_2155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2438 ( .LO ( optlc_net_2156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2439 ( .LO ( optlc_net_2157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2441 ( .LO ( optlc_net_2158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2442 ( .LO ( optlc_net_2159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2443 ( .LO ( optlc_net_2160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2445 ( .LO ( optlc_net_2161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2446 ( .LO ( optlc_net_2162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2447 ( .LO ( optlc_net_2163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2448 ( .LO ( optlc_net_2164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2449 ( .LO ( optlc_net_2165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2450 ( .LO ( optlc_net_2166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2451 ( .LO ( optlc_net_2167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2452 ( .LO ( optlc_net_2168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2454 ( .LO ( optlc_net_2169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2455 ( .LO ( optlc_net_2170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2456 ( .LO ( optlc_net_2171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2457 ( .LO ( optlc_net_2172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2458 ( .LO ( optlc_net_2173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2459 ( .LO ( optlc_net_2174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2460 ( .LO ( optlc_net_2175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2461 ( .LO ( optlc_net_2176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2462 ( .LO ( optlc_net_2177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2463 ( .LO ( optlc_net_2178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2465 ( .LO ( optlc_net_2179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2466 ( .LO ( optlc_net_2180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2467 ( .LO ( optlc_net_2181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2468 ( .LO ( optlc_net_2182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2469 ( .LO ( optlc_net_2183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2470 ( .LO ( optlc_net_2184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2472 ( .LO ( optlc_net_2185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2473 ( .LO ( optlc_net_2186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2474 ( .LO ( optlc_net_2187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2475 ( .LO ( optlc_net_2188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2476 ( .LO ( optlc_net_2189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2477 ( .LO ( optlc_net_2190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2479 ( .LO ( optlc_net_2191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2481 ( .LO ( optlc_net_2192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2483 ( .LO ( optlc_net_2193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2484 ( .LO ( optlc_net_2194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2485 ( .LO ( optlc_net_2195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2486 ( .LO ( optlc_net_2196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2488 ( .LO ( optlc_net_2197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2489 ( .LO ( optlc_net_2198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2490 ( .LO ( optlc_net_2199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2491 ( .LO ( optlc_net_2200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2492 ( .LO ( optlc_net_2201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2494 ( .LO ( optlc_net_2202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2495 ( .LO ( optlc_net_2203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2497 ( .LO ( optlc_net_2204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2498 ( .LO ( optlc_net_2205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2499 ( .LO ( optlc_net_2206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2500 ( .LO ( optlc_net_2207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2502 ( .LO ( optlc_net_2208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2503 ( .LO ( optlc_net_2209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2504 ( .LO ( optlc_net_2210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2505 ( .LO ( optlc_net_2211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2507 ( .LO ( optlc_net_2212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2509 ( .LO ( optlc_net_2213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2510 ( .LO ( optlc_net_2214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2511 ( .LO ( optlc_net_2215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2512 ( .LO ( optlc_net_2216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2513 ( .LO ( optlc_net_2217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2515 ( .LO ( optlc_net_2218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2517 ( .LO ( optlc_net_2219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2519 ( .LO ( optlc_net_2220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2521 ( .LO ( optlc_net_2221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2522 ( .LO ( optlc_net_2222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2523 ( .LO ( optlc_net_2223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2524 ( .LO ( optlc_net_2224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2525 ( .LO ( optlc_net_2225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2526 ( .LO ( optlc_net_2226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2527 ( .LO ( optlc_net_2227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2528 ( .LO ( optlc_net_2228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2529 ( .LO ( optlc_net_2229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2530 ( .LO ( optlc_net_2230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2531 ( .LO ( optlc_net_2231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2533 ( .LO ( optlc_net_2232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2534 ( .LO ( optlc_net_2233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2535 ( .LO ( optlc_net_2234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2536 ( .LO ( optlc_net_2235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2538 ( .LO ( optlc_net_2236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2539 ( .LO ( optlc_net_2237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2540 ( .LO ( optlc_net_2238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2541 ( .LO ( optlc_net_2239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2542 ( .LO ( optlc_net_2240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2543 ( .LO ( optlc_net_2241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2544 ( .LO ( optlc_net_2242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2545 ( .LO ( optlc_net_2243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2546 ( .LO ( optlc_net_2244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2547 ( .LO ( optlc_net_2245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2549 ( .LO ( optlc_net_2246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2550 ( .LO ( optlc_net_2247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2552 ( .LO ( optlc_net_2248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2553 ( .LO ( optlc_net_2249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2554 ( .LO ( optlc_net_2250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2556 ( .LO ( optlc_net_2251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2557 ( .LO ( optlc_net_2252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2558 ( .LO ( optlc_net_2253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2559 ( .LO ( optlc_net_2254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2560 ( .LO ( optlc_net_2255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2562 ( .LO ( optlc_net_2256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2563 ( .LO ( optlc_net_2257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2564 ( .LO ( optlc_net_2258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2566 ( .LO ( optlc_net_2259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2568 ( .LO ( optlc_net_2260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2569 ( .LO ( optlc_net_2261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2570 ( .LO ( optlc_net_2262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2571 ( .LO ( optlc_net_2263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2572 ( .LO ( optlc_net_2264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2573 ( .LO ( optlc_net_2265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2574 ( .LO ( optlc_net_2266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2575 ( .LO ( optlc_net_2267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2576 ( .LO ( optlc_net_2268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2577 ( .LO ( optlc_net_2269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2578 ( .LO ( optlc_net_2270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2579 ( .LO ( optlc_net_2271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2580 ( .LO ( optlc_net_2272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2581 ( .LO ( optlc_net_2273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2582 ( .LO ( optlc_net_2274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2583 ( .LO ( optlc_net_2275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2584 ( .LO ( optlc_net_2276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2585 ( .LO ( optlc_net_2277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2586 ( .LO ( optlc_net_2278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2587 ( .LO ( optlc_net_2279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2588 ( .LO ( optlc_net_2280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2589 ( .LO ( optlc_net_2281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2590 ( .LO ( optlc_net_2282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2591 ( .LO ( optlc_net_2283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2592 ( .LO ( optlc_net_2284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2593 ( .LO ( optlc_net_2285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2594 ( .LO ( optlc_net_2286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2595 ( .LO ( optlc_net_2287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2596 ( .LO ( optlc_net_2288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2597 ( .LO ( optlc_net_2289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2598 ( .LO ( optlc_net_2290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2599 ( .LO ( optlc_net_2291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2600 ( .LO ( optlc_net_2292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2601 ( .LO ( optlc_net_2293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2602 ( .LO ( optlc_net_2294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2603 ( .LO ( optlc_net_2295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2604 ( .LO ( optlc_net_2296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2605 ( .LO ( optlc_net_2297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2606 ( .LO ( optlc_net_2298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2607 ( .LO ( optlc_net_2299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2608 ( .LO ( optlc_net_2300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2609 ( .LO ( optlc_net_2301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2610 ( .LO ( optlc_net_2302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2611 ( .LO ( optlc_net_2303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2612 ( .LO ( optlc_net_2304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2613 ( .LO ( optlc_net_2305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2614 ( .LO ( optlc_net_2306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2615 ( .LO ( optlc_net_2307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2616 ( .LO ( optlc_net_2308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2617 ( .LO ( optlc_net_2309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2618 ( .LO ( optlc_net_2310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2619 ( .LO ( optlc_net_2311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2620 ( .LO ( optlc_net_2312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2621 ( .LO ( optlc_net_2313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2622 ( .LO ( optlc_net_2314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2623 ( .LO ( optlc_net_2315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2624 ( .LO ( optlc_net_2316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2625 ( .LO ( optlc_net_2317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2626 ( .LO ( optlc_net_2318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2627 ( .LO ( optlc_net_2319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2628 ( .LO ( optlc_net_2320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2629 ( .LO ( optlc_net_2321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2630 ( .LO ( optlc_net_2322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2631 ( .LO ( optlc_net_2323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2632 ( .LO ( optlc_net_2324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2633 ( .LO ( optlc_net_2325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2634 ( .LO ( optlc_net_2326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2635 ( .LO ( optlc_net_2327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2636 ( .LO ( optlc_net_2328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2637 ( .LO ( optlc_net_2329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2638 ( .LO ( optlc_net_2330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2639 ( .LO ( optlc_net_2331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2640 ( .LO ( optlc_net_2332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2641 ( .LO ( optlc_net_2333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2642 ( .LO ( optlc_net_2334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2643 ( .LO ( optlc_net_2335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2644 ( .LO ( optlc_net_2336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2645 ( .LO ( optlc_net_2337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2646 ( .LO ( optlc_net_2338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2647 ( .LO ( optlc_net_2339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2648 ( .LO ( optlc_net_2340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2649 ( .LO ( optlc_net_2341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2650 ( .LO ( optlc_net_2342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2651 ( .LO ( optlc_net_2343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2652 ( .LO ( optlc_net_2344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2653 ( .LO ( optlc_net_2345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2654 ( .LO ( optlc_net_2346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2655 ( .LO ( optlc_net_2347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2656 ( .LO ( optlc_net_2348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2657 ( .LO ( optlc_net_2349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2658 ( .LO ( optlc_net_2350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2659 ( .LO ( optlc_net_2351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2660 ( .LO ( optlc_net_2352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2661 ( .LO ( optlc_net_2353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2662 ( .LO ( optlc_net_2354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2663 ( .LO ( optlc_net_2355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2664 ( .LO ( optlc_net_2356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2665 ( .LO ( optlc_net_2357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2666 ( .LO ( optlc_net_2358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2667 ( .LO ( optlc_net_2359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2668 ( .LO ( optlc_net_2360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2669 ( .LO ( optlc_net_2361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2670 ( .LO ( optlc_net_2362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2671 ( .LO ( optlc_net_2363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2672 ( .LO ( optlc_net_2364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2673 ( .LO ( optlc_net_2365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2674 ( .LO ( optlc_net_2366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2675 ( .LO ( optlc_net_2367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2676 ( .LO ( optlc_net_2368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2677 ( .LO ( optlc_net_2369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2678 ( .LO ( optlc_net_2370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2680 ( .LO ( optlc_net_2371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2681 ( .LO ( optlc_net_2372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2682 ( .LO ( optlc_net_2373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2683 ( .LO ( optlc_net_2374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2685 ( .LO ( optlc_net_2375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2686 ( .LO ( optlc_net_2376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2687 ( .LO ( optlc_net_2377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2688 ( .LO ( optlc_net_2378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2689 ( .LO ( optlc_net_2379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2690 ( .LO ( optlc_net_2380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2692 ( .LO ( optlc_net_2381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2693 ( .LO ( optlc_net_2382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2694 ( .LO ( optlc_net_2383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2695 ( .LO ( optlc_net_2384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2697 ( .LO ( optlc_net_2385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2698 ( .LO ( optlc_net_2386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2699 ( .LO ( optlc_net_2387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2700 ( .LO ( optlc_net_2388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2702 ( .LO ( optlc_net_2389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2704 ( .LO ( optlc_net_2390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2705 ( .LO ( optlc_net_2391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2706 ( .LO ( optlc_net_2392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2707 ( .LO ( optlc_net_2393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2708 ( .LO ( optlc_net_2394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2709 ( .LO ( optlc_net_2395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2710 ( .LO ( optlc_net_2396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2711 ( .LO ( optlc_net_2397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2712 ( .LO ( optlc_net_2398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2713 ( .LO ( optlc_net_2399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2714 ( .LO ( optlc_net_2400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2715 ( .LO ( optlc_net_2401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2717 ( .LO ( optlc_net_2402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2719 ( .LO ( optlc_net_2403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2721 ( .LO ( optlc_net_2404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2722 ( .LO ( optlc_net_2405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2724 ( .LO ( optlc_net_2406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2725 ( .LO ( optlc_net_2407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2726 ( .LO ( optlc_net_2408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2727 ( .LO ( optlc_net_2409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2729 ( .LO ( optlc_net_2410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2730 ( .LO ( optlc_net_2411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2731 ( .LO ( optlc_net_2412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2733 ( .LO ( optlc_net_2413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2735 ( .LO ( optlc_net_2414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2736 ( .LO ( optlc_net_2415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2738 ( .LO ( optlc_net_2416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2739 ( .LO ( optlc_net_2417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2740 ( .LO ( optlc_net_2418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2741 ( .LO ( optlc_net_2419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2743 ( .LO ( optlc_net_2420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2745 ( .LO ( optlc_net_2421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2746 ( .LO ( optlc_net_2422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2747 ( .LO ( optlc_net_2423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2749 ( .LO ( optlc_net_2424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2750 ( .LO ( optlc_net_2425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2752 ( .LO ( optlc_net_2426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2753 ( .LO ( optlc_net_2427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2754 ( .LO ( optlc_net_2428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2755 ( .LO ( optlc_net_2429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2756 ( .LO ( optlc_net_2430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2757 ( .LO ( optlc_net_2431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2759 ( .LO ( optlc_net_2432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2760 ( .LO ( optlc_net_2433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2761 ( .LO ( optlc_net_2434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2762 ( .LO ( optlc_net_2435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2763 ( .LO ( optlc_net_2436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2764 ( .LO ( optlc_net_2437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2765 ( .LO ( optlc_net_2438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2766 ( .LO ( optlc_net_2439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2767 ( .LO ( optlc_net_2440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2768 ( .LO ( optlc_net_2441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2769 ( .LO ( optlc_net_2442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2770 ( .LO ( optlc_net_2443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2771 ( .LO ( optlc_net_2444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2773 ( .LO ( optlc_net_2445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2774 ( .LO ( optlc_net_2446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2775 ( .LO ( optlc_net_2447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2776 ( .LO ( optlc_net_2448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2777 ( .LO ( optlc_net_2449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2779 ( .LO ( optlc_net_2450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2780 ( .LO ( optlc_net_2451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2781 ( .LO ( optlc_net_2452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2782 ( .LO ( optlc_net_2453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2783 ( .LO ( optlc_net_2454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2784 ( .LO ( optlc_net_2455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2785 ( .LO ( optlc_net_2456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2786 ( .LO ( optlc_net_2457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2787 ( .LO ( optlc_net_2458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2789 ( .LO ( optlc_net_2459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2791 ( .LO ( optlc_net_2460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2792 ( .LO ( optlc_net_2461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2793 ( .LO ( optlc_net_2462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2794 ( .LO ( optlc_net_2463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2795 ( .LO ( optlc_net_2464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2796 ( .LO ( optlc_net_2465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2797 ( .LO ( optlc_net_2466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2798 ( .LO ( optlc_net_2467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2799 ( .LO ( optlc_net_2468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2801 ( .LO ( optlc_net_2469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2802 ( .LO ( optlc_net_2470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2803 ( .LO ( optlc_net_2471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2804 ( .LO ( optlc_net_2472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2805 ( .LO ( optlc_net_2473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2806 ( .LO ( optlc_net_2474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2807 ( .LO ( optlc_net_2475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2808 ( .LO ( optlc_net_2476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2809 ( .LO ( optlc_net_2477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2810 ( .LO ( optlc_net_2478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2812 ( .LO ( optlc_net_2479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2813 ( .LO ( optlc_net_2480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2814 ( .LO ( optlc_net_2481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2815 ( .LO ( optlc_net_2482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2816 ( .LO ( optlc_net_2483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2817 ( .LO ( optlc_net_2484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2818 ( .LO ( optlc_net_2485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2819 ( .LO ( optlc_net_2486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2820 ( .LO ( optlc_net_2487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2822 ( .LO ( optlc_net_2488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2823 ( .LO ( optlc_net_2489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2824 ( .LO ( optlc_net_2490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2825 ( .LO ( optlc_net_2491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2826 ( .LO ( optlc_net_2492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2827 ( .LO ( optlc_net_2493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2829 ( .LO ( optlc_net_2494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2830 ( .LO ( optlc_net_2495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2832 ( .LO ( optlc_net_2496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2833 ( .LO ( optlc_net_2497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2834 ( .LO ( optlc_net_2498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2835 ( .LO ( optlc_net_2499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2836 ( .LO ( optlc_net_2500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2837 ( .LO ( optlc_net_2501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2838 ( .LO ( optlc_net_2502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2839 ( .LO ( optlc_net_2503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2841 ( .LO ( optlc_net_2504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2842 ( .LO ( optlc_net_2505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2843 ( .LO ( optlc_net_2506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2844 ( .LO ( optlc_net_2507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2845 ( .LO ( optlc_net_2508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2846 ( .LO ( optlc_net_2509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2847 ( .LO ( optlc_net_2510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2848 ( .LO ( optlc_net_2511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2850 ( .LO ( optlc_net_2512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2851 ( .LO ( optlc_net_2513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2852 ( .LO ( optlc_net_2514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2853 ( .LO ( optlc_net_2515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2854 ( .LO ( optlc_net_2516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2855 ( .LO ( optlc_net_2517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2856 ( .LO ( optlc_net_2518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2857 ( .LO ( optlc_net_2519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2858 ( .LO ( optlc_net_2520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2859 ( .LO ( optlc_net_2521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2860 ( .LO ( optlc_net_2522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2861 ( .LO ( optlc_net_2523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2862 ( .LO ( optlc_net_2524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2863 ( .LO ( optlc_net_2525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2864 ( .LO ( optlc_net_2526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2865 ( .LO ( optlc_net_2527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2866 ( .LO ( optlc_net_2528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2867 ( .LO ( optlc_net_2529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2868 ( .LO ( optlc_net_2530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2869 ( .LO ( optlc_net_2531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2870 ( .LO ( optlc_net_2532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2871 ( .LO ( optlc_net_2533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2872 ( .LO ( optlc_net_2534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2873 ( .LO ( optlc_net_2535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2874 ( .LO ( optlc_net_2536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2875 ( .LO ( optlc_net_2537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2876 ( .LO ( optlc_net_2538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2877 ( .LO ( optlc_net_2539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2878 ( .LO ( optlc_net_2540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2879 ( .LO ( optlc_net_2541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2880 ( .LO ( optlc_net_2542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2881 ( .LO ( optlc_net_2543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2882 ( .LO ( optlc_net_2544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2883 ( .LO ( optlc_net_2545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2884 ( .LO ( optlc_net_2546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2885 ( .LO ( optlc_net_2547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2886 ( .LO ( optlc_net_2548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2887 ( .LO ( optlc_net_2549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2888 ( .LO ( optlc_net_2550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2889 ( .LO ( optlc_net_2551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2890 ( .LO ( optlc_net_2552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2891 ( .LO ( optlc_net_2553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2892 ( .LO ( optlc_net_2554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2893 ( .LO ( optlc_net_2555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2894 ( .LO ( optlc_net_2556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2895 ( .LO ( optlc_net_2557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2896 ( .LO ( optlc_net_2558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2897 ( .LO ( optlc_net_2559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2898 ( .LO ( optlc_net_2560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2899 ( .LO ( optlc_net_2561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2900 ( .LO ( optlc_net_2562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2901 ( .LO ( optlc_net_2563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2902 ( .LO ( optlc_net_2564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2903 ( .LO ( optlc_net_2565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2904 ( .LO ( optlc_net_2566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2905 ( .LO ( optlc_net_2567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2906 ( .LO ( optlc_net_2568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2907 ( .LO ( optlc_net_2569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2908 ( .LO ( optlc_net_2570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2909 ( .LO ( optlc_net_2571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2910 ( .LO ( optlc_net_2572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2911 ( .LO ( optlc_net_2573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2912 ( .LO ( optlc_net_2574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2913 ( .LO ( optlc_net_2575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2914 ( .LO ( optlc_net_2576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2915 ( .LO ( optlc_net_2577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2916 ( .LO ( optlc_net_2578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2917 ( .LO ( optlc_net_2579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2918 ( .LO ( optlc_net_2580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2919 ( .LO ( optlc_net_2581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2920 ( .LO ( optlc_net_2582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2921 ( .LO ( optlc_net_2583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2922 ( .LO ( optlc_net_2584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2923 ( .LO ( optlc_net_2585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2924 ( .LO ( optlc_net_2586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2925 ( .LO ( optlc_net_2587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2926 ( .LO ( optlc_net_2588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2927 ( .LO ( optlc_net_2589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2928 ( .LO ( optlc_net_2590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2929 ( .LO ( optlc_net_2591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2930 ( .LO ( optlc_net_2592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2931 ( .LO ( optlc_net_2593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2932 ( .LO ( optlc_net_2594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2933 ( .LO ( optlc_net_2595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2934 ( .LO ( optlc_net_2596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2935 ( .LO ( optlc_net_2597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2936 ( .LO ( optlc_net_2598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2937 ( .LO ( optlc_net_2599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2938 ( .LO ( optlc_net_2600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2939 ( .LO ( optlc_net_2601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2940 ( .LO ( optlc_net_2602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2941 ( .LO ( optlc_net_2603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2942 ( .LO ( optlc_net_2604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2943 ( .LO ( optlc_net_2605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2944 ( .LO ( optlc_net_2606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2945 ( .LO ( optlc_net_2607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2946 ( .LO ( optlc_net_2608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2947 ( .LO ( optlc_net_2609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2948 ( .LO ( optlc_net_2610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2949 ( .LO ( optlc_net_2611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2951 ( .LO ( optlc_net_2612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2952 ( .LO ( optlc_net_2613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2953 ( .LO ( optlc_net_2614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2954 ( .LO ( optlc_net_2615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2955 ( .LO ( optlc_net_2616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2956 ( .LO ( optlc_net_2617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2957 ( .LO ( optlc_net_2618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2958 ( .LO ( optlc_net_2619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2959 ( .LO ( optlc_net_2620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2960 ( .LO ( optlc_net_2621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2962 ( .LO ( optlc_net_2622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2963 ( .LO ( optlc_net_2623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2964 ( .LO ( optlc_net_2624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2965 ( .LO ( optlc_net_2625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2966 ( .LO ( optlc_net_2626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2967 ( .LO ( optlc_net_2627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2968 ( .LO ( optlc_net_2628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2969 ( .LO ( optlc_net_2629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2970 ( .LO ( optlc_net_2630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2971 ( .LO ( optlc_net_2631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2973 ( .LO ( optlc_net_2632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2974 ( .LO ( optlc_net_2633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2975 ( .LO ( optlc_net_2634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2976 ( .LO ( optlc_net_2635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2977 ( .LO ( optlc_net_2636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2978 ( .LO ( optlc_net_2637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2979 ( .LO ( optlc_net_2638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2980 ( .LO ( optlc_net_2639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2981 ( .LO ( optlc_net_2640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2982 ( .LO ( optlc_net_2641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2983 ( .LO ( optlc_net_2642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2985 ( .LO ( optlc_net_2643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2986 ( .LO ( optlc_net_2644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2987 ( .LO ( optlc_net_2645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2988 ( .LO ( optlc_net_2646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2989 ( .LO ( optlc_net_2647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2990 ( .LO ( optlc_net_2648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2991 ( .LO ( optlc_net_2649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2992 ( .LO ( optlc_net_2650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2993 ( .LO ( optlc_net_2651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2995 ( .LO ( optlc_net_2652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2997 ( .LO ( optlc_net_2653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2998 ( .LO ( optlc_net_2654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2999 ( .LO ( optlc_net_2655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3000 ( .LO ( optlc_net_2656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3001 ( .LO ( optlc_net_2657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3002 ( .LO ( optlc_net_2658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3003 ( .LO ( optlc_net_2659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3004 ( .LO ( optlc_net_2660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3005 ( .LO ( optlc_net_2661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3006 ( .LO ( optlc_net_2662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3007 ( .LO ( optlc_net_2663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3008 ( .LO ( optlc_net_2664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3009 ( .LO ( optlc_net_2665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3010 ( .LO ( optlc_net_2666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3011 ( .LO ( optlc_net_2667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3013 ( .LO ( optlc_net_2668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3014 ( .LO ( optlc_net_2669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3015 ( .LO ( optlc_net_2670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3016 ( .LO ( optlc_net_2671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3017 ( .LO ( optlc_net_2672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3019 ( .LO ( optlc_net_2673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3020 ( .LO ( optlc_net_2674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3021 ( .LO ( optlc_net_2675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3022 ( .LO ( optlc_net_2676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3023 ( .LO ( optlc_net_2677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3024 ( .LO ( optlc_net_2678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3025 ( .LO ( optlc_net_2679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3026 ( .LO ( optlc_net_2680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3027 ( .LO ( optlc_net_2681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3028 ( .LO ( optlc_net_2682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3030 ( .LO ( optlc_net_2683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3031 ( .LO ( optlc_net_2684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3032 ( .LO ( optlc_net_2685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3034 ( .LO ( optlc_net_2686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3035 ( .LO ( optlc_net_2687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3037 ( .LO ( optlc_net_2688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3038 ( .LO ( optlc_net_2689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3039 ( .LO ( optlc_net_2690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3040 ( .LO ( optlc_net_2691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3041 ( .LO ( optlc_net_2692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3042 ( .LO ( optlc_net_2693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3043 ( .LO ( optlc_net_2694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3044 ( .LO ( optlc_net_2695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3045 ( .LO ( optlc_net_2696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3046 ( .LO ( optlc_net_2697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3047 ( .LO ( optlc_net_2698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3048 ( .LO ( optlc_net_2699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3049 ( .LO ( optlc_net_2700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3050 ( .LO ( optlc_net_2701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3051 ( .LO ( optlc_net_2702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3052 ( .LO ( optlc_net_2703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3053 ( .LO ( optlc_net_2704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3054 ( .LO ( optlc_net_2705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3055 ( .LO ( optlc_net_2706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3056 ( .LO ( optlc_net_2707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3057 ( .LO ( optlc_net_2708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3058 ( .LO ( optlc_net_2709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3059 ( .LO ( optlc_net_2710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3060 ( .LO ( optlc_net_2711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3061 ( .LO ( optlc_net_2712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3062 ( .LO ( optlc_net_2713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3063 ( .LO ( optlc_net_2714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3064 ( .LO ( optlc_net_2715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3065 ( .LO ( optlc_net_2716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3066 ( .LO ( optlc_net_2717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3067 ( .LO ( optlc_net_2718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3068 ( .LO ( optlc_net_2719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3069 ( .LO ( optlc_net_2720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3070 ( .LO ( optlc_net_2721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3071 ( .LO ( optlc_net_2722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3073 ( .LO ( optlc_net_2723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3074 ( .LO ( optlc_net_2724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3075 ( .LO ( optlc_net_2725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3076 ( .LO ( optlc_net_2726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3077 ( .LO ( optlc_net_2727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3079 ( .LO ( optlc_net_2728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3080 ( .LO ( optlc_net_2729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3081 ( .LO ( optlc_net_2730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3082 ( .LO ( optlc_net_2731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3083 ( .LO ( optlc_net_2732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3084 ( .LO ( optlc_net_2733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3085 ( .LO ( optlc_net_2734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3086 ( .LO ( optlc_net_2735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3087 ( .LO ( optlc_net_2736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3088 ( .LO ( optlc_net_2737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3089 ( .LO ( optlc_net_2738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3090 ( .LO ( optlc_net_2739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3091 ( .LO ( optlc_net_2740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3092 ( .LO ( optlc_net_2741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3093 ( .LO ( optlc_net_2742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3094 ( .LO ( optlc_net_2743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3095 ( .LO ( optlc_net_2744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3096 ( .LO ( optlc_net_2745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3097 ( .LO ( optlc_net_2746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3098 ( .LO ( optlc_net_2747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3099 ( .LO ( optlc_net_2748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3100 ( .LO ( optlc_net_2749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3101 ( .LO ( optlc_net_2750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3102 ( .LO ( optlc_net_2751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3103 ( .LO ( optlc_net_2752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3104 ( .LO ( optlc_net_2753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3105 ( .LO ( optlc_net_2754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3106 ( .LO ( optlc_net_2755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3107 ( .LO ( optlc_net_2756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3108 ( .LO ( optlc_net_2757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3109 ( .LO ( optlc_net_2758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3110 ( .LO ( optlc_net_2759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3111 ( .LO ( optlc_net_2760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3112 ( .LO ( optlc_net_2761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3113 ( .LO ( optlc_net_2762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3114 ( .LO ( optlc_net_2763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3115 ( .LO ( optlc_net_2764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3116 ( .LO ( optlc_net_2765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3117 ( .LO ( optlc_net_2766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3118 ( .LO ( optlc_net_2767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3119 ( .LO ( optlc_net_2768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3120 ( .LO ( optlc_net_2769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3121 ( .LO ( optlc_net_2770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3122 ( .LO ( optlc_net_2771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3123 ( .LO ( optlc_net_2772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3124 ( .LO ( optlc_net_2773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3125 ( .LO ( optlc_net_2774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3126 ( .LO ( optlc_net_2775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3127 ( .LO ( optlc_net_2776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3128 ( .LO ( optlc_net_2777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3129 ( .LO ( optlc_net_2778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3130 ( .LO ( optlc_net_2779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3131 ( .LO ( optlc_net_2780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3132 ( .LO ( optlc_net_2781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3133 ( .LO ( optlc_net_2782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3134 ( .LO ( optlc_net_2783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3135 ( .LO ( optlc_net_2784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3136 ( .LO ( optlc_net_2785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3137 ( .LO ( optlc_net_2786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3138 ( .LO ( optlc_net_2787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3139 ( .LO ( optlc_net_2788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3140 ( .LO ( optlc_net_2789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3141 ( .LO ( optlc_net_2790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3142 ( .LO ( optlc_net_2791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3143 ( .LO ( optlc_net_2792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3144 ( .LO ( optlc_net_2793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3145 ( .LO ( optlc_net_2794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3146 ( .LO ( optlc_net_2795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3147 ( .LO ( optlc_net_2796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3148 ( .LO ( optlc_net_2797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3149 ( .LO ( optlc_net_2798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3150 ( .LO ( optlc_net_2799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3151 ( .LO ( optlc_net_2800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3152 ( .LO ( optlc_net_2801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3153 ( .LO ( optlc_net_2802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3154 ( .LO ( optlc_net_2803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3156 ( .LO ( optlc_net_2804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3157 ( .LO ( optlc_net_2805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3158 ( .LO ( optlc_net_2806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3159 ( .LO ( optlc_net_2807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3160 ( .LO ( optlc_net_2808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3161 ( .LO ( optlc_net_2809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3162 ( .LO ( optlc_net_2810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3163 ( .LO ( optlc_net_2811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3164 ( .LO ( optlc_net_2812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3166 ( .LO ( optlc_net_2813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3167 ( .LO ( optlc_net_2814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3168 ( .LO ( optlc_net_2815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3170 ( .LO ( optlc_net_2816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3171 ( .LO ( optlc_net_2817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3172 ( .LO ( optlc_net_2818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3173 ( .LO ( optlc_net_2819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3174 ( .LO ( optlc_net_2820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3175 ( .LO ( optlc_net_2821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3176 ( .LO ( optlc_net_2822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3177 ( .LO ( optlc_net_2823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3178 ( .LO ( optlc_net_2824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3179 ( .LO ( optlc_net_2825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3180 ( .LO ( optlc_net_2826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3181 ( .LO ( optlc_net_2827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3182 ( .LO ( optlc_net_2828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3183 ( .LO ( optlc_net_2829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3184 ( .LO ( optlc_net_2830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3185 ( .LO ( optlc_net_2831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3186 ( .LO ( optlc_net_2832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3187 ( .LO ( optlc_net_2833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3188 ( .LO ( optlc_net_2834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3190 ( .LO ( optlc_net_2835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3191 ( .LO ( optlc_net_2836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3192 ( .LO ( optlc_net_2837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3193 ( .LO ( optlc_net_2838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3194 ( .LO ( optlc_net_2839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3195 ( .LO ( optlc_net_2840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3196 ( .LO ( optlc_net_2841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3197 ( .LO ( optlc_net_2842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3198 ( .LO ( optlc_net_2843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3199 ( .LO ( optlc_net_2844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3200 ( .LO ( optlc_net_2845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3201 ( .LO ( optlc_net_2846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3202 ( .LO ( optlc_net_2847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3204 ( .LO ( optlc_net_2848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3205 ( .LO ( optlc_net_2849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3206 ( .LO ( optlc_net_2850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3207 ( .LO ( optlc_net_2851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3208 ( .LO ( optlc_net_2852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3209 ( .LO ( optlc_net_2853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3210 ( .LO ( optlc_net_2854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3211 ( .LO ( optlc_net_2855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3212 ( .LO ( optlc_net_2856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3213 ( .LO ( optlc_net_2857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3214 ( .LO ( optlc_net_2858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3215 ( .LO ( optlc_net_2859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3216 ( .LO ( optlc_net_2860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3217 ( .LO ( optlc_net_2861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3218 ( .LO ( optlc_net_2862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3219 ( .LO ( optlc_net_2863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3220 ( .LO ( optlc_net_2864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3221 ( .LO ( optlc_net_2865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3222 ( .LO ( optlc_net_2866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3223 ( .LO ( optlc_net_2867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3224 ( .LO ( optlc_net_2868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3225 ( .LO ( optlc_net_2869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3226 ( .LO ( optlc_net_2870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3227 ( .LO ( optlc_net_2871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3228 ( .LO ( optlc_net_2872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3229 ( .LO ( optlc_net_2873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3230 ( .LO ( optlc_net_2874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3231 ( .LO ( optlc_net_2875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3232 ( .LO ( optlc_net_2876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3233 ( .LO ( optlc_net_2877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3234 ( .LO ( optlc_net_2878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3235 ( .LO ( optlc_net_2879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3236 ( .LO ( optlc_net_2880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3237 ( .LO ( optlc_net_2881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3238 ( .LO ( optlc_net_2882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3240 ( .LO ( optlc_net_2883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3241 ( .LO ( optlc_net_2884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3242 ( .LO ( optlc_net_2885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3243 ( .LO ( optlc_net_2886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3244 ( .LO ( optlc_net_2887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3245 ( .LO ( optlc_net_2888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3246 ( .LO ( optlc_net_2889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3247 ( .LO ( optlc_net_2890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3248 ( .LO ( optlc_net_2891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3249 ( .LO ( optlc_net_2892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3250 ( .LO ( optlc_net_2893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3251 ( .LO ( optlc_net_2894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3252 ( .LO ( optlc_net_2895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3253 ( .LO ( optlc_net_2896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3254 ( .LO ( optlc_net_2897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3255 ( .LO ( optlc_net_2898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3256 ( .LO ( optlc_net_2899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3257 ( .LO ( optlc_net_2900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3258 ( .LO ( optlc_net_2901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3259 ( .LO ( optlc_net_2902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3260 ( .LO ( optlc_net_2903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3261 ( .LO ( optlc_net_2904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3262 ( .LO ( optlc_net_2905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3263 ( .LO ( optlc_net_2906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3264 ( .LO ( optlc_net_2907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3265 ( .LO ( optlc_net_2908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3266 ( .LO ( optlc_net_2909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3267 ( .LO ( optlc_net_2910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3268 ( .LO ( optlc_net_2911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3269 ( .LO ( optlc_net_2912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3270 ( .LO ( optlc_net_2913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3271 ( .LO ( optlc_net_2914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3272 ( .LO ( optlc_net_2915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3273 ( .LO ( optlc_net_2916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3274 ( .LO ( optlc_net_2917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3275 ( .LO ( optlc_net_2918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3276 ( .LO ( optlc_net_2919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3277 ( .LO ( optlc_net_2920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3278 ( .LO ( optlc_net_2921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3279 ( .LO ( optlc_net_2922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3280 ( .LO ( optlc_net_2923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3281 ( .LO ( optlc_net_2924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3282 ( .LO ( optlc_net_2925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3283 ( .LO ( optlc_net_2926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3284 ( .LO ( optlc_net_2927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3285 ( .LO ( optlc_net_2928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3286 ( .LO ( optlc_net_2929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3287 ( .LO ( optlc_net_2930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3288 ( .LO ( optlc_net_2931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3289 ( .LO ( optlc_net_2932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3290 ( .LO ( optlc_net_2933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3291 ( .LO ( optlc_net_2934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3292 ( .LO ( optlc_net_2935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3293 ( .LO ( optlc_net_2936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3294 ( .LO ( optlc_net_2937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3295 ( .LO ( optlc_net_2938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3296 ( .LO ( optlc_net_2939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3297 ( .LO ( optlc_net_2940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3298 ( .LO ( optlc_net_2941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3299 ( .LO ( optlc_net_2942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3300 ( .LO ( optlc_net_2943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3301 ( .LO ( optlc_net_2944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3302 ( .LO ( optlc_net_2945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3303 ( .LO ( optlc_net_2946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3304 ( .LO ( optlc_net_2947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3305 ( .LO ( optlc_net_2948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3306 ( .LO ( optlc_net_2949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3307 ( .LO ( optlc_net_2950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3308 ( .LO ( optlc_net_2951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3309 ( .LO ( optlc_net_2952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3310 ( .LO ( optlc_net_2953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3311 ( .LO ( optlc_net_2954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3312 ( .LO ( optlc_net_2955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3313 ( .LO ( optlc_net_2956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3314 ( .LO ( optlc_net_2957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3315 ( .LO ( optlc_net_2958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3316 ( .LO ( optlc_net_2959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3317 ( .LO ( optlc_net_2960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3318 ( .LO ( optlc_net_2961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3319 ( .LO ( optlc_net_2962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3320 ( .LO ( optlc_net_2963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3321 ( .LO ( optlc_net_2964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3322 ( .LO ( optlc_net_2965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3323 ( .LO ( optlc_net_2966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3324 ( .LO ( optlc_net_2967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3325 ( .LO ( optlc_net_2968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3326 ( .LO ( optlc_net_2969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3327 ( .LO ( optlc_net_2970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3328 ( .LO ( optlc_net_2971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3329 ( .LO ( optlc_net_2972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3330 ( .LO ( optlc_net_2973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3331 ( .LO ( optlc_net_2974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3332 ( .LO ( optlc_net_2975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3333 ( .LO ( optlc_net_2976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3334 ( .LO ( optlc_net_2977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3335 ( .LO ( optlc_net_2978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3336 ( .LO ( optlc_net_2979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3337 ( .LO ( optlc_net_2980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3338 ( .LO ( optlc_net_2981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3339 ( .LO ( optlc_net_2982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3340 ( .LO ( optlc_net_2983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3341 ( .LO ( optlc_net_2984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3342 ( .LO ( optlc_net_2985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3343 ( .LO ( optlc_net_2986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3344 ( .LO ( optlc_net_2987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3345 ( .LO ( optlc_net_2988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3346 ( .LO ( optlc_net_2989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3347 ( .LO ( optlc_net_2990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3348 ( .LO ( optlc_net_2991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3349 ( .LO ( optlc_net_2992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3350 ( .LO ( optlc_net_2993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3351 ( .LO ( optlc_net_2994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3352 ( .LO ( optlc_net_2995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3353 ( .LO ( optlc_net_2996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3354 ( .LO ( optlc_net_2997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3355 ( .LO ( optlc_net_2998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3356 ( .LO ( optlc_net_2999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3357 ( .LO ( optlc_net_3000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3358 ( .LO ( optlc_net_3001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3359 ( .LO ( optlc_net_3002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3360 ( .LO ( optlc_net_3003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3361 ( .LO ( optlc_net_3004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3362 ( .LO ( optlc_net_3005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3363 ( .LO ( optlc_net_3006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3364 ( .LO ( optlc_net_3007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3365 ( .LO ( optlc_net_3008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3366 ( .LO ( optlc_net_3009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3367 ( .LO ( optlc_net_3010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3368 ( .LO ( optlc_net_3011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3369 ( .LO ( optlc_net_3012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3370 ( .LO ( optlc_net_3013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3371 ( .LO ( optlc_net_3014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3372 ( .LO ( optlc_net_3015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3373 ( .LO ( optlc_net_3016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3374 ( .LO ( optlc_net_3017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3375 ( .LO ( optlc_net_3018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3376 ( .LO ( optlc_net_3019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3377 ( .LO ( optlc_net_3020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3378 ( .LO ( optlc_net_3021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3379 ( .LO ( optlc_net_3022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3380 ( .LO ( optlc_net_3023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3381 ( .LO ( optlc_net_3024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3382 ( .LO ( optlc_net_3025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3383 ( .LO ( optlc_net_3026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3384 ( .LO ( optlc_net_3027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3385 ( .LO ( optlc_net_3028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3386 ( .LO ( optlc_net_3029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3387 ( .LO ( optlc_net_3030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3388 ( .LO ( optlc_net_3031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3389 ( .LO ( optlc_net_3032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3390 ( .LO ( optlc_net_3033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3391 ( .LO ( optlc_net_3034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3392 ( .LO ( optlc_net_3035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3393 ( .LO ( optlc_net_3036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3394 ( .LO ( optlc_net_3037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3395 ( .LO ( optlc_net_3038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3396 ( .LO ( optlc_net_3039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3397 ( .LO ( optlc_net_3040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3398 ( .LO ( optlc_net_3041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3399 ( .LO ( optlc_net_3042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3400 ( .LO ( optlc_net_3043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3401 ( .LO ( optlc_net_3044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3402 ( .LO ( optlc_net_3045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3403 ( .LO ( optlc_net_3046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3404 ( .LO ( optlc_net_3047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3405 ( .LO ( optlc_net_3048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3406 ( .LO ( optlc_net_3049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3407 ( .LO ( optlc_net_3050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3408 ( .LO ( optlc_net_3051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3409 ( .LO ( optlc_net_3052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3410 ( .LO ( optlc_net_3053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3411 ( .LO ( optlc_net_3054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3412 ( .LO ( optlc_net_3055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3413 ( .LO ( optlc_net_3056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3414 ( .LO ( optlc_net_3057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3415 ( .LO ( optlc_net_3058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3416 ( .LO ( optlc_net_3059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3417 ( .LO ( optlc_net_3060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3418 ( .LO ( optlc_net_3061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3419 ( .LO ( optlc_net_3062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3420 ( .LO ( optlc_net_3063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3421 ( .LO ( optlc_net_3064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3422 ( .LO ( optlc_net_3065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3423 ( .LO ( optlc_net_3066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3424 ( .LO ( optlc_net_3067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3425 ( .LO ( optlc_net_3068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3426 ( .LO ( optlc_net_3069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3427 ( .LO ( optlc_net_3070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3428 ( .LO ( optlc_net_3071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3429 ( .LO ( optlc_net_3072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3430 ( .LO ( optlc_net_3073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3431 ( .LO ( optlc_net_3074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3432 ( .LO ( optlc_net_3075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3433 ( .LO ( optlc_net_3076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3434 ( .LO ( optlc_net_3077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3435 ( .LO ( optlc_net_3078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3436 ( .LO ( optlc_net_3079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3437 ( .LO ( optlc_net_3080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3438 ( .LO ( optlc_net_3081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3439 ( .LO ( optlc_net_3082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3440 ( .LO ( optlc_net_3083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3441 ( .LO ( optlc_net_3084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3442 ( .LO ( optlc_net_3085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3443 ( .LO ( optlc_net_3086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3444 ( .LO ( optlc_net_3087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3445 ( .LO ( optlc_net_3088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3446 ( .LO ( optlc_net_3089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3447 ( .LO ( optlc_net_3090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3448 ( .LO ( optlc_net_3091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3449 ( .LO ( optlc_net_3092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3450 ( .LO ( optlc_net_3093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3451 ( .LO ( optlc_net_3094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3452 ( .LO ( optlc_net_3095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3453 ( .LO ( optlc_net_3096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3454 ( .LO ( optlc_net_3097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3455 ( .LO ( optlc_net_3098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3456 ( .LO ( optlc_net_3099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3457 ( .LO ( optlc_net_3100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3458 ( .LO ( optlc_net_3101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3459 ( .LO ( optlc_net_3102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3460 ( .LO ( optlc_net_3103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3461 ( .LO ( optlc_net_3104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3462 ( .LO ( optlc_net_3105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3463 ( .LO ( optlc_net_3106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3464 ( .LO ( optlc_net_3107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3465 ( .LO ( optlc_net_3108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3466 ( .LO ( optlc_net_3109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3467 ( .LO ( optlc_net_3110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3468 ( .LO ( optlc_net_3111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3469 ( .LO ( optlc_net_3112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3470 ( .LO ( optlc_net_3113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3471 ( .LO ( optlc_net_3114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3472 ( .LO ( optlc_net_3115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3473 ( .LO ( optlc_net_3116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3474 ( .LO ( optlc_net_3117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3475 ( .LO ( optlc_net_3118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3476 ( .LO ( optlc_net_3119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3477 ( .LO ( optlc_net_3120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3478 ( .LO ( optlc_net_3121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3479 ( .LO ( optlc_net_3122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3480 ( .LO ( optlc_net_3123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3481 ( .LO ( optlc_net_3124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3482 ( .LO ( optlc_net_3125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3483 ( .LO ( optlc_net_3126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3484 ( .LO ( optlc_net_3127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3485 ( .LO ( optlc_net_3128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3486 ( .LO ( optlc_net_3129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3487 ( .LO ( optlc_net_3130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3488 ( .LO ( optlc_net_3131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3489 ( .LO ( optlc_net_3132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3490 ( .LO ( optlc_net_3133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3491 ( .LO ( optlc_net_3134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3492 ( .LO ( optlc_net_3135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3493 ( .LO ( optlc_net_3136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3494 ( .LO ( optlc_net_3137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3495 ( .LO ( optlc_net_3138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3496 ( .LO ( optlc_net_3139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3497 ( .LO ( optlc_net_3140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3498 ( .LO ( optlc_net_3141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3499 ( .LO ( optlc_net_3142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3500 ( .LO ( optlc_net_3143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3501 ( .LO ( optlc_net_3144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3502 ( .LO ( optlc_net_3145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3503 ( .LO ( optlc_net_3146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3504 ( .LO ( optlc_net_3147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3505 ( .LO ( optlc_net_3148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3506 ( .LO ( optlc_net_3149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3507 ( .LO ( optlc_net_3150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3509 ( .LO ( optlc_net_3151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3510 ( .LO ( optlc_net_3152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3511 ( .LO ( optlc_net_3153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3512 ( .LO ( optlc_net_3154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3513 ( .LO ( optlc_net_3155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3514 ( .LO ( optlc_net_3156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3515 ( .LO ( optlc_net_3157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3516 ( .LO ( optlc_net_3158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3517 ( .LO ( optlc_net_3159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3518 ( .LO ( optlc_net_3160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3519 ( .LO ( optlc_net_3161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3520 ( .LO ( optlc_net_3162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3521 ( .LO ( optlc_net_3163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3522 ( .LO ( optlc_net_3164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3523 ( .LO ( optlc_net_3165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3524 ( .LO ( optlc_net_3166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3525 ( .LO ( optlc_net_3167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3526 ( .LO ( optlc_net_3168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3527 ( .LO ( optlc_net_3169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3528 ( .LO ( optlc_net_3170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3529 ( .LO ( optlc_net_3171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3530 ( .LO ( optlc_net_3172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3531 ( .LO ( optlc_net_3173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3532 ( .LO ( optlc_net_3174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3533 ( .LO ( optlc_net_3175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3534 ( .LO ( optlc_net_3176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3535 ( .LO ( optlc_net_3177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3536 ( .LO ( optlc_net_3178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3537 ( .LO ( optlc_net_3179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3538 ( .LO ( optlc_net_3180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3539 ( .LO ( optlc_net_3181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3540 ( .LO ( optlc_net_3182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3541 ( .LO ( optlc_net_3183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3542 ( .LO ( optlc_net_3184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3543 ( .LO ( optlc_net_3185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3544 ( .LO ( optlc_net_3186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3545 ( .LO ( optlc_net_3187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3546 ( .LO ( optlc_net_3188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3547 ( .LO ( optlc_net_3189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3548 ( .LO ( optlc_net_3190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3549 ( .LO ( optlc_net_3191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3550 ( .LO ( optlc_net_3192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3551 ( .LO ( optlc_net_3193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3552 ( .LO ( optlc_net_3194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3553 ( .LO ( optlc_net_3195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3554 ( .LO ( optlc_net_3196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3555 ( .LO ( optlc_net_3197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3556 ( .LO ( optlc_net_3198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3557 ( .LO ( optlc_net_3199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3558 ( .LO ( optlc_net_3200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3559 ( .LO ( optlc_net_3201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3560 ( .LO ( optlc_net_3202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3561 ( .LO ( optlc_net_3203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3562 ( .LO ( optlc_net_3204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3563 ( .LO ( optlc_net_3205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3564 ( .LO ( optlc_net_3206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3565 ( .LO ( optlc_net_3207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3566 ( .LO ( optlc_net_3208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3567 ( .LO ( optlc_net_3209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3568 ( .LO ( optlc_net_3210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3569 ( .LO ( optlc_net_3211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3570 ( .LO ( optlc_net_3212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3571 ( .LO ( optlc_net_3213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3572 ( .LO ( optlc_net_3214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3573 ( .LO ( optlc_net_3215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3574 ( .LO ( optlc_net_3216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3575 ( .LO ( optlc_net_3217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3576 ( .LO ( optlc_net_3218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3577 ( .LO ( optlc_net_3219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3578 ( .LO ( optlc_net_3220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3579 ( .LO ( optlc_net_3221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3580 ( .LO ( optlc_net_3222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3581 ( .LO ( optlc_net_3223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3582 ( .LO ( optlc_net_3224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3583 ( .LO ( optlc_net_3225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3584 ( .LO ( optlc_net_3226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3585 ( .LO ( optlc_net_3227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3586 ( .LO ( optlc_net_3228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3587 ( .LO ( optlc_net_3229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3588 ( .LO ( optlc_net_3230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3589 ( .LO ( optlc_net_3231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3590 ( .LO ( optlc_net_3232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3591 ( .LO ( optlc_net_3233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3592 ( .LO ( optlc_net_3234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3593 ( .LO ( optlc_net_3235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3594 ( .LO ( optlc_net_3236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3595 ( .LO ( optlc_net_3237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3596 ( .LO ( optlc_net_3238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3597 ( .LO ( optlc_net_3239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3598 ( .LO ( optlc_net_3240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3599 ( .LO ( optlc_net_3241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3600 ( .LO ( optlc_net_3242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3601 ( .LO ( optlc_net_3243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3602 ( .LO ( optlc_net_3244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3603 ( .LO ( optlc_net_3245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3604 ( .LO ( optlc_net_3246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3605 ( .LO ( optlc_net_3247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3606 ( .LO ( optlc_net_3248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3607 ( .LO ( optlc_net_3249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3608 ( .LO ( optlc_net_3250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3609 ( .LO ( optlc_net_3251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3610 ( .LO ( optlc_net_3252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3611 ( .LO ( optlc_net_3253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3612 ( .LO ( optlc_net_3254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3613 ( .LO ( optlc_net_3255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3614 ( .LO ( optlc_net_3256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3615 ( .LO ( optlc_net_3257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3616 ( .LO ( optlc_net_3258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3617 ( .LO ( optlc_net_3259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3618 ( .LO ( optlc_net_3260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3619 ( .LO ( optlc_net_3261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3620 ( .LO ( optlc_net_3262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3621 ( .LO ( optlc_net_3263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3622 ( .LO ( optlc_net_3264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3623 ( .LO ( optlc_net_3265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3624 ( .LO ( optlc_net_3266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3625 ( .LO ( optlc_net_3267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3626 ( .LO ( optlc_net_3268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3627 ( .LO ( optlc_net_3269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3628 ( .LO ( optlc_net_3270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3629 ( .LO ( optlc_net_3271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3630 ( .LO ( optlc_net_3272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3631 ( .LO ( optlc_net_3273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3632 ( .LO ( optlc_net_3274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3633 ( .LO ( optlc_net_3275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3634 ( .LO ( optlc_net_3276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3635 ( .LO ( optlc_net_3277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3636 ( .LO ( optlc_net_3278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3637 ( .LO ( optlc_net_3279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3638 ( .LO ( optlc_net_3280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3639 ( .LO ( optlc_net_3281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3640 ( .LO ( optlc_net_3282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3641 ( .LO ( optlc_net_3283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3642 ( .LO ( optlc_net_3284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3643 ( .LO ( optlc_net_3285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3644 ( .LO ( optlc_net_3286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3645 ( .LO ( optlc_net_3287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3646 ( .LO ( optlc_net_3288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3647 ( .LO ( optlc_net_3289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3648 ( .LO ( optlc_net_3290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3649 ( .LO ( optlc_net_3291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3650 ( .LO ( optlc_net_3292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3651 ( .LO ( optlc_net_3293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3652 ( .LO ( optlc_net_3294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3653 ( .LO ( optlc_net_3295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3654 ( .LO ( optlc_net_3296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3655 ( .LO ( optlc_net_3297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3656 ( .LO ( optlc_net_3298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3657 ( .LO ( optlc_net_3299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3658 ( .LO ( optlc_net_3300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3659 ( .LO ( optlc_net_3301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3660 ( .LO ( optlc_net_3302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3661 ( .LO ( optlc_net_3303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3662 ( .LO ( optlc_net_3304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3663 ( .LO ( optlc_net_3305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3664 ( .LO ( optlc_net_3306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3665 ( .LO ( optlc_net_3307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3666 ( .LO ( optlc_net_3308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3667 ( .LO ( optlc_net_3309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3668 ( .LO ( optlc_net_3310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3669 ( .LO ( optlc_net_3311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3670 ( .LO ( optlc_net_3312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3671 ( .LO ( optlc_net_3313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3672 ( .LO ( optlc_net_3314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3673 ( .LO ( optlc_net_3315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3674 ( .LO ( optlc_net_3316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3675 ( .LO ( optlc_net_3317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3676 ( .LO ( optlc_net_3318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3677 ( .LO ( optlc_net_3319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3678 ( .LO ( optlc_net_3320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3679 ( .LO ( optlc_net_3321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3680 ( .LO ( optlc_net_3322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3681 ( .LO ( optlc_net_3323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3682 ( .LO ( optlc_net_3324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3683 ( .LO ( optlc_net_3325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3684 ( .LO ( optlc_net_3326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3685 ( .LO ( optlc_net_3327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3686 ( .LO ( optlc_net_3328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3687 ( .LO ( optlc_net_3329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3688 ( .LO ( optlc_net_3330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3689 ( .LO ( optlc_net_3331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3690 ( .LO ( optlc_net_3332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3691 ( .LO ( optlc_net_3333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3692 ( .LO ( optlc_net_3334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3693 ( .LO ( optlc_net_3335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3694 ( .LO ( optlc_net_3336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3695 ( .LO ( optlc_net_3337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3696 ( .LO ( optlc_net_3338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3697 ( .LO ( optlc_net_3339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3698 ( .LO ( optlc_net_3340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3699 ( .LO ( optlc_net_3341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3700 ( .LO ( optlc_net_3342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3701 ( .LO ( optlc_net_3343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3702 ( .LO ( optlc_net_3344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3703 ( .LO ( optlc_net_3345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3704 ( .LO ( optlc_net_3346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3705 ( .LO ( optlc_net_3347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3706 ( .LO ( optlc_net_3348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3707 ( .LO ( optlc_net_3349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3708 ( .LO ( optlc_net_3350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3709 ( .LO ( optlc_net_3351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3710 ( .LO ( optlc_net_3352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3711 ( .LO ( optlc_net_3353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3712 ( .LO ( optlc_net_3354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3713 ( .LO ( optlc_net_3355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3714 ( .LO ( optlc_net_3356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3715 ( .LO ( optlc_net_3357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3716 ( .LO ( optlc_net_3358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3717 ( .LO ( optlc_net_3359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3718 ( .LO ( optlc_net_3360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3719 ( .LO ( optlc_net_3361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3720 ( .LO ( optlc_net_3362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3721 ( .LO ( optlc_net_3363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3722 ( .LO ( optlc_net_3364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3723 ( .LO ( optlc_net_3365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3724 ( .LO ( optlc_net_3366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3725 ( .LO ( optlc_net_3367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3726 ( .LO ( optlc_net_3368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3727 ( .LO ( optlc_net_3369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3728 ( .LO ( optlc_net_3370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3729 ( .LO ( optlc_net_3371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3730 ( .LO ( optlc_net_3372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3731 ( .LO ( optlc_net_3373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3732 ( .LO ( optlc_net_3374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3733 ( .LO ( optlc_net_3375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3734 ( .LO ( optlc_net_3376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3735 ( .LO ( optlc_net_3377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3736 ( .LO ( optlc_net_3378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3737 ( .LO ( optlc_net_3379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3738 ( .LO ( optlc_net_3380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3739 ( .LO ( optlc_net_3381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3740 ( .LO ( optlc_net_3382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3741 ( .LO ( optlc_net_3383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3742 ( .LO ( optlc_net_3384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3743 ( .LO ( optlc_net_3385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3744 ( .LO ( optlc_net_3386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3745 ( .LO ( optlc_net_3387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3746 ( .LO ( optlc_net_3388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3747 ( .LO ( optlc_net_3389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3748 ( .LO ( optlc_net_3390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3749 ( .LO ( optlc_net_3391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3750 ( .LO ( optlc_net_3392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3751 ( .LO ( optlc_net_3393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3752 ( .LO ( optlc_net_3394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3753 ( .LO ( optlc_net_3395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3754 ( .LO ( optlc_net_3396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3755 ( .LO ( optlc_net_3397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3756 ( .LO ( optlc_net_3398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3757 ( .LO ( optlc_net_3399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3758 ( .LO ( optlc_net_3400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3759 ( .LO ( optlc_net_3401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3760 ( .LO ( optlc_net_3402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3761 ( .LO ( optlc_net_3403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3762 ( .LO ( optlc_net_3404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3763 ( .LO ( optlc_net_3405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3764 ( .LO ( optlc_net_3406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3765 ( .LO ( optlc_net_3407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3766 ( .LO ( optlc_net_3408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3767 ( .LO ( optlc_net_3409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3768 ( .LO ( optlc_net_3410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3769 ( .LO ( optlc_net_3411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3770 ( .LO ( optlc_net_3412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3771 ( .LO ( optlc_net_3413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3772 ( .LO ( optlc_net_3414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3773 ( .LO ( optlc_net_3415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3774 ( .LO ( optlc_net_3416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3775 ( .LO ( optlc_net_3417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3776 ( .LO ( optlc_net_3418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3777 ( .LO ( optlc_net_3419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3778 ( .LO ( optlc_net_3420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3779 ( .LO ( optlc_net_3421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3780 ( .LO ( optlc_net_3422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3781 ( .LO ( optlc_net_3423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3782 ( .LO ( optlc_net_3424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3783 ( .LO ( optlc_net_3425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3784 ( .LO ( optlc_net_3426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3785 ( .LO ( optlc_net_3427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3786 ( .LO ( optlc_net_3428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3787 ( .LO ( optlc_net_3429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3788 ( .LO ( optlc_net_3430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3789 ( .LO ( optlc_net_3431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3790 ( .LO ( optlc_net_3432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3791 ( .LO ( optlc_net_3433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3792 ( .LO ( optlc_net_3434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3793 ( .LO ( optlc_net_3435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3794 ( .LO ( optlc_net_3436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3795 ( .LO ( optlc_net_3437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3796 ( .LO ( optlc_net_3438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3797 ( .LO ( optlc_net_3439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3798 ( .LO ( optlc_net_3440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3799 ( .LO ( optlc_net_3441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3800 ( .LO ( optlc_net_3442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3801 ( .LO ( optlc_net_3443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3802 ( .LO ( optlc_net_3444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3803 ( .LO ( optlc_net_3445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3804 ( .LO ( optlc_net_3446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3805 ( .LO ( optlc_net_3447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3806 ( .LO ( optlc_net_3448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3807 ( .LO ( optlc_net_3449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3808 ( .LO ( optlc_net_3450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3809 ( .LO ( optlc_net_3451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3810 ( .LO ( optlc_net_3452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3811 ( .LO ( optlc_net_3453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3812 ( .LO ( optlc_net_3454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3813 ( .LO ( optlc_net_3455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3814 ( .LO ( optlc_net_3456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3815 ( .LO ( optlc_net_3457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3816 ( .LO ( optlc_net_3458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3817 ( .LO ( optlc_net_3459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3818 ( .LO ( optlc_net_3460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3819 ( .LO ( optlc_net_3461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3820 ( .LO ( optlc_net_3462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3821 ( .LO ( optlc_net_3463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3822 ( .LO ( optlc_net_3464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3823 ( .LO ( optlc_net_3465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3824 ( .LO ( optlc_net_3466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3825 ( .LO ( optlc_net_3467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3826 ( .LO ( optlc_net_3468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3827 ( .LO ( optlc_net_3469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3828 ( .LO ( optlc_net_3470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3829 ( .LO ( optlc_net_3471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3830 ( .LO ( optlc_net_3472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3831 ( .LO ( optlc_net_3473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3832 ( .LO ( optlc_net_3474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3833 ( .LO ( optlc_net_3475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3834 ( .LO ( optlc_net_3476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3835 ( .LO ( optlc_net_3477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3836 ( .LO ( optlc_net_3478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3837 ( .LO ( optlc_net_3479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3838 ( .LO ( optlc_net_3480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3839 ( .LO ( optlc_net_3481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3840 ( .LO ( optlc_net_3482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3841 ( .LO ( optlc_net_3483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3842 ( .LO ( optlc_net_3484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3843 ( .LO ( optlc_net_3485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3844 ( .LO ( optlc_net_3486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3845 ( .LO ( optlc_net_3487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3846 ( .LO ( optlc_net_3488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3847 ( .LO ( optlc_net_3489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3848 ( .LO ( optlc_net_3490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3849 ( .LO ( optlc_net_3491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3850 ( .LO ( optlc_net_3492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3851 ( .LO ( optlc_net_3493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3852 ( .LO ( optlc_net_3494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3853 ( .LO ( optlc_net_3495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3854 ( .LO ( optlc_net_3496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3855 ( .LO ( optlc_net_3497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3856 ( .LO ( optlc_net_3498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3857 ( .LO ( optlc_net_3499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3858 ( .LO ( optlc_net_3500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3859 ( .LO ( optlc_net_3501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3860 ( .LO ( optlc_net_3502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3861 ( .LO ( optlc_net_3503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3862 ( .LO ( optlc_net_3504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3863 ( .LO ( optlc_net_3505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3864 ( .LO ( optlc_net_3506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3865 ( .LO ( optlc_net_3507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3866 ( .LO ( optlc_net_3508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3867 ( .LO ( optlc_net_3509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3868 ( .LO ( optlc_net_3510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3869 ( .LO ( optlc_net_3511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3870 ( .LO ( optlc_net_3512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3871 ( .LO ( optlc_net_3513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3872 ( .LO ( optlc_net_3514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3873 ( .LO ( optlc_net_3515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3874 ( .LO ( optlc_net_3516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3609 ) ) ;
+endmodule
+
+
diff --git a/SOFA_HD/README.md b/SOFA_HD/README.md
new file mode 100644
index 0000000..90624ee
--- /dev/null
+++ b/SOFA_HD/README.md
@@ -0,0 +1,4 @@
+# FPGA1212_SOFA_HD_PNR
+
+12x12 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`.
+Flat Module design style
diff --git a/SOFA_HD/fpga_top/fpga_top_icv_in_design.gds.gz b/SOFA_HD/fpga_top/fpga_top_icv_in_design.gds.gz
new file mode 100644
index 0000000..a31374c
--- /dev/null
+++ b/SOFA_HD/fpga_top/fpga_top_icv_in_design.gds.gz
Binary files differ
diff --git a/SOFA_HD/fpga_top/fpga_top_icv_in_design.lef b/SOFA_HD/fpga_top/fpga_top_icv_in_design.lef
new file mode 100644
index 0000000..bc1a90d
--- /dev/null
+++ b/SOFA_HD/fpga_top/fpga_top_icv_in_design.lef
@@ -0,0 +1,352 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+ DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.46 ;
+ WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+ TYPE CUT ;
+END mcon
+
+LAYER met1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 0.34 ;
+ WIDTH 0.14 ;
+END met1
+
+LAYER via
+ TYPE CUT ;
+END via
+
+LAYER met2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.46 ;
+ WIDTH 0.14 ;
+END met2
+
+LAYER via2
+ TYPE CUT ;
+END via2
+
+LAYER met3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 0.68 ;
+ WIDTH 0.3 ;
+END met3
+
+LAYER via3
+ TYPE CUT ;
+END via3
+
+LAYER met4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.92 ;
+ WIDTH 0.3 ;
+END met4
+
+LAYER via4
+ TYPE CUT ;
+END via4
+
+LAYER met5
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 3.4 ;
+ WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+ TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+ TYPE MASTERSLICE ;
+END pwell
+
+VIA L1M1_PR
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+ LAYER met1 ;
+ RECT -0.16 -0.16 0.16 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+ LAYER met2 ;
+ RECT -0.185 -0.185 0.185 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+ LAYER met3 ;
+ RECT -0.19 -0.19 0.19 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+ CLASS CORE ;
+ SYMMETRY Y ;
+ SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+ CLASS CORE ;
+ SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+END LIBRARY
diff --git a/SOFA_HD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz b/SOFA_HD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz
new file mode 100644
index 0000000..79c4506
--- /dev/null
+++ b/SOFA_HD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz
Binary files differ
diff --git a/SOFA_HD/fpga_top/fpga_top_icv_in_design.pt.v b/SOFA_HD/fpga_top/fpga_top_icv_in_design.pt.v
new file mode 100644
index 0000000..bd9b5ec
--- /dev/null
+++ b/SOFA_HD/fpga_top/fpga_top_icv_in_design.pt.v
@@ -0,0 +1,93235 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_88 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_88 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_89 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_88 ) ,
+ .X ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_86 ) ,
+ .X ( copt_net_87 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_87 ) ,
+ .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 copt_h_inst_1311 ( .A ( mem_out[0] ) ,
+ .X ( copt_net_89 ) ) ;
+endmodule
+
+
+module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_59 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_59 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_59 ( .A ( BUF_net_61 ) , .Y ( BUF_net_59 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_61 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_61 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head ,
+ iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_92 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ropt_net_94 ) ,
+ .X ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_79 ) ,
+ .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_80 ) ,
+ .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) ,
+ .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) ,
+ .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( copt_net_84 ) ,
+ .X ( ropt_net_92 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_82 ) ,
+ .X ( ropt_net_93 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_93 ) ,
+ .X ( ropt_net_94 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1_ ( chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ ,
+ left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ ,
+ left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ ,
+ left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ ,
+ left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ ,
+ left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ,
+ IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper ,
+ left_width_0_height_0__pin_1_lower , prog_clk_0_W_in , prog_clk_0_S_out ,
+ prog_clk_0_N_out ) ;
+input [0:19] chany_bottom_in ;
+input [0:19] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
+ chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] ,
+ chany_bottom_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
+ chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] ,
+ chany_bottom_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
+ chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] ,
+ chany_bottom_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_73 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
+ chany_top_out[9] , chany_bottom_out[9] , chany_top_out[15] ,
+ chany_bottom_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_73 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
+ chany_bottom_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_73 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] ,
+ chany_bottom_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_74 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[17] ,
+ chany_bottom_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
+ chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] ,
+ chany_bottom_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_73 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_7 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[14] , chany_bottom_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_74 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[15] , chany_bottom_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_73 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[18] , chany_bottom_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[19] , chany_bottom_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_73 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[14] , chany_bottom_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_73 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[15] , chany_bottom_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_74 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[18] , chany_bottom_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_74 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[19] , chany_bottom_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_73 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( left_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_177 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_278 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[1] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 (
+ .A ( left_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .HI ( optlc_net_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .HI ( optlc_net_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
+ .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) ,
+ .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+wire copt_net_84 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_84 ) ,
+ .X ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1316 ( .A ( copt_net_79 ) ,
+ .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1317 ( .A ( copt_net_80 ) ,
+ .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_81 ) ,
+ .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_82 ) ,
+ .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_83 ) ,
+ .X ( mem_out[3] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_91 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ccff_head[0] ) ,
+ .X ( ropt_net_88 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_92 ) ,
+ .X ( ropt_net_89 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_88 ) ,
+ .X ( ropt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1362 ( .A ( ropt_net_89 ) ,
+ .X ( ropt_net_91 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1363 ( .A ( ropt_net_90 ) ,
+ .X ( ropt_net_92 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_59 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_57 ) ) ;
+endmodule
+
+
+module cby_1__1_ ( chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ ,
+ left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ ,
+ left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ ,
+ left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ ,
+ left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ ,
+ left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in ,
+ Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out ,
+ Test_en_E_out , prog_clk_0_W_in , prog_clk_0_S_out , prog_clk_0_N_out ,
+ prog_clk_2_N_in , prog_clk_2_S_in , prog_clk_2_S_out , prog_clk_2_N_out ,
+ prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_N_out , prog_clk_3_S_out ,
+ clk_2_N_in , clk_2_S_in , clk_2_S_out , clk_2_N_out , clk_3_S_in ,
+ clk_3_N_in , clk_3_N_out , clk_3_S_out ) ;
+input [0:19] chany_bottom_in ;
+input [0:19] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input Test_en_S_in ;
+input Test_en_E_in ;
+input Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input prog_clk_2_N_in ;
+input prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input prog_clk_3_S_in ;
+input prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input clk_2_N_in ;
+input clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input clk_3_S_in ;
+input clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign Test_en_E_in = Test_en_S_in ;
+assign Test_en_E_in = Test_en_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
+
+cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
+ chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] ,
+ chany_bottom_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
+ chany_bottom_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
+ chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] ,
+ chany_bottom_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] ,
+ chany_bottom_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
+ chany_top_out[11] , chany_bottom_out[11] , chany_top_out[15] ,
+ chany_bottom_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_12 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] ,
+ chany_bottom_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[19] ,
+ chany_bottom_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
+ chany_top_out[13] , chany_bottom_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[14] , chany_bottom_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[17] , chany_bottom_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[18] , chany_bottom_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
+ chany_top_out[13] , chany_bottom_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[14] , chany_bottom_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[17] , chany_bottom_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[18] , chany_bottom_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( net_net_68 ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_177 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_278 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) ,
+ .X ( ropt_net_87 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) ,
+ .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) ,
+ .X ( prog_clk_3_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) ,
+ .X ( clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) ,
+ .X ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) ,
+ .X ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[1] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_67 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
+ .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) ,
+ .X ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) ,
+ .X ( clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) ,
+ .X ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) ,
+ .X ( prog_clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) ,
+ .X ( prog_clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_60 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) ,
+ .X ( copt_net_55 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) ,
+ .X ( copt_net_56 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) ,
+ .X ( copt_net_57 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) ,
+ .X ( copt_net_58 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) ,
+ .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) ,
+ .X ( copt_net_61 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_43 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_43 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_43 ( .A ( BUF_net_45 ) , .Y ( BUF_net_43 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_45 ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head ,
+ iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_49 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) ,
+ .X ( copt_net_50 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) ,
+ .X ( copt_net_51 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) ,
+ .X ( copt_net_52 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) ,
+ .X ( copt_net_53 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) ,
+ .X ( copt_net_54 ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_47 ) ) ;
+endmodule
+
+
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail ,
+ IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper ,
+ right_width_0_height_0__pin_1_lower , prog_clk_0_E_in ) ;
+input [0:19] chany_bottom_in ;
+input [0:19] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_67 ;
+wire ropt_net_68 ;
+wire ropt_net_66 ;
+wire ropt_net_65 ;
+wire ropt_net_63 ;
+wire ropt_net_69 ;
+wire ropt_net_64 ;
+wire ropt_net_62 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
+ chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
+ chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] ,
+ chany_bottom_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( right_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) ,
+ .X ( ropt_net_67 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) ,
+ .X ( ropt_net_68 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) ,
+ .X ( ropt_net_66 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) ,
+ .X ( ropt_net_65 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) ,
+ .X ( ropt_net_63 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) ,
+ .X ( ropt_net_69 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) ,
+ .X ( ropt_net_64 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) ,
+ .X ( ropt_net_62 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 (
+ .A ( right_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( optlc_net_48 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_86 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_84 ) ,
+ .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_86 ) ,
+ .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) ,
+ .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) ,
+ .X ( mem_out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( BUF_net_64 ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_64 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( BUF_net_63 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head ,
+ iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_95 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_75 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_75 ) ,
+ .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_76 ) ,
+ .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_77 ) ,
+ .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_78 ) ,
+ .X ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_79 ) ,
+ .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_80 ) ,
+ .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1314 ( .A ( ropt_net_94 ) ,
+ .X ( ropt_net_95 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2_ ( chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ ,
+ bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
+ bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
+ bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
+ ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper ,
+ bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT ,
+ SC_IN_BOT , SC_OUT_TOP , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+input [0:19] chanx_left_in ;
+input [0:19] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
+ chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
+ chanx_left_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
+ chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] ,
+ chanx_left_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
+ chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] ,
+ chanx_left_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
+ chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] ,
+ chanx_left_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] ,
+ chanx_left_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[17] ,
+ chanx_left_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
+ chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
+ chanx_left_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_7 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[14] , chanx_left_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[15] , chanx_left_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[18] , chanx_left_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[19] , chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[14] , chanx_left_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[15] , chanx_left_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[18] , chanx_left_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[19] , chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( bottom_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_174 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 (
+ .A ( bottom_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .HI ( optlc_net_73 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+wire copt_net_84 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_87 ) ,
+ .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_83 ) ,
+ .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_85 ) ,
+ .X ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_84 ) ,
+ .X ( copt_net_87 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_103 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) ,
+ .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_76 ) ,
+ .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_77 ) ,
+ .X ( copt_net_78 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_79 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_78 ) ,
+ .X ( copt_net_80 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_80 ) ,
+ .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1323 ( .A ( copt_net_81 ) ,
+ .X ( ropt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1324 ( .A ( ropt_net_102 ) ,
+ .X ( ropt_net_103 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1_ ( chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
+ bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
+ bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
+ bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
+ ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP ,
+ REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , prog_clk_0_N_in ,
+ prog_clk_0_W_out , prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out ,
+ prog_clk_1_S_out , prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out ,
+ prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out ,
+ prog_clk_3_W_out , clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out ,
+ clk_2_E_in , clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in ,
+ clk_3_E_in , clk_3_E_out , clk_3_W_out ) ;
+input [0:19] chanx_left_in ;
+input [0:19] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input REGIN_FEEDTHROUGH ;
+output REGOUT_FEEDTHROUGH ;
+input prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input prog_clk_1_W_in ;
+input prog_clk_1_E_in ;
+output prog_clk_1_N_out ;
+output prog_clk_1_S_out ;
+input prog_clk_2_E_in ;
+input prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_E_out ;
+input prog_clk_3_W_in ;
+input prog_clk_3_E_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+input clk_1_W_in ;
+input clk_1_E_in ;
+output clk_1_N_out ;
+output clk_1_S_out ;
+input clk_2_E_in ;
+input clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_E_out ;
+input clk_3_W_in ;
+input clk_3_E_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign clk_1_E_in = clk_1_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
+
+cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
+ chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
+ chanx_left_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
+ chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] ,
+ chanx_left_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] ,
+ chanx_left_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
+ chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[15] ,
+ chanx_left_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] ,
+ chanx_left_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[19] ,
+ chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
+ chanx_right_out[13] , chanx_left_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[14] , chanx_left_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[17] , chanx_left_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[18] , chanx_left_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
+ chanx_right_out[13] , chanx_left_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[14] , chanx_left_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[17] , chanx_left_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[18] , chanx_left_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
+ .X ( ctsbuf_net_175 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) ,
+ .X ( prog_clk_1_S_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) ,
+ .X ( net_net_69 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) ,
+ .X ( prog_clk_2_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) ,
+ .X ( prog_clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) ,
+ .X ( prog_clk_3_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) ,
+ .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) ,
+ .X ( clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) ,
+ .X ( clk_3_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_18__17 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) ,
+ .X ( REGOUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) ,
+ .Y ( prog_clk_1_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_68 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) ,
+ .X ( prog_clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
+ .HI ( optlc_net_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) ,
+ .HI ( optlc_net_74 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) ,
+ .X ( clk_3_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) ,
+ .X ( clk_1_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_122 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_122 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1346 ( .A ( copt_net_124 ) ,
+ .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_125 ) ,
+ .X ( copt_net_124 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_126 ) ,
+ .X ( copt_net_125 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_127 ) ,
+ .X ( copt_net_126 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_122 ) ,
+ .X ( copt_net_127 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) ,
+ .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_92 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head ,
+ iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_7 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_87 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_86 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_86 ( .A ( BUF_net_88 ) , .Y ( BUF_net_86 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( BUF_net_87 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_88 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_88 ) , .Y ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( BUF_net_81 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_80 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_8 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_507_ ) ,
+ .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_77 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_77 ( .A ( BUF_net_79 ) , .Y ( BUF_net_77 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( BUF_net_78 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_79 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( BUF_net_78 ) , .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_211_0 ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+input ZBUF_211_0 ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_211_0 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( ZBUF_211_0 ) , .Z ( SOC_OUT ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_211_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_211_0 ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ,
+ .ZBUF_211_0 ( ZBUF_211_0 ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail , ZBUF_211_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_211_0 ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ,
+ .ZBUF_211_0 ( ZBUF_211_0 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_506_ ) ,
+ .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_74 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_76 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_74 ( .A ( BUF_net_76 ) , .Y ( BUF_net_74 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) ,
+ .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_136 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_116 ) ,
+ .X ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_117 ) ,
+ .X ( copt_net_118 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_118 ) ,
+ .X ( copt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_119 ) ,
+ .X ( copt_net_120 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_120 ) ,
+ .X ( copt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_121 ) ,
+ .X ( ropt_net_136 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_105 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_103 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_96 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0_ ( chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
+ bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ ,
+ top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ ,
+ top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ ,
+ top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ ,
+ top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ ,
+ top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower ,
+ top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower ,
+ top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower ,
+ top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower ,
+ top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower ,
+ top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower ,
+ top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower ,
+ top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower ,
+ top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower ,
+ SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , prog_clk_0_N_in ,
+ prog_clk_0_W_out ) ;
+input [0:19] chanx_left_in ;
+input [0:19] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_16_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] top_width_0_height_0__pin_0_ ;
+input [0:0] top_width_0_height_0__pin_2_ ;
+input [0:0] top_width_0_height_0__pin_4_ ;
+input [0:0] top_width_0_height_0__pin_6_ ;
+input [0:0] top_width_0_height_0__pin_8_ ;
+input [0:0] top_width_0_height_0__pin_10_ ;
+input [0:0] top_width_0_height_0__pin_12_ ;
+input [0:0] top_width_0_height_0__pin_14_ ;
+input [0:0] top_width_0_height_0__pin_16_ ;
+output [0:0] top_width_0_height_0__pin_1_upper ;
+output [0:0] top_width_0_height_0__pin_1_lower ;
+output [0:0] top_width_0_height_0__pin_3_upper ;
+output [0:0] top_width_0_height_0__pin_3_lower ;
+output [0:0] top_width_0_height_0__pin_5_upper ;
+output [0:0] top_width_0_height_0__pin_5_lower ;
+output [0:0] top_width_0_height_0__pin_7_upper ;
+output [0:0] top_width_0_height_0__pin_7_lower ;
+output [0:0] top_width_0_height_0__pin_9_upper ;
+output [0:0] top_width_0_height_0__pin_9_lower ;
+output [0:0] top_width_0_height_0__pin_11_upper ;
+output [0:0] top_width_0_height_0__pin_11_lower ;
+output [0:0] top_width_0_height_0__pin_13_upper ;
+output [0:0] top_width_0_height_0__pin_13_lower ;
+output [0:0] top_width_0_height_0__pin_15_upper ;
+output [0:0] top_width_0_height_0__pin_15_lower ;
+output [0:0] top_width_0_height_0__pin_17_upper ;
+output [0:0] top_width_0_height_0__pin_17_lower ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
+ chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
+ chanx_left_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_112 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
+ chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] ,
+ chanx_left_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_112 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
+ chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] ,
+ chanx_left_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
+ chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] ,
+ chanx_left_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
+ chanx_left_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_112 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] ,
+ chanx_left_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_112 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
+ chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_113 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .io_outpad ( top_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( top_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) ,
+ .io_outpad ( top_width_0_height_0__pin_2_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_3_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) ,
+ .io_outpad ( top_width_0_height_0__pin_4_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_5_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ,
+ .ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) ,
+ .io_outpad ( top_width_0_height_0__pin_6_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_7_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ,
+ .io_outpad ( top_width_0_height_0__pin_8_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_9_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ,
+ .io_outpad ( top_width_0_height_0__pin_10_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_11_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) ,
+ .io_outpad ( top_width_0_height_0__pin_12_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_13_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ,
+ .io_outpad ( top_width_0_height_0__pin_14_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_15_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ,
+ .io_outpad ( top_width_0_height_0__pin_16_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_17_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
+ .X ( ctsbuf_net_1115 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 (
+ .A ( top_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 (
+ .A ( top_width_0_height_0__pin_3_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 (
+ .A ( top_width_0_height_0__pin_5_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_62__61 (
+ .A ( top_width_0_height_0__pin_7_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 (
+ .A ( top_width_0_height_0__pin_9_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_64__63 (
+ .A ( top_width_0_height_0__pin_11_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_65__64 (
+ .A ( top_width_0_height_0__pin_13_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_66__65 (
+ .A ( top_width_0_height_0__pin_15_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_67__66 (
+ .A ( top_width_0_height_0__pin_17_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) ,
+ .HI ( optlc_net_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) ,
+ .HI ( optlc_net_113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) ,
+ .HI ( optlc_net_114 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( copt_net_99 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) ,
+ .X ( copt_net_102 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_58 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_56 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_54 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_52 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_50 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_109 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1257 ( .A ( copt_net_95 ) ,
+ .X ( copt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_91 ) ,
+ .X ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_93 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) ,
+ .X ( copt_net_94 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) ,
+ .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_93 ) ,
+ .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) ,
+ .X ( ropt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1275 ( .A ( copt_net_92 ) ,
+ .X ( ropt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1276 ( .A ( ropt_net_110 ) ,
+ .X ( ropt_net_111 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_48 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_46 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_44 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_41 ( .A ( BUF_net_42 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_42 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_42 ) ) ;
+endmodule
+
+
+module sb_2__2_ ( chany_bottom_in , bottom_right_grid_pin_1_ ,
+ bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ ,
+ bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
+ bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
+ bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in ,
+ left_top_grid_pin_1_ , left_bottom_grid_pin_34_ ,
+ left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out ,
+ ccff_tail , SC_IN_BOT , SC_OUT_BOT , prog_clk_0_S_in ) ;
+input [0:19] chany_bottom_in ;
+input [0:0] bottom_right_grid_pin_1_ ;
+input [0:0] bottom_left_grid_pin_42_ ;
+input [0:0] bottom_left_grid_pin_43_ ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:19] chanx_left_in ;
+input [0:0] left_top_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_34_ ;
+input [0:0] left_bottom_grid_pin_35_ ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_BOT ;
+output SC_OUT_BOT ;
+input prog_clk_0_S_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+ .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 (
+ .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 (
+ .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] ,
+ chanx_left_in[2] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 (
+ .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] ,
+ chanx_left_in[4] } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+ .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
+ SYNOPSYS_UNCONNECTED_21 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_87 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 (
+ .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
+ SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_87 ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 (
+ .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_87 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 (
+ .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_87 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 (
+ .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_87 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 (
+ .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_87 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 (
+ .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 (
+ .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 (
+ .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 (
+ .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 (
+ .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 (
+ .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_87 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 (
+ .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 (
+ .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 (
+ .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 (
+ .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 (
+ .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 (
+ .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_87 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 (
+ .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 (
+ .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chanx_left_out[13] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 (
+ .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 (
+ .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 (
+ .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 (
+ .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 (
+ .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 (
+ .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_left_out[19] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_19 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_21 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_23 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_27 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_29 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] ,
+ chanx_left_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 (
+ .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 (
+ .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_88 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[0] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[16] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[17] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) ,
+ .HI ( optlc_net_87 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) ,
+ .HI ( optlc_net_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) ,
+ .HI ( optlc_net_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) ,
+ .HI ( optlc_net_90 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_103 ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_103 ) ,
+ .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( copt_net_105 ) ,
+ .X ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_107 ) ,
+ .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_104 ) ,
+ .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_108 ) ,
+ .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_106 ) ,
+ .X ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__buf_1 copt_h_inst_1282 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_108 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:13] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:13] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ,
+ .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .Y ( BUF_net_61 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1_ ( chany_top_in , top_left_grid_pin_42_ ,
+ top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ ,
+ top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ ,
+ top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in ,
+ bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ ,
+ bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ ,
+ bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ ,
+ bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ ,
+ bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ ,
+ left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out ,
+ chanx_left_out , ccff_tail , prog_clk_0_N_in ) ;
+input [0:19] chany_top_in ;
+input [0:0] top_left_grid_pin_42_ ;
+input [0:0] top_left_grid_pin_43_ ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_right_grid_pin_1_ ;
+input [0:19] chany_bottom_in ;
+input [0:0] bottom_right_grid_pin_1_ ;
+input [0:0] bottom_left_grid_pin_42_ ;
+input [0:0] bottom_left_grid_pin_43_ ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:19] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_34_ ;
+input [0:0] left_bottom_grid_pin_35_ ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input prog_clk_0_N_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
+ top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
+ top_right_grid_pin_1_[0] , chany_top_out[3] , chany_top_out[13] ,
+ chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[3] , chany_bottom_out[13] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] ,
+ chanx_left_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_101 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 (
+ .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] ,
+ top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
+ chany_top_out[5] , chany_top_out[14] , chanx_left_in[6] ,
+ chanx_left_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] ,
+ top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] ,
+ chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_101 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[17] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] ,
+ chanx_left_in[18] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] ,
+ top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] ,
+ top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] ,
+ top_right_grid_pin_1_[0] , chany_top_out[6] , chany_top_out[15] ,
+ chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_101 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[6] , chany_bottom_out[15] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] ,
+ bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] ,
+ chanx_left_in[17] } ) ,
+ .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size14_mem mem_bottom_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 (
+ .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] ,
+ chany_top_out[9] , chany_top_out[18] , chanx_left_in[3] ,
+ chanx_left_in[10] , chanx_left_in[17] } ) ,
+ .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] ,
+ chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] ,
+ chanx_left_in[9] , chanx_left_in[16] } ) ,
+ .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 ,
+ SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_101 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[18] ,
+ bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] ,
+ chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 ,
+ SYNOPSYS_UNCONNECTED_37 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_101 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] ,
+ left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 ,
+ SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_99 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 (
+ .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] ,
+ chanx_left_out[13] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_99 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 (
+ .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] ,
+ left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 ,
+ SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_99 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 (
+ .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] ,
+ chanx_left_out[13] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 ,
+ SYNOPSYS_UNCONNECTED_49 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_98 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_left_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem mem_left_track_7 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] ,
+ chany_top_out[11] , chanx_left_in[1] , chanx_left_in[8] ,
+ chanx_left_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 ,
+ SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_top_out[16] ) , .p0 ( optlc_net_101 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 (
+ .in ( { chany_bottom_out[10] , chany_bottom_out[19] ,
+ bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] ,
+ chanx_left_in[6] , chanx_left_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_98 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 (
+ .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] ,
+ chanx_left_in[14] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 ,
+ SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem mem_bottom_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[5] , chany_bottom_out[14] ,
+ bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] ,
+ chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) ,
+ .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 ,
+ SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_101 ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 (
+ .in ( { chany_bottom_out[9] , chany_bottom_in[7] , chany_top_out[9] ,
+ left_bottom_grid_pin_34_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 ,
+ SYNOPSYS_UNCONNECTED_65 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 (
+ .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] ,
+ chanx_left_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 ,
+ SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_98 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 (
+ .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] ,
+ left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 (
+ .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] ,
+ left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 ,
+ SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_99 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 (
+ .in ( { chany_bottom_out[14] , chany_top_out[14] ,
+ left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_99 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 (
+ .in ( { chany_bottom_out[15] , chany_top_out[15] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 (
+ .in ( { chany_bottom_out[17] , chany_top_out[17] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 (
+ .in ( { chany_bottom_out[18] , chany_top_out[18] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_99 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 (
+ .in ( { chany_bottom_out[19] , chany_top_out[19] ,
+ left_bottom_grid_pin_34_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 (
+ .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 (
+ .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 (
+ .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 (
+ .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 (
+ .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_100 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 (
+ .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_left_out[19] ) , .p0 ( optlc_net_98 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) ,
+ .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) ,
+ .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) ,
+ .HI ( optlc_net_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) ,
+ .HI ( optlc_net_101 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_104 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_104 ) ,
+ .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) ,
+ .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_64 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_57 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_52 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_50 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_48 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_120 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_94 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_99 ) ,
+ .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) ,
+ .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_98 ) ,
+ .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) ,
+ .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_97 ) ,
+ .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1282 ( .A ( copt_net_95 ) ,
+ .X ( ropt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1283 ( .A ( ropt_net_121 ) ,
+ .X ( ropt_net_120 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1284 ( .A ( ropt_net_119 ) ,
+ .X ( ropt_net_121 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_46 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_43 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_40 ( .A ( BUF_net_41 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_41 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_41 ) ) ;
+endmodule
+
+
+module sb_2__0_ ( chany_top_in , top_left_grid_pin_42_ ,
+ top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ ,
+ top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ ,
+ top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in ,
+ left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
+ left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
+ left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
+ left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
+ left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out ,
+ ccff_tail , prog_clk_0_N_in ) ;
+input [0:19] chany_top_in ;
+input [0:0] top_left_grid_pin_42_ ;
+input [0:0] top_left_grid_pin_43_ ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_right_grid_pin_1_ ;
+input [0:19] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_3_ ;
+input [0:0] left_bottom_grid_pin_5_ ;
+input [0:0] left_bottom_grid_pin_7_ ;
+input [0:0] left_bottom_grid_pin_9_ ;
+input [0:0] left_bottom_grid_pin_11_ ;
+input [0:0] left_bottom_grid_pin_13_ ;
+input [0:0] left_bottom_grid_pin_15_ ;
+input [0:0] left_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input prog_clk_0_N_in ;
+
+wire ropt_net_110 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
+ top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
+ top_right_grid_pin_1_[0] , chanx_left_in[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
+ top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
+ top_right_grid_pin_1_[0] , chanx_left_in[18] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 (
+ .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
+ left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 (
+ .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
+ left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+ .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] ,
+ top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
+ chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 (
+ .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] ,
+ top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
+ chanx_left_in[17] } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 (
+ .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
+ left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
+ SYNOPSYS_UNCONNECTED_21 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 (
+ .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
+ left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
+ SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 (
+ .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] ,
+ chanx_left_in[16] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 (
+ .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] ,
+ chanx_left_in[8] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 (
+ .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 (
+ .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 (
+ .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 (
+ .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chany_top_out[7] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chany_top_out[9] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chany_top_out[11] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 (
+ .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chany_top_out[13] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 (
+ .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 (
+ .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 (
+ .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 (
+ .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 (
+ .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 (
+ .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 (
+ .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_89 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 (
+ .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chanx_left_out[13] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 (
+ .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 (
+ .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 (
+ .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 (
+ .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 (
+ .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_91 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 (
+ .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_left_out[19] ) , .p0 ( optlc_net_90 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_14 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_18 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_20 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_22 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_26 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_left_track_19 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_left_track_21 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_left_track_23 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_27 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_29 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_31 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_35 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_37 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) ,
+ .X ( ropt_net_110 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) ,
+ .HI ( optlc_net_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) ,
+ .HI ( optlc_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) ,
+ .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) ,
+ .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) ,
+ .HI ( optlc_net_93 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) ,
+ .X ( chany_top_out[17] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_109 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( mem_out[2] ) ,
+ .X ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_107 ) ,
+ .X ( copt_net_108 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1295 ( .A ( copt_net_108 ) ,
+ .X ( copt_net_109 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_79 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_75 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .Y ( BUF_net_71 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:13] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ,
+ .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:13] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_130 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_100 ) ,
+ .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_101 ) ,
+ .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_104 ) ,
+ .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_103 ) ,
+ .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_105 ) ,
+ .X ( ropt_net_129 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_131 ) ,
+ .X ( ropt_net_130 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1317 ( .A ( ropt_net_129 ) ,
+ .X ( ropt_net_131 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2_ ( chanx_right_in , right_top_grid_pin_1_ ,
+ right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ ,
+ right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in ,
+ bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ ,
+ bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
+ bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
+ bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in ,
+ left_top_grid_pin_1_ , left_bottom_grid_pin_34_ ,
+ left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , ccff_head , chanx_right_out ,
+ chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT ,
+ prog_clk_0_S_in ) ;
+input [0:19] chanx_right_in ;
+input [0:0] right_top_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_34_ ;
+input [0:0] right_bottom_grid_pin_35_ ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:19] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_42_ ;
+input [0:0] bottom_left_grid_pin_43_ ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:19] chanx_left_in ;
+input [0:0] left_top_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_34_ ;
+input [0:0] left_bottom_grid_pin_35_ ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_BOT ;
+output SC_OUT_BOT ;
+input prog_clk_0_S_in ;
+
+wire ropt_net_118 ;
+wire ropt_net_119 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:2] mux_tree_tapbuf_size7_7_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:3] mux_tree_tapbuf_size9_2_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[5] ,
+ chany_bottom_in[12] , chany_bottom_in[19] , chanx_right_out[3] ,
+ chanx_right_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 (
+ .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
+ chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] ,
+ chanx_right_out[5] , chanx_right_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 (
+ .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] ,
+ chany_bottom_in[13] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 (
+ .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] ,
+ chany_bottom_in[7] , chany_bottom_in[14] ,
+ left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size9_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_3 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] ,
+ right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[3] ,
+ chany_bottom_in[10] , chany_bottom_in[17] , chanx_right_out[6] ,
+ chanx_right_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 (
+ .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] ,
+ chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size14_mem mem_left_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[2] ,
+ chany_bottom_in[9] , chany_bottom_in[16] , chanx_right_out[7] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 (
+ .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] ,
+ chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 (
+ .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] ,
+ chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] ,
+ chanx_right_out[9] , chanx_right_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 (
+ .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] ,
+ chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] ,
+ chanx_right_out[10] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 ,
+ SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 (
+ .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_right_out[3] } ) ,
+ .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 ,
+ SYNOPSYS_UNCONNECTED_41 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 (
+ .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_right_out[5] } ) ,
+ .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 ,
+ SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 (
+ .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_48_[0] , chanx_right_out[6] , chanx_left_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 (
+ .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_right_out[7] , chanx_left_in[11] } ) ,
+ .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 ,
+ SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 (
+ .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] ,
+ chany_bottom_in[10] , chany_bottom_in[17] ,
+ left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 ,
+ SYNOPSYS_UNCONNECTED_53 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 (
+ .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] ,
+ chany_bottom_in[11] , chany_bottom_in[18] ,
+ left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 ,
+ SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_bottom_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_7 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] ,
+ chany_bottom_in[6] , chany_bottom_in[13] , chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 (
+ .in ( { chanx_left_out[9] , bottom_left_grid_pin_42_[0] ,
+ chanx_right_out[9] , chanx_left_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 ,
+ SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 (
+ .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] ,
+ chanx_right_out[10] , chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 ,
+ SYNOPSYS_UNCONNECTED_65 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_99 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 (
+ .in ( { chanx_left_out[19] , chanx_right_in[19] ,
+ bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 ,
+ SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_11 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 (
+ .in ( { chanx_left_out[11] , bottom_left_grid_pin_44_[0] ,
+ chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 (
+ .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] ,
+ chanx_right_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 (
+ .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] ,
+ chanx_right_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 (
+ .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] ,
+ chanx_right_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 (
+ .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 (
+ .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] ,
+ chanx_right_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 (
+ .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 (
+ .in ( { chanx_left_out[11] , chany_bottom_in[5] , chany_bottom_in[12] ,
+ chany_bottom_in[19] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 ,
+ SYNOPSYS_UNCONNECTED_85 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) ,
+ .X ( ropt_net_118 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[11] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[0] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) ,
+ .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) ,
+ .HI ( optlc_net_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) ,
+ .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) ,
+ .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) ,
+ .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) ,
+ .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) ,
+ .X ( SC_OUT_BOT ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+wire copt_net_120 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_120 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_120 ) ,
+ .X ( mem_out[2] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_90 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_88 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:4] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:15] in ;
+input [0:4] sram ;
+input [0:4] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:15] in ;
+input [0:4] sram ;
+input [0:4] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:15] in ;
+input [0:4] sram ;
+input [0:4] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:15] in ;
+input [0:4] sram ;
+input [0:4] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ,
+ .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_125 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_114 ) ,
+ .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_109 ) ,
+ .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_110 ) ,
+ .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_111 ) ,
+ .X ( copt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_112 ) ,
+ .X ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_114 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( copt_net_113 ) ,
+ .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_122 ) ,
+ .X ( ropt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1311 ( .A ( ropt_net_123 ) ,
+ .X ( ropt_net_124 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1312 ( .A ( ropt_net_124 ) ,
+ .X ( ropt_net_125 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1_ ( chany_top_in , top_left_grid_pin_42_ ,
+ top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ ,
+ top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ ,
+ top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ ,
+ right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ ,
+ right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ ,
+ right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ ,
+ right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ ,
+ bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ ,
+ bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ ,
+ bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ ,
+ bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ ,
+ left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out ,
+ chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in ,
+ Test_en_N_out , prog_clk_0_N_in , prog_clk_1_N_in , prog_clk_1_S_in ,
+ prog_clk_1_E_out , prog_clk_1_W_out , prog_clk_2_N_in , prog_clk_2_E_in ,
+ prog_clk_2_S_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_S_out ,
+ prog_clk_2_N_out , prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in ,
+ prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out ,
+ prog_clk_3_N_out , prog_clk_3_S_out , clk_1_N_in , clk_1_S_in ,
+ clk_1_E_out , clk_1_W_out , clk_2_N_in , clk_2_E_in , clk_2_S_in ,
+ clk_2_W_in , clk_2_W_out , clk_2_S_out , clk_2_N_out , clk_2_E_out ,
+ clk_3_W_in , clk_3_E_in , clk_3_S_in , clk_3_N_in , clk_3_E_out ,
+ clk_3_W_out , clk_3_N_out , clk_3_S_out ) ;
+input [0:19] chany_top_in ;
+input [0:0] top_left_grid_pin_42_ ;
+input [0:0] top_left_grid_pin_43_ ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:19] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_34_ ;
+input [0:0] right_bottom_grid_pin_35_ ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:19] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_42_ ;
+input [0:0] bottom_left_grid_pin_43_ ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:19] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_34_ ;
+input [0:0] left_bottom_grid_pin_35_ ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input Test_en_S_in ;
+output Test_en_N_out ;
+input prog_clk_0_N_in ;
+input prog_clk_1_N_in ;
+input prog_clk_1_S_in ;
+output prog_clk_1_E_out ;
+output prog_clk_1_W_out ;
+input prog_clk_2_N_in ;
+input prog_clk_2_E_in ;
+input prog_clk_2_S_in ;
+input prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+output prog_clk_2_E_out ;
+input prog_clk_3_W_in ;
+input prog_clk_3_E_in ;
+input prog_clk_3_S_in ;
+input prog_clk_3_N_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input clk_1_N_in ;
+input clk_1_S_in ;
+output clk_1_E_out ;
+output clk_1_W_out ;
+input clk_2_N_in ;
+input clk_2_E_in ;
+input clk_2_S_in ;
+input clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+output clk_2_E_out ;
+input clk_3_W_in ;
+input clk_3_E_in ;
+input clk_3_S_in ;
+input clk_3_N_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_10_sram ;
+wire [0:3] mux_tree_tapbuf_size10_11_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:3] mux_tree_tapbuf_size10_9_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:4] mux_tree_tapbuf_size16_0_sram ;
+wire [0:4] mux_tree_tapbuf_size16_1_sram ;
+wire [0:4] mux_tree_tapbuf_size16_2_sram ;
+wire [0:4] mux_tree_tapbuf_size16_3_sram ;
+wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+
+assign prog_clk_1_E_out = prog_clk_1_S_in ;
+assign prog_clk_1_W_out = prog_clk_1_S_in ;
+assign prog_clk_2_W_out = prog_clk_2_E_in ;
+assign prog_clk_2_S_out = prog_clk_2_E_in ;
+assign prog_clk_2_N_out = prog_clk_2_E_in ;
+assign prog_clk_2_E_out = prog_clk_2_E_in ;
+assign prog_clk_3_E_out = prog_clk_3_E_in ;
+assign prog_clk_3_W_out = prog_clk_3_E_in ;
+assign prog_clk_3_N_out = prog_clk_3_E_in ;
+assign prog_clk_3_S_out = prog_clk_3_E_in ;
+assign clk_1_E_out = clk_1_S_in ;
+assign clk_1_W_out = clk_1_S_in ;
+assign clk_2_W_out = clk_2_E_in ;
+assign clk_2_S_out = clk_2_E_in ;
+assign clk_2_N_out = clk_2_E_in ;
+assign clk_2_E_out = clk_2_E_in ;
+assign clk_3_E_out = clk_3_E_in ;
+assign clk_3_W_out = clk_3_E_in ;
+assign clk_3_N_out = clk_3_E_in ;
+assign clk_3_S_out = clk_3_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_S_in = prog_clk_1_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_S_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_S_in ;
+assign prog_clk_3_E_in = prog_clk_3_N_in ;
+assign clk_1_S_in = clk_1_N_in ;
+assign clk_2_E_in = clk_2_N_in ;
+assign clk_2_E_in = clk_2_S_in ;
+assign clk_2_E_in = clk_2_W_in ;
+assign clk_3_E_in = clk_3_W_in ;
+assign clk_3_E_in = clk_3_S_in ;
+assign clk_3_E_in = clk_3_N_in ;
+
+sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
+ top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
+ chanx_right_in[1] , chanx_left_out[3] , chanx_left_out[13] ,
+ chany_top_out[3] , chany_top_out[13] , chanx_left_in[0] ,
+ chanx_right_out[3] , chanx_right_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 (
+ .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] ,
+ top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
+ chanx_right_in[3] , chanx_left_out[5] , chanx_left_out[14] ,
+ chany_top_out[5] , chany_top_out[14] , chanx_right_out[5] ,
+ chanx_right_out[14] , chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 (
+ .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chany_top_in[19] ,
+ right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
+ chany_top_out[3] , chany_top_out[13] , chany_bottom_in[15] ,
+ chanx_right_out[3] , chanx_right_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] ,
+ right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] ,
+ right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[5] , chany_bottom_in[11] , chany_top_out[14] ,
+ chanx_right_out[5] , chanx_right_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] ,
+ chanx_left_out[13] , chanx_right_in[15] ,
+ bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] ,
+ chanx_left_in[1] , chanx_right_out[3] , chanx_right_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] ,
+ chanx_right_in[11] , chanx_left_out[14] ,
+ bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] ,
+ chanx_left_in[3] , chanx_right_out[5] , chanx_right_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_bottom_out[13] ,
+ chanx_left_out[3] , chanx_left_out[13] , chany_top_out[3] ,
+ chany_top_out[13] , chany_bottom_in[19] ,
+ left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 (
+ .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] ,
+ chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] ,
+ chany_top_out[5] , chany_top_out[14] , left_bottom_grid_pin_35_[0] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_0 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_0 mux_top_track_4 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] ,
+ top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] ,
+ top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] ,
+ chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] ,
+ chany_top_out[6] , chany_top_out[15] , chanx_right_out[6] ,
+ chanx_right_out[15] , chanx_left_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size16_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 ,
+ SYNOPSYS_UNCONNECTED_37 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_bottom_out[6] , chany_bottom_out[15] ,
+ right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[6] , chany_bottom_in[7] , chany_top_out[15] ,
+ chanx_right_out[6] , chanx_right_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size16_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 ,
+ SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
+ SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] ,
+ chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] ,
+ bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_right_out[6] , chanx_left_in[7] ,
+ chanx_right_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size16_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
+ SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 (
+ .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chany_top_in[15] ,
+ chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] ,
+ chany_top_out[6] , chany_top_out[15] , left_bottom_grid_pin_34_[0] ,
+ left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_38_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size16_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 ,
+ SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 ,
+ SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_right_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_bottom_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size16_mem mem_left_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_8 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] ,
+ chanx_left_out[7] , chanx_right_in[11] , chanx_left_out[17] ,
+ chany_top_out[7] , chany_top_out[17] , chanx_right_out[7] ,
+ chanx_left_in[11] , chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 (
+ .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] ,
+ chanx_left_out[9] , chanx_right_in[15] , chanx_left_out[18] ,
+ chany_top_out[9] , chany_top_out[18] , chanx_left_in[7] ,
+ chanx_right_out[9] , chanx_right_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_107 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] ,
+ chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] ,
+ chany_top_out[10] , chany_top_out[19] , chanx_left_in[3] ,
+ chanx_right_out[10] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_107 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 (
+ .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] ,
+ right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] ,
+ chany_bottom_in[3] , chany_top_out[7] , chany_top_out[17] ,
+ chanx_right_out[7] , chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 (
+ .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] ,
+ right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] ,
+ chany_bottom_in[1] , chany_top_out[9] , chany_top_out[18] ,
+ chanx_right_out[9] , chanx_right_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_108 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 (
+ .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] ,
+ chany_bottom_in[0] , chany_top_out[10] , chany_top_out[19] ,
+ chanx_right_out[10] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_108 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] ,
+ chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] ,
+ bottom_left_grid_pin_46_[0] , chanx_right_out[7] , chanx_left_in[11] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
+ SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_17 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] ,
+ chanx_left_out[9] , chanx_left_out[18] , bottom_left_grid_pin_43_[0] ,
+ bottom_left_grid_pin_47_[0] , chanx_right_out[9] , chanx_left_in[15] ,
+ chanx_right_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
+ SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 (
+ .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] ,
+ chanx_left_out[10] , chanx_left_out[19] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] ,
+ chanx_right_out[10] , chanx_right_out[19] , chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
+ SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 (
+ .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] ,
+ chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] ,
+ chany_top_out[7] , chany_top_out[17] , left_bottom_grid_pin_34_[0] ,
+ left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size10_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
+ SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_102 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 (
+ .in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] ,
+ chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[7] ,
+ chany_top_out[9] , chany_top_out[18] , left_bottom_grid_pin_35_[0] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size10_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
+ SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 (
+ .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] ,
+ chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] ,
+ chany_bottom_in[11] , chany_top_out[19] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size10_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 ,
+ SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_105 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] ,
+ chanx_right_in[0] , chanx_left_out[11] , chany_top_out[11] ,
+ chanx_left_in[1] , chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
+ SYNOPSYS_UNCONNECTED_103 } ) ,
+ .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 (
+ .in ( { chany_bottom_out[11] , chany_top_in[15] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[11] , chany_bottom_in[19] , chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 ,
+ SYNOPSYS_UNCONNECTED_106 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 (
+ .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] ,
+ chanx_left_in[0] , chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 ,
+ SYNOPSYS_UNCONNECTED_109 } ) ,
+ .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_103 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 (
+ .in ( { chany_top_in[1] , chany_bottom_out[11] , chanx_left_out[11] ,
+ chany_top_out[11] , chany_bottom_in[15] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 ,
+ SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_104 ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) ,
+ .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) ,
+ .X ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) ,
+ .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) ,
+ .HI ( optlc_net_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) ,
+ .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) ,
+ .HI ( optlc_net_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) ,
+ .HI ( optlc_net_107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) ,
+ .HI ( optlc_net_108 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+wire copt_net_106 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_106 ) ,
+ .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_109 ) ,
+ .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1290 ( .A ( copt_net_110 ) ,
+ .X ( mem_out[2] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:13] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:13] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_82 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) ,
+ .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_105 ) ,
+ .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_101 ) ,
+ .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) ,
+ .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( copt_net_104 ) ,
+ .X ( ropt_net_131 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_131 ) ,
+ .X ( ropt_net_132 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_132 ) ,
+ .X ( ropt_net_133 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_1__0_ ( chany_top_in , top_left_grid_pin_42_ ,
+ top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ ,
+ top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ ,
+ top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ ,
+ right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ ,
+ right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ ,
+ right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ ,
+ right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in ,
+ left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
+ left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
+ left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
+ left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
+ left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
+ chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in ,
+ Test_en_N_out , prog_clk_0_N_in , prog_clk_3_S_in , prog_clk_3_N_out ,
+ clk_3_S_in , clk_3_N_out ) ;
+input [0:19] chany_top_in ;
+input [0:0] top_left_grid_pin_42_ ;
+input [0:0] top_left_grid_pin_43_ ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:19] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_3_ ;
+input [0:0] right_bottom_grid_pin_5_ ;
+input [0:0] right_bottom_grid_pin_7_ ;
+input [0:0] right_bottom_grid_pin_9_ ;
+input [0:0] right_bottom_grid_pin_11_ ;
+input [0:0] right_bottom_grid_pin_13_ ;
+input [0:0] right_bottom_grid_pin_15_ ;
+input [0:0] right_bottom_grid_pin_17_ ;
+input [0:19] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_3_ ;
+input [0:0] left_bottom_grid_pin_5_ ;
+input [0:0] left_bottom_grid_pin_7_ ;
+input [0:0] left_bottom_grid_pin_9_ ;
+input [0:0] left_bottom_grid_pin_11_ ;
+input [0:0] left_bottom_grid_pin_13_ ;
+input [0:0] left_bottom_grid_pin_15_ ;
+input [0:0] left_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_TOP ;
+input Test_en_S_in ;
+output Test_en_N_out ;
+input prog_clk_0_N_in ;
+input prog_clk_3_S_in ;
+output prog_clk_3_N_out ;
+input clk_3_S_in ;
+output clk_3_N_out ;
+
+wire ropt_net_119 ;
+wire ropt_net_118 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size14_0_sram ;
+wire [0:3] mux_tree_tapbuf_size14_1_sram ;
+wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:1] mux_tree_tapbuf_size3_6_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
+ top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
+ chanx_right_in[1] , chanx_left_out[3] , chanx_left_in[0] ,
+ chanx_right_out[3] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 (
+ .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] ,
+ right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] ,
+ right_bottom_grid_pin_17_[0] , chanx_right_out[7] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 (
+ .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] ,
+ chanx_left_out[14] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
+ left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 (
+ .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] ,
+ chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_2 mem_left_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 (
+ .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] ,
+ top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
+ chanx_right_in[3] , chanx_left_out[5] , chanx_right_out[5] } ) ,
+ .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 (
+ .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
+ top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
+ chanx_left_out[6] , chanx_right_in[7] , chanx_right_out[6] } ) ,
+ .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 ,
+ SYNOPSYS_UNCONNECTED_22 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 (
+ .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] ,
+ top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
+ chanx_left_out[7] , chanx_right_in[11] , chanx_right_out[7] } ) ,
+ .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 ,
+ SYNOPSYS_UNCONNECTED_25 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_99 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 (
+ .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] ,
+ right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] ,
+ chanx_right_out[9] , chanx_right_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 ,
+ SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_99 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 (
+ .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] ,
+ chanx_right_out[10] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 (
+ .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] ,
+ chanx_left_out[9] , chanx_left_out[18] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 ,
+ SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 (
+ .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] ,
+ chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 ,
+ SYNOPSYS_UNCONNECTED_37 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_top_track_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 (
+ .in ( { top_left_grid_pin_42_[0] , chanx_left_out[9] ,
+ chanx_right_in[15] , chanx_right_out[9] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 ,
+ SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_99 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 (
+ .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] ,
+ chanx_right_out[10] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_10 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , chanx_left_out[11] ,
+ chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 (
+ .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] ,
+ chanx_right_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) ,
+ .out ( chany_top_out[7] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] ,
+ chanx_right_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] ,
+ chanx_right_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) ,
+ .out ( chany_top_out[9] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] ,
+ chanx_right_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) ,
+ .out ( chany_top_out[11] ) , .p0 ( optlc_net_95 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 (
+ .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] ,
+ chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size3_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 (
+ .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) ,
+ .out ( chany_top_out[19] ) , .p0 ( optlc_net_99 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_0 (
+ .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] ,
+ right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] ,
+ chanx_right_out[3] , chanx_right_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 ,
+ SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] ,
+ right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] ,
+ right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] ,
+ chanx_right_out[5] , chanx_right_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 ,
+ SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem mem_right_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_0 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] ,
+ right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] ,
+ right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] ,
+ right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_15_[0] ,
+ right_bottom_grid_pin_17_[0] , chanx_right_out[6] ,
+ chanx_right_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size14_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 ,
+ SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 (
+ .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] ,
+ chanx_left_out[6] , chanx_left_out[15] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] ,
+ left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_13_[0] ,
+ left_bottom_grid_pin_15_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size14_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 ,
+ SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size14_mem mem_left_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 (
+ .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] ,
+ right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_15_[0] ,
+ chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 ,
+ SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 (
+ .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] ,
+ chanx_left_out[11] , left_bottom_grid_pin_7_[0] ,
+ left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 ,
+ SYNOPSYS_UNCONNECTED_81 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem mem_left_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] ,
+ chanx_left_out[3] , chanx_left_out[13] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
+ left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 ,
+ SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_98 ) ) ;
+sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) ,
+ .HI ( optlc_net_95 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) ,
+ .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( top_left_grid_pin_43_[0] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[3] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) ,
+ .X ( ropt_net_119 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[11] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) ,
+ .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_92 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) ,
+ .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) ,
+ .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) ,
+ .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) ,
+ .HI ( optlc_net_99 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) ,
+ .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) ,
+ .X ( chany_top_out[17] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( copt_net_71 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_70 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_74 ) ,
+ .X ( copt_net_71 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1237 ( .A ( copt_net_70 ) ,
+ .X ( copt_net_72 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_72 ) ,
+ .X ( copt_net_73 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_73 ) ,
+ .X ( copt_net_74 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_51 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_49 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_58 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_45 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_43 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_118 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_63 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_63 ) ,
+ .X ( copt_net_64 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( copt_net_64 ) ,
+ .X ( copt_net_65 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_68 ) ,
+ .X ( copt_net_66 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_65 ) ,
+ .X ( copt_net_67 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_67 ) ,
+ .X ( copt_net_68 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1281 ( .A ( copt_net_66 ) ,
+ .X ( ropt_net_117 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1282 ( .A ( ropt_net_117 ) ,
+ .X ( ropt_net_118 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_41 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2_ ( chanx_right_in , right_top_grid_pin_1_ ,
+ right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ ,
+ right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in ,
+ bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out ,
+ ccff_tail , SC_IN_TOP , SC_OUT_BOT , prog_clk_0_E_in ) ;
+input [0:19] chanx_right_in ;
+input [0:0] right_top_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_34_ ;
+input [0:0] right_bottom_grid_pin_35_ ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:19] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_1_ ;
+input [0:0] ccff_head ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_88 ;
+wire ropt_net_87 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_60 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_62 ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+ .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
+ chany_bottom_in[17] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_60 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 (
+ .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
+ chany_bottom_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_60 ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_bottom_in[14] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_60 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_bottom_in[6] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 (
+ .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_62 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 (
+ .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_62 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_62 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 (
+ .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_60 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 (
+ .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_62 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_62 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_62 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_62 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_right_out[19] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 (
+ .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 (
+ .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 (
+ .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 (
+ .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_61 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_20 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_22 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_28 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_30 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_34 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_36 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_38 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_bottom_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_bottom_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_right_in[0] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_right_in[1] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) ,
+ .X ( ropt_net_88 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) ,
+ .X ( ropt_net_87 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) ,
+ .HI ( optlc_net_60 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) ,
+ .HI ( optlc_net_61 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) ,
+ .HI ( optlc_net_62 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_96 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_110 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( copt_net_129 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_124 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_124 ) ,
+ .X ( copt_net_125 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_125 ) ,
+ .X ( copt_net_126 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_126 ) ,
+ .X ( copt_net_127 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_127 ) ,
+ .X ( copt_net_128 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_128 ) ,
+ .X ( copt_net_129 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_108 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_79 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_77 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_106 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_73 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_71 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_120 ) ,
+ .X ( copt_net_118 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_121 ) ,
+ .X ( copt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_119 ) ,
+ .X ( copt_net_120 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_123 ) ,
+ .X ( copt_net_121 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_122 ) ,
+ .X ( copt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1299 ( .A ( copt_net_118 ) ,
+ .X ( ropt_net_131 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( ropt_net_131 ) ,
+ .X ( ropt_net_132 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_132 ) ,
+ .X ( ropt_net_133 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in ,
+ right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ ,
+ right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in ,
+ bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out ,
+ chany_bottom_out , ccff_tail , prog_clk_0_E_in ) ;
+input [0:19] chany_top_in ;
+input [0:0] top_left_grid_pin_1_ ;
+input [0:19] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_34_ ;
+input [0:0] right_bottom_grid_pin_35_ ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:19] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_1_ ;
+input [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:19] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:2] mux_tree_tapbuf_size6_4_sram ;
+wire [0:2] mux_tree_tapbuf_size6_5_sram ;
+wire [0:2] mux_tree_tapbuf_size6_6_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] ,
+ chanx_right_in[15] , chany_top_out[3] , chany_top_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_114 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] ,
+ chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_114 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] ,
+ chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_114 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 (
+ .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_40_[0] , chany_top_out[3] } ) ,
+ .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] ,
+ chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] ,
+ chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] ,
+ chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
+ SYNOPSYS_UNCONNECTED_21 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_116 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_bottom_track_1 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_bottom_track_5 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_9 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+ .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] ,
+ chany_top_out[5] , chany_top_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
+ SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 (
+ .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] ,
+ chany_top_out[9] , chany_top_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_116 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] ,
+ chanx_right_in[11] , chanx_right_in[18] } ) ,
+ .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
+ SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_114 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] ,
+ chanx_right_in[8] , chanx_right_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
+ SYNOPSYS_UNCONNECTED_33 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_116 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 (
+ .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] ,
+ chanx_right_in[7] , chanx_right_in[14] } ) ,
+ .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
+ SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_117 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_17 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_25 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 (
+ .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_top_out[10] ,
+ chany_top_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_116 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 (
+ .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] ,
+ chany_top_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
+ SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chany_top_out[16] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 (
+ .in ( { chany_top_in[7] , chany_bottom_out[9] ,
+ right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
+ SYNOPSYS_UNCONNECTED_45 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 (
+ .in ( { chany_bottom_out[10] , chany_top_in[11] ,
+ right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
+ SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 (
+ .in ( { chany_bottom_out[11] , chany_top_in[15] ,
+ right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 (
+ .in ( { chany_bottom_out[13] , chany_top_in[19] ,
+ right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 ,
+ SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_114 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 (
+ .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] ,
+ chany_top_out[19] , chany_bottom_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 ,
+ SYNOPSYS_UNCONNECTED_57 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_117 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_10 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_14 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem mem_right_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_bottom_out[5] ,
+ right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] ,
+ right_bottom_grid_pin_39_[0] , chanx_right_out[19] ,
+ chany_top_out[5] } ) ,
+ .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 ,
+ SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_bottom_out[6] ,
+ right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
+ chany_top_out[6] } ) ,
+ .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 (
+ .in ( { chany_top_in[3] , chany_bottom_out[7] ,
+ right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] ,
+ right_bottom_grid_pin_39_[0] , chanx_right_out[19] ,
+ chany_top_out[7] } ) ,
+ .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 ,
+ SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_115 ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 (
+ .in ( { chany_bottom_out[14] , right_bottom_grid_pin_38_[0] ,
+ chany_top_out[14] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 (
+ .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] ,
+ chany_top_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 (
+ .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] ,
+ chany_top_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 (
+ .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_117 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 (
+ .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_117 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_18 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_20 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_22 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_33 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 (
+ .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_113 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( right_bottom_grid_pin_41_[0] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) ,
+ .HI ( optlc_net_113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) ,
+ .HI ( optlc_net_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) ,
+ .HI ( optlc_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) ,
+ .HI ( optlc_net_116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) ,
+ .HI ( optlc_net_117 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_92 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_92 ) ,
+ .X ( copt_net_88 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) ,
+ .X ( copt_net_89 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) ,
+ .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) ,
+ .X ( copt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1256 ( .A ( copt_net_91 ) ,
+ .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_137 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_81 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) ,
+ .X ( copt_net_82 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) ,
+ .X ( copt_net_83 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_86 ) ,
+ .X ( copt_net_84 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) ,
+ .X ( copt_net_85 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( copt_net_82 ) ,
+ .X ( copt_net_86 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( copt_net_84 ) ,
+ .X ( ropt_net_136 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1301 ( .A ( ropt_net_136 ) ,
+ .X ( ropt_net_137 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_60 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_58 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_56 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_54 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_52 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_50 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_48 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_46 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_43 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_40 ( .A ( BUF_net_41 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_41 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_41 ) ) ;
+endmodule
+
+
+module sb_0__0_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in ,
+ right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ ,
+ right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ ,
+ right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ ,
+ right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ ,
+ right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
+ ccff_tail , prog_clk_0_E_in ) ;
+input [0:19] chany_top_in ;
+input [0:0] top_left_grid_pin_1_ ;
+input [0:19] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_3_ ;
+input [0:0] right_bottom_grid_pin_5_ ;
+input [0:0] right_bottom_grid_pin_7_ ;
+input [0:0] right_bottom_grid_pin_9_ ;
+input [0:0] right_bottom_grid_pin_11_ ;
+input [0:0] right_bottom_grid_pin_13_ ;
+input [0:0] right_bottom_grid_pin_15_ ;
+input [0:0] right_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:19] chany_top_out ;
+output [0:19] chanx_right_out ;
+output [0:0] ccff_tail ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_107 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_80 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 (
+ .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 (
+ .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_80 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 (
+ .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_80 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 (
+ .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 (
+ .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 (
+ .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 (
+ .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 (
+ .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 (
+ .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_80 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 (
+ .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_80 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 (
+ .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 (
+ .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_77 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 (
+ .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 (
+ .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_right_out[19] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_38 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 (
+ .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] ,
+ right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_79 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 (
+ .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] ,
+ right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
+ SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size6_mem mem_right_track_4 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 (
+ .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] ,
+ right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] ,
+ right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
+ SYNOPSYS_UNCONNECTED_45 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 (
+ .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] ,
+ right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] ,
+ right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
+ SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size5_mem mem_right_track_6 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 (
+ .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 (
+ .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_78 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_24 (
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chanx_right_in[0] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_right_in[2] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( chanx_right_in[4] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[6] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[7] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) ,
+ .X ( ropt_net_107 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[14] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[15] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[16] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[17] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) ,
+ .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) ,
+ .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) ,
+ .HI ( optlc_net_79 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) ,
+ .HI ( optlc_net_80 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) ,
+ .X ( chany_top_out[9] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( copt_net_165 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1943 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_160 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1944 ( .A ( copt_net_160 ) ,
+ .X ( copt_net_161 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1945 ( .A ( copt_net_161 ) ,
+ .X ( copt_net_162 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1946 ( .A ( copt_net_162 ) ,
+ .X ( copt_net_163 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1947 ( .A ( copt_net_163 ) ,
+ .X ( copt_net_164 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1948 ( .A ( copt_net_164 ) ,
+ .X ( copt_net_165 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_31 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_31 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__buf_1 BUFT_RR_119 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( p_abuf0 ) , .Y ( BUF_net_118 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( net_net_73 ) ) ;
+sky130_fd_sc_hd__buf_8 BUFT_RR_73 ( .A ( copt_net_168 ) , .X ( ff_Q[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1950 ( .A ( net_net_73 ) ,
+ .X ( copt_net_167 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1951 ( .A ( copt_net_167 ) ,
+ .X ( copt_net_168 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv ,
+ lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 (
+ prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out ,
+ frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic (
+ prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] ccff_tail ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric (
+ prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_29 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_30 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_31 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_29 mem_fabric_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_30 mem_fabric_out_1 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_31 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem mem_ff_1_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) ,
+ .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( ropt_net_170 ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_h_inst_1954 ( .A ( fabric_sc_out[0] ) ,
+ .X ( ropt_net_170 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en ,
+ fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out ,
+ fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) ,
+ .fabric_reg_in ( fle_reg_in ) , .fabric_sc_in ( fle_sc_in ) ,
+ .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) ,
+ .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) ,
+ .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_38 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_517_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_517_ ) ,
+ .Y ( BUF_net_116 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_516_ ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_516_ ) ,
+ .Y ( BUF_net_113 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv ,
+ lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 (
+ prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out ,
+ frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 (
+ prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] ccff_tail ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 (
+ prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_25 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_26 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_27 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_38 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_25 mem_fabric_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_26 mem_fabric_out_1 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_27 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_38 mem_ff_1_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) ,
+ .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en ,
+ fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out ,
+ fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) ,
+ .fabric_reg_in ( fle_reg_in ) , .fabric_sc_in ( fle_sc_in ) ,
+ .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) ,
+ .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) ,
+ .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_37 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_515_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_515_ ) ,
+ .Y ( BUF_net_110 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_514_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_514_ ) ,
+ .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv ,
+ lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 (
+ prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out ,
+ frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 (
+ prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] ccff_tail ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_mux_tree_size2_20 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_20 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 (
+ prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_21 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_22 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_23 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_37 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_37 mem_ff_1_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) ,
+ .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en ,
+ fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out ,
+ fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) ,
+ .fabric_reg_in ( fle_reg_in ) , .fabric_sc_in ( fle_sc_in ) ,
+ .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) ,
+ .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) ,
+ .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_36 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_36 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 ,
+ p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_513_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_513_ ) ,
+ .Y ( BUF_net_104 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p_abuf0 ,
+ p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_512_ ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_512_ ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv ,
+ lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 (
+ prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out ,
+ frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 (
+ prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] ccff_tail ;
+input p2 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_mux_tree_size2_16 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_mem_16 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 (
+ prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out ,
+ ccff_tail , p_abuf0 , p_abuf1 , p2 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p2 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p2 ( p2 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_17 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_18 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_19 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_36 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_mem_17 mem_fabric_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_18 mem_fabric_out_1 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_19 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_36 mem_ff_1_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) ,
+ .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en ,
+ fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out ,
+ fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p2 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) ,
+ .fabric_reg_in ( fle_reg_in ) , .fabric_sc_in ( fle_sc_in ) ,
+ .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) ,
+ .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) ,
+ .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_35 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_35 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p_abuf0 ,
+ p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) ,
+ .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv ,
+ lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 (
+ prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out ,
+ frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 (
+ prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] ccff_tail ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 (
+ prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p2 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_13 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_14 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_15 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_35 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_mem_13 mem_fabric_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_14 mem_fabric_out_1 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_15 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_35 mem_ff_1_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) ,
+ .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en ,
+ fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out ,
+ fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p2 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) ,
+ .fabric_reg_in ( fle_reg_in ) , .fabric_sc_in ( fle_sc_in ) ,
+ .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) ,
+ .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) ,
+ .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_34 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv ,
+ lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 (
+ prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out ,
+ frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 (
+ prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] ccff_tail ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_mux_tree_size2_8 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_8 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 (
+ prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_9 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_10 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_11 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_34 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_34 mem_ff_1_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) ,
+ .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en ,
+ fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out ,
+ fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) ,
+ .fabric_reg_in ( fle_reg_in ) , .fabric_sc_in ( fle_sc_in ) ,
+ .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) ,
+ .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) ,
+ .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_33 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf0 ) , .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv ,
+ lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 (
+ prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out ,
+ frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 (
+ prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] ccff_tail ;
+input p1 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_mux_tree_size2_4 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_mem_4 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 (
+ prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p1 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p1 ( p1 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_5 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_6 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_7 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_33 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_mem_5 mem_fabric_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_6 mem_fabric_out_1 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_7 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_33 mem_ff_1_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) ,
+ .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en ,
+ fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out ,
+ fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p1 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) ,
+ .fabric_reg_in ( fle_reg_in ) , .fabric_sc_in ( fle_sc_in ) ,
+ .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) ,
+ .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) ,
+ .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_32 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_32 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( out[0] ) , .Y ( BUF_net_81 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( p_abuf0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_78 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ Test_en , ff_D , ff_DI , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail ,
+ mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_159 ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1937 ( .A ( copt_net_156 ) ,
+ .X ( copt_net_154 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1938 ( .A ( copt_net_158 ) ,
+ .X ( copt_net_155 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1939 ( .A ( copt_net_157 ) ,
+ .X ( copt_net_156 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1940 ( .A ( copt_net_155 ) ,
+ .X ( copt_net_157 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1941 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_158 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1942 ( .A ( copt_net_154 ) ,
+ .X ( copt_net_159 ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv ,
+ lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out ,
+ frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] ccff_tail ;
+input p1 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_mux_tree_size2_0 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_mem_0 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out ,
+ ccff_tail , p_abuf0 , p_abuf1 , p1 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p1 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p1 ( p1 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_1 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_2 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_3 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_32 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_mem_1 mem_fabric_out_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_2 mem_fabric_out_1 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_3 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_32 mem_ff_1_D_0 ( .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) ,
+ .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en ,
+ fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out ,
+ fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p1 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p1 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) ,
+ .fabric_reg_in ( fle_reg_in ) , .fabric_sc_in ( fle_sc_in ) ,
+ .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) ,
+ .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) ,
+ .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clb_I0 ,
+ clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , clb_I3i ,
+ clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 ,
+ clb_I7i , clb_reg_in , clb_sc_in , clb_clk , ccff_head , clb_O ,
+ clb_reg_out , clb_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 ,
+ p_abuf3 , p_abuf4 , p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 ,
+ p_abuf10 , p_abuf11 , p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p0 ,
+ p1 , p2 , p3 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:2] clb_I0 ;
+input [0:0] clb_I0i ;
+input [0:2] clb_I1 ;
+input [0:0] clb_I1i ;
+input [0:2] clb_I2 ;
+input [0:0] clb_I2i ;
+input [0:2] clb_I3 ;
+input [0:0] clb_I3i ;
+input [0:2] clb_I4 ;
+input [0:0] clb_I4i ;
+input [0:2] clb_I5 ;
+input [0:0] clb_I5i ;
+input [0:2] clb_I6 ;
+input [0:0] clb_I6i ;
+input [0:2] clb_I7 ;
+input [0:0] clb_I7i ;
+input [0:0] clb_reg_in ;
+input [0:0] clb_sc_in ;
+input [0:0] clb_clk ;
+input [0:0] ccff_head ;
+output [0:15] clb_O ;
+output [0:0] clb_reg_out ;
+output [0:0] clb_sc_out ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+output p_abuf2 ;
+output p_abuf3 ;
+output p_abuf4 ;
+output p_abuf5 ;
+output p_abuf6 ;
+output p_abuf7 ;
+output p_abuf8 ;
+output p_abuf9 ;
+output p_abuf10 ;
+output p_abuf11 ;
+output p_abuf12 ;
+output p_abuf13 ;
+output p_abuf14 ;
+output p_abuf15 ;
+input p0 ;
+input p1 ;
+input p2 ;
+input p3 ;
+
+wire [0:0] direct_interc_29_out ;
+wire [0:0] direct_interc_36_out ;
+wire [0:0] direct_interc_43_out ;
+wire [0:0] direct_interc_50_out ;
+wire [0:0] direct_interc_57_out ;
+wire [0:0] direct_interc_64_out ;
+wire [0:0] direct_interc_71_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ;
+
+grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0[2] , clb_I0i[0] } ) ,
+ .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) ,
+ .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) ,
+ .fle_out ( { clb_O[1] , clb_O[0] } ) ,
+ .fle_reg_out ( direct_interc_29_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p2 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1[2] , clb_I1i[0] } ) ,
+ .fle_reg_in ( direct_interc_29_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) ,
+ .fle_out ( { clb_O[3] , clb_O[2] } ) ,
+ .fle_reg_out ( direct_interc_36_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) ,
+ .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2[2] , clb_I2i[0] } ) ,
+ .fle_reg_in ( direct_interc_36_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) ,
+ .fle_out ( { clb_O[5] , clb_O[4] } ) ,
+ .fle_reg_out ( direct_interc_43_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) ,
+ .p_abuf0 ( p_abuf4 ) , .p_abuf1 ( p_abuf5 ) , .p0 ( p0 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) ,
+ .fle_reg_in ( direct_interc_43_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) ,
+ .fle_out ( { clb_O[7] , clb_O[6] } ) ,
+ .fle_reg_out ( direct_interc_50_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) ,
+ .p_abuf0 ( p_abuf6 ) , .p_abuf1 ( p_abuf7 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) ,
+ .fle_reg_in ( direct_interc_50_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) ,
+ .fle_out ( { clb_O[9] , clb_O[8] } ) ,
+ .fle_reg_out ( direct_interc_57_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) ,
+ .p_abuf0 ( p_abuf8 ) , .p_abuf1 ( p_abuf9 ) , .p2 ( p3 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) ,
+ .fle_reg_in ( direct_interc_57_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) ,
+ .fle_out ( { clb_O[11] , clb_O[10] } ) ,
+ .fle_reg_out ( direct_interc_64_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) ,
+ .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p0 ( p1 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) ,
+ .fle_reg_in ( direct_interc_64_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) ,
+ .fle_out ( { clb_O[13] , clb_O[12] } ) ,
+ .fle_reg_out ( direct_interc_71_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) ,
+ .p_abuf0 ( p_abuf12 ) , .p_abuf1 ( p_abuf13 ) , .p0 ( p1 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
+ .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) ,
+ .fle_reg_in ( direct_interc_71_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) ,
+ .fle_out ( { clb_O[15] , clb_O[14] } ) ,
+ .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) ,
+ .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf14 ) , .p_abuf1 ( p_abuf15 ) ,
+ .p0 ( p1 ) ) ;
+endmodule
+
+
+module grid_clb ( top_width_0_height_0__pin_0_ ,
+ top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ ,
+ top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ ,
+ top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ ,
+ top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ ,
+ top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ ,
+ top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ ,
+ top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ ,
+ top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ ,
+ top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_16_ ,
+ right_width_0_height_0__pin_17_ , right_width_0_height_0__pin_18_ ,
+ right_width_0_height_0__pin_19_ , right_width_0_height_0__pin_20_ ,
+ right_width_0_height_0__pin_21_ , right_width_0_height_0__pin_22_ ,
+ right_width_0_height_0__pin_23_ , right_width_0_height_0__pin_24_ ,
+ right_width_0_height_0__pin_25_ , right_width_0_height_0__pin_26_ ,
+ right_width_0_height_0__pin_27_ , right_width_0_height_0__pin_28_ ,
+ right_width_0_height_0__pin_29_ , right_width_0_height_0__pin_30_ ,
+ right_width_0_height_0__pin_31_ , ccff_head ,
+ top_width_0_height_0__pin_34_upper , top_width_0_height_0__pin_34_lower ,
+ top_width_0_height_0__pin_35_upper , top_width_0_height_0__pin_35_lower ,
+ top_width_0_height_0__pin_36_upper , top_width_0_height_0__pin_36_lower ,
+ top_width_0_height_0__pin_37_upper , top_width_0_height_0__pin_37_lower ,
+ top_width_0_height_0__pin_38_upper , top_width_0_height_0__pin_38_lower ,
+ top_width_0_height_0__pin_39_upper , top_width_0_height_0__pin_39_lower ,
+ top_width_0_height_0__pin_40_upper , top_width_0_height_0__pin_40_lower ,
+ top_width_0_height_0__pin_41_upper , top_width_0_height_0__pin_41_lower ,
+ right_width_0_height_0__pin_42_upper ,
+ right_width_0_height_0__pin_42_lower ,
+ right_width_0_height_0__pin_43_upper ,
+ right_width_0_height_0__pin_43_lower ,
+ right_width_0_height_0__pin_44_upper ,
+ right_width_0_height_0__pin_44_lower ,
+ right_width_0_height_0__pin_45_upper ,
+ right_width_0_height_0__pin_45_lower ,
+ right_width_0_height_0__pin_46_upper ,
+ right_width_0_height_0__pin_46_lower ,
+ right_width_0_height_0__pin_47_upper ,
+ right_width_0_height_0__pin_47_lower ,
+ right_width_0_height_0__pin_48_upper ,
+ right_width_0_height_0__pin_48_lower ,
+ right_width_0_height_0__pin_49_upper ,
+ right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ ,
+ bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT ,
+ SC_OUT_TOP , SC_OUT_BOT , Test_en_E_in , Test_en_W_in , Test_en_W_out ,
+ Test_en_E_out , prog_clk_0_N_in , prog_clk_0_S_in , prog_clk_0_S_out ,
+ prog_clk_0_E_out , prog_clk_0_W_out , prog_clk_0_N_out , clk_0_N_in ,
+ clk_0_S_in ) ;
+input [0:0] top_width_0_height_0__pin_0_ ;
+input [0:0] top_width_0_height_0__pin_1_ ;
+input [0:0] top_width_0_height_0__pin_2_ ;
+input [0:0] top_width_0_height_0__pin_3_ ;
+input [0:0] top_width_0_height_0__pin_4_ ;
+input [0:0] top_width_0_height_0__pin_5_ ;
+input [0:0] top_width_0_height_0__pin_6_ ;
+input [0:0] top_width_0_height_0__pin_7_ ;
+input [0:0] top_width_0_height_0__pin_8_ ;
+input [0:0] top_width_0_height_0__pin_9_ ;
+input [0:0] top_width_0_height_0__pin_10_ ;
+input [0:0] top_width_0_height_0__pin_11_ ;
+input [0:0] top_width_0_height_0__pin_12_ ;
+input [0:0] top_width_0_height_0__pin_13_ ;
+input [0:0] top_width_0_height_0__pin_14_ ;
+input [0:0] top_width_0_height_0__pin_15_ ;
+input [0:0] top_width_0_height_0__pin_32_ ;
+input [0:0] top_width_0_height_0__pin_33_ ;
+input [0:0] right_width_0_height_0__pin_16_ ;
+input [0:0] right_width_0_height_0__pin_17_ ;
+input [0:0] right_width_0_height_0__pin_18_ ;
+input [0:0] right_width_0_height_0__pin_19_ ;
+input [0:0] right_width_0_height_0__pin_20_ ;
+input [0:0] right_width_0_height_0__pin_21_ ;
+input [0:0] right_width_0_height_0__pin_22_ ;
+input [0:0] right_width_0_height_0__pin_23_ ;
+input [0:0] right_width_0_height_0__pin_24_ ;
+input [0:0] right_width_0_height_0__pin_25_ ;
+input [0:0] right_width_0_height_0__pin_26_ ;
+input [0:0] right_width_0_height_0__pin_27_ ;
+input [0:0] right_width_0_height_0__pin_28_ ;
+input [0:0] right_width_0_height_0__pin_29_ ;
+input [0:0] right_width_0_height_0__pin_30_ ;
+input [0:0] right_width_0_height_0__pin_31_ ;
+input [0:0] ccff_head ;
+output [0:0] top_width_0_height_0__pin_34_upper ;
+output [0:0] top_width_0_height_0__pin_34_lower ;
+output [0:0] top_width_0_height_0__pin_35_upper ;
+output [0:0] top_width_0_height_0__pin_35_lower ;
+output [0:0] top_width_0_height_0__pin_36_upper ;
+output [0:0] top_width_0_height_0__pin_36_lower ;
+output [0:0] top_width_0_height_0__pin_37_upper ;
+output [0:0] top_width_0_height_0__pin_37_lower ;
+output [0:0] top_width_0_height_0__pin_38_upper ;
+output [0:0] top_width_0_height_0__pin_38_lower ;
+output [0:0] top_width_0_height_0__pin_39_upper ;
+output [0:0] top_width_0_height_0__pin_39_lower ;
+output [0:0] top_width_0_height_0__pin_40_upper ;
+output [0:0] top_width_0_height_0__pin_40_lower ;
+output [0:0] top_width_0_height_0__pin_41_upper ;
+output [0:0] top_width_0_height_0__pin_41_lower ;
+output [0:0] right_width_0_height_0__pin_42_upper ;
+output [0:0] right_width_0_height_0__pin_42_lower ;
+output [0:0] right_width_0_height_0__pin_43_upper ;
+output [0:0] right_width_0_height_0__pin_43_lower ;
+output [0:0] right_width_0_height_0__pin_44_upper ;
+output [0:0] right_width_0_height_0__pin_44_lower ;
+output [0:0] right_width_0_height_0__pin_45_upper ;
+output [0:0] right_width_0_height_0__pin_45_lower ;
+output [0:0] right_width_0_height_0__pin_46_upper ;
+output [0:0] right_width_0_height_0__pin_46_lower ;
+output [0:0] right_width_0_height_0__pin_47_upper ;
+output [0:0] right_width_0_height_0__pin_47_lower ;
+output [0:0] right_width_0_height_0__pin_48_upper ;
+output [0:0] right_width_0_height_0__pin_48_lower ;
+output [0:0] right_width_0_height_0__pin_49_upper ;
+output [0:0] right_width_0_height_0__pin_49_lower ;
+output [0:0] bottom_width_0_height_0__pin_50_ ;
+output [0:0] bottom_width_0_height_0__pin_51_ ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+output SC_OUT_BOT ;
+input Test_en_E_in ;
+input Test_en_W_in ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input prog_clk_0_N_in ;
+input prog_clk_0_S_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_E_out ;
+output prog_clk_0_W_out ;
+output prog_clk_0_N_out ;
+input clk_0_N_in ;
+input clk_0_S_in ;
+
+wire p_abuf2 ;
+wire p_abuf8 ;
+wire p_abuf12 ;
+wire prog_clk_0 ;
+wire [0:0] prog_clk ;
+wire [0:0] clk ;
+wire clk_0 ;
+wire [0:0] Test_en ;
+
+assign SC_IN_BOT = SC_IN_TOP ;
+assign Test_en_W_in = Test_en_E_in ;
+assign prog_clk[0] = prog_clk_0 ;
+assign prog_clk_0_S_in = prog_clk_0_N_in ;
+assign clk_0 = clk[0] ;
+assign clk_0_S_in = clk_0_N_in ;
+
+grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
+ .prog_clk ( { prog_clk_0 } ) ,
+ .Test_en ( Test_en ) ,
+ .clb_I0 ( { top_width_0_height_0__pin_0_[0] ,
+ top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) ,
+ .clb_I0i ( top_width_0_height_0__pin_3_ ) ,
+ .clb_I1 ( { top_width_0_height_0__pin_4_[0] ,
+ top_width_0_height_0__pin_5_[0] , top_width_0_height_0__pin_6_[0] } ) ,
+ .clb_I1i ( top_width_0_height_0__pin_7_ ) ,
+ .clb_I2 ( { top_width_0_height_0__pin_8_[0] ,
+ top_width_0_height_0__pin_9_[0] , top_width_0_height_0__pin_10_[0] } ) ,
+ .clb_I2i ( top_width_0_height_0__pin_11_ ) ,
+ .clb_I3 ( { top_width_0_height_0__pin_12_[0] ,
+ top_width_0_height_0__pin_13_[0] , top_width_0_height_0__pin_14_[0] } ) ,
+ .clb_I3i ( top_width_0_height_0__pin_15_ ) ,
+ .clb_I4 ( { right_width_0_height_0__pin_16_[0] ,
+ right_width_0_height_0__pin_17_[0] ,
+ right_width_0_height_0__pin_18_[0] } ) ,
+ .clb_I4i ( right_width_0_height_0__pin_19_ ) ,
+ .clb_I5 ( { right_width_0_height_0__pin_20_[0] ,
+ right_width_0_height_0__pin_21_[0] ,
+ right_width_0_height_0__pin_22_[0] } ) ,
+ .clb_I5i ( right_width_0_height_0__pin_23_ ) ,
+ .clb_I6 ( { right_width_0_height_0__pin_24_[0] ,
+ right_width_0_height_0__pin_25_[0] ,
+ right_width_0_height_0__pin_26_[0] } ) ,
+ .clb_I6i ( right_width_0_height_0__pin_27_ ) ,
+ .clb_I7 ( { right_width_0_height_0__pin_28_[0] ,
+ right_width_0_height_0__pin_29_[0] ,
+ right_width_0_height_0__pin_30_[0] } ) ,
+ .clb_I7i ( right_width_0_height_0__pin_31_ ) ,
+ .clb_reg_in ( top_width_0_height_0__pin_32_ ) ,
+ .clb_sc_in ( { SC_IN_BOT } ) ,
+ .clb_clk ( clk ) , .ccff_head ( ccff_head ) ,
+ .clb_O ( { aps_rename_520_ , aps_rename_521_ , aps_rename_522_ ,
+ top_width_0_height_0__pin_37_lower[0] , aps_rename_524_ ,
+ aps_rename_525_ , aps_rename_526_ , aps_rename_527_ ,
+ aps_rename_528_ , right_width_0_height_0__pin_43_lower[0] ,
+ aps_rename_530_ , aps_rename_531_ , aps_rename_532_ ,
+ right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ ,
+ aps_rename_535_ } ) ,
+ .clb_reg_out ( bottom_width_0_height_0__pin_50_ ) ,
+ .clb_sc_out ( { SC_OUT_BOT } ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( top_width_0_height_0__pin_35_lower[0] ) ,
+ .p_abuf1 ( top_width_0_height_0__pin_34_lower[0] ) ,
+ .p_abuf2 ( p_abuf2 ) ,
+ .p_abuf3 ( top_width_0_height_0__pin_36_lower[0] ) ,
+ .p_abuf4 ( top_width_0_height_0__pin_39_lower[0] ) ,
+ .p_abuf5 ( top_width_0_height_0__pin_38_lower[0] ) ,
+ .p_abuf6 ( top_width_0_height_0__pin_41_lower[0] ) ,
+ .p_abuf7 ( top_width_0_height_0__pin_40_lower[0] ) ,
+ .p_abuf8 ( p_abuf8 ) ,
+ .p_abuf9 ( right_width_0_height_0__pin_42_lower[0] ) ,
+ .p_abuf10 ( right_width_0_height_0__pin_45_lower[0] ) ,
+ .p_abuf11 ( right_width_0_height_0__pin_44_lower[0] ) ,
+ .p_abuf12 ( p_abuf12 ) ,
+ .p_abuf13 ( right_width_0_height_0__pin_46_lower[0] ) ,
+ .p_abuf14 ( right_width_0_height_0__pin_49_lower[0] ) ,
+ .p_abuf15 ( right_width_0_height_0__pin_48_lower[0] ) ,
+ .p0 ( optlc_net_146 ) , .p1 ( optlc_net_147 ) , .p2 ( optlc_net_148 ) ,
+ .p3 ( optlc_net_149 ) ) ;
+sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) ,
+ .X ( Test_en[0] ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) ,
+ .X ( aps_rename_536_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_W_in ) ,
+ .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__buf_12 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk_0 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_1150 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_2151 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_3152 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_4153 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( aps_rename_520_ ) ,
+ .X ( top_width_0_height_0__pin_34_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( aps_rename_521_ ) ,
+ .X ( top_width_0_height_0__pin_35_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( aps_rename_522_ ) ,
+ .X ( top_width_0_height_0__pin_36_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( p_abuf2 ) ,
+ .X ( top_width_0_height_0__pin_37_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( aps_rename_524_ ) ,
+ .X ( top_width_0_height_0__pin_38_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_62__61 ( .A ( aps_rename_525_ ) ,
+ .X ( top_width_0_height_0__pin_39_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( aps_rename_526_ ) ,
+ .X ( top_width_0_height_0__pin_40_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_64__63 ( .A ( aps_rename_527_ ) ,
+ .X ( top_width_0_height_0__pin_41_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_528_ ) ,
+ .X ( right_width_0_height_0__pin_42_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( p_abuf8 ) ,
+ .X ( right_width_0_height_0__pin_43_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_530_ ) ,
+ .X ( right_width_0_height_0__pin_44_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_531_ ) ,
+ .X ( right_width_0_height_0__pin_45_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_532_ ) ,
+ .X ( right_width_0_height_0__pin_46_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( p_abuf12 ) ,
+ .X ( right_width_0_height_0__pin_47_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_534_ ) ,
+ .X ( right_width_0_height_0__pin_48_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_535_ ) ,
+ .X ( right_width_0_height_0__pin_49_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_OUT_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) ,
+ .Y ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( aps_rename_536_ ) ,
+ .Y ( BUF_net_121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) ,
+ .HI ( optlc_net_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( optlc_net_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( optlc_net_148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( optlc_net_149 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3901295 ( .A ( ctsbuf_net_1150 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3951300 ( .A ( ctsbuf_net_2151 ) ,
+ .X ( prog_clk_0_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4001305 ( .A ( ctsbuf_net_3152 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4051310 ( .A ( ctsbuf_net_4153 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+endmodule
+
+
+module fpga_core ( prog_clk , Test_en , IO_ISOL_N , clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , ccff_head , ccff_tail , sc_head ,
+ sc_tail , h_incr0 , p0 , p1 , p2 , p3 , p4 , p5 , p6 , p7 , p8 , p9 ,
+ p10 , p11 , p12 , p13 , p14 , p15 , p16 , p17 , p18 , p19 , p20 , p21 ,
+ p22 , p23 , p24 , p25 , p26 , p27 , p28 , p29 , p30 , p31 , p32 , p33 ,
+ p34 , p35 , p36 , p37 , p38 , p39 , p40 , p41 , p42 , p43 , p44 , p45 ,
+ p46 , p47 , p48 , p49 , p50 , p51 , p52 , p53 , p54 , p55 , p56 , p57 ,
+ p58 , p59 , p60 , p61 , p62 , p63 , p64 , p65 , p66 , p67 , p68 , p69 ,
+ p70 , p71 , p72 , p73 , p74 , p75 , p76 , p77 , p78 , p79 , p80 , p81 ,
+ p82 , p83 , p84 , p85 , p86 , p87 , p88 , p89 , p90 , p91 , p92 , p93 ,
+ p94 , p95 , p96 , p97 , p98 , p99 , p100 , p101 , p102 , p103 , p104 ,
+ p105 , p106 , p107 , p108 , p109 , p110 , p111 , p112 , p113 , p114 ,
+ p115 , p116 , p117 , p118 , p119 , p120 , p121 , p122 , p123 , p124 ,
+ p125 , p126 , p127 , p128 , p129 , p130 , p131 , p132 , p133 , p134 ,
+ p135 , p136 , p137 , p138 , p139 , p140 , p141 , p142 , p143 , p144 ,
+ p145 , p146 , p147 , p148 , p149 , p150 , p151 , p152 , p153 , p154 ,
+ p155 , p156 , p157 , p158 , p159 , p160 , p161 , p162 , p163 , p164 ,
+ p165 , p166 , p167 , p168 , p169 , p170 , p171 , p172 , p173 , p174 ,
+ p175 , p176 , p177 , p178 , p179 , p180 , p181 , p182 , p183 , p184 ,
+ p185 , p186 , p187 , p188 , p189 , p190 , p191 , p192 , p193 , p194 ,
+ p195 , p196 , p197 , p198 , p199 , p200 , p201 , p202 , p203 , p204 ,
+ p205 , p206 , p207 , p208 , p209 , p210 , p211 , p212 , p213 , p214 ,
+ p215 , p216 , p217 , p218 , p219 , p220 , p221 , p222 , p223 , p224 ,
+ p225 , p226 , p227 , p228 , p229 , p230 , p231 , p232 , p233 , p234 ,
+ p235 , p236 , p237 , p238 , p239 , p240 , p241 , p242 , p243 , p244 ,
+ p245 , p246 , p247 , p248 , p249 , p250 , p251 , p252 , p253 , p254 ,
+ p255 , p256 , p257 , p258 , p259 , p260 , p261 , p262 , p263 , p264 ,
+ p265 , p266 , p267 , p268 , p269 , p270 , p271 , p272 , p273 , p274 ,
+ p275 , p276 , p277 , p278 , p279 , p280 , p281 , p282 , p283 , p284 ,
+ p285 , p286 , p287 , p288 , p289 , p290 , p291 , p292 , p293 , p294 ,
+ p295 , p296 , p297 , p298 , p299 , p300 , p301 , p302 , p303 , p304 ,
+ p305 , p306 , p307 , p308 , p309 , p310 , p311 , p312 , p313 , p314 ,
+ p315 , p316 , p317 , p318 , p319 , p320 , p321 , p322 , p323 , p324 ,
+ p325 , p326 , p327 , p328 , p329 , p330 , p331 , p332 , p333 , p334 ,
+ p335 , p336 , p337 , p338 , p339 , p340 , p341 , p342 , p343 , p344 ,
+ p345 , p346 , p347 , p348 , p349 , p350 , p351 , p352 , p353 , p354 ,
+ p355 , p356 , p357 , p358 , p359 , p360 , p361 , p362 , p363 , p364 ,
+ p365 , p366 , p367 , p368 , p369 , p370 , p371 , p372 , p373 , p374 ,
+ p375 , p376 , p377 , p378 , p379 , p380 , p381 , p382 , p383 , p384 ,
+ p385 , p386 , p387 , p388 , p389 , p390 , p391 , p392 , p393 , p394 ,
+ p395 , p396 , p397 , p398 , p399 , p400 , p401 , p402 , p403 , p404 ,
+ p405 , p406 , p407 , p408 , p409 , p410 , p411 , p412 , p413 , p414 ,
+ p415 , p416 , p417 , p418 , p419 , p420 , p421 , p422 , p423 , p424 ,
+ p425 , p426 , p427 , p428 , p429 , p430 , p431 , p432 , p433 , p434 ,
+ p435 , p436 , p437 , p438 , p439 , p440 , p441 , p442 , p443 , p444 ,
+ p445 , p446 , p447 , p448 , p449 , p450 , p451 , p452 , p453 , p454 ,
+ p455 , p456 , p457 , p458 , p459 , p460 , p461 , p462 , p463 , p464 ,
+ p465 , p466 , p467 , p468 , p469 , p470 , p471 , p472 , p473 , p474 ,
+ p475 , p476 , p477 , p478 , p479 , p480 , p481 , p482 , p483 , p484 ,
+ p485 , p486 , p487 , p488 , p489 , p490 , p491 , p492 , p493 , p494 ,
+ p495 , p496 , p497 , p498 , p499 , p500 , p501 , p502 , p503 , p504 ,
+ p505 , p506 , p507 , p508 , p509 , p510 , p511 , p512 , p513 , p514 ,
+ p515 , p516 , p517 , p518 , p519 , p520 , p521 , p522 , p523 , p524 ,
+ p525 , p526 , p527 , p528 , p529 , p530 , p531 , p532 , p533 , p534 ,
+ p535 , p536 , p537 , p538 , p539 , p540 , p541 , p542 , p543 , p544 ,
+ p545 , p546 , p547 , p548 , p549 , p550 , p551 , p552 , p553 , p554 ,
+ p555 , p556 , p557 , p558 , p559 , p560 , p561 , p562 , p563 , p564 ,
+ p565 , p566 , p567 , p568 , p569 , p570 , p571 , p572 , p573 , p574 ,
+ p575 , p576 , p577 , p578 , p579 , p580 , p581 , p582 , p583 , p584 ,
+ p585 , p586 , p587 , p588 , p589 , p590 , p591 , p592 , p593 , p594 ,
+ p595 , p596 , p597 , p598 , p599 , p600 , p601 , p602 , p603 , p604 ,
+ p605 , p606 , p607 , p608 , p609 , p610 , p611 , p612 , p613 , p614 ,
+ p615 , p616 , p617 , p618 , p619 , p620 , p621 , p622 , p623 , p624 ,
+ p625 , p626 , p627 , p628 , p629 , p630 , p631 , p632 , p633 , p634 ,
+ p635 , p636 , p637 , p638 , p639 , p640 , p641 , p642 , p643 , p644 ,
+ p645 , p646 , p647 , p648 , p649 , p650 , p651 , p652 , p653 , p654 ,
+ p655 , p656 , p657 , p658 , p659 , p660 , p661 , p662 , p663 , p664 ,
+ p665 , p666 , p667 , p668 , p669 , p670 , p671 , p672 , p673 , p674 ,
+ p675 , p676 , p677 , p678 , p679 , p680 , p681 , p682 , p683 , p684 ,
+ p685 , p686 , p687 , p688 , p689 , p690 , p691 , p692 , p693 , p694 ,
+ p695 , p696 , p697 , p698 , p699 , p700 , p701 , p702 , p703 , p704 ,
+ p705 , p706 , p707 , p708 , p709 , p710 , p711 , p712 , p713 , p714 ,
+ p715 , p716 , p717 , p718 , p719 , p720 , p721 , p722 , p723 , p724 ,
+ p725 , p726 , p727 , p728 , p729 , p730 , p731 , p732 , p733 , p734 ,
+ p735 , p736 , p737 , p738 , p739 , p740 , p741 , p742 , p743 , p744 ,
+ p745 , p746 , p747 , p748 , p749 , p750 , p751 , p752 , p753 , p754 ,
+ p755 , p756 , p757 , p758 , p759 , p760 , p761 , p762 , p763 , p764 ,
+ p765 , p766 , p767 , p768 , p769 , p770 , p771 , p772 , p773 , p774 ,
+ p775 , p776 , p777 , p778 , p779 , p780 , p781 , p782 , p783 , p784 ,
+ p785 , p786 , p787 , p788 , p789 , p790 , p791 , p792 , p793 , p794 ,
+ p795 , p796 , p797 , p798 , p799 , p800 , p801 , p802 , p803 , p804 ,
+ p805 , p806 , p807 , p808 , p809 , p810 , p811 , p812 , p813 , p814 ,
+ p815 , p816 , p817 , p818 , p819 , p820 , p821 , p822 , p823 , p824 ,
+ p825 , p826 , p827 , p828 , p829 , p830 , p831 , p832 , p833 , p834 ,
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+ p2742 , p2743 , p2744 , p2745 , p2746 , p2747 , p2748 , p2749 , p2750 ,
+ p2751 , p2752 , p2753 , p2754 , p2755 , p2756 , p2757 , p2758 , p2759 ,
+ p2760 , p2761 , p2762 , p2763 , p2764 , p2765 , p2766 , p2767 , p2768 ,
+ p2769 , p2770 , p2771 , p2772 , p2773 , p2774 , p2775 , p2776 , p2777 ,
+ p2778 , p2779 , p2780 , p2781 , p2782 , p2783 , p2784 , p2785 , p2786 ,
+ p2787 , p2788 , p2789 , p2790 , p2791 , p2792 , p2793 , p2794 , p2795 ,
+ p2796 , p2797 , p2798 , p2799 , p2800 , p2801 , p2802 , p2803 , p2804 ,
+ p2805 , p2806 , p2807 , p2808 , p2809 , p2810 , p2811 , p2812 , p2813 ,
+ p2814 , p2815 , p2816 , p2817 , p2818 , p2819 , p2820 , p2821 , p2822 ,
+ p2823 , p2824 , p2825 , p2826 , p2827 , p2828 , p2829 , p2830 , p2831 ,
+ p2832 , p2833 , p2834 , p2835 , p2836 , p2837 , p2838 , p2839 , p2840 ,
+ p2841 , p2842 , p2843 , p2844 , p2845 , p2846 , p2847 , p2848 , p2849 ,
+ p2850 , p2851 , p2852 , p2853 , p2854 , p2855 , p2856 , p2857 , p2858 ,
+ p2859 , p2860 , p2861 , p2862 , p2863 , p2864 , p2865 , p2866 , p2867 ,
+ p2868 , p2869 , p2870 , p2871 , p2872 , p2873 , p2874 , p2875 , p2876 ,
+ p2877 , p2878 , p2879 , p2880 , p2881 , p2882 , p2883 , p2884 , p2885 ,
+ p2886 , p2887 , p2888 , p2889 , p2890 , p2891 , p2892 , p2893 , p2894 ,
+ p2895 , p2896 , p2897 , p2898 , p2899 , p2900 , p2901 , p2902 , p2903 ,
+ p2904 , p2905 , p2906 , p2907 , p2908 , p2909 , p2910 , p2911 , p2912 ,
+ p2913 , p2914 , p2915 , p2916 , p2917 , p2918 , p2919 , p2920 , p2921 ,
+ p2922 , p2923 , p2924 , p2925 , p2926 , p2927 , p2928 , p2929 , p2930 ,
+ p2931 , p2932 , p2933 , p2934 , p2935 , p2936 , p2937 , p2938 , p2939 ,
+ p2940 , p2941 , p2942 , p2943 , p2944 , p2945 , p2946 , p2947 , p2948 ,
+ p2949 , p2950 , p2951 , p2952 , p2953 , p2954 , p2955 , p2956 , p2957 ,
+ p2958 , p2959 , p2960 , p2961 , p2962 , p2963 , p2964 , p2965 , p2966 ,
+ p2967 , p2968 , p2969 , p2970 , p2971 , p2972 , p2973 , p2974 , p2975 ,
+ p2976 , p2977 , p2978 , p2979 , p2980 , p2981 , p2982 , p2983 , p2984 ,
+ p2985 , p2986 , p2987 , p2988 , p2989 , p2990 , p2991 , p2992 , p2993 ,
+ p2994 , p2995 , p2996 , p2997 , p2998 , p2999 , p3000 , p3001 , p3002 ,
+ p3003 , p3004 , p3005 , p3006 , p3007 , p3008 , p3009 , p3010 , p3011 ,
+ p3012 , p3013 , p3014 , p3015 , p3016 , p3017 , p3018 , p3019 , p3020 ,
+ p3021 , p3022 , p3023 , p3024 , p3025 , p3026 , p3027 , p3028 , p3029 ,
+ p3030 , p3031 , p3032 , p3033 , p3034 , p3035 , p3036 , p3037 , p3038 ,
+ p3039 , p3040 , p3041 , p3042 , p3043 , p3044 , p3045 , p3046 , p3047 ,
+ p3048 , p3049 , p3050 , p3051 , p3052 , p3053 , p3054 , p3055 , p3056 ,
+ p3057 , p3058 , p3059 , p3060 , p3061 , p3062 , p3063 , p3064 , p3065 ,
+ p3066 , p3067 , p3068 , p3069 , p3070 , p3071 , p3072 , p3073 , p3074 ,
+ p3075 , p3076 , p3077 , p3078 , p3079 , p3080 , p3081 , p3082 , p3083 ,
+ p3084 , p3085 , p3086 , p3087 , p3088 , p3089 , p3090 , p3091 , p3092 ,
+ p3093 , p3094 , p3095 , p3096 , p3097 , p3098 , p3099 , p3100 , p3101 ,
+ p3102 , p3103 , p3104 , p3105 , p3106 , p3107 , p3108 , p3109 , p3110 ,
+ p3111 , p3112 , p3113 , p3114 , p3115 , p3116 , p3117 , p3118 , p3119 ,
+ p3120 , p3121 , p3122 , p3123 , p3124 , p3125 , p3126 , p3127 , p3128 ,
+ p3129 , p3130 , p3131 , p3132 , p3133 , p3134 , p3135 , p3136 , p3137 ,
+ p3138 , p3139 , p3140 , p3141 , p3142 , p3143 , p3144 , p3145 , p3146 ,
+ p3147 , p3148 , p3149 , p3150 , p3151 , p3152 , p3153 , p3154 , p3155 ,
+ p3156 , p3157 , p3158 , p3159 , p3160 , p3161 , p3162 , p3163 , p3164 ,
+ p3165 , p3166 , p3167 , p3168 , p3169 , p3170 , p3171 , p3172 , p3173 ,
+ p3174 , p3175 , p3176 , p3177 , p3178 , p3179 , p3180 , p3181 , p3182 ,
+ p3183 , p3184 , p3185 , p3186 , p3187 , p3188 , p3189 , p3190 , p3191 ,
+ p3192 , p3193 , p3194 , p3195 , p3196 , p3197 , p3198 , p3199 , p3200 ,
+ p3201 , p3202 , p3203 , p3204 , p3205 , p3206 , p3207 , p3208 , p3209 ,
+ p3210 , p3211 , p3212 , p3213 , p3214 , p3215 , p3216 , p3217 , p3218 ,
+ p3219 , p3220 , p3221 , p3222 , p3223 , p3224 , p3225 , p3226 , p3227 ,
+ p3228 , p3229 , p3230 , p3231 , p3232 , p3233 , p3234 , p3235 , p3236 ,
+ p3237 , p3238 , p3239 , p3240 , p3241 , p3242 , p3243 , p3244 , p3245 ,
+ p3246 , p3247 , p3248 , p3249 , p3250 , p3251 , p3252 , p3253 , p3254 ,
+ p3255 , p3256 , p3257 , p3258 , p3259 , p3260 , p3261 , p3262 , p3263 ,
+ p3264 , p3265 , p3266 , p3267 , p3268 , p3269 , p3270 , p3271 , p3272 ,
+ p3273 , p3274 , p3275 , p3276 , p3277 , p3278 , p3279 , p3280 , p3281 ,
+ p3282 , p3283 , p3284 , p3285 , p3286 , p3287 , p3288 , p3289 , p3290 ,
+ p3291 , p3292 , p3293 , p3294 , p3295 , p3296 , p3297 , p3298 , p3299 ,
+ p3300 , p3301 , p3302 , p3303 , p3304 , p3305 , p3306 , p3307 , p3308 ,
+ p3309 , p3310 , p3311 , p3312 , p3313 , p3314 , p3315 , p3316 , p3317 ,
+ p3318 , p3319 , p3320 , p3321 , p3322 , p3323 , p3324 , p3325 , p3326 ,
+ p3327 , p3328 , p3329 , p3330 , p3331 , p3332 , p3333 , p3334 , p3335 ,
+ p3336 , p3337 , p3338 , p3339 , p3340 , p3341 , p3342 , p3343 , p3344 ,
+ p3345 , p3346 , p3347 , p3348 , p3349 , p3350 , p3351 , p3352 , p3353 ,
+ p3354 , p3355 , p3356 , p3357 , p3358 , p3359 , p3360 , p3361 , p3362 ,
+ p3363 , p3364 , p3365 , p3366 , p3367 , p3368 , p3369 , p3370 , p3371 ,
+ p3372 , p3373 , p3374 , p3375 , p3376 , p3377 , p3378 , p3379 , p3380 ,
+ p3381 , p3382 , p3383 , p3384 , p3385 , p3386 , p3387 , p3388 , p3389 ,
+ p3390 , p3391 , p3392 , p3393 , p3394 , p3395 , p3396 , p3397 , p3398 ,
+ p3399 , p3400 , p3401 , p3402 , p3403 , p3404 , p3405 , p3406 , p3407 ,
+ p3408 , p3409 , p3410 , p3411 , p3412 , p3413 , p3414 , p3415 , p3416 ,
+ p3417 , p3418 , p3419 , p3420 , p3421 , p3422 , p3423 , p3424 , p3425 ,
+ p3426 , p3427 , p3428 , p3429 , p3430 , p3431 , p3432 , p3433 , p3434 ,
+ p3435 , p3436 , p3437 , p3438 , p3439 , p3440 , p3441 , p3442 , p3443 ,
+ p3444 , p3445 , p3446 , p3447 , p3448 , p3449 , p3450 , p3451 , p3452 ,
+ p3453 , p3454 , p3455 , p3456 , p3457 , p3458 , p3459 , p3460 , p3461 ,
+ p3462 , p3463 , p3464 , p3465 , p3466 , p3467 , p3468 , p3469 , p3470 ,
+ p3471 , p3472 , p3473 , p3474 , p3475 , p3476 , p3477 , p3478 , p3479 ,
+ p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , p3487 , p3488 ,
+ p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , p3496 , p3497 ,
+ p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , p3505 , p3506 ,
+ p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , p3514 , p3515 ,
+ p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 ) ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:0] IO_ISOL_N ;
+input [0:0] clk ;
+input [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+input sc_head ;
+output sc_tail ;
+input h_incr0 ;
+input p0 ;
+input p1 ;
+input p2 ;
+input p3 ;
+input p4 ;
+input p5 ;
+input p6 ;
+input p7 ;
+input p8 ;
+input p9 ;
+input p10 ;
+input p11 ;
+input p12 ;
+input p13 ;
+input p14 ;
+input p15 ;
+input p16 ;
+input p17 ;
+input p18 ;
+input p19 ;
+input p20 ;
+input p21 ;
+input p22 ;
+input p23 ;
+input p24 ;
+input p25 ;
+input p26 ;
+input p27 ;
+input p28 ;
+input p29 ;
+input p30 ;
+input p31 ;
+input p32 ;
+input p33 ;
+input p34 ;
+input p35 ;
+input p36 ;
+input p37 ;
+input p38 ;
+input p39 ;
+input p40 ;
+input p41 ;
+input p42 ;
+input p43 ;
+input p44 ;
+input p45 ;
+input p46 ;
+input p47 ;
+input p48 ;
+input p49 ;
+input p50 ;
+input p51 ;
+input p52 ;
+input p53 ;
+input p54 ;
+input p55 ;
+input p56 ;
+input p57 ;
+input p58 ;
+input p59 ;
+input p60 ;
+input p61 ;
+input p62 ;
+input p63 ;
+input p64 ;
+input p65 ;
+input p66 ;
+input p67 ;
+input p68 ;
+input p69 ;
+input p70 ;
+input p71 ;
+input p72 ;
+input p73 ;
+input p74 ;
+input p75 ;
+input p76 ;
+input p77 ;
+input p78 ;
+input p79 ;
+input p80 ;
+input p81 ;
+input p82 ;
+input p83 ;
+input p84 ;
+input p85 ;
+input p86 ;
+input p87 ;
+input p88 ;
+input p89 ;
+input p90 ;
+input p91 ;
+input p92 ;
+input p93 ;
+input p94 ;
+input p95 ;
+input p96 ;
+input p97 ;
+input p98 ;
+input p99 ;
+input p100 ;
+input p101 ;
+input p102 ;
+input p103 ;
+input p104 ;
+input p105 ;
+input p106 ;
+input p107 ;
+input p108 ;
+input p109 ;
+input p110 ;
+input p111 ;
+input p112 ;
+input p113 ;
+input p114 ;
+input p115 ;
+input p116 ;
+input p117 ;
+input p118 ;
+input p119 ;
+input p120 ;
+input p121 ;
+input p122 ;
+input p123 ;
+input p124 ;
+input p125 ;
+input p126 ;
+input p127 ;
+input p128 ;
+input p129 ;
+input p130 ;
+input p131 ;
+input p132 ;
+input p133 ;
+input p134 ;
+input p135 ;
+input p136 ;
+input p137 ;
+input p138 ;
+input p139 ;
+input p140 ;
+input p141 ;
+input p142 ;
+input p143 ;
+input p144 ;
+input p145 ;
+input p146 ;
+input p147 ;
+input p148 ;
+input p149 ;
+input p150 ;
+input p151 ;
+input p152 ;
+input p153 ;
+input p154 ;
+input p155 ;
+input p156 ;
+input p157 ;
+input p158 ;
+input p159 ;
+input p160 ;
+input p161 ;
+input p162 ;
+input p163 ;
+input p164 ;
+input p165 ;
+input p166 ;
+input p167 ;
+input p168 ;
+input p169 ;
+input p170 ;
+input p171 ;
+input p172 ;
+input p173 ;
+input p174 ;
+input p175 ;
+input p176 ;
+input p177 ;
+input p178 ;
+input p179 ;
+input p180 ;
+input p181 ;
+input p182 ;
+input p183 ;
+input p184 ;
+input p185 ;
+input p186 ;
+input p187 ;
+input p188 ;
+input p189 ;
+input p190 ;
+input p191 ;
+input p192 ;
+input p193 ;
+input p194 ;
+input p195 ;
+input p196 ;
+input p197 ;
+input p198 ;
+input p199 ;
+input p200 ;
+input p201 ;
+input p202 ;
+input p203 ;
+input p204 ;
+input p205 ;
+input p206 ;
+input p207 ;
+input p208 ;
+input p209 ;
+input p210 ;
+input p211 ;
+input p212 ;
+input p213 ;
+input p214 ;
+input p215 ;
+input p216 ;
+input p217 ;
+input p218 ;
+input p219 ;
+input p220 ;
+input p221 ;
+input p222 ;
+input p223 ;
+input p224 ;
+input p225 ;
+input p226 ;
+input p227 ;
+input p228 ;
+input p229 ;
+input p230 ;
+input p231 ;
+input p232 ;
+input p233 ;
+input p234 ;
+input p235 ;
+input p236 ;
+input p237 ;
+input p238 ;
+input p239 ;
+input p240 ;
+input p241 ;
+input p242 ;
+input p243 ;
+input p244 ;
+input p245 ;
+input p246 ;
+input p247 ;
+input p248 ;
+input p249 ;
+input p250 ;
+input p251 ;
+input p252 ;
+input p253 ;
+input p254 ;
+input p255 ;
+input p256 ;
+input p257 ;
+input p258 ;
+input p259 ;
+input p260 ;
+input p261 ;
+input p262 ;
+input p263 ;
+input p264 ;
+input p265 ;
+input p266 ;
+input p267 ;
+input p268 ;
+input p269 ;
+input p270 ;
+input p271 ;
+input p272 ;
+input p273 ;
+input p274 ;
+input p275 ;
+input p276 ;
+input p277 ;
+input p278 ;
+input p279 ;
+input p280 ;
+input p281 ;
+input p282 ;
+input p283 ;
+input p284 ;
+input p285 ;
+input p286 ;
+input p287 ;
+input p288 ;
+input p289 ;
+input p290 ;
+input p291 ;
+input p292 ;
+input p293 ;
+input p294 ;
+input p295 ;
+input p296 ;
+input p297 ;
+input p298 ;
+input p299 ;
+input p300 ;
+input p301 ;
+input p302 ;
+input p303 ;
+input p304 ;
+input p305 ;
+input p306 ;
+input p307 ;
+input p308 ;
+input p309 ;
+input p310 ;
+input p311 ;
+input p312 ;
+input p313 ;
+input p314 ;
+input p315 ;
+input p316 ;
+input p317 ;
+input p318 ;
+input p319 ;
+input p320 ;
+input p321 ;
+input p322 ;
+input p323 ;
+input p324 ;
+input p325 ;
+input p326 ;
+input p327 ;
+input p328 ;
+input p329 ;
+input p330 ;
+input p331 ;
+input p332 ;
+input p333 ;
+input p334 ;
+input p335 ;
+input p336 ;
+input p337 ;
+input p338 ;
+input p339 ;
+input p340 ;
+input p341 ;
+input p342 ;
+input p343 ;
+input p344 ;
+input p345 ;
+input p346 ;
+input p347 ;
+input p348 ;
+input p349 ;
+input p350 ;
+input p351 ;
+input p352 ;
+input p353 ;
+input p354 ;
+input p355 ;
+input p356 ;
+input p357 ;
+input p358 ;
+input p359 ;
+input p360 ;
+input p361 ;
+input p362 ;
+input p363 ;
+input p364 ;
+input p365 ;
+input p366 ;
+input p367 ;
+input p368 ;
+input p369 ;
+input p370 ;
+input p371 ;
+input p372 ;
+input p373 ;
+input p374 ;
+input p375 ;
+input p376 ;
+input p377 ;
+input p378 ;
+input p379 ;
+input p380 ;
+input p381 ;
+input p382 ;
+input p383 ;
+input p384 ;
+input p385 ;
+input p386 ;
+input p387 ;
+input p388 ;
+input p389 ;
+input p390 ;
+input p391 ;
+input p392 ;
+input p393 ;
+input p394 ;
+input p395 ;
+input p396 ;
+input p397 ;
+input p398 ;
+input p399 ;
+input p400 ;
+input p401 ;
+input p402 ;
+input p403 ;
+input p404 ;
+input p405 ;
+input p406 ;
+input p407 ;
+input p408 ;
+input p409 ;
+input p410 ;
+input p411 ;
+input p412 ;
+input p413 ;
+input p414 ;
+input p415 ;
+input p416 ;
+input p417 ;
+input p418 ;
+input p419 ;
+input p420 ;
+input p421 ;
+input p422 ;
+input p423 ;
+input p424 ;
+input p425 ;
+input p426 ;
+input p427 ;
+input p428 ;
+input p429 ;
+input p430 ;
+input p431 ;
+input p432 ;
+input p433 ;
+input p434 ;
+input p435 ;
+input p436 ;
+input p437 ;
+input p438 ;
+input p439 ;
+input p440 ;
+input p441 ;
+input p442 ;
+input p443 ;
+input p444 ;
+input p445 ;
+input p446 ;
+input p447 ;
+input p448 ;
+input p449 ;
+input p450 ;
+input p451 ;
+input p452 ;
+input p453 ;
+input p454 ;
+input p455 ;
+input p456 ;
+input p457 ;
+input p458 ;
+input p459 ;
+input p460 ;
+input p461 ;
+input p462 ;
+input p463 ;
+input p464 ;
+input p465 ;
+input p466 ;
+input p467 ;
+input p468 ;
+input p469 ;
+input p470 ;
+input p471 ;
+input p472 ;
+input p473 ;
+input p474 ;
+input p475 ;
+input p476 ;
+input p477 ;
+input p478 ;
+input p479 ;
+input p480 ;
+input p481 ;
+input p482 ;
+input p483 ;
+input p484 ;
+input p485 ;
+input p486 ;
+input p487 ;
+input p488 ;
+input p489 ;
+input p490 ;
+input p491 ;
+input p492 ;
+input p493 ;
+input p494 ;
+input p495 ;
+input p496 ;
+input p497 ;
+input p498 ;
+input p499 ;
+input p500 ;
+input p501 ;
+input p502 ;
+input p503 ;
+input p504 ;
+input p505 ;
+input p506 ;
+input p507 ;
+input p508 ;
+input p509 ;
+input p510 ;
+input p511 ;
+input p512 ;
+input p513 ;
+input p514 ;
+input p515 ;
+input p516 ;
+input p517 ;
+input p518 ;
+input p519 ;
+input p520 ;
+input p521 ;
+input p522 ;
+input p523 ;
+input p524 ;
+input p525 ;
+input p526 ;
+input p527 ;
+input p528 ;
+input p529 ;
+input p530 ;
+input p531 ;
+input p532 ;
+input p533 ;
+input p534 ;
+input p535 ;
+input p536 ;
+input p537 ;
+input p538 ;
+input p539 ;
+input p540 ;
+input p541 ;
+input p542 ;
+input p543 ;
+input p544 ;
+input p545 ;
+input p546 ;
+input p547 ;
+input p548 ;
+input p549 ;
+input p550 ;
+input p551 ;
+input p552 ;
+input p553 ;
+input p554 ;
+input p555 ;
+input p556 ;
+input p557 ;
+input p558 ;
+input p559 ;
+input p560 ;
+input p561 ;
+input p562 ;
+input p563 ;
+input p564 ;
+input p565 ;
+input p566 ;
+input p567 ;
+input p568 ;
+input p569 ;
+input p570 ;
+input p571 ;
+input p572 ;
+input p573 ;
+input p574 ;
+input p575 ;
+input p576 ;
+input p577 ;
+input p578 ;
+input p579 ;
+input p580 ;
+input p581 ;
+input p582 ;
+input p583 ;
+input p584 ;
+input p585 ;
+input p586 ;
+input p587 ;
+input p588 ;
+input p589 ;
+input p590 ;
+input p591 ;
+input p592 ;
+input p593 ;
+input p594 ;
+input p595 ;
+input p596 ;
+input p597 ;
+input p598 ;
+input p599 ;
+input p600 ;
+input p601 ;
+input p602 ;
+input p603 ;
+input p604 ;
+input p605 ;
+input p606 ;
+input p607 ;
+input p608 ;
+input p609 ;
+input p610 ;
+input p611 ;
+input p612 ;
+input p613 ;
+input p614 ;
+input p615 ;
+input p616 ;
+input p617 ;
+input p618 ;
+input p619 ;
+input p620 ;
+input p621 ;
+input p622 ;
+input p623 ;
+input p624 ;
+input p625 ;
+input p626 ;
+input p627 ;
+input p628 ;
+input p629 ;
+input p630 ;
+input p631 ;
+input p632 ;
+input p633 ;
+input p634 ;
+input p635 ;
+input p636 ;
+input p637 ;
+input p638 ;
+input p639 ;
+input p640 ;
+input p641 ;
+input p642 ;
+input p643 ;
+input p644 ;
+input p645 ;
+input p646 ;
+input p647 ;
+input p648 ;
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+wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__0_ccff_tail ;
+wire [0:19] cbx_1__0__0_chanx_left_out ;
+wire [0:19] cbx_1__0__0_chanx_right_out ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__10_ccff_tail ;
+wire [0:19] cbx_1__0__10_chanx_left_out ;
+wire [0:19] cbx_1__0__10_chanx_right_out ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__11_ccff_tail ;
+wire [0:19] cbx_1__0__11_chanx_left_out ;
+wire [0:19] cbx_1__0__11_chanx_right_out ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__1_ccff_tail ;
+wire [0:19] cbx_1__0__1_chanx_left_out ;
+wire [0:19] cbx_1__0__1_chanx_right_out ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__2_ccff_tail ;
+wire [0:19] cbx_1__0__2_chanx_left_out ;
+wire [0:19] cbx_1__0__2_chanx_right_out ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__3_ccff_tail ;
+wire [0:19] cbx_1__0__3_chanx_left_out ;
+wire [0:19] cbx_1__0__3_chanx_right_out ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__4_ccff_tail ;
+wire [0:19] cbx_1__0__4_chanx_left_out ;
+wire [0:19] cbx_1__0__4_chanx_right_out ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__5_ccff_tail ;
+wire [0:19] cbx_1__0__5_chanx_left_out ;
+wire [0:19] cbx_1__0__5_chanx_right_out ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__6_ccff_tail ;
+wire [0:19] cbx_1__0__6_chanx_left_out ;
+wire [0:19] cbx_1__0__6_chanx_right_out ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__7_ccff_tail ;
+wire [0:19] cbx_1__0__7_chanx_left_out ;
+wire [0:19] cbx_1__0__7_chanx_right_out ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__8_ccff_tail ;
+wire [0:19] cbx_1__0__8_chanx_left_out ;
+wire [0:19] cbx_1__0__8_chanx_right_out ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__9_ccff_tail ;
+wire [0:19] cbx_1__0__9_chanx_left_out ;
+wire [0:19] cbx_1__0__9_chanx_right_out ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__0_ccff_tail ;
+wire [0:19] cbx_1__12__0_chanx_left_out ;
+wire [0:19] cbx_1__12__0_chanx_right_out ;
+wire [0:0] cbx_1__12__0_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__10_ccff_tail ;
+wire [0:19] cbx_1__12__10_chanx_left_out ;
+wire [0:19] cbx_1__12__10_chanx_right_out ;
+wire [0:0] cbx_1__12__10_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__11_ccff_tail ;
+wire [0:19] cbx_1__12__11_chanx_left_out ;
+wire [0:19] cbx_1__12__11_chanx_right_out ;
+wire [0:0] cbx_1__12__11_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__1_ccff_tail ;
+wire [0:19] cbx_1__12__1_chanx_left_out ;
+wire [0:19] cbx_1__12__1_chanx_right_out ;
+wire [0:0] cbx_1__12__1_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__2_ccff_tail ;
+wire [0:19] cbx_1__12__2_chanx_left_out ;
+wire [0:19] cbx_1__12__2_chanx_right_out ;
+wire [0:0] cbx_1__12__2_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__3_ccff_tail ;
+wire [0:19] cbx_1__12__3_chanx_left_out ;
+wire [0:19] cbx_1__12__3_chanx_right_out ;
+wire [0:0] cbx_1__12__3_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__4_ccff_tail ;
+wire [0:19] cbx_1__12__4_chanx_left_out ;
+wire [0:19] cbx_1__12__4_chanx_right_out ;
+wire [0:0] cbx_1__12__4_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__5_ccff_tail ;
+wire [0:19] cbx_1__12__5_chanx_left_out ;
+wire [0:19] cbx_1__12__5_chanx_right_out ;
+wire [0:0] cbx_1__12__5_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__6_ccff_tail ;
+wire [0:19] cbx_1__12__6_chanx_left_out ;
+wire [0:19] cbx_1__12__6_chanx_right_out ;
+wire [0:0] cbx_1__12__6_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__7_ccff_tail ;
+wire [0:19] cbx_1__12__7_chanx_left_out ;
+wire [0:19] cbx_1__12__7_chanx_right_out ;
+wire [0:0] cbx_1__12__7_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__8_ccff_tail ;
+wire [0:19] cbx_1__12__8_chanx_left_out ;
+wire [0:19] cbx_1__12__8_chanx_right_out ;
+wire [0:0] cbx_1__12__8_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__9_ccff_tail ;
+wire [0:19] cbx_1__12__9_chanx_left_out ;
+wire [0:19] cbx_1__12__9_chanx_right_out ;
+wire [0:0] cbx_1__12__9_top_grid_pin_0_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__0_ccff_tail ;
+wire [0:19] cbx_1__1__0_chanx_left_out ;
+wire [0:19] cbx_1__1__0_chanx_right_out ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__100_ccff_tail ;
+wire [0:19] cbx_1__1__100_chanx_left_out ;
+wire [0:19] cbx_1__1__100_chanx_right_out ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__101_ccff_tail ;
+wire [0:19] cbx_1__1__101_chanx_left_out ;
+wire [0:19] cbx_1__1__101_chanx_right_out ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__102_ccff_tail ;
+wire [0:19] cbx_1__1__102_chanx_left_out ;
+wire [0:19] cbx_1__1__102_chanx_right_out ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__103_ccff_tail ;
+wire [0:19] cbx_1__1__103_chanx_left_out ;
+wire [0:19] cbx_1__1__103_chanx_right_out ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__104_ccff_tail ;
+wire [0:19] cbx_1__1__104_chanx_left_out ;
+wire [0:19] cbx_1__1__104_chanx_right_out ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__105_ccff_tail ;
+wire [0:19] cbx_1__1__105_chanx_left_out ;
+wire [0:19] cbx_1__1__105_chanx_right_out ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__106_ccff_tail ;
+wire [0:19] cbx_1__1__106_chanx_left_out ;
+wire [0:19] cbx_1__1__106_chanx_right_out ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__107_ccff_tail ;
+wire [0:19] cbx_1__1__107_chanx_left_out ;
+wire [0:19] cbx_1__1__107_chanx_right_out ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__108_ccff_tail ;
+wire [0:19] cbx_1__1__108_chanx_left_out ;
+wire [0:19] cbx_1__1__108_chanx_right_out ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__109_ccff_tail ;
+wire [0:19] cbx_1__1__109_chanx_left_out ;
+wire [0:19] cbx_1__1__109_chanx_right_out ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__10_ccff_tail ;
+wire [0:19] cbx_1__1__10_chanx_left_out ;
+wire [0:19] cbx_1__1__10_chanx_right_out ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__110_ccff_tail ;
+wire [0:19] cbx_1__1__110_chanx_left_out ;
+wire [0:19] cbx_1__1__110_chanx_right_out ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__111_ccff_tail ;
+wire [0:19] cbx_1__1__111_chanx_left_out ;
+wire [0:19] cbx_1__1__111_chanx_right_out ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__112_ccff_tail ;
+wire [0:19] cbx_1__1__112_chanx_left_out ;
+wire [0:19] cbx_1__1__112_chanx_right_out ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__113_ccff_tail ;
+wire [0:19] cbx_1__1__113_chanx_left_out ;
+wire [0:19] cbx_1__1__113_chanx_right_out ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__114_ccff_tail ;
+wire [0:19] cbx_1__1__114_chanx_left_out ;
+wire [0:19] cbx_1__1__114_chanx_right_out ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__115_ccff_tail ;
+wire [0:19] cbx_1__1__115_chanx_left_out ;
+wire [0:19] cbx_1__1__115_chanx_right_out ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__116_ccff_tail ;
+wire [0:19] cbx_1__1__116_chanx_left_out ;
+wire [0:19] cbx_1__1__116_chanx_right_out ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__117_ccff_tail ;
+wire [0:19] cbx_1__1__117_chanx_left_out ;
+wire [0:19] cbx_1__1__117_chanx_right_out ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__118_ccff_tail ;
+wire [0:19] cbx_1__1__118_chanx_left_out ;
+wire [0:19] cbx_1__1__118_chanx_right_out ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__119_ccff_tail ;
+wire [0:19] cbx_1__1__119_chanx_left_out ;
+wire [0:19] cbx_1__1__119_chanx_right_out ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__11_ccff_tail ;
+wire [0:19] cbx_1__1__11_chanx_left_out ;
+wire [0:19] cbx_1__1__11_chanx_right_out ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__120_ccff_tail ;
+wire [0:19] cbx_1__1__120_chanx_left_out ;
+wire [0:19] cbx_1__1__120_chanx_right_out ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__121_ccff_tail ;
+wire [0:19] cbx_1__1__121_chanx_left_out ;
+wire [0:19] cbx_1__1__121_chanx_right_out ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__122_ccff_tail ;
+wire [0:19] cbx_1__1__122_chanx_left_out ;
+wire [0:19] cbx_1__1__122_chanx_right_out ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__123_ccff_tail ;
+wire [0:19] cbx_1__1__123_chanx_left_out ;
+wire [0:19] cbx_1__1__123_chanx_right_out ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__124_ccff_tail ;
+wire [0:19] cbx_1__1__124_chanx_left_out ;
+wire [0:19] cbx_1__1__124_chanx_right_out ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__125_ccff_tail ;
+wire [0:19] cbx_1__1__125_chanx_left_out ;
+wire [0:19] cbx_1__1__125_chanx_right_out ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__126_ccff_tail ;
+wire [0:19] cbx_1__1__126_chanx_left_out ;
+wire [0:19] cbx_1__1__126_chanx_right_out ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__127_ccff_tail ;
+wire [0:19] cbx_1__1__127_chanx_left_out ;
+wire [0:19] cbx_1__1__127_chanx_right_out ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__128_ccff_tail ;
+wire [0:19] cbx_1__1__128_chanx_left_out ;
+wire [0:19] cbx_1__1__128_chanx_right_out ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__129_ccff_tail ;
+wire [0:19] cbx_1__1__129_chanx_left_out ;
+wire [0:19] cbx_1__1__129_chanx_right_out ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__12_ccff_tail ;
+wire [0:19] cbx_1__1__12_chanx_left_out ;
+wire [0:19] cbx_1__1__12_chanx_right_out ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__130_ccff_tail ;
+wire [0:19] cbx_1__1__130_chanx_left_out ;
+wire [0:19] cbx_1__1__130_chanx_right_out ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__131_ccff_tail ;
+wire [0:19] cbx_1__1__131_chanx_left_out ;
+wire [0:19] cbx_1__1__131_chanx_right_out ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__13_ccff_tail ;
+wire [0:19] cbx_1__1__13_chanx_left_out ;
+wire [0:19] cbx_1__1__13_chanx_right_out ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__14_ccff_tail ;
+wire [0:19] cbx_1__1__14_chanx_left_out ;
+wire [0:19] cbx_1__1__14_chanx_right_out ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__15_ccff_tail ;
+wire [0:19] cbx_1__1__15_chanx_left_out ;
+wire [0:19] cbx_1__1__15_chanx_right_out ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__16_ccff_tail ;
+wire [0:19] cbx_1__1__16_chanx_left_out ;
+wire [0:19] cbx_1__1__16_chanx_right_out ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__17_ccff_tail ;
+wire [0:19] cbx_1__1__17_chanx_left_out ;
+wire [0:19] cbx_1__1__17_chanx_right_out ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__18_ccff_tail ;
+wire [0:19] cbx_1__1__18_chanx_left_out ;
+wire [0:19] cbx_1__1__18_chanx_right_out ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__19_ccff_tail ;
+wire [0:19] cbx_1__1__19_chanx_left_out ;
+wire [0:19] cbx_1__1__19_chanx_right_out ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__1_ccff_tail ;
+wire [0:19] cbx_1__1__1_chanx_left_out ;
+wire [0:19] cbx_1__1__1_chanx_right_out ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__20_ccff_tail ;
+wire [0:19] cbx_1__1__20_chanx_left_out ;
+wire [0:19] cbx_1__1__20_chanx_right_out ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__21_ccff_tail ;
+wire [0:19] cbx_1__1__21_chanx_left_out ;
+wire [0:19] cbx_1__1__21_chanx_right_out ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__22_ccff_tail ;
+wire [0:19] cbx_1__1__22_chanx_left_out ;
+wire [0:19] cbx_1__1__22_chanx_right_out ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__23_ccff_tail ;
+wire [0:19] cbx_1__1__23_chanx_left_out ;
+wire [0:19] cbx_1__1__23_chanx_right_out ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__24_ccff_tail ;
+wire [0:19] cbx_1__1__24_chanx_left_out ;
+wire [0:19] cbx_1__1__24_chanx_right_out ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__25_ccff_tail ;
+wire [0:19] cbx_1__1__25_chanx_left_out ;
+wire [0:19] cbx_1__1__25_chanx_right_out ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__26_ccff_tail ;
+wire [0:19] cbx_1__1__26_chanx_left_out ;
+wire [0:19] cbx_1__1__26_chanx_right_out ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__27_ccff_tail ;
+wire [0:19] cbx_1__1__27_chanx_left_out ;
+wire [0:19] cbx_1__1__27_chanx_right_out ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__28_ccff_tail ;
+wire [0:19] cbx_1__1__28_chanx_left_out ;
+wire [0:19] cbx_1__1__28_chanx_right_out ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__29_ccff_tail ;
+wire [0:19] cbx_1__1__29_chanx_left_out ;
+wire [0:19] cbx_1__1__29_chanx_right_out ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__2_ccff_tail ;
+wire [0:19] cbx_1__1__2_chanx_left_out ;
+wire [0:19] cbx_1__1__2_chanx_right_out ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__30_ccff_tail ;
+wire [0:19] cbx_1__1__30_chanx_left_out ;
+wire [0:19] cbx_1__1__30_chanx_right_out ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__31_ccff_tail ;
+wire [0:19] cbx_1__1__31_chanx_left_out ;
+wire [0:19] cbx_1__1__31_chanx_right_out ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__32_ccff_tail ;
+wire [0:19] cbx_1__1__32_chanx_left_out ;
+wire [0:19] cbx_1__1__32_chanx_right_out ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__33_ccff_tail ;
+wire [0:19] cbx_1__1__33_chanx_left_out ;
+wire [0:19] cbx_1__1__33_chanx_right_out ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__34_ccff_tail ;
+wire [0:19] cbx_1__1__34_chanx_left_out ;
+wire [0:19] cbx_1__1__34_chanx_right_out ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__35_ccff_tail ;
+wire [0:19] cbx_1__1__35_chanx_left_out ;
+wire [0:19] cbx_1__1__35_chanx_right_out ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__36_ccff_tail ;
+wire [0:19] cbx_1__1__36_chanx_left_out ;
+wire [0:19] cbx_1__1__36_chanx_right_out ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__37_ccff_tail ;
+wire [0:19] cbx_1__1__37_chanx_left_out ;
+wire [0:19] cbx_1__1__37_chanx_right_out ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__38_ccff_tail ;
+wire [0:19] cbx_1__1__38_chanx_left_out ;
+wire [0:19] cbx_1__1__38_chanx_right_out ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__39_ccff_tail ;
+wire [0:19] cbx_1__1__39_chanx_left_out ;
+wire [0:19] cbx_1__1__39_chanx_right_out ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__3_ccff_tail ;
+wire [0:19] cbx_1__1__3_chanx_left_out ;
+wire [0:19] cbx_1__1__3_chanx_right_out ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__40_ccff_tail ;
+wire [0:19] cbx_1__1__40_chanx_left_out ;
+wire [0:19] cbx_1__1__40_chanx_right_out ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__41_ccff_tail ;
+wire [0:19] cbx_1__1__41_chanx_left_out ;
+wire [0:19] cbx_1__1__41_chanx_right_out ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__42_ccff_tail ;
+wire [0:19] cbx_1__1__42_chanx_left_out ;
+wire [0:19] cbx_1__1__42_chanx_right_out ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__43_ccff_tail ;
+wire [0:19] cbx_1__1__43_chanx_left_out ;
+wire [0:19] cbx_1__1__43_chanx_right_out ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__44_ccff_tail ;
+wire [0:19] cbx_1__1__44_chanx_left_out ;
+wire [0:19] cbx_1__1__44_chanx_right_out ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__45_ccff_tail ;
+wire [0:19] cbx_1__1__45_chanx_left_out ;
+wire [0:19] cbx_1__1__45_chanx_right_out ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__46_ccff_tail ;
+wire [0:19] cbx_1__1__46_chanx_left_out ;
+wire [0:19] cbx_1__1__46_chanx_right_out ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__47_ccff_tail ;
+wire [0:19] cbx_1__1__47_chanx_left_out ;
+wire [0:19] cbx_1__1__47_chanx_right_out ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__48_ccff_tail ;
+wire [0:19] cbx_1__1__48_chanx_left_out ;
+wire [0:19] cbx_1__1__48_chanx_right_out ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__49_ccff_tail ;
+wire [0:19] cbx_1__1__49_chanx_left_out ;
+wire [0:19] cbx_1__1__49_chanx_right_out ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__4_ccff_tail ;
+wire [0:19] cbx_1__1__4_chanx_left_out ;
+wire [0:19] cbx_1__1__4_chanx_right_out ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__50_ccff_tail ;
+wire [0:19] cbx_1__1__50_chanx_left_out ;
+wire [0:19] cbx_1__1__50_chanx_right_out ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__51_ccff_tail ;
+wire [0:19] cbx_1__1__51_chanx_left_out ;
+wire [0:19] cbx_1__1__51_chanx_right_out ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__52_ccff_tail ;
+wire [0:19] cbx_1__1__52_chanx_left_out ;
+wire [0:19] cbx_1__1__52_chanx_right_out ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__53_ccff_tail ;
+wire [0:19] cbx_1__1__53_chanx_left_out ;
+wire [0:19] cbx_1__1__53_chanx_right_out ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__54_ccff_tail ;
+wire [0:19] cbx_1__1__54_chanx_left_out ;
+wire [0:19] cbx_1__1__54_chanx_right_out ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__55_ccff_tail ;
+wire [0:19] cbx_1__1__55_chanx_left_out ;
+wire [0:19] cbx_1__1__55_chanx_right_out ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__56_ccff_tail ;
+wire [0:19] cbx_1__1__56_chanx_left_out ;
+wire [0:19] cbx_1__1__56_chanx_right_out ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__57_ccff_tail ;
+wire [0:19] cbx_1__1__57_chanx_left_out ;
+wire [0:19] cbx_1__1__57_chanx_right_out ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__58_ccff_tail ;
+wire [0:19] cbx_1__1__58_chanx_left_out ;
+wire [0:19] cbx_1__1__58_chanx_right_out ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__59_ccff_tail ;
+wire [0:19] cbx_1__1__59_chanx_left_out ;
+wire [0:19] cbx_1__1__59_chanx_right_out ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__5_ccff_tail ;
+wire [0:19] cbx_1__1__5_chanx_left_out ;
+wire [0:19] cbx_1__1__5_chanx_right_out ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__60_ccff_tail ;
+wire [0:19] cbx_1__1__60_chanx_left_out ;
+wire [0:19] cbx_1__1__60_chanx_right_out ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__61_ccff_tail ;
+wire [0:19] cbx_1__1__61_chanx_left_out ;
+wire [0:19] cbx_1__1__61_chanx_right_out ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__62_ccff_tail ;
+wire [0:19] cbx_1__1__62_chanx_left_out ;
+wire [0:19] cbx_1__1__62_chanx_right_out ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__63_ccff_tail ;
+wire [0:19] cbx_1__1__63_chanx_left_out ;
+wire [0:19] cbx_1__1__63_chanx_right_out ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__64_ccff_tail ;
+wire [0:19] cbx_1__1__64_chanx_left_out ;
+wire [0:19] cbx_1__1__64_chanx_right_out ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__65_ccff_tail ;
+wire [0:19] cbx_1__1__65_chanx_left_out ;
+wire [0:19] cbx_1__1__65_chanx_right_out ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__66_ccff_tail ;
+wire [0:19] cbx_1__1__66_chanx_left_out ;
+wire [0:19] cbx_1__1__66_chanx_right_out ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__67_ccff_tail ;
+wire [0:19] cbx_1__1__67_chanx_left_out ;
+wire [0:19] cbx_1__1__67_chanx_right_out ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__68_ccff_tail ;
+wire [0:19] cbx_1__1__68_chanx_left_out ;
+wire [0:19] cbx_1__1__68_chanx_right_out ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__69_ccff_tail ;
+wire [0:19] cbx_1__1__69_chanx_left_out ;
+wire [0:19] cbx_1__1__69_chanx_right_out ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__6_ccff_tail ;
+wire [0:19] cbx_1__1__6_chanx_left_out ;
+wire [0:19] cbx_1__1__6_chanx_right_out ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__70_ccff_tail ;
+wire [0:19] cbx_1__1__70_chanx_left_out ;
+wire [0:19] cbx_1__1__70_chanx_right_out ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__71_ccff_tail ;
+wire [0:19] cbx_1__1__71_chanx_left_out ;
+wire [0:19] cbx_1__1__71_chanx_right_out ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__72_ccff_tail ;
+wire [0:19] cbx_1__1__72_chanx_left_out ;
+wire [0:19] cbx_1__1__72_chanx_right_out ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__73_ccff_tail ;
+wire [0:19] cbx_1__1__73_chanx_left_out ;
+wire [0:19] cbx_1__1__73_chanx_right_out ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__74_ccff_tail ;
+wire [0:19] cbx_1__1__74_chanx_left_out ;
+wire [0:19] cbx_1__1__74_chanx_right_out ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__75_ccff_tail ;
+wire [0:19] cbx_1__1__75_chanx_left_out ;
+wire [0:19] cbx_1__1__75_chanx_right_out ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__76_ccff_tail ;
+wire [0:19] cbx_1__1__76_chanx_left_out ;
+wire [0:19] cbx_1__1__76_chanx_right_out ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__77_ccff_tail ;
+wire [0:19] cbx_1__1__77_chanx_left_out ;
+wire [0:19] cbx_1__1__77_chanx_right_out ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__78_ccff_tail ;
+wire [0:19] cbx_1__1__78_chanx_left_out ;
+wire [0:19] cbx_1__1__78_chanx_right_out ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__79_ccff_tail ;
+wire [0:19] cbx_1__1__79_chanx_left_out ;
+wire [0:19] cbx_1__1__79_chanx_right_out ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__7_ccff_tail ;
+wire [0:19] cbx_1__1__7_chanx_left_out ;
+wire [0:19] cbx_1__1__7_chanx_right_out ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__80_ccff_tail ;
+wire [0:19] cbx_1__1__80_chanx_left_out ;
+wire [0:19] cbx_1__1__80_chanx_right_out ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__81_ccff_tail ;
+wire [0:19] cbx_1__1__81_chanx_left_out ;
+wire [0:19] cbx_1__1__81_chanx_right_out ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__82_ccff_tail ;
+wire [0:19] cbx_1__1__82_chanx_left_out ;
+wire [0:19] cbx_1__1__82_chanx_right_out ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__83_ccff_tail ;
+wire [0:19] cbx_1__1__83_chanx_left_out ;
+wire [0:19] cbx_1__1__83_chanx_right_out ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__84_ccff_tail ;
+wire [0:19] cbx_1__1__84_chanx_left_out ;
+wire [0:19] cbx_1__1__84_chanx_right_out ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__85_ccff_tail ;
+wire [0:19] cbx_1__1__85_chanx_left_out ;
+wire [0:19] cbx_1__1__85_chanx_right_out ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__86_ccff_tail ;
+wire [0:19] cbx_1__1__86_chanx_left_out ;
+wire [0:19] cbx_1__1__86_chanx_right_out ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__87_ccff_tail ;
+wire [0:19] cbx_1__1__87_chanx_left_out ;
+wire [0:19] cbx_1__1__87_chanx_right_out ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__88_ccff_tail ;
+wire [0:19] cbx_1__1__88_chanx_left_out ;
+wire [0:19] cbx_1__1__88_chanx_right_out ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__89_ccff_tail ;
+wire [0:19] cbx_1__1__89_chanx_left_out ;
+wire [0:19] cbx_1__1__89_chanx_right_out ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__8_ccff_tail ;
+wire [0:19] cbx_1__1__8_chanx_left_out ;
+wire [0:19] cbx_1__1__8_chanx_right_out ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__90_ccff_tail ;
+wire [0:19] cbx_1__1__90_chanx_left_out ;
+wire [0:19] cbx_1__1__90_chanx_right_out ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__91_ccff_tail ;
+wire [0:19] cbx_1__1__91_chanx_left_out ;
+wire [0:19] cbx_1__1__91_chanx_right_out ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__92_ccff_tail ;
+wire [0:19] cbx_1__1__92_chanx_left_out ;
+wire [0:19] cbx_1__1__92_chanx_right_out ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__93_ccff_tail ;
+wire [0:19] cbx_1__1__93_chanx_left_out ;
+wire [0:19] cbx_1__1__93_chanx_right_out ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__94_ccff_tail ;
+wire [0:19] cbx_1__1__94_chanx_left_out ;
+wire [0:19] cbx_1__1__94_chanx_right_out ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__95_ccff_tail ;
+wire [0:19] cbx_1__1__95_chanx_left_out ;
+wire [0:19] cbx_1__1__95_chanx_right_out ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__96_ccff_tail ;
+wire [0:19] cbx_1__1__96_chanx_left_out ;
+wire [0:19] cbx_1__1__96_chanx_right_out ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__97_ccff_tail ;
+wire [0:19] cbx_1__1__97_chanx_left_out ;
+wire [0:19] cbx_1__1__97_chanx_right_out ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__98_ccff_tail ;
+wire [0:19] cbx_1__1__98_chanx_left_out ;
+wire [0:19] cbx_1__1__98_chanx_right_out ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__99_ccff_tail ;
+wire [0:19] cbx_1__1__99_chanx_left_out ;
+wire [0:19] cbx_1__1__99_chanx_right_out ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__9_ccff_tail ;
+wire [0:19] cbx_1__1__9_chanx_left_out ;
+wire [0:19] cbx_1__1__9_chanx_right_out ;
+wire [0:0] cby_0__1__0_ccff_tail ;
+wire [0:19] cby_0__1__0_chany_bottom_out ;
+wire [0:19] cby_0__1__0_chany_top_out ;
+wire [0:0] cby_0__1__0_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__10_ccff_tail ;
+wire [0:19] cby_0__1__10_chany_bottom_out ;
+wire [0:19] cby_0__1__10_chany_top_out ;
+wire [0:0] cby_0__1__10_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__11_ccff_tail ;
+wire [0:19] cby_0__1__11_chany_bottom_out ;
+wire [0:19] cby_0__1__11_chany_top_out ;
+wire [0:0] cby_0__1__11_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__1_ccff_tail ;
+wire [0:19] cby_0__1__1_chany_bottom_out ;
+wire [0:19] cby_0__1__1_chany_top_out ;
+wire [0:0] cby_0__1__1_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__2_ccff_tail ;
+wire [0:19] cby_0__1__2_chany_bottom_out ;
+wire [0:19] cby_0__1__2_chany_top_out ;
+wire [0:0] cby_0__1__2_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__3_ccff_tail ;
+wire [0:19] cby_0__1__3_chany_bottom_out ;
+wire [0:19] cby_0__1__3_chany_top_out ;
+wire [0:0] cby_0__1__3_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__4_ccff_tail ;
+wire [0:19] cby_0__1__4_chany_bottom_out ;
+wire [0:19] cby_0__1__4_chany_top_out ;
+wire [0:0] cby_0__1__4_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__5_ccff_tail ;
+wire [0:19] cby_0__1__5_chany_bottom_out ;
+wire [0:19] cby_0__1__5_chany_top_out ;
+wire [0:0] cby_0__1__5_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__6_ccff_tail ;
+wire [0:19] cby_0__1__6_chany_bottom_out ;
+wire [0:19] cby_0__1__6_chany_top_out ;
+wire [0:0] cby_0__1__6_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__7_ccff_tail ;
+wire [0:19] cby_0__1__7_chany_bottom_out ;
+wire [0:19] cby_0__1__7_chany_top_out ;
+wire [0:0] cby_0__1__7_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__8_ccff_tail ;
+wire [0:19] cby_0__1__8_chany_bottom_out ;
+wire [0:19] cby_0__1__8_chany_top_out ;
+wire [0:0] cby_0__1__8_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__9_ccff_tail ;
+wire [0:19] cby_0__1__9_chany_bottom_out ;
+wire [0:19] cby_0__1__9_chany_top_out ;
+wire [0:0] cby_0__1__9_left_grid_pin_0_ ;
+wire [0:0] cby_12__1__0_ccff_tail ;
+wire [0:19] cby_12__1__0_chany_bottom_out ;
+wire [0:19] cby_12__1__0_chany_top_out ;
+wire [0:0] cby_12__1__0_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__0_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__10_ccff_tail ;
+wire [0:19] cby_12__1__10_chany_bottom_out ;
+wire [0:19] cby_12__1__10_chany_top_out ;
+wire [0:0] cby_12__1__10_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__10_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__11_ccff_tail ;
+wire [0:19] cby_12__1__11_chany_bottom_out ;
+wire [0:19] cby_12__1__11_chany_top_out ;
+wire [0:0] cby_12__1__11_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__11_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__1_ccff_tail ;
+wire [0:19] cby_12__1__1_chany_bottom_out ;
+wire [0:19] cby_12__1__1_chany_top_out ;
+wire [0:0] cby_12__1__1_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__1_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__2_ccff_tail ;
+wire [0:19] cby_12__1__2_chany_bottom_out ;
+wire [0:19] cby_12__1__2_chany_top_out ;
+wire [0:0] cby_12__1__2_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__2_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__3_ccff_tail ;
+wire [0:19] cby_12__1__3_chany_bottom_out ;
+wire [0:19] cby_12__1__3_chany_top_out ;
+wire [0:0] cby_12__1__3_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__3_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__4_ccff_tail ;
+wire [0:19] cby_12__1__4_chany_bottom_out ;
+wire [0:19] cby_12__1__4_chany_top_out ;
+wire [0:0] cby_12__1__4_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__4_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__5_ccff_tail ;
+wire [0:19] cby_12__1__5_chany_bottom_out ;
+wire [0:19] cby_12__1__5_chany_top_out ;
+wire [0:0] cby_12__1__5_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__5_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__6_ccff_tail ;
+wire [0:19] cby_12__1__6_chany_bottom_out ;
+wire [0:19] cby_12__1__6_chany_top_out ;
+wire [0:0] cby_12__1__6_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__6_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__7_ccff_tail ;
+wire [0:19] cby_12__1__7_chany_bottom_out ;
+wire [0:19] cby_12__1__7_chany_top_out ;
+wire [0:0] cby_12__1__7_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__7_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__8_ccff_tail ;
+wire [0:19] cby_12__1__8_chany_bottom_out ;
+wire [0:19] cby_12__1__8_chany_top_out ;
+wire [0:0] cby_12__1__8_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__8_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__9_ccff_tail ;
+wire [0:19] cby_12__1__9_chany_bottom_out ;
+wire [0:19] cby_12__1__9_chany_top_out ;
+wire [0:0] cby_12__1__9_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__9_right_grid_pin_0_ ;
+wire [0:0] cby_1__1__0_ccff_tail ;
+wire [0:19] cby_1__1__0_chany_bottom_out ;
+wire [0:19] cby_1__1__0_chany_top_out ;
+wire [0:0] cby_1__1__0_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__100_ccff_tail ;
+wire [0:19] cby_1__1__100_chany_bottom_out ;
+wire [0:19] cby_1__1__100_chany_top_out ;
+wire [0:0] cby_1__1__100_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__101_ccff_tail ;
+wire [0:19] cby_1__1__101_chany_bottom_out ;
+wire [0:19] cby_1__1__101_chany_top_out ;
+wire [0:0] cby_1__1__101_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__102_ccff_tail ;
+wire [0:19] cby_1__1__102_chany_bottom_out ;
+wire [0:19] cby_1__1__102_chany_top_out ;
+wire [0:0] cby_1__1__102_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__103_ccff_tail ;
+wire [0:19] cby_1__1__103_chany_bottom_out ;
+wire [0:19] cby_1__1__103_chany_top_out ;
+wire [0:0] cby_1__1__103_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__104_ccff_tail ;
+wire [0:19] cby_1__1__104_chany_bottom_out ;
+wire [0:19] cby_1__1__104_chany_top_out ;
+wire [0:0] cby_1__1__104_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__105_ccff_tail ;
+wire [0:19] cby_1__1__105_chany_bottom_out ;
+wire [0:19] cby_1__1__105_chany_top_out ;
+wire [0:0] cby_1__1__105_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__106_ccff_tail ;
+wire [0:19] cby_1__1__106_chany_bottom_out ;
+wire [0:19] cby_1__1__106_chany_top_out ;
+wire [0:0] cby_1__1__106_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__107_ccff_tail ;
+wire [0:19] cby_1__1__107_chany_bottom_out ;
+wire [0:19] cby_1__1__107_chany_top_out ;
+wire [0:0] cby_1__1__107_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__108_ccff_tail ;
+wire [0:19] cby_1__1__108_chany_bottom_out ;
+wire [0:19] cby_1__1__108_chany_top_out ;
+wire [0:0] cby_1__1__108_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__109_ccff_tail ;
+wire [0:19] cby_1__1__109_chany_bottom_out ;
+wire [0:19] cby_1__1__109_chany_top_out ;
+wire [0:0] cby_1__1__109_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__10_ccff_tail ;
+wire [0:19] cby_1__1__10_chany_bottom_out ;
+wire [0:19] cby_1__1__10_chany_top_out ;
+wire [0:0] cby_1__1__10_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__110_ccff_tail ;
+wire [0:19] cby_1__1__110_chany_bottom_out ;
+wire [0:19] cby_1__1__110_chany_top_out ;
+wire [0:0] cby_1__1__110_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__111_ccff_tail ;
+wire [0:19] cby_1__1__111_chany_bottom_out ;
+wire [0:19] cby_1__1__111_chany_top_out ;
+wire [0:0] cby_1__1__111_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__112_ccff_tail ;
+wire [0:19] cby_1__1__112_chany_bottom_out ;
+wire [0:19] cby_1__1__112_chany_top_out ;
+wire [0:0] cby_1__1__112_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__113_ccff_tail ;
+wire [0:19] cby_1__1__113_chany_bottom_out ;
+wire [0:19] cby_1__1__113_chany_top_out ;
+wire [0:0] cby_1__1__113_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__114_ccff_tail ;
+wire [0:19] cby_1__1__114_chany_bottom_out ;
+wire [0:19] cby_1__1__114_chany_top_out ;
+wire [0:0] cby_1__1__114_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__115_ccff_tail ;
+wire [0:19] cby_1__1__115_chany_bottom_out ;
+wire [0:19] cby_1__1__115_chany_top_out ;
+wire [0:0] cby_1__1__115_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__116_ccff_tail ;
+wire [0:19] cby_1__1__116_chany_bottom_out ;
+wire [0:19] cby_1__1__116_chany_top_out ;
+wire [0:0] cby_1__1__116_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__117_ccff_tail ;
+wire [0:19] cby_1__1__117_chany_bottom_out ;
+wire [0:19] cby_1__1__117_chany_top_out ;
+wire [0:0] cby_1__1__117_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__118_ccff_tail ;
+wire [0:19] cby_1__1__118_chany_bottom_out ;
+wire [0:19] cby_1__1__118_chany_top_out ;
+wire [0:0] cby_1__1__118_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__119_ccff_tail ;
+wire [0:19] cby_1__1__119_chany_bottom_out ;
+wire [0:19] cby_1__1__119_chany_top_out ;
+wire [0:0] cby_1__1__119_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__11_ccff_tail ;
+wire [0:19] cby_1__1__11_chany_bottom_out ;
+wire [0:19] cby_1__1__11_chany_top_out ;
+wire [0:0] cby_1__1__11_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__120_ccff_tail ;
+wire [0:19] cby_1__1__120_chany_bottom_out ;
+wire [0:19] cby_1__1__120_chany_top_out ;
+wire [0:0] cby_1__1__120_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__121_ccff_tail ;
+wire [0:19] cby_1__1__121_chany_bottom_out ;
+wire [0:19] cby_1__1__121_chany_top_out ;
+wire [0:0] cby_1__1__121_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__122_ccff_tail ;
+wire [0:19] cby_1__1__122_chany_bottom_out ;
+wire [0:19] cby_1__1__122_chany_top_out ;
+wire [0:0] cby_1__1__122_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__123_ccff_tail ;
+wire [0:19] cby_1__1__123_chany_bottom_out ;
+wire [0:19] cby_1__1__123_chany_top_out ;
+wire [0:0] cby_1__1__123_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__124_ccff_tail ;
+wire [0:19] cby_1__1__124_chany_bottom_out ;
+wire [0:19] cby_1__1__124_chany_top_out ;
+wire [0:0] cby_1__1__124_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__125_ccff_tail ;
+wire [0:19] cby_1__1__125_chany_bottom_out ;
+wire [0:19] cby_1__1__125_chany_top_out ;
+wire [0:0] cby_1__1__125_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__126_ccff_tail ;
+wire [0:19] cby_1__1__126_chany_bottom_out ;
+wire [0:19] cby_1__1__126_chany_top_out ;
+wire [0:0] cby_1__1__126_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__127_ccff_tail ;
+wire [0:19] cby_1__1__127_chany_bottom_out ;
+wire [0:19] cby_1__1__127_chany_top_out ;
+wire [0:0] cby_1__1__127_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__128_ccff_tail ;
+wire [0:19] cby_1__1__128_chany_bottom_out ;
+wire [0:19] cby_1__1__128_chany_top_out ;
+wire [0:0] cby_1__1__128_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__129_ccff_tail ;
+wire [0:19] cby_1__1__129_chany_bottom_out ;
+wire [0:19] cby_1__1__129_chany_top_out ;
+wire [0:0] cby_1__1__129_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__12_ccff_tail ;
+wire [0:19] cby_1__1__12_chany_bottom_out ;
+wire [0:19] cby_1__1__12_chany_top_out ;
+wire [0:0] cby_1__1__12_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__130_ccff_tail ;
+wire [0:19] cby_1__1__130_chany_bottom_out ;
+wire [0:19] cby_1__1__130_chany_top_out ;
+wire [0:0] cby_1__1__130_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__131_ccff_tail ;
+wire [0:19] cby_1__1__131_chany_bottom_out ;
+wire [0:19] cby_1__1__131_chany_top_out ;
+wire [0:0] cby_1__1__131_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__13_ccff_tail ;
+wire [0:19] cby_1__1__13_chany_bottom_out ;
+wire [0:19] cby_1__1__13_chany_top_out ;
+wire [0:0] cby_1__1__13_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__14_ccff_tail ;
+wire [0:19] cby_1__1__14_chany_bottom_out ;
+wire [0:19] cby_1__1__14_chany_top_out ;
+wire [0:0] cby_1__1__14_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__15_ccff_tail ;
+wire [0:19] cby_1__1__15_chany_bottom_out ;
+wire [0:19] cby_1__1__15_chany_top_out ;
+wire [0:0] cby_1__1__15_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__16_ccff_tail ;
+wire [0:19] cby_1__1__16_chany_bottom_out ;
+wire [0:19] cby_1__1__16_chany_top_out ;
+wire [0:0] cby_1__1__16_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__17_ccff_tail ;
+wire [0:19] cby_1__1__17_chany_bottom_out ;
+wire [0:19] cby_1__1__17_chany_top_out ;
+wire [0:0] cby_1__1__17_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__18_ccff_tail ;
+wire [0:19] cby_1__1__18_chany_bottom_out ;
+wire [0:19] cby_1__1__18_chany_top_out ;
+wire [0:0] cby_1__1__18_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__19_ccff_tail ;
+wire [0:19] cby_1__1__19_chany_bottom_out ;
+wire [0:19] cby_1__1__19_chany_top_out ;
+wire [0:0] cby_1__1__19_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__1_ccff_tail ;
+wire [0:19] cby_1__1__1_chany_bottom_out ;
+wire [0:19] cby_1__1__1_chany_top_out ;
+wire [0:0] cby_1__1__1_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__20_ccff_tail ;
+wire [0:19] cby_1__1__20_chany_bottom_out ;
+wire [0:19] cby_1__1__20_chany_top_out ;
+wire [0:0] cby_1__1__20_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__21_ccff_tail ;
+wire [0:19] cby_1__1__21_chany_bottom_out ;
+wire [0:19] cby_1__1__21_chany_top_out ;
+wire [0:0] cby_1__1__21_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__22_ccff_tail ;
+wire [0:19] cby_1__1__22_chany_bottom_out ;
+wire [0:19] cby_1__1__22_chany_top_out ;
+wire [0:0] cby_1__1__22_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__23_ccff_tail ;
+wire [0:19] cby_1__1__23_chany_bottom_out ;
+wire [0:19] cby_1__1__23_chany_top_out ;
+wire [0:0] cby_1__1__23_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__24_ccff_tail ;
+wire [0:19] cby_1__1__24_chany_bottom_out ;
+wire [0:19] cby_1__1__24_chany_top_out ;
+wire [0:0] cby_1__1__24_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__25_ccff_tail ;
+wire [0:19] cby_1__1__25_chany_bottom_out ;
+wire [0:19] cby_1__1__25_chany_top_out ;
+wire [0:0] cby_1__1__25_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__26_ccff_tail ;
+wire [0:19] cby_1__1__26_chany_bottom_out ;
+wire [0:19] cby_1__1__26_chany_top_out ;
+wire [0:0] cby_1__1__26_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__27_ccff_tail ;
+wire [0:19] cby_1__1__27_chany_bottom_out ;
+wire [0:19] cby_1__1__27_chany_top_out ;
+wire [0:0] cby_1__1__27_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__28_ccff_tail ;
+wire [0:19] cby_1__1__28_chany_bottom_out ;
+wire [0:19] cby_1__1__28_chany_top_out ;
+wire [0:0] cby_1__1__28_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__29_ccff_tail ;
+wire [0:19] cby_1__1__29_chany_bottom_out ;
+wire [0:19] cby_1__1__29_chany_top_out ;
+wire [0:0] cby_1__1__29_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__2_ccff_tail ;
+wire [0:19] cby_1__1__2_chany_bottom_out ;
+wire [0:19] cby_1__1__2_chany_top_out ;
+wire [0:0] cby_1__1__2_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__30_ccff_tail ;
+wire [0:19] cby_1__1__30_chany_bottom_out ;
+wire [0:19] cby_1__1__30_chany_top_out ;
+wire [0:0] cby_1__1__30_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__31_ccff_tail ;
+wire [0:19] cby_1__1__31_chany_bottom_out ;
+wire [0:19] cby_1__1__31_chany_top_out ;
+wire [0:0] cby_1__1__31_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__32_ccff_tail ;
+wire [0:19] cby_1__1__32_chany_bottom_out ;
+wire [0:19] cby_1__1__32_chany_top_out ;
+wire [0:0] cby_1__1__32_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__33_ccff_tail ;
+wire [0:19] cby_1__1__33_chany_bottom_out ;
+wire [0:19] cby_1__1__33_chany_top_out ;
+wire [0:0] cby_1__1__33_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__34_ccff_tail ;
+wire [0:19] cby_1__1__34_chany_bottom_out ;
+wire [0:19] cby_1__1__34_chany_top_out ;
+wire [0:0] cby_1__1__34_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__35_ccff_tail ;
+wire [0:19] cby_1__1__35_chany_bottom_out ;
+wire [0:19] cby_1__1__35_chany_top_out ;
+wire [0:0] cby_1__1__35_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__36_ccff_tail ;
+wire [0:19] cby_1__1__36_chany_bottom_out ;
+wire [0:19] cby_1__1__36_chany_top_out ;
+wire [0:0] cby_1__1__36_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__37_ccff_tail ;
+wire [0:19] cby_1__1__37_chany_bottom_out ;
+wire [0:19] cby_1__1__37_chany_top_out ;
+wire [0:0] cby_1__1__37_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__38_ccff_tail ;
+wire [0:19] cby_1__1__38_chany_bottom_out ;
+wire [0:19] cby_1__1__38_chany_top_out ;
+wire [0:0] cby_1__1__38_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__39_ccff_tail ;
+wire [0:19] cby_1__1__39_chany_bottom_out ;
+wire [0:19] cby_1__1__39_chany_top_out ;
+wire [0:0] cby_1__1__39_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__3_ccff_tail ;
+wire [0:19] cby_1__1__3_chany_bottom_out ;
+wire [0:19] cby_1__1__3_chany_top_out ;
+wire [0:0] cby_1__1__3_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__40_ccff_tail ;
+wire [0:19] cby_1__1__40_chany_bottom_out ;
+wire [0:19] cby_1__1__40_chany_top_out ;
+wire [0:0] cby_1__1__40_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__41_ccff_tail ;
+wire [0:19] cby_1__1__41_chany_bottom_out ;
+wire [0:19] cby_1__1__41_chany_top_out ;
+wire [0:0] cby_1__1__41_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__42_ccff_tail ;
+wire [0:19] cby_1__1__42_chany_bottom_out ;
+wire [0:19] cby_1__1__42_chany_top_out ;
+wire [0:0] cby_1__1__42_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__43_ccff_tail ;
+wire [0:19] cby_1__1__43_chany_bottom_out ;
+wire [0:19] cby_1__1__43_chany_top_out ;
+wire [0:0] cby_1__1__43_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__44_ccff_tail ;
+wire [0:19] cby_1__1__44_chany_bottom_out ;
+wire [0:19] cby_1__1__44_chany_top_out ;
+wire [0:0] cby_1__1__44_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__45_ccff_tail ;
+wire [0:19] cby_1__1__45_chany_bottom_out ;
+wire [0:19] cby_1__1__45_chany_top_out ;
+wire [0:0] cby_1__1__45_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__46_ccff_tail ;
+wire [0:19] cby_1__1__46_chany_bottom_out ;
+wire [0:19] cby_1__1__46_chany_top_out ;
+wire [0:0] cby_1__1__46_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__47_ccff_tail ;
+wire [0:19] cby_1__1__47_chany_bottom_out ;
+wire [0:19] cby_1__1__47_chany_top_out ;
+wire [0:0] cby_1__1__47_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__48_ccff_tail ;
+wire [0:19] cby_1__1__48_chany_bottom_out ;
+wire [0:19] cby_1__1__48_chany_top_out ;
+wire [0:0] cby_1__1__48_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__49_ccff_tail ;
+wire [0:19] cby_1__1__49_chany_bottom_out ;
+wire [0:19] cby_1__1__49_chany_top_out ;
+wire [0:0] cby_1__1__49_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__4_ccff_tail ;
+wire [0:19] cby_1__1__4_chany_bottom_out ;
+wire [0:19] cby_1__1__4_chany_top_out ;
+wire [0:0] cby_1__1__4_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__50_ccff_tail ;
+wire [0:19] cby_1__1__50_chany_bottom_out ;
+wire [0:19] cby_1__1__50_chany_top_out ;
+wire [0:0] cby_1__1__50_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__51_ccff_tail ;
+wire [0:19] cby_1__1__51_chany_bottom_out ;
+wire [0:19] cby_1__1__51_chany_top_out ;
+wire [0:0] cby_1__1__51_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__52_ccff_tail ;
+wire [0:19] cby_1__1__52_chany_bottom_out ;
+wire [0:19] cby_1__1__52_chany_top_out ;
+wire [0:0] cby_1__1__52_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__53_ccff_tail ;
+wire [0:19] cby_1__1__53_chany_bottom_out ;
+wire [0:19] cby_1__1__53_chany_top_out ;
+wire [0:0] cby_1__1__53_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__54_ccff_tail ;
+wire [0:19] cby_1__1__54_chany_bottom_out ;
+wire [0:19] cby_1__1__54_chany_top_out ;
+wire [0:0] cby_1__1__54_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__55_ccff_tail ;
+wire [0:19] cby_1__1__55_chany_bottom_out ;
+wire [0:19] cby_1__1__55_chany_top_out ;
+wire [0:0] cby_1__1__55_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__56_ccff_tail ;
+wire [0:19] cby_1__1__56_chany_bottom_out ;
+wire [0:19] cby_1__1__56_chany_top_out ;
+wire [0:0] cby_1__1__56_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__57_ccff_tail ;
+wire [0:19] cby_1__1__57_chany_bottom_out ;
+wire [0:19] cby_1__1__57_chany_top_out ;
+wire [0:0] cby_1__1__57_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__58_ccff_tail ;
+wire [0:19] cby_1__1__58_chany_bottom_out ;
+wire [0:19] cby_1__1__58_chany_top_out ;
+wire [0:0] cby_1__1__58_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__59_ccff_tail ;
+wire [0:19] cby_1__1__59_chany_bottom_out ;
+wire [0:19] cby_1__1__59_chany_top_out ;
+wire [0:0] cby_1__1__59_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__5_ccff_tail ;
+wire [0:19] cby_1__1__5_chany_bottom_out ;
+wire [0:19] cby_1__1__5_chany_top_out ;
+wire [0:0] cby_1__1__5_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__60_ccff_tail ;
+wire [0:19] cby_1__1__60_chany_bottom_out ;
+wire [0:19] cby_1__1__60_chany_top_out ;
+wire [0:0] cby_1__1__60_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__61_ccff_tail ;
+wire [0:19] cby_1__1__61_chany_bottom_out ;
+wire [0:19] cby_1__1__61_chany_top_out ;
+wire [0:0] cby_1__1__61_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__62_ccff_tail ;
+wire [0:19] cby_1__1__62_chany_bottom_out ;
+wire [0:19] cby_1__1__62_chany_top_out ;
+wire [0:0] cby_1__1__62_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__63_ccff_tail ;
+wire [0:19] cby_1__1__63_chany_bottom_out ;
+wire [0:19] cby_1__1__63_chany_top_out ;
+wire [0:0] cby_1__1__63_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__64_ccff_tail ;
+wire [0:19] cby_1__1__64_chany_bottom_out ;
+wire [0:19] cby_1__1__64_chany_top_out ;
+wire [0:0] cby_1__1__64_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__65_ccff_tail ;
+wire [0:19] cby_1__1__65_chany_bottom_out ;
+wire [0:19] cby_1__1__65_chany_top_out ;
+wire [0:0] cby_1__1__65_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__66_ccff_tail ;
+wire [0:19] cby_1__1__66_chany_bottom_out ;
+wire [0:19] cby_1__1__66_chany_top_out ;
+wire [0:0] cby_1__1__66_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__67_ccff_tail ;
+wire [0:19] cby_1__1__67_chany_bottom_out ;
+wire [0:19] cby_1__1__67_chany_top_out ;
+wire [0:0] cby_1__1__67_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__68_ccff_tail ;
+wire [0:19] cby_1__1__68_chany_bottom_out ;
+wire [0:19] cby_1__1__68_chany_top_out ;
+wire [0:0] cby_1__1__68_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__69_ccff_tail ;
+wire [0:19] cby_1__1__69_chany_bottom_out ;
+wire [0:19] cby_1__1__69_chany_top_out ;
+wire [0:0] cby_1__1__69_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__6_ccff_tail ;
+wire [0:19] cby_1__1__6_chany_bottom_out ;
+wire [0:19] cby_1__1__6_chany_top_out ;
+wire [0:0] cby_1__1__6_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__70_ccff_tail ;
+wire [0:19] cby_1__1__70_chany_bottom_out ;
+wire [0:19] cby_1__1__70_chany_top_out ;
+wire [0:0] cby_1__1__70_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__71_ccff_tail ;
+wire [0:19] cby_1__1__71_chany_bottom_out ;
+wire [0:19] cby_1__1__71_chany_top_out ;
+wire [0:0] cby_1__1__71_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__72_ccff_tail ;
+wire [0:19] cby_1__1__72_chany_bottom_out ;
+wire [0:19] cby_1__1__72_chany_top_out ;
+wire [0:0] cby_1__1__72_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__73_ccff_tail ;
+wire [0:19] cby_1__1__73_chany_bottom_out ;
+wire [0:19] cby_1__1__73_chany_top_out ;
+wire [0:0] cby_1__1__73_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__74_ccff_tail ;
+wire [0:19] cby_1__1__74_chany_bottom_out ;
+wire [0:19] cby_1__1__74_chany_top_out ;
+wire [0:0] cby_1__1__74_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__75_ccff_tail ;
+wire [0:19] cby_1__1__75_chany_bottom_out ;
+wire [0:19] cby_1__1__75_chany_top_out ;
+wire [0:0] cby_1__1__75_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__76_ccff_tail ;
+wire [0:19] cby_1__1__76_chany_bottom_out ;
+wire [0:19] cby_1__1__76_chany_top_out ;
+wire [0:0] cby_1__1__76_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__77_ccff_tail ;
+wire [0:19] cby_1__1__77_chany_bottom_out ;
+wire [0:19] cby_1__1__77_chany_top_out ;
+wire [0:0] cby_1__1__77_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__78_ccff_tail ;
+wire [0:19] cby_1__1__78_chany_bottom_out ;
+wire [0:19] cby_1__1__78_chany_top_out ;
+wire [0:0] cby_1__1__78_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__79_ccff_tail ;
+wire [0:19] cby_1__1__79_chany_bottom_out ;
+wire [0:19] cby_1__1__79_chany_top_out ;
+wire [0:0] cby_1__1__79_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__7_ccff_tail ;
+wire [0:19] cby_1__1__7_chany_bottom_out ;
+wire [0:19] cby_1__1__7_chany_top_out ;
+wire [0:0] cby_1__1__7_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__80_ccff_tail ;
+wire [0:19] cby_1__1__80_chany_bottom_out ;
+wire [0:19] cby_1__1__80_chany_top_out ;
+wire [0:0] cby_1__1__80_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__81_ccff_tail ;
+wire [0:19] cby_1__1__81_chany_bottom_out ;
+wire [0:19] cby_1__1__81_chany_top_out ;
+wire [0:0] cby_1__1__81_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__82_ccff_tail ;
+wire [0:19] cby_1__1__82_chany_bottom_out ;
+wire [0:19] cby_1__1__82_chany_top_out ;
+wire [0:0] cby_1__1__82_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__83_ccff_tail ;
+wire [0:19] cby_1__1__83_chany_bottom_out ;
+wire [0:19] cby_1__1__83_chany_top_out ;
+wire [0:0] cby_1__1__83_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__84_ccff_tail ;
+wire [0:19] cby_1__1__84_chany_bottom_out ;
+wire [0:19] cby_1__1__84_chany_top_out ;
+wire [0:0] cby_1__1__84_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__85_ccff_tail ;
+wire [0:19] cby_1__1__85_chany_bottom_out ;
+wire [0:19] cby_1__1__85_chany_top_out ;
+wire [0:0] cby_1__1__85_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__86_ccff_tail ;
+wire [0:19] cby_1__1__86_chany_bottom_out ;
+wire [0:19] cby_1__1__86_chany_top_out ;
+wire [0:0] cby_1__1__86_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__87_ccff_tail ;
+wire [0:19] cby_1__1__87_chany_bottom_out ;
+wire [0:19] cby_1__1__87_chany_top_out ;
+wire [0:0] cby_1__1__87_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__88_ccff_tail ;
+wire [0:19] cby_1__1__88_chany_bottom_out ;
+wire [0:19] cby_1__1__88_chany_top_out ;
+wire [0:0] cby_1__1__88_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__89_ccff_tail ;
+wire [0:19] cby_1__1__89_chany_bottom_out ;
+wire [0:19] cby_1__1__89_chany_top_out ;
+wire [0:0] cby_1__1__89_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__8_ccff_tail ;
+wire [0:19] cby_1__1__8_chany_bottom_out ;
+wire [0:19] cby_1__1__8_chany_top_out ;
+wire [0:0] cby_1__1__8_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__90_ccff_tail ;
+wire [0:19] cby_1__1__90_chany_bottom_out ;
+wire [0:19] cby_1__1__90_chany_top_out ;
+wire [0:0] cby_1__1__90_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__91_ccff_tail ;
+wire [0:19] cby_1__1__91_chany_bottom_out ;
+wire [0:19] cby_1__1__91_chany_top_out ;
+wire [0:0] cby_1__1__91_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__92_ccff_tail ;
+wire [0:19] cby_1__1__92_chany_bottom_out ;
+wire [0:19] cby_1__1__92_chany_top_out ;
+wire [0:0] cby_1__1__92_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__93_ccff_tail ;
+wire [0:19] cby_1__1__93_chany_bottom_out ;
+wire [0:19] cby_1__1__93_chany_top_out ;
+wire [0:0] cby_1__1__93_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__94_ccff_tail ;
+wire [0:19] cby_1__1__94_chany_bottom_out ;
+wire [0:19] cby_1__1__94_chany_top_out ;
+wire [0:0] cby_1__1__94_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__95_ccff_tail ;
+wire [0:19] cby_1__1__95_chany_bottom_out ;
+wire [0:19] cby_1__1__95_chany_top_out ;
+wire [0:0] cby_1__1__95_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__96_ccff_tail ;
+wire [0:19] cby_1__1__96_chany_bottom_out ;
+wire [0:19] cby_1__1__96_chany_top_out ;
+wire [0:0] cby_1__1__96_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__97_ccff_tail ;
+wire [0:19] cby_1__1__97_chany_bottom_out ;
+wire [0:19] cby_1__1__97_chany_top_out ;
+wire [0:0] cby_1__1__97_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__98_ccff_tail ;
+wire [0:19] cby_1__1__98_chany_bottom_out ;
+wire [0:19] cby_1__1__98_chany_top_out ;
+wire [0:0] cby_1__1__98_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__99_ccff_tail ;
+wire [0:19] cby_1__1__99_chany_bottom_out ;
+wire [0:19] cby_1__1__99_chany_top_out ;
+wire [0:0] cby_1__1__99_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__9_ccff_tail ;
+wire [0:19] cby_1__1__9_chany_bottom_out ;
+wire [0:19] cby_1__1__9_chany_top_out ;
+wire [0:0] cby_1__1__9_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_31_ ;
+wire [0:0] direct_interc_0_out ;
+wire [0:0] direct_interc_100_out ;
+wire [0:0] direct_interc_101_out ;
+wire [0:0] direct_interc_102_out ;
+wire [0:0] direct_interc_103_out ;
+wire [0:0] direct_interc_104_out ;
+wire [0:0] direct_interc_105_out ;
+wire [0:0] direct_interc_106_out ;
+wire [0:0] direct_interc_107_out ;
+wire [0:0] direct_interc_108_out ;
+wire [0:0] direct_interc_109_out ;
+wire [0:0] direct_interc_10_out ;
+wire [0:0] direct_interc_110_out ;
+wire [0:0] direct_interc_111_out ;
+wire [0:0] direct_interc_112_out ;
+wire [0:0] direct_interc_113_out ;
+wire [0:0] direct_interc_114_out ;
+wire [0:0] direct_interc_115_out ;
+wire [0:0] direct_interc_116_out ;
+wire [0:0] direct_interc_117_out ;
+wire [0:0] direct_interc_118_out ;
+wire [0:0] direct_interc_119_out ;
+wire [0:0] direct_interc_11_out ;
+wire [0:0] direct_interc_120_out ;
+wire [0:0] direct_interc_121_out ;
+wire [0:0] direct_interc_122_out ;
+wire [0:0] direct_interc_123_out ;
+wire [0:0] direct_interc_124_out ;
+wire [0:0] direct_interc_125_out ;
+wire [0:0] direct_interc_126_out ;
+wire [0:0] direct_interc_127_out ;
+wire [0:0] direct_interc_128_out ;
+wire [0:0] direct_interc_129_out ;
+wire [0:0] direct_interc_12_out ;
+wire [0:0] direct_interc_130_out ;
+wire [0:0] direct_interc_131_out ;
+wire [0:0] direct_interc_132_out ;
+wire [0:0] direct_interc_133_out ;
+wire [0:0] direct_interc_134_out ;
+wire [0:0] direct_interc_135_out ;
+wire [0:0] direct_interc_136_out ;
+wire [0:0] direct_interc_137_out ;
+wire [0:0] direct_interc_138_out ;
+wire [0:0] direct_interc_139_out ;
+wire [0:0] direct_interc_13_out ;
+wire [0:0] direct_interc_140_out ;
+wire [0:0] direct_interc_141_out ;
+wire [0:0] direct_interc_142_out ;
+wire [0:0] direct_interc_143_out ;
+wire [0:0] direct_interc_144_out ;
+wire [0:0] direct_interc_145_out ;
+wire [0:0] direct_interc_146_out ;
+wire [0:0] direct_interc_147_out ;
+wire [0:0] direct_interc_148_out ;
+wire [0:0] direct_interc_149_out ;
+wire [0:0] direct_interc_14_out ;
+wire [0:0] direct_interc_150_out ;
+wire [0:0] direct_interc_151_out ;
+wire [0:0] direct_interc_152_out ;
+wire [0:0] direct_interc_153_out ;
+wire [0:0] direct_interc_154_out ;
+wire [0:0] direct_interc_155_out ;
+wire [0:0] direct_interc_156_out ;
+wire [0:0] direct_interc_157_out ;
+wire [0:0] direct_interc_158_out ;
+wire [0:0] direct_interc_159_out ;
+wire [0:0] direct_interc_15_out ;
+wire [0:0] direct_interc_160_out ;
+wire [0:0] direct_interc_161_out ;
+wire [0:0] direct_interc_162_out ;
+wire [0:0] direct_interc_163_out ;
+wire [0:0] direct_interc_164_out ;
+wire [0:0] direct_interc_165_out ;
+wire [0:0] direct_interc_166_out ;
+wire [0:0] direct_interc_167_out ;
+wire [0:0] direct_interc_168_out ;
+wire [0:0] direct_interc_169_out ;
+wire [0:0] direct_interc_16_out ;
+wire [0:0] direct_interc_170_out ;
+wire [0:0] direct_interc_171_out ;
+wire [0:0] direct_interc_172_out ;
+wire [0:0] direct_interc_173_out ;
+wire [0:0] direct_interc_174_out ;
+wire [0:0] direct_interc_175_out ;
+wire [0:0] direct_interc_176_out ;
+wire [0:0] direct_interc_177_out ;
+wire [0:0] direct_interc_178_out ;
+wire [0:0] direct_interc_179_out ;
+wire [0:0] direct_interc_17_out ;
+wire [0:0] direct_interc_180_out ;
+wire [0:0] direct_interc_181_out ;
+wire [0:0] direct_interc_182_out ;
+wire [0:0] direct_interc_183_out ;
+wire [0:0] direct_interc_184_out ;
+wire [0:0] direct_interc_185_out ;
+wire [0:0] direct_interc_186_out ;
+wire [0:0] direct_interc_187_out ;
+wire [0:0] direct_interc_188_out ;
+wire [0:0] direct_interc_189_out ;
+wire [0:0] direct_interc_18_out ;
+wire [0:0] direct_interc_190_out ;
+wire [0:0] direct_interc_191_out ;
+wire [0:0] direct_interc_192_out ;
+wire [0:0] direct_interc_193_out ;
+wire [0:0] direct_interc_194_out ;
+wire [0:0] direct_interc_195_out ;
+wire [0:0] direct_interc_196_out ;
+wire [0:0] direct_interc_197_out ;
+wire [0:0] direct_interc_198_out ;
+wire [0:0] direct_interc_199_out ;
+wire [0:0] direct_interc_19_out ;
+wire [0:0] direct_interc_1_out ;
+wire [0:0] direct_interc_200_out ;
+wire [0:0] direct_interc_201_out ;
+wire [0:0] direct_interc_202_out ;
+wire [0:0] direct_interc_203_out ;
+wire [0:0] direct_interc_204_out ;
+wire [0:0] direct_interc_205_out ;
+wire [0:0] direct_interc_206_out ;
+wire [0:0] direct_interc_207_out ;
+wire [0:0] direct_interc_208_out ;
+wire [0:0] direct_interc_209_out ;
+wire [0:0] direct_interc_20_out ;
+wire [0:0] direct_interc_210_out ;
+wire [0:0] direct_interc_211_out ;
+wire [0:0] direct_interc_212_out ;
+wire [0:0] direct_interc_213_out ;
+wire [0:0] direct_interc_214_out ;
+wire [0:0] direct_interc_215_out ;
+wire [0:0] direct_interc_216_out ;
+wire [0:0] direct_interc_217_out ;
+wire [0:0] direct_interc_218_out ;
+wire [0:0] direct_interc_219_out ;
+wire [0:0] direct_interc_21_out ;
+wire [0:0] direct_interc_220_out ;
+wire [0:0] direct_interc_221_out ;
+wire [0:0] direct_interc_222_out ;
+wire [0:0] direct_interc_223_out ;
+wire [0:0] direct_interc_224_out ;
+wire [0:0] direct_interc_225_out ;
+wire [0:0] direct_interc_226_out ;
+wire [0:0] direct_interc_227_out ;
+wire [0:0] direct_interc_228_out ;
+wire [0:0] direct_interc_229_out ;
+wire [0:0] direct_interc_22_out ;
+wire [0:0] direct_interc_230_out ;
+wire [0:0] direct_interc_231_out ;
+wire [0:0] direct_interc_232_out ;
+wire [0:0] direct_interc_233_out ;
+wire [0:0] direct_interc_234_out ;
+wire [0:0] direct_interc_235_out ;
+wire [0:0] direct_interc_236_out ;
+wire [0:0] direct_interc_237_out ;
+wire [0:0] direct_interc_238_out ;
+wire [0:0] direct_interc_239_out ;
+wire [0:0] direct_interc_23_out ;
+wire [0:0] direct_interc_240_out ;
+wire [0:0] direct_interc_241_out ;
+wire [0:0] direct_interc_242_out ;
+wire [0:0] direct_interc_243_out ;
+wire [0:0] direct_interc_244_out ;
+wire [0:0] direct_interc_245_out ;
+wire [0:0] direct_interc_246_out ;
+wire [0:0] direct_interc_247_out ;
+wire [0:0] direct_interc_248_out ;
+wire [0:0] direct_interc_249_out ;
+wire [0:0] direct_interc_24_out ;
+wire [0:0] direct_interc_250_out ;
+wire [0:0] direct_interc_251_out ;
+wire [0:0] direct_interc_252_out ;
+wire [0:0] direct_interc_253_out ;
+wire [0:0] direct_interc_254_out ;
+wire [0:0] direct_interc_255_out ;
+wire [0:0] direct_interc_256_out ;
+wire [0:0] direct_interc_257_out ;
+wire [0:0] direct_interc_258_out ;
+wire [0:0] direct_interc_259_out ;
+wire [0:0] direct_interc_25_out ;
+wire [0:0] direct_interc_260_out ;
+wire [0:0] direct_interc_261_out ;
+wire [0:0] direct_interc_262_out ;
+wire [0:0] direct_interc_263_out ;
+wire [0:0] direct_interc_264_out ;
+wire [0:0] direct_interc_265_out ;
+wire [0:0] direct_interc_266_out ;
+wire [0:0] direct_interc_267_out ;
+wire [0:0] direct_interc_268_out ;
+wire [0:0] direct_interc_269_out ;
+wire [0:0] direct_interc_26_out ;
+wire [0:0] direct_interc_270_out ;
+wire [0:0] direct_interc_271_out ;
+wire [0:0] direct_interc_272_out ;
+wire [0:0] direct_interc_273_out ;
+wire [0:0] direct_interc_274_out ;
+wire [0:0] direct_interc_27_out ;
+wire [0:0] direct_interc_28_out ;
+wire [0:0] direct_interc_29_out ;
+wire [0:0] direct_interc_2_out ;
+wire [0:0] direct_interc_30_out ;
+wire [0:0] direct_interc_31_out ;
+wire [0:0] direct_interc_32_out ;
+wire [0:0] direct_interc_33_out ;
+wire [0:0] direct_interc_34_out ;
+wire [0:0] direct_interc_35_out ;
+wire [0:0] direct_interc_36_out ;
+wire [0:0] direct_interc_37_out ;
+wire [0:0] direct_interc_38_out ;
+wire [0:0] direct_interc_39_out ;
+wire [0:0] direct_interc_3_out ;
+wire [0:0] direct_interc_40_out ;
+wire [0:0] direct_interc_41_out ;
+wire [0:0] direct_interc_42_out ;
+wire [0:0] direct_interc_43_out ;
+wire [0:0] direct_interc_44_out ;
+wire [0:0] direct_interc_45_out ;
+wire [0:0] direct_interc_46_out ;
+wire [0:0] direct_interc_47_out ;
+wire [0:0] direct_interc_48_out ;
+wire [0:0] direct_interc_49_out ;
+wire [0:0] direct_interc_4_out ;
+wire [0:0] direct_interc_50_out ;
+wire [0:0] direct_interc_51_out ;
+wire [0:0] direct_interc_52_out ;
+wire [0:0] direct_interc_53_out ;
+wire [0:0] direct_interc_54_out ;
+wire [0:0] direct_interc_55_out ;
+wire [0:0] direct_interc_56_out ;
+wire [0:0] direct_interc_57_out ;
+wire [0:0] direct_interc_58_out ;
+wire [0:0] direct_interc_59_out ;
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_60_out ;
+wire [0:0] direct_interc_61_out ;
+wire [0:0] direct_interc_62_out ;
+wire [0:0] direct_interc_63_out ;
+wire [0:0] direct_interc_64_out ;
+wire [0:0] direct_interc_65_out ;
+wire [0:0] direct_interc_66_out ;
+wire [0:0] direct_interc_67_out ;
+wire [0:0] direct_interc_68_out ;
+wire [0:0] direct_interc_69_out ;
+wire [0:0] direct_interc_6_out ;
+wire [0:0] direct_interc_70_out ;
+wire [0:0] direct_interc_71_out ;
+wire [0:0] direct_interc_72_out ;
+wire [0:0] direct_interc_73_out ;
+wire [0:0] direct_interc_74_out ;
+wire [0:0] direct_interc_75_out ;
+wire [0:0] direct_interc_76_out ;
+wire [0:0] direct_interc_77_out ;
+wire [0:0] direct_interc_78_out ;
+wire [0:0] direct_interc_79_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] direct_interc_80_out ;
+wire [0:0] direct_interc_81_out ;
+wire [0:0] direct_interc_82_out ;
+wire [0:0] direct_interc_83_out ;
+wire [0:0] direct_interc_84_out ;
+wire [0:0] direct_interc_85_out ;
+wire [0:0] direct_interc_86_out ;
+wire [0:0] direct_interc_87_out ;
+wire [0:0] direct_interc_88_out ;
+wire [0:0] direct_interc_89_out ;
+wire [0:0] direct_interc_8_out ;
+wire [0:0] direct_interc_90_out ;
+wire [0:0] direct_interc_91_out ;
+wire [0:0] direct_interc_92_out ;
+wire [0:0] direct_interc_93_out ;
+wire [0:0] direct_interc_94_out ;
+wire [0:0] direct_interc_95_out ;
+wire [0:0] direct_interc_96_out ;
+wire [0:0] direct_interc_97_out ;
+wire [0:0] direct_interc_98_out ;
+wire [0:0] direct_interc_99_out ;
+wire [0:0] direct_interc_9_out ;
+wire [0:0] grid_clb_0_ccff_tail ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_100_ccff_tail ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_101_ccff_tail ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_102_ccff_tail ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_103_ccff_tail ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_104_ccff_tail ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_105_ccff_tail ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_106_ccff_tail ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_107_ccff_tail ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_108_ccff_tail ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_109_ccff_tail ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_10_ccff_tail ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_110_ccff_tail ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_111_ccff_tail ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_112_ccff_tail ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_113_ccff_tail ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_114_ccff_tail ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_115_ccff_tail ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_116_ccff_tail ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_117_ccff_tail ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_118_ccff_tail ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_119_ccff_tail ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_11_ccff_tail ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_120_ccff_tail ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_121_ccff_tail ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_122_ccff_tail ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_123_ccff_tail ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_124_ccff_tail ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_125_ccff_tail ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_126_ccff_tail ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_127_ccff_tail ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_128_ccff_tail ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_129_ccff_tail ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_51_ ;
+wire [0:0] grid_clb_12_ccff_tail ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_130_ccff_tail ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_131_ccff_tail ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_132_ccff_tail ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_133_ccff_tail ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_134_ccff_tail ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_135_ccff_tail ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_136_ccff_tail ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_137_ccff_tail ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_138_ccff_tail ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_139_ccff_tail ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_13_ccff_tail ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_140_ccff_tail ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_141_ccff_tail ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_142_ccff_tail ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_143_ccff_tail ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_14_ccff_tail ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_15_ccff_tail ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_16_ccff_tail ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_17_ccff_tail ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_18_ccff_tail ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_19_ccff_tail ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_33_ ;
+wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_1_ccff_tail ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_20_ccff_tail ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_21_ccff_tail ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_22_ccff_tail ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_23_ccff_tail ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_24_ccff_tail ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_25_ccff_tail ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_26_ccff_tail ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_27_ccff_tail ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_28_ccff_tail ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_29_ccff_tail ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_2_ccff_tail ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_30_ccff_tail ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_31_ccff_tail ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_32_ccff_tail ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_33_ccff_tail ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_34_ccff_tail ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_35_ccff_tail ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_36_ccff_tail ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_37_ccff_tail ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_38_ccff_tail ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_39_ccff_tail ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_3_ccff_tail ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_40_ccff_tail ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_41_ccff_tail ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_42_ccff_tail ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_43_ccff_tail ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_44_ccff_tail ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_45_ccff_tail ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_46_ccff_tail ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_47_ccff_tail ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_48_ccff_tail ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_49_ccff_tail ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_4_ccff_tail ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_50_ccff_tail ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_51_ccff_tail ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_52_ccff_tail ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_53_ccff_tail ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_54_ccff_tail ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_55_ccff_tail ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_56_ccff_tail ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_57_ccff_tail ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_58_ccff_tail ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_59_ccff_tail ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_5_ccff_tail ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_60_ccff_tail ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_61_ccff_tail ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_62_ccff_tail ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_63_ccff_tail ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_64_ccff_tail ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_65_ccff_tail ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_66_ccff_tail ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_67_ccff_tail ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_68_ccff_tail ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_69_ccff_tail ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_6_ccff_tail ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_70_ccff_tail ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_71_ccff_tail ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_72_ccff_tail ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_73_ccff_tail ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_74_ccff_tail ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_75_ccff_tail ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_76_ccff_tail ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_77_ccff_tail ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_78_ccff_tail ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_79_ccff_tail ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_7_ccff_tail ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_80_ccff_tail ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_81_ccff_tail ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_82_ccff_tail ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_83_ccff_tail ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_84_ccff_tail ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_85_ccff_tail ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_86_ccff_tail ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_87_ccff_tail ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_88_ccff_tail ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_89_ccff_tail ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_8_ccff_tail ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_90_ccff_tail ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_91_ccff_tail ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_92_ccff_tail ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_93_ccff_tail ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_94_ccff_tail ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_95_ccff_tail ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_96_ccff_tail ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_97_ccff_tail ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_98_ccff_tail ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_99_ccff_tail ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_50_ ;
+wire [0:0] grid_clb_9_ccff_tail ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_34_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_34_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_35_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_35_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_io_bottom_0_ccff_tail ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_10_ccff_tail ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_11_ccff_tail ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_1_ccff_tail ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_2_ccff_tail ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_3_ccff_tail ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_4_ccff_tail ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_5_ccff_tail ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_6_ccff_tail ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_7_ccff_tail ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_8_ccff_tail ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_9_ccff_tail ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_left_0_ccff_tail ;
+wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_10_ccff_tail ;
+wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_11_ccff_tail ;
+wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_1_ccff_tail ;
+wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_2_ccff_tail ;
+wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_3_ccff_tail ;
+wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_4_ccff_tail ;
+wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_5_ccff_tail ;
+wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_6_ccff_tail ;
+wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_7_ccff_tail ;
+wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_8_ccff_tail ;
+wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_9_ccff_tail ;
+wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_0_ccff_tail ;
+wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_10_ccff_tail ;
+wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_11_ccff_tail ;
+wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_1_ccff_tail ;
+wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_2_ccff_tail ;
+wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_3_ccff_tail ;
+wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_4_ccff_tail ;
+wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_5_ccff_tail ;
+wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_6_ccff_tail ;
+wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_7_ccff_tail ;
+wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_8_ccff_tail ;
+wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_9_ccff_tail ;
+wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_0_ccff_tail ;
+wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_10_ccff_tail ;
+wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_11_ccff_tail ;
+wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_1_ccff_tail ;
+wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_2_ccff_tail ;
+wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_3_ccff_tail ;
+wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_4_ccff_tail ;
+wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_5_ccff_tail ;
+wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_6_ccff_tail ;
+wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_7_ccff_tail ;
+wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_8_ccff_tail ;
+wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_9_ccff_tail ;
+wire [0:19] sb_0__0__0_chanx_right_out ;
+wire [0:19] sb_0__0__0_chany_top_out ;
+wire [0:0] sb_0__12__0_ccff_tail ;
+wire [0:19] sb_0__12__0_chanx_right_out ;
+wire [0:19] sb_0__12__0_chany_bottom_out ;
+wire [0:0] sb_0__1__0_ccff_tail ;
+wire [0:19] sb_0__1__0_chanx_right_out ;
+wire [0:19] sb_0__1__0_chany_bottom_out ;
+wire [0:19] sb_0__1__0_chany_top_out ;
+wire [0:0] sb_0__1__10_ccff_tail ;
+wire [0:19] sb_0__1__10_chanx_right_out ;
+wire [0:19] sb_0__1__10_chany_bottom_out ;
+wire [0:19] sb_0__1__10_chany_top_out ;
+wire [0:0] sb_0__1__1_ccff_tail ;
+wire [0:19] sb_0__1__1_chanx_right_out ;
+wire [0:19] sb_0__1__1_chany_bottom_out ;
+wire [0:19] sb_0__1__1_chany_top_out ;
+wire [0:0] sb_0__1__2_ccff_tail ;
+wire [0:19] sb_0__1__2_chanx_right_out ;
+wire [0:19] sb_0__1__2_chany_bottom_out ;
+wire [0:19] sb_0__1__2_chany_top_out ;
+wire [0:0] sb_0__1__3_ccff_tail ;
+wire [0:19] sb_0__1__3_chanx_right_out ;
+wire [0:19] sb_0__1__3_chany_bottom_out ;
+wire [0:19] sb_0__1__3_chany_top_out ;
+wire [0:0] sb_0__1__4_ccff_tail ;
+wire [0:19] sb_0__1__4_chanx_right_out ;
+wire [0:19] sb_0__1__4_chany_bottom_out ;
+wire [0:19] sb_0__1__4_chany_top_out ;
+wire [0:0] sb_0__1__5_ccff_tail ;
+wire [0:19] sb_0__1__5_chanx_right_out ;
+wire [0:19] sb_0__1__5_chany_bottom_out ;
+wire [0:19] sb_0__1__5_chany_top_out ;
+wire [0:0] sb_0__1__6_ccff_tail ;
+wire [0:19] sb_0__1__6_chanx_right_out ;
+wire [0:19] sb_0__1__6_chany_bottom_out ;
+wire [0:19] sb_0__1__6_chany_top_out ;
+wire [0:0] sb_0__1__7_ccff_tail ;
+wire [0:19] sb_0__1__7_chanx_right_out ;
+wire [0:19] sb_0__1__7_chany_bottom_out ;
+wire [0:19] sb_0__1__7_chany_top_out ;
+wire [0:0] sb_0__1__8_ccff_tail ;
+wire [0:19] sb_0__1__8_chanx_right_out ;
+wire [0:19] sb_0__1__8_chany_bottom_out ;
+wire [0:19] sb_0__1__8_chany_top_out ;
+wire [0:0] sb_0__1__9_ccff_tail ;
+wire [0:19] sb_0__1__9_chanx_right_out ;
+wire [0:19] sb_0__1__9_chany_bottom_out ;
+wire [0:19] sb_0__1__9_chany_top_out ;
+wire [0:0] sb_12__0__0_ccff_tail ;
+wire [0:19] sb_12__0__0_chanx_left_out ;
+wire [0:19] sb_12__0__0_chany_top_out ;
+wire [0:0] sb_12__12__0_ccff_tail ;
+wire [0:19] sb_12__12__0_chanx_left_out ;
+wire [0:19] sb_12__12__0_chany_bottom_out ;
+wire [0:0] sb_12__1__0_ccff_tail ;
+wire [0:19] sb_12__1__0_chanx_left_out ;
+wire [0:19] sb_12__1__0_chany_bottom_out ;
+wire [0:19] sb_12__1__0_chany_top_out ;
+wire [0:0] sb_12__1__10_ccff_tail ;
+wire [0:19] sb_12__1__10_chanx_left_out ;
+wire [0:19] sb_12__1__10_chany_bottom_out ;
+wire [0:19] sb_12__1__10_chany_top_out ;
+wire [0:0] sb_12__1__1_ccff_tail ;
+wire [0:19] sb_12__1__1_chanx_left_out ;
+wire [0:19] sb_12__1__1_chany_bottom_out ;
+wire [0:19] sb_12__1__1_chany_top_out ;
+wire [0:0] sb_12__1__2_ccff_tail ;
+wire [0:19] sb_12__1__2_chanx_left_out ;
+wire [0:19] sb_12__1__2_chany_bottom_out ;
+wire [0:19] sb_12__1__2_chany_top_out ;
+wire [0:0] sb_12__1__3_ccff_tail ;
+wire [0:19] sb_12__1__3_chanx_left_out ;
+wire [0:19] sb_12__1__3_chany_bottom_out ;
+wire [0:19] sb_12__1__3_chany_top_out ;
+wire [0:0] sb_12__1__4_ccff_tail ;
+wire [0:19] sb_12__1__4_chanx_left_out ;
+wire [0:19] sb_12__1__4_chany_bottom_out ;
+wire [0:19] sb_12__1__4_chany_top_out ;
+wire [0:0] sb_12__1__5_ccff_tail ;
+wire [0:19] sb_12__1__5_chanx_left_out ;
+wire [0:19] sb_12__1__5_chany_bottom_out ;
+wire [0:19] sb_12__1__5_chany_top_out ;
+wire [0:0] sb_12__1__6_ccff_tail ;
+wire [0:19] sb_12__1__6_chanx_left_out ;
+wire [0:19] sb_12__1__6_chany_bottom_out ;
+wire [0:19] sb_12__1__6_chany_top_out ;
+wire [0:0] sb_12__1__7_ccff_tail ;
+wire [0:19] sb_12__1__7_chanx_left_out ;
+wire [0:19] sb_12__1__7_chany_bottom_out ;
+wire [0:19] sb_12__1__7_chany_top_out ;
+wire [0:0] sb_12__1__8_ccff_tail ;
+wire [0:19] sb_12__1__8_chanx_left_out ;
+wire [0:19] sb_12__1__8_chany_bottom_out ;
+wire [0:19] sb_12__1__8_chany_top_out ;
+wire [0:0] sb_12__1__9_ccff_tail ;
+wire [0:19] sb_12__1__9_chanx_left_out ;
+wire [0:19] sb_12__1__9_chany_bottom_out ;
+wire [0:19] sb_12__1__9_chany_top_out ;
+wire [0:0] sb_1__0__0_ccff_tail ;
+wire [0:19] sb_1__0__0_chanx_left_out ;
+wire [0:19] sb_1__0__0_chanx_right_out ;
+wire [0:19] sb_1__0__0_chany_top_out ;
+wire [0:0] sb_1__0__10_ccff_tail ;
+wire [0:19] sb_1__0__10_chanx_left_out ;
+wire [0:19] sb_1__0__10_chanx_right_out ;
+wire [0:19] sb_1__0__10_chany_top_out ;
+wire [0:0] sb_1__0__1_ccff_tail ;
+wire [0:19] sb_1__0__1_chanx_left_out ;
+wire [0:19] sb_1__0__1_chanx_right_out ;
+wire [0:19] sb_1__0__1_chany_top_out ;
+wire [0:0] sb_1__0__2_ccff_tail ;
+wire [0:19] sb_1__0__2_chanx_left_out ;
+wire [0:19] sb_1__0__2_chanx_right_out ;
+wire [0:19] sb_1__0__2_chany_top_out ;
+wire [0:0] sb_1__0__3_ccff_tail ;
+wire [0:19] sb_1__0__3_chanx_left_out ;
+wire [0:19] sb_1__0__3_chanx_right_out ;
+wire [0:19] sb_1__0__3_chany_top_out ;
+wire [0:0] sb_1__0__4_ccff_tail ;
+wire [0:19] sb_1__0__4_chanx_left_out ;
+wire [0:19] sb_1__0__4_chanx_right_out ;
+wire [0:19] sb_1__0__4_chany_top_out ;
+wire [0:0] sb_1__0__5_ccff_tail ;
+wire [0:19] sb_1__0__5_chanx_left_out ;
+wire [0:19] sb_1__0__5_chanx_right_out ;
+wire [0:19] sb_1__0__5_chany_top_out ;
+wire [0:0] sb_1__0__6_ccff_tail ;
+wire [0:19] sb_1__0__6_chanx_left_out ;
+wire [0:19] sb_1__0__6_chanx_right_out ;
+wire [0:19] sb_1__0__6_chany_top_out ;
+wire [0:0] sb_1__0__7_ccff_tail ;
+wire [0:19] sb_1__0__7_chanx_left_out ;
+wire [0:19] sb_1__0__7_chanx_right_out ;
+wire [0:19] sb_1__0__7_chany_top_out ;
+wire [0:0] sb_1__0__8_ccff_tail ;
+wire [0:19] sb_1__0__8_chanx_left_out ;
+wire [0:19] sb_1__0__8_chanx_right_out ;
+wire [0:19] sb_1__0__8_chany_top_out ;
+wire [0:0] sb_1__0__9_ccff_tail ;
+wire [0:19] sb_1__0__9_chanx_left_out ;
+wire [0:19] sb_1__0__9_chanx_right_out ;
+wire [0:19] sb_1__0__9_chany_top_out ;
+wire [0:0] sb_1__12__0_ccff_tail ;
+wire [0:19] sb_1__12__0_chanx_left_out ;
+wire [0:19] sb_1__12__0_chanx_right_out ;
+wire [0:19] sb_1__12__0_chany_bottom_out ;
+wire [0:0] sb_1__12__10_ccff_tail ;
+wire [0:19] sb_1__12__10_chanx_left_out ;
+wire [0:19] sb_1__12__10_chanx_right_out ;
+wire [0:19] sb_1__12__10_chany_bottom_out ;
+wire [0:0] sb_1__12__1_ccff_tail ;
+wire [0:19] sb_1__12__1_chanx_left_out ;
+wire [0:19] sb_1__12__1_chanx_right_out ;
+wire [0:19] sb_1__12__1_chany_bottom_out ;
+wire [0:0] sb_1__12__2_ccff_tail ;
+wire [0:19] sb_1__12__2_chanx_left_out ;
+wire [0:19] sb_1__12__2_chanx_right_out ;
+wire [0:19] sb_1__12__2_chany_bottom_out ;
+wire [0:0] sb_1__12__3_ccff_tail ;
+wire [0:19] sb_1__12__3_chanx_left_out ;
+wire [0:19] sb_1__12__3_chanx_right_out ;
+wire [0:19] sb_1__12__3_chany_bottom_out ;
+wire [0:0] sb_1__12__4_ccff_tail ;
+wire [0:19] sb_1__12__4_chanx_left_out ;
+wire [0:19] sb_1__12__4_chanx_right_out ;
+wire [0:19] sb_1__12__4_chany_bottom_out ;
+wire [0:0] sb_1__12__5_ccff_tail ;
+wire [0:19] sb_1__12__5_chanx_left_out ;
+wire [0:19] sb_1__12__5_chanx_right_out ;
+wire [0:19] sb_1__12__5_chany_bottom_out ;
+wire [0:0] sb_1__12__6_ccff_tail ;
+wire [0:19] sb_1__12__6_chanx_left_out ;
+wire [0:19] sb_1__12__6_chanx_right_out ;
+wire [0:19] sb_1__12__6_chany_bottom_out ;
+wire [0:0] sb_1__12__7_ccff_tail ;
+wire [0:19] sb_1__12__7_chanx_left_out ;
+wire [0:19] sb_1__12__7_chanx_right_out ;
+wire [0:19] sb_1__12__7_chany_bottom_out ;
+wire [0:0] sb_1__12__8_ccff_tail ;
+wire [0:19] sb_1__12__8_chanx_left_out ;
+wire [0:19] sb_1__12__8_chanx_right_out ;
+wire [0:19] sb_1__12__8_chany_bottom_out ;
+wire [0:0] sb_1__12__9_ccff_tail ;
+wire [0:19] sb_1__12__9_chanx_left_out ;
+wire [0:19] sb_1__12__9_chanx_right_out ;
+wire [0:19] sb_1__12__9_chany_bottom_out ;
+wire [0:0] sb_1__1__0_ccff_tail ;
+wire [0:19] sb_1__1__0_chanx_left_out ;
+wire [0:19] sb_1__1__0_chanx_right_out ;
+wire [0:19] sb_1__1__0_chany_bottom_out ;
+wire [0:19] sb_1__1__0_chany_top_out ;
+wire [0:0] sb_1__1__100_ccff_tail ;
+wire [0:19] sb_1__1__100_chanx_left_out ;
+wire [0:19] sb_1__1__100_chanx_right_out ;
+wire [0:19] sb_1__1__100_chany_bottom_out ;
+wire [0:19] sb_1__1__100_chany_top_out ;
+wire [0:0] sb_1__1__101_ccff_tail ;
+wire [0:19] sb_1__1__101_chanx_left_out ;
+wire [0:19] sb_1__1__101_chanx_right_out ;
+wire [0:19] sb_1__1__101_chany_bottom_out ;
+wire [0:19] sb_1__1__101_chany_top_out ;
+wire [0:0] sb_1__1__102_ccff_tail ;
+wire [0:19] sb_1__1__102_chanx_left_out ;
+wire [0:19] sb_1__1__102_chanx_right_out ;
+wire [0:19] sb_1__1__102_chany_bottom_out ;
+wire [0:19] sb_1__1__102_chany_top_out ;
+wire [0:0] sb_1__1__103_ccff_tail ;
+wire [0:19] sb_1__1__103_chanx_left_out ;
+wire [0:19] sb_1__1__103_chanx_right_out ;
+wire [0:19] sb_1__1__103_chany_bottom_out ;
+wire [0:19] sb_1__1__103_chany_top_out ;
+wire [0:0] sb_1__1__104_ccff_tail ;
+wire [0:19] sb_1__1__104_chanx_left_out ;
+wire [0:19] sb_1__1__104_chanx_right_out ;
+wire [0:19] sb_1__1__104_chany_bottom_out ;
+wire [0:19] sb_1__1__104_chany_top_out ;
+wire [0:0] sb_1__1__105_ccff_tail ;
+wire [0:19] sb_1__1__105_chanx_left_out ;
+wire [0:19] sb_1__1__105_chanx_right_out ;
+wire [0:19] sb_1__1__105_chany_bottom_out ;
+wire [0:19] sb_1__1__105_chany_top_out ;
+wire [0:0] sb_1__1__106_ccff_tail ;
+wire [0:19] sb_1__1__106_chanx_left_out ;
+wire [0:19] sb_1__1__106_chanx_right_out ;
+wire [0:19] sb_1__1__106_chany_bottom_out ;
+wire [0:19] sb_1__1__106_chany_top_out ;
+wire [0:0] sb_1__1__107_ccff_tail ;
+wire [0:19] sb_1__1__107_chanx_left_out ;
+wire [0:19] sb_1__1__107_chanx_right_out ;
+wire [0:19] sb_1__1__107_chany_bottom_out ;
+wire [0:19] sb_1__1__107_chany_top_out ;
+wire [0:0] sb_1__1__108_ccff_tail ;
+wire [0:19] sb_1__1__108_chanx_left_out ;
+wire [0:19] sb_1__1__108_chanx_right_out ;
+wire [0:19] sb_1__1__108_chany_bottom_out ;
+wire [0:19] sb_1__1__108_chany_top_out ;
+wire [0:0] sb_1__1__109_ccff_tail ;
+wire [0:19] sb_1__1__109_chanx_left_out ;
+wire [0:19] sb_1__1__109_chanx_right_out ;
+wire [0:19] sb_1__1__109_chany_bottom_out ;
+wire [0:19] sb_1__1__109_chany_top_out ;
+wire [0:0] sb_1__1__10_ccff_tail ;
+wire [0:19] sb_1__1__10_chanx_left_out ;
+wire [0:19] sb_1__1__10_chanx_right_out ;
+wire [0:19] sb_1__1__10_chany_bottom_out ;
+wire [0:19] sb_1__1__10_chany_top_out ;
+wire [0:0] sb_1__1__110_ccff_tail ;
+wire [0:19] sb_1__1__110_chanx_left_out ;
+wire [0:19] sb_1__1__110_chanx_right_out ;
+wire [0:19] sb_1__1__110_chany_bottom_out ;
+wire [0:19] sb_1__1__110_chany_top_out ;
+wire [0:0] sb_1__1__111_ccff_tail ;
+wire [0:19] sb_1__1__111_chanx_left_out ;
+wire [0:19] sb_1__1__111_chanx_right_out ;
+wire [0:19] sb_1__1__111_chany_bottom_out ;
+wire [0:19] sb_1__1__111_chany_top_out ;
+wire [0:0] sb_1__1__112_ccff_tail ;
+wire [0:19] sb_1__1__112_chanx_left_out ;
+wire [0:19] sb_1__1__112_chanx_right_out ;
+wire [0:19] sb_1__1__112_chany_bottom_out ;
+wire [0:19] sb_1__1__112_chany_top_out ;
+wire [0:0] sb_1__1__113_ccff_tail ;
+wire [0:19] sb_1__1__113_chanx_left_out ;
+wire [0:19] sb_1__1__113_chanx_right_out ;
+wire [0:19] sb_1__1__113_chany_bottom_out ;
+wire [0:19] sb_1__1__113_chany_top_out ;
+wire [0:0] sb_1__1__114_ccff_tail ;
+wire [0:19] sb_1__1__114_chanx_left_out ;
+wire [0:19] sb_1__1__114_chanx_right_out ;
+wire [0:19] sb_1__1__114_chany_bottom_out ;
+wire [0:19] sb_1__1__114_chany_top_out ;
+wire [0:0] sb_1__1__115_ccff_tail ;
+wire [0:19] sb_1__1__115_chanx_left_out ;
+wire [0:19] sb_1__1__115_chanx_right_out ;
+wire [0:19] sb_1__1__115_chany_bottom_out ;
+wire [0:19] sb_1__1__115_chany_top_out ;
+wire [0:0] sb_1__1__116_ccff_tail ;
+wire [0:19] sb_1__1__116_chanx_left_out ;
+wire [0:19] sb_1__1__116_chanx_right_out ;
+wire [0:19] sb_1__1__116_chany_bottom_out ;
+wire [0:19] sb_1__1__116_chany_top_out ;
+wire [0:0] sb_1__1__117_ccff_tail ;
+wire [0:19] sb_1__1__117_chanx_left_out ;
+wire [0:19] sb_1__1__117_chanx_right_out ;
+wire [0:19] sb_1__1__117_chany_bottom_out ;
+wire [0:19] sb_1__1__117_chany_top_out ;
+wire [0:0] sb_1__1__118_ccff_tail ;
+wire [0:19] sb_1__1__118_chanx_left_out ;
+wire [0:19] sb_1__1__118_chanx_right_out ;
+wire [0:19] sb_1__1__118_chany_bottom_out ;
+wire [0:19] sb_1__1__118_chany_top_out ;
+wire [0:0] sb_1__1__119_ccff_tail ;
+wire [0:19] sb_1__1__119_chanx_left_out ;
+wire [0:19] sb_1__1__119_chanx_right_out ;
+wire [0:19] sb_1__1__119_chany_bottom_out ;
+wire [0:19] sb_1__1__119_chany_top_out ;
+wire [0:0] sb_1__1__11_ccff_tail ;
+wire [0:19] sb_1__1__11_chanx_left_out ;
+wire [0:19] sb_1__1__11_chanx_right_out ;
+wire [0:19] sb_1__1__11_chany_bottom_out ;
+wire [0:19] sb_1__1__11_chany_top_out ;
+wire [0:0] sb_1__1__120_ccff_tail ;
+wire [0:19] sb_1__1__120_chanx_left_out ;
+wire [0:19] sb_1__1__120_chanx_right_out ;
+wire [0:19] sb_1__1__120_chany_bottom_out ;
+wire [0:19] sb_1__1__120_chany_top_out ;
+wire [0:0] sb_1__1__12_ccff_tail ;
+wire [0:19] sb_1__1__12_chanx_left_out ;
+wire [0:19] sb_1__1__12_chanx_right_out ;
+wire [0:19] sb_1__1__12_chany_bottom_out ;
+wire [0:19] sb_1__1__12_chany_top_out ;
+wire [0:0] sb_1__1__13_ccff_tail ;
+wire [0:19] sb_1__1__13_chanx_left_out ;
+wire [0:19] sb_1__1__13_chanx_right_out ;
+wire [0:19] sb_1__1__13_chany_bottom_out ;
+wire [0:19] sb_1__1__13_chany_top_out ;
+wire [0:0] sb_1__1__14_ccff_tail ;
+wire [0:19] sb_1__1__14_chanx_left_out ;
+wire [0:19] sb_1__1__14_chanx_right_out ;
+wire [0:19] sb_1__1__14_chany_bottom_out ;
+wire [0:19] sb_1__1__14_chany_top_out ;
+wire [0:0] sb_1__1__15_ccff_tail ;
+wire [0:19] sb_1__1__15_chanx_left_out ;
+wire [0:19] sb_1__1__15_chanx_right_out ;
+wire [0:19] sb_1__1__15_chany_bottom_out ;
+wire [0:19] sb_1__1__15_chany_top_out ;
+wire [0:0] sb_1__1__16_ccff_tail ;
+wire [0:19] sb_1__1__16_chanx_left_out ;
+wire [0:19] sb_1__1__16_chanx_right_out ;
+wire [0:19] sb_1__1__16_chany_bottom_out ;
+wire [0:19] sb_1__1__16_chany_top_out ;
+wire [0:0] sb_1__1__17_ccff_tail ;
+wire [0:19] sb_1__1__17_chanx_left_out ;
+wire [0:19] sb_1__1__17_chanx_right_out ;
+wire [0:19] sb_1__1__17_chany_bottom_out ;
+wire [0:19] sb_1__1__17_chany_top_out ;
+wire [0:0] sb_1__1__18_ccff_tail ;
+wire [0:19] sb_1__1__18_chanx_left_out ;
+wire [0:19] sb_1__1__18_chanx_right_out ;
+wire [0:19] sb_1__1__18_chany_bottom_out ;
+wire [0:19] sb_1__1__18_chany_top_out ;
+wire [0:0] sb_1__1__19_ccff_tail ;
+wire [0:19] sb_1__1__19_chanx_left_out ;
+wire [0:19] sb_1__1__19_chanx_right_out ;
+wire [0:19] sb_1__1__19_chany_bottom_out ;
+wire [0:19] sb_1__1__19_chany_top_out ;
+wire [0:0] sb_1__1__1_ccff_tail ;
+wire [0:19] sb_1__1__1_chanx_left_out ;
+wire [0:19] sb_1__1__1_chanx_right_out ;
+wire [0:19] sb_1__1__1_chany_bottom_out ;
+wire [0:19] sb_1__1__1_chany_top_out ;
+wire [0:0] sb_1__1__20_ccff_tail ;
+wire [0:19] sb_1__1__20_chanx_left_out ;
+wire [0:19] sb_1__1__20_chanx_right_out ;
+wire [0:19] sb_1__1__20_chany_bottom_out ;
+wire [0:19] sb_1__1__20_chany_top_out ;
+wire [0:0] sb_1__1__21_ccff_tail ;
+wire [0:19] sb_1__1__21_chanx_left_out ;
+wire [0:19] sb_1__1__21_chanx_right_out ;
+wire [0:19] sb_1__1__21_chany_bottom_out ;
+wire [0:19] sb_1__1__21_chany_top_out ;
+wire [0:0] sb_1__1__22_ccff_tail ;
+wire [0:19] sb_1__1__22_chanx_left_out ;
+wire [0:19] sb_1__1__22_chanx_right_out ;
+wire [0:19] sb_1__1__22_chany_bottom_out ;
+wire [0:19] sb_1__1__22_chany_top_out ;
+wire [0:0] sb_1__1__23_ccff_tail ;
+wire [0:19] sb_1__1__23_chanx_left_out ;
+wire [0:19] sb_1__1__23_chanx_right_out ;
+wire [0:19] sb_1__1__23_chany_bottom_out ;
+wire [0:19] sb_1__1__23_chany_top_out ;
+wire [0:0] sb_1__1__24_ccff_tail ;
+wire [0:19] sb_1__1__24_chanx_left_out ;
+wire [0:19] sb_1__1__24_chanx_right_out ;
+wire [0:19] sb_1__1__24_chany_bottom_out ;
+wire [0:19] sb_1__1__24_chany_top_out ;
+wire [0:0] sb_1__1__25_ccff_tail ;
+wire [0:19] sb_1__1__25_chanx_left_out ;
+wire [0:19] sb_1__1__25_chanx_right_out ;
+wire [0:19] sb_1__1__25_chany_bottom_out ;
+wire [0:19] sb_1__1__25_chany_top_out ;
+wire [0:0] sb_1__1__26_ccff_tail ;
+wire [0:19] sb_1__1__26_chanx_left_out ;
+wire [0:19] sb_1__1__26_chanx_right_out ;
+wire [0:19] sb_1__1__26_chany_bottom_out ;
+wire [0:19] sb_1__1__26_chany_top_out ;
+wire [0:0] sb_1__1__27_ccff_tail ;
+wire [0:19] sb_1__1__27_chanx_left_out ;
+wire [0:19] sb_1__1__27_chanx_right_out ;
+wire [0:19] sb_1__1__27_chany_bottom_out ;
+wire [0:19] sb_1__1__27_chany_top_out ;
+wire [0:0] sb_1__1__28_ccff_tail ;
+wire [0:19] sb_1__1__28_chanx_left_out ;
+wire [0:19] sb_1__1__28_chanx_right_out ;
+wire [0:19] sb_1__1__28_chany_bottom_out ;
+wire [0:19] sb_1__1__28_chany_top_out ;
+wire [0:0] sb_1__1__29_ccff_tail ;
+wire [0:19] sb_1__1__29_chanx_left_out ;
+wire [0:19] sb_1__1__29_chanx_right_out ;
+wire [0:19] sb_1__1__29_chany_bottom_out ;
+wire [0:19] sb_1__1__29_chany_top_out ;
+wire [0:0] sb_1__1__2_ccff_tail ;
+wire [0:19] sb_1__1__2_chanx_left_out ;
+wire [0:19] sb_1__1__2_chanx_right_out ;
+wire [0:19] sb_1__1__2_chany_bottom_out ;
+wire [0:19] sb_1__1__2_chany_top_out ;
+wire [0:0] sb_1__1__30_ccff_tail ;
+wire [0:19] sb_1__1__30_chanx_left_out ;
+wire [0:19] sb_1__1__30_chanx_right_out ;
+wire [0:19] sb_1__1__30_chany_bottom_out ;
+wire [0:19] sb_1__1__30_chany_top_out ;
+wire [0:0] sb_1__1__31_ccff_tail ;
+wire [0:19] sb_1__1__31_chanx_left_out ;
+wire [0:19] sb_1__1__31_chanx_right_out ;
+wire [0:19] sb_1__1__31_chany_bottom_out ;
+wire [0:19] sb_1__1__31_chany_top_out ;
+wire [0:0] sb_1__1__32_ccff_tail ;
+wire [0:19] sb_1__1__32_chanx_left_out ;
+wire [0:19] sb_1__1__32_chanx_right_out ;
+wire [0:19] sb_1__1__32_chany_bottom_out ;
+wire [0:19] sb_1__1__32_chany_top_out ;
+wire [0:0] sb_1__1__33_ccff_tail ;
+wire [0:19] sb_1__1__33_chanx_left_out ;
+wire [0:19] sb_1__1__33_chanx_right_out ;
+wire [0:19] sb_1__1__33_chany_bottom_out ;
+wire [0:19] sb_1__1__33_chany_top_out ;
+wire [0:0] sb_1__1__34_ccff_tail ;
+wire [0:19] sb_1__1__34_chanx_left_out ;
+wire [0:19] sb_1__1__34_chanx_right_out ;
+wire [0:19] sb_1__1__34_chany_bottom_out ;
+wire [0:19] sb_1__1__34_chany_top_out ;
+wire [0:0] sb_1__1__35_ccff_tail ;
+wire [0:19] sb_1__1__35_chanx_left_out ;
+wire [0:19] sb_1__1__35_chanx_right_out ;
+wire [0:19] sb_1__1__35_chany_bottom_out ;
+wire [0:19] sb_1__1__35_chany_top_out ;
+wire [0:0] sb_1__1__36_ccff_tail ;
+wire [0:19] sb_1__1__36_chanx_left_out ;
+wire [0:19] sb_1__1__36_chanx_right_out ;
+wire [0:19] sb_1__1__36_chany_bottom_out ;
+wire [0:19] sb_1__1__36_chany_top_out ;
+wire [0:0] sb_1__1__37_ccff_tail ;
+wire [0:19] sb_1__1__37_chanx_left_out ;
+wire [0:19] sb_1__1__37_chanx_right_out ;
+wire [0:19] sb_1__1__37_chany_bottom_out ;
+wire [0:19] sb_1__1__37_chany_top_out ;
+wire [0:0] sb_1__1__38_ccff_tail ;
+wire [0:19] sb_1__1__38_chanx_left_out ;
+wire [0:19] sb_1__1__38_chanx_right_out ;
+wire [0:19] sb_1__1__38_chany_bottom_out ;
+wire [0:19] sb_1__1__38_chany_top_out ;
+wire [0:0] sb_1__1__39_ccff_tail ;
+wire [0:19] sb_1__1__39_chanx_left_out ;
+wire [0:19] sb_1__1__39_chanx_right_out ;
+wire [0:19] sb_1__1__39_chany_bottom_out ;
+wire [0:19] sb_1__1__39_chany_top_out ;
+wire [0:0] sb_1__1__3_ccff_tail ;
+wire [0:19] sb_1__1__3_chanx_left_out ;
+wire [0:19] sb_1__1__3_chanx_right_out ;
+wire [0:19] sb_1__1__3_chany_bottom_out ;
+wire [0:19] sb_1__1__3_chany_top_out ;
+wire [0:0] sb_1__1__40_ccff_tail ;
+wire [0:19] sb_1__1__40_chanx_left_out ;
+wire [0:19] sb_1__1__40_chanx_right_out ;
+wire [0:19] sb_1__1__40_chany_bottom_out ;
+wire [0:19] sb_1__1__40_chany_top_out ;
+wire [0:0] sb_1__1__41_ccff_tail ;
+wire [0:19] sb_1__1__41_chanx_left_out ;
+wire [0:19] sb_1__1__41_chanx_right_out ;
+wire [0:19] sb_1__1__41_chany_bottom_out ;
+wire [0:19] sb_1__1__41_chany_top_out ;
+wire [0:0] sb_1__1__42_ccff_tail ;
+wire [0:19] sb_1__1__42_chanx_left_out ;
+wire [0:19] sb_1__1__42_chanx_right_out ;
+wire [0:19] sb_1__1__42_chany_bottom_out ;
+wire [0:19] sb_1__1__42_chany_top_out ;
+wire [0:0] sb_1__1__43_ccff_tail ;
+wire [0:19] sb_1__1__43_chanx_left_out ;
+wire [0:19] sb_1__1__43_chanx_right_out ;
+wire [0:19] sb_1__1__43_chany_bottom_out ;
+wire [0:19] sb_1__1__43_chany_top_out ;
+wire [0:0] sb_1__1__44_ccff_tail ;
+wire [0:19] sb_1__1__44_chanx_left_out ;
+wire [0:19] sb_1__1__44_chanx_right_out ;
+wire [0:19] sb_1__1__44_chany_bottom_out ;
+wire [0:19] sb_1__1__44_chany_top_out ;
+wire [0:0] sb_1__1__45_ccff_tail ;
+wire [0:19] sb_1__1__45_chanx_left_out ;
+wire [0:19] sb_1__1__45_chanx_right_out ;
+wire [0:19] sb_1__1__45_chany_bottom_out ;
+wire [0:19] sb_1__1__45_chany_top_out ;
+wire [0:0] sb_1__1__46_ccff_tail ;
+wire [0:19] sb_1__1__46_chanx_left_out ;
+wire [0:19] sb_1__1__46_chanx_right_out ;
+wire [0:19] sb_1__1__46_chany_bottom_out ;
+wire [0:19] sb_1__1__46_chany_top_out ;
+wire [0:0] sb_1__1__47_ccff_tail ;
+wire [0:19] sb_1__1__47_chanx_left_out ;
+wire [0:19] sb_1__1__47_chanx_right_out ;
+wire [0:19] sb_1__1__47_chany_bottom_out ;
+wire [0:19] sb_1__1__47_chany_top_out ;
+wire [0:0] sb_1__1__48_ccff_tail ;
+wire [0:19] sb_1__1__48_chanx_left_out ;
+wire [0:19] sb_1__1__48_chanx_right_out ;
+wire [0:19] sb_1__1__48_chany_bottom_out ;
+wire [0:19] sb_1__1__48_chany_top_out ;
+wire [0:0] sb_1__1__49_ccff_tail ;
+wire [0:19] sb_1__1__49_chanx_left_out ;
+wire [0:19] sb_1__1__49_chanx_right_out ;
+wire [0:19] sb_1__1__49_chany_bottom_out ;
+wire [0:19] sb_1__1__49_chany_top_out ;
+wire [0:0] sb_1__1__4_ccff_tail ;
+wire [0:19] sb_1__1__4_chanx_left_out ;
+wire [0:19] sb_1__1__4_chanx_right_out ;
+wire [0:19] sb_1__1__4_chany_bottom_out ;
+wire [0:19] sb_1__1__4_chany_top_out ;
+wire [0:0] sb_1__1__50_ccff_tail ;
+wire [0:19] sb_1__1__50_chanx_left_out ;
+wire [0:19] sb_1__1__50_chanx_right_out ;
+wire [0:19] sb_1__1__50_chany_bottom_out ;
+wire [0:19] sb_1__1__50_chany_top_out ;
+wire [0:0] sb_1__1__51_ccff_tail ;
+wire [0:19] sb_1__1__51_chanx_left_out ;
+wire [0:19] sb_1__1__51_chanx_right_out ;
+wire [0:19] sb_1__1__51_chany_bottom_out ;
+wire [0:19] sb_1__1__51_chany_top_out ;
+wire [0:0] sb_1__1__52_ccff_tail ;
+wire [0:19] sb_1__1__52_chanx_left_out ;
+wire [0:19] sb_1__1__52_chanx_right_out ;
+wire [0:19] sb_1__1__52_chany_bottom_out ;
+wire [0:19] sb_1__1__52_chany_top_out ;
+wire [0:0] sb_1__1__53_ccff_tail ;
+wire [0:19] sb_1__1__53_chanx_left_out ;
+wire [0:19] sb_1__1__53_chanx_right_out ;
+wire [0:19] sb_1__1__53_chany_bottom_out ;
+wire [0:19] sb_1__1__53_chany_top_out ;
+wire [0:0] sb_1__1__54_ccff_tail ;
+wire [0:19] sb_1__1__54_chanx_left_out ;
+wire [0:19] sb_1__1__54_chanx_right_out ;
+wire [0:19] sb_1__1__54_chany_bottom_out ;
+wire [0:19] sb_1__1__54_chany_top_out ;
+wire [0:0] sb_1__1__55_ccff_tail ;
+wire [0:19] sb_1__1__55_chanx_left_out ;
+wire [0:19] sb_1__1__55_chanx_right_out ;
+wire [0:19] sb_1__1__55_chany_bottom_out ;
+wire [0:19] sb_1__1__55_chany_top_out ;
+wire [0:0] sb_1__1__56_ccff_tail ;
+wire [0:19] sb_1__1__56_chanx_left_out ;
+wire [0:19] sb_1__1__56_chanx_right_out ;
+wire [0:19] sb_1__1__56_chany_bottom_out ;
+wire [0:19] sb_1__1__56_chany_top_out ;
+wire [0:0] sb_1__1__57_ccff_tail ;
+wire [0:19] sb_1__1__57_chanx_left_out ;
+wire [0:19] sb_1__1__57_chanx_right_out ;
+wire [0:19] sb_1__1__57_chany_bottom_out ;
+wire [0:19] sb_1__1__57_chany_top_out ;
+wire [0:0] sb_1__1__58_ccff_tail ;
+wire [0:19] sb_1__1__58_chanx_left_out ;
+wire [0:19] sb_1__1__58_chanx_right_out ;
+wire [0:19] sb_1__1__58_chany_bottom_out ;
+wire [0:19] sb_1__1__58_chany_top_out ;
+wire [0:0] sb_1__1__59_ccff_tail ;
+wire [0:19] sb_1__1__59_chanx_left_out ;
+wire [0:19] sb_1__1__59_chanx_right_out ;
+wire [0:19] sb_1__1__59_chany_bottom_out ;
+wire [0:19] sb_1__1__59_chany_top_out ;
+wire [0:0] sb_1__1__5_ccff_tail ;
+wire [0:19] sb_1__1__5_chanx_left_out ;
+wire [0:19] sb_1__1__5_chanx_right_out ;
+wire [0:19] sb_1__1__5_chany_bottom_out ;
+wire [0:19] sb_1__1__5_chany_top_out ;
+wire [0:0] sb_1__1__60_ccff_tail ;
+wire [0:19] sb_1__1__60_chanx_left_out ;
+wire [0:19] sb_1__1__60_chanx_right_out ;
+wire [0:19] sb_1__1__60_chany_bottom_out ;
+wire [0:19] sb_1__1__60_chany_top_out ;
+wire [0:0] sb_1__1__61_ccff_tail ;
+wire [0:19] sb_1__1__61_chanx_left_out ;
+wire [0:19] sb_1__1__61_chanx_right_out ;
+wire [0:19] sb_1__1__61_chany_bottom_out ;
+wire [0:19] sb_1__1__61_chany_top_out ;
+wire [0:0] sb_1__1__62_ccff_tail ;
+wire [0:19] sb_1__1__62_chanx_left_out ;
+wire [0:19] sb_1__1__62_chanx_right_out ;
+wire [0:19] sb_1__1__62_chany_bottom_out ;
+wire [0:19] sb_1__1__62_chany_top_out ;
+wire [0:0] sb_1__1__63_ccff_tail ;
+wire [0:19] sb_1__1__63_chanx_left_out ;
+wire [0:19] sb_1__1__63_chanx_right_out ;
+wire [0:19] sb_1__1__63_chany_bottom_out ;
+wire [0:19] sb_1__1__63_chany_top_out ;
+wire [0:0] sb_1__1__64_ccff_tail ;
+wire [0:19] sb_1__1__64_chanx_left_out ;
+wire [0:19] sb_1__1__64_chanx_right_out ;
+wire [0:19] sb_1__1__64_chany_bottom_out ;
+wire [0:19] sb_1__1__64_chany_top_out ;
+wire [0:0] sb_1__1__65_ccff_tail ;
+wire [0:19] sb_1__1__65_chanx_left_out ;
+wire [0:19] sb_1__1__65_chanx_right_out ;
+wire [0:19] sb_1__1__65_chany_bottom_out ;
+wire [0:19] sb_1__1__65_chany_top_out ;
+wire [0:0] sb_1__1__66_ccff_tail ;
+wire [0:19] sb_1__1__66_chanx_left_out ;
+wire [0:19] sb_1__1__66_chanx_right_out ;
+wire [0:19] sb_1__1__66_chany_bottom_out ;
+wire [0:19] sb_1__1__66_chany_top_out ;
+wire [0:0] sb_1__1__67_ccff_tail ;
+wire [0:19] sb_1__1__67_chanx_left_out ;
+wire [0:19] sb_1__1__67_chanx_right_out ;
+wire [0:19] sb_1__1__67_chany_bottom_out ;
+wire [0:19] sb_1__1__67_chany_top_out ;
+wire [0:0] sb_1__1__68_ccff_tail ;
+wire [0:19] sb_1__1__68_chanx_left_out ;
+wire [0:19] sb_1__1__68_chanx_right_out ;
+wire [0:19] sb_1__1__68_chany_bottom_out ;
+wire [0:19] sb_1__1__68_chany_top_out ;
+wire [0:0] sb_1__1__69_ccff_tail ;
+wire [0:19] sb_1__1__69_chanx_left_out ;
+wire [0:19] sb_1__1__69_chanx_right_out ;
+wire [0:19] sb_1__1__69_chany_bottom_out ;
+wire [0:19] sb_1__1__69_chany_top_out ;
+wire [0:0] sb_1__1__6_ccff_tail ;
+wire [0:19] sb_1__1__6_chanx_left_out ;
+wire [0:19] sb_1__1__6_chanx_right_out ;
+wire [0:19] sb_1__1__6_chany_bottom_out ;
+wire [0:19] sb_1__1__6_chany_top_out ;
+wire [0:0] sb_1__1__70_ccff_tail ;
+wire [0:19] sb_1__1__70_chanx_left_out ;
+wire [0:19] sb_1__1__70_chanx_right_out ;
+wire [0:19] sb_1__1__70_chany_bottom_out ;
+wire [0:19] sb_1__1__70_chany_top_out ;
+wire [0:0] sb_1__1__71_ccff_tail ;
+wire [0:19] sb_1__1__71_chanx_left_out ;
+wire [0:19] sb_1__1__71_chanx_right_out ;
+wire [0:19] sb_1__1__71_chany_bottom_out ;
+wire [0:19] sb_1__1__71_chany_top_out ;
+wire [0:0] sb_1__1__72_ccff_tail ;
+wire [0:19] sb_1__1__72_chanx_left_out ;
+wire [0:19] sb_1__1__72_chanx_right_out ;
+wire [0:19] sb_1__1__72_chany_bottom_out ;
+wire [0:19] sb_1__1__72_chany_top_out ;
+wire [0:0] sb_1__1__73_ccff_tail ;
+wire [0:19] sb_1__1__73_chanx_left_out ;
+wire [0:19] sb_1__1__73_chanx_right_out ;
+wire [0:19] sb_1__1__73_chany_bottom_out ;
+wire [0:19] sb_1__1__73_chany_top_out ;
+wire [0:0] sb_1__1__74_ccff_tail ;
+wire [0:19] sb_1__1__74_chanx_left_out ;
+wire [0:19] sb_1__1__74_chanx_right_out ;
+wire [0:19] sb_1__1__74_chany_bottom_out ;
+wire [0:19] sb_1__1__74_chany_top_out ;
+wire [0:0] sb_1__1__75_ccff_tail ;
+wire [0:19] sb_1__1__75_chanx_left_out ;
+wire [0:19] sb_1__1__75_chanx_right_out ;
+wire [0:19] sb_1__1__75_chany_bottom_out ;
+wire [0:19] sb_1__1__75_chany_top_out ;
+wire [0:0] sb_1__1__76_ccff_tail ;
+wire [0:19] sb_1__1__76_chanx_left_out ;
+wire [0:19] sb_1__1__76_chanx_right_out ;
+wire [0:19] sb_1__1__76_chany_bottom_out ;
+wire [0:19] sb_1__1__76_chany_top_out ;
+wire [0:0] sb_1__1__77_ccff_tail ;
+wire [0:19] sb_1__1__77_chanx_left_out ;
+wire [0:19] sb_1__1__77_chanx_right_out ;
+wire [0:19] sb_1__1__77_chany_bottom_out ;
+wire [0:19] sb_1__1__77_chany_top_out ;
+wire [0:0] sb_1__1__78_ccff_tail ;
+wire [0:19] sb_1__1__78_chanx_left_out ;
+wire [0:19] sb_1__1__78_chanx_right_out ;
+wire [0:19] sb_1__1__78_chany_bottom_out ;
+wire [0:19] sb_1__1__78_chany_top_out ;
+wire [0:0] sb_1__1__79_ccff_tail ;
+wire [0:19] sb_1__1__79_chanx_left_out ;
+wire [0:19] sb_1__1__79_chanx_right_out ;
+wire [0:19] sb_1__1__79_chany_bottom_out ;
+wire [0:19] sb_1__1__79_chany_top_out ;
+wire [0:0] sb_1__1__7_ccff_tail ;
+wire [0:19] sb_1__1__7_chanx_left_out ;
+wire [0:19] sb_1__1__7_chanx_right_out ;
+wire [0:19] sb_1__1__7_chany_bottom_out ;
+wire [0:19] sb_1__1__7_chany_top_out ;
+wire [0:0] sb_1__1__80_ccff_tail ;
+wire [0:19] sb_1__1__80_chanx_left_out ;
+wire [0:19] sb_1__1__80_chanx_right_out ;
+wire [0:19] sb_1__1__80_chany_bottom_out ;
+wire [0:19] sb_1__1__80_chany_top_out ;
+wire [0:0] sb_1__1__81_ccff_tail ;
+wire [0:19] sb_1__1__81_chanx_left_out ;
+wire [0:19] sb_1__1__81_chanx_right_out ;
+wire [0:19] sb_1__1__81_chany_bottom_out ;
+wire [0:19] sb_1__1__81_chany_top_out ;
+wire [0:0] sb_1__1__82_ccff_tail ;
+wire [0:19] sb_1__1__82_chanx_left_out ;
+wire [0:19] sb_1__1__82_chanx_right_out ;
+wire [0:19] sb_1__1__82_chany_bottom_out ;
+wire [0:19] sb_1__1__82_chany_top_out ;
+wire [0:0] sb_1__1__83_ccff_tail ;
+wire [0:19] sb_1__1__83_chanx_left_out ;
+wire [0:19] sb_1__1__83_chanx_right_out ;
+wire [0:19] sb_1__1__83_chany_bottom_out ;
+wire [0:19] sb_1__1__83_chany_top_out ;
+wire [0:0] sb_1__1__84_ccff_tail ;
+wire [0:19] sb_1__1__84_chanx_left_out ;
+wire [0:19] sb_1__1__84_chanx_right_out ;
+wire [0:19] sb_1__1__84_chany_bottom_out ;
+wire [0:19] sb_1__1__84_chany_top_out ;
+wire [0:0] sb_1__1__85_ccff_tail ;
+wire [0:19] sb_1__1__85_chanx_left_out ;
+wire [0:19] sb_1__1__85_chanx_right_out ;
+wire [0:19] sb_1__1__85_chany_bottom_out ;
+wire [0:19] sb_1__1__85_chany_top_out ;
+wire [0:0] sb_1__1__86_ccff_tail ;
+wire [0:19] sb_1__1__86_chanx_left_out ;
+wire [0:19] sb_1__1__86_chanx_right_out ;
+wire [0:19] sb_1__1__86_chany_bottom_out ;
+wire [0:19] sb_1__1__86_chany_top_out ;
+wire [0:0] sb_1__1__87_ccff_tail ;
+wire [0:19] sb_1__1__87_chanx_left_out ;
+wire [0:19] sb_1__1__87_chanx_right_out ;
+wire [0:19] sb_1__1__87_chany_bottom_out ;
+wire [0:19] sb_1__1__87_chany_top_out ;
+wire [0:0] sb_1__1__88_ccff_tail ;
+wire [0:19] sb_1__1__88_chanx_left_out ;
+wire [0:19] sb_1__1__88_chanx_right_out ;
+wire [0:19] sb_1__1__88_chany_bottom_out ;
+wire [0:19] sb_1__1__88_chany_top_out ;
+wire [0:0] sb_1__1__89_ccff_tail ;
+wire [0:19] sb_1__1__89_chanx_left_out ;
+wire [0:19] sb_1__1__89_chanx_right_out ;
+wire [0:19] sb_1__1__89_chany_bottom_out ;
+wire [0:19] sb_1__1__89_chany_top_out ;
+wire [0:0] sb_1__1__8_ccff_tail ;
+wire [0:19] sb_1__1__8_chanx_left_out ;
+wire [0:19] sb_1__1__8_chanx_right_out ;
+wire [0:19] sb_1__1__8_chany_bottom_out ;
+wire [0:19] sb_1__1__8_chany_top_out ;
+wire [0:0] sb_1__1__90_ccff_tail ;
+wire [0:19] sb_1__1__90_chanx_left_out ;
+wire [0:19] sb_1__1__90_chanx_right_out ;
+wire [0:19] sb_1__1__90_chany_bottom_out ;
+wire [0:19] sb_1__1__90_chany_top_out ;
+wire [0:0] sb_1__1__91_ccff_tail ;
+wire [0:19] sb_1__1__91_chanx_left_out ;
+wire [0:19] sb_1__1__91_chanx_right_out ;
+wire [0:19] sb_1__1__91_chany_bottom_out ;
+wire [0:19] sb_1__1__91_chany_top_out ;
+wire [0:0] sb_1__1__92_ccff_tail ;
+wire [0:19] sb_1__1__92_chanx_left_out ;
+wire [0:19] sb_1__1__92_chanx_right_out ;
+wire [0:19] sb_1__1__92_chany_bottom_out ;
+wire [0:19] sb_1__1__92_chany_top_out ;
+wire [0:0] sb_1__1__93_ccff_tail ;
+wire [0:19] sb_1__1__93_chanx_left_out ;
+wire [0:19] sb_1__1__93_chanx_right_out ;
+wire [0:19] sb_1__1__93_chany_bottom_out ;
+wire [0:19] sb_1__1__93_chany_top_out ;
+wire [0:0] sb_1__1__94_ccff_tail ;
+wire [0:19] sb_1__1__94_chanx_left_out ;
+wire [0:19] sb_1__1__94_chanx_right_out ;
+wire [0:19] sb_1__1__94_chany_bottom_out ;
+wire [0:19] sb_1__1__94_chany_top_out ;
+wire [0:0] sb_1__1__95_ccff_tail ;
+wire [0:19] sb_1__1__95_chanx_left_out ;
+wire [0:19] sb_1__1__95_chanx_right_out ;
+wire [0:19] sb_1__1__95_chany_bottom_out ;
+wire [0:19] sb_1__1__95_chany_top_out ;
+wire [0:0] sb_1__1__96_ccff_tail ;
+wire [0:19] sb_1__1__96_chanx_left_out ;
+wire [0:19] sb_1__1__96_chanx_right_out ;
+wire [0:19] sb_1__1__96_chany_bottom_out ;
+wire [0:19] sb_1__1__96_chany_top_out ;
+wire [0:0] sb_1__1__97_ccff_tail ;
+wire [0:19] sb_1__1__97_chanx_left_out ;
+wire [0:19] sb_1__1__97_chanx_right_out ;
+wire [0:19] sb_1__1__97_chany_bottom_out ;
+wire [0:19] sb_1__1__97_chany_top_out ;
+wire [0:0] sb_1__1__98_ccff_tail ;
+wire [0:19] sb_1__1__98_chanx_left_out ;
+wire [0:19] sb_1__1__98_chanx_right_out ;
+wire [0:19] sb_1__1__98_chany_bottom_out ;
+wire [0:19] sb_1__1__98_chany_top_out ;
+wire [0:0] sb_1__1__99_ccff_tail ;
+wire [0:19] sb_1__1__99_chanx_left_out ;
+wire [0:19] sb_1__1__99_chanx_right_out ;
+wire [0:19] sb_1__1__99_chany_bottom_out ;
+wire [0:19] sb_1__1__99_chany_top_out ;
+wire [0:0] sb_1__1__9_ccff_tail ;
+wire [0:19] sb_1__1__9_chanx_left_out ;
+wire [0:19] sb_1__1__9_chanx_right_out ;
+wire [0:19] sb_1__1__9_chany_bottom_out ;
+wire [0:19] sb_1__1__9_chany_top_out ;
+wire [1:0] UNCONN ;
+wire [317:0] scff_Wires ;
+wire [132:0] regin_feedthrough_wires ;
+wire [132:0] regout_feedthrough_wires ;
+wire [287:0] Test_enWires ;
+wire [624:0] prog_clk_0_wires ;
+wire [251:0] prog_clk_1_wires ;
+wire [135:0] prog_clk_2_wires ;
+wire [100:0] prog_clk_3_wires ;
+wire [251:0] clk_1_wires ;
+wire [135:0] clk_2_wires ;
+wire [100:0] clk_3_wires ;
+
+grid_clb grid_clb_1__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[0] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_0_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_0_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_0_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_0_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_0_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_0_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_0_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_0_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_0_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_2 } ) ,
+ .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[23] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires[25] ) ,
+ .Test_en_E_in ( Test_enWires[24] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[4] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[0] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[1] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[3] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9 ) ,
+ .clk_0_N_in ( clk_1_wires[4] ) , .clk_0_S_in ( SYNOPSYS_UNCONNECTED_10 ) ) ;
+grid_clb grid_clb_1__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[1] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_11 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_1_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_1_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_1_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_1_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_1_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_1_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_1_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_1_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_1_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[0] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_12 } ) ,
+ .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[21] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_13 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_14 ) , .SC_OUT_BOT ( scff_Wires[22] ) ,
+ .Test_en_E_in ( Test_enWires[46] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_15 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_16 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_17 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_18 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[3] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[6] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[7] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[9] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_19 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_20 ) , .clk_0_S_in ( clk_1_wires[3] ) ) ;
+grid_clb grid_clb_1__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[2] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_21 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_2_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_2_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_2_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_2_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_2_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_2_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_2_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_2_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_2_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[1] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_22 } ) ,
+ .ccff_tail ( grid_clb_2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[19] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_23 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_24 ) , .SC_OUT_BOT ( scff_Wires[20] ) ,
+ .Test_en_E_in ( Test_enWires[68] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_25 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_26 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_27 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[11] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_28 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[11] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[12] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[14] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_29 ) ,
+ .clk_0_N_in ( clk_1_wires[11] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_30 ) ) ;
+grid_clb grid_clb_1__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[3] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_31 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_3_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_3_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_3_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_3_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_3_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_3_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_3_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_3_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_3_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[2] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_32 } ) ,
+ .ccff_tail ( grid_clb_3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[17] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_33 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_34 ) , .SC_OUT_BOT ( scff_Wires[18] ) ,
+ .Test_en_E_in ( Test_enWires[90] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_35 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_36 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_37 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_38 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[10] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[16] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[17] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[19] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_39 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_40 ) ,
+ .clk_0_S_in ( clk_1_wires[10] ) ) ;
+grid_clb grid_clb_1__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[4] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_41 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_4_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_4_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_4_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_4_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_4_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_4_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_4_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_4_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_4_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_4_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_4_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_4_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_4_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_4_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_4_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_4_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_4_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_4_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_4_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_4_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_4_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_4_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_4_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_4_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_4_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_4_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_4_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_4_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_4_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_4_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_4_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_4_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_4_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[3] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_42 } ) ,
+ .ccff_tail ( grid_clb_4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[15] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_43 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_44 ) , .SC_OUT_BOT ( scff_Wires[16] ) ,
+ .Test_en_E_in ( Test_enWires[112] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_45 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_46 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_47 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[18] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_48 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[21] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[22] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[24] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_49 ) ,
+ .clk_0_N_in ( clk_1_wires[18] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_50 ) ) ;
+grid_clb grid_clb_1__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[5] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_51 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_5_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_5_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_5_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_5_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_5_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_5_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_5_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_5_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_5_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_5_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_5_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_5_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_5_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_5_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_5_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_5_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_5_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_5_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_5_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_5_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_5_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_5_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_5_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_5_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_5_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_5_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_5_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_5_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_5_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_5_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_5_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_5_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_5_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[4] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_52 } ) ,
+ .ccff_tail ( grid_clb_5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[13] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_53 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_54 ) , .SC_OUT_BOT ( scff_Wires[14] ) ,
+ .Test_en_E_in ( Test_enWires[134] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_55 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_56 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_57 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_58 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[17] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[26] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[27] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[29] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_59 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_60 ) ,
+ .clk_0_S_in ( clk_1_wires[17] ) ) ;
+grid_clb grid_clb_1__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[6] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_61 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_6_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_6_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_6_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_6_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_6_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_6_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_6_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_6_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_6_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_6_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_6_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_6_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_6_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_6_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_6_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_6_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_6_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_6_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_6_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_6_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_6_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_6_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_6_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_6_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_6_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_6_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_6_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_6_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_6_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_6_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_6_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_6_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_6_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[5] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_62 } ) ,
+ .ccff_tail ( grid_clb_6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[11] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_63 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_64 ) , .SC_OUT_BOT ( scff_Wires[12] ) ,
+ .Test_en_E_in ( Test_enWires[156] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_66 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_67 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[25] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_68 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[31] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[32] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[34] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .clk_0_N_in ( clk_1_wires[25] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_70 ) ) ;
+grid_clb grid_clb_1__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[7] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_71 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_7_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_7_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_7_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_7_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_7_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_7_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_7_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_7_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_7_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_7_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_7_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_7_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_7_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_7_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_7_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_7_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_7_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_7_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_7_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_7_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_7_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_7_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_7_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_7_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_7_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_7_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_7_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_7_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_7_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_7_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_7_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_7_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_7_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[6] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_72 } ) ,
+ .ccff_tail ( grid_clb_7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[9] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_73 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_74 ) , .SC_OUT_BOT ( scff_Wires[10] ) ,
+ .Test_en_E_in ( Test_enWires[178] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_75 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_76 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_77 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_78 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[24] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[36] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[37] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[39] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_79 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_80 ) ,
+ .clk_0_S_in ( clk_1_wires[24] ) ) ;
+grid_clb grid_clb_1__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[8] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_81 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_8_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_8_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_8_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_8_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_8_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_8_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_8_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_8_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_8_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_8_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_8_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_8_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_8_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_8_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_8_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_8_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_8_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_8_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_8_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_8_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_8_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_8_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_8_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_8_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_8_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_8_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_8_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_8_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_8_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_8_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_8_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_8_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_8_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[7] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_82 } ) ,
+ .ccff_tail ( grid_clb_8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[7] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_83 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_84 ) , .SC_OUT_BOT ( scff_Wires[8] ) ,
+ .Test_en_E_in ( Test_enWires[200] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_85 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_86 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_87 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[32] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_88 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[41] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[42] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[44] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_89 ) ,
+ .clk_0_N_in ( clk_1_wires[32] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_90 ) ) ;
+grid_clb grid_clb_1__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[9] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_91 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_9_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_9_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_9_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_9_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_9_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_9_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_9_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_9_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_9_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_9_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_9_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_9_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_9_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_9_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_9_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_9_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_9_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_9_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_9_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_9_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_9_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_9_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_9_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_9_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_9_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_9_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_9_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_9_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_9_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_9_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_9_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_9_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_9_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[8] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_92 } ) ,
+ .ccff_tail ( grid_clb_9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[5] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_93 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_94 ) , .SC_OUT_BOT ( scff_Wires[6] ) ,
+ .Test_en_E_in ( Test_enWires[222] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_95 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_96 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_97 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_98 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[31] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[46] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[47] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[49] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_99 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_100 ) ,
+ .clk_0_S_in ( clk_1_wires[31] ) ) ;
+grid_clb grid_clb_1__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[10] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_101 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_10_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_10_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_10_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_10_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_10_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_10_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_10_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_10_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_10_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_10_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_10_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_10_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_10_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_10_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_10_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_10_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_10_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_10_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_10_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_10_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_10_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_10_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_10_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_10_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_10_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_10_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_10_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_10_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_10_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_10_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_10_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_10_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_10_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[9] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_102 } ) ,
+ .ccff_tail ( grid_clb_10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[3] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_103 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_104 ) , .SC_OUT_BOT ( scff_Wires[4] ) ,
+ .Test_en_E_in ( Test_enWires[244] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_105 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_106 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_107 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[39] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_108 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[51] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[52] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[54] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_109 ) ,
+ .clk_0_N_in ( clk_1_wires[39] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_110 ) ) ;
+grid_clb grid_clb_1__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_111 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) ,
+ .ccff_head ( grid_io_left_11_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_11_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_11_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_11_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_11_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_11_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_11_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_11_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_11_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_11_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_11_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_11_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_11_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_11_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_11_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_11_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_11_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_11_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_11_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_11_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_11_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_11_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_11_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_11_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_11_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_11_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_11_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_11_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_11_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_11_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_11_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_11_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_11_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[10] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_112 } ) ,
+ .ccff_tail ( grid_clb_11_ccff_tail ) , .SC_IN_TOP ( scff_Wires[1] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_113 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_114 ) , .SC_OUT_BOT ( scff_Wires[2] ) ,
+ .Test_en_E_in ( Test_enWires[266] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_115 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_116 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_117 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_118 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[38] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[56] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[57] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[61] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[59] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_119 ) ,
+ .clk_0_S_in ( clk_1_wires[38] ) ) ;
+grid_clb grid_clb_2__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[11] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_120 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__0_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_12_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_12_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_12_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_12_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_12_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_12_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_12_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_12_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_12_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_12_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_12_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_12_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_12_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_12_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_12_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_12_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_12_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_12_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_12_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_12_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_12_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_12_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_12_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_12_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_12_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_12_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_12_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_12_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_12_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_12_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_12_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_12_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_121 } ) ,
+ .ccff_tail ( grid_clb_12_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_122 ) , .SC_IN_BOT ( scff_Wires[28] ) ,
+ .SC_OUT_TOP ( scff_Wires[29] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_123 ) ,
+ .Test_en_E_in ( Test_enWires[25] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_124 ) ,
+ .Test_en_W_out ( Test_enWires[26] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_125 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[6] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_126 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[63] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[64] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_127 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_128 ) ,
+ .clk_0_N_in ( clk_1_wires[6] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_129 ) ) ;
+grid_clb grid_clb_2__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[12] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_130 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__1_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_13_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_13_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_13_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_13_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_13_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_13_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_13_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_13_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_13_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_13_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_13_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_13_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_13_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_13_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_13_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_13_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_13_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_13_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_13_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_13_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_13_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_13_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_13_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_13_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_13_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_13_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_13_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_13_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_13_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_13_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_13_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_13_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[11] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_131 } ) ,
+ .ccff_tail ( grid_clb_13_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_132 ) , .SC_IN_BOT ( scff_Wires[30] ) ,
+ .SC_OUT_TOP ( scff_Wires[31] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_133 ) ,
+ .Test_en_E_in ( Test_enWires[47] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_134 ) ,
+ .Test_en_W_out ( Test_enWires[48] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_135 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_136 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[5] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[66] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[67] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_137 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_138 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_139 ) ,
+ .clk_0_S_in ( clk_1_wires[5] ) ) ;
+grid_clb grid_clb_2__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[13] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_140 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__2_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_14_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_14_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_14_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_14_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_14_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_14_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_14_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_14_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_14_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_14_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_14_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_14_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_14_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_14_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_14_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_14_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_14_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_14_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_14_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_14_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_14_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_14_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_14_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_14_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_14_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_14_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_14_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_14_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_14_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_14_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_14_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_14_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[12] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_141 } ) ,
+ .ccff_tail ( grid_clb_14_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_142 ) , .SC_IN_BOT ( scff_Wires[32] ) ,
+ .SC_OUT_TOP ( scff_Wires[33] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_143 ) ,
+ .Test_en_E_in ( Test_enWires[69] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_144 ) ,
+ .Test_en_W_out ( Test_enWires[70] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_145 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[13] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_146 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[69] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[70] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_147 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_148 ) ,
+ .clk_0_N_in ( clk_1_wires[13] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_149 ) ) ;
+grid_clb grid_clb_2__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[14] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_150 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__3_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_15_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_15_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_15_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_15_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_15_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_15_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_15_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_15_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_15_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_15_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_15_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_15_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_15_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_15_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_15_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_15_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_15_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_15_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_15_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_15_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_15_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_15_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_15_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_15_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_15_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_15_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_15_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_15_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_15_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_15_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_15_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_15_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[13] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_151 } ) ,
+ .ccff_tail ( grid_clb_15_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_152 ) , .SC_IN_BOT ( scff_Wires[34] ) ,
+ .SC_OUT_TOP ( scff_Wires[35] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_153 ) ,
+ .Test_en_E_in ( Test_enWires[91] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_154 ) ,
+ .Test_en_W_out ( Test_enWires[92] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_155 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_156 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[12] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[72] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[73] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_157 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_158 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_159 ) ,
+ .clk_0_S_in ( clk_1_wires[12] ) ) ;
+grid_clb grid_clb_2__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[15] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_160 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__4_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_16_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_16_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_16_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_16_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_16_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_16_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_16_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_16_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_16_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_16_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_16_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_16_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_16_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_16_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_16_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_16_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_16_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_16_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_16_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_16_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_16_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_16_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_16_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_16_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_16_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_16_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_16_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_16_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_16_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_16_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_16_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_16_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[14] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_161 } ) ,
+ .ccff_tail ( grid_clb_16_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_162 ) , .SC_IN_BOT ( scff_Wires[36] ) ,
+ .SC_OUT_TOP ( scff_Wires[37] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_163 ) ,
+ .Test_en_E_in ( Test_enWires[113] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_164 ) ,
+ .Test_en_W_out ( Test_enWires[114] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_165 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[20] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_166 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[75] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[76] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_167 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_168 ) ,
+ .clk_0_N_in ( clk_1_wires[20] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_169 ) ) ;
+grid_clb grid_clb_2__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[16] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_170 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__5_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_17_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_17_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_17_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_17_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_17_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_17_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_17_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_17_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_17_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_17_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_17_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_17_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_17_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_17_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_17_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_17_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_17_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_17_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_17_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_17_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_17_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_17_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_17_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_17_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_17_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_17_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_17_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_17_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_17_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_17_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_17_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_17_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[15] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_171 } ) ,
+ .ccff_tail ( grid_clb_17_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_172 ) , .SC_IN_BOT ( scff_Wires[38] ) ,
+ .SC_OUT_TOP ( scff_Wires[39] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_173 ) ,
+ .Test_en_E_in ( Test_enWires[135] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_174 ) ,
+ .Test_en_W_out ( Test_enWires[136] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_175 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_176 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[19] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[78] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[79] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_177 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_178 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_179 ) ,
+ .clk_0_S_in ( clk_1_wires[19] ) ) ;
+grid_clb grid_clb_2__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[17] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_180 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__6_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_18_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_18_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_18_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_18_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_18_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_18_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_18_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_18_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_18_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_18_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_18_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_18_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_18_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_18_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_18_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_18_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_18_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_18_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_18_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_18_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_18_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_18_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_18_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_18_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_18_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_18_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_18_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_18_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_18_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_18_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_18_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_18_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[16] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_181 } ) ,
+ .ccff_tail ( grid_clb_18_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_182 ) , .SC_IN_BOT ( scff_Wires[40] ) ,
+ .SC_OUT_TOP ( scff_Wires[41] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_183 ) ,
+ .Test_en_E_in ( Test_enWires[157] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_184 ) ,
+ .Test_en_W_out ( Test_enWires[158] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_185 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[27] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_186 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[81] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[82] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_187 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_188 ) ,
+ .clk_0_N_in ( clk_1_wires[27] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_189 ) ) ;
+grid_clb grid_clb_2__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[18] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_190 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__7_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_19_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_19_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_19_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_19_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_19_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_19_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_19_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_19_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_19_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_19_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_19_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_19_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_19_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_19_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_19_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_19_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_19_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_19_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_19_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_19_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_19_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_19_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_19_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_19_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_19_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_19_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_19_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_19_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_19_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_19_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_19_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_19_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[17] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_191 } ) ,
+ .ccff_tail ( grid_clb_19_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_192 ) , .SC_IN_BOT ( scff_Wires[42] ) ,
+ .SC_OUT_TOP ( scff_Wires[43] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_193 ) ,
+ .Test_en_E_in ( Test_enWires[179] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_194 ) ,
+ .Test_en_W_out ( Test_enWires[180] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_195 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_196 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[26] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[84] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[85] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_197 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_198 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_199 ) ,
+ .clk_0_S_in ( clk_1_wires[26] ) ) ;
+grid_clb grid_clb_2__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[19] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_200 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__8_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_20_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_20_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_20_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_20_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_20_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_20_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_20_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_20_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_20_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_20_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_20_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_20_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_20_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_20_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_20_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_20_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_20_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_20_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_20_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_20_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_20_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_20_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_20_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_20_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_20_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_20_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_20_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_20_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_20_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_20_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_20_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_20_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[18] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_201 } ) ,
+ .ccff_tail ( grid_clb_20_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_202 ) , .SC_IN_BOT ( scff_Wires[44] ) ,
+ .SC_OUT_TOP ( scff_Wires[45] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_203 ) ,
+ .Test_en_E_in ( Test_enWires[201] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_204 ) ,
+ .Test_en_W_out ( Test_enWires[202] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_205 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[34] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_206 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[87] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[88] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_207 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_208 ) ,
+ .clk_0_N_in ( clk_1_wires[34] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_209 ) ) ;
+grid_clb grid_clb_2__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[20] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_210 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__9_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_21_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_21_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_21_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_21_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_21_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_21_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_21_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_21_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_21_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_21_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_21_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_21_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_21_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_21_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_21_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_21_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_21_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_21_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_21_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_21_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_21_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_21_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_21_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_21_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_21_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_21_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_21_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_21_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_21_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_21_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_21_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_21_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[19] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_211 } ) ,
+ .ccff_tail ( grid_clb_21_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_212 ) , .SC_IN_BOT ( scff_Wires[46] ) ,
+ .SC_OUT_TOP ( scff_Wires[47] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_213 ) ,
+ .Test_en_E_in ( Test_enWires[223] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_214 ) ,
+ .Test_en_W_out ( Test_enWires[224] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_215 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_216 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[33] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[90] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[91] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_217 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_218 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_219 ) ,
+ .clk_0_S_in ( clk_1_wires[33] ) ) ;
+grid_clb grid_clb_2__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[21] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_220 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__10_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_22_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_22_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_22_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_22_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_22_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_22_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_22_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_22_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_22_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_22_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_22_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_22_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_22_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_22_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_22_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_22_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_22_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_22_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_22_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_22_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_22_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_22_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_22_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_22_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_22_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_22_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_22_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_22_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_22_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_22_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_22_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_22_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[20] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_221 } ) ,
+ .ccff_tail ( grid_clb_22_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_222 ) , .SC_IN_BOT ( scff_Wires[48] ) ,
+ .SC_OUT_TOP ( scff_Wires[49] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_223 ) ,
+ .Test_en_E_in ( Test_enWires[245] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_224 ) ,
+ .Test_en_W_out ( Test_enWires[246] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_225 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[41] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_226 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[93] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[94] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_227 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_228 ) ,
+ .clk_0_N_in ( clk_1_wires[41] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_229 ) ) ;
+grid_clb grid_clb_2__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_230 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__11_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_23_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_23_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_23_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_23_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_23_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_23_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_23_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_23_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_23_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_23_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_23_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_23_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_23_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_23_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_23_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_23_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_23_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_23_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_23_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_23_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_23_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_23_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_23_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_23_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_23_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_23_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_23_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_23_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_23_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_23_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_23_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_23_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[21] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_231 } ) ,
+ .ccff_tail ( grid_clb_23_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_232 ) , .SC_IN_BOT ( scff_Wires[50] ) ,
+ .SC_OUT_TOP ( scff_Wires[51] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_233 ) ,
+ .Test_en_E_in ( Test_enWires[267] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_234 ) ,
+ .Test_en_W_out ( Test_enWires[268] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_235 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_236 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[40] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[96] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[97] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_237 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[99] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_238 ) ,
+ .clk_0_S_in ( clk_1_wires[40] ) ) ;
+grid_clb grid_clb_3__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[22] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_239 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__12_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_24_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_24_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_24_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_24_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_24_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_24_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_24_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_24_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_24_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_24_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_24_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_24_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_24_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_24_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_24_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_24_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_24_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_24_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_24_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_24_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_24_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_24_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_24_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_24_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_24_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_24_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_24_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_24_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_24_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_24_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_24_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_24_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_240 } ) ,
+ .ccff_tail ( grid_clb_24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[76] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_241 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_242 ) ,
+ .SC_OUT_BOT ( scff_Wires[78] ) , .Test_en_E_in ( Test_enWires[27] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_243 ) ,
+ .Test_en_W_out ( Test_enWires[28] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_244 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[46] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_245 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[101] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[102] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_246 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_247 ) ,
+ .clk_0_N_in ( clk_1_wires[46] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_248 ) ) ;
+grid_clb grid_clb_3__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[23] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_249 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__13_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_25_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_25_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_25_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_25_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_25_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_25_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_25_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_25_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_25_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_25_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_25_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_25_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_25_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_25_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_25_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_25_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_25_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_25_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_25_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_25_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_25_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_25_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_25_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_25_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_25_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_25_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_25_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_25_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_25_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_25_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_25_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_25_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[22] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_250 } ) ,
+ .ccff_tail ( grid_clb_25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[74] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_251 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_252 ) ,
+ .SC_OUT_BOT ( scff_Wires[75] ) , .Test_en_E_in ( Test_enWires[49] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_253 ) ,
+ .Test_en_W_out ( Test_enWires[50] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_254 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_255 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[45] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[104] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[105] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_256 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_257 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_258 ) ,
+ .clk_0_S_in ( clk_1_wires[45] ) ) ;
+grid_clb grid_clb_3__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[24] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_259 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__14_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_26_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_26_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_26_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_26_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_26_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_26_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_26_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_26_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_26_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_26_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_26_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_26_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_26_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_26_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_26_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_26_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_26_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_26_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_26_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_26_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_26_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_26_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_26_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_26_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_26_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_26_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_26_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_26_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_26_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_26_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_26_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_26_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[23] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_260 } ) ,
+ .ccff_tail ( grid_clb_26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[72] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_261 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_262 ) ,
+ .SC_OUT_BOT ( scff_Wires[73] ) , .Test_en_E_in ( Test_enWires[71] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_263 ) ,
+ .Test_en_W_out ( Test_enWires[72] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_264 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[53] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_265 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[107] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[108] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_266 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_267 ) ,
+ .clk_0_N_in ( clk_1_wires[53] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_268 ) ) ;
+grid_clb grid_clb_3__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[25] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_269 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__15_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_27_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_27_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_27_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_27_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_27_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_27_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_27_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_27_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_27_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_27_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_27_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_27_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_27_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_27_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_27_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_27_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_27_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_27_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_27_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_27_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_27_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_27_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_27_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_27_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_27_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_27_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_27_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_27_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_27_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_27_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_27_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_27_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[24] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_270 } ) ,
+ .ccff_tail ( grid_clb_27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[70] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_271 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_272 ) ,
+ .SC_OUT_BOT ( scff_Wires[71] ) , .Test_en_E_in ( Test_enWires[93] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_273 ) ,
+ .Test_en_W_out ( Test_enWires[94] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_274 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_275 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[52] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[110] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[111] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_276 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_277 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_278 ) ,
+ .clk_0_S_in ( clk_1_wires[52] ) ) ;
+grid_clb grid_clb_3__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[26] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_279 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__16_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_28_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_28_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_28_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_28_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_28_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_28_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_28_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_28_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_28_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_28_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_28_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_28_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_28_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_28_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_28_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_28_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_28_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_28_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_28_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_28_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_28_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_28_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_28_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_28_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_28_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_28_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_28_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_28_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_28_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_28_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_28_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_28_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[25] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_280 } ) ,
+ .ccff_tail ( grid_clb_28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[68] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_281 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_282 ) ,
+ .SC_OUT_BOT ( scff_Wires[69] ) , .Test_en_E_in ( Test_enWires[115] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_283 ) ,
+ .Test_en_W_out ( Test_enWires[116] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_284 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[60] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_285 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[113] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[114] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_286 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_287 ) ,
+ .clk_0_N_in ( clk_1_wires[60] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_288 ) ) ;
+grid_clb grid_clb_3__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[27] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_289 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__17_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_29_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_29_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_29_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_29_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_29_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_29_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_29_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_29_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_29_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_29_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_29_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_29_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_29_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_29_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_29_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_29_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_29_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_29_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_29_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_29_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_29_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_29_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_29_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_29_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_29_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_29_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_29_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_29_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_29_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_29_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_29_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_29_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[26] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_290 } ) ,
+ .ccff_tail ( grid_clb_29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[66] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_291 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_292 ) ,
+ .SC_OUT_BOT ( scff_Wires[67] ) , .Test_en_E_in ( Test_enWires[137] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_293 ) ,
+ .Test_en_W_out ( Test_enWires[138] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_294 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_295 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[59] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[116] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[117] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_296 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_297 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_298 ) ,
+ .clk_0_S_in ( clk_1_wires[59] ) ) ;
+grid_clb grid_clb_3__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[28] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_299 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__18_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_30_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_30_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_30_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_30_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_30_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_30_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_30_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_30_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_30_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_30_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_30_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_30_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_30_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_30_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_30_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_30_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_30_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_30_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_30_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_30_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_30_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_30_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_30_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_30_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_30_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_30_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_30_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_30_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_30_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_30_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_30_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_30_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[27] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_300 } ) ,
+ .ccff_tail ( grid_clb_30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[64] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_301 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_302 ) ,
+ .SC_OUT_BOT ( scff_Wires[65] ) , .Test_en_E_in ( Test_enWires[159] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_303 ) ,
+ .Test_en_W_out ( Test_enWires[160] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_304 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[67] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_305 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[119] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[120] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_306 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_307 ) ,
+ .clk_0_N_in ( clk_1_wires[67] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_308 ) ) ;
+grid_clb grid_clb_3__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[29] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_309 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__19_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_31_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_31_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_31_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_31_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_31_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_31_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_31_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_31_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_31_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_31_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_31_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_31_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_31_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_31_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_31_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_31_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_31_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_31_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_31_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_31_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_31_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_31_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_31_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_31_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_31_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_31_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_31_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_31_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_31_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_31_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_31_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_31_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[28] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_310 } ) ,
+ .ccff_tail ( grid_clb_31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[62] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_311 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_312 ) ,
+ .SC_OUT_BOT ( scff_Wires[63] ) , .Test_en_E_in ( Test_enWires[181] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_313 ) ,
+ .Test_en_W_out ( Test_enWires[182] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_314 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_315 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[66] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[122] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[123] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_316 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_317 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_318 ) ,
+ .clk_0_S_in ( clk_1_wires[66] ) ) ;
+grid_clb grid_clb_3__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[30] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_319 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__20_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_32_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_32_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_32_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_32_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_32_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_32_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_32_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_32_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_32_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_32_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_32_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_32_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_32_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_32_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_32_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_32_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_32_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_32_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_32_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_32_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_32_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_32_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_32_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_32_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_32_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_32_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_32_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_32_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_32_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_32_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_32_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_32_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[29] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_320 } ) ,
+ .ccff_tail ( grid_clb_32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[60] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_321 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_322 ) ,
+ .SC_OUT_BOT ( scff_Wires[61] ) , .Test_en_E_in ( Test_enWires[203] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_323 ) ,
+ .Test_en_W_out ( Test_enWires[204] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_324 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[74] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_325 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[125] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[126] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_326 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_327 ) ,
+ .clk_0_N_in ( clk_1_wires[74] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_328 ) ) ;
+grid_clb grid_clb_3__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[31] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_329 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__21_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_33_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_33_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_33_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_33_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_33_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_33_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_33_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_33_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_33_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_33_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_33_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_33_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_33_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_33_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_33_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_33_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_33_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_33_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_33_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_33_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_33_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_33_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_33_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_33_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_33_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_33_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_33_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_33_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_33_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_33_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_33_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_33_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[30] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_330 } ) ,
+ .ccff_tail ( grid_clb_33_ccff_tail ) , .SC_IN_TOP ( scff_Wires[58] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_331 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_332 ) ,
+ .SC_OUT_BOT ( scff_Wires[59] ) , .Test_en_E_in ( Test_enWires[225] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_333 ) ,
+ .Test_en_W_out ( Test_enWires[226] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_334 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_335 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[73] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[128] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[129] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_336 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_337 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_338 ) ,
+ .clk_0_S_in ( clk_1_wires[73] ) ) ;
+grid_clb grid_clb_3__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[32] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_339 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__22_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_34_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_34_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_34_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_34_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_34_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_34_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_34_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_34_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_34_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_34_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_34_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_34_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_34_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_34_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_34_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_34_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_34_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_34_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_34_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_34_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_34_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_34_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_34_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_34_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_34_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_34_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_34_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_34_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_34_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_34_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_34_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_34_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[31] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_340 } ) ,
+ .ccff_tail ( grid_clb_34_ccff_tail ) , .SC_IN_TOP ( scff_Wires[56] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_341 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_342 ) ,
+ .SC_OUT_BOT ( scff_Wires[57] ) , .Test_en_E_in ( Test_enWires[247] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_343 ) ,
+ .Test_en_W_out ( Test_enWires[248] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_344 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[81] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_345 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[131] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[132] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_346 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_347 ) ,
+ .clk_0_N_in ( clk_1_wires[81] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_348 ) ) ;
+grid_clb grid_clb_3__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_349 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__23_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_35_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_35_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_35_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_35_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_35_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_35_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_35_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_35_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_35_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_35_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_35_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_35_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_35_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_35_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_35_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_35_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_35_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_35_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_35_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_35_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_35_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_35_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_35_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_35_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_35_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_35_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_35_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_35_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_35_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_35_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_35_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_35_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[32] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_350 } ) ,
+ .ccff_tail ( grid_clb_35_ccff_tail ) , .SC_IN_TOP ( scff_Wires[54] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_351 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_352 ) ,
+ .SC_OUT_BOT ( scff_Wires[55] ) , .Test_en_E_in ( Test_enWires[269] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_353 ) ,
+ .Test_en_W_out ( Test_enWires[270] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_354 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_355 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[80] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[134] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[135] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_356 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[137] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_357 ) ,
+ .clk_0_S_in ( clk_1_wires[80] ) ) ;
+grid_clb grid_clb_4__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[33] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_358 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__24_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_36_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_36_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_36_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_36_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_36_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_36_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_36_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_36_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_36_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_36_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_36_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_36_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_36_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_36_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_36_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_36_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_36_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_36_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_36_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_36_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_36_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_36_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_36_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_36_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_36_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_36_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_36_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_36_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_36_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_36_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_36_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_36_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_359 } ) ,
+ .ccff_tail ( grid_clb_36_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_360 ) , .SC_IN_BOT ( scff_Wires[81] ) ,
+ .SC_OUT_TOP ( scff_Wires[82] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_361 ) ,
+ .Test_en_E_in ( Test_enWires[29] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_362 ) ,
+ .Test_en_W_out ( Test_enWires[30] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_363 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[48] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_364 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[139] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[140] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_365 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_366 ) ,
+ .clk_0_N_in ( clk_1_wires[48] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_367 ) ) ;
+grid_clb grid_clb_4__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[34] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_368 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__25_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_37_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_37_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_37_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_37_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_37_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_37_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_37_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_37_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_37_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_37_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_37_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_37_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_37_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_37_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_37_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_37_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_37_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_37_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_37_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_37_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_37_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_37_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_37_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_37_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_37_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_37_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_37_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_37_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_37_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_37_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_37_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_37_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[33] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_369 } ) ,
+ .ccff_tail ( grid_clb_37_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_370 ) , .SC_IN_BOT ( scff_Wires[83] ) ,
+ .SC_OUT_TOP ( scff_Wires[84] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_371 ) ,
+ .Test_en_E_in ( Test_enWires[51] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_372 ) ,
+ .Test_en_W_out ( Test_enWires[52] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_373 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_374 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[47] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[142] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[143] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_375 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_376 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_377 ) ,
+ .clk_0_S_in ( clk_1_wires[47] ) ) ;
+grid_clb grid_clb_4__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[35] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_378 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__26_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_38_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_38_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_38_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_38_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_38_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_38_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_38_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_38_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_38_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_38_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_38_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_38_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_38_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_38_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_38_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_38_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_38_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_38_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_38_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_38_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_38_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_38_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_38_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_38_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_38_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_38_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_38_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_38_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_38_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_38_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_38_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_38_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[34] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_379 } ) ,
+ .ccff_tail ( grid_clb_38_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_380 ) , .SC_IN_BOT ( scff_Wires[85] ) ,
+ .SC_OUT_TOP ( scff_Wires[86] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_381 ) ,
+ .Test_en_E_in ( Test_enWires[73] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_382 ) ,
+ .Test_en_W_out ( Test_enWires[74] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_383 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[55] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_384 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[145] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[146] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_385 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_386 ) ,
+ .clk_0_N_in ( clk_1_wires[55] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_387 ) ) ;
+grid_clb grid_clb_4__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[36] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_388 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__27_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_39_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_39_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_39_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_39_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_39_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_39_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_39_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_39_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_39_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_39_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_39_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_39_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_39_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_39_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_39_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_39_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_39_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_39_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_39_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_39_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_39_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_39_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_39_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_39_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_39_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_39_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_39_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_39_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_39_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_39_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_39_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_39_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[35] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_389 } ) ,
+ .ccff_tail ( grid_clb_39_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_390 ) , .SC_IN_BOT ( scff_Wires[87] ) ,
+ .SC_OUT_TOP ( scff_Wires[88] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_391 ) ,
+ .Test_en_E_in ( Test_enWires[95] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_392 ) ,
+ .Test_en_W_out ( Test_enWires[96] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_393 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_394 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[54] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[148] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[149] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_395 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_396 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_397 ) ,
+ .clk_0_S_in ( clk_1_wires[54] ) ) ;
+grid_clb grid_clb_4__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[37] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_398 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__28_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_40_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_40_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_40_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_40_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_40_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_40_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_40_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_40_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_40_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_40_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_40_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_40_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_40_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_40_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_40_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_40_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_40_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_40_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_40_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_40_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_40_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_40_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_40_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_40_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_40_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_40_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_40_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_40_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_40_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_40_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_40_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_40_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[36] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_399 } ) ,
+ .ccff_tail ( grid_clb_40_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_400 ) , .SC_IN_BOT ( scff_Wires[89] ) ,
+ .SC_OUT_TOP ( scff_Wires[90] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_401 ) ,
+ .Test_en_E_in ( Test_enWires[117] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_402 ) ,
+ .Test_en_W_out ( Test_enWires[118] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_403 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[62] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_404 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[151] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[152] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_405 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_406 ) ,
+ .clk_0_N_in ( clk_1_wires[62] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_407 ) ) ;
+grid_clb grid_clb_4__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[38] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_408 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__29_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_41_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_41_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_41_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_41_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_41_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_41_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_41_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_41_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_41_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_41_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_41_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_41_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_41_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_41_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_41_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_41_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_41_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_41_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_41_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_41_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_41_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_41_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_41_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_41_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_41_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_41_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_41_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_41_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_41_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_41_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_41_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_41_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[37] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_409 } ) ,
+ .ccff_tail ( grid_clb_41_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_410 ) , .SC_IN_BOT ( scff_Wires[91] ) ,
+ .SC_OUT_TOP ( scff_Wires[92] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_411 ) ,
+ .Test_en_E_in ( Test_enWires[139] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_412 ) ,
+ .Test_en_W_out ( Test_enWires[140] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_413 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_414 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[61] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[154] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[155] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_415 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_416 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_417 ) ,
+ .clk_0_S_in ( clk_1_wires[61] ) ) ;
+grid_clb grid_clb_4__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[39] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_418 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__30_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_42_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_42_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_42_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_42_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_42_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_42_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_42_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_42_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_42_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_42_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_42_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_42_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_42_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_42_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_42_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_42_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_42_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_42_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_42_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_42_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_42_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_42_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_42_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_42_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_42_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_42_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_42_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_42_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_42_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_42_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_42_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_42_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[38] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_419 } ) ,
+ .ccff_tail ( grid_clb_42_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_420 ) , .SC_IN_BOT ( scff_Wires[93] ) ,
+ .SC_OUT_TOP ( scff_Wires[94] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_421 ) ,
+ .Test_en_E_in ( Test_enWires[161] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_422 ) ,
+ .Test_en_W_out ( Test_enWires[162] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_423 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[69] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_424 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[157] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[158] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_425 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_426 ) ,
+ .clk_0_N_in ( clk_1_wires[69] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_427 ) ) ;
+grid_clb grid_clb_4__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[40] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_428 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__31_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_43_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_43_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_43_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_43_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_43_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_43_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_43_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_43_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_43_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_43_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_43_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_43_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_43_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_43_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_43_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_43_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_43_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_43_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_43_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_43_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_43_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_43_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_43_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_43_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_43_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_43_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_43_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_43_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_43_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_43_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_43_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_43_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[39] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_429 } ) ,
+ .ccff_tail ( grid_clb_43_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_430 ) , .SC_IN_BOT ( scff_Wires[95] ) ,
+ .SC_OUT_TOP ( scff_Wires[96] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_431 ) ,
+ .Test_en_E_in ( Test_enWires[183] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_432 ) ,
+ .Test_en_W_out ( Test_enWires[184] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_433 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_434 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[68] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[160] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[161] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_435 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_436 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_437 ) ,
+ .clk_0_S_in ( clk_1_wires[68] ) ) ;
+grid_clb grid_clb_4__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[41] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_438 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__32_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_44_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_44_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_44_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_44_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_44_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_44_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_44_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_44_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_44_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_44_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_44_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_44_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_44_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_44_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_44_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_44_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_44_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_44_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_44_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_44_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_44_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_44_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_44_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_44_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_44_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_44_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_44_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_44_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_44_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_44_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_44_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_44_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[40] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_439 } ) ,
+ .ccff_tail ( grid_clb_44_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_440 ) , .SC_IN_BOT ( scff_Wires[97] ) ,
+ .SC_OUT_TOP ( scff_Wires[98] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_441 ) ,
+ .Test_en_E_in ( Test_enWires[205] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_442 ) ,
+ .Test_en_W_out ( Test_enWires[206] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_443 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[76] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_444 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[163] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[164] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_445 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_446 ) ,
+ .clk_0_N_in ( clk_1_wires[76] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_447 ) ) ;
+grid_clb grid_clb_4__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[42] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_448 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__33_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_45_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_45_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_45_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_45_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_45_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_45_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_45_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_45_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_45_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_45_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_45_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_45_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_45_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_45_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_45_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_45_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_45_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_45_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_45_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_45_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_45_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_45_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_45_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_45_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_45_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_45_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_45_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_45_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_45_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_45_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_45_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_45_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[41] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_449 } ) ,
+ .ccff_tail ( grid_clb_45_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_450 ) , .SC_IN_BOT ( scff_Wires[99] ) ,
+ .SC_OUT_TOP ( scff_Wires[100] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_451 ) ,
+ .Test_en_E_in ( Test_enWires[227] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_452 ) ,
+ .Test_en_W_out ( Test_enWires[228] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_453 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_454 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[75] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[166] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[167] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_455 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_456 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_457 ) ,
+ .clk_0_S_in ( clk_1_wires[75] ) ) ;
+grid_clb grid_clb_4__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[43] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_458 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__34_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_46_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_46_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_46_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_46_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_46_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_46_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_46_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_46_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_46_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_46_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_46_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_46_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_46_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_46_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_46_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_46_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_46_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_46_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_46_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_46_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_46_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_46_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_46_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_46_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_46_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_46_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_46_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_46_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_46_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_46_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_46_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_46_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[42] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_459 } ) ,
+ .ccff_tail ( grid_clb_46_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_460 ) , .SC_IN_BOT ( scff_Wires[101] ) ,
+ .SC_OUT_TOP ( scff_Wires[102] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_461 ) ,
+ .Test_en_E_in ( Test_enWires[249] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_462 ) ,
+ .Test_en_W_out ( Test_enWires[250] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_463 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[83] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_464 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[169] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[170] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_465 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_466 ) ,
+ .clk_0_N_in ( clk_1_wires[83] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_467 ) ) ;
+grid_clb grid_clb_4__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_468 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__35_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_47_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_47_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_47_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_47_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_47_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_47_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_47_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_47_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_47_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_47_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_47_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_47_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_47_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_47_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_47_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_47_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_47_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_47_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_47_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_47_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_47_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_47_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_47_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_47_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_47_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_47_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_47_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_47_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_47_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_47_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_47_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_47_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[43] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_469 } ) ,
+ .ccff_tail ( grid_clb_47_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_470 ) , .SC_IN_BOT ( scff_Wires[103] ) ,
+ .SC_OUT_TOP ( scff_Wires[104] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_471 ) ,
+ .Test_en_E_in ( Test_enWires[271] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_472 ) ,
+ .Test_en_W_out ( Test_enWires[272] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_473 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_474 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[82] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[172] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[173] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_475 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[175] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_476 ) ,
+ .clk_0_S_in ( clk_1_wires[82] ) ) ;
+grid_clb grid_clb_5__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[44] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_477 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__36_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_48_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_48_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_48_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_48_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_48_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_48_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_48_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_48_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_48_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_48_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_48_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_48_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_48_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_48_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_48_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_48_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_48_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_48_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_48_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_48_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_48_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_48_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_48_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_48_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_48_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_48_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_48_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_48_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_48_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_48_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_48_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_48_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_478 } ) ,
+ .ccff_tail ( grid_clb_48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[129] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_479 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_480 ) ,
+ .SC_OUT_BOT ( scff_Wires[131] ) , .Test_en_E_in ( Test_enWires[31] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_481 ) ,
+ .Test_en_W_out ( Test_enWires[32] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_482 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[88] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_483 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[177] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[178] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_484 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_485 ) ,
+ .clk_0_N_in ( clk_1_wires[88] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_486 ) ) ;
+grid_clb grid_clb_5__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[45] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_487 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__37_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_49_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_49_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_49_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_49_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_49_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_49_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_49_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_49_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_49_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_49_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_49_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_49_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_49_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_49_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_49_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_49_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_49_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_49_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_49_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_49_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_49_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_49_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_49_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_49_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_49_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_49_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_49_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_49_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_49_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_49_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_49_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_49_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[44] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_488 } ) ,
+ .ccff_tail ( grid_clb_49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[127] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_489 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_490 ) ,
+ .SC_OUT_BOT ( scff_Wires[128] ) , .Test_en_E_in ( Test_enWires[53] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_491 ) ,
+ .Test_en_W_out ( Test_enWires[54] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_492 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_493 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[87] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[180] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[181] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_494 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_495 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_496 ) ,
+ .clk_0_S_in ( clk_1_wires[87] ) ) ;
+grid_clb grid_clb_5__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[46] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_497 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__38_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_50_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_50_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_50_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_50_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_50_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_50_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_50_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_50_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_50_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_50_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_50_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_50_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_50_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_50_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_50_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_50_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_50_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_50_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_50_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_50_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_50_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_50_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_50_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_50_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_50_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_50_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_50_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_50_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_50_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_50_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_50_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_50_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[45] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_498 } ) ,
+ .ccff_tail ( grid_clb_50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[125] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_499 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_500 ) ,
+ .SC_OUT_BOT ( scff_Wires[126] ) , .Test_en_E_in ( Test_enWires[75] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_501 ) ,
+ .Test_en_W_out ( Test_enWires[76] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_502 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[95] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_503 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[183] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[184] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_504 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_505 ) ,
+ .clk_0_N_in ( clk_1_wires[95] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_506 ) ) ;
+grid_clb grid_clb_5__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[47] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_507 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__39_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_51_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_51_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_51_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_51_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_51_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_51_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_51_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_51_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_51_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_51_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_51_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_51_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_51_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_51_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_51_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_51_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_51_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_51_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_51_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_51_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_51_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_51_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_51_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_51_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_51_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_51_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_51_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_51_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_51_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_51_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_51_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_51_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[46] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_508 } ) ,
+ .ccff_tail ( grid_clb_51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[123] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_509 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_510 ) ,
+ .SC_OUT_BOT ( scff_Wires[124] ) , .Test_en_E_in ( Test_enWires[97] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_511 ) ,
+ .Test_en_W_out ( Test_enWires[98] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_512 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_513 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[94] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[186] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[187] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_514 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_515 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_516 ) ,
+ .clk_0_S_in ( clk_1_wires[94] ) ) ;
+grid_clb grid_clb_5__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[48] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_517 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__40_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_52_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_52_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_52_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_52_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_52_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_52_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_52_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_52_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_52_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_52_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_52_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_52_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_52_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_52_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_52_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_52_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_52_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_52_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_52_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_52_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_52_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_52_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_52_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_52_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_52_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_52_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_52_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_52_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_52_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_52_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_52_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_52_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[47] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_518 } ) ,
+ .ccff_tail ( grid_clb_52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[121] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_519 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_520 ) ,
+ .SC_OUT_BOT ( scff_Wires[122] ) , .Test_en_E_in ( Test_enWires[119] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_521 ) ,
+ .Test_en_W_out ( Test_enWires[120] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_522 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[102] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_523 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[189] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[190] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_524 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_525 ) ,
+ .clk_0_N_in ( clk_1_wires[102] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_526 ) ) ;
+grid_clb grid_clb_5__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[49] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_527 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__41_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_53_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_53_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_53_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_53_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_53_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_53_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_53_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_53_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_53_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_53_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_53_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_53_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_53_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_53_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_53_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_53_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_53_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_53_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_53_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_53_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_53_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_53_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_53_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_53_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_53_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_53_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_53_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_53_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_53_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_53_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_53_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_53_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[48] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_528 } ) ,
+ .ccff_tail ( grid_clb_53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[119] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_529 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_530 ) ,
+ .SC_OUT_BOT ( scff_Wires[120] ) , .Test_en_E_in ( Test_enWires[141] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_531 ) ,
+ .Test_en_W_out ( Test_enWires[142] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_532 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_533 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[101] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[192] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[193] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_534 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_535 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_536 ) ,
+ .clk_0_S_in ( clk_1_wires[101] ) ) ;
+grid_clb grid_clb_5__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[50] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_537 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__42_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_54_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_54_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_54_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_54_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_54_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_54_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_54_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_54_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_54_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_54_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_54_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_54_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_54_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_54_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_54_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_54_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_54_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_54_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_54_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_54_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_54_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_54_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_54_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_54_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_54_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_54_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_54_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_54_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_54_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_54_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_54_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_54_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[49] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_538 } ) ,
+ .ccff_tail ( grid_clb_54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[117] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_539 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_540 ) ,
+ .SC_OUT_BOT ( scff_Wires[118] ) , .Test_en_E_in ( Test_enWires[163] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_541 ) ,
+ .Test_en_W_out ( Test_enWires[164] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_542 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[109] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_543 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[195] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[196] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_544 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_545 ) ,
+ .clk_0_N_in ( clk_1_wires[109] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_546 ) ) ;
+grid_clb grid_clb_5__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[51] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_547 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__43_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_55_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_55_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_55_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_55_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_55_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_55_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_55_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_55_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_55_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_55_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_55_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_55_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_55_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_55_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_55_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_55_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_55_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_55_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_55_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_55_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_55_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_55_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_55_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_55_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_55_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_55_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_55_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_55_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_55_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_55_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_55_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_55_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[50] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_548 } ) ,
+ .ccff_tail ( grid_clb_55_ccff_tail ) , .SC_IN_TOP ( scff_Wires[115] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_549 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_550 ) ,
+ .SC_OUT_BOT ( scff_Wires[116] ) , .Test_en_E_in ( Test_enWires[185] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_551 ) ,
+ .Test_en_W_out ( Test_enWires[186] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_552 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_553 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[108] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[198] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[199] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_554 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_555 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_556 ) ,
+ .clk_0_S_in ( clk_1_wires[108] ) ) ;
+grid_clb grid_clb_5__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[52] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_557 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__44_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_56_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_56_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_56_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_56_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_56_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_56_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_56_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_56_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_56_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_56_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_56_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_56_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_56_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_56_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_56_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_56_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_56_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_56_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_56_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_56_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_56_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_56_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_56_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_56_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_56_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_56_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_56_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_56_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_56_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_56_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_56_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_56_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[51] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_558 } ) ,
+ .ccff_tail ( grid_clb_56_ccff_tail ) , .SC_IN_TOP ( scff_Wires[113] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_559 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_560 ) ,
+ .SC_OUT_BOT ( scff_Wires[114] ) , .Test_en_E_in ( Test_enWires[207] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_561 ) ,
+ .Test_en_W_out ( Test_enWires[208] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_562 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[116] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_563 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[201] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[202] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_564 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_565 ) ,
+ .clk_0_N_in ( clk_1_wires[116] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_566 ) ) ;
+grid_clb grid_clb_5__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[53] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_567 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__45_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_57_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_57_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_57_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_57_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_57_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_57_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_57_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_57_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_57_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_57_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_57_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_57_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_57_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_57_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_57_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_57_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_57_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_57_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_57_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_57_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_57_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_57_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_57_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_57_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_57_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_57_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_57_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_57_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_57_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_57_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_57_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_57_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[52] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_568 } ) ,
+ .ccff_tail ( grid_clb_57_ccff_tail ) , .SC_IN_TOP ( scff_Wires[111] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_569 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_570 ) ,
+ .SC_OUT_BOT ( scff_Wires[112] ) , .Test_en_E_in ( Test_enWires[229] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_571 ) ,
+ .Test_en_W_out ( Test_enWires[230] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_572 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_573 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[115] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[204] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[205] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_574 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_575 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_576 ) ,
+ .clk_0_S_in ( clk_1_wires[115] ) ) ;
+grid_clb grid_clb_5__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[54] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_577 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__46_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_58_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_58_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_58_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_58_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_58_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_58_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_58_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_58_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_58_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_58_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_58_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_58_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_58_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_58_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_58_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_58_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_58_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_58_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_58_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_58_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_58_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_58_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_58_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_58_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_58_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_58_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_58_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_58_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_58_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_58_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_58_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_58_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[53] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_578 } ) ,
+ .ccff_tail ( grid_clb_58_ccff_tail ) , .SC_IN_TOP ( scff_Wires[109] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_579 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_580 ) ,
+ .SC_OUT_BOT ( scff_Wires[110] ) , .Test_en_E_in ( Test_enWires[251] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_581 ) ,
+ .Test_en_W_out ( Test_enWires[252] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_582 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[123] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_583 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[207] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[208] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_584 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_585 ) ,
+ .clk_0_N_in ( clk_1_wires[123] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_586 ) ) ;
+grid_clb grid_clb_5__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_587 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__47_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_59_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_59_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_59_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_59_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_59_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_59_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_59_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_59_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_59_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_59_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_59_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_59_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_59_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_59_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_59_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_59_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_59_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_59_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_59_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_59_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_59_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_59_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_59_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_59_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_59_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_59_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_59_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_59_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_59_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_59_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_59_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_59_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[54] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_588 } ) ,
+ .ccff_tail ( grid_clb_59_ccff_tail ) , .SC_IN_TOP ( scff_Wires[107] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_589 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_590 ) ,
+ .SC_OUT_BOT ( scff_Wires[108] ) , .Test_en_E_in ( Test_enWires[273] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_591 ) ,
+ .Test_en_W_out ( Test_enWires[274] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_592 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_593 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[122] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[210] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[211] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_594 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[213] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_595 ) ,
+ .clk_0_S_in ( clk_1_wires[122] ) ) ;
+grid_clb grid_clb_6__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[55] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_596 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__48_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_60_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_60_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_60_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_60_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_60_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_60_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_60_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_60_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_60_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_60_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_60_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_60_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_60_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_60_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_60_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_60_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_60_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_60_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_60_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_60_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_60_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_60_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_60_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_60_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_60_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_60_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_60_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_60_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_60_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_60_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_60_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_60_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_597 } ) ,
+ .ccff_tail ( grid_clb_60_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_598 ) , .SC_IN_BOT ( scff_Wires[134] ) ,
+ .SC_OUT_TOP ( scff_Wires[135] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_599 ) ,
+ .Test_en_E_in ( Test_enWires[33] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_600 ) ,
+ .Test_en_W_out ( Test_enWires[34] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_601 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[90] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_602 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[215] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[216] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_603 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_604 ) ,
+ .clk_0_N_in ( clk_1_wires[90] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_605 ) ) ;
+grid_clb grid_clb_6__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[56] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_606 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__49_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_61_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_61_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_61_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_61_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_61_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_61_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_61_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_61_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_61_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_61_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_61_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_61_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_61_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_61_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_61_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_61_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_61_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_61_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_61_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_61_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_61_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_61_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_61_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_61_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_61_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_61_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_61_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_61_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_61_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_61_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_61_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_61_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[55] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_607 } ) ,
+ .ccff_tail ( grid_clb_61_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_608 ) , .SC_IN_BOT ( scff_Wires[136] ) ,
+ .SC_OUT_TOP ( scff_Wires[137] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_609 ) ,
+ .Test_en_E_in ( Test_enWires[55] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_610 ) ,
+ .Test_en_W_out ( Test_enWires[56] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_611 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_612 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[89] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[218] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[219] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_613 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_614 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_615 ) ,
+ .clk_0_S_in ( clk_1_wires[89] ) ) ;
+grid_clb grid_clb_6__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[57] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_616 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__50_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_62_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_62_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_62_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_62_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_62_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_62_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_62_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_62_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_62_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_62_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_62_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_62_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_62_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_62_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_62_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_62_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_62_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_62_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_62_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_62_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_62_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_62_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_62_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_62_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_62_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_62_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_62_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_62_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_62_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_62_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_62_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_62_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[56] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_617 } ) ,
+ .ccff_tail ( grid_clb_62_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_618 ) , .SC_IN_BOT ( scff_Wires[138] ) ,
+ .SC_OUT_TOP ( scff_Wires[139] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_619 ) ,
+ .Test_en_E_in ( Test_enWires[77] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_620 ) ,
+ .Test_en_W_out ( Test_enWires[78] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_621 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[97] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_622 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[221] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[222] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_623 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_624 ) ,
+ .clk_0_N_in ( clk_1_wires[97] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_625 ) ) ;
+grid_clb grid_clb_6__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[58] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_626 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__51_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_63_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_63_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_63_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_63_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_63_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_63_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_63_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_63_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_63_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_63_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_63_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_63_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_63_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_63_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_63_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_63_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_63_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_63_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_63_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_63_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_63_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_63_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_63_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_63_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_63_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_63_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_63_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_63_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_63_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_63_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_63_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_63_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[57] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_627 } ) ,
+ .ccff_tail ( grid_clb_63_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_628 ) , .SC_IN_BOT ( scff_Wires[140] ) ,
+ .SC_OUT_TOP ( scff_Wires[141] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_629 ) ,
+ .Test_en_E_in ( Test_enWires[99] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_630 ) ,
+ .Test_en_W_out ( Test_enWires[100] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_631 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_632 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[96] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[224] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[225] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_633 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_634 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_635 ) ,
+ .clk_0_S_in ( clk_1_wires[96] ) ) ;
+grid_clb grid_clb_6__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[59] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_636 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__52_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_64_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_64_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_64_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_64_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_64_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_64_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_64_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_64_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_64_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_64_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_64_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_64_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_64_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_64_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_64_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_64_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_64_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_64_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_64_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_64_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_64_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_64_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_64_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_64_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_64_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_64_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_64_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_64_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_64_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_64_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_64_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_64_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[58] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_637 } ) ,
+ .ccff_tail ( grid_clb_64_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_638 ) , .SC_IN_BOT ( scff_Wires[142] ) ,
+ .SC_OUT_TOP ( scff_Wires[143] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_639 ) ,
+ .Test_en_E_in ( Test_enWires[121] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_640 ) ,
+ .Test_en_W_out ( Test_enWires[122] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_641 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[104] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_642 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[227] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[228] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_643 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_644 ) ,
+ .clk_0_N_in ( clk_1_wires[104] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_645 ) ) ;
+grid_clb grid_clb_6__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[60] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_646 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__53_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_65_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_65_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_65_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_65_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_65_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_65_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_65_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_65_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_65_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_65_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_65_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_65_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_65_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_65_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_65_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_65_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_65_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_65_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_65_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_65_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_65_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_65_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_65_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_65_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_65_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_65_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_65_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_65_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_65_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_65_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_65_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_65_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[59] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_647 } ) ,
+ .ccff_tail ( grid_clb_65_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_648 ) , .SC_IN_BOT ( scff_Wires[144] ) ,
+ .SC_OUT_TOP ( scff_Wires[145] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_649 ) ,
+ .Test_en_E_in ( Test_enWires[143] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_650 ) ,
+ .Test_en_W_out ( Test_enWires[144] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_651 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_652 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[103] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[230] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[231] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_653 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_654 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_655 ) ,
+ .clk_0_S_in ( clk_1_wires[103] ) ) ;
+grid_clb grid_clb_6__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[61] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_656 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__54_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_66_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_66_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_66_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_66_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_66_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_66_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_66_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_66_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_66_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_66_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_66_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_66_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_66_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_66_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_66_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_66_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_66_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_66_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_66_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_66_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_66_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_66_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_66_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_66_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_66_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_66_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_66_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_66_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_66_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_66_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_66_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_66_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[60] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_657 } ) ,
+ .ccff_tail ( grid_clb_66_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_658 ) , .SC_IN_BOT ( scff_Wires[146] ) ,
+ .SC_OUT_TOP ( scff_Wires[147] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_659 ) ,
+ .Test_en_E_in ( Test_enWires[165] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_660 ) ,
+ .Test_en_W_out ( Test_enWires[166] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_661 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[111] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_662 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[233] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[234] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_663 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_664 ) ,
+ .clk_0_N_in ( clk_1_wires[111] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_665 ) ) ;
+grid_clb grid_clb_6__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[62] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_666 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__55_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_67_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_67_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_67_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_67_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_67_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_67_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_67_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_67_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_67_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_67_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_67_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_67_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_67_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_67_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_67_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_67_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_67_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_67_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_67_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_67_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_67_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_67_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_67_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_67_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_67_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_67_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_67_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_67_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_67_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_67_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_67_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_67_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[61] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_667 } ) ,
+ .ccff_tail ( grid_clb_67_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_668 ) , .SC_IN_BOT ( scff_Wires[148] ) ,
+ .SC_OUT_TOP ( scff_Wires[149] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_669 ) ,
+ .Test_en_E_in ( Test_enWires[187] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_670 ) ,
+ .Test_en_W_out ( Test_enWires[188] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_671 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_672 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[110] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[236] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[237] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_673 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_674 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_675 ) ,
+ .clk_0_S_in ( clk_1_wires[110] ) ) ;
+grid_clb grid_clb_6__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[63] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_676 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__56_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_68_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_68_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_68_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_68_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_68_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_68_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_68_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_68_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_68_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_68_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_68_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_68_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_68_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_68_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_68_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_68_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_68_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_68_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_68_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_68_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_68_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_68_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_68_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_68_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_68_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_68_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_68_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_68_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_68_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_68_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_68_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_68_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[62] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_677 } ) ,
+ .ccff_tail ( grid_clb_68_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_678 ) , .SC_IN_BOT ( scff_Wires[150] ) ,
+ .SC_OUT_TOP ( scff_Wires[151] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_679 ) ,
+ .Test_en_E_in ( Test_enWires[209] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_680 ) ,
+ .Test_en_W_out ( Test_enWires[210] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_681 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[118] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_682 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[239] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[240] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_683 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_684 ) ,
+ .clk_0_N_in ( clk_1_wires[118] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_685 ) ) ;
+grid_clb grid_clb_6__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[64] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_686 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__57_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_69_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_69_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_69_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_69_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_69_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_69_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_69_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_69_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_69_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_69_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_69_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_69_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_69_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_69_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_69_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_69_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_69_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_69_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_69_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_69_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_69_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_69_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_69_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_69_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_69_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_69_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_69_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_69_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_69_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_69_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_69_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_69_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[63] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_687 } ) ,
+ .ccff_tail ( grid_clb_69_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_688 ) , .SC_IN_BOT ( scff_Wires[152] ) ,
+ .SC_OUT_TOP ( scff_Wires[153] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_689 ) ,
+ .Test_en_E_in ( Test_enWires[231] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_690 ) ,
+ .Test_en_W_out ( Test_enWires[232] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_691 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_692 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[117] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[242] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[243] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_693 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_694 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_695 ) ,
+ .clk_0_S_in ( clk_1_wires[117] ) ) ;
+grid_clb grid_clb_6__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[65] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_696 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__58_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_70_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_70_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_70_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_70_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_70_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_70_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_70_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_70_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_70_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_70_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_70_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_70_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_70_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_70_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_70_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_70_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_70_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_70_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_70_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_70_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_70_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_70_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_70_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_70_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_70_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_70_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_70_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_70_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_70_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_70_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_70_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_70_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[64] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_697 } ) ,
+ .ccff_tail ( grid_clb_70_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_698 ) , .SC_IN_BOT ( scff_Wires[154] ) ,
+ .SC_OUT_TOP ( scff_Wires[155] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_699 ) ,
+ .Test_en_E_in ( Test_enWires[253] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_700 ) ,
+ .Test_en_W_out ( Test_enWires[254] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_701 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[125] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_702 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[245] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[246] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_703 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_704 ) ,
+ .clk_0_N_in ( clk_1_wires[125] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_705 ) ) ;
+grid_clb grid_clb_6__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_706 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__59_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_71_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_71_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_71_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_71_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_71_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_71_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_71_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_71_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_71_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_71_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_71_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_71_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_71_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_71_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_71_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_71_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_71_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_71_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_71_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_71_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_71_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_71_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_71_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_71_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_71_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_71_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_71_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_71_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_71_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_71_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_71_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_71_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[65] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_707 } ) ,
+ .ccff_tail ( grid_clb_71_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_708 ) , .SC_IN_BOT ( scff_Wires[156] ) ,
+ .SC_OUT_TOP ( scff_Wires[157] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_709 ) ,
+ .Test_en_E_in ( Test_enWires[275] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_710 ) ,
+ .Test_en_W_out ( Test_enWires[276] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_711 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_712 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[124] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[248] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[249] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_713 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[251] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_714 ) ,
+ .clk_0_S_in ( clk_1_wires[124] ) ) ;
+grid_clb grid_clb_7__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[66] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_715 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__60_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_72_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_72_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_72_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_72_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_72_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_72_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_72_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_72_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_72_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_72_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_72_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_72_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_72_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_72_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_72_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_72_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_72_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_72_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_72_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_72_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_72_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_72_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_72_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_72_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_72_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_72_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_72_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_72_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_72_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_72_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_72_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_72_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_716 } ) ,
+ .ccff_tail ( grid_clb_72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[182] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_717 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_718 ) ,
+ .SC_OUT_BOT ( scff_Wires[184] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_719 ) ,
+ .Test_en_W_in ( Test_enWires[35] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_720 ) ,
+ .Test_en_E_out ( Test_enWires[36] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[130] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_721 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[253] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[254] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_722 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_723 ) ,
+ .clk_0_N_in ( clk_1_wires[130] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_724 ) ) ;
+grid_clb grid_clb_7__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[67] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_725 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__61_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_73_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_73_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_73_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_73_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_73_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_73_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_73_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_73_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_73_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_73_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_73_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_73_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_73_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_73_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_73_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_73_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_73_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_73_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_73_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_73_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_73_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_73_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_73_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_73_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_73_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_73_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_73_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_73_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_73_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_73_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_73_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_73_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[66] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_726 } ) ,
+ .ccff_tail ( grid_clb_73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[180] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_727 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_728 ) ,
+ .SC_OUT_BOT ( scff_Wires[181] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_729 ) ,
+ .Test_en_W_in ( Test_enWires[57] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_730 ) ,
+ .Test_en_E_out ( Test_enWires[58] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_731 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[129] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[256] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[257] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_732 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_733 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_734 ) ,
+ .clk_0_S_in ( clk_1_wires[129] ) ) ;
+grid_clb grid_clb_7__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[68] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_735 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__62_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_74_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_74_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_74_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_74_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_74_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_74_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_74_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_74_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_74_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_74_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_74_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_74_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_74_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_74_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_74_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_74_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_74_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_74_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_74_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_74_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_74_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_74_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_74_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_74_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_74_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_74_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_74_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_74_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_74_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_74_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_74_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_74_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[67] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_736 } ) ,
+ .ccff_tail ( grid_clb_74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[178] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_737 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_738 ) ,
+ .SC_OUT_BOT ( scff_Wires[179] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_739 ) ,
+ .Test_en_W_in ( Test_enWires[79] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_740 ) ,
+ .Test_en_E_out ( Test_enWires[80] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[137] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_741 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[259] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[260] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_742 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_743 ) ,
+ .clk_0_N_in ( clk_1_wires[137] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_744 ) ) ;
+grid_clb grid_clb_7__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[69] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_745 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__63_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_75_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_75_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_75_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_75_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_75_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_75_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_75_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_75_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_75_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_75_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_75_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_75_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_75_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_75_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_75_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_75_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_75_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_75_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_75_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_75_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_75_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_75_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_75_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_75_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_75_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_75_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_75_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_75_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_75_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_75_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_75_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_75_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[68] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_746 } ) ,
+ .ccff_tail ( grid_clb_75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[176] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_747 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_748 ) ,
+ .SC_OUT_BOT ( scff_Wires[177] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_749 ) ,
+ .Test_en_W_in ( Test_enWires[101] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_750 ) ,
+ .Test_en_E_out ( Test_enWires[102] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_751 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[136] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[262] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[263] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_752 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_753 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_754 ) ,
+ .clk_0_S_in ( clk_1_wires[136] ) ) ;
+grid_clb grid_clb_7__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[70] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_755 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__64_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_76_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_76_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_76_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_76_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_76_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_76_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_76_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_76_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_76_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_76_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_76_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_76_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_76_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_76_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_76_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_76_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_76_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_76_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_76_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_76_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_76_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_76_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_76_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_76_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_76_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_76_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_76_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_76_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_76_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_76_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_76_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_76_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[69] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_756 } ) ,
+ .ccff_tail ( grid_clb_76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[174] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_757 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_758 ) ,
+ .SC_OUT_BOT ( scff_Wires[175] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_759 ) ,
+ .Test_en_W_in ( Test_enWires[123] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_760 ) ,
+ .Test_en_E_out ( Test_enWires[124] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[144] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_761 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[265] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[266] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_762 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_763 ) ,
+ .clk_0_N_in ( clk_1_wires[144] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_764 ) ) ;
+grid_clb grid_clb_7__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[71] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_765 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__65_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_77_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_77_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_77_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_77_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_77_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_77_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_77_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_77_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_77_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_77_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_77_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_77_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_77_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_77_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_77_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_77_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_77_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_77_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_77_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_77_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_77_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_77_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_77_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_77_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_77_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_77_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_77_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_77_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_77_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_77_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_77_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_77_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[70] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_766 } ) ,
+ .ccff_tail ( grid_clb_77_ccff_tail ) , .SC_IN_TOP ( scff_Wires[172] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_767 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_768 ) ,
+ .SC_OUT_BOT ( scff_Wires[173] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_769 ) ,
+ .Test_en_W_in ( Test_enWires[145] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_770 ) ,
+ .Test_en_E_out ( Test_enWires[146] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_771 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[143] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[268] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[269] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_772 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_773 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_774 ) ,
+ .clk_0_S_in ( clk_1_wires[143] ) ) ;
+grid_clb grid_clb_7__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[72] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_775 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__66_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_78_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_78_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_78_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_78_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_78_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_78_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_78_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_78_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_78_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_78_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_78_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_78_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_78_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_78_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_78_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_78_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_78_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_78_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_78_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_78_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_78_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_78_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_78_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_78_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_78_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_78_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_78_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_78_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_78_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_78_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_78_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_78_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[71] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_776 } ) ,
+ .ccff_tail ( grid_clb_78_ccff_tail ) , .SC_IN_TOP ( scff_Wires[170] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_777 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_778 ) ,
+ .SC_OUT_BOT ( scff_Wires[171] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_779 ) ,
+ .Test_en_W_in ( Test_enWires[167] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_780 ) ,
+ .Test_en_E_out ( Test_enWires[168] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[151] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_781 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[271] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[272] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_782 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_783 ) ,
+ .clk_0_N_in ( clk_1_wires[151] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_784 ) ) ;
+grid_clb grid_clb_7__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[73] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_785 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__67_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_79_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_79_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_79_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_79_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_79_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_79_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_79_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_79_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_79_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_79_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_79_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_79_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_79_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_79_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_79_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_79_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_79_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_79_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_79_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_79_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_79_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_79_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_79_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_79_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_79_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_79_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_79_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_79_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_79_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_79_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_79_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_79_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[72] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_786 } ) ,
+ .ccff_tail ( grid_clb_79_ccff_tail ) , .SC_IN_TOP ( scff_Wires[168] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_787 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_788 ) ,
+ .SC_OUT_BOT ( scff_Wires[169] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_789 ) ,
+ .Test_en_W_in ( Test_enWires[189] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_790 ) ,
+ .Test_en_E_out ( Test_enWires[190] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_791 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[150] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[274] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[275] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_792 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_793 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_794 ) ,
+ .clk_0_S_in ( clk_1_wires[150] ) ) ;
+grid_clb grid_clb_7__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[74] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_795 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__68_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_80_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_80_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_80_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_80_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_80_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_80_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_80_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_80_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_80_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_80_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_80_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_80_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_80_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_80_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_80_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_80_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_80_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_80_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_80_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_80_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_80_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_80_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_80_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_80_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_80_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_80_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_80_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_80_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_80_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_80_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_80_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_80_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[73] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_796 } ) ,
+ .ccff_tail ( grid_clb_80_ccff_tail ) , .SC_IN_TOP ( scff_Wires[166] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_797 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_798 ) ,
+ .SC_OUT_BOT ( scff_Wires[167] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_799 ) ,
+ .Test_en_W_in ( Test_enWires[211] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_800 ) ,
+ .Test_en_E_out ( Test_enWires[212] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[158] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_801 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[277] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[278] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_802 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_803 ) ,
+ .clk_0_N_in ( clk_1_wires[158] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_804 ) ) ;
+grid_clb grid_clb_7__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[75] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_805 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__69_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_81_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_81_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_81_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_81_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_81_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_81_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_81_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_81_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_81_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_81_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_81_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_81_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_81_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_81_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_81_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_81_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_81_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_81_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_81_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_81_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_81_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_81_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_81_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_81_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_81_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_81_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_81_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_81_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_81_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_81_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_81_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_81_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[74] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_806 } ) ,
+ .ccff_tail ( grid_clb_81_ccff_tail ) , .SC_IN_TOP ( scff_Wires[164] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_807 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_808 ) ,
+ .SC_OUT_BOT ( scff_Wires[165] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_809 ) ,
+ .Test_en_W_in ( Test_enWires[233] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_810 ) ,
+ .Test_en_E_out ( Test_enWires[234] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_811 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[157] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[280] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[281] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_812 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_813 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_814 ) ,
+ .clk_0_S_in ( clk_1_wires[157] ) ) ;
+grid_clb grid_clb_7__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[76] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_815 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__70_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_82_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_82_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_82_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_82_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_82_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_82_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_82_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_82_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_82_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_82_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_82_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_82_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_82_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_82_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_82_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_82_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_82_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_82_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_82_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_82_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_82_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_82_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_82_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_82_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_82_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_82_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_82_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_82_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_82_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_82_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_82_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_82_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[75] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_816 } ) ,
+ .ccff_tail ( grid_clb_82_ccff_tail ) , .SC_IN_TOP ( scff_Wires[162] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_817 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_818 ) ,
+ .SC_OUT_BOT ( scff_Wires[163] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_819 ) ,
+ .Test_en_W_in ( Test_enWires[255] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_820 ) ,
+ .Test_en_E_out ( Test_enWires[256] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[165] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_821 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[283] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[284] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_822 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_823 ) ,
+ .clk_0_N_in ( clk_1_wires[165] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_824 ) ) ;
+grid_clb grid_clb_7__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_825 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__71_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_83_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_83_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_83_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_83_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_83_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_83_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_83_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_83_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_83_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_83_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_83_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_83_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_83_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_83_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_83_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_83_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_83_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_83_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_83_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_83_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_83_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_83_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_83_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_83_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_83_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_83_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_83_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_83_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_83_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_83_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_83_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_83_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[76] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_826 } ) ,
+ .ccff_tail ( grid_clb_83_ccff_tail ) , .SC_IN_TOP ( scff_Wires[160] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_827 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_828 ) ,
+ .SC_OUT_BOT ( scff_Wires[161] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_829 ) ,
+ .Test_en_W_in ( Test_enWires[277] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_830 ) ,
+ .Test_en_E_out ( Test_enWires[278] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_831 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[164] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[286] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[287] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_832 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[289] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_833 ) ,
+ .clk_0_S_in ( clk_1_wires[164] ) ) ;
+grid_clb grid_clb_8__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[77] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_834 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__72_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_84_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_84_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_84_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_84_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_84_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_84_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_84_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_84_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_84_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_84_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_84_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_84_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_84_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_84_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_84_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_84_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_84_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_84_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_84_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_84_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_84_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_84_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_84_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_84_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_84_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_84_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_84_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_84_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_84_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_84_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_84_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_84_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_835 } ) ,
+ .ccff_tail ( grid_clb_84_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_836 ) , .SC_IN_BOT ( scff_Wires[187] ) ,
+ .SC_OUT_TOP ( scff_Wires[188] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_837 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_838 ) ,
+ .Test_en_W_in ( Test_enWires[37] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_839 ) ,
+ .Test_en_E_out ( Test_enWires[38] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[132] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_840 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[291] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[292] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_841 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_842 ) ,
+ .clk_0_N_in ( clk_1_wires[132] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_843 ) ) ;
+grid_clb grid_clb_8__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[78] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_844 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__73_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_85_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_85_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_85_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_85_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_85_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_85_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_85_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_85_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_85_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_85_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_85_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_85_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_85_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_85_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_85_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_85_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_85_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_85_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_85_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_85_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_85_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_85_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_85_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_85_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_85_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_85_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_85_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_85_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_85_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_85_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_85_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_85_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[77] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_845 } ) ,
+ .ccff_tail ( grid_clb_85_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_846 ) , .SC_IN_BOT ( scff_Wires[189] ) ,
+ .SC_OUT_TOP ( scff_Wires[190] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_847 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_848 ) ,
+ .Test_en_W_in ( Test_enWires[59] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_849 ) ,
+ .Test_en_E_out ( Test_enWires[60] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_850 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[131] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[294] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[295] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_851 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_852 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_853 ) ,
+ .clk_0_S_in ( clk_1_wires[131] ) ) ;
+grid_clb grid_clb_8__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[79] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_854 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__74_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_86_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_86_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_86_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_86_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_86_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_86_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_86_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_86_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_86_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_86_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_86_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_86_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_86_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_86_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_86_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_86_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_86_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_86_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_86_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_86_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_86_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_86_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_86_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_86_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_86_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_86_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_86_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_86_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_86_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_86_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_86_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_86_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[78] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_855 } ) ,
+ .ccff_tail ( grid_clb_86_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_856 ) , .SC_IN_BOT ( scff_Wires[191] ) ,
+ .SC_OUT_TOP ( scff_Wires[192] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_857 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_858 ) ,
+ .Test_en_W_in ( Test_enWires[81] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_859 ) ,
+ .Test_en_E_out ( Test_enWires[82] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[139] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_860 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[297] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[298] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_861 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_862 ) ,
+ .clk_0_N_in ( clk_1_wires[139] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_863 ) ) ;
+grid_clb grid_clb_8__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[80] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_864 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__75_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_87_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_87_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_87_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_87_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_87_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_87_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_87_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_87_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_87_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_87_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_87_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_87_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_87_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_87_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_87_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_87_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_87_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_87_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_87_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_87_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_87_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_87_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_87_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_87_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_87_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_87_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_87_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_87_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_87_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_87_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_87_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_87_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[79] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_865 } ) ,
+ .ccff_tail ( grid_clb_87_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_866 ) , .SC_IN_BOT ( scff_Wires[193] ) ,
+ .SC_OUT_TOP ( scff_Wires[194] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_867 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_868 ) ,
+ .Test_en_W_in ( Test_enWires[103] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_869 ) ,
+ .Test_en_E_out ( Test_enWires[104] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_870 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[138] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[300] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[301] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_871 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_872 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_873 ) ,
+ .clk_0_S_in ( clk_1_wires[138] ) ) ;
+grid_clb grid_clb_8__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[81] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_874 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__76_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_88_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_88_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_88_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_88_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_88_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_88_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_88_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_88_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_88_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_88_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_88_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_88_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_88_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_88_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_88_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_88_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_88_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_88_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_88_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_88_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_88_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_88_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_88_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_88_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_88_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_88_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_88_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_88_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_88_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_88_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_88_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_88_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[80] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_875 } ) ,
+ .ccff_tail ( grid_clb_88_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_876 ) , .SC_IN_BOT ( scff_Wires[195] ) ,
+ .SC_OUT_TOP ( scff_Wires[196] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_877 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_878 ) ,
+ .Test_en_W_in ( Test_enWires[125] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_879 ) ,
+ .Test_en_E_out ( Test_enWires[126] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[146] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_880 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[303] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[304] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_881 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_882 ) ,
+ .clk_0_N_in ( clk_1_wires[146] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_883 ) ) ;
+grid_clb grid_clb_8__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[82] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_884 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__77_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_89_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_89_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_89_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_89_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_89_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_89_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_89_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_89_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_89_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_89_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_89_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_89_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_89_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_89_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_89_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_89_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_89_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_89_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_89_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_89_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_89_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_89_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_89_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_89_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_89_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_89_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_89_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_89_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_89_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_89_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_89_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_89_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[81] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_885 } ) ,
+ .ccff_tail ( grid_clb_89_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_886 ) , .SC_IN_BOT ( scff_Wires[197] ) ,
+ .SC_OUT_TOP ( scff_Wires[198] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_887 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_888 ) ,
+ .Test_en_W_in ( Test_enWires[147] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_889 ) ,
+ .Test_en_E_out ( Test_enWires[148] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_890 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[145] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[306] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[307] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_891 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_892 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_893 ) ,
+ .clk_0_S_in ( clk_1_wires[145] ) ) ;
+grid_clb grid_clb_8__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[83] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_894 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__78_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_90_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_90_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_90_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_90_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_90_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_90_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_90_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_90_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_90_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_90_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_90_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_90_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_90_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_90_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_90_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_90_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_90_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_90_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_90_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_90_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_90_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_90_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_90_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_90_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_90_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_90_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_90_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_90_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_90_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_90_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_90_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_90_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[82] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_895 } ) ,
+ .ccff_tail ( grid_clb_90_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_896 ) , .SC_IN_BOT ( scff_Wires[199] ) ,
+ .SC_OUT_TOP ( scff_Wires[200] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_897 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_898 ) ,
+ .Test_en_W_in ( Test_enWires[169] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_899 ) ,
+ .Test_en_E_out ( Test_enWires[170] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[153] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_900 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[309] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[310] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_901 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_902 ) ,
+ .clk_0_N_in ( clk_1_wires[153] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_903 ) ) ;
+grid_clb grid_clb_8__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[84] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_904 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__79_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_91_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_91_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_91_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_91_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_91_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_91_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_91_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_91_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_91_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_91_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_91_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_91_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_91_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_91_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_91_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_91_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_91_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_91_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_91_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_91_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_91_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_91_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_91_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_91_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_91_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_91_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_91_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_91_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_91_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_91_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_91_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_91_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[83] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_905 } ) ,
+ .ccff_tail ( grid_clb_91_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_906 ) , .SC_IN_BOT ( scff_Wires[201] ) ,
+ .SC_OUT_TOP ( scff_Wires[202] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_907 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_908 ) ,
+ .Test_en_W_in ( Test_enWires[191] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_909 ) ,
+ .Test_en_E_out ( Test_enWires[192] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_910 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[152] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[312] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[313] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_911 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_912 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_913 ) ,
+ .clk_0_S_in ( clk_1_wires[152] ) ) ;
+grid_clb grid_clb_8__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[85] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_914 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__80_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_92_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_92_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_92_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_92_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_92_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_92_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_92_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_92_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_92_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_92_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_92_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_92_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_92_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_92_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_92_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_92_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_92_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_92_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_92_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_92_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_92_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_92_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_92_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_92_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_92_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_92_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_92_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_92_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_92_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_92_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_92_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_92_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[84] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_915 } ) ,
+ .ccff_tail ( grid_clb_92_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_916 ) , .SC_IN_BOT ( scff_Wires[203] ) ,
+ .SC_OUT_TOP ( scff_Wires[204] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_917 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_918 ) ,
+ .Test_en_W_in ( Test_enWires[213] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_919 ) ,
+ .Test_en_E_out ( Test_enWires[214] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[160] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_920 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[315] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[316] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_921 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_922 ) ,
+ .clk_0_N_in ( clk_1_wires[160] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_923 ) ) ;
+grid_clb grid_clb_8__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[86] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_924 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__81_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_93_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_93_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_93_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_93_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_93_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_93_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_93_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_93_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_93_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_93_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_93_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_93_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_93_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_93_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_93_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_93_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_93_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_93_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_93_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_93_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_93_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_93_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_93_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_93_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_93_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_93_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_93_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_93_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_93_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_93_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_93_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_93_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[85] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_925 } ) ,
+ .ccff_tail ( grid_clb_93_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_926 ) , .SC_IN_BOT ( scff_Wires[205] ) ,
+ .SC_OUT_TOP ( scff_Wires[206] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_927 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_928 ) ,
+ .Test_en_W_in ( Test_enWires[235] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_929 ) ,
+ .Test_en_E_out ( Test_enWires[236] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_930 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[159] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[318] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[319] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_931 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_932 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_933 ) ,
+ .clk_0_S_in ( clk_1_wires[159] ) ) ;
+grid_clb grid_clb_8__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[87] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_934 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__82_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_94_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_94_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_94_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_94_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_94_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_94_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_94_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_94_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_94_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_94_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_94_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_94_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_94_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_94_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_94_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_94_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_94_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_94_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_94_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_94_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_94_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_94_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_94_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_94_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_94_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_94_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_94_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_94_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_94_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_94_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_94_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_94_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[86] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_935 } ) ,
+ .ccff_tail ( grid_clb_94_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_936 ) , .SC_IN_BOT ( scff_Wires[207] ) ,
+ .SC_OUT_TOP ( scff_Wires[208] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_937 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_938 ) ,
+ .Test_en_W_in ( Test_enWires[257] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_939 ) ,
+ .Test_en_E_out ( Test_enWires[258] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[167] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_940 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[321] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[322] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_941 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_942 ) ,
+ .clk_0_N_in ( clk_1_wires[167] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_943 ) ) ;
+grid_clb grid_clb_8__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_944 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__83_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_95_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_95_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_95_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_95_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_95_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_95_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_95_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_95_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_95_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_95_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_95_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_95_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_95_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_95_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_95_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_95_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_95_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_95_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_95_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_95_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_95_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_95_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_95_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_95_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_95_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_95_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_95_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_95_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_95_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_95_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_95_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_95_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[87] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_945 } ) ,
+ .ccff_tail ( grid_clb_95_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_946 ) , .SC_IN_BOT ( scff_Wires[209] ) ,
+ .SC_OUT_TOP ( scff_Wires[210] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_947 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_948 ) ,
+ .Test_en_W_in ( Test_enWires[279] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_949 ) ,
+ .Test_en_E_out ( Test_enWires[280] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_950 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[166] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[324] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[325] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_951 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[327] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_952 ) ,
+ .clk_0_S_in ( clk_1_wires[166] ) ) ;
+grid_clb grid_clb_9__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[88] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_953 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__84_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_96_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_96_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_96_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_96_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_96_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_96_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_96_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_96_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_96_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_96_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_96_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_96_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_96_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_96_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_96_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_96_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_96_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_96_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_96_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_96_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_96_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_96_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_96_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_96_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_96_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_96_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_96_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_96_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_96_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_96_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_96_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_96_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_954 } ) ,
+ .ccff_tail ( grid_clb_96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[235] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_955 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_956 ) ,
+ .SC_OUT_BOT ( scff_Wires[237] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_957 ) ,
+ .Test_en_W_in ( Test_enWires[39] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_958 ) ,
+ .Test_en_E_out ( Test_enWires[40] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[172] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_959 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[329] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[330] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_960 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_961 ) ,
+ .clk_0_N_in ( clk_1_wires[172] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_962 ) ) ;
+grid_clb grid_clb_9__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[89] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_963 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__85_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_97_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_97_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_97_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_97_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_97_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_97_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_97_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_97_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_97_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_97_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_97_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_97_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_97_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_97_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_97_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_97_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_97_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_97_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_97_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_97_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_97_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_97_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_97_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_97_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_97_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_97_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_97_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_97_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_97_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_97_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_97_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_97_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[88] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_964 } ) ,
+ .ccff_tail ( grid_clb_97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[233] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_965 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_966 ) ,
+ .SC_OUT_BOT ( scff_Wires[234] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_967 ) ,
+ .Test_en_W_in ( Test_enWires[61] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_968 ) ,
+ .Test_en_E_out ( Test_enWires[62] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_969 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[171] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[332] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[333] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_970 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_971 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_972 ) ,
+ .clk_0_S_in ( clk_1_wires[171] ) ) ;
+grid_clb grid_clb_9__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[90] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_973 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__86_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_98_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_98_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_98_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_98_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_98_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_98_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_98_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_98_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_98_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_98_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_98_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_98_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_98_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_98_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_98_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_98_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_98_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_98_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_98_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_98_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_98_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_98_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_98_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_98_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_98_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_98_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_98_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_98_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_98_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_98_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_98_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_98_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[89] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_974 } ) ,
+ .ccff_tail ( grid_clb_98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[231] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_975 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_976 ) ,
+ .SC_OUT_BOT ( scff_Wires[232] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_977 ) ,
+ .Test_en_W_in ( Test_enWires[83] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_978 ) ,
+ .Test_en_E_out ( Test_enWires[84] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[179] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_979 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[335] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[336] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_980 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_981 ) ,
+ .clk_0_N_in ( clk_1_wires[179] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_982 ) ) ;
+grid_clb grid_clb_9__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[91] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_983 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__87_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_99_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_99_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_99_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_99_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_99_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_99_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_99_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_99_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_99_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_99_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_99_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_99_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_99_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_99_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_99_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_99_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_99_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_99_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_99_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_99_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_99_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_99_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_99_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_99_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_99_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_99_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_99_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_99_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_99_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_99_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_99_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_99_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[90] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_984 } ) ,
+ .ccff_tail ( grid_clb_99_ccff_tail ) , .SC_IN_TOP ( scff_Wires[229] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_985 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_986 ) ,
+ .SC_OUT_BOT ( scff_Wires[230] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_987 ) ,
+ .Test_en_W_in ( Test_enWires[105] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_988 ) ,
+ .Test_en_E_out ( Test_enWires[106] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_989 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[178] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[338] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[339] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_990 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_991 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_992 ) ,
+ .clk_0_S_in ( clk_1_wires[178] ) ) ;
+grid_clb grid_clb_9__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[92] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_993 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__88_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_100_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_100_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_100_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_100_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_100_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_100_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_100_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_100_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_100_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_100_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_100_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_100_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_100_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_100_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_100_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_100_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_100_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_100_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_100_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_100_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_100_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_100_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_100_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_100_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_100_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_100_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_100_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_100_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_100_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_100_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_100_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_100_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[91] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_994 } ) ,
+ .ccff_tail ( grid_clb_100_ccff_tail ) , .SC_IN_TOP ( scff_Wires[227] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_995 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_996 ) ,
+ .SC_OUT_BOT ( scff_Wires[228] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_997 ) ,
+ .Test_en_W_in ( Test_enWires[127] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_998 ) ,
+ .Test_en_E_out ( Test_enWires[128] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[186] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_999 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[341] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[342] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1000 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1001 ) ,
+ .clk_0_N_in ( clk_1_wires[186] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1002 ) ) ;
+grid_clb grid_clb_9__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[93] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1003 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__89_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_101_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_101_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_101_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_101_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_101_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_101_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_101_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_101_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_101_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_101_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_101_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_101_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_101_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_101_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_101_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_101_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_101_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_101_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_101_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_101_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_101_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_101_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_101_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_101_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_101_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_101_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_101_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_101_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_101_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_101_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_101_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_101_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[92] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1004 } ) ,
+ .ccff_tail ( grid_clb_101_ccff_tail ) , .SC_IN_TOP ( scff_Wires[225] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1005 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1006 ) ,
+ .SC_OUT_BOT ( scff_Wires[226] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1007 ) ,
+ .Test_en_W_in ( Test_enWires[149] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1008 ) ,
+ .Test_en_E_out ( Test_enWires[150] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1009 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[185] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[344] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[345] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1010 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1011 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1012 ) ,
+ .clk_0_S_in ( clk_1_wires[185] ) ) ;
+grid_clb grid_clb_9__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[94] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1013 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__90_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_102_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_102_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_102_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_102_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_102_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_102_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_102_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_102_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_102_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_102_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_102_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_102_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_102_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_102_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_102_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_102_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_102_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_102_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_102_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_102_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_102_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_102_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_102_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_102_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_102_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_102_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_102_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_102_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_102_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_102_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_102_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_102_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[93] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1014 } ) ,
+ .ccff_tail ( grid_clb_102_ccff_tail ) , .SC_IN_TOP ( scff_Wires[223] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1015 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1016 ) ,
+ .SC_OUT_BOT ( scff_Wires[224] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1017 ) ,
+ .Test_en_W_in ( Test_enWires[171] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1018 ) ,
+ .Test_en_E_out ( Test_enWires[172] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[193] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1019 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[347] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[348] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1020 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1021 ) ,
+ .clk_0_N_in ( clk_1_wires[193] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1022 ) ) ;
+grid_clb grid_clb_9__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[95] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1023 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__91_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_103_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_103_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_103_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_103_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_103_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_103_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_103_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_103_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_103_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_103_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_103_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_103_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_103_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_103_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_103_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_103_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_103_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_103_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_103_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_103_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_103_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_103_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_103_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_103_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_103_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_103_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_103_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_103_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_103_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_103_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_103_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_103_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[94] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1024 } ) ,
+ .ccff_tail ( grid_clb_103_ccff_tail ) , .SC_IN_TOP ( scff_Wires[221] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1025 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1026 ) ,
+ .SC_OUT_BOT ( scff_Wires[222] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1027 ) ,
+ .Test_en_W_in ( Test_enWires[193] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1028 ) ,
+ .Test_en_E_out ( Test_enWires[194] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1029 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[192] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[350] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[351] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1030 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1031 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1032 ) ,
+ .clk_0_S_in ( clk_1_wires[192] ) ) ;
+grid_clb grid_clb_9__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[96] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1033 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__92_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_104_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_104_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_104_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_104_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_104_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_104_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_104_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_104_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_104_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_104_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_104_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_104_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_104_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_104_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_104_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_104_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_104_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_104_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_104_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_104_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_104_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_104_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_104_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_104_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_104_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_104_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_104_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_104_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_104_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_104_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_104_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_104_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[95] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1034 } ) ,
+ .ccff_tail ( grid_clb_104_ccff_tail ) , .SC_IN_TOP ( scff_Wires[219] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1035 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1036 ) ,
+ .SC_OUT_BOT ( scff_Wires[220] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1037 ) ,
+ .Test_en_W_in ( Test_enWires[215] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1038 ) ,
+ .Test_en_E_out ( Test_enWires[216] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[200] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1039 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[353] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[354] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1040 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1041 ) ,
+ .clk_0_N_in ( clk_1_wires[200] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1042 ) ) ;
+grid_clb grid_clb_9__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[97] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1043 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__93_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_105_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_105_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_105_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_105_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_105_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_105_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_105_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_105_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_105_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_105_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_105_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_105_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_105_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_105_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_105_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_105_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_105_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_105_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_105_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_105_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_105_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_105_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_105_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_105_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_105_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_105_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_105_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_105_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_105_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_105_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_105_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_105_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[96] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1044 } ) ,
+ .ccff_tail ( grid_clb_105_ccff_tail ) , .SC_IN_TOP ( scff_Wires[217] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1045 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1046 ) ,
+ .SC_OUT_BOT ( scff_Wires[218] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1047 ) ,
+ .Test_en_W_in ( Test_enWires[237] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1048 ) ,
+ .Test_en_E_out ( Test_enWires[238] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1049 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[199] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[356] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[357] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1050 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1051 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1052 ) ,
+ .clk_0_S_in ( clk_1_wires[199] ) ) ;
+grid_clb grid_clb_9__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[98] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1053 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__94_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_106_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_106_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_106_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_106_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_106_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_106_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_106_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_106_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_106_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_106_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_106_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_106_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_106_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_106_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_106_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_106_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_106_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_106_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_106_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_106_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_106_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_106_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_106_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_106_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_106_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_106_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_106_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_106_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_106_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_106_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_106_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_106_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[97] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1054 } ) ,
+ .ccff_tail ( grid_clb_106_ccff_tail ) , .SC_IN_TOP ( scff_Wires[215] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1055 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1056 ) ,
+ .SC_OUT_BOT ( scff_Wires[216] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1057 ) ,
+ .Test_en_W_in ( Test_enWires[259] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1058 ) ,
+ .Test_en_E_out ( Test_enWires[260] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[207] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1059 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[359] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[360] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1060 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1061 ) ,
+ .clk_0_N_in ( clk_1_wires[207] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1062 ) ) ;
+grid_clb grid_clb_9__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1063 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__95_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_107_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_107_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_107_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_107_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_107_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_107_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_107_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_107_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_107_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_107_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_107_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_107_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_107_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_107_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_107_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_107_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_107_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_107_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_107_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_107_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_107_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_107_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_107_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_107_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_107_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_107_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_107_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_107_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_107_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_107_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_107_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_107_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[98] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1064 } ) ,
+ .ccff_tail ( grid_clb_107_ccff_tail ) , .SC_IN_TOP ( scff_Wires[213] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1065 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1066 ) ,
+ .SC_OUT_BOT ( scff_Wires[214] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1067 ) ,
+ .Test_en_W_in ( Test_enWires[281] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1068 ) ,
+ .Test_en_E_out ( Test_enWires[282] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1069 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[206] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[362] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[363] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1070 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[365] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1071 ) ,
+ .clk_0_S_in ( clk_1_wires[206] ) ) ;
+grid_clb grid_clb_10__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[99] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1072 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__96_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_108_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_108_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_108_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_108_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_108_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_108_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_108_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_108_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_108_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_108_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_108_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_108_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_108_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_108_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_108_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_108_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_108_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_108_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_108_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_108_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_108_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_108_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_108_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_108_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_108_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_108_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_108_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_108_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_108_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_108_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_108_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_108_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1073 } ) ,
+ .ccff_tail ( grid_clb_108_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1074 ) ,
+ .SC_IN_BOT ( scff_Wires[240] ) , .SC_OUT_TOP ( scff_Wires[241] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1075 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1076 ) ,
+ .Test_en_W_in ( Test_enWires[41] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1077 ) ,
+ .Test_en_E_out ( Test_enWires[42] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[174] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1078 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[367] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[368] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1079 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1080 ) ,
+ .clk_0_N_in ( clk_1_wires[174] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1081 ) ) ;
+grid_clb grid_clb_10__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[100] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1082 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__97_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_109_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_109_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_109_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_109_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_109_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_109_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_109_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_109_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_109_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_109_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_109_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_109_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_109_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_109_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_109_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_109_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_109_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_109_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_109_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_109_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_109_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_109_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_109_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_109_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_109_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_109_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_109_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_109_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_109_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_109_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_109_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_109_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[99] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1083 } ) ,
+ .ccff_tail ( grid_clb_109_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1084 ) ,
+ .SC_IN_BOT ( scff_Wires[242] ) , .SC_OUT_TOP ( scff_Wires[243] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1085 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1086 ) ,
+ .Test_en_W_in ( Test_enWires[63] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1087 ) ,
+ .Test_en_E_out ( Test_enWires[64] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1088 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[173] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[370] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[371] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1089 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1090 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1091 ) ,
+ .clk_0_S_in ( clk_1_wires[173] ) ) ;
+grid_clb grid_clb_10__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[101] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1092 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__98_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_110_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_110_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_110_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_110_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_110_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_110_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_110_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_110_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_110_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_110_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_110_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_110_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_110_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_110_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_110_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_110_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_110_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_110_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_110_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_110_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_110_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_110_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_110_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_110_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_110_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_110_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_110_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_110_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_110_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_110_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_110_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_110_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[100] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1093 } ) ,
+ .ccff_tail ( grid_clb_110_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1094 ) ,
+ .SC_IN_BOT ( scff_Wires[244] ) , .SC_OUT_TOP ( scff_Wires[245] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1095 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1096 ) ,
+ .Test_en_W_in ( Test_enWires[85] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1097 ) ,
+ .Test_en_E_out ( Test_enWires[86] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[181] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1098 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[373] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[374] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1099 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1100 ) ,
+ .clk_0_N_in ( clk_1_wires[181] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1101 ) ) ;
+grid_clb grid_clb_10__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[102] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1102 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__99_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_111_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_111_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_111_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_111_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_111_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_111_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_111_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_111_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_111_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_111_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_111_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_111_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_111_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_111_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_111_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_111_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_111_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_111_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_111_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_111_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_111_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_111_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_111_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_111_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_111_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_111_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_111_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_111_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_111_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_111_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_111_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_111_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[101] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1103 } ) ,
+ .ccff_tail ( grid_clb_111_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1104 ) ,
+ .SC_IN_BOT ( scff_Wires[246] ) , .SC_OUT_TOP ( scff_Wires[247] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1105 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1106 ) ,
+ .Test_en_W_in ( Test_enWires[107] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1107 ) ,
+ .Test_en_E_out ( Test_enWires[108] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1108 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[180] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[376] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[377] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1109 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1110 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1111 ) ,
+ .clk_0_S_in ( clk_1_wires[180] ) ) ;
+grid_clb grid_clb_10__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[103] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1112 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__100_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_112_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_112_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_112_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_112_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_112_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_112_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_112_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_112_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_112_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_112_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_112_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_112_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_112_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_112_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_112_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_112_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_112_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_112_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_112_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_112_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_112_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_112_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_112_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_112_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_112_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_112_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_112_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_112_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_112_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_112_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_112_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_112_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[102] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1113 } ) ,
+ .ccff_tail ( grid_clb_112_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1114 ) ,
+ .SC_IN_BOT ( scff_Wires[248] ) , .SC_OUT_TOP ( scff_Wires[249] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1115 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1116 ) ,
+ .Test_en_W_in ( Test_enWires[129] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1117 ) ,
+ .Test_en_E_out ( Test_enWires[130] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[188] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1118 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[379] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[380] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1119 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1120 ) ,
+ .clk_0_N_in ( clk_1_wires[188] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1121 ) ) ;
+grid_clb grid_clb_10__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[104] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1122 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__101_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_113_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_113_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_113_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_113_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_113_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_113_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_113_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_113_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_113_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_113_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_113_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_113_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_113_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_113_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_113_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_113_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_113_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_113_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_113_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_113_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_113_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_113_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_113_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_113_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_113_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_113_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_113_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_113_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_113_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_113_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_113_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_113_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[103] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1123 } ) ,
+ .ccff_tail ( grid_clb_113_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1124 ) ,
+ .SC_IN_BOT ( scff_Wires[250] ) , .SC_OUT_TOP ( scff_Wires[251] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1125 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1126 ) ,
+ .Test_en_W_in ( Test_enWires[151] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1127 ) ,
+ .Test_en_E_out ( Test_enWires[152] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1128 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[187] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[382] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[383] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1129 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1130 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1131 ) ,
+ .clk_0_S_in ( clk_1_wires[187] ) ) ;
+grid_clb grid_clb_10__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[105] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1132 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__102_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_114_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_114_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_114_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_114_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_114_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_114_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_114_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_114_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_114_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_114_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_114_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_114_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_114_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_114_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_114_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_114_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_114_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_114_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_114_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_114_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_114_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_114_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_114_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_114_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_114_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_114_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_114_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_114_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_114_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_114_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_114_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_114_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[104] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1133 } ) ,
+ .ccff_tail ( grid_clb_114_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1134 ) ,
+ .SC_IN_BOT ( scff_Wires[252] ) , .SC_OUT_TOP ( scff_Wires[253] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1135 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1136 ) ,
+ .Test_en_W_in ( Test_enWires[173] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1137 ) ,
+ .Test_en_E_out ( Test_enWires[174] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[195] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1138 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[385] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[386] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1139 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1140 ) ,
+ .clk_0_N_in ( clk_1_wires[195] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1141 ) ) ;
+grid_clb grid_clb_10__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[106] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1142 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__103_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_115_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_115_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_115_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_115_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_115_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_115_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_115_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_115_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_115_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_115_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_115_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_115_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_115_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_115_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_115_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_115_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_115_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_115_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_115_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_115_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_115_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_115_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_115_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_115_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_115_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_115_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_115_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_115_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_115_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_115_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_115_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_115_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[105] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1143 } ) ,
+ .ccff_tail ( grid_clb_115_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1144 ) ,
+ .SC_IN_BOT ( scff_Wires[254] ) , .SC_OUT_TOP ( scff_Wires[255] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1145 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1146 ) ,
+ .Test_en_W_in ( Test_enWires[195] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1147 ) ,
+ .Test_en_E_out ( Test_enWires[196] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1148 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[194] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[388] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[389] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1149 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1150 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1151 ) ,
+ .clk_0_S_in ( clk_1_wires[194] ) ) ;
+grid_clb grid_clb_10__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[107] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1152 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__104_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_116_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_116_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_116_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_116_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_116_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_116_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_116_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_116_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_116_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_116_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_116_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_116_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_116_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_116_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_116_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_116_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_116_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_116_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_116_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_116_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_116_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_116_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_116_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_116_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_116_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_116_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_116_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_116_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_116_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_116_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_116_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_116_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[106] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1153 } ) ,
+ .ccff_tail ( grid_clb_116_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1154 ) ,
+ .SC_IN_BOT ( scff_Wires[256] ) , .SC_OUT_TOP ( scff_Wires[257] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1155 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1156 ) ,
+ .Test_en_W_in ( Test_enWires[217] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1157 ) ,
+ .Test_en_E_out ( Test_enWires[218] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[202] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1158 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[391] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[392] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1159 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1160 ) ,
+ .clk_0_N_in ( clk_1_wires[202] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1161 ) ) ;
+grid_clb grid_clb_10__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[108] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1162 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__105_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_117_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_117_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_117_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_117_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_117_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_117_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_117_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_117_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_117_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_117_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_117_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_117_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_117_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_117_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_117_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_117_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_117_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_117_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_117_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_117_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_117_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_117_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_117_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_117_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_117_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_117_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_117_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_117_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_117_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_117_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_117_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_117_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[107] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1163 } ) ,
+ .ccff_tail ( grid_clb_117_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1164 ) ,
+ .SC_IN_BOT ( scff_Wires[258] ) , .SC_OUT_TOP ( scff_Wires[259] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1165 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1166 ) ,
+ .Test_en_W_in ( Test_enWires[239] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1167 ) ,
+ .Test_en_E_out ( Test_enWires[240] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1168 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[201] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[394] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[395] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1169 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1170 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1171 ) ,
+ .clk_0_S_in ( clk_1_wires[201] ) ) ;
+grid_clb grid_clb_10__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[109] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1172 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__106_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_118_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_118_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_118_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_118_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_118_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_118_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_118_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_118_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_118_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_118_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_118_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_118_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_118_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_118_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_118_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_118_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_118_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_118_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_118_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_118_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_118_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_118_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_118_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_118_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_118_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_118_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_118_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_118_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_118_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_118_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_118_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_118_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[108] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1173 } ) ,
+ .ccff_tail ( grid_clb_118_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1174 ) ,
+ .SC_IN_BOT ( scff_Wires[260] ) , .SC_OUT_TOP ( scff_Wires[261] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1175 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1176 ) ,
+ .Test_en_W_in ( Test_enWires[261] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1177 ) ,
+ .Test_en_E_out ( Test_enWires[262] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[209] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1178 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[397] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[398] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1179 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1180 ) ,
+ .clk_0_N_in ( clk_1_wires[209] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1181 ) ) ;
+grid_clb grid_clb_10__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1182 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__107_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_119_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_119_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_119_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_119_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_119_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_119_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_119_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_119_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_119_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_119_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_119_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_119_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_119_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_119_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_119_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_119_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_119_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_119_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_119_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_119_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_119_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_119_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_119_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_119_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_119_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_119_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_119_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_119_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_119_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_119_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_119_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_119_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[109] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1183 } ) ,
+ .ccff_tail ( grid_clb_119_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1184 ) ,
+ .SC_IN_BOT ( scff_Wires[262] ) , .SC_OUT_TOP ( scff_Wires[263] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1185 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1186 ) ,
+ .Test_en_W_in ( Test_enWires[283] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1187 ) ,
+ .Test_en_E_out ( Test_enWires[284] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1188 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[208] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[400] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[401] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1189 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[403] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1190 ) ,
+ .clk_0_S_in ( clk_1_wires[208] ) ) ;
+grid_clb grid_clb_11__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[110] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1191 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__108_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_120_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_120_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_120_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_120_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_120_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_120_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_120_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_120_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_120_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_120_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_120_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_120_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_120_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_120_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_120_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_120_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_120_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_120_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_120_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_120_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_120_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_120_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_120_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_120_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_120_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_120_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_120_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_120_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_120_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_120_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_120_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_120_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1192 } ) ,
+ .ccff_tail ( grid_clb_120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[288] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1193 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1194 ) ,
+ .SC_OUT_BOT ( scff_Wires[290] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1195 ) ,
+ .Test_en_W_in ( Test_enWires[43] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1196 ) ,
+ .Test_en_E_out ( Test_enWires[44] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[214] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1197 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[405] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[406] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1198 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1199 ) ,
+ .clk_0_N_in ( clk_1_wires[214] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1200 ) ) ;
+grid_clb grid_clb_11__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[111] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1201 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__109_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_121_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_121_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_121_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_121_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_121_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_121_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_121_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_121_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_121_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_121_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_121_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_121_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_121_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_121_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_121_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_121_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_121_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_121_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_121_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_121_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_121_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_121_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_121_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_121_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_121_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_121_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_121_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_121_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_121_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_121_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_121_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_121_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[110] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1202 } ) ,
+ .ccff_tail ( grid_clb_121_ccff_tail ) , .SC_IN_TOP ( scff_Wires[286] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1203 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1204 ) ,
+ .SC_OUT_BOT ( scff_Wires[287] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1205 ) ,
+ .Test_en_W_in ( Test_enWires[65] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1206 ) ,
+ .Test_en_E_out ( Test_enWires[66] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1207 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[213] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[408] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[409] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1208 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1209 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1210 ) ,
+ .clk_0_S_in ( clk_1_wires[213] ) ) ;
+grid_clb grid_clb_11__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[112] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1211 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__110_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_122_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_122_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_122_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_122_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_122_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_122_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_122_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_122_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_122_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_122_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_122_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_122_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_122_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_122_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_122_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_122_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_122_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_122_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_122_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_122_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_122_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_122_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_122_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_122_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_122_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_122_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_122_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_122_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_122_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_122_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_122_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_122_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[111] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1212 } ) ,
+ .ccff_tail ( grid_clb_122_ccff_tail ) , .SC_IN_TOP ( scff_Wires[284] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1213 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1214 ) ,
+ .SC_OUT_BOT ( scff_Wires[285] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1215 ) ,
+ .Test_en_W_in ( Test_enWires[87] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1216 ) ,
+ .Test_en_E_out ( Test_enWires[88] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[221] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1217 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[411] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[412] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1218 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1219 ) ,
+ .clk_0_N_in ( clk_1_wires[221] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1220 ) ) ;
+grid_clb grid_clb_11__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[113] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1221 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__111_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_123_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_123_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_123_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_123_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_123_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_123_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_123_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_123_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_123_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_123_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_123_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_123_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_123_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_123_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_123_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_123_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_123_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_123_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_123_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_123_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_123_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_123_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_123_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_123_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_123_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_123_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_123_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_123_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_123_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_123_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_123_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_123_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[112] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1222 } ) ,
+ .ccff_tail ( grid_clb_123_ccff_tail ) , .SC_IN_TOP ( scff_Wires[282] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1223 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1224 ) ,
+ .SC_OUT_BOT ( scff_Wires[283] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1225 ) ,
+ .Test_en_W_in ( Test_enWires[109] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1226 ) ,
+ .Test_en_E_out ( Test_enWires[110] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1227 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[220] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[414] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[415] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1228 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1229 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1230 ) ,
+ .clk_0_S_in ( clk_1_wires[220] ) ) ;
+grid_clb grid_clb_11__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[114] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1231 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__112_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_124_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_124_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_124_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_124_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_124_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_124_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_124_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_124_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_124_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_124_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_124_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_124_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_124_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_124_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_124_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_124_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_124_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_124_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_124_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_124_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_124_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_124_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_124_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_124_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_124_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_124_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_124_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_124_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_124_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_124_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_124_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_124_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[113] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1232 } ) ,
+ .ccff_tail ( grid_clb_124_ccff_tail ) , .SC_IN_TOP ( scff_Wires[280] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1233 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1234 ) ,
+ .SC_OUT_BOT ( scff_Wires[281] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1235 ) ,
+ .Test_en_W_in ( Test_enWires[131] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1236 ) ,
+ .Test_en_E_out ( Test_enWires[132] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[228] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1237 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[417] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[418] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1238 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1239 ) ,
+ .clk_0_N_in ( clk_1_wires[228] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1240 ) ) ;
+grid_clb grid_clb_11__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[115] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1241 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__113_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_125_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_125_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_125_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_125_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_125_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_125_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_125_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_125_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_125_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_125_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_125_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_125_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_125_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_125_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_125_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_125_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_125_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_125_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_125_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_125_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_125_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_125_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_125_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_125_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_125_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_125_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_125_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_125_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_125_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_125_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_125_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_125_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[114] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1242 } ) ,
+ .ccff_tail ( grid_clb_125_ccff_tail ) , .SC_IN_TOP ( scff_Wires[278] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1243 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1244 ) ,
+ .SC_OUT_BOT ( scff_Wires[279] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1245 ) ,
+ .Test_en_W_in ( Test_enWires[153] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1246 ) ,
+ .Test_en_E_out ( Test_enWires[154] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1247 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[227] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[420] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[421] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1248 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1249 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1250 ) ,
+ .clk_0_S_in ( clk_1_wires[227] ) ) ;
+grid_clb grid_clb_11__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[116] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1251 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__114_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_126_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_126_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_126_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_126_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_126_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_126_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_126_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_126_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_126_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_126_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_126_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_126_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_126_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_126_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_126_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_126_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_126_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_126_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_126_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_126_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_126_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_126_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_126_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_126_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_126_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_126_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_126_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_126_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_126_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_126_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_126_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_126_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[115] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1252 } ) ,
+ .ccff_tail ( grid_clb_126_ccff_tail ) , .SC_IN_TOP ( scff_Wires[276] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1253 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1254 ) ,
+ .SC_OUT_BOT ( scff_Wires[277] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1255 ) ,
+ .Test_en_W_in ( Test_enWires[175] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1256 ) ,
+ .Test_en_E_out ( Test_enWires[176] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[235] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1257 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[423] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[424] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1258 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1259 ) ,
+ .clk_0_N_in ( clk_1_wires[235] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1260 ) ) ;
+grid_clb grid_clb_11__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[117] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1261 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__115_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_127_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_127_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_127_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_127_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_127_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_127_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_127_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_127_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_127_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_127_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_127_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_127_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_127_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_127_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_127_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_127_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_127_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_127_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_127_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_127_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_127_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_127_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_127_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_127_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_127_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_127_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_127_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_127_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_127_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_127_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_127_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_127_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[116] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1262 } ) ,
+ .ccff_tail ( grid_clb_127_ccff_tail ) , .SC_IN_TOP ( scff_Wires[274] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1263 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1264 ) ,
+ .SC_OUT_BOT ( scff_Wires[275] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1265 ) ,
+ .Test_en_W_in ( Test_enWires[197] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1266 ) ,
+ .Test_en_E_out ( Test_enWires[198] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1267 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[234] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[426] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[427] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1268 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1269 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1270 ) ,
+ .clk_0_S_in ( clk_1_wires[234] ) ) ;
+grid_clb grid_clb_11__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[118] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1271 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__116_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_128_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_128_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_128_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_128_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_128_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_128_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_128_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_128_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_128_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_128_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_128_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_128_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_128_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_128_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_128_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_128_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_128_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_128_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_128_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_128_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_128_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_128_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_128_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_128_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_128_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_128_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_128_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_128_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_128_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_128_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_128_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_128_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[117] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1272 } ) ,
+ .ccff_tail ( grid_clb_128_ccff_tail ) , .SC_IN_TOP ( scff_Wires[272] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1273 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1274 ) ,
+ .SC_OUT_BOT ( scff_Wires[273] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1275 ) ,
+ .Test_en_W_in ( Test_enWires[219] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1276 ) ,
+ .Test_en_E_out ( Test_enWires[220] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[242] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1277 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[429] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[430] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1278 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1279 ) ,
+ .clk_0_N_in ( clk_1_wires[242] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1280 ) ) ;
+grid_clb grid_clb_11__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[119] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1281 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__117_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_129_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_129_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_129_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_129_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_129_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_129_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_129_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_129_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_129_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_129_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_129_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_129_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_129_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_129_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_129_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_129_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_129_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_129_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_129_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_129_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_129_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_129_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_129_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_129_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_129_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_129_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_129_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_129_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_129_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_129_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_129_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_129_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[118] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1282 } ) ,
+ .ccff_tail ( grid_clb_129_ccff_tail ) , .SC_IN_TOP ( scff_Wires[270] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1283 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1284 ) ,
+ .SC_OUT_BOT ( scff_Wires[271] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1285 ) ,
+ .Test_en_W_in ( Test_enWires[241] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1286 ) ,
+ .Test_en_E_out ( Test_enWires[242] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1287 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[241] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[432] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[433] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1288 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1289 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1290 ) ,
+ .clk_0_S_in ( clk_1_wires[241] ) ) ;
+grid_clb grid_clb_11__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[120] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1291 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__118_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_130_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_130_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_130_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_130_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_130_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_130_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_130_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_130_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_130_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_130_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_130_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_130_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_130_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_130_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_130_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_130_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_130_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_130_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_130_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_130_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_130_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_130_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_130_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_130_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_130_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_130_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_130_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_130_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_130_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_130_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_130_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_130_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[119] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1292 } ) ,
+ .ccff_tail ( grid_clb_130_ccff_tail ) , .SC_IN_TOP ( scff_Wires[268] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1293 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1294 ) ,
+ .SC_OUT_BOT ( scff_Wires[269] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1295 ) ,
+ .Test_en_W_in ( Test_enWires[263] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1296 ) ,
+ .Test_en_E_out ( Test_enWires[264] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[249] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1297 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[435] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[436] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1298 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1299 ) ,
+ .clk_0_N_in ( clk_1_wires[249] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1300 ) ) ;
+grid_clb grid_clb_11__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1301 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__119_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_131_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_131_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_131_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_131_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_131_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_131_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_131_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_131_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_131_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_131_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_131_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_131_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_131_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_131_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_131_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_131_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_131_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_131_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_131_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_131_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_131_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_131_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_131_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_131_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_131_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_131_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_131_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_131_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_131_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_131_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_131_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_131_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[120] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1302 } ) ,
+ .ccff_tail ( grid_clb_131_ccff_tail ) , .SC_IN_TOP ( scff_Wires[266] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1303 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1304 ) ,
+ .SC_OUT_BOT ( scff_Wires[267] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1305 ) ,
+ .Test_en_W_in ( Test_enWires[285] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1306 ) ,
+ .Test_en_E_out ( Test_enWires[286] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1307 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[248] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[438] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[439] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1308 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[441] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1309 ) ,
+ .clk_0_S_in ( clk_1_wires[248] ) ) ;
+grid_clb grid_clb_12__1_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[121] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1310 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__120_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_132_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_132_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_132_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_132_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_132_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_132_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_132_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_132_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_132_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_132_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_132_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_132_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_132_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_132_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_132_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_132_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_132_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_132_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_132_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_132_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_132_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_132_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_132_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_132_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_132_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_132_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_132_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_132_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_132_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_132_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_132_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_132_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1311 } ) ,
+ .ccff_tail ( grid_clb_132_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1312 ) ,
+ .SC_IN_BOT ( scff_Wires[293] ) , .SC_OUT_TOP ( scff_Wires[294] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1313 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1314 ) ,
+ .Test_en_W_in ( Test_enWires[45] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1315 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1316 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[216] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1317 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[443] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[444] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1318 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1319 ) ,
+ .clk_0_N_in ( clk_1_wires[216] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1320 ) ) ;
+grid_clb grid_clb_12__2_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[122] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1321 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__121_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_133_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_133_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_133_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_133_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_133_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_133_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_133_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_133_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_133_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_133_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_133_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_133_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_133_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_133_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_133_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_133_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_133_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_133_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_133_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_133_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_133_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_133_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_133_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_133_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_133_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_133_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_133_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_133_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_133_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_133_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_133_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_133_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[121] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1322 } ) ,
+ .ccff_tail ( grid_clb_133_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1323 ) ,
+ .SC_IN_BOT ( scff_Wires[295] ) , .SC_OUT_TOP ( scff_Wires[296] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1324 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1325 ) ,
+ .Test_en_W_in ( Test_enWires[67] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1326 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1327 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1328 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[215] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[446] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[447] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1329 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1330 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1331 ) ,
+ .clk_0_S_in ( clk_1_wires[215] ) ) ;
+grid_clb grid_clb_12__3_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[123] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1332 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__122_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_134_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_134_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_134_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_134_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_134_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_134_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_134_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_134_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_134_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_134_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_134_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_134_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_134_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_134_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_134_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_134_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_134_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_134_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_134_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_134_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_134_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_134_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_134_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_134_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_134_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_134_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_134_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_134_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_134_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_134_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_134_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_134_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[122] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1333 } ) ,
+ .ccff_tail ( grid_clb_134_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1334 ) ,
+ .SC_IN_BOT ( scff_Wires[297] ) , .SC_OUT_TOP ( scff_Wires[298] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1335 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1336 ) ,
+ .Test_en_W_in ( Test_enWires[89] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1337 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1338 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[223] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1339 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[449] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[450] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1340 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1341 ) ,
+ .clk_0_N_in ( clk_1_wires[223] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1342 ) ) ;
+grid_clb grid_clb_12__4_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[124] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1343 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__123_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_135_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_135_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_135_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_135_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_135_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_135_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_135_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_135_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_135_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_135_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_135_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_135_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_135_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_135_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_135_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_135_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_135_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_135_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_135_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_135_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_135_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_135_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_135_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_135_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_135_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_135_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_135_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_135_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_135_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_135_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_135_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_135_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[123] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1344 } ) ,
+ .ccff_tail ( grid_clb_135_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1345 ) ,
+ .SC_IN_BOT ( scff_Wires[299] ) , .SC_OUT_TOP ( scff_Wires[300] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1346 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1347 ) ,
+ .Test_en_W_in ( Test_enWires[111] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1348 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1349 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1350 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[222] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[452] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[453] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1351 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1352 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1353 ) ,
+ .clk_0_S_in ( clk_1_wires[222] ) ) ;
+grid_clb grid_clb_12__5_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[125] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1354 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__124_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_136_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_136_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_136_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_136_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_136_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_136_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_136_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_136_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_136_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_136_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_136_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_136_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_136_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_136_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_136_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_136_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_136_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_136_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_136_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_136_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_136_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_136_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_136_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_136_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_136_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_136_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_136_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_136_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_136_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_136_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_136_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_136_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[124] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1355 } ) ,
+ .ccff_tail ( grid_clb_136_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1356 ) ,
+ .SC_IN_BOT ( scff_Wires[301] ) , .SC_OUT_TOP ( scff_Wires[302] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1357 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1358 ) ,
+ .Test_en_W_in ( Test_enWires[133] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1359 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1360 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[230] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1361 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[455] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[456] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1362 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1363 ) ,
+ .clk_0_N_in ( clk_1_wires[230] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1364 ) ) ;
+grid_clb grid_clb_12__6_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[126] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1365 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__125_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_137_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_137_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_137_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_137_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_137_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_137_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_137_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_137_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_137_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_137_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_137_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_137_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_137_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_137_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_137_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_137_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_137_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_137_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_137_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_137_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_137_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_137_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_137_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_137_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_137_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_137_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_137_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_137_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_137_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_137_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_137_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_137_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[125] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1366 } ) ,
+ .ccff_tail ( grid_clb_137_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1367 ) ,
+ .SC_IN_BOT ( scff_Wires[303] ) , .SC_OUT_TOP ( scff_Wires[304] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1368 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1369 ) ,
+ .Test_en_W_in ( Test_enWires[155] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1370 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1371 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1372 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[229] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[458] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[459] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1373 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1374 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1375 ) ,
+ .clk_0_S_in ( clk_1_wires[229] ) ) ;
+grid_clb grid_clb_12__7_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[127] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1376 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__126_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_138_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_138_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_138_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_138_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_138_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_138_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_138_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_138_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_138_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_138_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_138_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_138_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_138_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_138_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_138_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_138_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_138_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_138_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_138_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_138_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_138_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_138_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_138_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_138_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_138_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_138_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_138_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_138_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_138_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_138_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_138_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_138_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[126] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1377 } ) ,
+ .ccff_tail ( grid_clb_138_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1378 ) ,
+ .SC_IN_BOT ( scff_Wires[305] ) , .SC_OUT_TOP ( scff_Wires[306] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1379 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1380 ) ,
+ .Test_en_W_in ( Test_enWires[177] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1381 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1382 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[237] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1383 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[461] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[462] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1384 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1385 ) ,
+ .clk_0_N_in ( clk_1_wires[237] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1386 ) ) ;
+grid_clb grid_clb_12__8_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[128] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1387 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__127_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_139_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_139_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_139_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_139_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_139_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_139_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_139_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_139_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_139_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_139_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_139_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_139_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_139_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_139_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_139_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_139_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_139_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_139_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_139_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_139_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_139_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_139_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_139_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_139_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_139_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_139_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_139_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_139_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_139_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_139_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_139_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_139_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[127] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1388 } ) ,
+ .ccff_tail ( grid_clb_139_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1389 ) ,
+ .SC_IN_BOT ( scff_Wires[307] ) , .SC_OUT_TOP ( scff_Wires[308] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1390 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1391 ) ,
+ .Test_en_W_in ( Test_enWires[199] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1392 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1393 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1394 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[236] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[464] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[465] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1395 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1396 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1397 ) ,
+ .clk_0_S_in ( clk_1_wires[236] ) ) ;
+grid_clb grid_clb_12__9_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[129] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1398 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__128_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_140_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_140_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_140_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_140_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_140_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_140_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_140_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_140_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_140_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_140_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_140_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_140_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_140_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_140_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_140_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_140_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_140_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_140_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_140_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_140_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_140_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_140_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_140_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_140_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_140_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_140_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_140_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_140_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_140_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_140_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_140_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_140_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[128] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1399 } ) ,
+ .ccff_tail ( grid_clb_140_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1400 ) ,
+ .SC_IN_BOT ( scff_Wires[309] ) , .SC_OUT_TOP ( scff_Wires[310] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1401 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1402 ) ,
+ .Test_en_W_in ( Test_enWires[221] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1403 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1404 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[244] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1405 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[467] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[468] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1406 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1407 ) ,
+ .clk_0_N_in ( clk_1_wires[244] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1408 ) ) ;
+grid_clb grid_clb_12__10_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[130] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1409 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__129_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_141_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_141_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_141_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_141_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_141_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_141_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_141_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_141_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_141_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_141_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_141_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_141_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_141_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_141_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_141_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_141_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_141_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_141_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_141_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_141_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_141_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_141_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_141_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_141_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_141_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_141_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_141_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_141_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_141_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_141_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_141_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_141_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[129] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1410 } ) ,
+ .ccff_tail ( grid_clb_141_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1411 ) ,
+ .SC_IN_BOT ( scff_Wires[311] ) , .SC_OUT_TOP ( scff_Wires[312] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1412 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1413 ) ,
+ .Test_en_W_in ( Test_enWires[243] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1414 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1415 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1416 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[243] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[470] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[471] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1417 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1418 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1419 ) ,
+ .clk_0_S_in ( clk_1_wires[243] ) ) ;
+grid_clb grid_clb_12__11_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[131] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1420 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__130_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_142_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_142_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_142_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_142_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_142_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_142_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_142_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_142_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_142_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_142_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_142_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_142_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_142_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_142_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_142_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_142_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_142_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_142_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_142_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_142_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_142_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_142_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_142_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_142_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_142_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_142_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_142_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_142_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_142_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_142_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_142_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_142_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[130] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1421 } ) ,
+ .ccff_tail ( grid_clb_142_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1422 ) ,
+ .SC_IN_BOT ( scff_Wires[313] ) , .SC_OUT_TOP ( scff_Wires[314] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1423 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1424 ) ,
+ .Test_en_W_in ( Test_enWires[265] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1425 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1426 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[251] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1427 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[473] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[474] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1428 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1429 ) ,
+ .clk_0_N_in ( clk_1_wires[251] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1430 ) ) ;
+grid_clb grid_clb_12__12_ (
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1431 } ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) ,
+ .ccff_head ( cby_1__1__131_ccff_tail ) ,
+ .top_width_0_height_0__pin_34_upper ( grid_clb_143_top_width_0_height_0__pin_34_upper ) ,
+ .top_width_0_height_0__pin_34_lower ( grid_clb_143_top_width_0_height_0__pin_34_lower ) ,
+ .top_width_0_height_0__pin_35_upper ( grid_clb_143_top_width_0_height_0__pin_35_upper ) ,
+ .top_width_0_height_0__pin_35_lower ( grid_clb_143_top_width_0_height_0__pin_35_lower ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_143_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_143_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_143_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_143_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_143_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_143_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_143_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_143_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_143_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_143_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_143_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_143_top_width_0_height_0__pin_41_lower ) ,
+ .right_width_0_height_0__pin_42_upper ( grid_clb_143_right_width_0_height_0__pin_42_upper ) ,
+ .right_width_0_height_0__pin_42_lower ( grid_clb_143_right_width_0_height_0__pin_42_lower ) ,
+ .right_width_0_height_0__pin_43_upper ( grid_clb_143_right_width_0_height_0__pin_43_upper ) ,
+ .right_width_0_height_0__pin_43_lower ( grid_clb_143_right_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_143_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_143_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_143_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_143_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_143_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_143_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_143_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_143_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_143_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_143_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_143_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_143_right_width_0_height_0__pin_49_lower ) ,
+ .bottom_width_0_height_0__pin_50_ ( regin_feedthrough_wires[131] ) ,
+ .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1432 } ) ,
+ .ccff_tail ( grid_clb_143_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1433 ) ,
+ .SC_IN_BOT ( scff_Wires[315] ) , .SC_OUT_TOP ( scff_Wires[316] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1434 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1435 ) ,
+ .Test_en_W_in ( Test_enWires[287] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1436 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1437 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1438 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[250] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[476] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[477] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1439 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[479] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1440 ) ,
+ .clk_0_S_in ( clk_1_wires[250] ) ) ;
+sb_0__0_ sb_0__0_ ( .chany_top_in ( cby_0__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__0__0_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) ,
+ .ccff_head ( grid_io_bottom_11_ccff_tail ) ,
+ .chany_top_out ( sb_0__0__0_chany_top_out ) ,
+ .chanx_right_out ( sb_0__0__0_chanx_right_out ) ,
+ .ccff_tail ( ccff_tail ) , .prog_clk_0_E_in ( prog_clk_0_wires[5] ) ) ;
+sb_0__1_ sb_0__1_ ( .chany_top_in ( cby_0__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__0_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__0_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__0_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__0_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__0_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[4] ) ) ;
+sb_0__1_ sb_0__2_ ( .chany_top_in ( cby_0__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__1_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__1_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__1_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__1_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__1_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__1_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[10] ) ) ;
+sb_0__1_ sb_0__3_ ( .chany_top_in ( cby_0__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__2_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__2_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__2_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__2_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__2_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__2_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[15] ) ) ;
+sb_0__1_ sb_0__4_ ( .chany_top_in ( cby_0__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__3_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__3_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__3_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__3_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__3_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__3_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[20] ) ) ;
+sb_0__1_ sb_0__5_ ( .chany_top_in ( cby_0__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__4_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_4_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_4_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__4_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__4_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__4_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__4_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__4_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[25] ) ) ;
+sb_0__1_ sb_0__6_ ( .chany_top_in ( cby_0__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__5_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_5_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_5_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__5_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__5_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__5_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__5_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__5_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[30] ) ) ;
+sb_0__1_ sb_0__7_ ( .chany_top_in ( cby_0__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__6_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_6_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_6_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__6_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__6_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__6_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__6_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__6_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[35] ) ) ;
+sb_0__1_ sb_0__8_ ( .chany_top_in ( cby_0__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__7_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_7_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_7_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__7_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__7_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__7_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__7_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__7_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[40] ) ) ;
+sb_0__1_ sb_0__9_ ( .chany_top_in ( cby_0__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__8_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_8_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_8_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__8_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__8_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__8_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__8_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__8_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[45] ) ) ;
+sb_0__1_ sb_0__10_ ( .chany_top_in ( cby_0__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__9_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_9_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_9_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__9_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__9_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__9_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__9_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__9_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[50] ) ) ;
+sb_0__1_ sb_0__11_ ( .chany_top_in ( cby_0__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__10_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_10_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_10_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__10_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__10_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__10_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__10_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__10_ccff_tail ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[55] ) ) ;
+sb_0__2_ sb_0__12_ ( .chanx_right_in ( cbx_1__12__0_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_11_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_11_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_0__1__11_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( grid_io_top_0_ccff_tail ) ,
+ .chanx_right_out ( sb_0__12__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__12__0_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__12__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) ,
+ .SC_OUT_BOT ( scff_Wires[0] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[62] ) ) ;
+sb_1__0_ sb_1__0_ ( .chany_top_in ( cby_1__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__1_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__0_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_10_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__0_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__0_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) ,
+ .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p1418 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1441 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p1418 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1442 ) , .clk_3_S_in ( p1418 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1443 ) ) ;
+sb_1__0_ sb_2__0_ ( .chany_top_in ( cby_1__1__12_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_12_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_12_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__2_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__1_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_9_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__1_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__1_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1466 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1444 ) , .Test_en_S_in ( p1549 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1445 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p1549 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1446 ) , .clk_3_S_in ( p1549 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1447 ) ) ;
+sb_1__0_ sb_3__0_ ( .chany_top_in ( cby_1__1__24_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_24_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_24_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__3_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__2_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_8_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__2_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__2_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) ,
+ .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1255 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1448 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1677 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1449 ) , .clk_3_S_in ( p1677 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1450 ) ) ;
+sb_1__0_ sb_4__0_ ( .chany_top_in ( cby_1__1__36_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_36_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_36_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__4_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__3_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_7_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__3_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__3_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1522 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1451 ) , .Test_en_S_in ( p1536 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1452 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1876 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1453 ) , .clk_3_S_in ( p1512 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1454 ) ) ;
+sb_1__0_ sb_5__0_ ( .chany_top_in ( cby_1__1__48_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_48_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_48_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__5_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__4_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_6_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__4_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__4_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) ,
+ .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1128 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1455 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1128 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1456 ) , .clk_3_S_in ( p1128 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1457 ) ) ;
+sb_1__0_ sb_6__0_ ( .chany_top_in ( cby_1__1__60_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_60_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_60_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__6_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__5_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_5_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__5_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__5_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1480 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1458 ) , .Test_en_S_in ( Test_en[0] ) ,
+ .Test_en_N_out ( Test_enWires[1] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[217] ) ,
+ .prog_clk_3_S_in ( prog_clk[0] ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[90] ) , .clk_3_S_in ( clk[0] ) ,
+ .clk_3_N_out ( clk_3_wires[90] ) ) ;
+sb_1__0_ sb_7__0_ ( .chany_top_in ( cby_1__1__72_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_72_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_72_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__7_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__6_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_4_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__6_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__6_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) ,
+ .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p1290 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1459 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p1290 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1460 ) , .clk_3_S_in ( p1290 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1461 ) ) ;
+sb_1__0_ sb_8__0_ ( .chany_top_in ( cby_1__1__84_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_84_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_84_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__8_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__7_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_3_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__7_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__7_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1052 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1462 ) , .Test_en_S_in ( p1499 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1463 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p1499 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1464 ) , .clk_3_S_in ( p1499 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1465 ) ) ;
+sb_1__0_ sb_9__0_ ( .chany_top_in ( cby_1__1__96_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_96_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_96_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__9_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__8_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_2_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__8_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__8_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) ,
+ .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p1048 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1466 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1048 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1467 ) , .clk_3_S_in ( p1048 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1468 ) ) ;
+sb_1__0_ sb_10__0_ ( .chany_top_in ( cby_1__1__108_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_108_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_108_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__10_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__9_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_1_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__9_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__9_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1433 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1469 ) , .Test_en_S_in ( p1214 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1470 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1214 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1471 ) , .clk_3_S_in ( p1214 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1472 ) ) ;
+sb_1__0_ sb_11__0_ ( .chany_top_in ( cby_1__1__120_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_120_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_120_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__0__11_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__10_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_0_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__10_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__10_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) ,
+ .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1575 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1473 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1575 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1474 ) , .clk_3_S_in ( p1575 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1475 ) ) ;
+sb_1__1_ sb_1__1_ ( .chany_top_in ( cby_1__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__11_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_12_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_12_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__0_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__0_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__11_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__0_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p2348 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1476 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[8] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[4] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1477 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[1] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3191 ) ,
+ .prog_clk_2_E_in ( p467 ) , .prog_clk_2_S_in ( p448 ) ,
+ .prog_clk_2_W_in ( p86 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1478 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1479 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1480 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1481 ) ,
+ .prog_clk_3_W_in ( p2899 ) , .prog_clk_3_E_in ( p425 ) ,
+ .prog_clk_3_S_in ( p7 ) , .prog_clk_3_N_in ( p3163 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1482 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1483 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1484 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1485 ) ,
+ .clk_1_N_in ( clk_2_wires[4] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1486 ) ,
+ .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) ,
+ .clk_2_N_in ( p3031 ) , .clk_2_E_in ( p540 ) , .clk_2_S_in ( p2256 ) ,
+ .clk_2_W_in ( p2812 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1487 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1488 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1489 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1490 ) , .clk_3_W_in ( p2138 ) ,
+ .clk_3_E_in ( p906 ) , .clk_3_S_in ( p1295 ) , .clk_3_N_in ( p2957 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1491 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1492 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1493 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1494 ) ) ;
+sb_1__1_ sb_1__2_ ( .chany_top_in ( cby_1__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__12_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_13_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_13_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__1_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__1_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__12_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__1_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2068 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1495 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p3034 ) ,
+ .prog_clk_1_S_in ( p109 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1496 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1497 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1498 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[1] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1499 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1500 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1501 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[3] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1502 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1503 ) ,
+ .prog_clk_3_W_in ( p1680 ) , .prog_clk_3_E_in ( p150 ) ,
+ .prog_clk_3_S_in ( p1936 ) , .prog_clk_3_N_in ( p1962 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1504 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1505 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1506 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1507 ) , .clk_1_N_in ( p2561 ) ,
+ .clk_1_S_in ( p703 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1508 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1509 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1510 ) ,
+ .clk_2_E_in ( clk_2_wires[1] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1511 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1512 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1513 ) ,
+ .clk_2_S_out ( clk_2_wires[3] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1514 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1515 ) , .clk_3_W_in ( p1680 ) ,
+ .clk_3_E_in ( p2663 ) , .clk_3_S_in ( p382 ) , .clk_3_N_in ( p2969 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1516 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1517 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1518 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1519 ) ) ;
+sb_1__1_ sb_1__3_ ( .chany_top_in ( cby_1__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__13_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_14_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_14_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__2_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__2_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__13_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__2_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p3127 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1520 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[18] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[11] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1521 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[8] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3331 ) ,
+ .prog_clk_2_E_in ( p1247 ) , .prog_clk_2_S_in ( p545 ) ,
+ .prog_clk_2_W_in ( p575 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1522 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1523 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1524 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1525 ) ,
+ .prog_clk_3_W_in ( p3213 ) , .prog_clk_3_E_in ( p649 ) ,
+ .prog_clk_3_S_in ( p155 ) , .prog_clk_3_N_in ( p3308 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1526 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1527 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1528 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1529 ) ,
+ .clk_1_N_in ( clk_2_wires[11] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1530 ) ,
+ .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) ,
+ .clk_2_N_in ( p3209 ) , .clk_2_E_in ( p236 ) , .clk_2_S_in ( p3092 ) ,
+ .clk_2_W_in ( p3170 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1531 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1532 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1533 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1534 ) , .clk_3_W_in ( p1833 ) ,
+ .clk_3_E_in ( p901 ) , .clk_3_S_in ( p1328 ) , .clk_3_N_in ( p3156 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1535 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1536 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1537 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1538 ) ) ;
+sb_1__1_ sb_1__4_ ( .chany_top_in ( cby_1__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_4_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_4_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__14_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_15_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_15_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__3_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__3_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__14_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__3_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p2365 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1539 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p2600 ) ,
+ .prog_clk_1_S_in ( p221 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1540 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1541 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1542 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[6] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1543 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1544 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1545 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[10] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[8] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1546 ) ,
+ .prog_clk_3_W_in ( p2099 ) , .prog_clk_3_E_in ( p187 ) ,
+ .prog_clk_3_S_in ( p2217 ) , .prog_clk_3_N_in ( p1920 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1547 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1548 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1549 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1550 ) , .clk_1_N_in ( p2017 ) ,
+ .clk_1_S_in ( p1269 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1551 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1552 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1553 ) ,
+ .clk_2_E_in ( clk_2_wires[6] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1554 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1555 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1556 ) ,
+ .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1557 ) , .clk_3_W_in ( p2099 ) ,
+ .clk_3_E_in ( p1349 ) , .clk_3_S_in ( p1253 ) , .clk_3_N_in ( p2438 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1558 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1559 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1560 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1561 ) ) ;
+sb_1__1_ sb_1__5_ ( .chany_top_in ( cby_1__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_5_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_5_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__15_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_16_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_16_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__4_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_4_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_4_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__4_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_4_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_4_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__15_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__4_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p2358 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1562 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[28] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1563 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[9] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[15] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3328 ) ,
+ .prog_clk_2_E_in ( p956 ) , .prog_clk_2_S_in ( p1161 ) ,
+ .prog_clk_2_W_in ( p1134 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1564 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1565 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1566 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1567 ) ,
+ .prog_clk_3_W_in ( p2797 ) , .prog_clk_3_E_in ( p780 ) ,
+ .prog_clk_3_S_in ( p288 ) , .prog_clk_3_N_in ( p3320 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1568 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1569 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1570 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1571 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1572 ) ,
+ .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) ,
+ .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3479 ) ,
+ .clk_2_E_in ( p135 ) , .clk_2_S_in ( p2190 ) , .clk_2_W_in ( p3253 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1573 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1574 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1575 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1576 ) , .clk_3_W_in ( p3284 ) ,
+ .clk_3_E_in ( p802 ) , .clk_3_S_in ( p1346 ) , .clk_3_N_in ( p3471 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1577 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1578 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1579 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1580 ) ) ;
+sb_1__1_ sb_1__6_ ( .chany_top_in ( cby_1__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_6_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_6_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__16_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_17_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_17_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__5_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_5_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_5_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__5_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_5_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_5_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__16_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__5_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p2892 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1581 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p3197 ) ,
+ .prog_clk_1_S_in ( p1263 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1582 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1583 ) ,
+ .prog_clk_2_N_in ( p3442 ) , .prog_clk_2_E_in ( p751 ) ,
+ .prog_clk_2_S_in ( p63 ) , .prog_clk_2_W_in ( p23 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1584 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1585 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1586 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1587 ) ,
+ .prog_clk_3_W_in ( p2596 ) , .prog_clk_3_E_in ( p122 ) ,
+ .prog_clk_3_S_in ( p1402 ) , .prog_clk_3_N_in ( p3430 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1588 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1589 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1590 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1591 ) , .clk_1_N_in ( p2789 ) ,
+ .clk_1_S_in ( p439 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1592 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1593 ) , .clk_2_N_in ( p3201 ) ,
+ .clk_2_E_in ( p991 ) , .clk_2_S_in ( p2849 ) , .clk_2_W_in ( p2666 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1594 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1595 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1596 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1597 ) , .clk_3_W_in ( p2784 ) ,
+ .clk_3_E_in ( p687 ) , .clk_3_S_in ( p568 ) , .clk_3_N_in ( p3190 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1598 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1599 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1600 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1601 ) ) ;
+sb_1__1_ sb_1__7_ ( .chany_top_in ( cby_1__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_7_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_7_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__17_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_18_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_18_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__6_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_6_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_6_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__6_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_6_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_6_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__17_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__6_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2521 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1602 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[38] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[18] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1603 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[22] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3393 ) ,
+ .prog_clk_2_E_in ( p1091 ) , .prog_clk_2_S_in ( p1129 ) ,
+ .prog_clk_2_W_in ( p198 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1604 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1605 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1606 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1607 ) ,
+ .prog_clk_3_W_in ( p2893 ) , .prog_clk_3_E_in ( p656 ) ,
+ .prog_clk_3_S_in ( p557 ) , .prog_clk_3_N_in ( p3371 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1608 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1609 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1610 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1611 ) ,
+ .clk_1_N_in ( clk_2_wires[18] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1612 ) ,
+ .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) ,
+ .clk_2_N_in ( p3131 ) , .clk_2_E_in ( p53 ) , .clk_2_S_in ( p2434 ) ,
+ .clk_2_W_in ( p2977 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1613 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1614 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1615 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1616 ) , .clk_3_W_in ( p3024 ) ,
+ .clk_3_E_in ( p304 ) , .clk_3_S_in ( p633 ) , .clk_3_N_in ( p3075 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1617 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1618 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1619 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1620 ) ) ;
+sb_1__1_ sb_1__8_ ( .chany_top_in ( cby_1__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_8_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_8_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__18_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_19_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_19_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__7_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_7_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_7_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__7_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_7_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_7_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__18_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__7_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p2764 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1621 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p3395 ) ,
+ .prog_clk_1_S_in ( p276 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1622 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1623 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1624 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[13] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1625 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1626 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1627 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[17] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[15] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1628 ) ,
+ .prog_clk_3_W_in ( p1571 ) , .prog_clk_3_E_in ( p432 ) ,
+ .prog_clk_3_S_in ( p2658 ) , .prog_clk_3_N_in ( p1922 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1629 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1630 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1631 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1632 ) , .clk_1_N_in ( p2122 ) ,
+ .clk_1_S_in ( p462 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1633 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1634 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1635 ) ,
+ .clk_2_E_in ( clk_2_wires[13] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1636 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1637 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1638 ) ,
+ .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1639 ) , .clk_3_W_in ( p1571 ) ,
+ .clk_3_E_in ( p190 ) , .clk_3_S_in ( p274 ) , .clk_3_N_in ( p3364 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1640 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1641 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1642 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1643 ) ) ;
+sb_1__1_ sb_1__9_ ( .chany_top_in ( cby_1__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_9_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_9_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__19_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_20_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_20_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__8_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_8_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_8_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__8_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_8_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_8_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__19_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__8_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p2528 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1644 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[48] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1645 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[16] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[29] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3452 ) ,
+ .prog_clk_2_E_in ( p1257 ) , .prog_clk_2_S_in ( p1185 ) ,
+ .prog_clk_2_W_in ( p1965 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1646 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1647 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1648 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1649 ) ,
+ .prog_clk_3_W_in ( p2913 ) , .prog_clk_3_E_in ( p204 ) ,
+ .prog_clk_3_S_in ( p730 ) , .prog_clk_3_N_in ( p3427 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1650 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1651 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1652 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1653 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1654 ) ,
+ .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) ,
+ .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p3443 ) ,
+ .clk_2_E_in ( p370 ) , .clk_2_S_in ( p2457 ) , .clk_2_W_in ( p2807 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1655 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1656 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1657 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1658 ) , .clk_3_W_in ( p2758 ) ,
+ .clk_3_E_in ( p1197 ) , .clk_3_S_in ( p1301 ) , .clk_3_N_in ( p3437 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1659 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1660 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1661 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1662 ) ) ;
+sb_1__1_ sb_1__10_ ( .chany_top_in ( cby_1__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_10_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_10_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__20_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_21_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_21_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__9_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_9_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_9_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__9_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_9_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_9_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__20_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__9_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2724 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1663 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p3385 ) ,
+ .prog_clk_1_S_in ( p671 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1664 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1665 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1666 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[20] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1667 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1668 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1669 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1670 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[22] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1671 ) ,
+ .prog_clk_3_W_in ( p1537 ) , .prog_clk_3_E_in ( p1192 ) ,
+ .prog_clk_3_S_in ( p2667 ) , .prog_clk_3_N_in ( p127 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1672 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1673 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1674 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1675 ) , .clk_1_N_in ( p2296 ) ,
+ .clk_1_S_in ( p1324 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1676 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1677 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1678 ) ,
+ .clk_2_E_in ( clk_2_wires[20] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1679 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1680 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1681 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1682 ) ,
+ .clk_2_N_out ( clk_2_wires[22] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1683 ) , .clk_3_W_in ( p1537 ) ,
+ .clk_3_E_in ( p1933 ) , .clk_3_S_in ( p836 ) , .clk_3_N_in ( p3353 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1684 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1685 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1686 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1687 ) ) ;
+sb_1__1_ sb_1__11_ ( .chany_top_in ( cby_1__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_11_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_11_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__21_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_22_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_22_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__10_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_10_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_10_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__10_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_10_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_10_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__21_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__10_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p2398 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1688 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[58] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1689 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[23] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[36] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p3392 ) ,
+ .prog_clk_2_E_in ( p921 ) , .prog_clk_2_S_in ( p1148 ) ,
+ .prog_clk_2_W_in ( p1076 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1690 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1691 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1692 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1693 ) ,
+ .prog_clk_3_W_in ( p3003 ) , .prog_clk_3_E_in ( p757 ) ,
+ .prog_clk_3_S_in ( p424 ) , .prog_clk_3_N_in ( p3374 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1694 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1695 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1696 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1697 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1698 ) ,
+ .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) ,
+ .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p3480 ) ,
+ .clk_2_E_in ( p544 ) , .clk_2_S_in ( p2227 ) , .clk_2_W_in ( p3162 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1699 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1700 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1701 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1702 ) , .clk_3_W_in ( p3207 ) ,
+ .clk_3_E_in ( p257 ) , .clk_3_S_in ( p1145 ) , .clk_3_N_in ( p3473 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1703 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1704 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1705 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1706 ) ) ;
+sb_1__1_ sb_2__1_ ( .chany_top_in ( cby_1__1__13_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_13_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_13_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__22_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_24_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_24_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__12_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_12_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_12_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__11_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_12_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_12_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__22_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__11_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__11_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__11_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p2516 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1707 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p2883 ) ,
+ .prog_clk_1_S_in ( p1049 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1708 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1709 ) ,
+ .prog_clk_2_N_in ( p3500 ) , .prog_clk_2_E_in ( p162 ) ,
+ .prog_clk_2_S_in ( p315 ) , .prog_clk_2_W_in ( p598 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1710 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1711 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1712 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1713 ) ,
+ .prog_clk_3_W_in ( p2791 ) , .prog_clk_3_E_in ( p800 ) ,
+ .prog_clk_3_S_in ( p497 ) , .prog_clk_3_N_in ( p3496 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1714 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1715 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1716 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1717 ) , .clk_1_N_in ( p2046 ) ,
+ .clk_1_S_in ( p693 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1718 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1719 ) , .clk_2_N_in ( p3440 ) ,
+ .clk_2_E_in ( p1043 ) , .clk_2_S_in ( p2431 ) , .clk_2_W_in ( p3174 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1720 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1721 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1722 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1723 ) , .clk_3_W_in ( p3212 ) ,
+ .clk_3_E_in ( p1110 ) , .clk_3_S_in ( p1121 ) , .clk_3_N_in ( p3439 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1724 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1725 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1726 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1727 ) ) ;
+sb_1__1_ sb_2__2_ ( .chany_top_in ( cby_1__1__14_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_14_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_14_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__23_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_25_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_25_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__13_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_13_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_13_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__12_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_13_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_13_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__23_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__12_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__12_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__12_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p2570 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1728 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p3227 ) ,
+ .prog_clk_1_S_in ( p293 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1729 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1730 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[69] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1731 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1732 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1733 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[2] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1734 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1735 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1736 ) ,
+ .prog_clk_3_W_in ( p1435 ) , .prog_clk_3_E_in ( p1208 ) ,
+ .prog_clk_3_S_in ( p2451 ) , .prog_clk_3_N_in ( p287 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1737 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1738 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1739 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1740 ) , .clk_1_N_in ( p2613 ) ,
+ .clk_1_S_in ( p896 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1741 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1742 ) ,
+ .clk_2_N_in ( clk_3_wires[69] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1743 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1744 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1745 ) ,
+ .clk_2_W_out ( clk_2_wires[2] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1746 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1747 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1748 ) , .clk_3_W_in ( p1435 ) ,
+ .clk_3_E_in ( p237 ) , .clk_3_S_in ( p1061 ) , .clk_3_N_in ( p3175 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1749 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1750 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1751 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+sb_1__1_ sb_2__3_ ( .chany_top_in ( cby_1__1__15_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_15_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_15_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__24_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_26_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_26_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__14_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_14_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_14_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__13_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_14_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_14_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__24_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__13_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__13_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__13_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2154 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1753 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1612 ) ,
+ .prog_clk_1_S_in ( p878 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1754 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1755 ) ,
+ .prog_clk_2_N_in ( p1612 ) , .prog_clk_2_E_in ( p256 ) ,
+ .prog_clk_2_S_in ( p685 ) , .prog_clk_2_W_in ( p314 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1756 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1757 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1758 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1759 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1760 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1761 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1762 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[65] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1763 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1764 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1765 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1612 ) ,
+ .clk_1_S_in ( p64 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1766 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1767 ) , .clk_2_N_in ( p1612 ) ,
+ .clk_2_E_in ( p898 ) , .clk_2_S_in ( p1898 ) , .clk_2_W_in ( p910 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1768 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1769 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1770 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1771 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1772 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1773 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1774 ) ,
+ .clk_3_N_in ( clk_3_wires[65] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1775 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1776 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1777 ) ,
+ .clk_3_S_out ( clk_3_wires[68] ) ) ;
+sb_1__1_ sb_2__4_ ( .chany_top_in ( cby_1__1__16_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_16_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_16_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__25_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_27_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_27_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__15_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_15_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_15_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__14_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_15_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_15_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__25_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__14_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__14_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__14_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p1627 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1778 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1653 ) ,
+ .prog_clk_1_S_in ( p337 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1779 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1780 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[59] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1781 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1782 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1783 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[7] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1784 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1785 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1786 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1787 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1788 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1789 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[59] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1790 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1791 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1792 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1728 ) ,
+ .clk_1_S_in ( p949 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1793 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1794 ) ,
+ .clk_2_N_in ( clk_3_wires[59] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1795 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1796 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1797 ) ,
+ .clk_2_W_out ( clk_2_wires[7] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1798 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1799 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1800 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1801 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1802 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1803 ) ,
+ .clk_3_N_in ( clk_3_wires[59] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1804 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1805 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1806 ) ,
+ .clk_3_S_out ( clk_3_wires[64] ) ) ;
+sb_1__1_ sb_2__5_ ( .chany_top_in ( cby_1__1__17_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_17_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_17_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__26_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_28_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_28_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__16_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_16_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_16_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__15_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_16_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_16_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__26_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__15_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__15_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__15_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2534 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1807 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1619 ) ,
+ .prog_clk_1_S_in ( p726 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1808 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1809 ) ,
+ .prog_clk_2_N_in ( p1619 ) , .prog_clk_2_E_in ( p765 ) ,
+ .prog_clk_2_S_in ( p1902 ) , .prog_clk_2_W_in ( p140 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1810 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1811 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1812 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1813 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1814 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1815 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1816 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[55] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1817 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1818 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1819 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1619 ) ,
+ .clk_1_S_in ( p341 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1820 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1821 ) , .clk_2_N_in ( p1619 ) ,
+ .clk_2_E_in ( p301 ) , .clk_2_S_in ( p2466 ) , .clk_2_W_in ( p1268 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1822 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1823 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1824 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1825 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1826 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1827 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1828 ) ,
+ .clk_3_N_in ( clk_3_wires[55] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1829 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1830 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1831 ) ,
+ .clk_3_S_out ( clk_3_wires[58] ) ) ;
+sb_1__1_ sb_2__6_ ( .chany_top_in ( cby_1__1__18_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_18_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_18_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__27_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_29_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_29_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__17_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_17_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_17_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__16_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_17_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_17_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__27_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__16_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__16_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__16_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p2072 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1832 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1515 ) ,
+ .prog_clk_1_S_in ( p225 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1833 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1834 ) ,
+ .prog_clk_2_N_in ( p1711 ) , .prog_clk_2_E_in ( p128 ) ,
+ .prog_clk_2_S_in ( p1894 ) , .prog_clk_2_W_in ( p449 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1835 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1836 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1837 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1838 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1839 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[51] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1840 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1841 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1842 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1843 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[52] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1515 ) ,
+ .clk_1_S_in ( p869 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1844 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1845 ) , .clk_2_N_in ( p1515 ) ,
+ .clk_2_E_in ( p1207 ) , .clk_2_S_in ( p1967 ) , .clk_2_W_in ( p738 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1846 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1847 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1848 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1849 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1850 ) ,
+ .clk_3_E_in ( clk_3_wires[51] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1851 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1852 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1853 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1854 ) ,
+ .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) ) ;
+sb_1__1_ sb_2__7_ ( .chany_top_in ( cby_1__1__19_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_19_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_19_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__28_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_30_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_30_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__18_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_18_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_18_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__17_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_18_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_18_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__28_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__17_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__17_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__17_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p1756 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1855 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1769 ) ,
+ .prog_clk_1_S_in ( p1154 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1856 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1857 ) ,
+ .prog_clk_2_N_in ( p1769 ) , .prog_clk_2_E_in ( p371 ) ,
+ .prog_clk_2_S_in ( p2182 ) , .prog_clk_2_W_in ( p876 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1858 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1859 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1860 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1861 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1862 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1863 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[53] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1864 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1865 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1866 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[56] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1867 ) , .clk_1_N_in ( p1769 ) ,
+ .clk_1_S_in ( p154 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1868 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1869 ) , .clk_2_N_in ( p1769 ) ,
+ .clk_2_E_in ( p1256 ) , .clk_2_S_in ( p705 ) , .clk_2_W_in ( p935 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1870 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1871 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1872 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1873 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1874 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1875 ) ,
+ .clk_3_S_in ( clk_3_wires[53] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1876 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1877 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1878 ) ,
+ .clk_3_N_out ( clk_3_wires[56] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
+sb_1__1_ sb_2__8_ ( .chany_top_in ( cby_1__1__20_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_20_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_20_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__29_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_31_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_31_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__19_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_19_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_19_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__18_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_19_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_19_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__29_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__18_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__18_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__18_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p1869 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1880 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1870 ) ,
+ .prog_clk_1_S_in ( p952 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1881 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1882 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1883 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1884 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[57] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1885 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[14] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1886 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1887 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1888 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1889 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1890 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[57] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1891 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1892 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1893 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[62] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1894 ) , .clk_1_N_in ( p1870 ) ,
+ .clk_1_S_in ( p343 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1895 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1896 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1897 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1898 ) ,
+ .clk_2_S_in ( clk_3_wires[57] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1899 ) ,
+ .clk_2_W_out ( clk_2_wires[14] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1900 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1901 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1902 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1903 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1904 ) ,
+ .clk_3_S_in ( clk_3_wires[57] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1905 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1906 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1907 ) ,
+ .clk_3_N_out ( clk_3_wires[62] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1908 ) ) ;
+sb_1__1_ sb_2__9_ ( .chany_top_in ( cby_1__1__21_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_21_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_21_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__30_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_32_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_32_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__20_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_20_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_20_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__19_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_20_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_20_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__30_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__19_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__19_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__19_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p3044 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1909 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1637 ) ,
+ .prog_clk_1_S_in ( p865 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1910 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1911 ) ,
+ .prog_clk_2_N_in ( p1637 ) , .prog_clk_2_E_in ( p1098 ) ,
+ .prog_clk_2_S_in ( p19 ) , .prog_clk_2_W_in ( p145 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1912 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1913 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1914 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1915 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1916 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1917 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[63] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1918 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1919 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1920 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[66] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1921 ) , .clk_1_N_in ( p1637 ) ,
+ .clk_1_S_in ( p459 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1922 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1923 ) , .clk_2_N_in ( p1637 ) ,
+ .clk_2_E_in ( p526 ) , .clk_2_S_in ( p2952 ) , .clk_2_W_in ( p982 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1924 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1925 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1926 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1927 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1928 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1929 ) ,
+ .clk_3_S_in ( clk_3_wires[63] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1930 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1931 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1932 ) ,
+ .clk_3_N_out ( clk_3_wires[66] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1933 ) ) ;
+sb_1__1_ sb_2__10_ ( .chany_top_in ( cby_1__1__22_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_22_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_22_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__31_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_33_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_33_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__21_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_21_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_21_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__20_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_21_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_21_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__31_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__20_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__20_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__20_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2386 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1934 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p3421 ) ,
+ .prog_clk_1_S_in ( p612 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1935 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1936 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1937 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1938 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[67] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1939 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[21] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1940 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1941 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1942 ) ,
+ .prog_clk_3_W_in ( p1227 ) , .prog_clk_3_E_in ( p339 ) ,
+ .prog_clk_3_S_in ( p2231 ) , .prog_clk_3_N_in ( p2444 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1943 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1944 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1945 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1946 ) , .clk_1_N_in ( p2920 ) ,
+ .clk_1_S_in ( p917 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1947 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1948 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1949 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1950 ) ,
+ .clk_2_S_in ( clk_3_wires[67] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1951 ) ,
+ .clk_2_W_out ( clk_2_wires[21] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1952 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1953 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1954 ) , .clk_3_W_in ( p1227 ) ,
+ .clk_3_E_in ( p1046 ) , .clk_3_S_in ( p152 ) , .clk_3_N_in ( p3409 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1955 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1956 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1957 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1958 ) ) ;
+sb_1__1_ sb_2__11_ ( .chany_top_in ( cby_1__1__23_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_23_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_23_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__32_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_34_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_34_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__22_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_22_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_22_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__21_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_22_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_22_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__32_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__21_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__21_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__21_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p2737 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1959 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p3325 ) ,
+ .prog_clk_1_S_in ( p655 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1960 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1961 ) ,
+ .prog_clk_2_N_in ( p3444 ) , .prog_clk_2_E_in ( p530 ) ,
+ .prog_clk_2_S_in ( p512 ) , .prog_clk_2_W_in ( p767 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1962 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1963 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1964 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1965 ) ,
+ .prog_clk_3_W_in ( p2537 ) , .prog_clk_3_E_in ( p947 ) ,
+ .prog_clk_3_S_in ( p853 ) , .prog_clk_3_N_in ( p3438 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1966 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1967 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1968 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1969 ) , .clk_1_N_in ( p2612 ) ,
+ .clk_1_S_in ( p877 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1970 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1971 ) , .clk_2_N_in ( p3468 ) ,
+ .clk_2_E_in ( p297 ) , .clk_2_S_in ( p2681 ) , .clk_2_W_in ( p3311 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1972 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1973 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1974 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1975 ) , .clk_3_W_in ( p3346 ) ,
+ .clk_3_E_in ( p923 ) , .clk_3_S_in ( p36 ) , .clk_3_N_in ( p3458 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1976 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1977 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1978 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1979 ) ) ;
+sb_1__1_ sb_3__1_ ( .chany_top_in ( cby_1__1__25_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_25_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_25_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__33_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_36_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_36_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__24_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_24_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_24_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__22_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_24_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_24_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__33_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__22_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__22_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__22_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2530 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1980 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[106] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[30] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1981 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[43] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p2168 ) ,
+ .prog_clk_2_E_in ( p1104 ) , .prog_clk_2_S_in ( p1147 ) ,
+ .prog_clk_2_W_in ( p1961 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1982 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1983 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1984 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1985 ) ,
+ .prog_clk_3_W_in ( p2734 ) , .prog_clk_3_E_in ( p502 ) ,
+ .prog_clk_3_S_in ( p593 ) , .prog_clk_3_N_in ( p1954 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1986 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1987 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1988 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1989 ) ,
+ .clk_1_N_in ( clk_2_wires[30] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1990 ) ,
+ .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) ,
+ .clk_2_N_in ( p3276 ) , .clk_2_E_in ( p159 ) , .clk_2_S_in ( p2454 ) ,
+ .clk_2_W_in ( p3173 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1991 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1992 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1993 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1994 ) , .clk_3_W_in ( p3218 ) ,
+ .clk_3_E_in ( p702 ) , .clk_3_S_in ( p1264 ) , .clk_3_N_in ( p3245 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1995 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1996 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1997 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1998 ) ) ;
+sb_1__1_ sb_3__2_ ( .chany_top_in ( cby_1__1__26_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_26_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_26_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__34_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_37_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_37_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__25_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_25_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_25_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__23_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_25_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_25_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__34_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__23_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__23_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__23_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2728 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1999 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1752 ) ,
+ .prog_clk_1_S_in ( p84 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2000 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2001 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2002 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[28] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2003 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2004 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2005 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[29] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2006 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2007 ) ,
+ .prog_clk_3_W_in ( p1755 ) , .prog_clk_3_E_in ( p1326 ) ,
+ .prog_clk_3_S_in ( p2652 ) , .prog_clk_3_N_in ( p621 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2008 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2009 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2010 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2011 ) , .clk_1_N_in ( p1718 ) ,
+ .clk_1_S_in ( p874 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2012 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2013 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2014 ) ,
+ .clk_2_E_in ( clk_2_wires[28] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2015 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2016 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2017 ) ,
+ .clk_2_S_out ( clk_2_wires[29] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2018 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2019 ) , .clk_3_W_in ( p1755 ) ,
+ .clk_3_E_in ( p272 ) , .clk_3_S_in ( p252 ) , .clk_3_N_in ( p533 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2020 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2021 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2022 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2023 ) ) ;
+sb_1__1_ sb_3__3_ ( .chany_top_in ( cby_1__1__27_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_27_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_27_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__35_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_38_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_38_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__26_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_26_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_26_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__24_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_26_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_26_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__35_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__24_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__24_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__24_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p1759 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2024 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[112] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[41] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2025 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[50] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p2589 ) ,
+ .prog_clk_2_E_in ( p1333 ) , .prog_clk_2_S_in ( p1025 ) ,
+ .prog_clk_2_W_in ( p535 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2026 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2027 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2028 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2029 ) ,
+ .prog_clk_3_W_in ( p2988 ) , .prog_clk_3_E_in ( p246 ) ,
+ .prog_clk_3_S_in ( p356 ) , .prog_clk_3_N_in ( p2477 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2030 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2031 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2032 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2033 ) ,
+ .clk_1_N_in ( clk_2_wires[41] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2034 ) ,
+ .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) ,
+ .clk_2_N_in ( p3501 ) , .clk_2_E_in ( p553 ) , .clk_2_S_in ( p32 ) ,
+ .clk_2_W_in ( p3369 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2035 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2036 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2037 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2038 ) , .clk_3_W_in ( p3384 ) ,
+ .clk_3_E_in ( p696 ) , .clk_3_S_in ( p1032 ) , .clk_3_N_in ( p3498 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2039 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2040 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2041 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2042 ) ) ;
+sb_1__1_ sb_3__4_ ( .chany_top_in ( cby_1__1__28_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_28_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_28_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__36_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_39_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_39_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__27_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_27_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_27_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__25_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_27_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_27_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__36_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__25_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__25_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__25_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2315 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2043 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p3028 ) ,
+ .prog_clk_1_S_in ( p931 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2044 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2045 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2046 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[37] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2047 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2048 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2049 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[40] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[38] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2050 ) ,
+ .prog_clk_3_W_in ( p2150 ) , .prog_clk_3_E_in ( p83 ) ,
+ .prog_clk_3_S_in ( p2205 ) , .prog_clk_3_N_in ( p2180 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2051 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2052 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2053 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2054 ) , .clk_1_N_in ( p2770 ) ,
+ .clk_1_S_in ( p214 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2055 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2056 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2057 ) ,
+ .clk_2_E_in ( clk_2_wires[37] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2058 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2059 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2060 ) ,
+ .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2061 ) , .clk_3_W_in ( p2150 ) ,
+ .clk_3_E_in ( p969 ) , .clk_3_S_in ( p355 ) , .clk_3_N_in ( p2951 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2062 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2063 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2064 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2065 ) ) ;
+sb_1__1_ sb_3__5_ ( .chany_top_in ( cby_1__1__29_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_29_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_29_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__37_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_40_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_40_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__28_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_28_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_28_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__26_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_28_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_28_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__37_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__26_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__26_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__26_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p3014 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2066 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[118] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2067 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[39] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[57] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3043 ) ,
+ .prog_clk_2_E_in ( p961 ) , .prog_clk_2_S_in ( p919 ) ,
+ .prog_clk_2_W_in ( p404 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2068 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2069 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2070 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2071 ) ,
+ .prog_clk_3_W_in ( p3147 ) , .prog_clk_3_E_in ( p1173 ) ,
+ .prog_clk_3_S_in ( p1277 ) , .prog_clk_3_N_in ( p2947 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2072 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2073 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2074 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2075 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2076 ) ,
+ .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) ,
+ .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p2859 ) ,
+ .clk_2_E_in ( p933 ) , .clk_2_S_in ( p2970 ) , .clk_2_W_in ( p3090 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2077 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2078 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2079 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2080 ) , .clk_3_W_in ( p2066 ) ,
+ .clk_3_E_in ( p192 ) , .clk_3_S_in ( p395 ) , .clk_3_N_in ( p2845 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2081 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2082 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2083 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2084 ) ) ;
+sb_1__1_ sb_3__6_ ( .chany_top_in ( cby_1__1__30_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_30_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_30_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__38_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_41_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_41_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__29_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_29_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_29_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__27_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_29_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_29_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__38_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__27_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__27_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__27_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p2155 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2085 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1351 ) ,
+ .prog_clk_1_S_in ( p541 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2086 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2087 ) ,
+ .prog_clk_2_N_in ( p1597 ) , .prog_clk_2_E_in ( p264 ) ,
+ .prog_clk_2_S_in ( p56 ) , .prog_clk_2_W_in ( p37 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2088 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2089 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2090 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2091 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2092 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[47] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2093 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2094 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2095 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[50] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2096 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2097 ) , .clk_1_N_in ( p1351 ) ,
+ .clk_1_S_in ( p564 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2098 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2099 ) , .clk_2_N_in ( p1351 ) ,
+ .clk_2_E_in ( p962 ) , .clk_2_S_in ( p1980 ) , .clk_2_W_in ( p1236 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2100 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2101 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2102 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2103 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2104 ) ,
+ .clk_3_E_in ( clk_3_wires[47] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2105 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2106 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2107 ) ,
+ .clk_3_W_out ( clk_3_wires[50] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2108 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2109 ) ) ;
+sb_1__1_ sb_3__7_ ( .chany_top_in ( cby_1__1__31_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_31_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_31_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__39_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_42_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_42_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__30_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_30_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_30_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__28_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_30_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_30_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__39_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__28_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__28_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__28_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p2870 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2110 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[124] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[54] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2111 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[64] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p2708 ) ,
+ .prog_clk_2_E_in ( p119 ) , .prog_clk_2_S_in ( p247 ) ,
+ .prog_clk_2_W_in ( p2261 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2112 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2113 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2114 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2115 ) ,
+ .prog_clk_3_W_in ( p2405 ) , .prog_clk_3_E_in ( p920 ) ,
+ .prog_clk_3_S_in ( p1330 ) , .prog_clk_3_N_in ( p2640 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2116 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2117 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2118 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2119 ) ,
+ .clk_1_N_in ( clk_2_wires[54] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2120 ) ,
+ .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) ,
+ .clk_2_N_in ( p3381 ) , .clk_2_E_in ( p971 ) , .clk_2_S_in ( p2808 ) ,
+ .clk_2_W_in ( p2945 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2121 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2122 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2123 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2124 ) , .clk_3_W_in ( p3017 ) ,
+ .clk_3_E_in ( p997 ) , .clk_3_S_in ( p475 ) , .clk_3_N_in ( p3363 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2125 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2126 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2127 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2128 ) ) ;
+sb_1__1_ sb_3__8_ ( .chany_top_in ( cby_1__1__32_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_32_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_32_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__40_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_43_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_43_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__31_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_31_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_31_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__29_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_31_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_31_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__40_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__29_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__29_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__29_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p1081 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2129 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p3492 ) ,
+ .prog_clk_1_S_in ( p1140 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2130 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2131 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2132 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[50] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2133 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2134 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2135 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[53] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[51] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2136 ) ,
+ .prog_clk_3_W_in ( p2340 ) , .prog_clk_3_E_in ( p412 ) ,
+ .prog_clk_3_S_in ( p114 ) , .prog_clk_3_N_in ( p2482 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2137 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2138 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2139 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_1_N_in ( p2048 ) ,
+ .clk_1_S_in ( p130 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2141 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2142 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2143 ) ,
+ .clk_2_E_in ( clk_2_wires[50] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2144 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2145 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2146 ) ,
+ .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2147 ) , .clk_3_W_in ( p2722 ) ,
+ .clk_3_E_in ( p1138 ) , .clk_3_S_in ( p711 ) , .clk_3_N_in ( p3486 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2148 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2149 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2150 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2151 ) ) ;
+sb_1__1_ sb_3__9_ ( .chany_top_in ( cby_1__1__33_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_33_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_33_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__41_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_44_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_44_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__32_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_32_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_32_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__30_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_32_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_32_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__41_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__30_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__30_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__30_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p3011 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2152 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[130] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2153 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[52] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[71] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3467 ) ,
+ .prog_clk_2_E_in ( p1008 ) , .prog_clk_2_S_in ( p916 ) ,
+ .prog_clk_2_W_in ( p1963 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2154 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2155 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2156 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2157 ) ,
+ .prog_clk_3_W_in ( p3269 ) , .prog_clk_3_E_in ( p788 ) ,
+ .prog_clk_3_S_in ( p367 ) , .prog_clk_3_N_in ( p3454 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2158 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2159 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2160 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2161 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2162 ) ,
+ .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) ,
+ .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3286 ) ,
+ .clk_2_E_in ( p26 ) , .clk_2_S_in ( p2959 ) , .clk_2_W_in ( p3252 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2163 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2164 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2165 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2166 ) , .clk_3_W_in ( p3134 ) ,
+ .clk_3_E_in ( p666 ) , .clk_3_S_in ( p1409 ) , .clk_3_N_in ( p3256 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2167 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2168 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2169 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2170 ) ) ;
+sb_1__1_ sb_3__10_ ( .chany_top_in ( cby_1__1__34_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_34_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_34_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__42_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_45_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_45_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__33_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_33_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_33_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__31_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_33_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_33_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__42_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__31_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__31_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__31_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p1630 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2171 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p3448 ) ,
+ .prog_clk_1_S_in ( p743 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2172 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2173 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2174 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[63] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2175 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2176 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2177 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2178 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[64] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2179 ) ,
+ .prog_clk_3_W_in ( p2332 ) , .prog_clk_3_E_in ( p844 ) ,
+ .prog_clk_3_S_in ( p392 ) , .prog_clk_3_N_in ( p372 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2180 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2181 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2182 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p2624 ) ,
+ .clk_1_S_in ( p62 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2185 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2186 ) ,
+ .clk_2_E_in ( clk_2_wires[63] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2187 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2188 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2189 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2190 ) ,
+ .clk_2_N_out ( clk_2_wires[64] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p2332 ) ,
+ .clk_3_E_in ( p132 ) , .clk_3_S_in ( p1279 ) , .clk_3_N_in ( p3431 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2192 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2193 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2194 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sb_1__1_ sb_3__11_ ( .chany_top_in ( cby_1__1__35_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_35_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_35_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__43_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_46_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_46_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__34_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_34_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_34_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__32_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_34_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_34_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__43_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__32_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__32_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__32_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2713 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2196 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[136] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2197 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[65] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[78] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p2738 ) ,
+ .prog_clk_2_E_in ( p1096 ) , .prog_clk_2_S_in ( p665 ) ,
+ .prog_clk_2_W_in ( p688 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2198 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2199 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2200 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2201 ) ,
+ .prog_clk_3_W_in ( p3347 ) , .prog_clk_3_E_in ( p890 ) ,
+ .prog_clk_3_S_in ( p1024 ) , .prog_clk_3_N_in ( p2684 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2202 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2203 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2204 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2205 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2206 ) ,
+ .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) ,
+ .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p3462 ) ,
+ .clk_2_E_in ( p217 ) , .clk_2_S_in ( p2653 ) , .clk_2_W_in ( p3301 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2207 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2208 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2209 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2210 ) , .clk_3_W_in ( p3339 ) ,
+ .clk_3_E_in ( p722 ) , .clk_3_S_in ( p157 ) , .clk_3_N_in ( p3459 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2211 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2212 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2213 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2214 ) ) ;
+sb_1__1_ sb_4__1_ ( .chany_top_in ( cby_1__1__37_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_37_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_37_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__44_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_48_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_48_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__36_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_36_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_36_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__33_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_36_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_36_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__44_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__33_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__33_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__33_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2294 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2215 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p3004 ) ,
+ .prog_clk_1_S_in ( p76 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2216 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2217 ) ,
+ .prog_clk_2_N_in ( p3383 ) , .prog_clk_2_E_in ( p747 ) ,
+ .prog_clk_2_S_in ( p1126 ) , .prog_clk_2_W_in ( p248 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2218 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2219 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2220 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2221 ) ,
+ .prog_clk_3_W_in ( p3512 ) , .prog_clk_3_E_in ( p268 ) ,
+ .prog_clk_3_S_in ( p859 ) , .prog_clk_3_N_in ( p3366 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2222 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2223 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2224 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2225 ) , .clk_1_N_in ( p3042 ) ,
+ .clk_1_S_in ( p948 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2226 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2227 ) , .clk_2_N_in ( p3226 ) ,
+ .clk_2_E_in ( p104 ) , .clk_2_S_in ( p2250 ) , .clk_2_W_in ( p3509 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2228 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2229 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2230 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2231 ) , .clk_3_W_in ( p3271 ) ,
+ .clk_3_E_in ( p772 ) , .clk_3_S_in ( p380 ) , .clk_3_N_in ( p3182 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2232 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2233 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2234 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2235 ) ) ;
+sb_1__1_ sb_4__2_ ( .chany_top_in ( cby_1__1__38_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_38_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_38_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__45_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_49_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_49_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__37_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_37_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_37_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__34_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_37_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_37_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__45_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__34_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__34_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__34_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p1545 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2236 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p3344 ) ,
+ .prog_clk_1_S_in ( p798 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2238 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[25] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2239 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2240 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2241 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[27] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2242 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2243 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p1763 ) ,
+ .prog_clk_3_E_in ( p1139 ) , .prog_clk_3_S_in ( p451 ) ,
+ .prog_clk_3_N_in ( p978 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2244 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2245 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2246 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2247 ) , .clk_1_N_in ( p2748 ) ,
+ .clk_1_S_in ( p438 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2248 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2249 ) ,
+ .clk_2_N_in ( clk_3_wires[25] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2250 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2251 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2252 ) ,
+ .clk_2_W_out ( clk_2_wires[27] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2253 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2254 ) ,
+ .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p1763 ) ,
+ .clk_3_E_in ( p210 ) , .clk_3_S_in ( p330 ) , .clk_3_N_in ( p3317 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2255 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2256 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2257 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2258 ) ) ;
+sb_1__1_ sb_4__3_ ( .chany_top_in ( cby_1__1__39_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_39_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_39_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__46_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_50_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_50_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__38_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_38_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_38_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__35_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_38_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_38_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__46_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__35_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__35_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__35_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2060 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2259 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1847 ) ,
+ .prog_clk_1_S_in ( p1027 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2260 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2261 ) ,
+ .prog_clk_2_N_in ( p1827 ) , .prog_clk_2_E_in ( p585 ) ,
+ .prog_clk_2_S_in ( p1193 ) , .prog_clk_2_W_in ( p1211 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2262 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2263 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2264 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2265 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2266 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2267 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2268 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[21] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2269 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2270 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2271 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1648 ) ,
+ .clk_1_S_in ( p617 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2272 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2273 ) , .clk_2_N_in ( p1847 ) ,
+ .clk_2_E_in ( p626 ) , .clk_2_S_in ( p1917 ) , .clk_2_W_in ( p121 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2274 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2275 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2276 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2277 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2278 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2279 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2280 ) ,
+ .clk_3_N_in ( clk_3_wires[21] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2281 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2282 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2283 ) ,
+ .clk_3_S_out ( clk_3_wires[24] ) ) ;
+sb_1__1_ sb_4__4_ ( .chany_top_in ( cby_1__1__40_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_40_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_40_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__47_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_51_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_51_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__39_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_39_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_39_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__36_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_39_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_39_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__47_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__36_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__36_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__36_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p1743 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2284 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p2091 ) ,
+ .prog_clk_1_S_in ( p1042 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2285 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2286 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[15] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2287 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2288 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2289 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[36] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2290 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2291 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[34] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2292 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2293 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2294 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[15] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2295 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2296 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2297 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p2091 ) ,
+ .clk_1_S_in ( p125 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2298 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2299 ) ,
+ .clk_2_N_in ( clk_3_wires[15] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2300 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2301 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2302 ) ,
+ .clk_2_W_out ( clk_2_wires[36] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2303 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2304 ) ,
+ .clk_2_E_out ( clk_2_wires[34] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2305 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2306 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2307 ) ,
+ .clk_3_N_in ( clk_3_wires[15] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2308 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2309 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2310 ) ,
+ .clk_3_S_out ( clk_3_wires[20] ) ) ;
+sb_1__1_ sb_4__5_ ( .chany_top_in ( cby_1__1__41_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_41_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_41_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__48_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_52_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_52_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__40_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_40_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_40_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__37_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_40_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_40_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__48_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__37_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__37_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__37_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p2542 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2311 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1650 ) ,
+ .prog_clk_1_S_in ( p92 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2312 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2313 ) ,
+ .prog_clk_2_N_in ( p1650 ) , .prog_clk_2_E_in ( p1342 ) ,
+ .prog_clk_2_S_in ( p1163 ) , .prog_clk_2_W_in ( p312 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2315 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2316 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2318 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2319 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2320 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[11] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2321 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2322 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2323 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1650 ) ,
+ .clk_1_S_in ( p574 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2324 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2325 ) , .clk_2_N_in ( p1650 ) ,
+ .clk_2_E_in ( p810 ) , .clk_2_S_in ( p2468 ) , .clk_2_W_in ( p870 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2326 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2327 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2328 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2329 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2330 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2331 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2332 ) ,
+ .clk_3_N_in ( clk_3_wires[11] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2333 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2334 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2335 ) ,
+ .clk_3_S_out ( clk_3_wires[14] ) ) ;
+sb_1__1_ sb_4__6_ ( .chany_top_in ( cby_1__1__42_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_42_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_42_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__49_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_53_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_53_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__41_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_41_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_41_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__38_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_41_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_41_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__49_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__38_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__38_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__38_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p1864 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2336 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1629 ) ,
+ .prog_clk_1_S_in ( p1028 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2337 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2338 ) ,
+ .prog_clk_2_N_in ( p1629 ) , .prog_clk_2_E_in ( p51 ) ,
+ .prog_clk_2_S_in ( p1157 ) , .prog_clk_2_W_in ( p207 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2339 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2340 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2341 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2342 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2343 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[7] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2344 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2345 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2346 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[46] ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[8] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1629 ) ,
+ .clk_1_S_in ( p168 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2347 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2348 ) , .clk_2_N_in ( p1629 ) ,
+ .clk_2_E_in ( p1317 ) , .clk_2_S_in ( p600 ) , .clk_2_W_in ( p1280 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2349 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2350 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2351 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2352 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2353 ) ,
+ .clk_3_E_in ( clk_3_wires[7] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2354 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2355 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2356 ) ,
+ .clk_3_W_out ( clk_3_wires[46] ) , .clk_3_N_out ( clk_3_wires[8] ) ,
+ .clk_3_S_out ( clk_3_wires[10] ) ) ;
+sb_1__1_ sb_4__7_ ( .chany_top_in ( cby_1__1__43_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_43_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_43_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__50_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_54_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_54_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__42_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_42_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_42_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__39_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_42_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_42_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__50_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__39_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__39_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__39_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2171 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2357 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1220 ) ,
+ .prog_clk_1_S_in ( p354 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2358 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2359 ) ,
+ .prog_clk_2_N_in ( p1220 ) , .prog_clk_2_E_in ( p973 ) ,
+ .prog_clk_2_S_in ( p1285 ) , .prog_clk_2_W_in ( p466 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2360 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2361 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2362 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2363 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2364 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2365 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[9] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2366 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2367 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2368 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[12] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_1_N_in ( p1220 ) ,
+ .clk_1_S_in ( p1050 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2370 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2371 ) , .clk_2_N_in ( p1220 ) ,
+ .clk_2_E_in ( p129 ) , .clk_2_S_in ( p1907 ) , .clk_2_W_in ( p1331 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2372 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2373 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2374 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2375 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2376 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2377 ) ,
+ .clk_3_S_in ( clk_3_wires[9] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2378 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2379 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2380 ) ,
+ .clk_3_N_out ( clk_3_wires[12] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2381 ) ) ;
+sb_1__1_ sb_4__8_ ( .chany_top_in ( cby_1__1__44_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_44_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_44_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__51_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_55_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_55_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__43_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_43_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_43_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__40_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_43_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_43_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__51_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__40_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__40_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__40_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1701 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2382 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1526 ) ,
+ .prog_clk_1_S_in ( p43 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2383 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2384 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2385 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2386 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[13] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2387 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[49] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2388 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2389 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[47] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2390 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2391 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[13] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2392 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2393 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2394 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[18] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2395 ) , .clk_1_N_in ( p1526 ) ,
+ .clk_1_S_in ( p778 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2396 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2397 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2398 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2399 ) ,
+ .clk_2_S_in ( clk_3_wires[13] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2400 ) ,
+ .clk_2_W_out ( clk_2_wires[49] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2401 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2402 ) ,
+ .clk_2_E_out ( clk_2_wires[47] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2403 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2404 ) ,
+ .clk_3_S_in ( clk_3_wires[13] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2405 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2406 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2407 ) ,
+ .clk_3_N_out ( clk_3_wires[18] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2408 ) ) ;
+sb_1__1_ sb_4__9_ ( .chany_top_in ( cby_1__1__45_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_45_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_45_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__52_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_56_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_56_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__44_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_44_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_44_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__41_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_44_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_44_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__52_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__41_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__41_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__41_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2621 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2409 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1388 ) ,
+ .prog_clk_1_S_in ( p289 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2410 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2411 ) ,
+ .prog_clk_2_N_in ( p1388 ) , .prog_clk_2_E_in ( p1209 ) ,
+ .prog_clk_2_S_in ( p1927 ) , .prog_clk_2_W_in ( p583 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2412 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2413 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2414 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2415 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2416 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2417 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[19] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2418 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2419 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2420 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[22] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2421 ) , .clk_1_N_in ( p1388 ) ,
+ .clk_1_S_in ( p826 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2422 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_2_N_in ( p1388 ) ,
+ .clk_2_E_in ( p5 ) , .clk_2_S_in ( p2447 ) , .clk_2_W_in ( p988 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2424 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2425 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2426 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2427 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2428 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2429 ) ,
+ .clk_3_S_in ( clk_3_wires[19] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2430 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2431 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2432 ) ,
+ .clk_3_N_out ( clk_3_wires[22] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2433 ) ) ;
+sb_1__1_ sb_4__10_ ( .chany_top_in ( cby_1__1__46_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_46_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_46_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__53_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_57_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_57_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__45_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_45_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_45_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__42_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_45_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_45_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__53_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__42_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__42_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__42_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2059 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2434 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p3382 ) ,
+ .prog_clk_1_S_in ( p981 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2435 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2436 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2437 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2438 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[23] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2439 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[62] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2440 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2441 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p2536 ) ,
+ .prog_clk_3_E_in ( p918 ) , .prog_clk_3_S_in ( p1906 ) ,
+ .prog_clk_3_N_in ( p748 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2442 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2443 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2444 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_1_N_in ( p2732 ) ,
+ .clk_1_S_in ( p358 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2446 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2447 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2448 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2449 ) ,
+ .clk_2_S_in ( clk_3_wires[23] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2450 ) ,
+ .clk_2_W_out ( clk_2_wires[62] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2451 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2452 ) ,
+ .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p2536 ) ,
+ .clk_3_E_in ( p116 ) , .clk_3_S_in ( p1005 ) , .clk_3_N_in ( p3355 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2453 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2454 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2455 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
+sb_1__1_ sb_4__11_ ( .chany_top_in ( cby_1__1__47_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_47_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_47_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__54_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_58_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_58_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__46_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_46_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_46_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__43_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_46_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_46_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__54_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__43_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__43_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__43_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p2729 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2457 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p3102 ) ,
+ .prog_clk_1_S_in ( p1115 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2458 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2459 ) ,
+ .prog_clk_2_N_in ( p3144 ) , .prog_clk_2_E_in ( p1372 ) ,
+ .prog_clk_2_S_in ( p592 ) , .prog_clk_2_W_in ( p311 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2460 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2461 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2462 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2463 ) ,
+ .prog_clk_3_W_in ( p2426 ) , .prog_clk_3_E_in ( p661 ) ,
+ .prog_clk_3_S_in ( p1459 ) , .prog_clk_3_N_in ( p3069 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2464 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2465 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2466 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2467 ) , .clk_1_N_in ( p2611 ) ,
+ .clk_1_S_in ( p446 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2468 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2469 ) , .clk_2_N_in ( p3502 ) ,
+ .clk_2_E_in ( p720 ) , .clk_2_S_in ( p2637 ) , .clk_2_W_in ( p2963 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2470 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2471 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2472 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2473 ) , .clk_3_W_in ( p3048 ) ,
+ .clk_3_E_in ( p98 ) , .clk_3_S_in ( p228 ) , .clk_3_N_in ( p3495 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2474 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2475 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2476 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
+sb_1__1_ sb_5__1_ ( .chany_top_in ( cby_1__1__49_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_49_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_49_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__55_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_60_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_60_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__48_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_48_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_48_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__44_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_48_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_48_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__55_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__44_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__44_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__44_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p1853 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2478 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[182] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[32] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2479 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[85] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p3478 ) ,
+ .prog_clk_2_E_in ( p1114 ) , .prog_clk_2_S_in ( p391 ) ,
+ .prog_clk_2_W_in ( p1338 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2480 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2481 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2482 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2483 ) ,
+ .prog_clk_3_W_in ( p2736 ) , .prog_clk_3_E_in ( p258 ) ,
+ .prog_clk_3_S_in ( p663 ) , .prog_clk_3_N_in ( p3475 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2484 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2485 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2486 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2487 ) ,
+ .clk_1_N_in ( clk_2_wires[32] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2488 ) ,
+ .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) ,
+ .clk_2_N_in ( p3264 ) , .clk_2_E_in ( p590 ) , .clk_2_S_in ( p133 ) ,
+ .clk_2_W_in ( p3410 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2489 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2490 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2491 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2492 ) , .clk_3_W_in ( p3426 ) ,
+ .clk_3_E_in ( p858 ) , .clk_3_S_in ( p1218 ) , .clk_3_N_in ( p3263 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2493 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2494 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2495 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
+sb_1__1_ sb_5__2_ ( .chany_top_in ( cby_1__1__50_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_50_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_50_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__56_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_61_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_61_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__49_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_49_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_49_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__45_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_49_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_49_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__56_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__45_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__45_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__45_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p2274 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2497 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p3166 ) ,
+ .prog_clk_1_S_in ( p41 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2498 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2499 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2500 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2501 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2502 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[26] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2503 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[31] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2504 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2505 ) ,
+ .prog_clk_3_W_in ( p2134 ) , .prog_clk_3_E_in ( p238 ) ,
+ .prog_clk_3_S_in ( p2194 ) , .prog_clk_3_N_in ( p1887 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2506 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2507 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2508 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2509 ) , .clk_1_N_in ( p2769 ) ,
+ .clk_1_S_in ( p659 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2510 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2511 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2512 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2513 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2514 ) ,
+ .clk_2_W_in ( clk_2_wires[26] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2515 ) ,
+ .clk_2_S_out ( clk_2_wires[31] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2516 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2517 ) , .clk_3_W_in ( p2134 ) ,
+ .clk_3_E_in ( p794 ) , .clk_3_S_in ( p561 ) , .clk_3_N_in ( p3192 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2518 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2519 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2520 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
+sb_1__1_ sb_5__3_ ( .chany_top_in ( cby_1__1__51_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_51_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_51_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__57_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_62_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_62_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__50_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_50_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_50_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__46_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_50_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_50_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__57_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__46_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__46_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__46_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p2319 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2522 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[188] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[45] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2523 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[92] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3445 ) ,
+ .prog_clk_2_E_in ( p1461 ) , .prog_clk_2_S_in ( p510 ) ,
+ .prog_clk_2_W_in ( p399 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2524 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2525 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2526 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2527 ) ,
+ .prog_clk_3_W_in ( p3015 ) , .prog_clk_3_E_in ( p239 ) ,
+ .prog_clk_3_S_in ( p1234 ) , .prog_clk_3_N_in ( p3432 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2528 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2529 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2530 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2531 ) ,
+ .clk_1_N_in ( clk_2_wires[45] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2532 ) ,
+ .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) ,
+ .clk_2_N_in ( p2900 ) , .clk_2_E_in ( p715 ) , .clk_2_S_in ( p2196 ) ,
+ .clk_2_W_in ( p3246 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2533 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2534 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2535 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2536 ) , .clk_3_W_in ( p3268 ) ,
+ .clk_3_E_in ( p1089 ) , .clk_3_S_in ( p112 ) , .clk_3_N_in ( p2846 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2537 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2538 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2539 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
+sb_1__1_ sb_5__4_ ( .chany_top_in ( cby_1__1__52_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_52_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_52_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__58_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_63_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_63_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__51_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_51_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_51_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__47_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_51_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_51_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__58_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__47_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__47_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__47_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2371 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2541 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p3280 ) ,
+ .prog_clk_1_S_in ( p320 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2542 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2543 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2544 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2545 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2546 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[35] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2547 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[44] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[42] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2548 ) ,
+ .prog_clk_3_W_in ( p2512 ) , .prog_clk_3_E_in ( p326 ) ,
+ .prog_clk_3_S_in ( p2178 ) , .prog_clk_3_N_in ( p2819 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2549 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2550 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2551 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2552 ) , .clk_1_N_in ( p1300 ) ,
+ .clk_1_S_in ( p361 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2553 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2554 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2555 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2556 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2557 ) ,
+ .clk_2_W_in ( clk_2_wires[35] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2558 ) ,
+ .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2559 ) , .clk_3_W_in ( p2512 ) ,
+ .clk_3_E_in ( p1229 ) , .clk_3_S_in ( p8 ) , .clk_3_N_in ( p3257 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2560 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2561 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2562 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
+sb_1__1_ sb_5__5_ ( .chany_top_in ( cby_1__1__53_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_53_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_53_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__59_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_64_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_64_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__52_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_52_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_52_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__48_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_52_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_52_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__59_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__48_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__48_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__48_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2759 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2564 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[194] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2565 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[43] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[99] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p2706 ) ,
+ .prog_clk_2_E_in ( p607 ) , .prog_clk_2_S_in ( p965 ) ,
+ .prog_clk_2_W_in ( p305 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2566 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2567 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2568 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2569 ) ,
+ .prog_clk_3_W_in ( p3272 ) , .prog_clk_3_E_in ( p18 ) ,
+ .prog_clk_3_S_in ( p984 ) , .prog_clk_3_N_in ( p2688 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2570 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2571 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2572 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2573 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2574 ) ,
+ .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) ,
+ .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p3466 ) ,
+ .clk_2_E_in ( p1202 ) , .clk_2_S_in ( p2648 ) , .clk_2_W_in ( p3237 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2575 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2576 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2577 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2578 ) , .clk_3_W_in ( p2344 ) ,
+ .clk_3_E_in ( p807 ) , .clk_3_S_in ( p232 ) , .clk_3_N_in ( p3460 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2579 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2580 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2581 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
+sb_1__1_ sb_5__6_ ( .chany_top_in ( cby_1__1__54_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_54_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_54_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__60_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_65_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_65_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__53_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_53_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_53_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__49_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_53_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_53_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__60_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__49_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__49_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__49_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p2880 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2583 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p1690 ) ,
+ .prog_clk_1_S_in ( p511 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2584 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2585 ) ,
+ .prog_clk_2_N_in ( p1690 ) , .prog_clk_2_E_in ( p584 ) ,
+ .prog_clk_2_S_in ( p1109 ) , .prog_clk_2_W_in ( p913 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2586 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2587 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2588 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2589 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2590 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[3] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2591 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2592 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2593 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[6] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2594 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2595 ) , .clk_1_N_in ( p1690 ) ,
+ .clk_1_S_in ( p846 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2596 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2597 ) , .clk_2_N_in ( p1690 ) ,
+ .clk_2_E_in ( p1127 ) , .clk_2_S_in ( p2799 ) , .clk_2_W_in ( p416 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2598 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2599 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2600 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2601 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2602 ) ,
+ .clk_3_E_in ( clk_3_wires[3] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2603 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2604 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2605 ) ,
+ .clk_3_W_out ( clk_3_wires[6] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2606 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
+sb_1__1_ sb_5__7_ ( .chany_top_in ( cby_1__1__55_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_55_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_55_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__61_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_66_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_66_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__54_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_54_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_54_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__50_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_54_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_54_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__61_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__50_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__50_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__50_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2548 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2608 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[200] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[58] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2609 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[106] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p3484 ) ,
+ .prog_clk_2_E_in ( p1287 ) , .prog_clk_2_S_in ( p178 ) ,
+ .prog_clk_2_W_in ( p336 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2610 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2611 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2612 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2613 ) ,
+ .prog_clk_3_W_in ( p3296 ) , .prog_clk_3_E_in ( p925 ) ,
+ .prog_clk_3_S_in ( p719 ) , .prog_clk_3_N_in ( p3476 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2614 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2615 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2616 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2617 ) ,
+ .clk_1_N_in ( clk_2_wires[58] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2618 ) ,
+ .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) ,
+ .clk_2_N_in ( p3447 ) , .clk_2_E_in ( p44 ) , .clk_2_S_in ( p2471 ) ,
+ .clk_2_W_in ( p3247 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2619 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2620 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2621 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2622 ) , .clk_3_W_in ( p2735 ) ,
+ .clk_3_E_in ( p595 ) , .clk_3_S_in ( p1100 ) , .clk_3_N_in ( p3435 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2623 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2624 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2625 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
+sb_1__1_ sb_5__8_ ( .chany_top_in ( cby_1__1__56_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_56_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_56_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__62_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_67_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_67_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__55_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_55_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_55_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__51_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_55_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_55_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__62_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__51_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__51_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__51_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2409 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2627 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p3441 ) ,
+ .prog_clk_1_S_in ( p458 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2628 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2629 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2630 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2631 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2632 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[48] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2633 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[57] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[55] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2634 ) ,
+ .prog_clk_3_W_in ( p2355 ) , .prog_clk_3_E_in ( p376 ) ,
+ .prog_clk_3_S_in ( p2186 ) , .prog_clk_3_N_in ( p80 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2635 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2636 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2637 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2638 ) , .clk_1_N_in ( p2036 ) ,
+ .clk_1_S_in ( p851 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2639 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2640 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2641 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2642 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2643 ) ,
+ .clk_2_W_in ( clk_2_wires[48] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2644 ) ,
+ .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2645 ) , .clk_3_W_in ( p2355 ) ,
+ .clk_3_E_in ( p977 ) , .clk_3_S_in ( p284 ) , .clk_3_N_in ( p3436 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2646 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2647 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2648 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
+sb_1__1_ sb_5__9_ ( .chany_top_in ( cby_1__1__57_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_57_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_57_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__63_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_68_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_68_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__56_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_56_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_56_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__52_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_56_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_56_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__63_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__52_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__52_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__52_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p1803 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2650 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[206] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2651 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[56] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[113] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3275 ) ,
+ .prog_clk_2_E_in ( p1084 ) , .prog_clk_2_S_in ( p331 ) ,
+ .prog_clk_2_W_in ( p1957 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2652 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2653 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2654 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2655 ) ,
+ .prog_clk_3_W_in ( p2935 ) , .prog_clk_3_E_in ( p723 ) ,
+ .prog_clk_3_S_in ( p205 ) , .prog_clk_3_N_in ( p3238 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2656 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2657 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2658 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2659 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2660 ) ,
+ .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) ,
+ .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p2500 ) ,
+ .clk_2_E_in ( p839 ) , .clk_2_S_in ( p872 ) , .clk_2_W_in ( p2976 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2661 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2662 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2663 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2664 ) , .clk_3_W_in ( p3038 ) ,
+ .clk_3_E_in ( p100 ) , .clk_3_S_in ( p967 ) , .clk_3_N_in ( p2467 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2665 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2666 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2667 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
+sb_1__1_ sb_5__10_ ( .chany_top_in ( cby_1__1__58_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_58_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_58_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__64_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_69_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_69_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__57_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_57_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_57_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__53_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_57_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_57_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__64_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__53_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__53_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__53_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p1667 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2669 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p3342 ) ,
+ .prog_clk_1_S_in ( p325 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2670 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2671 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2672 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2673 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2674 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[61] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2675 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2676 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[66] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2677 ) ,
+ .prog_clk_3_W_in ( p2375 ) , .prog_clk_3_E_in ( p1212 ) ,
+ .prog_clk_3_S_in ( p1294 ) , .prog_clk_3_N_in ( p2220 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2678 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2679 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2680 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2681 ) , .clk_1_N_in ( p2785 ) ,
+ .clk_1_S_in ( p230 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2682 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2683 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2684 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2685 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2686 ) ,
+ .clk_2_W_in ( clk_2_wires[61] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2687 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2688 ) ,
+ .clk_2_N_out ( clk_2_wires[66] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_3_W_in ( p2375 ) ,
+ .clk_3_E_in ( p244 ) , .clk_3_S_in ( p515 ) , .clk_3_N_in ( p3315 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2690 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2691 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2692 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
+sb_1__1_ sb_5__11_ ( .chany_top_in ( cby_1__1__59_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_59_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_59_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__65_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_70_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_70_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__58_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_58_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_58_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__54_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_58_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_58_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__65_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__54_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__54_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__54_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p1783 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2694 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[212] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2695 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[67] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[120] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p2372 ) ,
+ .prog_clk_2_E_in ( p1204 ) , .prog_clk_2_S_in ( p734 ) ,
+ .prog_clk_2_W_in ( p1144 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2696 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2697 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2698 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2699 ) ,
+ .prog_clk_3_W_in ( p3380 ) , .prog_clk_3_E_in ( p1037 ) ,
+ .prog_clk_3_S_in ( p390 ) , .prog_clk_3_N_in ( p2230 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2700 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2701 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2702 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2703 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2704 ) ,
+ .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) ,
+ .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3329 ) ,
+ .clk_2_E_in ( p571 ) , .clk_2_S_in ( p426 ) , .clk_2_W_in ( p3368 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2705 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2706 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2707 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2708 ) , .clk_3_W_in ( p2896 ) ,
+ .clk_3_E_in ( p255 ) , .clk_3_S_in ( p1067 ) , .clk_3_N_in ( p3322 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2709 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2710 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2711 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
+sb_1__1_ sb_6__1_ ( .chany_top_in ( cby_1__1__61_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_61_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_61_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__66_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_72_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_72_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__60_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_60_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_60_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__55_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_60_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_60_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__66_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__55_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__55_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__55_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__55_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__55_ccff_tail ) , .Test_en_S_in ( Test_enWires[2] ) ,
+ .Test_en_N_out ( Test_enWires[3] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1245 ) ,
+ .prog_clk_1_S_in ( p282 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2713 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2714 ) ,
+ .prog_clk_2_N_in ( p1245 ) , .prog_clk_2_E_in ( p226 ) ,
+ .prog_clk_2_S_in ( p1937 ) , .prog_clk_2_W_in ( p614 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2715 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2716 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2717 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2718 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2719 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2720 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[89] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2721 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2722 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2723 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[92] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2724 ) , .clk_1_N_in ( p1245 ) ,
+ .clk_1_S_in ( p1155 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2725 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2726 ) , .clk_2_N_in ( p1245 ) ,
+ .clk_2_E_in ( p680 ) , .clk_2_S_in ( p1302 ) , .clk_2_W_in ( p285 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2727 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2728 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2729 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2730 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2731 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2732 ) ,
+ .clk_3_S_in ( clk_3_wires[89] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2733 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2734 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2735 ) ,
+ .clk_3_N_out ( clk_3_wires[92] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
+sb_1__1_ sb_6__2_ ( .chany_top_in ( cby_1__1__62_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_62_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_62_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__67_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_73_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_73_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__61_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_61_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_61_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__56_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_61_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_61_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__67_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__56_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__56_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__56_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__56_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__56_ccff_tail ) , .Test_en_S_in ( Test_enWires[4] ) ,
+ .Test_en_N_out ( Test_enWires[5] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1636 ) ,
+ .prog_clk_1_S_in ( p172 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2737 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2738 ) ,
+ .prog_clk_2_N_in ( p1636 ) , .prog_clk_2_E_in ( p1321 ) ,
+ .prog_clk_2_S_in ( p1940 ) , .prog_clk_2_W_in ( p195 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2739 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2740 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2741 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2742 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2743 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2744 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[91] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2745 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2746 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2747 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[94] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2748 ) , .clk_1_N_in ( p1636 ) ,
+ .clk_1_S_in ( p744 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2749 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2750 ) , .clk_2_N_in ( p1636 ) ,
+ .clk_2_E_in ( p527 ) , .clk_2_S_in ( p505 ) , .clk_2_W_in ( p444 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2751 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2752 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2753 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2754 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2755 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2756 ) ,
+ .clk_3_S_in ( clk_3_wires[91] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2757 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2758 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2759 ) ,
+ .clk_3_N_out ( clk_3_wires[94] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
+sb_1__1_ sb_6__3_ ( .chany_top_in ( cby_1__1__63_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_63_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_63_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__68_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_74_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_74_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__62_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_62_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_62_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__57_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_62_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_62_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__68_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__57_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__57_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__57_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__57_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__57_ccff_tail ) , .Test_en_S_in ( Test_enWires[6] ) ,
+ .Test_en_N_out ( Test_enWires[7] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1819 ) ,
+ .prog_clk_1_S_in ( p605 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2761 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2762 ) ,
+ .prog_clk_2_N_in ( p1819 ) , .prog_clk_2_E_in ( p431 ) ,
+ .prog_clk_2_S_in ( p1323 ) , .prog_clk_2_W_in ( p57 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2763 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2764 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2765 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2766 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2767 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2768 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[93] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2769 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2770 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2771 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[96] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2772 ) , .clk_1_N_in ( p1819 ) ,
+ .clk_1_S_in ( p643 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2773 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2774 ) , .clk_2_N_in ( p1819 ) ,
+ .clk_2_E_in ( p1297 ) , .clk_2_S_in ( p219 ) , .clk_2_W_in ( p1200 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2775 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2776 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2777 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2778 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2779 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2780 ) ,
+ .clk_3_S_in ( clk_3_wires[93] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2781 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2782 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2783 ) ,
+ .clk_3_N_out ( clk_3_wires[96] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
+sb_1__1_ sb_6__4_ ( .chany_top_in ( cby_1__1__64_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_64_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_64_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__69_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_75_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_75_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__63_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_63_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_63_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__58_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_63_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_63_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__69_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__58_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__58_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__58_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__58_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__58_ccff_tail ) , .Test_en_S_in ( Test_enWires[8] ) ,
+ .Test_en_N_out ( Test_enWires[9] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1436 ) ,
+ .prog_clk_1_S_in ( p784 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2785 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2786 ) ,
+ .prog_clk_2_N_in ( p1436 ) , .prog_clk_2_E_in ( p97 ) ,
+ .prog_clk_2_S_in ( p2198 ) , .prog_clk_2_W_in ( p149 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2787 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2788 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2789 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2790 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2791 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2792 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[95] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2793 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2794 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2795 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[98] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2796 ) , .clk_1_N_in ( p1436 ) ,
+ .clk_1_S_in ( p654 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2797 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2798 ) , .clk_2_N_in ( p1436 ) ,
+ .clk_2_E_in ( p1276 ) , .clk_2_S_in ( p1111 ) , .clk_2_W_in ( p1320 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2799 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2800 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2801 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2802 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2803 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2804 ) ,
+ .clk_3_S_in ( clk_3_wires[95] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2805 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2806 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2807 ) ,
+ .clk_3_N_out ( clk_3_wires[98] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
+sb_1__1_ sb_6__5_ ( .chany_top_in ( cby_1__1__65_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_65_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_65_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__70_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_76_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_76_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__64_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_64_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_64_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__59_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_64_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_64_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__70_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__59_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__59_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__59_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__59_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__59_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[10] ) , .Test_en_N_out ( Test_enWires[11] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p2011 ) ,
+ .prog_clk_1_S_in ( p776 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2809 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2810 ) ,
+ .prog_clk_2_N_in ( p2011 ) , .prog_clk_2_E_in ( p278 ) ,
+ .prog_clk_2_S_in ( p2219 ) , .prog_clk_2_W_in ( p889 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2811 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2812 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2813 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2814 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2815 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2816 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[97] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2817 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2818 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2819 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[100] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2820 ) , .clk_1_N_in ( p2011 ) ,
+ .clk_1_S_in ( p28 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2821 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2822 ) , .clk_2_N_in ( p2011 ) ,
+ .clk_2_E_in ( p782 ) , .clk_2_S_in ( p1196 ) , .clk_2_W_in ( p335 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2823 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2824 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2825 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2826 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2827 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2828 ) ,
+ .clk_3_S_in ( clk_3_wires[97] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2829 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) ,
+ .clk_3_N_out ( clk_3_wires[100] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
+sb_1__1_ sb_6__6_ ( .chany_top_in ( cby_1__1__66_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_66_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_66_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__71_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_77_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_77_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__65_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_65_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_65_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__60_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_65_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_65_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__71_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__60_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__60_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__60_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__60_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__60_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[12] ) , .Test_en_N_out ( Test_enWires[13] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1748 ) ,
+ .prog_clk_1_S_in ( p618 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2833 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2834 ) ,
+ .prog_clk_2_N_in ( p1617 ) , .prog_clk_2_E_in ( p215 ) ,
+ .prog_clk_2_S_in ( p1897 ) , .prog_clk_2_W_in ( p2176 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2835 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2836 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2837 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2838 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2839 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2840 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[99] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2841 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[0] ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[2] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2842 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2843 ) , .clk_1_N_in ( p1748 ) ,
+ .clk_1_S_in ( p822 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2844 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2845 ) , .clk_2_N_in ( p1748 ) ,
+ .clk_2_E_in ( p482 ) , .clk_2_S_in ( p321 ) , .clk_2_W_in ( p677 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2846 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2847 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2848 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2849 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2850 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2851 ) ,
+ .clk_3_S_in ( clk_3_wires[99] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2852 ) ,
+ .clk_3_E_out ( clk_3_wires[0] ) , .clk_3_W_out ( clk_3_wires[2] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2853 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
+sb_1__1_ sb_6__7_ ( .chany_top_in ( cby_1__1__67_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_67_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_67_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__72_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_78_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_78_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__66_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_66_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_66_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__61_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_66_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_66_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__72_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__61_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__61_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__61_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__61_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__61_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[14] ) , .Test_en_N_out ( Test_enWires[15] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p3278 ) ,
+ .prog_clk_1_S_in ( p453 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2855 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2856 ) ,
+ .prog_clk_2_N_in ( p3412 ) , .prog_clk_2_E_in ( p1194 ) ,
+ .prog_clk_2_S_in ( p808 ) , .prog_clk_2_W_in ( p735 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2857 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2858 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2859 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2860 ) ,
+ .prog_clk_3_W_in ( p3106 ) , .prog_clk_3_E_in ( p543 ) ,
+ .prog_clk_3_S_in ( p1199 ) , .prog_clk_3_N_in ( p3399 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2861 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2862 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2863 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2864 ) , .clk_1_N_in ( p2367 ) ,
+ .clk_1_S_in ( p396 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2865 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2866 ) , .clk_2_N_in ( p3515 ) ,
+ .clk_2_E_in ( p99 ) , .clk_2_S_in ( p504 ) , .clk_2_W_in ( p3085 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2867 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2868 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2869 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2870 ) , .clk_3_W_in ( p3146 ) ,
+ .clk_3_E_in ( p1120 ) , .clk_3_S_in ( p452 ) , .clk_3_N_in ( p3513 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2871 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2872 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2873 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
+sb_1__1_ sb_6__8_ ( .chany_top_in ( cby_1__1__68_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_68_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_68_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__73_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_79_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_79_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__67_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_67_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_67_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__62_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_67_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_67_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__73_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__62_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__62_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__62_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__62_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__62_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[16] ) , .Test_en_N_out ( Test_enWires[17] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p3413 ) ,
+ .prog_clk_1_S_in ( p871 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2875 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2876 ) ,
+ .prog_clk_2_N_in ( p2410 ) , .prog_clk_2_E_in ( p624 ) ,
+ .prog_clk_2_S_in ( p465 ) , .prog_clk_2_W_in ( p1979 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2877 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2878 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2879 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2880 ) ,
+ .prog_clk_3_W_in ( p3006 ) , .prog_clk_3_E_in ( p1250 ) ,
+ .prog_clk_3_S_in ( p1307 ) , .prog_clk_3_N_in ( p2221 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2881 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2882 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2883 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2884 ) , .clk_1_N_in ( p2860 ) ,
+ .clk_1_S_in ( p281 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2885 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2886 ) , .clk_2_N_in ( p3507 ) ,
+ .clk_2_E_in ( p892 ) , .clk_2_S_in ( p888 ) , .clk_2_W_in ( p2962 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2887 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2888 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2889 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .clk_3_W_in ( p2761 ) ,
+ .clk_3_E_in ( p117 ) , .clk_3_S_in ( p9 ) , .clk_3_N_in ( p3503 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2891 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2892 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2893 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
+sb_1__1_ sb_6__9_ ( .chany_top_in ( cby_1__1__69_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_69_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_69_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__74_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_80_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_80_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__68_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_68_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_68_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__63_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_68_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_68_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__74_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__63_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__63_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__63_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__63_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__63_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[18] ) , .Test_en_N_out ( Test_enWires[19] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p2564 ) ,
+ .prog_clk_1_S_in ( p486 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2895 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2896 ) ,
+ .prog_clk_2_N_in ( p3337 ) , .prog_clk_2_E_in ( p790 ) ,
+ .prog_clk_2_S_in ( p189 ) , .prog_clk_2_W_in ( p266 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2897 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2898 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2899 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2900 ) ,
+ .prog_clk_3_W_in ( p3148 ) , .prog_clk_3_E_in ( p954 ) ,
+ .prog_clk_3_S_in ( p610 ) , .prog_clk_3_N_in ( p3318 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2901 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2902 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2903 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2904 ) , .clk_1_N_in ( p2385 ) ,
+ .clk_1_S_in ( p1015 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2905 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2906 ) , .clk_2_N_in ( p3141 ) ,
+ .clk_2_E_in ( p697 ) , .clk_2_S_in ( p1160 ) , .clk_2_W_in ( p3066 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2907 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2908 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2909 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2910 ) , .clk_3_W_in ( p3049 ) ,
+ .clk_3_E_in ( p241 ) , .clk_3_S_in ( p983 ) , .clk_3_N_in ( p3088 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2911 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2912 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2913 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
+sb_1__1_ sb_6__10_ ( .chany_top_in ( cby_1__1__70_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_70_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_70_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__75_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_81_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_81_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__69_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_69_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_69_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__64_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_69_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_69_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__75_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__64_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__64_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__64_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__64_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__64_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[20] ) , .Test_en_N_out ( Test_enWires[21] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p3142 ) ,
+ .prog_clk_1_S_in ( p1105 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2915 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2916 ) ,
+ .prog_clk_2_N_in ( p2278 ) , .prog_clk_2_E_in ( p957 ) ,
+ .prog_clk_2_S_in ( p1131 ) , .prog_clk_2_W_in ( p1904 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2917 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2918 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2919 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2920 ) ,
+ .prog_clk_3_W_in ( p3423 ) , .prog_clk_3_E_in ( p811 ) ,
+ .prog_clk_3_S_in ( p435 ) , .prog_clk_3_N_in ( p2206 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2921 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2922 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2923 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2924 ) , .clk_1_N_in ( p2051 ) ,
+ .clk_1_S_in ( p455 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2925 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2926 ) , .clk_2_N_in ( p3499 ) ,
+ .clk_2_E_in ( p879 ) , .clk_2_S_in ( p141 ) , .clk_2_W_in ( p3407 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2927 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2928 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2929 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2930 ) , .clk_3_W_in ( p3214 ) ,
+ .clk_3_E_in ( p94 ) , .clk_3_S_in ( p848 ) , .clk_3_N_in ( p3497 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2931 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2932 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2933 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
+sb_1__1_ sb_6__11_ ( .chany_top_in ( cby_1__1__71_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_71_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_71_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__76_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_82_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_82_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__70_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_70_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_70_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__65_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_70_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_70_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__76_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__65_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__65_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__65_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__65_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__65_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[22] ) , .Test_en_N_out ( Test_enWires[23] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p2567 ) ,
+ .prog_clk_1_S_in ( p854 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2935 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2936 ) ,
+ .prog_clk_2_N_in ( p3205 ) , .prog_clk_2_E_in ( p1055 ) ,
+ .prog_clk_2_S_in ( p216 ) , .prog_clk_2_W_in ( p1977 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2937 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2938 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2939 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2940 ) ,
+ .prog_clk_3_W_in ( p3222 ) , .prog_clk_3_E_in ( p937 ) ,
+ .prog_clk_3_S_in ( p89 ) , .prog_clk_3_N_in ( p3172 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2941 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2942 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2943 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2944 ) , .clk_1_N_in ( p2339 ) ,
+ .clk_1_S_in ( p309 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2945 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2946 ) , .clk_2_N_in ( p3446 ) ,
+ .clk_2_E_in ( p199 ) , .clk_2_S_in ( p963 ) , .clk_2_W_in ( p3167 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2947 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2948 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2949 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2950 ) , .clk_3_W_in ( p2997 ) ,
+ .clk_3_E_in ( p495 ) , .clk_3_S_in ( p1383 ) , .clk_3_N_in ( p3433 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2951 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2952 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2953 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
+sb_1__1_ sb_7__1_ ( .chany_top_in ( cby_1__1__73_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_73_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_73_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__77_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_84_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_84_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__72_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_72_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_72_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__66_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_72_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_72_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__77_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__66_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__66_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__66_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p2772 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2955 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[258] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[74] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2956 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[127] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3516 ) ,
+ .prog_clk_2_E_in ( p573 ) , .prog_clk_2_S_in ( p2 ) ,
+ .prog_clk_2_W_in ( p429 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2957 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2958 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2959 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2960 ) ,
+ .prog_clk_3_W_in ( p2933 ) , .prog_clk_3_E_in ( p732 ) ,
+ .prog_clk_3_S_in ( p1309 ) , .prog_clk_3_N_in ( p3514 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2961 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2962 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2963 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2964 ) ,
+ .clk_1_N_in ( clk_2_wires[74] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2965 ) ,
+ .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) ,
+ .clk_2_N_in ( p2989 ) , .clk_2_E_in ( p1065 ) , .clk_2_S_in ( p2660 ) ,
+ .clk_2_W_in ( p2831 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2966 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2967 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2968 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2969 ) , .clk_3_W_in ( p2781 ) ,
+ .clk_3_E_in ( p1137 ) , .clk_3_S_in ( p340 ) , .clk_3_N_in ( p2949 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2970 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2971 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2972 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
+sb_1__1_ sb_7__2_ ( .chany_top_in ( cby_1__1__74_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_74_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_74_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__78_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_85_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_85_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__73_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_73_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_73_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__67_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_73_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_73_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__78_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__67_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__67_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__67_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p2756 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2974 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p2580 ) ,
+ .prog_clk_1_S_in ( p615 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2975 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2976 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2977 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[72] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2978 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2979 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2980 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[73] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2981 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2982 ) ,
+ .prog_clk_3_W_in ( p1683 ) , .prog_clk_3_E_in ( p176 ) ,
+ .prog_clk_3_S_in ( p2656 ) , .prog_clk_3_N_in ( p1931 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2983 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2984 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2985 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2986 ) , .clk_1_N_in ( p2019 ) ,
+ .clk_1_S_in ( p777 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2987 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2988 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2989 ) ,
+ .clk_2_E_in ( clk_2_wires[72] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2990 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2991 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2992 ) ,
+ .clk_2_S_out ( clk_2_wires[73] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2993 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2994 ) , .clk_3_W_in ( p1683 ) ,
+ .clk_3_E_in ( p1926 ) , .clk_3_S_in ( p762 ) , .clk_3_N_in ( p2439 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2995 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2996 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2997 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
+sb_1__1_ sb_7__3_ ( .chany_top_in ( cby_1__1__75_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_75_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_75_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__79_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_86_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_86_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__74_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_74_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_74_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__68_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_74_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_74_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__79_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__68_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__68_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__68_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2987 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2999 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[264] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[85] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3000 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[134] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3333 ) ,
+ .prog_clk_2_E_in ( p1152 ) , .prog_clk_2_S_in ( p490 ) ,
+ .prog_clk_2_W_in ( p472 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3001 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3002 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3003 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3004 ) ,
+ .prog_clk_3_W_in ( p3223 ) , .prog_clk_3_E_in ( p912 ) ,
+ .prog_clk_3_S_in ( p87 ) , .prog_clk_3_N_in ( p3312 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3005 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3006 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3007 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3008 ) ,
+ .clk_1_N_in ( clk_2_wires[85] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3009 ) ,
+ .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) ,
+ .clk_2_N_in ( p3518 ) , .clk_2_E_in ( p300 ) , .clk_2_S_in ( p2942 ) ,
+ .clk_2_W_in ( p3183 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3010 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3011 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3012 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3013 ) , .clk_3_W_in ( p3037 ) ,
+ .clk_3_E_in ( p850 ) , .clk_3_S_in ( p1406 ) , .clk_3_N_in ( p3517 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3014 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3015 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3016 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
+sb_1__1_ sb_7__4_ ( .chany_top_in ( cby_1__1__76_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_76_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_76_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__80_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_87_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_87_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__75_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_75_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_75_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__69_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_75_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_75_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__80_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__69_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__69_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__69_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p2050 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3018 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p2793 ) ,
+ .prog_clk_1_S_in ( p648 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3019 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3020 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3021 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[81] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3022 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3023 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3024 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[84] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[82] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3025 ) ,
+ .prog_clk_3_W_in ( p1691 ) , .prog_clk_3_E_in ( p761 ) ,
+ .prog_clk_3_S_in ( p1916 ) , .prog_clk_3_N_in ( p838 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3026 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3027 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3028 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3029 ) , .clk_1_N_in ( p1296 ) ,
+ .clk_1_S_in ( p483 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3030 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3031 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3032 ) ,
+ .clk_2_E_in ( clk_2_wires[81] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3033 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3034 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3035 ) ,
+ .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3036 ) , .clk_3_W_in ( p1691 ) ,
+ .clk_3_E_in ( p1919 ) , .clk_3_S_in ( p578 ) , .clk_3_N_in ( p2631 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3037 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3038 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3039 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
+sb_1__1_ sb_7__5_ ( .chany_top_in ( cby_1__1__77_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_77_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_77_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__81_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_88_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_88_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__76_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_76_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_76_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__70_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_76_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_76_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__81_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__70_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__70_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__70_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p1750 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3041 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[270] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3042 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[83] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[141] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3511 ) ,
+ .prog_clk_2_E_in ( p1077 ) , .prog_clk_2_S_in ( p477 ) ,
+ .prog_clk_2_W_in ( p1198 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3043 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3044 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3045 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3046 ) ,
+ .prog_clk_3_W_in ( p3352 ) , .prog_clk_3_E_in ( p46 ) ,
+ .prog_clk_3_S_in ( p867 ) , .prog_clk_3_N_in ( p3510 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3047 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3048 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3049 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3050 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3051 ) ,
+ .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) ,
+ .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3481 ) ,
+ .clk_2_E_in ( p283 ) , .clk_2_S_in ( p1401 ) , .clk_2_W_in ( p3302 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3052 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3053 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3054 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3055 ) , .clk_3_W_in ( p3145 ) ,
+ .clk_3_E_in ( p1000 ) , .clk_3_S_in ( p137 ) , .clk_3_N_in ( p3474 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3056 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3057 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3058 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
+sb_1__1_ sb_7__6_ ( .chany_top_in ( cby_1__1__78_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_78_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_78_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__82_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_89_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_89_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__77_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_77_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_77_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__71_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_77_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_77_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__82_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__71_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__71_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__71_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2513 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3060 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1457 ) ,
+ .prog_clk_1_S_in ( p972 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3061 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3062 ) ,
+ .prog_clk_2_N_in ( p1838 ) , .prog_clk_2_E_in ( p955 ) ,
+ .prog_clk_2_S_in ( p1075 ) , .prog_clk_2_W_in ( p2209 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3063 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3064 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3065 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3066 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[1] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3067 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3068 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3069 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[4] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3070 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3071 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3072 ) , .clk_1_N_in ( p1457 ) ,
+ .clk_1_S_in ( p646 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3073 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3074 ) , .clk_2_N_in ( p1457 ) ,
+ .clk_2_E_in ( p265 ) , .clk_2_S_in ( p2495 ) , .clk_2_W_in ( p1124 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3075 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3076 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3077 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3078 ) ,
+ .clk_3_W_in ( clk_3_wires[1] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3079 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3080 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3081 ) ,
+ .clk_3_E_out ( clk_3_wires[4] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3082 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3083 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
+sb_1__1_ sb_7__7_ ( .chany_top_in ( cby_1__1__79_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_79_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_79_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__83_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_90_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_90_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__78_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_78_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_78_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__72_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_78_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_78_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__83_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__72_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__72_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__72_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p2571 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3085 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[276] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[98] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3086 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[148] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p2921 ) ,
+ .prog_clk_2_E_in ( p1054 ) , .prog_clk_2_S_in ( p220 ) ,
+ .prog_clk_2_W_in ( p834 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3087 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3088 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3089 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3090 ) ,
+ .prog_clk_3_W_in ( p3118 ) , .prog_clk_3_E_in ( p454 ) ,
+ .prog_clk_3_S_in ( p689 ) , .prog_clk_3_N_in ( p2815 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3091 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3092 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3093 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3094 ) ,
+ .clk_1_N_in ( clk_2_wires[98] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3095 ) ,
+ .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) ,
+ .clk_2_N_in ( p3508 ) , .clk_2_E_in ( p126 ) , .clk_2_S_in ( p2479 ) ,
+ .clk_2_W_in ( p3071 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3096 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3097 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3098 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3099 ) , .clk_3_W_in ( p2318 ) ,
+ .clk_3_E_in ( p894 ) , .clk_3_S_in ( p55 ) , .clk_3_N_in ( p3505 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3100 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3101 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3102 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3103 ) ) ;
+sb_1__1_ sb_7__8_ ( .chany_top_in ( cby_1__1__80_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_80_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_80_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__84_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_91_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_91_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__79_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_79_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_79_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__73_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_79_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_79_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__84_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__73_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__73_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__73_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p2743 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3104 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p3379 ) ,
+ .prog_clk_1_S_in ( p647 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3105 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3106 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3107 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[94] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3108 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3109 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3110 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[97] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[95] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3111 ) ,
+ .prog_clk_3_W_in ( p1562 ) , .prog_clk_3_E_in ( p234 ) ,
+ .prog_clk_3_S_in ( p2646 ) , .prog_clk_3_N_in ( p1901 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3112 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3113 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3114 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3115 ) , .clk_1_N_in ( p2421 ) ,
+ .clk_1_S_in ( p151 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3116 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3117 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3118 ) ,
+ .clk_2_E_in ( clk_2_wires[94] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3119 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3120 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3121 ) ,
+ .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3122 ) , .clk_3_W_in ( p2523 ) ,
+ .clk_3_E_in ( p565 ) , .clk_3_S_in ( p1464 ) , .clk_3_N_in ( p3367 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3123 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3124 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3125 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
+sb_1__1_ sb_7__9_ ( .chany_top_in ( cby_1__1__81_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_81_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_81_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__85_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_92_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_92_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__80_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_80_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_80_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__74_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_80_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_80_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__85_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__74_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__74_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__74_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p2559 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3127 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[282] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3128 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[96] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[155] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p3130 ) ,
+ .prog_clk_2_E_in ( p938 ) , .prog_clk_2_S_in ( p775 ) ,
+ .prog_clk_2_W_in ( p177 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3129 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3130 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3131 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3132 ) ,
+ .prog_clk_3_W_in ( p3047 ) , .prog_clk_3_E_in ( p975 ) ,
+ .prog_clk_3_S_in ( p191 ) , .prog_clk_3_N_in ( p3078 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3133 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3134 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3135 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3136 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3137 ) ,
+ .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) ,
+ .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3491 ) ,
+ .clk_2_E_in ( p1210 ) , .clk_2_S_in ( p2469 ) , .clk_2_W_in ( p2955 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3138 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3139 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3140 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3141 ) , .clk_3_W_in ( p2020 ) ,
+ .clk_3_E_in ( p14 ) , .clk_3_S_in ( p1097 ) , .clk_3_N_in ( p3488 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3142 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3143 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3144 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
+sb_1__1_ sb_7__10_ ( .chany_top_in ( cby_1__1__82_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_82_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_82_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__86_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_93_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_93_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__81_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_81_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_81_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__75_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_81_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_81_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__86_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__75_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__75_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__75_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p2366 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3146 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p3204 ) ,
+ .prog_clk_1_S_in ( p73 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3147 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3148 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3149 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[107] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3150 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3151 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3152 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3153 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[108] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3154 ) ,
+ .prog_clk_3_W_in ( p2081 ) , .prog_clk_3_E_in ( p852 ) ,
+ .prog_clk_3_S_in ( p2183 ) , .prog_clk_3_N_in ( p2241 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3155 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3156 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3157 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3158 ) , .clk_1_N_in ( p2885 ) ,
+ .clk_1_S_in ( p501 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3159 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3160 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3161 ) ,
+ .clk_2_E_in ( clk_2_wires[107] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3162 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3163 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3164 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3165 ) ,
+ .clk_2_N_out ( clk_2_wires[108] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .clk_3_W_in ( p2081 ) ,
+ .clk_3_E_in ( p279 ) , .clk_3_S_in ( p295 ) , .clk_3_N_in ( p3171 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3167 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3168 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3169 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3170 ) ) ;
+sb_1__1_ sb_7__11_ ( .chany_top_in ( cby_1__1__83_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_83_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_83_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__87_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_94_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_94_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__82_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_82_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_82_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__76_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_82_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_82_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__87_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__76_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__76_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__76_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p2416 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3171 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[288] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3172 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[109] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[162] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3470 ) ,
+ .prog_clk_2_E_in ( p797 ) , .prog_clk_2_S_in ( p40 ) ,
+ .prog_clk_2_W_in ( p245 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3173 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3174 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3175 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3176 ) ,
+ .prog_clk_3_W_in ( p3013 ) , .prog_clk_3_E_in ( p39 ) ,
+ .prog_clk_3_S_in ( p1191 ) , .prog_clk_3_N_in ( p3455 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3177 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3178 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3179 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3180 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3181 ) ,
+ .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) ,
+ .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p3451 ) ,
+ .clk_2_E_in ( p1206 ) , .clk_2_S_in ( p2247 ) , .clk_2_W_in ( p3360 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3182 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3183 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3184 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3185 ) , .clk_3_W_in ( p3391 ) ,
+ .clk_3_E_in ( p886 ) , .clk_3_S_in ( p754 ) , .clk_3_N_in ( p3428 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3186 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3187 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3188 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3189 ) ) ;
+sb_1__1_ sb_8__1_ ( .chany_top_in ( cby_1__1__85_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_85_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_85_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__88_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_96_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_96_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__84_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_84_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_84_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__77_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_84_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_84_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__88_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__77_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__77_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__77_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p2908 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3190 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p3194 ) ,
+ .prog_clk_1_S_in ( p1093 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3191 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3192 ) ,
+ .prog_clk_2_N_in ( p3351 ) , .prog_clk_2_E_in ( p809 ) ,
+ .prog_clk_2_S_in ( p786 ) , .prog_clk_2_W_in ( p492 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3193 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3194 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3195 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3196 ) ,
+ .prog_clk_3_W_in ( p3114 ) , .prog_clk_3_E_in ( p1094 ) ,
+ .prog_clk_3_S_in ( p327 ) , .prog_clk_3_N_in ( p3300 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3197 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3198 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3199 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3200 ) , .clk_1_N_in ( p2393 ) ,
+ .clk_1_S_in ( p430 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3201 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3202 ) , .clk_2_N_in ( p3348 ) ,
+ .clk_2_E_in ( p628 ) , .clk_2_S_in ( p2833 ) , .clk_2_W_in ( p3055 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3203 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3204 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3205 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3206 ) , .clk_3_W_in ( p1669 ) ,
+ .clk_3_E_in ( p352 ) , .clk_3_S_in ( p1066 ) , .clk_3_N_in ( p3324 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3207 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3208 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3209 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
+sb_1__1_ sb_8__2_ ( .chany_top_in ( cby_1__1__86_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_86_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_86_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__89_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_97_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_97_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__85_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_85_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_85_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__78_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_85_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_85_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__89_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__78_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__78_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__78_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p2992 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3211 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p3422 ) ,
+ .prog_clk_1_S_in ( p832 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3212 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3213 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[43] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3214 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3215 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3216 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[71] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3217 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3218 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p1560 ) ,
+ .prog_clk_3_E_in ( p211 ) , .prog_clk_3_S_in ( p2975 ) ,
+ .prog_clk_3_N_in ( p299 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3219 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3220 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3221 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3222 ) , .clk_1_N_in ( p2337 ) ,
+ .clk_1_S_in ( p138 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3223 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3224 ) ,
+ .clk_2_N_in ( clk_3_wires[43] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3225 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3226 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3227 ) ,
+ .clk_2_W_out ( clk_2_wires[71] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3228 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3229 ) ,
+ .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p1560 ) ,
+ .clk_3_E_in ( p567 ) , .clk_3_S_in ( p409 ) , .clk_3_N_in ( p3408 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3230 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3231 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3232 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3233 ) ) ;
+sb_1__1_ sb_8__3_ ( .chany_top_in ( cby_1__1__87_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_87_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_87_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__90_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_98_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_98_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__86_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_86_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_86_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__79_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_86_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_86_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__90_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__79_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__79_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__79_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2588 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3234 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p2044 ) ,
+ .prog_clk_1_S_in ( p317 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3235 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3236 ) ,
+ .prog_clk_2_N_in ( p2044 ) , .prog_clk_2_E_in ( p987 ) ,
+ .prog_clk_2_S_in ( p1924 ) , .prog_clk_2_W_in ( p1007 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3237 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3238 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3239 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3240 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3241 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3242 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3243 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[39] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3244 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3245 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3246 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p2044 ) ,
+ .clk_1_S_in ( p883 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3247 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3248 ) , .clk_2_N_in ( p2044 ) ,
+ .clk_2_E_in ( p47 ) , .clk_2_S_in ( p2452 ) , .clk_2_W_in ( p517 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3249 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3250 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3251 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3252 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3253 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3254 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3255 ) ,
+ .clk_3_N_in ( clk_3_wires[39] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3256 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3257 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3258 ) ,
+ .clk_3_S_out ( clk_3_wires[42] ) ) ;
+sb_1__1_ sb_8__4_ ( .chany_top_in ( cby_1__1__88_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_88_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_88_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__91_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_99_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_99_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__87_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_87_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_87_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__80_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_87_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_87_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__91_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__80_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__80_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__80_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p1225 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3259 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p2103 ) ,
+ .prog_clk_1_S_in ( p6 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3260 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3261 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[33] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3262 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3263 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3264 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[80] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3265 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3266 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[78] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3267 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3268 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3269 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[33] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3270 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3271 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3272 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p2103 ) ,
+ .clk_1_S_in ( p771 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3273 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3274 ) ,
+ .clk_2_N_in ( clk_3_wires[33] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3275 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3276 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3277 ) ,
+ .clk_2_W_out ( clk_2_wires[80] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3278 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3279 ) ,
+ .clk_2_E_out ( clk_2_wires[78] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3280 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3281 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3282 ) ,
+ .clk_3_N_in ( clk_3_wires[33] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3283 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3284 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3285 ) ,
+ .clk_3_S_out ( clk_3_wires[38] ) ) ;
+sb_1__1_ sb_8__5_ ( .chany_top_in ( cby_1__1__89_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_89_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_89_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__92_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_100_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_100_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__88_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_88_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_88_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__81_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_88_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_88_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__92_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__81_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__81_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__81_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2412 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3286 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1405 ) ,
+ .prog_clk_1_S_in ( p929 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3287 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3288 ) ,
+ .prog_clk_2_N_in ( p1405 ) , .prog_clk_2_E_in ( p1187 ) ,
+ .prog_clk_2_S_in ( p820 ) , .prog_clk_2_W_in ( p414 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3289 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3290 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3291 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3292 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3293 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3294 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3295 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[29] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3296 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3297 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3298 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1844 ) ,
+ .clk_1_S_in ( p218 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3299 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3300 ) , .clk_2_N_in ( p1405 ) ,
+ .clk_2_E_in ( p161 ) , .clk_2_S_in ( p2175 ) , .clk_2_W_in ( p939 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3301 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3302 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3303 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3304 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3305 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3306 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3307 ) ,
+ .clk_3_N_in ( clk_3_wires[29] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3308 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3309 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3310 ) ,
+ .clk_3_S_out ( clk_3_wires[32] ) ) ;
+sb_1__1_ sb_8__6_ ( .chany_top_in ( cby_1__1__90_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_90_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_90_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__93_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_101_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_101_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__89_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_89_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_89_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__82_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_89_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_89_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__93_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__82_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__82_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__82_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p1742 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3311 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1559 ) ,
+ .prog_clk_1_S_in ( p549 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3312 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3313 ) ,
+ .prog_clk_2_N_in ( p1559 ) , .prog_clk_2_E_in ( p17 ) ,
+ .prog_clk_2_S_in ( p2212 ) , .prog_clk_2_W_in ( p1930 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3314 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3315 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3316 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3317 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[5] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3318 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3319 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3320 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[44] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3321 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[26] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1559 ) ,
+ .clk_1_S_in ( p290 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3322 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3323 ) , .clk_2_N_in ( p1559 ) ,
+ .clk_2_E_in ( p1146 ) , .clk_2_S_in ( p572 ) , .clk_2_W_in ( p1006 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3324 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3325 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3326 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3327 ) ,
+ .clk_3_W_in ( clk_3_wires[5] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3328 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3329 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3330 ) ,
+ .clk_3_E_out ( clk_3_wires[44] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3331 ) ,
+ .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) ) ;
+sb_1__1_ sb_8__7_ ( .chany_top_in ( cby_1__1__91_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_91_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_91_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__94_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_102_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_102_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__90_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_90_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_90_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__83_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_90_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_90_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__94_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__83_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__83_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__83_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p1547 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3332 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1426 ) ,
+ .prog_clk_1_S_in ( p915 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3333 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3334 ) ,
+ .prog_clk_2_N_in ( p1426 ) , .prog_clk_2_E_in ( p658 ) ,
+ .prog_clk_2_S_in ( p2450 ) , .prog_clk_2_W_in ( p570 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3335 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3336 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3337 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3338 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3339 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3340 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[27] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3341 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3342 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3343 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[30] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3344 ) , .clk_1_N_in ( p1426 ) ,
+ .clk_1_S_in ( p437 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3345 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3346 ) , .clk_2_N_in ( p1426 ) ,
+ .clk_2_E_in ( p147 ) , .clk_2_S_in ( p652 ) , .clk_2_W_in ( p318 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3347 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3348 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3349 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3350 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3351 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3352 ) ,
+ .clk_3_S_in ( clk_3_wires[27] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3353 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3354 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3355 ) ,
+ .clk_3_N_out ( clk_3_wires[30] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3356 ) ) ;
+sb_1__1_ sb_8__8_ ( .chany_top_in ( cby_1__1__92_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_92_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_92_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__95_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_103_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_103_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__91_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_91_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_91_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__84_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_91_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_91_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__95_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__84_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__84_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__84_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p1586 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3357 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1577 ) ,
+ .prog_clk_1_S_in ( p118 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3358 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3359 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3360 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3361 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[31] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3362 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[93] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3363 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3364 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[91] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3365 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3366 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[31] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3367 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3368 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3369 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[36] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3370 ) , .clk_1_N_in ( p1577 ) ,
+ .clk_1_S_in ( p845 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3371 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3372 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3373 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3374 ) ,
+ .clk_2_S_in ( clk_3_wires[31] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3375 ) ,
+ .clk_2_W_out ( clk_2_wires[93] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3376 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3377 ) ,
+ .clk_2_E_out ( clk_2_wires[91] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3378 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3379 ) ,
+ .clk_3_S_in ( clk_3_wires[31] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3380 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3381 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3382 ) ,
+ .clk_3_N_out ( clk_3_wires[36] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3383 ) ) ;
+sb_1__1_ sb_8__9_ ( .chany_top_in ( cby_1__1__93_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_93_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_93_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__96_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_104_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_104_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__92_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_92_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_92_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__85_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_92_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_92_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__96_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__85_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__85_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__85_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2016 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3384 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1554 ) ,
+ .prog_clk_1_S_in ( p934 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3385 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3386 ) ,
+ .prog_clk_2_N_in ( p1554 ) , .prog_clk_2_E_in ( p105 ) ,
+ .prog_clk_2_S_in ( p170 ) , .prog_clk_2_W_in ( p885 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3387 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3388 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3389 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3390 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3391 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3392 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[37] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3393 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3394 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3395 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[40] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3396 ) , .clk_1_N_in ( p1554 ) ,
+ .clk_1_S_in ( p588 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3397 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3398 ) , .clk_2_N_in ( p1554 ) ,
+ .clk_2_E_in ( p899 ) , .clk_2_S_in ( p1921 ) , .clk_2_W_in ( p158 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3399 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3400 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3401 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3402 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3403 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3404 ) ,
+ .clk_3_S_in ( clk_3_wires[37] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3405 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3406 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3407 ) ,
+ .clk_3_N_out ( clk_3_wires[40] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
+sb_1__1_ sb_8__10_ ( .chany_top_in ( cby_1__1__94_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_94_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_94_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__97_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_105_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_105_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__93_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_93_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_93_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__86_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_93_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_93_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__97_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__86_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__86_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__86_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p1684 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3409 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p3450 ) ,
+ .prog_clk_1_S_in ( p884 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3410 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3411 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3412 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3413 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[41] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3414 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[106] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3415 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3416 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p2324 ) ,
+ .prog_clk_3_E_in ( p1132 ) , .prog_clk_3_S_in ( p179 ) ,
+ .prog_clk_3_N_in ( p2223 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3417 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3418 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3419 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3420 ) , .clk_1_N_in ( p2858 ) ,
+ .clk_1_S_in ( p428 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3421 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3422 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3423 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3424 ) ,
+ .clk_2_S_in ( clk_3_wires[41] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3425 ) ,
+ .clk_2_W_out ( clk_2_wires[106] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3426 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3427 ) ,
+ .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p2324 ) ,
+ .clk_3_E_in ( p175 ) , .clk_3_S_in ( p1181 ) , .clk_3_N_in ( p3434 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3428 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3429 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3430 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
+sb_1__1_ sb_8__11_ ( .chany_top_in ( cby_1__1__95_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_95_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_95_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__98_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_106_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_106_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__94_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_94_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_94_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__87_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_94_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_94_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__98_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__87_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__87_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__87_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p2026 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3432 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p3416 ) ,
+ .prog_clk_1_S_in ( p903 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3433 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3434 ) ,
+ .prog_clk_2_N_in ( p2782 ) , .prog_clk_2_E_in ( p682 ) ,
+ .prog_clk_2_S_in ( p1106 ) , .prog_clk_2_W_in ( p932 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3435 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3436 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3437 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3438 ) ,
+ .prog_clk_3_W_in ( p3151 ) , .prog_clk_3_E_in ( p745 ) ,
+ .prog_clk_3_S_in ( p302 ) , .prog_clk_3_N_in ( p2628 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3439 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3440 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3441 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3442 ) , .clk_1_N_in ( p3100 ) ,
+ .clk_1_S_in ( p569 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3443 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3444 ) , .clk_2_N_in ( p3449 ) ,
+ .clk_2_E_in ( p1016 ) , .clk_2_S_in ( p1949 ) , .clk_2_W_in ( p3072 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3445 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3446 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3447 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3448 ) , .clk_3_W_in ( p3009 ) ,
+ .clk_3_E_in ( p197 ) , .clk_3_S_in ( p1068 ) , .clk_3_N_in ( p3429 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3449 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3450 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3451 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3452 ) ) ;
+sb_1__1_ sb_9__1_ ( .chany_top_in ( cby_1__1__97_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_97_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_97_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__99_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_108_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_108_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__96_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_96_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_96_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__88_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_96_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_96_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__99_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__88_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__88_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__88_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p2401 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3453 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[334] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[76] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3454 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[169] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3135 ) ,
+ .prog_clk_2_E_in ( p684 ) , .prog_clk_2_S_in ( p1182 ) ,
+ .prog_clk_2_W_in ( p856 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3455 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3456 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3457 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3458 ) ,
+ .prog_clk_3_W_in ( p3026 ) , .prog_clk_3_E_in ( p1304 ) ,
+ .prog_clk_3_S_in ( p1030 ) , .prog_clk_3_N_in ( p3086 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3459 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3460 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3461 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3462 ) ,
+ .clk_1_N_in ( clk_2_wires[76] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3463 ) ,
+ .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) ,
+ .clk_2_N_in ( p3506 ) , .clk_2_E_in ( p1009 ) , .clk_2_S_in ( p2216 ) ,
+ .clk_2_W_in ( p2948 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3464 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3465 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3466 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3467 ) , .clk_3_W_in ( p2878 ) ,
+ .clk_3_E_in ( p377 ) , .clk_3_S_in ( p201 ) , .clk_3_N_in ( p3504 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3468 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3469 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3470 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
+sb_1__1_ sb_9__2_ ( .chany_top_in ( cby_1__1__98_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_98_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_98_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__100_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_109_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_109_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__97_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_97_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_97_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__89_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_97_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_97_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__100_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__89_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__89_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__89_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p2765 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3472 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p3482 ) ,
+ .prog_clk_1_S_in ( p539 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3473 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3474 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3475 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3476 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3477 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[70] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3478 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[75] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3479 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3480 ) ,
+ .prog_clk_3_W_in ( p1465 ) , .prog_clk_3_E_in ( p1064 ) ,
+ .prog_clk_3_S_in ( p2638 ) , .prog_clk_3_N_in ( p2237 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3481 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3482 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3483 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3484 ) , .clk_1_N_in ( p3021 ) ,
+ .clk_1_S_in ( p964 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3485 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3486 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3487 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3488 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3489 ) ,
+ .clk_2_W_in ( clk_2_wires[70] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3490 ) ,
+ .clk_2_S_out ( clk_2_wires[75] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3491 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3492 ) , .clk_3_W_in ( p1465 ) ,
+ .clk_3_E_in ( p231 ) , .clk_3_S_in ( p1334 ) , .clk_3_N_in ( p3472 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3493 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3494 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3495 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3496 ) ) ;
+sb_1__1_ sb_9__3_ ( .chany_top_in ( cby_1__1__99_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_99_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_99_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__101_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_110_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_110_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__98_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_98_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_98_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__90_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_98_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_98_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__101_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__90_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__90_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__90_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p2788 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3497 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[340] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[89] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3498 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[176] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p3522 ) ,
+ .prog_clk_2_E_in ( p1286 ) , .prog_clk_2_S_in ( p61 ) ,
+ .prog_clk_2_W_in ( p843 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3499 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3500 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3501 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3502 ) ,
+ .prog_clk_3_W_in ( p3012 ) , .prog_clk_3_E_in ( p25 ) ,
+ .prog_clk_3_S_in ( p196 ) , .prog_clk_3_N_in ( p3521 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3503 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3504 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3505 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3506 ) ,
+ .clk_1_N_in ( clk_2_wires[89] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3507 ) ,
+ .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) ,
+ .clk_2_N_in ( p3287 ) , .clk_2_E_in ( p716 ) , .clk_2_S_in ( p2677 ) ,
+ .clk_2_W_in ( p3402 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3508 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3509 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3510 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_3_W_in ( p3415 ) ,
+ .clk_3_E_in ( p1171 ) , .clk_3_S_in ( p1262 ) , .clk_3_N_in ( p3248 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3512 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3513 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3514 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
+sb_1__1_ sb_9__4_ ( .chany_top_in ( cby_1__1__100_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_100_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_100_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__102_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_111_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_111_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__99_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_99_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_99_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__91_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_99_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_99_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__102_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__91_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__91_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__91_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2368 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3516 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p3469 ) ,
+ .prog_clk_1_S_in ( p914 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3517 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3518 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3519 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3520 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3521 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[79] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3522 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[88] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[86] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3523 ) ,
+ .prog_clk_3_W_in ( p2423 ) , .prog_clk_3_E_in ( p306 ) ,
+ .prog_clk_3_S_in ( p2229 ) , .prog_clk_3_N_in ( p608 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3524 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3525 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3526 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3527 ) , .clk_1_N_in ( p2031 ) ,
+ .clk_1_S_in ( p551 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3528 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3529 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3530 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3531 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3532 ) ,
+ .clk_2_W_in ( clk_2_wires[79] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3533 ) ,
+ .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3534 ) , .clk_3_W_in ( p2423 ) ,
+ .clk_3_E_in ( p1149 ) , .clk_3_S_in ( p769 ) , .clk_3_N_in ( p3461 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3535 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3536 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3537 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3538 ) ) ;
+sb_1__1_ sb_9__5_ ( .chany_top_in ( cby_1__1__101_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_101_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_101_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__103_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_112_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_112_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__100_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_100_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_100_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__92_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_100_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_100_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__103_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__92_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__92_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__92_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p2725 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3539 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[346] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3540 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[87] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[183] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p2101 ) ,
+ .prog_clk_2_E_in ( p1353 ) , .prog_clk_2_S_in ( p488 ) ,
+ .prog_clk_2_W_in ( p642 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3541 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3542 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3543 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3544 ) ,
+ .prog_clk_3_W_in ( p3376 ) , .prog_clk_3_E_in ( p825 ) ,
+ .prog_clk_3_S_in ( p709 ) , .prog_clk_3_N_in ( p2641 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3545 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3546 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3547 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3548 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3549 ) ,
+ .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) ,
+ .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p3378 ) ,
+ .clk_2_E_in ( p900 ) , .clk_2_S_in ( p2668 ) , .clk_2_W_in ( p3370 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3550 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3551 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3552 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3553 ) , .clk_3_W_in ( p3036 ) ,
+ .clk_3_E_in ( p42 ) , .clk_3_S_in ( p927 ) , .clk_3_N_in ( p3372 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3554 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3555 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3556 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3557 ) ) ;
+sb_1__1_ sb_9__6_ ( .chany_top_in ( cby_1__1__102_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_102_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_102_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__104_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_113_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_113_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__101_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_101_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_101_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__93_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_101_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_101_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__104_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__93_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__93_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__93_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p2715 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3558 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1796 ) ,
+ .prog_clk_1_S_in ( p513 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3559 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3560 ) ,
+ .prog_clk_2_N_in ( p1852 ) , .prog_clk_2_E_in ( p1316 ) ,
+ .prog_clk_2_S_in ( p324 ) , .prog_clk_2_W_in ( p924 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3561 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3562 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3563 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3564 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[45] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3565 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3566 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3567 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[48] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3568 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3569 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3570 ) , .clk_1_N_in ( p1796 ) ,
+ .clk_1_S_in ( p804 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3571 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3572 ) , .clk_2_N_in ( p1796 ) ,
+ .clk_2_E_in ( p78 ) , .clk_2_S_in ( p2675 ) , .clk_2_W_in ( p349 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3573 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3574 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3575 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3576 ) ,
+ .clk_3_W_in ( clk_3_wires[45] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3577 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3578 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3579 ) ,
+ .clk_3_E_out ( clk_3_wires[48] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3580 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3581 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3582 ) ) ;
+sb_1__1_ sb_9__7_ ( .chany_top_in ( cby_1__1__103_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_103_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_103_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__105_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_114_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_114_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__102_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_102_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_102_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__94_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_102_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_102_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__105_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__94_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__94_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__94_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p3123 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3583 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[352] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[102] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3584 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[190] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p2876 ) ,
+ .prog_clk_2_E_in ( p275 ) , .prog_clk_2_S_in ( p271 ) ,
+ .prog_clk_2_W_in ( p2502 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3585 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3586 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3587 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3588 ) ,
+ .prog_clk_3_W_in ( p3411 ) , .prog_clk_3_E_in ( p833 ) ,
+ .prog_clk_3_S_in ( p95 ) , .prog_clk_3_N_in ( p2804 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3589 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3590 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3591 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3592 ) ,
+ .clk_1_N_in ( clk_2_wires[102] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3593 ) ,
+ .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) ,
+ .clk_2_N_in ( p3483 ) , .clk_2_E_in ( p1164 ) , .clk_2_S_in ( p3095 ) ,
+ .clk_2_W_in ( p3405 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3594 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3595 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3596 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3597 ) , .clk_3_W_in ( p2591 ) ,
+ .clk_3_E_in ( p1184 ) , .clk_3_S_in ( p1001 ) , .clk_3_N_in ( p3477 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3598 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3599 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3600 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3601 ) ) ;
+sb_1__1_ sb_9__8_ ( .chany_top_in ( cby_1__1__104_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_104_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_104_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__106_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_115_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_115_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__103_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_103_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_103_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__95_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_103_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_103_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__106_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__95_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__95_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__95_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p2617 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3602 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p3210 ) ,
+ .prog_clk_1_S_in ( p1275 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3603 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3604 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3605 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3606 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3607 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[92] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3608 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[101] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[99] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3609 ) ,
+ .prog_clk_3_W_in ( p2163 ) , .prog_clk_3_E_in ( p366 ) ,
+ .prog_clk_3_S_in ( p2458 ) , .prog_clk_3_N_in ( p1959 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3610 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3611 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3612 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3613 ) , .clk_1_N_in ( p2996 ) ,
+ .clk_1_S_in ( p638 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3614 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3615 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3616 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3617 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3618 ) ,
+ .clk_2_W_in ( clk_2_wires[92] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3619 ) ,
+ .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3620 ) , .clk_3_W_in ( p2163 ) ,
+ .clk_3_E_in ( p992 ) , .clk_3_S_in ( p494 ) , .clk_3_N_in ( p3181 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3621 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3622 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3623 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3624 ) ) ;
+sb_1__1_ sb_9__9_ ( .chany_top_in ( cby_1__1__105_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_105_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_105_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__107_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_116_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_116_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__104_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_104_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_104_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__96_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_104_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_104_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__107_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__96_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__96_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__96_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p2159 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3625 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[358] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3626 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[100] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[197] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3273 ) ,
+ .prog_clk_2_E_in ( p1203 ) , .prog_clk_2_S_in ( p989 ) ,
+ .prog_clk_2_W_in ( p165 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3627 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3628 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3629 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3630 ) ,
+ .prog_clk_3_W_in ( p3334 ) , .prog_clk_3_E_in ( p603 ) ,
+ .prog_clk_3_S_in ( p1444 ) , .prog_clk_3_N_in ( p3260 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3631 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3632 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3633 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3634 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3635 ) ,
+ .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) ,
+ .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p3394 ) ,
+ .clk_2_E_in ( p70 ) , .clk_2_S_in ( p1899 ) , .clk_2_W_in ( p3316 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3636 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3637 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3638 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3639 ) , .clk_3_W_in ( p3122 ) ,
+ .clk_3_E_in ( p1125 ) , .clk_3_S_in ( p364 ) , .clk_3_N_in ( p3361 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3640 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3641 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3642 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3643 ) ) ;
+sb_1__1_ sb_9__10_ ( .chany_top_in ( cby_1__1__106_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_106_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_106_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__108_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_117_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_117_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__105_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_105_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_105_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__97_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_105_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_105_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__108_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__97_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__97_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__97_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p1812 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3644 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p3349 ) ,
+ .prog_clk_1_S_in ( p193 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3645 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3646 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3647 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3648 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3649 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[105] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3650 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3651 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[110] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3652 ) ,
+ .prog_clk_3_W_in ( p1581 ) , .prog_clk_3_E_in ( p182 ) ,
+ .prog_clk_3_S_in ( p1136 ) , .prog_clk_3_N_in ( p2632 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3653 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3654 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3655 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3656 ) , .clk_1_N_in ( p2868 ) ,
+ .clk_1_S_in ( p375 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3657 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3658 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3659 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3660 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3661 ) ,
+ .clk_2_W_in ( clk_2_wires[105] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3662 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3663 ) ,
+ .clk_2_N_out ( clk_2_wires[110] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3664 ) , .clk_3_W_in ( p1581 ) ,
+ .clk_3_E_in ( p736 ) , .clk_3_S_in ( p489 ) , .clk_3_N_in ( p3309 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3665 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3666 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3667 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) ) ;
+sb_1__1_ sb_9__11_ ( .chany_top_in ( cby_1__1__107_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_107_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_107_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__109_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_118_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_118_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__106_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_106_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_106_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__98_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_106_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_106_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__109_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__98_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__98_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__98_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2873 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3669 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[364] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3670 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[111] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[204] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p3417 ) ,
+ .prog_clk_2_E_in ( p841 ) , .prog_clk_2_S_in ( p990 ) ,
+ .prog_clk_2_W_in ( p707 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3671 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3672 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3673 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3674 ) ,
+ .prog_clk_3_W_in ( p3196 ) , .prog_clk_3_E_in ( p893 ) ,
+ .prog_clk_3_S_in ( p120 ) , .prog_clk_3_N_in ( p3406 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3675 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3676 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3677 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3678 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3679 ) ,
+ .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) ,
+ .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3520 ) ,
+ .clk_2_E_in ( p1238 ) , .clk_2_S_in ( p2798 ) , .clk_2_W_in ( p3155 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3680 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3681 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3682 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3683 ) , .clk_3_W_in ( p2152 ) ,
+ .clk_3_E_in ( p59 ) , .clk_3_S_in ( p785 ) , .clk_3_N_in ( p3519 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3684 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3685 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3686 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3687 ) ) ;
+sb_1__1_ sb_10__1_ ( .chany_top_in ( cby_1__1__109_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_109_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_109_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__110_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_120_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_120_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__108_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_108_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_108_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__99_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_108_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_108_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__110_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__99_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__99_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__99_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p2901 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3688 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p2711 ) ,
+ .prog_clk_1_S_in ( p50 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3689 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3690 ) ,
+ .prog_clk_2_N_in ( p3390 ) , .prog_clk_2_E_in ( p1117 ) ,
+ .prog_clk_2_S_in ( p1292 ) , .prog_clk_2_W_in ( p1085 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3691 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3692 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3693 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3694 ) ,
+ .prog_clk_3_W_in ( p2923 ) , .prog_clk_3_E_in ( p1101 ) ,
+ .prog_clk_3_S_in ( p1391 ) , .prog_clk_3_N_in ( p3357 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3695 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3696 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3697 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3698 ) , .clk_1_N_in ( p2251 ) ,
+ .clk_1_S_in ( p558 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3699 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3700 ) , .clk_2_N_in ( p3113 ) ,
+ .clk_2_E_in ( p1293 ) , .clk_2_S_in ( p2835 ) , .clk_2_W_in ( p2953 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3701 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3702 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3703 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3704 ) , .clk_3_W_in ( p3007 ) ,
+ .clk_3_E_in ( p30 ) , .clk_3_S_in ( p407 ) , .clk_3_N_in ( p3068 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3705 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3706 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3707 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3708 ) ) ;
+sb_1__1_ sb_10__2_ ( .chany_top_in ( cby_1__1__110_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_110_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_110_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__111_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_121_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_121_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__109_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_109_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_109_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__100_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_109_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_109_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__111_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__100_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__100_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__100_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p2376 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3709 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p3225 ) ,
+ .prog_clk_1_S_in ( p873 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3710 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3711 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[87] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3712 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3713 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3714 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3715 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3716 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3717 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p2562 ) ,
+ .prog_clk_3_E_in ( p2189 ) , .prog_clk_3_S_in ( p2211 ) ,
+ .prog_clk_3_N_in ( p579 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3718 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3719 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3720 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3721 ) , .clk_1_N_in ( p2889 ) ,
+ .clk_1_S_in ( p235 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3722 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3723 ) ,
+ .clk_2_N_in ( clk_3_wires[87] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3724 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3725 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3726 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3727 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3728 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3729 ) ,
+ .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p2614 ) ,
+ .clk_3_E_in ( p2435 ) , .clk_3_S_in ( p1216 ) , .clk_3_N_in ( p3160 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3730 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3731 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3732 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3733 ) ) ;
+sb_1__1_ sb_10__3_ ( .chany_top_in ( cby_1__1__111_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_111_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_111_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__112_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_122_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_122_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__110_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_110_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_110_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__101_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_110_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_110_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__112_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__101_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__101_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__101_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p2795 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3734 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1744 ) ,
+ .prog_clk_1_S_in ( p650 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3735 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3736 ) ,
+ .prog_clk_2_N_in ( p1744 ) , .prog_clk_2_E_in ( p928 ) ,
+ .prog_clk_2_S_in ( p1981 ) , .prog_clk_2_W_in ( p1022 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3737 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3738 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3739 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3740 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3741 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3742 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3743 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[83] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3744 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3745 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3746 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1744 ) ,
+ .clk_1_S_in ( p1044 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3747 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3748 ) , .clk_2_N_in ( p1744 ) ,
+ .clk_2_E_in ( p31 ) , .clk_2_S_in ( p2642 ) , .clk_2_W_in ( p303 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3749 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3750 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3751 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3752 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3753 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3754 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3755 ) ,
+ .clk_3_N_in ( clk_3_wires[83] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3756 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3757 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3758 ) ,
+ .clk_3_S_out ( clk_3_wires[86] ) ) ;
+sb_1__1_ sb_10__4_ ( .chany_top_in ( cby_1__1__112_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_112_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_112_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__113_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_123_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_123_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__111_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_111_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_111_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__102_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_111_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_111_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__113_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__102_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__102_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__102_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1557 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3759 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1699 ) ,
+ .prog_clk_1_S_in ( p329 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3760 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3761 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[77] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3762 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3763 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3764 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3765 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3766 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3767 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[119] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3768 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3769 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3770 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[77] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3771 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3772 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3773 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1699 ) ,
+ .clk_1_S_in ( p457 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3774 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3775 ) ,
+ .clk_2_N_in ( clk_3_wires[77] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3776 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3777 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3778 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3779 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3780 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3781 ) ,
+ .clk_2_E_out ( clk_2_wires[119] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3782 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3783 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3784 ) ,
+ .clk_3_N_in ( clk_3_wires[77] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3785 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3786 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3787 ) ,
+ .clk_3_S_out ( clk_3_wires[82] ) ) ;
+sb_1__1_ sb_10__5_ ( .chany_top_in ( cby_1__1__113_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_113_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_113_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__114_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_124_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_124_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__112_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_112_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_112_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__103_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_112_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_112_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__114_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__103_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__103_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__103_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p2753 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3788 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p1854 ) ,
+ .prog_clk_1_S_in ( p942 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3789 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3790 ) ,
+ .prog_clk_2_N_in ( p1854 ) , .prog_clk_2_E_in ( p174 ) ,
+ .prog_clk_2_S_in ( p1172 ) , .prog_clk_2_W_in ( p249 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3791 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3792 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3793 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3794 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3795 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3796 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3797 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[73] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3798 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3799 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3800 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p1685 ) ,
+ .clk_1_S_in ( p142 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3801 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_2_N_in ( p1854 ) ,
+ .clk_2_E_in ( p1056 ) , .clk_2_S_in ( p2643 ) , .clk_2_W_in ( p831 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3803 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3804 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3805 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3806 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3807 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3808 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3809 ) ,
+ .clk_3_N_in ( clk_3_wires[73] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3810 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3811 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3812 ) ,
+ .clk_3_S_out ( clk_3_wires[76] ) ) ;
+sb_1__1_ sb_10__6_ ( .chany_top_in ( cby_1__1__114_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_114_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_114_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__115_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_125_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_125_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__113_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_113_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_113_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__104_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_113_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_113_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__115_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__104_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__104_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__104_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p3116 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3813 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1362 ) ,
+ .prog_clk_1_S_in ( p296 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3814 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3815 ) ,
+ .prog_clk_2_N_in ( p1765 ) , .prog_clk_2_E_in ( p410 ) ,
+ .prog_clk_2_S_in ( p2272 ) , .prog_clk_2_W_in ( p2459 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3816 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3817 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3818 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3819 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[49] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3820 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3821 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3822 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3823 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3824 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[70] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1362 ) ,
+ .clk_1_S_in ( p676 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3825 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_2_N_in ( p1362 ) ,
+ .clk_2_E_in ( p840 ) , .clk_2_S_in ( p3061 ) , .clk_2_W_in ( p1011 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3827 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3828 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3829 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3830 ) ,
+ .clk_3_W_in ( clk_3_wires[49] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3831 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3832 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3833 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3834 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3835 ) ,
+ .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) ) ;
+sb_1__1_ sb_10__7_ ( .chany_top_in ( cby_1__1__115_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_115_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_115_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__116_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_126_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_126_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__114_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_114_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_114_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__105_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_114_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_114_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__116_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__105_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__105_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__105_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p1997 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3836 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1804 ) ,
+ .prog_clk_1_S_in ( p418 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3837 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3838 ) ,
+ .prog_clk_2_N_in ( p1804 ) , .prog_clk_2_E_in ( p673 ) ,
+ .prog_clk_2_S_in ( p2201 ) , .prog_clk_2_W_in ( p1156 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3839 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3840 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3841 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3842 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3843 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3844 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[71] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3845 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3846 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3847 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[74] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3848 ) , .clk_1_N_in ( p1804 ) ,
+ .clk_1_S_in ( p960 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3849 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3850 ) , .clk_2_N_in ( p1804 ) ,
+ .clk_2_E_in ( p389 ) , .clk_2_S_in ( p1999 ) , .clk_2_W_in ( p54 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3851 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3852 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3853 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3854 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3855 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3856 ) ,
+ .clk_3_S_in ( clk_3_wires[71] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3857 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3858 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3859 ) ,
+ .clk_3_N_out ( clk_3_wires[74] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3860 ) ) ;
+sb_1__1_ sb_10__8_ ( .chany_top_in ( cby_1__1__116_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_116_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_116_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__117_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_127_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_127_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__115_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_115_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_115_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__106_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_115_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_115_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__117_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__106_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__106_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__106_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p1774 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3861 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p1874 ) ,
+ .prog_clk_1_S_in ( p427 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3862 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3863 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3864 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3865 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[75] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3866 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3867 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3868 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3869 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[126] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3870 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3871 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[75] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3872 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3873 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3874 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[80] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3875 ) , .clk_1_N_in ( p1874 ) ,
+ .clk_1_S_in ( p1112 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3876 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3877 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3878 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3879 ) ,
+ .clk_2_S_in ( clk_3_wires[75] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3880 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3881 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3882 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3883 ) ,
+ .clk_2_E_out ( clk_2_wires[126] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3884 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3885 ) ,
+ .clk_3_S_in ( clk_3_wires[75] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3886 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3887 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3888 ) ,
+ .clk_3_N_out ( clk_3_wires[80] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3889 ) ) ;
+sb_1__1_ sb_10__9_ ( .chany_top_in ( cby_1__1__117_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_117_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_117_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__118_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_128_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_128_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__116_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_116_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_116_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__107_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_116_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_116_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__118_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__107_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__107_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__107_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p1663 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3890 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p803 ) ,
+ .prog_clk_1_S_in ( p860 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3891 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3892 ) ,
+ .prog_clk_2_N_in ( p803 ) , .prog_clk_2_E_in ( p773 ) ,
+ .prog_clk_2_S_in ( p1915 ) , .prog_clk_2_W_in ( p394 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3893 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3894 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3895 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3896 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3897 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3898 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[81] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3899 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3900 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3901 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[84] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3902 ) , .clk_1_N_in ( p803 ) ,
+ .clk_1_S_in ( p38 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3903 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3904 ) , .clk_2_N_in ( p803 ) ,
+ .clk_2_E_in ( p21 ) , .clk_2_S_in ( p542 ) , .clk_2_W_in ( p333 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3905 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3906 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3907 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3908 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3909 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3910 ) ,
+ .clk_3_S_in ( clk_3_wires[81] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3911 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3912 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3913 ) ,
+ .clk_3_N_out ( clk_3_wires[84] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3914 ) ) ;
+sb_1__1_ sb_10__10_ ( .chany_top_in ( cby_1__1__118_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_118_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_118_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__119_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_129_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_129_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__117_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_117_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_117_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__108_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_117_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_117_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__119_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__108_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__108_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__108_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p2361 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3915 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p2563 ) ,
+ .prog_clk_1_S_in ( p82 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3916 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3917 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3918 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3919 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[85] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3920 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3921 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3922 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3923 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1475 ) ,
+ .prog_clk_3_E_in ( p262 ) , .prog_clk_3_S_in ( p2179 ) ,
+ .prog_clk_3_N_in ( p1889 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3924 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3925 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3926 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3927 ) , .clk_1_N_in ( p2080 ) ,
+ .clk_1_S_in ( p1271 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3928 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3929 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3930 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3931 ) ,
+ .clk_2_S_in ( clk_3_wires[85] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3932 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3933 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3934 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3935 ) ,
+ .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1475 ) ,
+ .clk_3_E_in ( p891 ) , .clk_3_S_in ( p552 ) , .clk_3_N_in ( p2460 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3936 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3937 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3938 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3939 ) ) ;
+sb_1__1_ sb_10__11_ ( .chany_top_in ( cby_1__1__119_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_119_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_119_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__120_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_130_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_130_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__118_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_118_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_118_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__109_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_118_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_118_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__120_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__109_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__109_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__109_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p2877 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3940 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p3208 ) ,
+ .prog_clk_1_S_in ( p758 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3941 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3942 ) ,
+ .prog_clk_2_N_in ( p3464 ) , .prog_clk_2_E_in ( p830 ) ,
+ .prog_clk_2_S_in ( p307 ) , .prog_clk_2_W_in ( p111 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3943 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3944 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3945 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3946 ) ,
+ .prog_clk_3_W_in ( p3490 ) , .prog_clk_3_E_in ( p185 ) ,
+ .prog_clk_3_S_in ( p1432 ) , .prog_clk_3_N_in ( p3457 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3947 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3948 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3949 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3950 ) , .clk_1_N_in ( p3045 ) ,
+ .clk_1_S_in ( p499 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3951 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3952 ) , .clk_2_N_in ( p3375 ) ,
+ .clk_2_E_in ( p789 ) , .clk_2_S_in ( p2805 ) , .clk_2_W_in ( p3489 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3953 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3954 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3955 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3956 ) , .clk_3_W_in ( p2909 ) ,
+ .clk_3_E_in ( p1012 ) , .clk_3_S_in ( p169 ) , .clk_3_N_in ( p3358 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3957 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3958 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3959 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3960 ) ) ;
+sb_1__1_ sb_11__1_ ( .chany_top_in ( cby_1__1__121_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_121_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_121_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__121_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_132_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_132_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__120_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_120_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_120_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__110_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_120_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_120_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__121_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__110_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__110_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__110_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p1702 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3961 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[410] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[116] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3962 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[211] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3463 ) ,
+ .prog_clk_2_E_in ( p1325 ) , .prog_clk_2_S_in ( p136 ) ,
+ .prog_clk_2_W_in ( p1274 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3963 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3964 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3965 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3966 ) ,
+ .prog_clk_3_W_in ( p2776 ) , .prog_clk_3_E_in ( p402 ) ,
+ .prog_clk_3_S_in ( p678 ) , .prog_clk_3_N_in ( p3453 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3967 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3968 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3969 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) ,
+ .clk_1_N_in ( clk_2_wires[116] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3971 ) ,
+ .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) ,
+ .clk_2_N_in ( p2519 ) , .clk_2_E_in ( p381 ) , .clk_2_S_in ( p1108 ) ,
+ .clk_2_W_in ( p2974 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3972 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3973 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3974 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3975 ) , .clk_3_W_in ( p3008 ) ,
+ .clk_3_E_in ( p611 ) , .clk_3_S_in ( p1069 ) , .clk_3_N_in ( p2445 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3976 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3977 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3978 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3979 ) ) ;
+sb_1__1_ sb_11__2_ ( .chany_top_in ( cby_1__1__122_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_122_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_122_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__122_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_133_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_133_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__121_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_121_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_121_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__111_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_121_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_121_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__122_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__111_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__111_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__111_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p1487 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3980 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p3290 ) ,
+ .prog_clk_1_S_in ( p4 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3981 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3982 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3983 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3984 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3985 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[113] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3986 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[115] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3987 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3988 ) ,
+ .prog_clk_3_W_in ( p2124 ) , .prog_clk_3_E_in ( p334 ) ,
+ .prog_clk_3_S_in ( p587 ) , .prog_clk_3_N_in ( p1978 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3989 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3990 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3991 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3992 ) , .clk_1_N_in ( p2566 ) ,
+ .clk_1_S_in ( p1205 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3993 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3994 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3995 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3996 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3997 ) ,
+ .clk_2_W_in ( clk_2_wires[113] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3998 ) ,
+ .clk_2_S_out ( clk_2_wires[115] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3999 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4000 ) , .clk_3_W_in ( p2124 ) ,
+ .clk_3_E_in ( p1010 ) , .clk_3_S_in ( p365 ) , .clk_3_N_in ( p3250 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4001 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4002 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4003 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4004 ) ) ;
+sb_1__1_ sb_11__3_ ( .chany_top_in ( cby_1__1__123_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_123_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_123_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__123_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_134_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_134_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__122_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_122_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_122_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__112_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_122_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_122_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__123_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__112_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__112_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__112_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p2527 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4005 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[416] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[123] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4006 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[218] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3419 ) ,
+ .prog_clk_2_E_in ( p909 ) , .prog_clk_2_S_in ( p1060 ) ,
+ .prog_clk_2_W_in ( p160 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4007 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4008 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4009 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4010 ) ,
+ .prog_clk_3_W_in ( p2620 ) , .prog_clk_3_E_in ( p943 ) ,
+ .prog_clk_3_S_in ( p1310 ) , .prog_clk_3_N_in ( p3398 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4011 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4012 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4013 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4014 ) ,
+ .clk_1_N_in ( clk_2_wires[123] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4015 ) ,
+ .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) ,
+ .clk_2_N_in ( p3138 ) , .clk_2_E_in ( p613 ) , .clk_2_S_in ( p2494 ) ,
+ .clk_2_W_in ( p3404 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4016 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4017 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4018 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4019 ) , .clk_3_W_in ( p3420 ) ,
+ .clk_3_E_in ( p263 ) , .clk_3_S_in ( p101 ) , .clk_3_N_in ( p3067 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4020 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4021 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4022 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) ) ;
+sb_1__1_ sb_11__4_ ( .chany_top_in ( cby_1__1__124_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_124_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_124_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__124_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_135_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_135_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__123_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_123_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_123_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__113_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_123_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_123_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__124_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__113_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__113_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__113_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p2903 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4024 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p3389 ) ,
+ .prog_clk_1_S_in ( p139 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4025 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4026 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4027 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4028 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4029 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[118] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4030 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[122] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[120] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4031 ) ,
+ .prog_clk_3_W_in ( p1641 ) , .prog_clk_3_E_in ( p1273 ) ,
+ .prog_clk_3_S_in ( p2826 ) , .prog_clk_3_N_in ( p385 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4032 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4033 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4034 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4035 ) , .clk_1_N_in ( p1272 ) ,
+ .clk_1_S_in ( p1045 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4036 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4037 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4038 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4039 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4040 ) ,
+ .clk_2_W_in ( clk_2_wires[118] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4041 ) ,
+ .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4042 ) , .clk_3_W_in ( p1641 ) ,
+ .clk_3_E_in ( p519 ) , .clk_3_S_in ( p1178 ) , .clk_3_N_in ( p3365 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4043 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4044 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4045 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4046 ) ) ;
+sb_1__1_ sb_11__5_ ( .chany_top_in ( cby_1__1__125_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_125_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_125_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__125_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_136_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_136_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__124_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_124_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_124_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__114_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_124_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_124_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__125_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__114_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__114_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__114_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p2742 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4047 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[422] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4048 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[121] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[225] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p3341 ) ,
+ .prog_clk_2_E_in ( p1190 ) , .prog_clk_2_S_in ( p576 ) ,
+ .prog_clk_2_W_in ( p998 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4049 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4050 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4051 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4052 ) ,
+ .prog_clk_3_W_in ( p3217 ) , .prog_clk_3_E_in ( p817 ) ,
+ .prog_clk_3_S_in ( p970 ) , .prog_clk_3_N_in ( p3314 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4053 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4054 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4055 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4056 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4057 ) ,
+ .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) ,
+ .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p3035 ) ,
+ .clk_2_E_in ( p737 ) , .clk_2_S_in ( p2665 ) , .clk_2_W_in ( p3164 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4058 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4059 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4060 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4061 ) , .clk_3_W_in ( p2123 ) ,
+ .clk_3_E_in ( p123 ) , .clk_3_S_in ( p227 ) , .clk_3_N_in ( p2971 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4062 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4063 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4064 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4065 ) ) ;
+sb_1__1_ sb_11__6_ ( .chany_top_in ( cby_1__1__126_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_126_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_126_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__126_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_137_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_137_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__125_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_125_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_125_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__115_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_125_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_125_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__126_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__115_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__115_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__115_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2311 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4066 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p2505 ) ,
+ .prog_clk_1_S_in ( p606 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4067 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4068 ) ,
+ .prog_clk_2_N_in ( p3387 ) , .prog_clk_2_E_in ( p108 ) ,
+ .prog_clk_2_S_in ( p183 ) , .prog_clk_2_W_in ( p422 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4069 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4070 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4071 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4072 ) ,
+ .prog_clk_3_W_in ( p2411 ) , .prog_clk_3_E_in ( p338 ) ,
+ .prog_clk_3_S_in ( p1267 ) , .prog_clk_3_N_in ( p3362 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4073 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4074 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4075 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p2399 ) ,
+ .clk_1_S_in ( p1057 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p3493 ) ,
+ .clk_2_E_in ( p1379 ) , .clk_2_S_in ( p2207 ) , .clk_2_W_in ( p2818 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4079 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4080 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4081 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4082 ) , .clk_3_W_in ( p2932 ) ,
+ .clk_3_E_in ( p403 ) , .clk_3_S_in ( p328 ) , .clk_3_N_in ( p3487 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4083 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4084 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4085 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4086 ) ) ;
+sb_1__1_ sb_11__7_ ( .chany_top_in ( cby_1__1__127_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_127_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_127_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__127_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_138_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_138_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__126_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_126_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_126_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__116_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_126_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_126_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__127_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__116_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__116_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__116_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p2135 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4087 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[428] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[130] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4088 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[232] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3292 ) ,
+ .prog_clk_2_E_in ( p1241 ) , .prog_clk_2_S_in ( p496 ) ,
+ .prog_clk_2_W_in ( p863 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4089 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4090 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4091 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4092 ) ,
+ .prog_clk_3_W_in ( p3195 ) , .prog_clk_3_E_in ( p783 ) ,
+ .prog_clk_3_S_in ( p107 ) , .prog_clk_3_N_in ( p3243 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4093 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4094 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4095 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4096 ) ,
+ .clk_1_N_in ( clk_2_wires[130] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4097 ) ,
+ .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) ,
+ .clk_2_N_in ( p2875 ) , .clk_2_E_in ( p423 ) , .clk_2_S_in ( p1911 ) ,
+ .clk_2_W_in ( p3165 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4098 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4099 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4100 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4101 ) , .clk_3_W_in ( p3132 ) ,
+ .clk_3_E_in ( p692 ) , .clk_3_S_in ( p781 ) , .clk_3_N_in ( p2822 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4102 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4103 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4104 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4105 ) ) ;
+sb_1__1_ sb_11__8_ ( .chany_top_in ( cby_1__1__128_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_128_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_128_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__128_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_139_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_139_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__127_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_127_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_127_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__117_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_127_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_127_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__128_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__117_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__117_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__117_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p2774 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4106 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p3424 ) ,
+ .prog_clk_1_S_in ( p602 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4107 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4108 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4109 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4110 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4111 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[125] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4112 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[129] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[127] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4113 ) ,
+ .prog_clk_3_W_in ( p1741 ) , .prog_clk_3_E_in ( p950 ) ,
+ .prog_clk_3_S_in ( p2651 ) , .prog_clk_3_N_in ( p1923 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4114 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4115 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4116 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4117 ) , .clk_1_N_in ( p2088 ) ,
+ .clk_1_S_in ( p847 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4118 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4119 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4120 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4121 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4122 ) ,
+ .clk_2_W_in ( clk_2_wires[125] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4123 ) ,
+ .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4124 ) , .clk_3_W_in ( p1879 ) ,
+ .clk_3_E_in ( p85 ) , .clk_3_S_in ( p206 ) , .clk_3_N_in ( p3403 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4125 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4126 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4127 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4128 ) ) ;
+sb_1__1_ sb_11__9_ ( .chany_top_in ( cby_1__1__129_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_129_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_129_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__129_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_140_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_140_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__128_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_128_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_128_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__118_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_128_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_128_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__129_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__118_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__118_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__118_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2090 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4129 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[434] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4130 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[128] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[239] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3396 ) ,
+ .prog_clk_2_E_in ( p805 ) , .prog_clk_2_S_in ( p601 ) ,
+ .prog_clk_2_W_in ( p1118 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4131 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4132 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4133 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4134 ) ,
+ .prog_clk_3_W_in ( p3234 ) , .prog_clk_3_E_in ( p1237 ) ,
+ .prog_clk_3_S_in ( p10 ) , .prog_clk_3_N_in ( p3373 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4135 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4136 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4137 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4138 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4139 ) ,
+ .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) ,
+ .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p3494 ) ,
+ .clk_2_E_in ( p1397 ) , .clk_2_S_in ( p1946 ) , .clk_2_W_in ( p3177 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4140 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4141 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4142 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4143 ) , .clk_3_W_in ( p2927 ) ,
+ .clk_3_E_in ( p75 ) , .clk_3_S_in ( p1167 ) , .clk_3_N_in ( p3485 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4144 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4145 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4146 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4147 ) ) ;
+sb_1__1_ sb_11__10_ ( .chany_top_in ( cby_1__1__130_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_130_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_130_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__130_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_141_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_141_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__129_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_129_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_129_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__119_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_129_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_129_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__130_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__119_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__119_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__119_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p1985 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4148 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p3041 ) ,
+ .prog_clk_1_S_in ( p864 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4149 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4150 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4151 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4152 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4153 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[132] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4154 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4155 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[134] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4156 ) ,
+ .prog_clk_3_W_in ( p2578 ) , .prog_clk_3_E_in ( p379 ) ,
+ .prog_clk_3_S_in ( p1910 ) , .prog_clk_3_N_in ( p2191 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4157 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4158 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4159 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_1_N_in ( p2544 ) ,
+ .clk_1_S_in ( p184 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4161 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4162 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4163 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4164 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4165 ) ,
+ .clk_2_W_in ( clk_2_wires[132] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4166 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4167 ) ,
+ .clk_2_N_out ( clk_2_wires[134] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4168 ) , .clk_3_W_in ( p2578 ) ,
+ .clk_3_E_in ( p71 ) , .clk_3_S_in ( p1035 ) , .clk_3_N_in ( p2944 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4169 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4170 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4171 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4172 ) ) ;
+sb_1__1_ sb_11__11_ ( .chany_top_in ( cby_1__1__131_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_131_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_131_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_lower ) ,
+ .chanx_right_in ( cbx_1__1__131_chanx_left_out ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_142_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_142_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__130_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_130_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_130_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__120_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_130_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_130_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( cbx_1__1__131_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__120_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__120_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__120_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p2902 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4173 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[440] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4174 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[135] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[246] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p3291 ) ,
+ .prog_clk_2_E_in ( p1130 ) , .prog_clk_2_S_in ( p594 ) ,
+ .prog_clk_2_W_in ( p387 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4175 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4176 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4177 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4178 ) ,
+ .prog_clk_3_W_in ( p2773 ) , .prog_clk_3_E_in ( p1014 ) ,
+ .prog_clk_3_S_in ( p1195 ) , .prog_clk_3_N_in ( p3261 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4179 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4180 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4181 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4183 ) ,
+ .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) ,
+ .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p3350 ) ,
+ .clk_2_E_in ( p1318 ) , .clk_2_S_in ( p2839 ) , .clk_2_W_in ( p2809 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4184 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4185 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4186 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4187 ) , .clk_3_W_in ( p2872 ) ,
+ .clk_3_E_in ( p362 ) , .clk_3_S_in ( p188 ) , .clk_3_N_in ( p3323 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4188 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4189 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4190 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4191 ) ) ;
+sb_1__2_ sb_1__12_ ( .chanx_right_in ( cbx_1__12__1_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_23_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_23_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__11_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_11_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_11_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__0_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_11_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_11_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_1_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1368 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4192 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[60] ) ) ;
+sb_1__2_ sb_2__12_ ( .chanx_right_in ( cbx_1__12__2_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_35_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_35_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__23_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_23_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_23_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__1_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_23_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_23_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_2_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__1_ccff_tail ) , .SC_IN_BOT ( scff_Wires[52] ) ,
+ .SC_OUT_BOT ( scff_Wires[53] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[100] ) ) ;
+sb_1__2_ sb_3__12_ ( .chanx_right_in ( cbx_1__12__3_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_47_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_47_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__35_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_35_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_35_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__2_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_35_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_35_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_3_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1422 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4193 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[138] ) ) ;
+sb_1__2_ sb_4__12_ ( .chanx_right_in ( cbx_1__12__4_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_59_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_59_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__47_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_47_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_47_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__3_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_47_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_47_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_4_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__3_ccff_tail ) , .SC_IN_BOT ( scff_Wires[105] ) ,
+ .SC_OUT_BOT ( scff_Wires[106] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[176] ) ) ;
+sb_1__2_ sb_5__12_ ( .chanx_right_in ( cbx_1__12__5_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_71_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_71_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__59_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_59_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_59_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__4_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_59_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_59_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_5_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1589 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4194 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[214] ) ) ;
+sb_1__2_ sb_6__12_ ( .chanx_right_in ( cbx_1__12__6_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_83_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_83_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__71_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_71_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_71_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__5_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_71_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_71_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_6_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__5_ccff_tail ) , .SC_IN_BOT ( scff_Wires[158] ) ,
+ .SC_OUT_BOT ( scff_Wires[159] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[252] ) ) ;
+sb_1__2_ sb_7__12_ ( .chanx_right_in ( cbx_1__12__7_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_95_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_95_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__83_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_83_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_83_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__6_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_83_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_83_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_7_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1652 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4195 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[290] ) ) ;
+sb_1__2_ sb_8__12_ ( .chanx_right_in ( cbx_1__12__8_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_107_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_107_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__95_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_95_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_95_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__7_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_95_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_95_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_8_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__7_ccff_tail ) , .SC_IN_BOT ( scff_Wires[211] ) ,
+ .SC_OUT_BOT ( scff_Wires[212] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[328] ) ) ;
+sb_1__2_ sb_9__12_ ( .chanx_right_in ( cbx_1__12__9_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_119_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_119_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__107_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_107_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_107_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__8_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_107_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_107_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_9_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1523 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4196 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[366] ) ) ;
+sb_1__2_ sb_10__12_ ( .chanx_right_in ( cbx_1__12__10_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_131_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_131_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__119_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_119_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_119_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__9_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_119_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_119_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_10_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__9_ccff_tail ) , .SC_IN_BOT ( scff_Wires[264] ) ,
+ .SC_OUT_BOT ( scff_Wires[265] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[404] ) ) ;
+sb_1__2_ sb_11__12_ ( .chanx_right_in ( cbx_1__12__11_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_34_ ( grid_clb_143_top_width_0_height_0__pin_34_upper ) ,
+ .right_bottom_grid_pin_35_ ( grid_clb_143_top_width_0_height_0__pin_35_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_upper ) ,
+ .chany_bottom_in ( cby_1__1__131_chany_top_out ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_131_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_131_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__10_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_131_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_131_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_top_11_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1533 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4197 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[442] ) ) ;
+sb_2__0_ sb_12__0_ ( .chany_top_in ( cby_12__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_132_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_132_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) ,
+ .chanx_left_in ( cbx_1__0__11_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_right_11_ccff_tail ) ,
+ .chany_top_out ( sb_12__0__0_chany_top_out ) ,
+ .chanx_left_out ( sb_12__0__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__0__0_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[445] ) ) ;
+sb_2__1_ sb_12__1_ ( .chany_top_in ( cby_12__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_133_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_133_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__0_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_132_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_132_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__121_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_132_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_132_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_10_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__0_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__0_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[448] ) ) ;
+sb_2__1_ sb_12__2_ ( .chany_top_in ( cby_12__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_134_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_134_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__1_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_133_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_133_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__122_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_133_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_133_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_9_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__1_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__1_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__1_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[451] ) ) ;
+sb_2__1_ sb_12__3_ ( .chany_top_in ( cby_12__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_135_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_135_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__2_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_134_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_134_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__123_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_134_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_134_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_8_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__2_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__2_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__2_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[454] ) ) ;
+sb_2__1_ sb_12__4_ ( .chany_top_in ( cby_12__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_136_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_136_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__3_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_135_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_135_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__124_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_135_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_135_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_7_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__3_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__3_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__3_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[457] ) ) ;
+sb_2__1_ sb_12__5_ ( .chany_top_in ( cby_12__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_137_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_137_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__4_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_136_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_136_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__125_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_136_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_136_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_6_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__4_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__4_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__4_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[460] ) ) ;
+sb_2__1_ sb_12__6_ ( .chany_top_in ( cby_12__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_138_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_138_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__5_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_137_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_137_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__126_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_137_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_137_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_5_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__5_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__5_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__5_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[463] ) ) ;
+sb_2__1_ sb_12__7_ ( .chany_top_in ( cby_12__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_139_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_139_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__6_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_138_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_138_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__127_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_138_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_138_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_4_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__6_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__6_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__6_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[466] ) ) ;
+sb_2__1_ sb_12__8_ ( .chany_top_in ( cby_12__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_140_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_140_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__7_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_139_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_139_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__128_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_139_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_139_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_3_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__7_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__7_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__7_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[469] ) ) ;
+sb_2__1_ sb_12__9_ ( .chany_top_in ( cby_12__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_141_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_141_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__8_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_140_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_140_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__129_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_140_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_140_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_2_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__8_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__8_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__8_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[472] ) ) ;
+sb_2__1_ sb_12__10_ ( .chany_top_in ( cby_12__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_142_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_142_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__9_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_141_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_141_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__130_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_141_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_141_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_1_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__9_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__9_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__9_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[475] ) ) ;
+sb_2__1_ sb_12__11_ ( .chany_top_in ( cby_12__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_42_ ( grid_clb_143_right_width_0_height_0__pin_42_lower ) ,
+ .top_left_grid_pin_43_ ( grid_clb_143_right_width_0_height_0__pin_43_lower ) ,
+ .top_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__10_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_142_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_142_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__1__131_chanx_right_out ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_142_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_142_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( grid_io_right_0_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__10_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__10_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__10_ccff_tail ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[478] ) ) ;
+sb_2__2_ sb_12__12_ ( .chany_bottom_in ( cby_12__1__11_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_42_ ( grid_clb_143_right_width_0_height_0__pin_42_upper ) ,
+ .bottom_left_grid_pin_43_ ( grid_clb_143_right_width_0_height_0__pin_43_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_upper ) ,
+ .chanx_left_in ( cbx_1__12__11_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_34_ ( grid_clb_143_top_width_0_height_0__pin_34_lower ) ,
+ .left_bottom_grid_pin_35_ ( grid_clb_143_top_width_0_height_0__pin_35_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_lower ) ,
+ .ccff_head ( ccff_head ) ,
+ .chany_bottom_out ( sb_12__12__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__12__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__12__0_ccff_tail ) , .SC_IN_BOT ( scff_Wires[317] ) ,
+ .SC_OUT_BOT ( sc_tail ) , .prog_clk_0_S_in ( prog_clk_0_wires[480] ) ) ;
+cbx_1__0_ cbx_1__0_ ( .chanx_left_in ( sb_0__0__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__0_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123:131] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123:131] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123:131] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) ,
+ .SC_IN_BOT ( p1123 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4198 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[0] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[5] ) ) ;
+cbx_1__0_ cbx_2__0_ ( .chanx_left_in ( sb_1__0__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__1_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114:122] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114:122] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114:122] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1466 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4199 ) ,
+ .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[63] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4200 ) ) ;
+cbx_1__0_ cbx_3__0_ ( .chanx_left_in ( sb_1__0__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__2_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105:113] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105:113] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105:113] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) ,
+ .SC_IN_BOT ( p1616 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4201 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[101] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4202 ) ) ;
+cbx_1__0_ cbx_4__0_ ( .chanx_left_in ( sb_1__0__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__3_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:104] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:104] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:104] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1522 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4203 ) ,
+ .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[139] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4204 ) ) ;
+cbx_1__0_ cbx_5__0_ ( .chanx_left_in ( sb_1__0__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__4_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87:95] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87:95] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87:95] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) ,
+ .SC_IN_BOT ( p1646 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4205 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[177] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4206 ) ) ;
+cbx_1__0_ cbx_6__0_ ( .chanx_left_in ( sb_1__0__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__5_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78:86] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78:86] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78:86] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1480 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4207 ) ,
+ .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[215] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4208 ) ) ;
+cbx_1__0_ cbx_7__0_ ( .chanx_left_in ( sb_1__0__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__6_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69:77] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69:77] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69:77] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) ,
+ .SC_IN_BOT ( p2028 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4209 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[253] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4210 ) ) ;
+cbx_1__0_ cbx_8__0_ ( .chanx_left_in ( sb_1__0__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__7_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:68] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:68] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:68] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1052 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4211 ) ,
+ .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[291] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4212 ) ) ;
+cbx_1__0_ cbx_9__0_ ( .chanx_left_in ( sb_1__0__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__8_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51:59] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51:59] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51:59] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) ,
+ .SC_IN_BOT ( p1661 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4213 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[329] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4214 ) ) ;
+cbx_1__0_ cbx_10__0_ ( .chanx_left_in ( sb_1__0__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__9_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42:50] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42:50] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42:50] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1433 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4215 ) ,
+ .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[367] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4216 ) ) ;
+cbx_1__0_ cbx_11__0_ ( .chanx_left_in ( sb_1__0__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__10_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33:41] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33:41] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33:41] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) ,
+ .SC_IN_BOT ( p2022 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4217 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[405] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4218 ) ) ;
+cbx_1__0_ cbx_12__0_ ( .chanx_left_in ( sb_1__0__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__0__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__0__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__11_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:32] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:32] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:32] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1514 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4219 ) ,
+ .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[443] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4220 ) ) ;
+cbx_1__1_ cbx_1__1_ ( .chanx_left_in ( sb_0__1__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__0_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) ,
+ .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p2148 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4221 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[6] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[4] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4222 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[2] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[3] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p2750 ) ,
+ .prog_clk_2_W_in ( p881 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4223 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4224 ) ,
+ .prog_clk_3_W_in ( p1733 ) , .prog_clk_3_E_in ( p746 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4225 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4226 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4227 ) ,
+ .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) ,
+ .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p1696 ) ,
+ .clk_2_W_in ( p397 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4228 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4229 ) , .clk_3_W_in ( p1861 ) ,
+ .clk_3_E_in ( p2630 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4230 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4231 ) ) ;
+cbx_1__1_ cbx_1__2_ ( .chanx_left_in ( sb_0__1__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__1_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) ,
+ .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p1601 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4232 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[11] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p1425 ) ,
+ .prog_clk_1_E_in ( p91 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4233 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4234 ) ,
+ .prog_clk_2_E_in ( p2345 ) , .prog_clk_2_W_in ( p636 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4235 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4236 ) ,
+ .prog_clk_3_W_in ( p1569 ) , .prog_clk_3_E_in ( p2669 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4237 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4238 ) , .clk_1_W_in ( p1425 ) ,
+ .clk_1_E_in ( p1490 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4239 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_2_E_in ( p2727 ) ,
+ .clk_2_W_in ( p1228 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4241 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4242 ) , .clk_3_W_in ( p1569 ) ,
+ .clk_3_E_in ( p2232 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4243 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4244 ) ) ;
+cbx_1__1_ cbx_1__3_ ( .chanx_left_in ( sb_0__1__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__2_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) ,
+ .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1448 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4245 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[16] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[15] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4246 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[9] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[10] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p2915 ) ,
+ .prog_clk_2_W_in ( p103 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4247 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4248 ) ,
+ .prog_clk_3_W_in ( p1973 ) , .prog_clk_3_E_in ( p2689 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4249 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4250 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4251 ) ,
+ .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) ,
+ .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2731 ) ,
+ .clk_2_W_in ( p2008 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4252 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4253 ) , .clk_3_W_in ( p1973 ) ,
+ .clk_3_E_in ( p2854 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4254 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4255 ) ) ;
+cbx_1__1_ cbx_1__4_ ( .chanx_left_in ( sb_0__1__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__3_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) ,
+ .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1183 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4256 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[21] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p2131 ) ,
+ .prog_clk_1_E_in ( p641 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4257 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4258 ) ,
+ .prog_clk_2_E_in ( p2025 ) , .prog_clk_2_W_in ( p1935 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4259 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4260 ) ,
+ .prog_clk_3_W_in ( p2605 ) , .prog_clk_3_E_in ( p2940 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4261 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4262 ) , .clk_1_W_in ( p2131 ) ,
+ .clk_1_E_in ( p1500 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4263 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4264 ) , .clk_2_E_in ( p3053 ) ,
+ .clk_2_W_in ( p2476 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4265 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4266 ) , .clk_3_W_in ( p2605 ) ,
+ .clk_3_E_in ( p1914 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4267 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4268 ) ) ;
+cbx_1__1_ cbx_1__5_ ( .chanx_left_in ( sb_0__1__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__4_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) ,
+ .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1814 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4269 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[26] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[25] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4270 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[16] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[17] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p1235 ) ,
+ .prog_clk_2_W_in ( p200 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4271 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4272 ) ,
+ .prog_clk_3_W_in ( p1826 ) , .prog_clk_3_E_in ( p2848 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4273 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4274 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4275 ) ,
+ .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) ,
+ .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p2879 ) ,
+ .clk_2_W_in ( p1222 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4276 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4277 ) , .clk_3_W_in ( p1826 ) ,
+ .clk_3_E_in ( p1377 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4278 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4279 ) ) ;
+cbx_1__1_ cbx_1__6_ ( .chanx_left_in ( sb_0__1__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__5_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) ,
+ .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1580 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4280 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[31] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p1305 ) ,
+ .prog_clk_1_E_in ( p581 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4281 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4282 ) ,
+ .prog_clk_2_E_in ( p2568 ) , .prog_clk_2_W_in ( p669 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4283 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4284 ) ,
+ .prog_clk_3_W_in ( p2714 ) , .prog_clk_3_E_in ( p3089 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4285 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4286 ) , .clk_1_W_in ( p1305 ) ,
+ .clk_1_E_in ( p1424 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4287 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4288 ) , .clk_2_E_in ( p3121 ) ,
+ .clk_2_W_in ( p2682 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4289 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4290 ) , .clk_3_W_in ( p2714 ) ,
+ .clk_3_E_in ( p2506 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4291 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4292 ) ) ;
+cbx_1__1_ cbx_1__7_ ( .chanx_left_in ( sb_0__1__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__6_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) ,
+ .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1518 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4293 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[36] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[35] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4294 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[23] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[24] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p2089 ) ,
+ .prog_clk_2_W_in ( p463 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4295 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4296 ) ,
+ .prog_clk_3_W_in ( p2057 ) , .prog_clk_3_E_in ( p3083 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4297 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4298 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4299 ) ,
+ .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) ,
+ .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p3120 ) ,
+ .clk_2_W_in ( p1948 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4300 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4301 ) , .clk_3_W_in ( p2057 ) ,
+ .clk_3_E_in ( p2005 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4302 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4303 ) ) ;
+cbx_1__1_ cbx_1__8_ ( .chanx_left_in ( sb_0__1__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__7_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) ,
+ .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1824 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4304 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[41] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1494 ) ,
+ .prog_clk_1_E_in ( p1364 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4305 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4306 ) ,
+ .prog_clk_2_E_in ( p1534 ) , .prog_clk_2_W_in ( p332 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4307 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4308 ) ,
+ .prog_clk_3_W_in ( p1885 ) , .prog_clk_3_E_in ( p2939 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4309 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4310 ) , .clk_1_W_in ( p1494 ) ,
+ .clk_1_E_in ( p164 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4311 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4312 ) , .clk_2_E_in ( p3023 ) ,
+ .clk_2_W_in ( p1483 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4313 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4314 ) , .clk_3_W_in ( p1885 ) ,
+ .clk_3_E_in ( p405 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4315 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4316 ) ) ;
+cbx_1__1_ cbx_1__9_ ( .chanx_left_in ( sb_0__1__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__8_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) ,
+ .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1654 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4317 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[46] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[45] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4318 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[30] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[31] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p1662 ) ,
+ .prog_clk_2_W_in ( p1113 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4319 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4320 ) ,
+ .prog_clk_3_W_in ( p2359 ) , .prog_clk_3_E_in ( p3059 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4321 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4322 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4323 ) ,
+ .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) ,
+ .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p3125 ) ,
+ .clk_2_W_in ( p2245 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4324 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4325 ) , .clk_3_W_in ( p2359 ) ,
+ .clk_3_E_in ( p1408 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4326 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4327 ) ) ;
+cbx_1__1_ cbx_1__10_ ( .chanx_left_in ( sb_0__1__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__9_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) ,
+ .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p2140 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4328 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[51] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p1703 ) ,
+ .prog_clk_1_E_in ( p1446 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4329 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4330 ) ,
+ .prog_clk_2_E_in ( p2583 ) , .prog_clk_2_W_in ( p1392 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4331 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4332 ) ,
+ .prog_clk_3_W_in ( p1793 ) , .prog_clk_3_E_in ( p2841 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4333 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4334 ) , .clk_1_W_in ( p1703 ) ,
+ .clk_1_E_in ( p1942 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4335 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4336 ) , .clk_2_E_in ( p2910 ) ,
+ .clk_2_W_in ( p679 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4337 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4338 ) , .clk_3_W_in ( p1793 ) ,
+ .clk_3_E_in ( p2446 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4339 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4340 ) ) ;
+cbx_1__1_ cbx_1__11_ ( .chanx_left_in ( sb_0__1__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__10_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) ,
+ .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1638 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4341 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[56] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[55] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4342 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[37] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[38] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p1735 ) ,
+ .prog_clk_2_W_in ( p1361 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4343 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4344 ) ,
+ .prog_clk_3_W_in ( p2615 ) , .prog_clk_3_E_in ( p2855 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4345 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4346 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4347 ) ,
+ .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) ,
+ .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2929 ) ,
+ .clk_2_W_in ( p2464 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4348 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4349 ) , .clk_3_W_in ( p2615 ) ,
+ .clk_3_E_in ( p1142 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4350 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4351 ) ) ;
+cbx_1__1_ cbx_2__1_ ( .chanx_left_in ( sb_1__1__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__11_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__11_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__11_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p1460 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4352 ) ,
+ .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[11] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[66] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4353 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[1] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4354 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[5] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2363 ) ,
+ .prog_clk_2_W_in ( p16 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4355 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4356 ) ,
+ .prog_clk_3_W_in ( p2407 ) , .prog_clk_3_E_in ( p3073 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4357 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4358 ) ,
+ .clk_1_W_in ( clk_1_wires[1] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4359 ) ,
+ .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) ,
+ .clk_2_E_in ( p3143 ) , .clk_2_W_in ( p2238 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4360 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4361 ) , .clk_3_W_in ( p2407 ) ,
+ .clk_3_E_in ( p2257 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4362 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4363 ) ) ;
+cbx_1__1_ cbx_2__2_ ( .chanx_left_in ( sb_1__1__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__12_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__12_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__12_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__12_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p1410 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4364 ) ,
+ .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[12] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[69] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4365 ) ,
+ .prog_clk_1_W_in ( p1213 ) , .prog_clk_1_E_in ( p1366 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4366 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4367 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[2] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4368 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[1] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4369 ) ,
+ .prog_clk_3_W_in ( p2707 ) , .prog_clk_3_E_in ( p622 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4370 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4371 ) , .clk_1_W_in ( p1213 ) ,
+ .clk_1_E_in ( p791 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4372 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4373 ) ,
+ .clk_2_E_in ( clk_2_wires[2] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4374 ) ,
+ .clk_2_W_out ( clk_2_wires[1] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4375 ) , .clk_3_W_in ( p2707 ) ,
+ .clk_3_E_in ( p1412 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4376 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4377 ) ) ;
+cbx_1__1_ cbx_2__3_ ( .chanx_left_in ( sb_1__1__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__13_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__13_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__13_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__13_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1644 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4378 ) ,
+ .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[13] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[72] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4379 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[8] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4380 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[12] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p902 ) ,
+ .prog_clk_2_W_in ( p599 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4381 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4382 ) ,
+ .prog_clk_3_W_in ( p2607 ) , .prog_clk_3_E_in ( p2847 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4383 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4384 ) ,
+ .clk_1_W_in ( clk_1_wires[8] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4385 ) ,
+ .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) ,
+ .clk_2_E_in ( p2925 ) , .clk_2_W_in ( p2456 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4386 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4387 ) , .clk_3_W_in ( p2607 ) ,
+ .clk_3_E_in ( p1520 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4388 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4389 ) ) ;
+cbx_1__1_ cbx_2__4_ ( .chanx_left_in ( sb_1__1__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__14_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__14_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__14_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__14_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p1694 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4390 ) ,
+ .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[14] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[75] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4391 ) ,
+ .prog_clk_1_W_in ( p1558 ) , .prog_clk_1_E_in ( p419 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4392 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4393 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[7] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4394 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[6] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4395 ) ,
+ .prog_clk_3_W_in ( p1883 ) , .prog_clk_3_E_in ( p694 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4396 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4397 ) , .clk_1_W_in ( p1558 ) ,
+ .clk_1_E_in ( p1532 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4398 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4399 ) ,
+ .clk_2_E_in ( clk_2_wires[7] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4400 ) ,
+ .clk_2_W_out ( clk_2_wires[6] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4401 ) , .clk_3_W_in ( p1883 ) ,
+ .clk_3_E_in ( p1039 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4402 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4403 ) ) ;
+cbx_1__1_ cbx_2__5_ ( .chanx_left_in ( sb_1__1__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__15_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__15_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__15_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__15_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p2107 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4404 ) ,
+ .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[15] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[78] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4405 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[15] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4406 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[19] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p2316 ) ,
+ .prog_clk_2_W_in ( p631 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4407 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4408 ) ,
+ .prog_clk_3_W_in ( p2557 ) , .prog_clk_3_E_in ( p2655 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4409 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4410 ) ,
+ .clk_1_W_in ( clk_1_wires[15] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4411 ) ,
+ .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) ,
+ .clk_2_E_in ( p2730 ) , .clk_2_W_in ( p2475 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4412 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4413 ) , .clk_3_W_in ( p2557 ) ,
+ .clk_3_E_in ( p2246 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4414 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4415 ) ) ;
+cbx_1__1_ cbx_2__6_ ( .chanx_left_in ( sb_1__1__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__16_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__16_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__16_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__16_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p2306 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4416 ) ,
+ .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[16] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[81] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4417 ) ,
+ .prog_clk_1_W_in ( p1501 ) , .prog_clk_1_E_in ( p1394 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4418 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4419 ) ,
+ .prog_clk_2_E_in ( p1611 ) , .prog_clk_2_W_in ( p1019 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4420 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4421 ) ,
+ .prog_clk_3_W_in ( p2267 ) , .prog_clk_3_E_in ( p2973 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4422 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4423 ) , .clk_1_W_in ( p1501 ) ,
+ .clk_1_E_in ( p589 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4424 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4425 ) , .clk_2_E_in ( p3032 ) ,
+ .clk_2_W_in ( p2233 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4426 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4427 ) , .clk_3_W_in ( p2267 ) ,
+ .clk_3_E_in ( p1574 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4428 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4429 ) ) ;
+cbx_1__1_ cbx_2__7_ ( .chanx_left_in ( sb_1__1__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__17_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__17_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__17_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__17_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p1552 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4430 ) ,
+ .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[17] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[84] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4431 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[22] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4432 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[26] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p1080 ) ,
+ .prog_clk_2_W_in ( p1431 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4433 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4434 ) ,
+ .prog_clk_3_W_in ( p2108 ) , .prog_clk_3_E_in ( p3091 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4435 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4436 ) ,
+ .clk_1_W_in ( clk_1_wires[22] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4437 ) ,
+ .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) ,
+ .clk_2_E_in ( p3104 ) , .clk_2_W_in ( p1903 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4438 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_3_W_in ( p2108 ) ,
+ .clk_3_E_in ( p1159 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4440 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4441 ) ) ;
+cbx_1__1_ cbx_2__8_ ( .chanx_left_in ( sb_1__1__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__18_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__18_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__18_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__18_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p2576 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4442 ) ,
+ .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[18] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[87] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4443 ) ,
+ .prog_clk_1_W_in ( p1625 ) , .prog_clk_1_E_in ( p1389 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4444 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4445 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[14] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4446 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[13] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4447 ) ,
+ .prog_clk_3_W_in ( p1553 ) , .prog_clk_3_E_in ( p2487 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4448 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4449 ) , .clk_1_W_in ( p1828 ) ,
+ .clk_1_E_in ( p753 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4450 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4451 ) ,
+ .clk_2_E_in ( clk_2_wires[14] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4452 ) ,
+ .clk_2_W_out ( clk_2_wires[13] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4453 ) , .clk_3_W_in ( p1553 ) ,
+ .clk_3_E_in ( p1443 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4454 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4455 ) ) ;
+cbx_1__1_ cbx_2__9_ ( .chanx_left_in ( sb_1__1__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__19_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__19_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__19_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__19_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p2143 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4456 ) ,
+ .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[19] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[90] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4457 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[29] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4458 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[33] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p2012 ) ,
+ .prog_clk_2_W_in ( p1251 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4459 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4460 ) ,
+ .prog_clk_3_W_in ( p2577 ) , .prog_clk_3_E_in ( p2448 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4461 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4462 ) ,
+ .clk_1_W_in ( clk_1_wires[29] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4463 ) ,
+ .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) ,
+ .clk_2_E_in ( p2550 ) , .clk_2_W_in ( p2478 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4464 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4465 ) , .clk_3_W_in ( p2577 ) ,
+ .clk_3_E_in ( p1983 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4466 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4467 ) ) ;
+cbx_1__1_ cbx_2__10_ ( .chanx_left_in ( sb_1__1__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__20_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__20_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__20_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__20_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p1615 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4468 ) ,
+ .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[20] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[93] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4469 ) ,
+ .prog_clk_1_W_in ( p1704 ) , .prog_clk_1_E_in ( p348 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4470 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4471 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[21] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4472 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[20] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4473 ) ,
+ .prog_clk_3_W_in ( p2034 ) , .prog_clk_3_E_in ( p629 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4474 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4475 ) , .clk_1_W_in ( p1704 ) ,
+ .clk_1_E_in ( p471 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4476 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4477 ) ,
+ .clk_2_E_in ( clk_2_wires[21] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4478 ) ,
+ .clk_2_W_out ( clk_2_wires[20] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4479 ) , .clk_3_W_in ( p2034 ) ,
+ .clk_3_E_in ( p1423 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4480 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4481 ) ) ;
+cbx_1__1_ cbx_2__11_ ( .chanx_left_in ( sb_1__1__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__21_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__21_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__21_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__21_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1583 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4482 ) ,
+ .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[21] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[96] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4483 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[36] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4484 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[40] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p2079 ) ,
+ .prog_clk_2_W_in ( p728 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4485 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4486 ) ,
+ .prog_clk_3_W_in ( p1811 ) , .prog_clk_3_E_in ( p2978 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4487 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4488 ) ,
+ .clk_1_W_in ( clk_1_wires[36] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4489 ) ,
+ .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) ,
+ .clk_2_E_in ( p3033 ) , .clk_2_W_in ( p2840 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4490 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4491 ) , .clk_3_W_in ( p2856 ) ,
+ .clk_3_E_in ( p1958 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4492 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4493 ) ) ;
+cbx_1__1_ cbx_3__1_ ( .chanx_left_in ( sb_1__1__11_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__22_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__22_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__22_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__22_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) ,
+ .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1746 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4494 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[104] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4495 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4496 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[44] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[45] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p2098 ) ,
+ .prog_clk_2_W_in ( p1219 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4497 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4498 ) ,
+ .prog_clk_3_W_in ( p2560 ) , .prog_clk_3_E_in ( p2986 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4499 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4500 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4501 ) ,
+ .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) ,
+ .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p2991 ) ,
+ .clk_2_W_in ( p2442 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4502 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4503 ) , .clk_3_W_in ( p2560 ) ,
+ .clk_3_E_in ( p2013 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4504 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4505 ) ) ;
+cbx_1__1_ cbx_3__2_ ( .chanx_left_in ( sb_1__1__12_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__23_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__23_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__23_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__23_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) ,
+ .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1808 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4506 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[107] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4507 ) ,
+ .prog_clk_1_W_in ( p1445 ) , .prog_clk_1_E_in ( p441 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4508 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4509 ) ,
+ .prog_clk_2_E_in ( p1753 ) , .prog_clk_2_W_in ( p1488 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4510 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4511 ) ,
+ .prog_clk_3_W_in ( p2039 ) , .prog_clk_3_E_in ( p2972 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4512 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4513 ) , .clk_1_W_in ( p1445 ) ,
+ .clk_1_E_in ( p1417 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4514 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4515 ) , .clk_2_E_in ( p3040 ) ,
+ .clk_2_W_in ( p1955 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4516 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4517 ) , .clk_3_W_in ( p2039 ) ,
+ .clk_3_E_in ( p163 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4518 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4519 ) ) ;
+cbx_1__1_ cbx_3__3_ ( .chanx_left_in ( sb_1__1__13_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__24_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__24_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__24_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__24_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) ,
+ .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1498 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4520 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[110] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4521 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4522 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[51] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[52] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p1709 ) ,
+ .prog_clk_2_W_in ( p945 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4523 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4524 ) ,
+ .prog_clk_3_W_in ( p1407 ) , .prog_clk_3_E_in ( p1992 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4525 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4526 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4527 ) ,
+ .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) ,
+ .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p1944 ) ,
+ .clk_2_W_in ( p1455 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4528 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4529 ) , .clk_3_W_in ( p1407 ) ,
+ .clk_3_E_in ( p1298 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4530 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4531 ) ) ;
+cbx_1__1_ cbx_3__4_ ( .chanx_left_in ( sb_1__1__14_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__25_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__25_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__25_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__25_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) ,
+ .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1705 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4532 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[113] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4533 ) ,
+ .prog_clk_1_W_in ( p1221 ) , .prog_clk_1_E_in ( p1341 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4534 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4535 ) ,
+ .prog_clk_2_E_in ( p2905 ) , .prog_clk_2_W_in ( p267 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4536 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4537 ) ,
+ .prog_clk_3_W_in ( p2078 ) , .prog_clk_3_E_in ( p2509 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4538 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4539 ) , .clk_1_W_in ( p1221 ) ,
+ .clk_1_E_in ( p524 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4540 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4541 ) , .clk_2_E_in ( p2593 ) ,
+ .clk_2_W_in ( p2253 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4542 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4543 ) , .clk_3_W_in ( p2284 ) ,
+ .clk_3_E_in ( p2843 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4544 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4545 ) ) ;
+cbx_1__1_ cbx_3__5_ ( .chanx_left_in ( sb_1__1__15_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__26_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__26_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__26_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__26_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) ,
+ .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1555 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4546 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[116] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4547 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4548 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[58] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[59] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p1866 ) ,
+ .prog_clk_2_W_in ( p823 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4549 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4550 ) ,
+ .prog_clk_3_W_in ( p2522 ) , .prog_clk_3_E_in ( p1913 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4551 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4552 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4553 ) ,
+ .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) ,
+ .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p2047 ) ,
+ .clk_2_W_in ( p2430 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4554 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4555 ) , .clk_3_W_in ( p2522 ) ,
+ .clk_3_E_in ( p12 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4556 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4557 ) ) ;
+cbx_1__1_ cbx_3__6_ ( .chanx_left_in ( sb_1__1__16_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__27_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__27_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__27_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__27_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) ,
+ .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p1758 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4558 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[119] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4559 ) ,
+ .prog_clk_1_W_in ( p1386 ) , .prog_clk_1_E_in ( p1059 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4560 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4561 ) ,
+ .prog_clk_2_E_in ( p1773 ) , .prog_clk_2_W_in ( p1240 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4562 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4563 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4564 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[50] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4565 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p1386 ) ,
+ .clk_1_E_in ( p223 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4566 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4567 ) , .clk_2_E_in ( p1712 ) ,
+ .clk_2_W_in ( p986 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4568 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4569 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4570 ) ,
+ .clk_3_E_in ( clk_3_wires[50] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4571 ) ,
+ .clk_3_W_out ( clk_3_wires[51] ) ) ;
+cbx_1__1_ cbx_3__7_ ( .chanx_left_in ( sb_1__1__17_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__28_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__28_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__28_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__28_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) ,
+ .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1335 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4572 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[122] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4573 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4574 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[65] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[66] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2700 ) ,
+ .prog_clk_2_W_in ( p1491 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4575 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4576 ) ,
+ .prog_clk_3_W_in ( p1801 ) , .prog_clk_3_E_in ( p2507 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4577 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4578 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4579 ) ,
+ .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) ,
+ .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p2511 ) ,
+ .clk_2_W_in ( p222 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4580 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4581 ) , .clk_3_W_in ( p1801 ) ,
+ .clk_3_E_in ( p2629 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4582 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4583 ) ) ;
+cbx_1__1_ cbx_3__8_ ( .chanx_left_in ( sb_1__1__18_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__29_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__29_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__29_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__29_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) ,
+ .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p2069 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4584 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[125] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4585 ) ,
+ .prog_clk_1_W_in ( p1566 ) , .prog_clk_1_E_in ( p625 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4586 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4587 ) ,
+ .prog_clk_2_E_in ( p2340 ) , .prog_clk_2_W_in ( p13 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4588 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4589 ) ,
+ .prog_clk_3_W_in ( p1855 ) , .prog_clk_3_E_in ( p2455 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4590 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4591 ) , .clk_1_W_in ( p1566 ) ,
+ .clk_1_E_in ( p1896 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4592 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4593 ) , .clk_2_E_in ( p2626 ) ,
+ .clk_2_W_in ( p1495 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4594 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4595 ) , .clk_3_W_in ( p1790 ) ,
+ .clk_3_E_in ( p2678 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4596 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4597 ) ) ;
+cbx_1__1_ cbx_3__9_ ( .chanx_left_in ( sb_1__1__19_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__30_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__30_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__30_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__30_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) ,
+ .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1563 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4598 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[128] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4599 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4600 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[72] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[73] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p1539 ) ,
+ .prog_clk_2_W_in ( p1470 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4601 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4602 ) ,
+ .prog_clk_3_W_in ( p2112 ) , .prog_clk_3_E_in ( p2980 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4603 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4604 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4605 ) ,
+ .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) ,
+ .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p2999 ) ,
+ .clk_2_W_in ( p1890 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4606 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4607 ) , .clk_3_W_in ( p2112 ) ,
+ .clk_3_E_in ( p1365 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4608 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4609 ) ) ;
+cbx_1__1_ cbx_3__10_ ( .chanx_left_in ( sb_1__1__20_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__31_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__31_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__31_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__31_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) ,
+ .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1751 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4610 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[131] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4611 ) ,
+ .prog_clk_1_W_in ( p1414 ) , .prog_clk_1_E_in ( p529 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4612 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4613 ) ,
+ .prog_clk_2_E_in ( p2696 ) , .prog_clk_2_W_in ( p718 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4614 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4615 ) ,
+ .prog_clk_3_W_in ( p2771 ) , .prog_clk_3_E_in ( p2276 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4616 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4617 ) , .clk_1_W_in ( p1414 ) ,
+ .clk_1_E_in ( p531 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4618 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4619 ) , .clk_2_E_in ( p2290 ) ,
+ .clk_2_W_in ( p2683 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4620 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4621 ) , .clk_3_W_in ( p2771 ) ,
+ .clk_3_E_in ( p2672 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4622 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4623 ) ) ;
+cbx_1__1_ cbx_3__11_ ( .chanx_left_in ( sb_1__1__21_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__32_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__32_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__32_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__32_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) ,
+ .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1452 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4624 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[134] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4625 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4626 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[79] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[80] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p2317 ) ,
+ .prog_clk_2_W_in ( p1239 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4627 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4628 ) ,
+ .prog_clk_3_W_in ( p1732 ) , .prog_clk_3_E_in ( p2010 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4629 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4630 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4631 ) ,
+ .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) ,
+ .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p2144 ) ,
+ .clk_2_W_in ( p634 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4632 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4633 ) , .clk_3_W_in ( p1732 ) ,
+ .clk_3_E_in ( p2281 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4634 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4635 ) ) ;
+cbx_1__1_ cbx_4__1_ ( .chanx_left_in ( sb_1__1__22_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__33_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__33_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__33_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__33_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p2151 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4636 ) ,
+ .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[33] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[142] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4637 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[43] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4638 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[47] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p1835 ) ,
+ .prog_clk_2_W_in ( p1355 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4639 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4640 ) ,
+ .prog_clk_3_W_in ( p1626 ) , .prog_clk_3_E_in ( p2680 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4641 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4642 ) ,
+ .clk_1_W_in ( clk_1_wires[43] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4643 ) ,
+ .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) ,
+ .clk_2_E_in ( p2786 ) , .clk_2_W_in ( p2834 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4644 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4645 ) , .clk_3_W_in ( p2897 ) ,
+ .clk_3_E_in ( p1442 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4646 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4647 ) ) ;
+cbx_1__1_ cbx_4__2_ ( .chanx_left_in ( sb_1__1__23_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__34_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__34_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__34_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__34_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p1994 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4648 ) ,
+ .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[34] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[145] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4649 ) ,
+ .prog_clk_1_W_in ( p1021 ) , .prog_clk_1_E_in ( p1363 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4650 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4651 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[27] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4652 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[28] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4653 ) ,
+ .prog_clk_3_W_in ( p1802 ) , .prog_clk_3_E_in ( p1886 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4654 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4655 ) , .clk_1_W_in ( p1021 ) ,
+ .clk_1_E_in ( p759 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4656 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4657 ) ,
+ .clk_2_E_in ( clk_2_wires[27] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4658 ) ,
+ .clk_2_W_out ( clk_2_wires[28] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4659 ) , .clk_3_W_in ( p1802 ) ,
+ .clk_3_E_in ( p1231 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4660 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4661 ) ) ;
+cbx_1__1_ cbx_4__3_ ( .chanx_left_in ( sb_1__1__24_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__35_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__35_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__35_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__35_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p2121 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4662 ) ,
+ .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[35] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[148] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4663 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[50] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4664 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[54] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p1764 ) ,
+ .prog_clk_2_W_in ( p1047 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4665 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4666 ) ,
+ .prog_clk_3_W_in ( p2384 ) , .prog_clk_3_E_in ( p2654 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4667 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4668 ) ,
+ .clk_1_W_in ( clk_1_wires[50] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4669 ) ,
+ .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) ,
+ .clk_2_E_in ( p2779 ) , .clk_2_W_in ( p2258 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4670 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4671 ) , .clk_3_W_in ( p2403 ) ,
+ .clk_3_E_in ( p1319 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4672 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4673 ) ) ;
+cbx_1__1_ cbx_4__4_ ( .chanx_left_in ( sb_1__1__25_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__36_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__36_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__36_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__36_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p1531 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4674 ) ,
+ .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[36] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[151] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4675 ) ,
+ .prog_clk_1_W_in ( p1427 ) , .prog_clk_1_E_in ( p270 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4676 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4677 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[36] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4678 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[37] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4679 ) ,
+ .prog_clk_3_W_in ( p1618 ) , .prog_clk_3_E_in ( p491 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4680 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4681 ) , .clk_1_W_in ( p1598 ) ,
+ .clk_1_E_in ( p1429 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4682 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4683 ) ,
+ .clk_2_E_in ( clk_2_wires[36] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4684 ) ,
+ .clk_2_W_out ( clk_2_wires[37] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4685 ) , .clk_3_W_in ( p1618 ) ,
+ .clk_3_E_in ( p1428 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4686 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4687 ) ) ;
+cbx_1__1_ cbx_4__5_ ( .chanx_left_in ( sb_1__1__26_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__37_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__37_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__37_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__37_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p1778 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4688 ) ,
+ .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[37] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[154] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4689 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[57] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4690 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[61] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p2279 ) ,
+ .prog_clk_2_W_in ( p1086 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4691 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4692 ) ,
+ .prog_clk_3_W_in ( p2137 ) , .prog_clk_3_E_in ( p2282 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4693 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4694 ) ,
+ .clk_1_W_in ( clk_1_wires[57] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4695 ) ,
+ .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) ,
+ .clk_2_E_in ( p2417 ) , .clk_2_W_in ( p3057 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4696 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4697 ) , .clk_3_W_in ( p3101 ) ,
+ .clk_3_E_in ( p2204 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4698 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4699 ) ) ;
+cbx_1__1_ cbx_4__6_ ( .chanx_left_in ( sb_1__1__27_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__38_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__38_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__38_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__38_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1584 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4700 ) ,
+ .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[38] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[157] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4701 ) ,
+ .prog_clk_1_W_in ( p1656 ) , .prog_clk_1_E_in ( p1226 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4702 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4703 ) ,
+ .prog_clk_2_E_in ( p1551 ) , .prog_clk_2_W_in ( p484 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4704 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4705 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4706 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[46] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4707 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p1656 ) ,
+ .clk_1_E_in ( p383 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4708 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4709 ) , .clk_2_E_in ( p1837 ) ,
+ .clk_2_W_in ( p1373 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4710 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4711 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4712 ) ,
+ .clk_3_E_in ( clk_3_wires[46] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4713 ) ,
+ .clk_3_W_out ( clk_3_wires[47] ) ) ;
+cbx_1__1_ cbx_4__7_ ( .chanx_left_in ( sb_1__1__28_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__39_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__39_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__39_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__39_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p1862 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4714 ) ,
+ .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[39] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[160] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4715 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[64] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4716 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[68] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p2309 ) ,
+ .prog_clk_2_W_in ( p507 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4717 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4718 ) ,
+ .prog_clk_3_W_in ( p2569 ) , .prog_clk_3_E_in ( p22 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4719 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4720 ) ,
+ .clk_1_W_in ( clk_1_wires[64] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4721 ) ,
+ .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) ,
+ .clk_2_E_in ( p1862 ) , .clk_2_W_in ( p2443 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4722 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4723 ) , .clk_3_W_in ( p2579 ) ,
+ .clk_3_E_in ( p2177 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4724 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4725 ) ) ;
+cbx_1__1_ cbx_4__8_ ( .chanx_left_in ( sb_1__1__29_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__40_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__40_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__40_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__40_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p1687 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4726 ) ,
+ .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[40] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[163] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4727 ) ,
+ .prog_clk_1_W_in ( p755 ) , .prog_clk_1_E_in ( p664 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4728 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4729 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[49] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4730 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[50] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4731 ) ,
+ .prog_clk_3_W_in ( p1493 ) , .prog_clk_3_E_in ( p203 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4732 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4733 ) , .clk_1_W_in ( p755 ) ,
+ .clk_1_E_in ( p796 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4734 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4735 ) ,
+ .clk_2_E_in ( clk_2_wires[49] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4736 ) ,
+ .clk_2_W_out ( clk_2_wires[50] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_3_W_in ( p1493 ) ,
+ .clk_3_E_in ( p1339 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4738 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4739 ) ) ;
+cbx_1__1_ cbx_4__9_ ( .chanx_left_in ( sb_1__1__30_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__41_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__41_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__41_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__41_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p2313 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4740 ) ,
+ .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[41] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[166] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4741 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[71] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4742 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[75] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p1546 ) ,
+ .prog_clk_2_W_in ( p1369 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4743 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) ,
+ .prog_clk_3_W_in ( p2586 ) , .prog_clk_3_E_in ( p2664 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4745 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4746 ) ,
+ .clk_1_W_in ( clk_1_wires[71] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4747 ) ,
+ .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) ,
+ .clk_2_E_in ( p2719 ) , .clk_2_W_in ( p2821 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4748 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4749 ) , .clk_3_W_in ( p2881 ) ,
+ .clk_3_E_in ( p1357 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4750 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4751 ) ) ;
+cbx_1__1_ cbx_4__10_ ( .chanx_left_in ( sb_1__1__31_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__42_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__42_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__42_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__42_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1780 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4752 ) ,
+ .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[42] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[169] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4753 ) ,
+ .prog_clk_1_W_in ( p1496 ) , .prog_clk_1_E_in ( p577 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4754 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4755 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[62] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4756 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[63] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4757 ) ,
+ .prog_clk_3_W_in ( p1643 ) , .prog_clk_3_E_in ( p1484 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4758 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4759 ) , .clk_1_W_in ( p1496 ) ,
+ .clk_1_E_in ( p1380 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4760 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4761 ) ,
+ .clk_2_E_in ( clk_2_wires[62] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4762 ) ,
+ .clk_2_W_out ( clk_2_wires[63] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4763 ) , .clk_3_W_in ( p1643 ) ,
+ .clk_3_E_in ( p2429 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4764 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4765 ) ) ;
+cbx_1__1_ cbx_4__11_ ( .chanx_left_in ( sb_1__1__32_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__43_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__43_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__43_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__43_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p2302 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4766 ) ,
+ .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[43] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[172] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4767 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[78] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4768 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[82] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p2739 ) ,
+ .prog_clk_2_W_in ( p1020 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4769 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4770 ) ,
+ .prog_clk_3_W_in ( p2166 ) , .prog_clk_3_E_in ( p2690 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4771 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4772 ) ,
+ .clk_1_W_in ( clk_1_wires[78] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4773 ) ,
+ .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) ,
+ .clk_2_E_in ( p2767 ) , .clk_2_W_in ( p2836 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4774 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4775 ) , .clk_3_W_in ( p2874 ) ,
+ .clk_3_E_in ( p2645 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4776 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4777 ) ) ;
+cbx_1__1_ cbx_5__1_ ( .chanx_left_in ( sb_1__1__33_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__44_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__44_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__44_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__44_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) ,
+ .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1818 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4778 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[180] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4779 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4780 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[86] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[87] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p2926 ) ,
+ .prog_clk_2_W_in ( p1543 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4781 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4782 ) ,
+ .prog_clk_3_W_in ( p2543 ) , .prog_clk_3_E_in ( p2000 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4783 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4784 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4785 ) ,
+ .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) ,
+ .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p2132 ) ,
+ .clk_2_W_in ( p2470 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4786 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4787 ) , .clk_3_W_in ( p2543 ) ,
+ .clk_3_E_in ( p2825 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4788 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4789 ) ) ;
+cbx_1__1_ cbx_5__2_ ( .chanx_left_in ( sb_1__1__34_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__45_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__45_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__45_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__45_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) ,
+ .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p1762 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4790 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[183] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4791 ) ,
+ .prog_clk_1_W_in ( p1404 ) , .prog_clk_1_E_in ( p369 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4792 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4793 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4794 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[25] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4795 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1836 ) ,
+ .prog_clk_3_E_in ( p253 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4796 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4797 ) , .clk_1_W_in ( p1404 ) ,
+ .clk_1_E_in ( p1265 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4798 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4799 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4800 ) ,
+ .clk_2_W_in ( clk_2_wires[25] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4801 ) ,
+ .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1836 ) ,
+ .clk_3_E_in ( p1939 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4802 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4803 ) ) ;
+cbx_1__1_ cbx_5__3_ ( .chanx_left_in ( sb_1__1__35_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__46_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__46_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__46_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__46_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) ,
+ .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1456 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4804 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[186] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4805 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4806 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[93] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[94] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p2587 ) ,
+ .prog_clk_2_W_in ( p52 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4807 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4808 ) ,
+ .prog_clk_3_W_in ( p2594 ) , .prog_clk_3_E_in ( p1966 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4809 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4810 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4811 ) ,
+ .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) ,
+ .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p2067 ) ,
+ .clk_2_W_in ( p2966 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4812 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4813 ) , .clk_3_W_in ( p3018 ) ,
+ .clk_3_E_in ( p2489 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4814 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4815 ) ) ;
+cbx_1__1_ cbx_5__4_ ( .chanx_left_in ( sb_1__1__36_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__47_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__47_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__47_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__47_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) ,
+ .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p2116 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4816 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[189] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4817 ) ,
+ .prog_clk_1_W_in ( p1497 ) , .prog_clk_1_E_in ( p966 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4818 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4819 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4820 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[34] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4821 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1242 ) ,
+ .prog_clk_3_E_in ( p393 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4822 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4823 ) , .clk_1_W_in ( p1497 ) ,
+ .clk_1_E_in ( p1943 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4824 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4825 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4826 ) ,
+ .clk_2_W_in ( clk_2_wires[34] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4827 ) ,
+ .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1242 ) ,
+ .clk_3_E_in ( p2472 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4828 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4829 ) ) ;
+cbx_1__1_ cbx_5__5_ ( .chanx_left_in ( sb_1__1__37_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__48_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__48_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__48_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__48_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) ,
+ .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1666 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4830 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[192] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4831 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4832 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[100] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[101] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p2133 ) ,
+ .prog_clk_2_W_in ( p1284 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4833 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4834 ) ,
+ .prog_clk_3_W_in ( p2400 ) , .prog_clk_3_E_in ( p2474 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4835 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4836 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4837 ) ,
+ .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) ,
+ .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p2565 ) ,
+ .clk_2_W_in ( p2226 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4838 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4839 ) , .clk_3_W_in ( p2406 ) ,
+ .clk_3_E_in ( p1991 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4840 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4841 ) ) ;
+cbx_1__1_ cbx_5__6_ ( .chanx_left_in ( sb_1__1__38_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__49_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__49_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__49_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__49_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) ,
+ .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p2149 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4842 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[195] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4843 ) ,
+ .prog_clk_1_W_in ( p1692 ) , .prog_clk_1_E_in ( p261 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4844 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4845 ) ,
+ .prog_clk_2_E_in ( p1697 ) , .prog_clk_2_W_in ( p683 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4846 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4847 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4848 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[6] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4849 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p1692 ) ,
+ .clk_1_E_in ( p1892 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4850 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4851 ) , .clk_2_E_in ( p1697 ) ,
+ .clk_2_W_in ( p1299 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4852 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4853 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4854 ) ,
+ .clk_3_E_in ( clk_3_wires[6] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4855 ) ,
+ .clk_3_W_out ( clk_3_wires[7] ) ) ;
+cbx_1__1_ cbx_5__7_ ( .chanx_left_in ( sb_1__1__39_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__50_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__50_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__50_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__50_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) ,
+ .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p2347 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4856 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[198] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4857 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4858 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[107] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[108] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p2325 ) ,
+ .prog_clk_2_W_in ( p1289 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4859 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4860 ) ,
+ .prog_clk_3_W_in ( p2170 ) , .prog_clk_3_E_in ( p1951 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4861 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4862 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4863 ) ,
+ .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) ,
+ .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p2115 ) ,
+ .clk_2_W_in ( p1952 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4864 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4865 ) , .clk_3_W_in ( p2170 ) ,
+ .clk_3_E_in ( p2275 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4866 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4867 ) ) ;
+cbx_1__1_ cbx_5__8_ ( .chanx_left_in ( sb_1__1__40_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__51_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__51_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__51_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__51_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) ,
+ .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1463 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4868 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[201] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4869 ) ,
+ .prog_clk_1_W_in ( p1396 ) , .prog_clk_1_E_in ( p81 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4870 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4871 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4872 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[47] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4873 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1513 ) ,
+ .prog_clk_3_E_in ( p1343 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4874 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4875 ) , .clk_1_W_in ( p1396 ) ,
+ .clk_1_E_in ( p1119 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4876 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4877 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4878 ) ,
+ .clk_2_W_in ( clk_2_wires[47] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4879 ) ,
+ .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1513 ) ,
+ .clk_3_E_in ( p2222 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4880 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4881 ) ) ;
+cbx_1__1_ cbx_5__9_ ( .chanx_left_in ( sb_1__1__41_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__52_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__52_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__52_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__52_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) ,
+ .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1367 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4882 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[204] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4883 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4884 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[114] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[115] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p1821 ) ,
+ .prog_clk_2_W_in ( p456 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4885 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4886 ) ,
+ .prog_clk_3_W_in ( p2787 ) , .prog_clk_3_E_in ( p2817 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4887 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4888 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4889 ) ,
+ .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) ,
+ .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p2906 ) ,
+ .clk_2_W_in ( p2649 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4890 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4891 ) , .clk_3_W_in ( p2787 ) ,
+ .clk_3_E_in ( p1133 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4892 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4893 ) ) ;
+cbx_1__1_ cbx_5__10_ ( .chanx_left_in ( sb_1__1__42_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__53_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__53_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__53_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__53_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) ,
+ .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1385 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4894 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[207] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4895 ) ,
+ .prog_clk_1_W_in ( p1608 ) , .prog_clk_1_E_in ( p461 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4896 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4897 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4898 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[60] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4899 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p1657 ) ,
+ .prog_clk_3_E_in ( p291 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4900 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4901 ) , .clk_1_W_in ( p1608 ) ,
+ .clk_1_E_in ( p999 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4902 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4903 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4904 ) ,
+ .clk_2_W_in ( clk_2_wires[60] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4905 ) ,
+ .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p1657 ) ,
+ .clk_3_E_in ( p2197 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4906 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4907 ) ) ;
+cbx_1__1_ cbx_5__11_ ( .chanx_left_in ( sb_1__1__43_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__54_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__54_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__54_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__54_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) ,
+ .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1336 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4908 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[210] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4909 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4910 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[121] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[122] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p1591 ) ,
+ .prog_clk_2_W_in ( p958 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4911 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4912 ) ,
+ .prog_clk_3_W_in ( p2320 ) , .prog_clk_3_E_in ( p2486 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4913 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4914 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4915 ) ,
+ .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) ,
+ .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p2625 ) ,
+ .clk_2_W_in ( p2208 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4916 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4917 ) , .clk_3_W_in ( p2320 ) ,
+ .clk_3_E_in ( p1556 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4918 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4919 ) ) ;
+cbx_1__1_ cbx_6__1_ ( .chanx_left_in ( sb_1__1__44_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__55_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__55_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__55_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__55_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p2382 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4920 ) ,
+ .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[55] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[218] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4921 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[85] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4922 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[89] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p2867 ) ,
+ .prog_clk_2_W_in ( p1082 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4923 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4924 ) ,
+ .prog_clk_3_W_in ( p1469 ) , .prog_clk_3_E_in ( p2674 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4925 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4926 ) ,
+ .clk_1_W_in ( clk_1_wires[85] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4927 ) ,
+ .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) ,
+ .clk_2_E_in ( p2792 ) , .clk_2_W_in ( p787 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4928 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4929 ) , .clk_3_W_in ( p1469 ) ,
+ .clk_3_E_in ( p2829 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4930 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4931 ) ) ;
+cbx_1__1_ cbx_6__2_ ( .chanx_left_in ( sb_1__1__45_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__56_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__56_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__56_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__56_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1797 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4932 ) ,
+ .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[56] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[221] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4933 ) ,
+ .prog_clk_1_W_in ( p1568 ) , .prog_clk_1_E_in ( p835 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4934 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4935 ) ,
+ .prog_clk_2_E_in ( p2147 ) , .prog_clk_2_W_in ( p905 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4936 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4937 ) ,
+ .prog_clk_3_W_in ( p1670 ) , .prog_clk_3_E_in ( p1928 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4938 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4939 ) , .clk_1_W_in ( p1568 ) ,
+ .clk_1_E_in ( p408 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4940 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4941 ) , .clk_2_E_in ( p2030 ) ,
+ .clk_2_W_in ( p1314 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4942 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4943 ) , .clk_3_W_in ( p1670 ) ,
+ .clk_3_E_in ( p2006 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4944 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4945 ) ) ;
+cbx_1__1_ cbx_6__3_ ( .chanx_left_in ( sb_1__1__46_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__57_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__57_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__57_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__57_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p1440 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4946 ) ,
+ .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[57] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[224] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4947 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[92] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4948 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[96] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p2751 ) ,
+ .prog_clk_2_W_in ( p532 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4949 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4950 ) ,
+ .prog_clk_3_W_in ( p1649 ) , .prog_clk_3_E_in ( p2634 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4951 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4952 ) ,
+ .clk_1_W_in ( clk_1_wires[92] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4953 ) ,
+ .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) ,
+ .clk_2_E_in ( p2768 ) , .clk_2_W_in ( p1345 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4954 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4955 ) , .clk_3_W_in ( p1649 ) ,
+ .clk_3_E_in ( p2697 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4956 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4957 ) ) ;
+cbx_1__1_ cbx_6__4_ ( .chanx_left_in ( sb_1__1__47_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__58_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__58_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__58_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__58_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p1613 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4958 ) ,
+ .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[58] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[227] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4959 ) ,
+ .prog_clk_1_W_in ( p1489 ) , .prog_clk_1_E_in ( p700 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4960 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4961 ) ,
+ .prog_clk_2_E_in ( p1506 ) , .prog_clk_2_W_in ( p930 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4962 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4963 ) ,
+ .prog_clk_3_W_in ( p1668 ) , .prog_clk_3_E_in ( p347 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4964 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4965 ) , .clk_1_W_in ( p1489 ) ,
+ .clk_1_E_in ( p1092 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4966 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4967 ) , .clk_2_E_in ( p1613 ) ,
+ .clk_2_W_in ( p346 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4968 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4969 ) , .clk_3_W_in ( p1640 ) ,
+ .clk_3_E_in ( p686 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4970 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4971 ) ) ;
+cbx_1__1_ cbx_6__5_ ( .chanx_left_in ( sb_1__1__48_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__59_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__59_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__59_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__59_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p2305 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4972 ) ,
+ .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[59] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[230] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4973 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[99] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4974 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[103] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p2424 ) ,
+ .prog_clk_2_W_in ( p1441 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4975 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4976 ) ,
+ .prog_clk_3_W_in ( p1771 ) , .prog_clk_3_E_in ( p2830 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4977 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4978 ) ,
+ .clk_1_W_in ( clk_1_wires[99] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4979 ) ,
+ .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) ,
+ .clk_2_E_in ( p2912 ) , .clk_2_W_in ( p842 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4980 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4981 ) , .clk_3_W_in ( p1771 ) ,
+ .clk_3_E_in ( p2286 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4982 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4983 ) ) ;
+cbx_1__1_ cbx_6__6_ ( .chanx_left_in ( sb_1__1__49_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__60_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__60_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__60_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__60_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p1816 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4984 ) ,
+ .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[60] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[233] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4985 ) ,
+ .prog_clk_1_W_in ( p1747 ) , .prog_clk_1_E_in ( p951 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4986 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4987 ) ,
+ .prog_clk_2_E_in ( p2415 ) , .prog_clk_2_W_in ( p131 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4988 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4989 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4990 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[2] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4991 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p1747 ) ,
+ .clk_1_E_in ( p609 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4992 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4993 ) , .clk_2_E_in ( p1786 ) ,
+ .clk_2_W_in ( p1413 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4994 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4995 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4996 ) ,
+ .clk_3_E_in ( clk_3_wires[2] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4997 ) ,
+ .clk_3_W_out ( clk_3_wires[3] ) ) ;
+cbx_1__1_ cbx_6__7_ ( .chanx_left_in ( sb_1__1__50_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__61_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__61_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__61_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__61_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p2408 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4998 ) ,
+ .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[61] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[236] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4999 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[106] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5000 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[110] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p2402 ) ,
+ .prog_clk_2_W_in ( p277 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5001 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5002 ) ,
+ .prog_clk_3_W_in ( p2546 ) , .prog_clk_3_E_in ( p2263 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5003 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5004 ) ,
+ .clk_1_W_in ( clk_1_wires[106] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5005 ) ,
+ .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) ,
+ .clk_2_E_in ( p2408 ) , .clk_2_W_in ( p2485 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5006 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5007 ) , .clk_3_W_in ( p2573 ) ,
+ .clk_3_E_in ( p2193 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5008 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5009 ) ) ;
+cbx_1__1_ cbx_6__8_ ( .chanx_left_in ( sb_1__1__51_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__62_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__62_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__62_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__62_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p1800 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5010 ) ,
+ .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[62] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[239] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5011 ) ,
+ .prog_clk_1_W_in ( p1473 ) , .prog_clk_1_E_in ( p1438 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5012 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5013 ) ,
+ .prog_clk_2_E_in ( p1772 ) , .prog_clk_2_W_in ( p812 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5014 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5015 ) ,
+ .prog_clk_3_W_in ( p1594 ) , .prog_clk_3_E_in ( p96 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5016 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5017 ) , .clk_1_W_in ( p1473 ) ,
+ .clk_1_E_in ( p559 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5018 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5019 ) , .clk_2_E_in ( p1800 ) ,
+ .clk_2_W_in ( p1189 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5020 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5021 ) , .clk_3_W_in ( p1594 ) ,
+ .clk_3_E_in ( p1063 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5022 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5023 ) ) ;
+cbx_1__1_ cbx_6__9_ ( .chanx_left_in ( sb_1__1__52_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__63_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__63_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__63_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__63_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p2291 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5024 ) ,
+ .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[63] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[242] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5025 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[113] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5026 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[117] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2510 ) ,
+ .prog_clk_2_W_in ( p1303 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5027 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5028 ) ,
+ .prog_clk_3_W_in ( p1416 ) , .prog_clk_3_E_in ( p2960 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5029 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5030 ) ,
+ .clk_1_W_in ( clk_1_wires[113] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5031 ) ,
+ .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) ,
+ .clk_2_E_in ( p3022 ) , .clk_2_W_in ( p521 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5032 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5033 ) , .clk_3_W_in ( p1416 ) ,
+ .clk_3_E_in ( p2433 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5034 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5035 ) ) ;
+cbx_1__1_ cbx_6__10_ ( .chanx_left_in ( sb_1__1__53_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__64_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__64_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__64_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__64_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p2096 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5036 ) ,
+ .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[64] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[245] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5037 ) ,
+ .prog_clk_1_W_in ( p1686 ) , .prog_clk_1_E_in ( p668 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5038 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5039 ) ,
+ .prog_clk_2_E_in ( p2113 ) , .prog_clk_2_W_in ( p1564 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5040 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5041 ) ,
+ .prog_clk_3_W_in ( p2052 ) , .prog_clk_3_E_in ( p2800 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5042 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5043 ) , .clk_1_W_in ( p1686 ) ,
+ .clk_1_E_in ( p1308 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5044 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5045 ) , .clk_2_E_in ( p2934 ) ,
+ .clk_2_W_in ( p1941 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5046 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5047 ) , .clk_3_W_in ( p2052 ) ,
+ .clk_3_E_in ( p1993 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5048 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5049 ) ) ;
+cbx_1__1_ cbx_6__11_ ( .chanx_left_in ( sb_1__1__54_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__65_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__65_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__65_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__65_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p1882 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5050 ) ,
+ .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[65] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[248] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5051 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[120] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5052 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[124] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p2292 ) ,
+ .prog_clk_2_W_in ( p657 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5053 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5054 ) ,
+ .prog_clk_3_W_in ( p1434 ) , .prog_clk_3_E_in ( p1447 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5055 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5056 ) ,
+ .clk_1_W_in ( clk_1_wires[120] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5057 ) ,
+ .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) ,
+ .clk_2_E_in ( p1882 ) , .clk_2_W_in ( p2181 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5058 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5059 ) , .clk_3_W_in ( p2326 ) ,
+ .clk_3_E_in ( p2188 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5060 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5061 ) ) ;
+cbx_1__1_ cbx_7__1_ ( .chanx_left_in ( sb_1__1__55_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__66_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__66_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__66_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__66_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) ,
+ .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p1781 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5062 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[256] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5063 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5064 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[128] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[129] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p1737 ) ,
+ .prog_clk_2_W_in ( p1254 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5065 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5066 ) ,
+ .prog_clk_3_W_in ( p1770 ) , .prog_clk_3_E_in ( p2497 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5067 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5068 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5069 ) ,
+ .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) ,
+ .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p2541 ) ,
+ .clk_2_W_in ( p760 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5070 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5071 ) , .clk_3_W_in ( p1770 ) ,
+ .clk_3_E_in ( p29 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5072 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5073 ) ) ;
+cbx_1__1_ cbx_7__2_ ( .chanx_left_in ( sb_1__1__56_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__67_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__67_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__67_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__67_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) ,
+ .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2518 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5074 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[259] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5075 ) ,
+ .prog_clk_1_W_in ( p1789 ) , .prog_clk_1_E_in ( p534 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5076 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5077 ) ,
+ .prog_clk_2_E_in ( p1749 ) , .prog_clk_2_W_in ( p1462 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5078 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5079 ) ,
+ .prog_clk_3_W_in ( p1867 ) , .prog_clk_3_E_in ( p1932 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5080 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5081 ) , .clk_1_W_in ( p1789 ) ,
+ .clk_1_E_in ( p2462 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5082 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5083 ) , .clk_2_E_in ( p2058 ) ,
+ .clk_2_W_in ( p67 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5084 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5085 ) , .clk_3_W_in ( p1867 ) ,
+ .clk_3_E_in ( p148 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5086 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5087 ) ) ;
+cbx_1__1_ cbx_7__3_ ( .chanx_left_in ( sb_1__1__57_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__68_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__68_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__68_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__68_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) ,
+ .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1528 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5088 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[262] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5089 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5090 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[135] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[136] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p1842 ) ,
+ .prog_clk_2_W_in ( p1176 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5091 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5092 ) ,
+ .prog_clk_3_W_in ( p2064 ) , .prog_clk_3_E_in ( p2811 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5093 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5094 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5095 ) ,
+ .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) ,
+ .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2894 ) ,
+ .clk_2_W_in ( p1969 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5096 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5097 ) , .clk_3_W_in ( p2064 ) ,
+ .clk_3_E_in ( p604 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5098 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5099 ) ) ;
+cbx_1__1_ cbx_7__4_ ( .chanx_left_in ( sb_1__1__58_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__69_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__69_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__69_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__69_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) ,
+ .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1419 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5100 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[265] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5101 ) ,
+ .prog_clk_1_W_in ( p1582 ) , .prog_clk_1_E_in ( p1332 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5102 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5103 ) ,
+ .prog_clk_2_E_in ( p2127 ) , .prog_clk_2_W_in ( p1384 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5104 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5105 ) ,
+ .prog_clk_3_W_in ( p1791 ) , .prog_clk_3_E_in ( p3168 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5106 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5107 ) , .clk_1_W_in ( p1582 ) ,
+ .clk_1_E_in ( p434 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5108 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5109 ) , .clk_2_E_in ( p3203 ) ,
+ .clk_2_W_in ( p481 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5110 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5111 ) , .clk_3_W_in ( p1791 ) ,
+ .clk_3_E_in ( p1982 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5112 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5113 ) ) ;
+cbx_1__1_ cbx_7__5_ ( .chanx_left_in ( sb_1__1__59_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__70_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__70_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__70_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__70_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) ,
+ .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1588 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5114 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[268] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5115 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5116 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[142] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[143] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p280 ) ,
+ .prog_clk_2_W_in ( p110 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5117 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5118 ) ,
+ .prog_clk_3_W_in ( p1665 ) , .prog_clk_3_E_in ( p3249 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5119 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5120 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5121 ) ,
+ .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) ,
+ .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p3267 ) ,
+ .clk_2_W_in ( p926 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5122 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5123 ) , .clk_3_W_in ( p1665 ) ,
+ .clk_3_E_in ( p792 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5124 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5125 ) ) ;
+cbx_1__1_ cbx_7__6_ ( .chanx_left_in ( sb_1__1__60_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__71_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__71_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__71_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__71_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) ,
+ .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p2418 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5126 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[271] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5127 ) ,
+ .prog_clk_1_W_in ( p1607 ) , .prog_clk_1_E_in ( p1175 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5128 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5129 ) ,
+ .prog_clk_2_E_in ( p2354 ) , .prog_clk_2_W_in ( p447 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5130 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5131 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[0] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5132 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[1] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5133 ) , .clk_1_W_in ( p1607 ) ,
+ .clk_1_E_in ( p2255 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5134 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5135 ) , .clk_2_E_in ( p1620 ) ,
+ .clk_2_W_in ( p1403 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5136 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5137 ) ,
+ .clk_3_W_in ( clk_3_wires[0] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5138 ) ,
+ .clk_3_E_out ( clk_3_wires[1] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5139 ) ) ;
+cbx_1__1_ cbx_7__7_ ( .chanx_left_in ( sb_1__1__61_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__72_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__72_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__72_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__72_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) ,
+ .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p1767 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5140 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[274] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5141 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5142 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[149] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[150] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p2173 ) ,
+ .prog_clk_2_W_in ( p882 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5143 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5144 ) ,
+ .prog_clk_3_W_in ( p2271 ) , .prog_clk_3_E_in ( p2983 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5145 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5146 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5147 ) ,
+ .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) ,
+ .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p2990 ) ,
+ .clk_2_W_in ( p2234 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5148 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5149 ) , .clk_3_W_in ( p2271 ) ,
+ .clk_3_E_in ( p1950 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5150 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5151 ) ) ;
+cbx_1__1_ cbx_7__8_ ( .chanx_left_in ( sb_1__1__62_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__73_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__73_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__73_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__73_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) ,
+ .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p1785 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5152 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[277] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5153 ) ,
+ .prog_clk_1_W_in ( p1809 ) , .prog_clk_1_E_in ( p1281 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5154 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5155 ) ,
+ .prog_clk_2_E_in ( p1562 ) , .prog_clk_2_W_in ( p725 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5156 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5157 ) ,
+ .prog_clk_3_W_in ( p2342 ) , .prog_clk_3_E_in ( p2823 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5158 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5159 ) , .clk_1_W_in ( p1509 ) ,
+ .clk_1_E_in ( p209 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5160 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5161 ) , .clk_2_E_in ( p2884 ) ,
+ .clk_2_W_in ( p2838 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5162 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5163 ) , .clk_3_W_in ( p2919 ) ,
+ .clk_3_E_in ( p2499 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5164 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5165 ) ) ;
+cbx_1__1_ cbx_7__9_ ( .chanx_left_in ( sb_1__1__63_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__74_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__74_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__74_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__74_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) ,
+ .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p799 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5166 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[280] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5167 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5168 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[156] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[157] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p2092 ) ,
+ .prog_clk_2_W_in ( p640 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5169 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5170 ) ,
+ .prog_clk_3_W_in ( p2703 ) , .prog_clk_3_E_in ( p2844 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5171 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5172 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5173 ) ,
+ .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) ,
+ .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p2891 ) ,
+ .clk_2_W_in ( p2686 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5174 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5175 ) , .clk_3_W_in ( p2755 ) ,
+ .clk_3_E_in ( p1984 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5176 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5177 ) ) ;
+cbx_1__1_ cbx_7__10_ ( .chanx_left_in ( sb_1__1__64_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__75_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__75_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__75_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__75_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) ,
+ .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p2119 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5178 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[283] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5179 ) ,
+ .prog_clk_1_W_in ( p1535 ) , .prog_clk_1_E_in ( p704 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5180 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5181 ) ,
+ .prog_clk_2_E_in ( p2070 ) , .prog_clk_2_W_in ( p701 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5182 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5183 ) ,
+ .prog_clk_3_W_in ( p1486 ) , .prog_clk_3_E_in ( p2820 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5184 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5185 ) , .clk_1_W_in ( p1535 ) ,
+ .clk_1_E_in ( p1934 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5186 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5187 ) , .clk_2_E_in ( p2928 ) ,
+ .clk_2_W_in ( p1291 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5188 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5189 ) , .clk_3_W_in ( p1486 ) ,
+ .clk_3_E_in ( p2001 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5190 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5191 ) ) ;
+cbx_1__1_ cbx_7__11_ ( .chanx_left_in ( sb_1__1__65_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__76_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__76_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__76_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__76_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) ,
+ .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1398 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5192 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[286] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5193 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5194 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[163] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[164] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2139 ) ,
+ .prog_clk_2_W_in ( p837 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5195 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5196 ) ,
+ .prog_clk_3_W_in ( p1989 ) , .prog_clk_3_E_in ( p2692 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5197 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5198 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5199 ) ,
+ .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) ,
+ .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p2757 ) ,
+ .clk_2_W_in ( p1888 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5200 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5201 ) , .clk_3_W_in ( p2141 ) ,
+ .clk_3_E_in ( p1964 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5202 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5203 ) ) ;
+cbx_1__1_ cbx_8__1_ ( .chanx_left_in ( sb_1__1__66_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__77_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__77_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__77_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__77_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p2095 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5204 ) ,
+ .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[77] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[294] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5205 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[127] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5206 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[131] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p2532 ) ,
+ .prog_clk_2_W_in ( p1215 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5207 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5208 ) ,
+ .prog_clk_3_W_in ( p2117 ) , .prog_clk_3_E_in ( p2504 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5209 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5210 ) ,
+ .clk_1_W_in ( clk_1_wires[127] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5211 ) ,
+ .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) ,
+ .clk_2_E_in ( p2601 ) , .clk_2_W_in ( p1956 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5212 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5213 ) , .clk_3_W_in ( p2126 ) ,
+ .clk_3_E_in ( p2427 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5214 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5215 ) ) ;
+cbx_1__1_ cbx_8__2_ ( .chanx_left_in ( sb_1__1__67_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__78_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__78_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__78_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__78_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p2063 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5216 ) ,
+ .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[78] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[297] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5217 ) ,
+ .prog_clk_1_W_in ( p1725 ) , .prog_clk_1_E_in ( p953 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5218 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5219 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[71] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5220 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[72] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5221 ) ,
+ .prog_clk_3_W_in ( p2114 ) , .prog_clk_3_E_in ( p1953 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5222 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5223 ) , .clk_1_W_in ( p1725 ) ,
+ .clk_1_E_in ( p413 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5224 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5225 ) ,
+ .clk_2_E_in ( clk_2_wires[71] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5226 ) ,
+ .clk_2_W_out ( clk_2_wires[72] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5227 ) , .clk_3_W_in ( p2114 ) ,
+ .clk_3_E_in ( p1350 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5228 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5229 ) ) ;
+cbx_1__1_ cbx_8__3_ ( .chanx_left_in ( sb_1__1__68_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__79_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__79_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__79_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__79_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p1717 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5230 ) ,
+ .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[79] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[300] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5231 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[134] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5232 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[138] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p1777 ) ,
+ .prog_clk_2_W_in ( p3 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5233 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5234 ) ,
+ .prog_clk_3_W_in ( p2377 ) , .prog_clk_3_E_in ( p208 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5235 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5236 ) ,
+ .clk_1_W_in ( clk_1_wires[134] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5237 ) ,
+ .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) ,
+ .clk_2_E_in ( p1868 ) , .clk_2_W_in ( p2210 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5238 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5239 ) , .clk_3_W_in ( p2377 ) ,
+ .clk_3_E_in ( p1168 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5240 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5241 ) ) ;
+cbx_1__1_ cbx_8__4_ ( .chanx_left_in ( sb_1__1__69_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__80_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__80_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__80_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__80_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p2273 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5242 ) ,
+ .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[80] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[303] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5243 ) ,
+ .prog_clk_1_W_in ( p1610 ) , .prog_clk_1_E_in ( p259 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5244 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5245 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[80] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5246 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[81] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5247 ) ,
+ .prog_clk_3_W_in ( p2118 ) , .prog_clk_3_E_in ( p2228 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5248 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_W_in ( p1610 ) ,
+ .clk_1_E_in ( p1122 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5250 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5251 ) ,
+ .clk_2_E_in ( clk_2_wires[80] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5252 ) ,
+ .clk_2_W_out ( clk_2_wires[81] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5253 ) , .clk_3_W_in ( p2041 ) ,
+ .clk_3_E_in ( p20 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5254 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5255 ) ) ;
+cbx_1__1_ cbx_8__5_ ( .chanx_left_in ( sb_1__1__70_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__81_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__81_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__81_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__81_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p2556 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5256 ) ,
+ .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[81] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[306] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5257 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[141] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5258 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[145] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p2298 ) ,
+ .prog_clk_2_W_in ( p1381 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5259 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5260 ) ,
+ .prog_clk_3_W_in ( p2004 ) , .prog_clk_3_E_in ( p3087 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5261 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5262 ) ,
+ .clk_1_W_in ( clk_1_wires[141] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5263 ) ,
+ .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) ,
+ .clk_2_E_in ( p3140 ) , .clk_2_W_in ( p2635 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5264 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5265 ) , .clk_3_W_in ( p2775 ) ,
+ .clk_3_E_in ( p2264 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5266 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5267 ) ) ;
+cbx_1__1_ cbx_8__6_ ( .chanx_left_in ( sb_1__1__71_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__82_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__82_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__82_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__82_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1524 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5268 ) ,
+ .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[82] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[309] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5269 ) ,
+ .prog_clk_1_W_in ( p1541 ) , .prog_clk_1_E_in ( p415 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5270 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5271 ) ,
+ .prog_clk_2_E_in ( p2167 ) , .prog_clk_2_W_in ( p623 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5272 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5273 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[4] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5274 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[5] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5275 ) , .clk_1_W_in ( p1541 ) ,
+ .clk_1_E_in ( p1347 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5276 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5277 ) , .clk_2_E_in ( p1524 ) ,
+ .clk_2_W_in ( p795 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5278 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5279 ) ,
+ .clk_3_W_in ( clk_3_wires[4] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5280 ) ,
+ .clk_3_E_out ( clk_3_wires[5] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5281 ) ) ;
+cbx_1__1_ cbx_8__7_ ( .chanx_left_in ( sb_1__1__72_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__83_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__83_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__83_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__83_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p2606 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5282 ) ,
+ .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[83] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[312] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5283 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[148] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5284 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[152] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p2356 ) ,
+ .prog_clk_2_W_in ( p1166 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5285 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5286 ) ,
+ .prog_clk_3_W_in ( p3010 ) , .prog_clk_3_E_in ( p2488 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5287 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5288 ) ,
+ .clk_1_W_in ( clk_1_wires[148] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5289 ) ,
+ .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) ,
+ .clk_2_E_in ( p2606 ) , .clk_2_W_in ( p2941 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5290 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5291 ) , .clk_3_W_in ( p3010 ) ,
+ .clk_3_E_in ( p2195 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5292 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5293 ) ) ;
+cbx_1__1_ cbx_8__8_ ( .chanx_left_in ( sb_1__1__73_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__84_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__84_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__84_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__84_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p2574 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5294 ) ,
+ .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[84] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[315] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5295 ) ,
+ .prog_clk_1_W_in ( p1567 ) , .prog_clk_1_E_in ( p582 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5296 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5297 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[93] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5298 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[94] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5299 ) ,
+ .prog_clk_3_W_in ( p1723 ) , .prog_clk_3_E_in ( p2481 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5300 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5301 ) , .clk_1_W_in ( p1567 ) ,
+ .clk_1_E_in ( p436 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5302 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5303 ) ,
+ .clk_2_E_in ( clk_2_wires[93] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5304 ) ,
+ .clk_2_W_out ( clk_2_wires[94] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5305 ) , .clk_3_W_in ( p1723 ) ,
+ .clk_3_E_in ( p213 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5306 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5307 ) ) ;
+cbx_1__1_ cbx_8__9_ ( .chanx_left_in ( sb_1__1__74_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__85_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__85_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__85_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__85_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p2035 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5308 ) ,
+ .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[85] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[318] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5309 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[155] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5310 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[159] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p2353 ) ,
+ .prog_clk_2_W_in ( p1103 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5311 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5312 ) ,
+ .prog_clk_3_W_in ( p1639 ) , .prog_clk_3_E_in ( p2837 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5313 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5314 ) ,
+ .clk_1_W_in ( clk_1_wires[155] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5315 ) ,
+ .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) ,
+ .clk_2_E_in ( p2898 ) , .clk_2_W_in ( p2432 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5316 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5317 ) , .clk_3_W_in ( p2618 ) ,
+ .clk_3_E_in ( p2214 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5318 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5319 ) ) ;
+cbx_1__1_ cbx_8__10_ ( .chanx_left_in ( sb_1__1__75_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__86_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__86_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__86_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__86_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p1565 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5320 ) ,
+ .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[86] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[321] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5321 ) ,
+ .prog_clk_1_W_in ( p1660 ) , .prog_clk_1_E_in ( p359 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5322 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5323 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[106] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5324 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[107] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5325 ) ,
+ .prog_clk_3_W_in ( p1676 ) , .prog_clk_3_E_in ( p740 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5326 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5327 ) , .clk_1_W_in ( p1660 ) ,
+ .clk_1_E_in ( p1224 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5328 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5329 ) ,
+ .clk_2_E_in ( clk_2_wires[106] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5330 ) ,
+ .clk_2_W_out ( clk_2_wires[107] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5331 ) , .clk_3_W_in ( p1676 ) ,
+ .clk_3_E_in ( p2240 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5332 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5333 ) ) ;
+cbx_1__1_ cbx_8__11_ ( .chanx_left_in ( sb_1__1__76_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__87_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__87_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__87_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__87_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p1678 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5334 ) ,
+ .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[87] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[324] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5335 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[162] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5336 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[166] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p2603 ) ,
+ .prog_clk_2_W_in ( p768 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5337 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5338 ) ,
+ .prog_clk_3_W_in ( p1478 ) , .prog_clk_3_E_in ( p3158 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5339 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5340 ) ,
+ .clk_1_W_in ( clk_1_wires[162] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5341 ) ,
+ .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) ,
+ .clk_2_E_in ( p3202 ) , .clk_2_W_in ( p1135 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5342 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5343 ) , .clk_3_W_in ( p1478 ) ,
+ .clk_3_E_in ( p2465 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5344 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5345 ) ) ;
+cbx_1__1_ cbx_9__1_ ( .chanx_left_in ( sb_1__1__77_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__88_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__88_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__88_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__88_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) ,
+ .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p1871 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5346 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[332] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5347 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5348 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[170] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[171] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p2304 ) ,
+ .prog_clk_2_W_in ( p1358 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5349 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5350 ) ,
+ .prog_clk_3_W_in ( p1609 ) , .prog_clk_3_E_in ( p2265 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5351 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5352 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5353 ) ,
+ .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) ,
+ .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p2391 ) ,
+ .clk_2_W_in ( p698 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5354 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5355 ) , .clk_3_W_in ( p1609 ) ,
+ .clk_3_E_in ( p2199 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5356 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5357 ) ) ;
+cbx_1__1_ cbx_9__2_ ( .chanx_left_in ( sb_1__1__78_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__89_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__89_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__89_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__89_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) ,
+ .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1714 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5358 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[335] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5359 ) ,
+ .prog_clk_1_W_in ( p1672 ) , .prog_clk_1_E_in ( p1382 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5360 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5361 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5362 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[69] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5363 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1766 ) ,
+ .prog_clk_3_E_in ( p1174 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5364 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5365 ) , .clk_1_W_in ( p1672 ) ,
+ .clk_1_E_in ( p181 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5366 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5367 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5368 ) ,
+ .clk_2_W_in ( clk_2_wires[69] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5369 ) ,
+ .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1766 ) ,
+ .clk_3_E_in ( p310 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5370 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5371 ) ) ;
+cbx_1__1_ cbx_9__3_ ( .chanx_left_in ( sb_1__1__79_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__90_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__90_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__90_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__90_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) ,
+ .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1576 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5372 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[338] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5373 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5374 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[177] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[178] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p2747 ) ,
+ .prog_clk_2_W_in ( p806 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5375 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5376 ) ,
+ .prog_clk_3_W_in ( p2558 ) , .prog_clk_3_E_in ( p3062 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5377 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5378 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5379 ) ,
+ .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) ,
+ .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p3115 ) ,
+ .clk_2_W_in ( p2483 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5380 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5381 ) , .clk_3_W_in ( p2558 ) ,
+ .clk_3_E_in ( p2701 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5382 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5383 ) ) ;
+cbx_1__1_ cbx_9__4_ ( .chanx_left_in ( sb_1__1__80_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__91_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__91_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__91_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__91_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) ,
+ .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1872 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5384 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[341] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5385 ) ,
+ .prog_clk_1_W_in ( p1312 ) , .prog_clk_1_E_in ( p1102 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5386 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5387 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5388 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[78] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5389 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p1107 ) ,
+ .prog_clk_3_E_in ( p1058 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5390 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5391 ) , .clk_1_W_in ( p1312 ) ,
+ .clk_1_E_in ( p667 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5392 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5393 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5394 ) ,
+ .clk_2_W_in ( clk_2_wires[78] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5395 ) ,
+ .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p1510 ) ,
+ .clk_3_E_in ( p2239 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5396 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5397 ) ) ;
+cbx_1__1_ cbx_9__5_ ( .chanx_left_in ( sb_1__1__81_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__92_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__92_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__92_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__92_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) ,
+ .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1739 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5398 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[344] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5399 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5400 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[184] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[185] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p2609 ) ,
+ .prog_clk_2_W_in ( p681 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5401 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5402 ) ,
+ .prog_clk_3_W_in ( p1832 ) , .prog_clk_3_E_in ( p2979 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5403 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5404 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5405 ) ,
+ .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) ,
+ .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p3039 ) ,
+ .clk_2_W_in ( p1266 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5406 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5407 ) , .clk_3_W_in ( p1832 ) ,
+ .clk_3_E_in ( p2493 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5408 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5409 ) ) ;
+cbx_1__1_ cbx_9__6_ ( .chanx_left_in ( sb_1__1__82_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__93_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__93_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__93_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__93_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) ,
+ .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1734 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5410 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[347] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5411 ) ,
+ .prog_clk_1_W_in ( p1411 ) , .prog_clk_1_E_in ( p563 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5412 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5413 ) ,
+ .prog_clk_2_E_in ( p1623 ) , .prog_clk_2_W_in ( p690 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5414 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5415 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[44] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5416 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[45] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5417 ) , .clk_1_W_in ( p1411 ) ,
+ .clk_1_E_in ( p1360 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5418 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5419 ) , .clk_2_E_in ( p1472 ) ,
+ .clk_2_W_in ( p514 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5420 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5421 ) ,
+ .clk_3_W_in ( clk_3_wires[44] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5422 ) ,
+ .clk_3_E_out ( clk_3_wires[45] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5423 ) ) ;
+cbx_1__1_ cbx_9__7_ ( .chanx_left_in ( sb_1__1__83_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__94_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__94_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__94_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__94_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) ,
+ .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1843 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5424 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[350] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5425 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5426 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[191] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[192] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p2109 ) ,
+ .prog_clk_2_W_in ( p546 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5427 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5428 ) ,
+ .prog_clk_3_W_in ( p2082 ) , .prog_clk_3_E_in ( p3157 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5429 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5430 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5431 ) ,
+ .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) ,
+ .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p3215 ) ,
+ .clk_2_W_in ( p1912 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5432 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5433 ) , .clk_3_W_in ( p2082 ) ,
+ .clk_3_E_in ( p1960 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5434 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5435 ) ) ;
+cbx_1__1_ cbx_9__8_ ( .chanx_left_in ( sb_1__1__84_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__95_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__95_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__95_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__95_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) ,
+ .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p2425 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5436 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[353] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5437 ) ,
+ .prog_clk_1_W_in ( p674 ) , .prog_clk_1_E_in ( p1260 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5438 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5439 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5440 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[91] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5441 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1600 ) ,
+ .prog_clk_3_E_in ( p350 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5442 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5443 ) , .clk_1_W_in ( p674 ) ,
+ .clk_1_E_in ( p2192 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5444 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5445 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5446 ) ,
+ .clk_2_W_in ( clk_2_wires[91] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5447 ) ,
+ .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1600 ) ,
+ .clk_3_E_in ( p1905 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5448 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5449 ) ) ;
+cbx_1__1_ cbx_9__9_ ( .chanx_left_in ( sb_1__1__85_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__96_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__96_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__96_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__96_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) ,
+ .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1884 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5450 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[356] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5451 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5452 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[198] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[199] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p1839 ) ,
+ .prog_clk_2_W_in ( p815 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5453 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5454 ) ,
+ .prog_clk_3_W_in ( p2698 ) , .prog_clk_3_E_in ( p2266 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5455 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5456 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5457 ) ,
+ .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) ,
+ .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p2300 ) ,
+ .clk_2_W_in ( p2671 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5458 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5459 ) , .clk_3_W_in ( p2698 ) ,
+ .clk_3_E_in ( p1040 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5460 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5461 ) ) ;
+cbx_1__1_ cbx_9__10_ ( .chanx_left_in ( sb_1__1__86_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__97_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__97_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__97_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__97_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) ,
+ .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p2362 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5462 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[359] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5463 ) ,
+ .prog_clk_1_W_in ( p1511 ) , .prog_clk_1_E_in ( p1476 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5464 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5465 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5466 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[104] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5467 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p1726 ) ,
+ .prog_clk_3_E_in ( p1322 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5468 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5469 ) , .clk_1_W_in ( p1511 ) ,
+ .clk_1_E_in ( p2242 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5470 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5471 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5472 ) ,
+ .clk_2_W_in ( clk_2_wires[104] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5473 ) ,
+ .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p1726 ) ,
+ .clk_3_E_in ( p525 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5474 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5475 ) ) ;
+cbx_1__1_ cbx_9__11_ ( .chanx_left_in ( sb_1__1__87_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__98_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__98_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__98_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__98_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) ,
+ .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1450 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5476 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[362] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5477 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5478 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[205] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[206] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p1727 ) ,
+ .prog_clk_2_W_in ( p1188 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5479 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5480 ) ,
+ .prog_clk_3_W_in ( p2526 ) , .prog_clk_3_E_in ( p3241 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5481 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5482 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5483 ) ,
+ .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) ,
+ .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p3285 ) ,
+ .clk_2_W_in ( p2670 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5484 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5485 ) , .clk_3_W_in ( p2745 ) ,
+ .clk_3_E_in ( p620 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5486 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5487 ) ) ;
+cbx_1__1_ cbx_10__1_ ( .chanx_left_in ( sb_1__1__88_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__99_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__99_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__99_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__99_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1731 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5488 ) ,
+ .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[99] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[370] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5489 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[169] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5490 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[173] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p2364 ) ,
+ .prog_clk_2_W_in ( p2396 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5491 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5492 ) ,
+ .prog_clk_3_W_in ( p1807 ) , .prog_clk_3_E_in ( p2076 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5493 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5494 ) ,
+ .clk_1_W_in ( clk_1_wires[169] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5495 ) ,
+ .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) ,
+ .clk_2_E_in ( p2042 ) , .clk_2_W_in ( p2259 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5496 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5497 ) , .clk_3_W_in ( p1807 ) ,
+ .clk_3_E_in ( p2295 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5498 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5499 ) ) ;
+cbx_1__1_ cbx_10__2_ ( .chanx_left_in ( sb_1__1__89_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__100_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__100_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__100_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__100_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p2551 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5500 ) ,
+ .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[100] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[373] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5501 ) ,
+ .prog_clk_1_W_in ( p1454 ) , .prog_clk_1_E_in ( p1689 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5502 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5503 ) ,
+ .prog_clk_2_E_in ( p2783 ) , .prog_clk_2_W_in ( p1851 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5504 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5505 ) ,
+ .prog_clk_3_W_in ( p1474 ) , .prog_clk_3_E_in ( p3096 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5506 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5507 ) , .clk_1_W_in ( p1454 ) ,
+ .clk_1_E_in ( p959 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5508 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5509 ) , .clk_2_E_in ( p3097 ) ,
+ .clk_2_W_in ( p1395 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5510 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5511 ) , .clk_3_W_in ( p1474 ) ,
+ .clk_3_E_in ( p2693 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5512 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5513 ) ) ;
+cbx_1__1_ cbx_10__3_ ( .chanx_left_in ( sb_1__1__90_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__101_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__101_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__101_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__101_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p2310 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5514 ) ,
+ .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[101] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[376] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5515 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[176] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5516 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[180] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2387 ) ,
+ .prog_clk_2_W_in ( p1471 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5517 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5518 ) ,
+ .prog_clk_3_W_in ( p2110 ) , .prog_clk_3_E_in ( p2984 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5519 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5520 ) ,
+ .clk_1_W_in ( clk_1_wires[176] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5521 ) ,
+ .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) ,
+ .clk_2_E_in ( p3020 ) , .clk_2_W_in ( p1972 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5522 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5523 ) , .clk_3_W_in ( p2110 ) ,
+ .clk_3_E_in ( p2249 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5524 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5525 ) ) ;
+cbx_1__1_ cbx_10__4_ ( .chanx_left_in ( sb_1__1__91_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__102_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__102_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__102_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__102_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p1738 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5526 ) ,
+ .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[102] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[379] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5527 ) ,
+ .prog_clk_1_W_in ( p1651 ) , .prog_clk_1_E_in ( p1719 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5528 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5529 ) ,
+ .prog_clk_2_E_in ( p2623 ) , .prog_clk_2_W_in ( p1278 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5530 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5531 ) ,
+ .prog_clk_3_W_in ( p1794 ) , .prog_clk_3_E_in ( p1715 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5532 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5533 ) , .clk_1_W_in ( p1651 ) ,
+ .clk_1_E_in ( p764 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5534 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5535 ) , .clk_2_E_in ( p1738 ) ,
+ .clk_2_W_in ( p1232 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5536 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5537 ) , .clk_3_W_in ( p1794 ) ,
+ .clk_3_E_in ( p2498 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5538 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5539 ) ) ;
+cbx_1__1_ cbx_10__5_ ( .chanx_left_in ( sb_1__1__92_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__103_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__103_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__103_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__103_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p1716 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5540 ) ,
+ .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[103] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[382] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5541 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[183] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5542 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[187] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p2165 ) ,
+ .prog_clk_2_W_in ( p1002 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5543 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5544 ) ,
+ .prog_clk_3_W_in ( p2710 ) , .prog_clk_3_E_in ( p2169 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5545 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5546 ) ,
+ .clk_1_W_in ( clk_1_wires[183] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5547 ) ,
+ .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) ,
+ .clk_2_E_in ( p1716 ) , .clk_2_W_in ( p2694 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5548 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5549 ) , .clk_3_W_in ( p2752 ) ,
+ .clk_3_E_in ( p1947 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5550 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5551 ) ) ;
+cbx_1__1_ cbx_10__6_ ( .chanx_left_in ( sb_1__1__93_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__104_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__104_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__104_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__104_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1505 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5552 ) ,
+ .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[104] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[385] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5553 ) ,
+ .prog_clk_1_W_in ( p1578 ) , .prog_clk_1_E_in ( p1165 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5554 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5555 ) ,
+ .prog_clk_2_E_in ( p2531 ) , .prog_clk_2_W_in ( p1659 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5556 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5557 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[48] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5558 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[49] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5559 ) , .clk_1_W_in ( p1578 ) ,
+ .clk_1_E_in ( p1822 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5560 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5561 ) , .clk_2_E_in ( p1505 ) ,
+ .clk_2_W_in ( p1243 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5562 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5563 ) ,
+ .clk_3_W_in ( clk_3_wires[48] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5564 ) ,
+ .clk_3_E_out ( clk_3_wires[49] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5565 ) ) ;
+cbx_1__1_ cbx_10__7_ ( .chanx_left_in ( sb_1__1__94_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__105_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__105_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__105_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__105_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1729 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5566 ) ,
+ .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[105] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[388] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5567 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[190] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5568 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[194] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p1223 ) ,
+ .prog_clk_2_W_in ( p1975 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5569 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5570 ) ,
+ .prog_clk_3_W_in ( p2378 ) , .prog_clk_3_E_in ( p3094 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5571 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5572 ) ,
+ .clk_1_W_in ( clk_1_wires[190] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5573 ) ,
+ .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) ,
+ .clk_2_E_in ( p3112 ) , .clk_2_W_in ( p2262 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5574 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5575 ) , .clk_3_W_in ( p2378 ) ,
+ .clk_3_E_in ( p1614 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5576 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5577 ) ) ;
+cbx_1__1_ cbx_10__8_ ( .chanx_left_in ( sb_1__1__95_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__106_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__106_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__106_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__106_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p2383 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5578 ) ,
+ .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[106] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[391] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5579 ) ,
+ .prog_clk_1_W_in ( p1370 ) , .prog_clk_1_E_in ( p520 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5580 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5581 ) ,
+ .prog_clk_2_E_in ( p2622 ) , .prog_clk_2_W_in ( p1849 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5582 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5583 ) ,
+ .prog_clk_3_W_in ( p940 ) , .prog_clk_3_E_in ( p2303 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5584 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p1370 ) ,
+ .clk_1_E_in ( p1519 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2383 ) ,
+ .clk_2_W_in ( p1467 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p940 ) ,
+ .clk_3_E_in ( p2461 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) ) ;
+cbx_1__1_ cbx_10__9_ ( .chanx_left_in ( sb_1__1__96_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__107_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__107_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__107_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__107_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p1573 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5592 ) ,
+ .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[107] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[394] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5593 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[197] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5594 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[201] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p1863 ) ,
+ .prog_clk_2_W_in ( p662 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5595 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5596 ) ,
+ .prog_clk_3_W_in ( p1990 ) , .prog_clk_3_E_in ( p2520 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5597 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5598 ) ,
+ .clk_1_W_in ( clk_1_wires[197] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5599 ) ,
+ .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) ,
+ .clk_2_E_in ( p2503 ) , .clk_2_W_in ( p1970 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5600 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5601 ) , .clk_3_W_in ( p1990 ) ,
+ .clk_3_E_in ( p756 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5602 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5603 ) ) ;
+cbx_1__1_ cbx_10__10_ ( .chanx_left_in ( sb_1__1__97_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__108_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__108_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__108_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__108_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1995 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5604 ) ,
+ .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[108] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[397] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5605 ) ,
+ .prog_clk_1_W_in ( p1371 ) , .prog_clk_1_E_in ( p946 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5606 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5607 ) ,
+ .prog_clk_2_E_in ( p1158 ) , .prog_clk_2_W_in ( p1502 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5608 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5609 ) ,
+ .prog_clk_3_W_in ( p1710 ) , .prog_clk_3_E_in ( p2024 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5610 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5611 ) , .clk_1_W_in ( p1371 ) ,
+ .clk_1_E_in ( p946 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5612 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5613 ) , .clk_2_E_in ( p1995 ) ,
+ .clk_2_W_in ( p1502 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5614 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_3_W_in ( p1710 ) ,
+ .clk_3_E_in ( p2024 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5616 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5617 ) ) ;
+cbx_1__1_ cbx_10__11_ ( .chanx_left_in ( sb_1__1__98_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__109_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__109_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__109_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__109_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p2514 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5618 ) ,
+ .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[109] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[400] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5619 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[204] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5620 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[208] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p2073 ) ,
+ .prog_clk_2_W_in ( p2128 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5621 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5622 ) ,
+ .prog_clk_3_W_in ( p2414 ) , .prog_clk_3_E_in ( p2514 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5623 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5624 ) ,
+ .clk_1_W_in ( clk_1_wires[204] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5625 ) ,
+ .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) ,
+ .clk_2_E_in ( p2514 ) , .clk_2_W_in ( p2283 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5626 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5627 ) , .clk_3_W_in ( p2283 ) ,
+ .clk_3_E_in ( p2549 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5628 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5629 ) ) ;
+cbx_1__1_ cbx_11__1_ ( .chanx_left_in ( sb_1__1__99_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__110_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__110_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__110_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__110_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) ,
+ .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1354 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5630 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[408] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5631 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5632 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[212] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[213] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p2323 ) ,
+ .prog_clk_2_W_in ( p993 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5633 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5634 ) ,
+ .prog_clk_3_W_in ( p2307 ) , .prog_clk_3_E_in ( p2985 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5635 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5636 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5637 ) ,
+ .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) ,
+ .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p3052 ) ,
+ .clk_2_W_in ( p2270 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5638 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5639 ) , .clk_3_W_in ( p2307 ) ,
+ .clk_3_E_in ( p2336 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5640 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5641 ) ) ;
+cbx_1__1_ cbx_11__2_ ( .chanx_left_in ( sb_1__1__100_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__111_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__111_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__111_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__111_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) ,
+ .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p1721 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5642 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[411] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5643 ) ,
+ .prog_clk_1_W_in ( p1525 ) , .prog_clk_1_E_in ( p1458 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5644 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5645 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5646 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[114] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5647 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p2554 ) ,
+ .prog_clk_3_E_in ( p1542 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5648 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_1_W_in ( p1525 ) ,
+ .clk_1_E_in ( p904 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5650 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5651 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5652 ) ,
+ .clk_2_W_in ( clk_2_wires[114] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5653 ) ,
+ .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p2554 ) ,
+ .clk_3_E_in ( p1971 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5654 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5655 ) ) ;
+cbx_1__1_ cbx_11__3_ ( .chanx_left_in ( sb_1__1__101_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__112_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__112_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__112_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__112_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) ,
+ .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p1621 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5656 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[414] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5657 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5658 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[219] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[220] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2937 ) ,
+ .prog_clk_2_W_in ( p1071 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5659 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5660 ) ,
+ .prog_clk_3_W_in ( p1439 ) , .prog_clk_3_E_in ( p2285 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5661 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5662 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5663 ) ,
+ .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) ,
+ .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2380 ) ,
+ .clk_2_W_in ( p1631 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5664 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5665 ) , .clk_3_W_in ( p1439 ) ,
+ .clk_3_E_in ( p2853 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5666 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5667 ) ) ;
+cbx_1__1_ cbx_11__4_ ( .chanx_left_in ( sb_1__1__102_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__113_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__113_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__113_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__113_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) ,
+ .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1679 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5668 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[417] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5669 ) ,
+ .prog_clk_1_W_in ( p1378 ) , .prog_clk_1_E_in ( p827 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5670 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5671 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5672 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[119] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5673 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1393 ) ,
+ .prog_clk_3_E_in ( p1504 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5674 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p1378 ) ,
+ .clk_1_E_in ( p1561 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5678 ) ,
+ .clk_2_W_in ( clk_2_wires[119] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5679 ) ,
+ .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1393 ) ,
+ .clk_3_E_in ( p319 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) ) ;
+cbx_1__1_ cbx_11__5_ ( .chanx_left_in ( sb_1__1__103_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__114_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__114_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__114_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__114_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) ,
+ .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p1834 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5682 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[420] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5683 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5684 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[226] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[227] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p1421 ) ,
+ .prog_clk_2_W_in ( p1375 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5685 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5686 ) ,
+ .prog_clk_3_W_in ( p2086 ) , .prog_clk_3_E_in ( p2003 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5687 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5688 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5689 ) ,
+ .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) ,
+ .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p2083 ) ,
+ .clk_2_W_in ( p1968 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5690 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5691 ) , .clk_3_W_in ( p2086 ) ,
+ .clk_3_E_in ( p1311 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5692 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5693 ) ) ;
+cbx_1__1_ cbx_11__6_ ( .chanx_left_in ( sb_1__1__104_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__115_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__115_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__115_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__115_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) ,
+ .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p2056 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5694 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[423] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5695 ) ,
+ .prog_clk_1_W_in ( p1400 ) , .prog_clk_1_E_in ( p156 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5696 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5697 ) ,
+ .prog_clk_2_E_in ( p2691 ) , .prog_clk_2_W_in ( p1508 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5698 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5699 ) ,
+ .prog_clk_3_W_in ( p1806 ) , .prog_clk_3_E_in ( p2852 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5700 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5701 ) , .clk_1_W_in ( p1400 ) ,
+ .clk_1_E_in ( p1976 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5702 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5703 ) , .clk_2_E_in ( p2863 ) ,
+ .clk_2_W_in ( p699 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5704 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_3_W_in ( p1340 ) ,
+ .clk_3_E_in ( p2679 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5706 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5707 ) ) ;
+cbx_1__1_ cbx_11__7_ ( .chanx_left_in ( sb_1__1__105_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__116_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__116_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__116_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__116_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) ,
+ .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1658 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5708 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[426] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5709 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5710 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[233] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[234] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p2602 ) ,
+ .prog_clk_2_W_in ( p1517 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5711 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5712 ) ,
+ .prog_clk_3_W_in ( p1599 ) , .prog_clk_3_E_in ( p2857 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5713 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5714 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5715 ) ,
+ .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) ,
+ .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p2850 ) ,
+ .clk_2_W_in ( p1143 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5716 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5717 ) , .clk_3_W_in ( p1599 ) ,
+ .clk_3_E_in ( p2517 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5718 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5719 ) ) ;
+cbx_1__1_ cbx_11__8_ ( .chanx_left_in ( sb_1__1__106_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__117_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__117_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__117_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__117_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) ,
+ .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p2419 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5720 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[429] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5721 ) ,
+ .prog_clk_1_W_in ( p1453 ) , .prog_clk_1_E_in ( p849 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5722 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5723 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5724 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[126] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5725 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1180 ) ,
+ .prog_clk_3_E_in ( p1527 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5726 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5727 ) , .clk_1_W_in ( p1453 ) ,
+ .clk_1_E_in ( p2248 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5728 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5729 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5730 ) ,
+ .clk_2_W_in ( clk_2_wires[126] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5731 ) ,
+ .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1180 ) ,
+ .clk_3_E_in ( p500 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5732 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5733 ) ) ;
+cbx_1__1_ cbx_11__9_ ( .chanx_left_in ( sb_1__1__107_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__118_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__118_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__118_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__118_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) ,
+ .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p2007 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5734 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[432] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5735 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5736 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[240] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[241] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p2351 ) ,
+ .prog_clk_2_W_in ( p1587 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5737 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) ,
+ .prog_clk_3_W_in ( p2077 ) , .prog_clk_3_E_in ( p1779 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5741 ) ,
+ .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) ,
+ .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p1760 ) ,
+ .clk_2_W_in ( p2842 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5742 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5743 ) , .clk_3_W_in ( p2864 ) ,
+ .clk_3_E_in ( p2184 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5744 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5745 ) ) ;
+cbx_1__1_ cbx_11__10_ ( .chanx_left_in ( sb_1__1__108_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__119_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__119_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__119_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__119_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) ,
+ .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p2335 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5746 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[435] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5747 ) ,
+ .prog_clk_1_W_in ( p1605 ) , .prog_clk_1_E_in ( p1529 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5748 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5749 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5750 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[133] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5751 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1881 ) ,
+ .prog_clk_3_E_in ( p556 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5752 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5753 ) , .clk_1_W_in ( p1420 ) ,
+ .clk_1_E_in ( p2260 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5754 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5755 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5756 ) ,
+ .clk_2_W_in ( clk_2_wires[133] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5757 ) ,
+ .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1881 ) ,
+ .clk_3_E_in ( p2492 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5758 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5759 ) ) ;
+cbx_1__1_ cbx_11__11_ ( .chanx_left_in ( sb_1__1__109_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__120_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__120_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__120_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__120_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) ,
+ .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1642 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5760 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[438] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5761 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5762 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[247] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[248] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p1799 ) ,
+ .prog_clk_2_W_in ( p1387 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5763 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5764 ) ,
+ .prog_clk_3_W_in ( p2392 ) , .prog_clk_3_E_in ( p3189 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5765 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5766 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5767 ) ,
+ .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) ,
+ .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p3233 ) ,
+ .clk_2_W_in ( p2269 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5768 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5769 ) , .clk_3_W_in ( p2392 ) ,
+ .clk_3_E_in ( p866 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5770 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5771 ) ) ;
+cbx_1__1_ cbx_12__1_ ( .chanx_left_in ( sb_1__1__110_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__121_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__121_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p2162 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5772 ) ,
+ .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[121] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[446] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5773 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[211] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5774 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[215] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2314 ) ,
+ .prog_clk_2_W_in ( p269 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5775 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5776 ) ,
+ .prog_clk_3_W_in ( p2023 ) , .prog_clk_3_E_in ( p2032 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5777 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5778 ) ,
+ .clk_1_W_in ( clk_1_wires[211] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5779 ) ,
+ .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) ,
+ .clk_2_E_in ( p2162 ) , .clk_2_W_in ( p2981 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5780 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5781 ) , .clk_3_W_in ( p3051 ) ,
+ .clk_3_E_in ( p2268 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5782 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) ) ;
+cbx_1__1_ cbx_12__2_ ( .chanx_left_in ( sb_1__1__111_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__1_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__122_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__122_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1829 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5784 ) ,
+ .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[122] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[449] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5785 ) ,
+ .prog_clk_1_W_in ( p1688 ) , .prog_clk_1_E_in ( p733 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5786 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5787 ) ,
+ .prog_clk_2_E_in ( p2862 ) , .prog_clk_2_W_in ( p1344 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5788 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5789 ) ,
+ .prog_clk_3_W_in ( p2599 ) , .prog_clk_3_E_in ( p2695 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5790 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5791 ) , .clk_1_W_in ( p1688 ) ,
+ .clk_1_E_in ( p695 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5792 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5793 ) , .clk_2_E_in ( p2712 ) ,
+ .clk_2_W_in ( p2428 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5794 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5795 ) , .clk_3_W_in ( p2599 ) ,
+ .clk_3_E_in ( p2810 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5796 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5797 ) ) ;
+cbx_1__1_ cbx_12__3_ ( .chanx_left_in ( sb_1__1__112_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__2_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__123_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__123_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1810 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5798 ) ,
+ .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[123] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[452] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5799 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[218] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5800 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[222] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p2555 ) ,
+ .prog_clk_2_W_in ( p1540 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5801 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) ,
+ .prog_clk_3_W_in ( p2087 ) , .prog_clk_3_E_in ( p1908 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) ,
+ .clk_1_W_in ( clk_1_wires[218] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5805 ) ,
+ .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) ,
+ .clk_2_E_in ( p2018 ) , .clk_2_W_in ( p2496 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5806 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5807 ) , .clk_3_W_in ( p2581 ) ,
+ .clk_3_E_in ( p2436 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5808 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5809 ) ) ;
+cbx_1__1_ cbx_12__4_ ( .chanx_left_in ( sb_1__1__113_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__3_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__124_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__124_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1878 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5810 ) ,
+ .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[124] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[455] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5811 ) ,
+ .prog_clk_1_W_in ( p1570 ) , .prog_clk_1_E_in ( p1622 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5812 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5813 ) ,
+ .prog_clk_2_E_in ( p2744 ) , .prog_clk_2_W_in ( p48 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5814 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5815 ) ,
+ .prog_clk_3_W_in ( p1348 ) , .prog_clk_3_E_in ( p2699 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5816 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_1_W_in ( p1570 ) ,
+ .clk_1_E_in ( p398 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5818 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_2_E_in ( p2790 ) ,
+ .clk_2_W_in ( p1359 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5820 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5821 ) , .clk_3_W_in ( p1348 ) ,
+ .clk_3_E_in ( p2639 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5822 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5823 ) ) ;
+cbx_1__1_ cbx_12__5_ ( .chanx_left_in ( sb_1__1__114_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__4_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__125_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__125_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p2084 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5824 ) ,
+ .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[125] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[458] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5825 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[225] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5826 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[229] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p1548 ) ,
+ .prog_clk_2_W_in ( p670 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5827 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5828 ) ,
+ .prog_clk_3_W_in ( p1544 ) , .prog_clk_3_E_in ( p2463 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5829 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5830 ) ,
+ .clk_1_W_in ( clk_1_wires[225] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5831 ) ,
+ .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) ,
+ .clk_2_E_in ( p2552 ) , .clk_2_W_in ( p1482 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5832 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5833 ) , .clk_3_W_in ( p1628 ) ,
+ .clk_3_E_in ( p1550 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5834 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5835 ) ) ;
+cbx_1__1_ cbx_12__6_ ( .chanx_left_in ( sb_1__1__115_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__5_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__126_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__126_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p1754 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5836 ) ,
+ .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[126] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[461] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5837 ) ,
+ .prog_clk_1_W_in ( p1538 ) , .prog_clk_1_E_in ( p976 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5838 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5839 ) ,
+ .prog_clk_2_E_in ( p2343 ) , .prog_clk_2_W_in ( p1070 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5840 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5841 ) ,
+ .prog_clk_3_W_in ( p2379 ) , .prog_clk_3_E_in ( p2074 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5842 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5843 ) , .clk_1_W_in ( p1538 ) ,
+ .clk_1_E_in ( p580 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5844 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5845 ) , .clk_2_E_in ( p2027 ) ,
+ .clk_2_W_in ( p2480 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5846 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_3_W_in ( p2553 ) ,
+ .clk_3_E_in ( p2243 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5848 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5849 ) ) ;
+cbx_1__1_ cbx_12__7_ ( .chanx_left_in ( sb_1__1__116_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__6_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__127_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__127_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p1857 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5850 ) ,
+ .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[127] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[464] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5851 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[232] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5852 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[236] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2327 ) ,
+ .prog_clk_2_W_in ( p1449 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5853 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5854 ) ,
+ .prog_clk_3_W_in ( p1593 ) , .prog_clk_3_E_in ( p1595 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5855 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5856 ) ,
+ .clk_1_W_in ( clk_1_wires[232] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5857 ) ,
+ .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) ,
+ .clk_2_E_in ( p1857 ) , .clk_2_W_in ( p2982 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5858 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5859 ) , .clk_3_W_in ( p3025 ) ,
+ .clk_3_E_in ( p2213 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5860 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5861 ) ) ;
+cbx_1__1_ cbx_12__8_ ( .chanx_left_in ( sb_1__1__117_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__7_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__128_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__128_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p2033 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5862 ) ,
+ .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[128] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[467] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5863 ) ,
+ .prog_clk_1_W_in ( p1572 ) , .prog_clk_1_E_in ( p420 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5864 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5865 ) ,
+ .prog_clk_2_E_in ( p2413 ) , .prog_clk_2_W_in ( p1153 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5866 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5867 ) ,
+ .prog_clk_3_W_in ( p2422 ) , .prog_clk_3_E_in ( p2065 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5868 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5869 ) , .clk_1_W_in ( p1572 ) ,
+ .clk_1_E_in ( p1374 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5870 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5871 ) , .clk_2_E_in ( p2054 ) ,
+ .clk_2_W_in ( p2236 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5872 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5873 ) , .clk_3_W_in ( p2422 ) ,
+ .clk_3_E_in ( p2235 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5874 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5875 ) ) ;
+cbx_1__1_ cbx_12__9_ ( .chanx_left_in ( sb_1__1__118_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__8_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__129_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__129_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1841 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5876 ) ,
+ .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[129] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[470] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5877 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[239] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5878 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[243] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p1655 ) ,
+ .prog_clk_2_W_in ( p1248 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5879 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5880 ) ,
+ .prog_clk_3_W_in ( p2297 ) , .prog_clk_3_E_in ( p2215 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5881 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5882 ) ,
+ .clk_1_W_in ( clk_1_wires[239] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5883 ) ,
+ .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) ,
+ .clk_2_E_in ( p2373 ) , .clk_2_W_in ( p2252 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5884 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5885 ) , .clk_3_W_in ( p2297 ) ,
+ .clk_3_E_in ( p1437 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5886 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5887 ) ) ;
+cbx_1__1_ cbx_12__10_ ( .chanx_left_in ( sb_1__1__119_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__9_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__130_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__130_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p2338 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5888 ) ,
+ .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[130] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[473] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5889 ) ,
+ .prog_clk_1_W_in ( p1585 ) , .prog_clk_1_E_in ( p1282 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5890 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5891 ) ,
+ .prog_clk_2_E_in ( p2702 ) , .prog_clk_2_W_in ( p450 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5892 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5893 ) ,
+ .prog_clk_3_W_in ( p1798 ) , .prog_clk_3_E_in ( p2280 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5894 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , .clk_1_W_in ( p1585 ) ,
+ .clk_1_E_in ( p344 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5896 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5897 ) , .clk_2_E_in ( p2333 ) ,
+ .clk_2_W_in ( p1337 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5898 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , .clk_3_W_in ( p1798 ) ,
+ .clk_3_E_in ( p2673 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5900 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5901 ) ) ;
+cbx_1__1_ cbx_12__11_ ( .chanx_left_in ( sb_1__1__120_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__10_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__131_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__131_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p1848 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5902 ) ,
+ .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[131] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[476] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5903 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[246] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5904 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[250] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p1468 ) ,
+ .prog_clk_2_W_in ( p11 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5905 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5906 ) ,
+ .prog_clk_3_W_in ( p2312 ) , .prog_clk_3_E_in ( p1492 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5907 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5908 ) ,
+ .clk_1_W_in ( clk_1_wires[246] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5909 ) ,
+ .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) ,
+ .clk_2_E_in ( p1673 ) , .clk_2_W_in ( p2254 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5910 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5911 ) , .clk_3_W_in ( p2312 ) ,
+ .clk_3_E_in ( p523 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5912 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5913 ) ) ;
+cbx_1__2_ cbx_1__12_ ( .chanx_left_in ( sb_0__12__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__0_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) ,
+ .SC_IN_BOT ( p1368 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5914 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[59] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[62] ) ) ;
+cbx_1__2_ cbx_2__12_ ( .chanx_left_in ( sb_1__12__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__1_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1698 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5915 ) ,
+ .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[99] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5916 ) ) ;
+cbx_1__2_ cbx_3__12_ ( .chanx_left_in ( sb_1__12__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__2_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) ,
+ .SC_IN_BOT ( p1422 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5917 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[137] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5918 ) ) ;
+cbx_1__2_ cbx_4__12_ ( .chanx_left_in ( sb_1__12__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__3_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p2029 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5919 ) ,
+ .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[175] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5920 ) ) ;
+cbx_1__2_ cbx_5__12_ ( .chanx_left_in ( sb_1__12__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__4_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) ,
+ .SC_IN_BOT ( p1788 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5921 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[213] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5922 ) ) ;
+cbx_1__2_ cbx_6__12_ ( .chanx_left_in ( sb_1__12__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__5_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1736 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5923 ) ,
+ .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[251] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5924 ) ) ;
+cbx_1__2_ cbx_7__12_ ( .chanx_left_in ( sb_1__12__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__6_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) ,
+ .SC_IN_BOT ( p1652 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5925 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[289] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5926 ) ) ;
+cbx_1__2_ cbx_8__12_ ( .chanx_left_in ( sb_1__12__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__7_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1720 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5927 ) ,
+ .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[327] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5928 ) ) ;
+cbx_1__2_ cbx_9__12_ ( .chanx_left_in ( sb_1__12__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__8_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) ,
+ .SC_IN_BOT ( p1523 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5929 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[365] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5930 ) ) ;
+cbx_1__2_ cbx_10__12_ ( .chanx_left_in ( sb_1__12__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__9_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1787 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5931 ) ,
+ .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[403] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5932 ) ) ;
+cbx_1__2_ cbx_11__12_ ( .chanx_left_in ( sb_1__12__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__10_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) ,
+ .SC_IN_BOT ( p1533 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5933 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[441] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5934 ) ) ;
+cbx_1__2_ cbx_12__12_ ( .chanx_left_in ( sb_1__12__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__12__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__12__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__11_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p2161 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5935 ) ,
+ .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[479] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5936 ) ) ;
+cby_0__1_ cby_0__1_ ( .chany_bottom_in ( sb_0__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__0_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__0_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__0_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[3] ) ) ;
+cby_0__1_ cby_0__2_ ( .chany_bottom_in ( sb_0__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__1_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__1_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__1_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[9] ) ) ;
+cby_0__1_ cby_0__3_ ( .chany_bottom_in ( sb_0__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__2_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__2_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__2_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[14] ) ) ;
+cby_0__1_ cby_0__4_ ( .chany_bottom_in ( sb_0__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__3_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__3_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__3_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[19] ) ) ;
+cby_0__1_ cby_0__5_ ( .chany_bottom_in ( sb_0__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__4_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__4_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__4_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[24] ) ) ;
+cby_0__1_ cby_0__6_ ( .chany_bottom_in ( sb_0__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__5_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__5_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__5_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[29] ) ) ;
+cby_0__1_ cby_0__7_ ( .chany_bottom_in ( sb_0__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__6_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__6_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__6_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[34] ) ) ;
+cby_0__1_ cby_0__8_ ( .chany_bottom_in ( sb_0__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__7_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__7_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__7_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[39] ) ) ;
+cby_0__1_ cby_0__9_ ( .chany_bottom_in ( sb_0__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__8_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__8_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__8_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[44] ) ) ;
+cby_0__1_ cby_0__10_ ( .chany_bottom_in ( sb_0__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__9_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__9_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__9_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[49] ) ) ;
+cby_0__1_ cby_0__11_ ( .chany_bottom_in ( sb_0__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__10_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__10_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__10_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[54] ) ) ;
+cby_0__1_ cby_0__12_ ( .chany_bottom_in ( sb_0__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_0__12__0_chany_bottom_out ) ,
+ .ccff_head ( sb_0__12__0_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__11_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[61] ) ) ;
+cby_1__1_ cby_1__1_ ( .chany_bottom_in ( sb_1__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_0_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__0_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__0_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5937 ) ,
+ .Test_en_E_in ( Test_enWires[26] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5938 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5939 ) ,
+ .Test_en_W_out ( Test_enWires[24] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5940 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[1] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[2] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5941 ) ,
+ .prog_clk_2_N_in ( p3425 ) , .prog_clk_2_S_in ( p2824 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5942 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5943 ) ,
+ .prog_clk_3_S_in ( p2930 ) , .prog_clk_3_N_in ( p3401 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5944 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_2_N_in ( p3200 ) ,
+ .clk_2_S_in ( p2187 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5946 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5947 ) , .clk_3_S_in ( p2277 ) ,
+ .clk_3_N_in ( p766 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5948 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5949 ) ) ;
+cby_1__1_ cby_1__2_ ( .chany_bottom_in ( sb_1__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_1_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__1_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__1_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5950 ) ,
+ .Test_en_E_in ( Test_enWires[48] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5951 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5952 ) ,
+ .Test_en_W_out ( Test_enWires[46] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5953 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[7] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[8] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5954 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[3] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5955 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[4] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5956 ) ,
+ .prog_clk_3_S_in ( p1604 ) , .prog_clk_3_N_in ( p480 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5957 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5958 ) ,
+ .clk_2_N_in ( clk_2_wires[3] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5959 ) ,
+ .clk_2_S_out ( clk_2_wires[4] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_3_S_in ( p2037 ) ,
+ .clk_3_N_in ( p1261 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5961 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5962 ) ) ;
+cby_1__1_ cby_1__3_ ( .chany_bottom_in ( sb_1__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_2_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__2_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__2_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5963 ) ,
+ .Test_en_E_in ( Test_enWires[70] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5964 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5965 ) ,
+ .Test_en_W_out ( Test_enWires[68] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5966 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[12] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[13] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5967 ) ,
+ .prog_clk_2_N_in ( p3265 ) , .prog_clk_2_S_in ( p2200 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5968 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5969 ) ,
+ .prog_clk_3_S_in ( p2350 ) , .prog_clk_3_N_in ( p3240 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5970 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5971 ) , .clk_2_N_in ( p3139 ) ,
+ .clk_2_S_in ( p153 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5972 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5973 ) , .clk_3_S_in ( p2061 ) ,
+ .clk_3_N_in ( p106 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5974 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5975 ) ) ;
+cby_1__1_ cby_1__4_ ( .chany_bottom_in ( sb_1__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_3_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__3_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__3_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5976 ) ,
+ .Test_en_E_in ( Test_enWires[92] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5977 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5978 ) ,
+ .Test_en_W_out ( Test_enWires[90] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5979 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[17] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[18] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5980 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[10] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5981 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[11] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5982 ) ,
+ .prog_clk_3_S_in ( p1632 ) , .prog_clk_3_N_in ( p908 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5983 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5984 ) ,
+ .clk_2_N_in ( clk_2_wires[10] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5985 ) ,
+ .clk_2_S_out ( clk_2_wires[11] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5986 ) , .clk_3_S_in ( p1632 ) ,
+ .clk_3_N_in ( p476 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5987 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5988 ) ) ;
+cby_1__1_ cby_1__5_ ( .chany_bottom_in ( sb_1__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_4_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__4_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__4_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5989 ) ,
+ .Test_en_E_in ( Test_enWires[114] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5990 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5991 ) ,
+ .Test_en_W_out ( Test_enWires[112] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5992 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[22] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[23] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5993 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5994 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[8] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5995 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p2125 ) ,
+ .prog_clk_3_N_in ( p1073 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5996 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5997 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5998 ) ,
+ .clk_2_S_in ( clk_2_wires[8] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5999 ) ,
+ .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p2125 ) ,
+ .clk_3_N_in ( p630 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6000 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6001 ) ) ;
+cby_1__1_ cby_1__6_ ( .chany_bottom_in ( sb_1__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_5_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__5_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__5_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6002 ) ,
+ .Test_en_E_in ( Test_enWires[136] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6003 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6004 ) ,
+ .Test_en_W_out ( Test_enWires[134] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6005 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[27] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[28] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6006 ) ,
+ .prog_clk_2_N_in ( p3388 ) , .prog_clk_2_S_in ( p2484 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6007 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6008 ) ,
+ .prog_clk_3_S_in ( p2610 ) , .prog_clk_3_N_in ( p3354 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6009 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6010 ) , .clk_2_N_in ( p2288 ) ,
+ .clk_2_S_in ( p897 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6011 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6012 ) , .clk_3_S_in ( p2164 ) ,
+ .clk_3_N_in ( p862 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6013 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6014 ) ) ;
+cby_1__1_ cby_1__7_ ( .chany_bottom_in ( sb_1__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_6_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__6_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__6_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6015 ) ,
+ .Test_en_E_in ( Test_enWires[158] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6016 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6017 ) ,
+ .Test_en_W_out ( Test_enWires[156] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6018 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[32] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[33] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6019 ) ,
+ .prog_clk_2_N_in ( p1681 ) , .prog_clk_2_S_in ( p1945 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6020 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6021 ) ,
+ .prog_clk_3_S_in ( p2120 ) , .prog_clk_3_N_in ( p3187 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6022 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6023 ) , .clk_2_N_in ( p3216 ) ,
+ .clk_2_S_in ( p566 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6024 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6025 ) , .clk_3_S_in ( p1820 ) ,
+ .clk_3_N_in ( p1003 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6026 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6027 ) ) ;
+cby_1__1_ cby_1__8_ ( .chany_bottom_in ( sb_1__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_7_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__7_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__7_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6028 ) ,
+ .Test_en_E_in ( Test_enWires[180] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6029 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6030 ) ,
+ .Test_en_W_out ( Test_enWires[178] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6031 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[37] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[38] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6032 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[17] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6033 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[18] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6034 ) ,
+ .prog_clk_3_S_in ( p1503 ) , .prog_clk_3_N_in ( p27 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6035 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6036 ) ,
+ .clk_2_N_in ( clk_2_wires[17] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6037 ) ,
+ .clk_2_S_out ( clk_2_wires[18] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6038 ) , .clk_3_S_in ( p1635 ) ,
+ .clk_3_N_in ( p814 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6039 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6040 ) ) ;
+cby_1__1_ cby_1__9_ ( .chany_bottom_in ( sb_1__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_8_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__8_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__8_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6041 ) ,
+ .Test_en_E_in ( Test_enWires[202] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6042 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6043 ) ,
+ .Test_en_W_out ( Test_enWires[200] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6044 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[42] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[43] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6045 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6046 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[15] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6047 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1590 ) ,
+ .prog_clk_3_N_in ( p1170 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6048 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6049 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6050 ) ,
+ .clk_2_S_in ( clk_2_wires[15] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6051 ) ,
+ .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p2158 ) ,
+ .clk_3_N_in ( p586 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6052 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6053 ) ) ;
+cby_1__1_ cby_1__10_ ( .chany_bottom_in ( sb_1__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_9_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__9_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__9_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6054 ) ,
+ .Test_en_E_in ( Test_enWires[224] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6055 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6056 ) ,
+ .Test_en_W_out ( Test_enWires[222] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6057 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[47] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[48] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6058 ) ,
+ .prog_clk_2_N_in ( p2704 ) , .prog_clk_2_S_in ( p3081 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6059 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6060 ) ,
+ .prog_clk_3_S_in ( p3149 ) , .prog_clk_3_N_in ( p3076 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6061 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6062 ) , .clk_2_N_in ( p3099 ) ,
+ .clk_2_S_in ( p229 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6063 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6064 ) , .clk_3_S_in ( p1579 ) ,
+ .clk_3_N_in ( p813 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6065 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6066 ) ) ;
+cby_1__1_ cby_1__11_ ( .chany_bottom_in ( sb_1__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_10_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__10_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__10_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6067 ) ,
+ .Test_en_E_in ( Test_enWires[246] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6068 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6069 ) ,
+ .Test_en_W_out ( Test_enWires[244] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6070 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[52] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[53] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6071 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6072 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[22] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6073 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1858 ) ,
+ .prog_clk_3_N_in ( p708 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6074 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6075 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6076 ) ,
+ .clk_2_S_in ( clk_2_wires[22] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6077 ) ,
+ .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1390 ) ,
+ .clk_3_N_in ( p353 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6078 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6079 ) ) ;
+cby_1__1_ cby_1__12_ ( .chany_bottom_in ( sb_1__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_11_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__11_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__11_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6080 ) ,
+ .Test_en_E_in ( Test_enWires[268] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6081 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6082 ) ,
+ .Test_en_W_out ( Test_enWires[266] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6083 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[57] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[58] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p2040 ) ,
+ .prog_clk_2_S_in ( p3242 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6084 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6085 ) ,
+ .prog_clk_3_S_in ( p3266 ) , .prog_clk_3_N_in ( p2453 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6086 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6087 ) , .clk_2_N_in ( p2535 ) ,
+ .clk_2_S_in ( p672 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6088 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6089 ) , .clk_3_S_in ( p2404 ) ,
+ .clk_3_N_in ( p202 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6090 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6091 ) ) ;
+cby_1__1_ cby_2__1_ ( .chany_bottom_in ( sb_1__0__1_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__11_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_12_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__12_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__12_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__12_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6092 ) ,
+ .Test_en_E_in ( Test_enWires[28] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6093 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6094 ) ,
+ .Test_en_W_out ( Test_enWires[25] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6095 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[64] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[65] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6096 ) ,
+ .prog_clk_2_N_in ( p2595 ) , .prog_clk_2_S_in ( p2956 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6097 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6098 ) ,
+ .prog_clk_3_S_in ( p3054 ) , .prog_clk_3_N_in ( p2967 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6099 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6100 ) , .clk_2_N_in ( p3001 ) ,
+ .clk_2_S_in ( p1 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6101 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6102 ) , .clk_3_S_in ( p1859 ) ,
+ .clk_3_N_in ( p1230 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6103 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6104 ) ) ;
+cby_1__1_ cby_2__2_ ( .chany_bottom_in ( sb_1__1__11_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__12_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_13_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__13_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__13_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__13_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6105 ) ,
+ .Test_en_E_in ( Test_enWires[50] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6106 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6107 ) ,
+ .Test_en_W_out ( Test_enWires[47] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6108 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[67] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[68] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6109 ) ,
+ .prog_clk_2_N_in ( p2572 ) , .prog_clk_2_S_in ( p2490 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6110 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6111 ) ,
+ .prog_clk_3_S_in ( p2524 ) , .prog_clk_3_N_in ( p3154 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6112 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6113 ) , .clk_2_N_in ( p3232 ) ,
+ .clk_2_S_in ( p824 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6114 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6115 ) , .clk_3_S_in ( p2289 ) ,
+ .clk_3_N_in ( p167 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6116 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6117 ) ) ;
+cby_1__1_ cby_2__3_ ( .chany_bottom_in ( sb_1__1__12_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__13_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_14_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__14_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__14_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__14_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6118 ) ,
+ .Test_en_E_in ( Test_enWires[72] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6119 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6120 ) ,
+ .Test_en_W_out ( Test_enWires[69] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6121 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[70] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[71] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6122 ) ,
+ .prog_clk_2_N_in ( p1846 ) , .prog_clk_2_S_in ( p591 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6123 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6124 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6125 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[68] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6126 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1846 ) ,
+ .clk_2_S_in ( p1088 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6127 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6128 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6129 ) ,
+ .clk_3_N_in ( clk_3_wires[68] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6130 ) ,
+ .clk_3_S_out ( clk_3_wires[69] ) ) ;
+cby_1__1_ cby_2__4_ ( .chany_bottom_in ( sb_1__1__13_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__14_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_15_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__15_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__15_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__15_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6131 ) ,
+ .Test_en_E_in ( Test_enWires[94] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6132 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6133 ) ,
+ .Test_en_W_out ( Test_enWires[91] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6134 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[73] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[74] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6135 ) ,
+ .prog_clk_2_N_in ( p1627 ) , .prog_clk_2_S_in ( p400 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6136 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6137 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6138 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[64] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6139 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1627 ) ,
+ .clk_2_S_in ( p868 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6140 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6141 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6142 ) ,
+ .clk_3_N_in ( clk_3_wires[64] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6143 ) ,
+ .clk_3_S_out ( clk_3_wires[65] ) ) ;
+cby_1__1_ cby_2__5_ ( .chany_bottom_in ( sb_1__1__14_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__15_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_16_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__16_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__16_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__16_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6144 ) ,
+ .Test_en_E_in ( Test_enWires[116] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6145 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6146 ) ,
+ .Test_en_W_out ( Test_enWires[113] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6147 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[76] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[77] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6148 ) ,
+ .prog_clk_2_N_in ( p2130 ) , .prog_clk_2_S_in ( p273 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6149 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6150 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6151 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[58] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6152 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p2071 ) ,
+ .clk_2_S_in ( p637 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6153 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6154 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6155 ) ,
+ .clk_3_N_in ( clk_3_wires[58] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6156 ) ,
+ .clk_3_S_out ( clk_3_wires[59] ) ) ;
+cby_1__1_ cby_2__6_ ( .chany_bottom_in ( sb_1__1__15_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__16_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_17_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__17_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__17_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__17_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6157 ) ,
+ .Test_en_E_in ( Test_enWires[138] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6158 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6159 ) ,
+ .Test_en_W_out ( Test_enWires[135] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6160 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[79] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[80] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6161 ) ,
+ .prog_clk_2_N_in ( p2136 ) , .prog_clk_2_S_in ( p485 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6162 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6163 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6164 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[54] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6165 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p2136 ) ,
+ .clk_2_S_in ( p994 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6166 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6167 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6168 ) ,
+ .clk_3_N_in ( clk_3_wires[54] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6169 ) ,
+ .clk_3_S_out ( clk_3_wires[55] ) ) ;
+cby_1__1_ cby_2__7_ ( .chany_bottom_in ( sb_1__1__16_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__17_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_18_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__18_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__18_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__18_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6170 ) ,
+ .Test_en_E_in ( Test_enWires[160] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6171 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6172 ) ,
+ .Test_en_W_out ( Test_enWires[157] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6173 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[82] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[83] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6174 ) ,
+ .prog_clk_2_N_in ( p2357 ) , .prog_clk_2_S_in ( p536 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6175 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6176 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[52] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6177 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[53] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6178 ) , .clk_2_N_in ( p2357 ) ,
+ .clk_2_S_in ( p93 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6179 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6180 ) ,
+ .clk_3_S_in ( clk_3_wires[52] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6181 ) ,
+ .clk_3_N_out ( clk_3_wires[53] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6182 ) ) ;
+cby_1__1_ cby_2__8_ ( .chany_bottom_in ( sb_1__1__17_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__18_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_19_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__19_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__19_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__19_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6183 ) ,
+ .Test_en_E_in ( Test_enWires[182] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6184 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6185 ) ,
+ .Test_en_W_out ( Test_enWires[179] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6186 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[85] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[86] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6187 ) ,
+ .prog_clk_2_N_in ( p1869 ) , .prog_clk_2_S_in ( p250 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6188 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6189 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[56] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6190 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[57] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6191 ) , .clk_2_N_in ( p1869 ) ,
+ .clk_2_S_in ( p880 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6192 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6193 ) ,
+ .clk_3_S_in ( clk_3_wires[56] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6194 ) ,
+ .clk_3_N_out ( clk_3_wires[57] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6195 ) ) ;
+cby_1__1_ cby_2__9_ ( .chany_bottom_in ( sb_1__1__18_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__19_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_20_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__20_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__20_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__20_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6196 ) ,
+ .Test_en_E_in ( Test_enWires[204] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6197 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6198 ) ,
+ .Test_en_W_out ( Test_enWires[201] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6199 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[88] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[89] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6200 ) ,
+ .prog_clk_2_N_in ( p1507 ) , .prog_clk_2_S_in ( p180 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6201 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6202 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[62] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6203 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[63] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6204 ) , .clk_2_N_in ( p1507 ) ,
+ .clk_2_S_in ( p729 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6205 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6206 ) ,
+ .clk_3_S_in ( clk_3_wires[62] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6207 ) ,
+ .clk_3_N_out ( clk_3_wires[63] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6208 ) ) ;
+cby_1__1_ cby_2__10_ ( .chany_bottom_in ( sb_1__1__19_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__20_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_21_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__21_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__21_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__21_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6209 ) ,
+ .Test_en_E_in ( Test_enWires[226] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6210 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6211 ) ,
+ .Test_en_W_out ( Test_enWires[223] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6212 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[91] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[92] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6213 ) ,
+ .prog_clk_2_N_in ( p1399 ) , .prog_clk_2_S_in ( p323 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6214 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6215 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[66] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6216 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[67] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6217 ) , .clk_2_N_in ( p1399 ) ,
+ .clk_2_S_in ( p774 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6218 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6219 ) ,
+ .clk_3_S_in ( clk_3_wires[66] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6220 ) ,
+ .clk_3_N_out ( clk_3_wires[67] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6221 ) ) ;
+cby_1__1_ cby_2__11_ ( .chany_bottom_in ( sb_1__1__20_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__21_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_22_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__22_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__22_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__22_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6222 ) ,
+ .Test_en_E_in ( Test_enWires[248] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6223 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6224 ) ,
+ .Test_en_W_out ( Test_enWires[245] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6225 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[94] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[95] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6226 ) ,
+ .prog_clk_2_N_in ( p3279 ) , .prog_clk_2_S_in ( p3262 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6227 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6228 ) ,
+ .prog_clk_3_S_in ( p3270 ) , .prog_clk_3_N_in ( p3254 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6229 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6230 ) , .clk_2_N_in ( p2153 ) ,
+ .clk_2_S_in ( p895 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6231 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6232 ) , .clk_3_S_in ( p2590 ) ,
+ .clk_3_N_in ( p1186 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6233 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6234 ) ) ;
+cby_1__1_ cby_2__12_ ( .chany_bottom_in ( sb_1__1__21_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_23_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__23_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__23_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__23_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6235 ) ,
+ .Test_en_E_in ( Test_enWires[270] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6236 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6237 ) ,
+ .Test_en_W_out ( Test_enWires[267] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6238 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[97] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[98] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p1724 ) ,
+ .prog_clk_2_S_in ( p2832 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6239 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6240 ) ,
+ .prog_clk_3_S_in ( p2866 ) , .prog_clk_3_N_in ( p2965 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6241 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6242 ) , .clk_2_N_in ( p2994 ) ,
+ .clk_2_S_in ( p555 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6243 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6244 ) , .clk_3_S_in ( p1288 ) ,
+ .clk_3_N_in ( p1017 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6245 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6246 ) ) ;
+cby_1__1_ cby_3__1_ ( .chany_bottom_in ( sb_1__0__2_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__22_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_24_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__24_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__24_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__24_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6247 ) ,
+ .Test_en_E_in ( Test_enWires[30] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6248 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6249 ) ,
+ .Test_en_W_out ( Test_enWires[27] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6250 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[102] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[103] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6251 ) ,
+ .prog_clk_2_N_in ( p2328 ) , .prog_clk_2_S_in ( p3084 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6252 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6253 ) ,
+ .prog_clk_3_S_in ( p3129 ) , .prog_clk_3_N_in ( p3159 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6254 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6255 ) , .clk_2_N_in ( p3231 ) ,
+ .clk_2_S_in ( p1038 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6256 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6257 ) , .clk_3_S_in ( p1530 ) ,
+ .clk_3_N_in ( p49 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6258 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6259 ) ) ;
+cby_1__1_ cby_3__2_ ( .chany_bottom_in ( sb_1__1__22_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__23_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_25_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__25_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__25_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__25_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6260 ) ,
+ .Test_en_E_in ( Test_enWires[52] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6261 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6262 ) ,
+ .Test_en_W_out ( Test_enWires[49] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6263 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[105] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[106] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6264 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[29] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6265 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[30] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6266 ) ,
+ .prog_clk_3_S_in ( p1845 ) , .prog_clk_3_N_in ( p944 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6267 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6268 ) ,
+ .clk_2_N_in ( clk_2_wires[29] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6269 ) ,
+ .clk_2_S_out ( clk_2_wires[30] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6270 ) , .clk_3_S_in ( p1845 ) ,
+ .clk_3_N_in ( p173 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6271 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6272 ) ) ;
+cby_1__1_ cby_3__3_ ( .chany_bottom_in ( sb_1__1__23_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__24_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_26_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__26_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__26_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__26_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6273 ) ,
+ .Test_en_E_in ( Test_enWires[74] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6274 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6275 ) ,
+ .Test_en_W_out ( Test_enWires[71] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6276 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[108] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[109] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6277 ) ,
+ .prog_clk_2_N_in ( p2716 ) , .prog_clk_2_S_in ( p2449 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6278 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6279 ) ,
+ .prog_clk_3_S_in ( p2627 ) , .prog_clk_3_N_in ( p2662 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6280 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6281 ) , .clk_2_N_in ( p2374 ) ,
+ .clk_2_S_in ( p373 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6282 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6283 ) , .clk_3_S_in ( p1664 ) ,
+ .clk_3_N_in ( p1150 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6284 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6285 ) ) ;
+cby_1__1_ cby_3__4_ ( .chany_bottom_in ( sb_1__1__24_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__25_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_27_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__27_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__27_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__27_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6286 ) ,
+ .Test_en_E_in ( Test_enWires[96] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6287 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6288 ) ,
+ .Test_en_W_out ( Test_enWires[93] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6289 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[111] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[112] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6290 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[40] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6291 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[41] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6292 ) ,
+ .prog_clk_3_S_in ( p1675 ) , .prog_clk_3_N_in ( p742 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6293 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6294 ) ,
+ .clk_2_N_in ( clk_2_wires[40] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6295 ) ,
+ .clk_2_S_out ( clk_2_wires[41] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6296 ) , .clk_3_S_in ( p2053 ) ,
+ .clk_3_N_in ( p360 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6297 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6298 ) ) ;
+cby_1__1_ cby_3__5_ ( .chany_bottom_in ( sb_1__1__25_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__26_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_28_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__28_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__28_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__28_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6299 ) ,
+ .Test_en_E_in ( Test_enWires[118] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6300 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6301 ) ,
+ .Test_en_W_out ( Test_enWires[115] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6302 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[114] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[115] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6303 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6304 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[38] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6305 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p1356 ) ,
+ .prog_clk_3_N_in ( p493 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6306 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6307 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6308 ) ,
+ .clk_2_S_in ( clk_2_wires[38] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6309 ) ,
+ .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p2369 ) ,
+ .clk_3_N_in ( p1099 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6310 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6311 ) ) ;
+cby_1__1_ cby_3__6_ ( .chany_bottom_in ( sb_1__1__26_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__27_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_29_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__29_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__29_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__29_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6312 ) ,
+ .Test_en_E_in ( Test_enWires[140] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6313 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6314 ) ,
+ .Test_en_W_out ( Test_enWires[137] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6315 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[117] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[118] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6316 ) ,
+ .prog_clk_2_N_in ( p3414 ) , .prog_clk_2_S_in ( p2813 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6317 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6318 ) ,
+ .prog_clk_3_S_in ( p2871 ) , .prog_clk_3_N_in ( p3397 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6319 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6320 ) , .clk_2_N_in ( p3288 ) ,
+ .clk_2_S_in ( p721 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6321 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6322 ) , .clk_3_S_in ( p1817 ) ,
+ .clk_3_N_in ( p368 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6323 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6324 ) ) ;
+cby_1__1_ cby_3__7_ ( .chany_bottom_in ( sb_1__1__27_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__28_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_30_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__30_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__30_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__30_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6325 ) ,
+ .Test_en_E_in ( Test_enWires[162] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6326 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6327 ) ,
+ .Test_en_W_out ( Test_enWires[159] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6328 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[120] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[121] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6329 ) ,
+ .prog_clk_2_N_in ( p2890 ) , .prog_clk_2_S_in ( p2441 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6330 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6331 ) ,
+ .prog_clk_3_S_in ( p2619 ) , .prog_clk_3_N_in ( p3079 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6332 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6333 ) , .clk_2_N_in ( p3137 ) ,
+ .clk_2_S_in ( p1072 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6334 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6335 ) , .clk_3_S_in ( p1597 ) ,
+ .clk_3_N_in ( p68 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6336 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6337 ) ) ;
+cby_1__1_ cby_3__8_ ( .chany_bottom_in ( sb_1__1__28_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__29_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_31_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__31_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__31_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__31_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6338 ) ,
+ .Test_en_E_in ( Test_enWires[184] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6339 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6340 ) ,
+ .Test_en_W_out ( Test_enWires[181] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6341 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[123] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[124] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6342 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[53] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6343 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[54] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6344 ) ,
+ .prog_clk_3_S_in ( p1860 ) , .prog_clk_3_N_in ( p554 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6345 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6346 ) ,
+ .clk_2_N_in ( clk_2_wires[53] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6347 ) ,
+ .clk_2_S_out ( clk_2_wires[54] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6348 ) , .clk_3_S_in ( p2597 ) ,
+ .clk_3_N_in ( p406 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6349 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6350 ) ) ;
+cby_1__1_ cby_3__9_ ( .chany_bottom_in ( sb_1__1__29_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__30_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_32_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__32_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__32_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__32_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6351 ) ,
+ .Test_en_E_in ( Test_enWires[206] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6352 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6353 ) ,
+ .Test_en_W_out ( Test_enWires[203] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6354 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[126] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[127] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6355 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6356 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[51] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6357 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p2015 ) ,
+ .prog_clk_3_N_in ( p750 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6358 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6359 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6360 ) ,
+ .clk_2_S_in ( clk_2_wires[51] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6361 ) ,
+ .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p2608 ) ,
+ .clk_3_N_in ( p653 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6362 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6363 ) ) ;
+cby_1__1_ cby_3__10_ ( .chany_bottom_in ( sb_1__1__30_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__31_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_33_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__33_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__33_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__33_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6364 ) ,
+ .Test_en_E_in ( Test_enWires[228] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6365 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6366 ) ,
+ .Test_en_W_out ( Test_enWires[225] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6367 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[129] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[130] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6368 ) ,
+ .prog_clk_2_N_in ( p2709 ) , .prog_clk_2_S_in ( p2437 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6369 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6370 ) ,
+ .prog_clk_3_S_in ( p2616 ) , .prog_clk_3_N_in ( p3303 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6371 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_2_N_in ( p3343 ) ,
+ .clk_2_S_in ( p90 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6373 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6374 ) , .clk_3_S_in ( p1481 ) ,
+ .clk_3_N_in ( p941 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6375 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6376 ) ) ;
+cby_1__1_ cby_3__11_ ( .chany_bottom_in ( sb_1__1__31_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__32_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_34_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__34_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__34_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__34_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6377 ) ,
+ .Test_en_E_in ( Test_enWires[250] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6378 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6379 ) ,
+ .Test_en_W_out ( Test_enWires[247] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6380 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[132] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[133] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6381 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6382 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[64] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6383 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p1485 ) ,
+ .prog_clk_3_N_in ( p1034 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6384 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6385 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6386 ) ,
+ .clk_2_S_in ( clk_2_wires[64] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6387 ) ,
+ .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p1795 ) ,
+ .clk_3_N_in ( p254 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6388 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6389 ) ) ;
+cby_1__1_ cby_3__12_ ( .chany_bottom_in ( sb_1__1__32_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_35_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__35_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__35_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__35_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6390 ) ,
+ .Test_en_E_in ( Test_enWires[272] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6391 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6392 ) ,
+ .Test_en_W_out ( Test_enWires[269] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6393 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[135] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[136] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p2575 ) ,
+ .prog_clk_2_S_in ( p3321 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6394 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6395 ) ,
+ .prog_clk_3_S_in ( p3330 ) , .prog_clk_3_N_in ( p3152 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6396 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6397 ) , .clk_2_N_in ( p3211 ) ,
+ .clk_2_S_in ( p516 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6398 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6399 ) , .clk_3_S_in ( p2539 ) ,
+ .clk_3_N_in ( p1974 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6400 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6401 ) ) ;
+cby_1__1_ cby_4__1_ ( .chany_bottom_in ( sb_1__0__3_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__33_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_36_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__36_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__36_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__36_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6402 ) ,
+ .Test_en_E_in ( Test_enWires[32] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6403 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6404 ) ,
+ .Test_en_W_out ( Test_enWires[29] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6405 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[140] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[141] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6406 ) ,
+ .prog_clk_2_N_in ( p2604 ) , .prog_clk_2_S_in ( p1909 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6407 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6408 ) ,
+ .prog_clk_3_S_in ( p2157 ) , .prog_clk_3_N_in ( p3179 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6409 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6410 ) , .clk_2_N_in ( p3235 ) ,
+ .clk_2_S_in ( p60 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6411 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6412 ) , .clk_3_S_in ( p1775 ) ,
+ .clk_3_N_in ( p1270 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6413 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6414 ) ) ;
+cby_1__1_ cby_4__2_ ( .chany_bottom_in ( sb_1__1__33_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__34_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_37_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__37_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__37_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__37_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6415 ) ,
+ .Test_en_E_in ( Test_enWires[54] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6416 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6417 ) ,
+ .Test_en_W_out ( Test_enWires[51] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6418 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[143] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[144] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6419 ) ,
+ .prog_clk_2_N_in ( p3338 ) , .prog_clk_2_S_in ( p3064 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6420 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6421 ) ,
+ .prog_clk_3_S_in ( p3117 ) , .prog_clk_3_N_in ( p3305 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6422 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_2_N_in ( p3283 ) ,
+ .clk_2_S_in ( p727 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6424 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6425 ) , .clk_3_S_in ( p2100 ) ,
+ .clk_3_N_in ( p0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6426 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6427 ) ) ;
+cby_1__1_ cby_4__3_ ( .chany_bottom_in ( sb_1__1__34_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__35_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_38_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__38_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__38_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__38_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6428 ) ,
+ .Test_en_E_in ( Test_enWires[76] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6429 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6430 ) ,
+ .Test_en_W_out ( Test_enWires[73] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6431 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[146] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[147] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6432 ) ,
+ .prog_clk_2_N_in ( p1865 ) , .prog_clk_2_S_in ( p1078 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6433 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6434 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6435 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[24] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6436 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p1865 ) ,
+ .clk_2_S_in ( p378 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6437 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6438 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6439 ) ,
+ .clk_3_N_in ( clk_3_wires[24] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6440 ) ,
+ .clk_3_S_out ( clk_3_wires[25] ) ) ;
+cby_1__1_ cby_4__4_ ( .chany_bottom_in ( sb_1__1__35_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__36_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_39_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__39_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__39_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__39_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6441 ) ,
+ .Test_en_E_in ( Test_enWires[98] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6442 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6443 ) ,
+ .Test_en_W_out ( Test_enWires[95] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6444 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[149] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[150] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6445 ) ,
+ .prog_clk_2_N_in ( p1768 ) , .prog_clk_2_S_in ( p65 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6446 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6447 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6448 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[20] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6449 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1768 ) ,
+ .clk_2_S_in ( p374 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6450 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6451 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6452 ) ,
+ .clk_3_N_in ( clk_3_wires[20] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6453 ) ,
+ .clk_3_S_out ( clk_3_wires[21] ) ) ;
+cby_1__1_ cby_4__5_ ( .chany_bottom_in ( sb_1__1__36_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__37_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_40_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__40_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__40_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__40_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6454 ) ,
+ .Test_en_E_in ( Test_enWires[120] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6455 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6456 ) ,
+ .Test_en_W_out ( Test_enWires[117] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6457 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[152] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[153] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6458 ) ,
+ .prog_clk_2_N_in ( p1840 ) , .prog_clk_2_S_in ( p968 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6459 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6460 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6461 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[14] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6462 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1840 ) ,
+ .clk_2_S_in ( p1938 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6463 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6464 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6465 ) ,
+ .clk_3_N_in ( clk_3_wires[14] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6466 ) ,
+ .clk_3_S_out ( clk_3_wires[15] ) ) ;
+cby_1__1_ cby_4__6_ ( .chany_bottom_in ( sb_1__1__37_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__38_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_41_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__41_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__41_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__41_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6467 ) ,
+ .Test_en_E_in ( Test_enWires[142] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6468 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6469 ) ,
+ .Test_en_W_out ( Test_enWires[139] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6470 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[155] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[156] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6471 ) ,
+ .prog_clk_2_N_in ( p1805 ) , .prog_clk_2_S_in ( p411 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6472 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6473 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6474 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[10] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6475 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p1805 ) ,
+ .clk_2_S_in ( p857 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6476 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6477 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6478 ) ,
+ .clk_3_N_in ( clk_3_wires[10] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6479 ) ,
+ .clk_3_S_out ( clk_3_wires[11] ) ) ;
+cby_1__1_ cby_4__7_ ( .chany_bottom_in ( sb_1__1__38_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__39_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_42_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__42_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__42_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__42_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6480 ) ,
+ .Test_en_E_in ( Test_enWires[164] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6481 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6482 ) ,
+ .Test_en_W_out ( Test_enWires[161] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6483 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[158] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[159] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6484 ) ,
+ .prog_clk_2_N_in ( p1647 ) , .prog_clk_2_S_in ( p240 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6485 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6486 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[8] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6487 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[9] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6488 ) , .clk_2_N_in ( p1647 ) ,
+ .clk_2_S_in ( p645 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6489 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6490 ) ,
+ .clk_3_S_in ( clk_3_wires[8] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6491 ) ,
+ .clk_3_N_out ( clk_3_wires[9] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6492 ) ) ;
+cby_1__1_ cby_4__8_ ( .chany_bottom_in ( sb_1__1__39_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__40_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_43_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__43_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__43_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__43_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6493 ) ,
+ .Test_en_E_in ( Test_enWires[186] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6494 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6495 ) ,
+ .Test_en_W_out ( Test_enWires[183] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6496 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[161] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[162] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6497 ) ,
+ .prog_clk_2_N_in ( p1792 ) , .prog_clk_2_S_in ( p635 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6498 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6499 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[12] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6500 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[13] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6501 ) , .clk_2_N_in ( p1792 ) ,
+ .clk_2_S_in ( p224 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6502 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6503 ) ,
+ .clk_3_S_in ( clk_3_wires[12] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6504 ) ,
+ .clk_3_N_out ( clk_3_wires[13] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6505 ) ) ;
+cby_1__1_ cby_4__9_ ( .chany_bottom_in ( sb_1__1__40_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__41_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_44_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__44_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__44_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__44_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6506 ) ,
+ .Test_en_E_in ( Test_enWires[208] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6507 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6508 ) ,
+ .Test_en_W_out ( Test_enWires[205] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6509 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[164] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[165] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6510 ) ,
+ .prog_clk_2_N_in ( p2102 ) , .prog_clk_2_S_in ( p855 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6511 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6512 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[18] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6513 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[19] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6514 ) , .clk_2_N_in ( p2102 ) ,
+ .clk_2_S_in ( p166 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6515 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6516 ) ,
+ .clk_3_S_in ( clk_3_wires[18] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6517 ) ,
+ .clk_3_N_out ( clk_3_wires[19] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6518 ) ) ;
+cby_1__1_ cby_4__10_ ( .chany_bottom_in ( sb_1__1__41_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__42_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_45_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__45_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__45_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__45_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6519 ) ,
+ .Test_en_E_in ( Test_enWires[230] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6520 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6521 ) ,
+ .Test_en_W_out ( Test_enWires[227] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6522 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[167] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[168] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6523 ) ,
+ .prog_clk_2_N_in ( p1352 ) , .prog_clk_2_S_in ( p212 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6524 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6525 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[22] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6526 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[23] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6527 ) , .clk_2_N_in ( p1352 ) ,
+ .clk_2_S_in ( p550 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6528 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6529 ) ,
+ .clk_3_S_in ( clk_3_wires[22] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6530 ) ,
+ .clk_3_N_out ( clk_3_wires[23] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6531 ) ) ;
+cby_1__1_ cby_4__11_ ( .chany_bottom_in ( sb_1__1__42_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__43_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_46_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__46_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__46_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__46_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6532 ) ,
+ .Test_en_E_in ( Test_enWires[252] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6533 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6534 ) ,
+ .Test_en_W_out ( Test_enWires[249] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6535 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[170] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[171] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6536 ) ,
+ .prog_clk_2_N_in ( p3230 ) , .prog_clk_2_S_in ( p2958 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6537 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6538 ) ,
+ .prog_clk_3_S_in ( p2993 ) , .prog_clk_3_N_in ( p3161 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6539 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6540 ) , .clk_2_N_in ( p1782 ) ,
+ .clk_2_S_in ( p443 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6541 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6542 ) , .clk_3_S_in ( p1477 ) ,
+ .clk_3_N_in ( p1074 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6543 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6544 ) ) ;
+cby_1__1_ cby_4__12_ ( .chany_bottom_in ( sb_1__1__43_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_47_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__47_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__47_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__47_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6545 ) ,
+ .Test_en_E_in ( Test_enWires[274] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6546 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6547 ) ,
+ .Test_en_W_out ( Test_enWires[271] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6548 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[173] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[174] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p2723 ) ,
+ .prog_clk_2_S_in ( p1895 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6549 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6550 ) ,
+ .prog_clk_3_S_in ( p1986 ) , .prog_clk_3_N_in ( p2644 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6551 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6552 ) , .clk_2_N_in ( p2329 ) ,
+ .clk_2_S_in ( p547 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6553 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6554 ) , .clk_3_S_in ( p2529 ) ,
+ .clk_3_N_in ( p861 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6555 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6556 ) ) ;
+cby_1__1_ cby_5__1_ ( .chany_bottom_in ( sb_1__0__4_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__44_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_48_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__48_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__48_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__48_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6557 ) ,
+ .Test_en_E_in ( Test_enWires[34] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6558 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6559 ) ,
+ .Test_en_W_out ( Test_enWires[31] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6560 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[178] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[179] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6561 ) ,
+ .prog_clk_2_N_in ( p3199 ) , .prog_clk_2_S_in ( p2938 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6562 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6563 ) ,
+ .prog_clk_3_S_in ( p2995 ) , .prog_clk_3_N_in ( p3180 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6564 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6565 ) , .clk_2_N_in ( p2931 ) ,
+ .clk_2_S_in ( p2225 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6566 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6567 ) , .clk_3_S_in ( p2321 ) ,
+ .clk_3_N_in ( p749 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6568 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6569 ) ) ;
+cby_1__1_ cby_5__2_ ( .chany_bottom_in ( sb_1__1__44_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__45_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_49_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__49_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__49_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__49_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6570 ) ,
+ .Test_en_E_in ( Test_enWires[56] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6571 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6572 ) ,
+ .Test_en_W_out ( Test_enWires[53] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6573 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[181] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[182] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6574 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[31] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6575 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[32] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6576 ) ,
+ .prog_clk_3_S_in ( p1706 ) , .prog_clk_3_N_in ( p1259 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6577 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6578 ) ,
+ .clk_2_N_in ( clk_2_wires[31] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6579 ) ,
+ .clk_2_S_out ( clk_2_wires[32] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6580 ) , .clk_3_S_in ( p2174 ) ,
+ .clk_3_N_in ( p417 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6581 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6582 ) ) ;
+cby_1__1_ cby_5__3_ ( .chany_bottom_in ( sb_1__1__45_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__46_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_50_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__50_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__50_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__50_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6583 ) ,
+ .Test_en_E_in ( Test_enWires[78] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6584 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6585 ) ,
+ .Test_en_W_out ( Test_enWires[75] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6586 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[184] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[185] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6587 ) ,
+ .prog_clk_2_N_in ( p3030 ) , .prog_clk_2_S_in ( p2202 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6588 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6589 ) ,
+ .prog_clk_3_S_in ( p2331 ) , .prog_clk_3_N_in ( p3185 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6590 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6591 ) , .clk_2_N_in ( p3221 ) ,
+ .clk_2_S_in ( p102 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6592 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6593 ) , .clk_3_S_in ( p2160 ) ,
+ .clk_3_N_in ( p731 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6594 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6595 ) ) ;
+cby_1__1_ cby_5__4_ ( .chany_bottom_in ( sb_1__1__46_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__47_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_51_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__51_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__51_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__51_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6596 ) ,
+ .Test_en_E_in ( Test_enWires[100] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6597 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6598 ) ,
+ .Test_en_W_out ( Test_enWires[97] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6599 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[187] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[188] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6600 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[44] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6601 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[45] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6602 ) ,
+ .prog_clk_3_S_in ( p1877 ) , .prog_clk_3_N_in ( p1026 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6603 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6604 ) ,
+ .clk_2_N_in ( clk_2_wires[44] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6605 ) ,
+ .clk_2_S_out ( clk_2_wires[45] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6606 ) , .clk_3_S_in ( p2794 ) ,
+ .clk_3_N_in ( p639 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6607 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6608 ) ) ;
+cby_1__1_ cby_5__5_ ( .chany_bottom_in ( sb_1__1__47_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__48_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_52_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__52_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__52_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__52_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6609 ) ,
+ .Test_en_E_in ( Test_enWires[122] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6610 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6611 ) ,
+ .Test_en_W_out ( Test_enWires[119] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6612 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[190] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[191] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6613 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6614 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[42] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6615 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p2592 ) ,
+ .prog_clk_3_N_in ( p779 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6616 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6617 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6618 ) ,
+ .clk_2_S_in ( clk_2_wires[42] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6619 ) ,
+ .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p2861 ) ,
+ .clk_3_N_in ( p1313 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6620 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6621 ) ) ;
+cby_1__1_ cby_5__6_ ( .chany_bottom_in ( sb_1__1__48_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__49_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_53_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__53_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__53_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__53_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6622 ) ,
+ .Test_en_E_in ( Test_enWires[144] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6623 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6624 ) ,
+ .Test_en_W_out ( Test_enWires[141] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6625 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[193] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[194] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6626 ) ,
+ .prog_clk_2_N_in ( p3298 ) , .prog_clk_2_S_in ( p2828 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6627 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6628 ) ,
+ .prog_clk_3_S_in ( p2924 ) , .prog_clk_3_N_in ( p3259 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6629 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_2_N_in ( p2388 ) ,
+ .clk_2_S_in ( p357 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6631 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6632 ) , .clk_3_S_in ( p1633 ) ,
+ .clk_3_N_in ( p714 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6633 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6634 ) ) ;
+cby_1__1_ cby_5__7_ ( .chany_bottom_in ( sb_1__1__49_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__50_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_54_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__54_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__54_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__54_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6635 ) ,
+ .Test_en_E_in ( Test_enWires[166] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6636 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6637 ) ,
+ .Test_en_W_out ( Test_enWires[163] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6638 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[196] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[197] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6639 ) ,
+ .prog_clk_2_N_in ( p2922 ) , .prog_clk_2_S_in ( p2440 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6640 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6641 ) ,
+ .prog_clk_3_S_in ( p2540 ) , .prog_clk_3_N_in ( p2816 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6642 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6643 ) , .clk_2_N_in ( p2936 ) ,
+ .clk_2_S_in ( p1925 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6644 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_S_in ( p2145 ) ,
+ .clk_3_N_in ( p706 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6646 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6647 ) ) ;
+cby_1__1_ cby_5__8_ ( .chany_bottom_in ( sb_1__1__50_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__51_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_55_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__55_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__55_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__55_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6648 ) ,
+ .Test_en_E_in ( Test_enWires[188] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6649 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6650 ) ,
+ .Test_en_W_out ( Test_enWires[185] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6651 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[199] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[200] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6652 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[57] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6653 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[58] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6654 ) ,
+ .prog_clk_3_S_in ( p1708 ) , .prog_clk_3_N_in ( p445 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6655 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6656 ) ,
+ .clk_2_N_in ( clk_2_wires[57] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6657 ) ,
+ .clk_2_S_out ( clk_2_wires[58] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_3_S_in ( p2156 ) ,
+ .clk_3_N_in ( p1036 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6659 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6660 ) ) ;
+cby_1__1_ cby_5__9_ ( .chany_bottom_in ( sb_1__1__51_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__52_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_56_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__56_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__56_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__56_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6661 ) ,
+ .Test_en_E_in ( Test_enWires[210] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6662 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6663 ) ,
+ .Test_en_W_out ( Test_enWires[207] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6664 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[202] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[203] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6665 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6666 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[55] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6667 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1745 ) ,
+ .prog_clk_3_N_in ( p1201 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6668 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6669 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6670 ) ,
+ .clk_2_S_in ( clk_2_wires[55] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6671 ) ,
+ .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1745 ) ,
+ .clk_3_N_in ( p887 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6672 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6673 ) ) ;
+cby_1__1_ cby_5__10_ ( .chany_bottom_in ( sb_1__1__52_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__53_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_57_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__57_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__57_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__57_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6674 ) ,
+ .Test_en_E_in ( Test_enWires[232] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6675 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6676 ) ,
+ .Test_en_W_out ( Test_enWires[229] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6677 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[205] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[206] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6678 ) ,
+ .prog_clk_2_N_in ( p3228 ) , .prog_clk_2_S_in ( p3299 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6679 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6680 ) ,
+ .prog_clk_3_S_in ( p3336 ) , .prog_clk_3_N_in ( p3251 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6681 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6682 ) , .clk_2_N_in ( p3289 ) ,
+ .clk_2_S_in ( p503 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6683 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6684 ) , .clk_3_S_in ( p2014 ) ,
+ .clk_3_N_in ( p124 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6685 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6686 ) ) ;
+cby_1__1_ cby_5__11_ ( .chany_bottom_in ( sb_1__1__53_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__54_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_58_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__58_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__58_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__58_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6687 ) ,
+ .Test_en_E_in ( Test_enWires[254] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6688 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6689 ) ,
+ .Test_en_W_out ( Test_enWires[251] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6690 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[208] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[209] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6691 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6692 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[66] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6693 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p2330 ) ,
+ .prog_clk_3_N_in ( p194 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6694 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6695 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6696 ) ,
+ .clk_2_S_in ( clk_2_wires[66] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6697 ) ,
+ .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p2330 ) ,
+ .clk_3_N_in ( p1031 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6698 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6699 ) ) ;
+cby_1__1_ cby_5__12_ ( .chany_bottom_in ( sb_1__1__54_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_59_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__59_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__59_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__59_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6700 ) ,
+ .Test_en_E_in ( Test_enWires[276] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6701 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6702 ) ,
+ .Test_en_W_out ( Test_enWires[273] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6703 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[211] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[212] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p2780 ) ,
+ .prog_clk_2_S_in ( p3319 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6704 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6705 ) ,
+ .prog_clk_3_S_in ( p3326 ) , .prog_clk_3_N_in ( p2657 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6706 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6707 ) , .clk_2_N_in ( p2111 ) ,
+ .clk_2_S_in ( p24 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6708 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_S_in ( p1596 ) ,
+ .clk_3_N_in ( p498 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6710 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6711 ) ) ;
+cby_1__1_ cby_6__1_ ( .chany_bottom_in ( sb_1__0__5_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__55_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_60_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__60_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__60_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__60_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[1] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6712 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6713 ) ,
+ .Test_en_N_out ( Test_enWires[2] ) , .Test_en_W_out ( Test_enWires[33] ) ,
+ .Test_en_E_out ( Test_enWires[35] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[216] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[217] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6714 ) ,
+ .prog_clk_2_N_in ( p2049 ) , .prog_clk_2_S_in ( p1900 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6715 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6716 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[90] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6717 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[89] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6718 ) , .clk_2_N_in ( p2049 ) ,
+ .clk_2_S_in ( p88 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6719 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6720 ) ,
+ .clk_3_S_in ( clk_3_wires[90] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6721 ) ,
+ .clk_3_N_out ( clk_3_wires[89] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6722 ) ) ;
+cby_1__1_ cby_6__2_ ( .chany_bottom_in ( sb_1__1__55_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__56_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_61_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__61_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__61_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__61_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[3] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6723 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6724 ) ,
+ .Test_en_N_out ( Test_enWires[4] ) , .Test_en_W_out ( Test_enWires[55] ) ,
+ .Test_en_E_out ( Test_enWires[57] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[219] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[220] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6725 ) ,
+ .prog_clk_2_N_in ( p2062 ) , .prog_clk_2_S_in ( p233 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6726 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6727 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[92] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6728 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[91] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6729 ) , .clk_2_N_in ( p2062 ) ,
+ .clk_2_S_in ( p995 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6730 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6731 ) ,
+ .clk_3_S_in ( clk_3_wires[92] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6732 ) ,
+ .clk_3_N_out ( clk_3_wires[91] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6733 ) ) ;
+cby_1__1_ cby_6__3_ ( .chany_bottom_in ( sb_1__1__56_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__57_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_62_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__62_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__62_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__62_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[5] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6734 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6735 ) ,
+ .Test_en_N_out ( Test_enWires[6] ) , .Test_en_W_out ( Test_enWires[77] ) ,
+ .Test_en_E_out ( Test_enWires[79] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[222] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[223] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6736 ) ,
+ .prog_clk_2_N_in ( p1707 ) , .prog_clk_2_S_in ( p144 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6737 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6738 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[94] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6739 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[93] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6740 ) , .clk_2_N_in ( p1707 ) ,
+ .clk_2_S_in ( p421 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6741 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6742 ) ,
+ .clk_3_S_in ( clk_3_wires[94] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6743 ) ,
+ .clk_3_N_out ( clk_3_wires[93] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6744 ) ) ;
+cby_1__1_ cby_6__4_ ( .chany_bottom_in ( sb_1__1__57_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__58_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_63_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__63_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__63_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__63_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[7] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6745 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6746 ) ,
+ .Test_en_N_out ( Test_enWires[8] ) , .Test_en_W_out ( Test_enWires[99] ) ,
+ .Test_en_E_out ( Test_enWires[101] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[225] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[226] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6747 ) ,
+ .prog_clk_2_N_in ( p2349 ) , .prog_clk_2_S_in ( p739 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6748 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6749 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[96] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6750 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[95] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6751 ) , .clk_2_N_in ( p2349 ) ,
+ .clk_2_S_in ( p433 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6752 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6753 ) ,
+ .clk_3_S_in ( clk_3_wires[96] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6754 ) ,
+ .clk_3_N_out ( clk_3_wires[95] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6755 ) ) ;
+cby_1__1_ cby_6__5_ ( .chany_bottom_in ( sb_1__1__58_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__59_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_64_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__64_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__64_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__64_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[9] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6756 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6757 ) ,
+ .Test_en_N_out ( Test_enWires[10] ) ,
+ .Test_en_W_out ( Test_enWires[121] ) ,
+ .Test_en_E_out ( Test_enWires[123] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[228] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[229] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6758 ) ,
+ .prog_clk_2_N_in ( p2360 ) , .prog_clk_2_S_in ( p1023 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6759 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6760 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[98] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6761 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[97] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6762 ) , .clk_2_N_in ( p2360 ) ,
+ .clk_2_S_in ( p58 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6763 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6764 ) ,
+ .clk_3_S_in ( clk_3_wires[98] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6765 ) ,
+ .clk_3_N_out ( clk_3_wires[97] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6766 ) ) ;
+cby_1__1_ cby_6__6_ ( .chany_bottom_in ( sb_1__1__59_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__60_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_65_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__65_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__65_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__65_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[11] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6767 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6768 ) ,
+ .Test_en_N_out ( Test_enWires[12] ) ,
+ .Test_en_W_out ( Test_enWires[143] ) ,
+ .Test_en_E_out ( Test_enWires[145] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[231] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[232] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6769 ) ,
+ .prog_clk_2_N_in ( p2104 ) , .prog_clk_2_S_in ( p113 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6770 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6771 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[100] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6772 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[99] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_2_N_in ( p2104 ) ,
+ .clk_2_S_in ( p1929 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6774 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6775 ) ,
+ .clk_3_S_in ( clk_3_wires[100] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6776 ) ,
+ .clk_3_N_out ( clk_3_wires[99] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6777 ) ) ;
+cby_1__1_ cby_6__7_ ( .chany_bottom_in ( sb_1__1__60_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__61_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_66_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__66_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__66_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__66_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[13] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6778 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6779 ) ,
+ .Test_en_N_out ( Test_enWires[14] ) ,
+ .Test_en_W_out ( Test_enWires[165] ) ,
+ .Test_en_E_out ( Test_enWires[167] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[234] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[235] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6780 ) ,
+ .prog_clk_2_N_in ( p2914 ) , .prog_clk_2_S_in ( p3070 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6781 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6782 ) ,
+ .prog_clk_3_S_in ( p3110 ) , .prog_clk_3_N_in ( p2801 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6783 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6784 ) , .clk_2_N_in ( p2721 ) ,
+ .clk_2_S_in ( p911 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6785 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6786 ) , .clk_3_S_in ( p1617 ) ,
+ .clk_3_N_in ( p115 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6787 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6788 ) ) ;
+cby_1__1_ cby_6__8_ ( .chany_bottom_in ( sb_1__1__61_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__62_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_67_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__67_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__67_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__67_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[15] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6789 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6790 ) ,
+ .Test_en_N_out ( Test_enWires[16] ) ,
+ .Test_en_W_out ( Test_enWires[187] ) ,
+ .Test_en_E_out ( Test_enWires[189] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[237] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[238] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6791 ) ,
+ .prog_clk_2_N_in ( p2538 ) , .prog_clk_2_S_in ( p79 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6792 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6793 ) ,
+ .prog_clk_3_S_in ( p1671 ) , .prog_clk_3_N_in ( p2636 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6794 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6795 ) , .clk_2_N_in ( p2763 ) ,
+ .clk_2_S_in ( p1013 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6796 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6797 ) , .clk_3_S_in ( p2097 ) ,
+ .clk_3_N_in ( p363 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6798 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6799 ) ) ;
+cby_1__1_ cby_6__9_ ( .chany_bottom_in ( sb_1__1__62_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__63_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_68_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__68_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__68_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__68_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[17] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6800 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6801 ) ,
+ .Test_en_N_out ( Test_enWires[18] ) ,
+ .Test_en_W_out ( Test_enWires[209] ) ,
+ .Test_en_E_out ( Test_enWires[211] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[240] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[241] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6802 ) ,
+ .prog_clk_2_N_in ( p3016 ) , .prog_clk_2_S_in ( p2802 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6803 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6804 ) ,
+ .prog_clk_3_S_in ( p2917 ) , .prog_clk_3_N_in ( p2950 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6805 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6806 ) , .clk_2_N_in ( p2394 ) ,
+ .clk_2_S_in ( p470 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6807 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6808 ) , .clk_3_S_in ( p2105 ) ,
+ .clk_3_N_in ( p1083 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6809 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6810 ) ) ;
+cby_1__1_ cby_6__10_ ( .chany_bottom_in ( sb_1__1__63_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__64_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_69_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__69_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__69_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__69_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[19] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6811 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6812 ) ,
+ .Test_en_N_out ( Test_enWires[20] ) ,
+ .Test_en_W_out ( Test_enWires[231] ) ,
+ .Test_en_E_out ( Test_enWires[233] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[243] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[244] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6813 ) ,
+ .prog_clk_2_N_in ( p2741 ) , .prog_clk_2_S_in ( p74 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6814 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6815 ) ,
+ .prog_clk_3_S_in ( p1823 ) , .prog_clk_3_N_in ( p3074 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6816 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6817 ) , .clk_2_N_in ( p3105 ) ,
+ .clk_2_S_in ( p818 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6818 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6819 ) , .clk_3_S_in ( p1592 ) ,
+ .clk_3_N_in ( p460 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6820 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6821 ) ) ;
+cby_1__1_ cby_6__11_ ( .chany_bottom_in ( sb_1__1__64_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__65_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_70_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__70_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__70_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__70_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[21] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6822 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6823 ) ,
+ .Test_en_N_out ( Test_enWires[22] ) ,
+ .Test_en_W_out ( Test_enWires[253] ) ,
+ .Test_en_E_out ( Test_enWires[255] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[246] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[247] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6824 ) ,
+ .prog_clk_2_N_in ( p3000 ) , .prog_clk_2_S_in ( p2244 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6825 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6826 ) ,
+ .prog_clk_3_S_in ( p2293 ) , .prog_clk_3_N_in ( p3178 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6827 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6828 ) , .clk_2_N_in ( p3224 ) ,
+ .clk_2_S_in ( p518 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6829 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6830 ) , .clk_3_S_in ( p1602 ) ,
+ .clk_3_N_in ( p1095 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6831 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6832 ) ) ;
+cby_1__1_ cby_6__12_ ( .chany_bottom_in ( sb_1__1__65_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_71_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__71_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__71_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__71_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[23] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6833 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6834 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6835 ) ,
+ .Test_en_W_out ( Test_enWires[275] ) ,
+ .Test_en_E_out ( Test_enWires[277] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[249] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[250] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2887 ) ,
+ .prog_clk_2_S_in ( p3082 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6836 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6837 ) ,
+ .prog_clk_3_S_in ( p3111 ) , .prog_clk_3_N_in ( p2803 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6838 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6839 ) , .clk_2_N_in ( p2726 ) ,
+ .clk_2_S_in ( p442 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6840 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6841 ) , .clk_3_S_in ( p2038 ) ,
+ .clk_3_N_in ( p675 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6842 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6843 ) ) ;
+cby_1__1_ cby_7__1_ ( .chany_bottom_in ( sb_1__0__6_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__66_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_72_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__72_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__72_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__72_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6844 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6845 ) ,
+ .Test_en_W_in ( Test_enWires[36] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6846 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6847 ) ,
+ .Test_en_E_out ( Test_enWires[37] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[254] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[255] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6848 ) ,
+ .prog_clk_2_N_in ( p2501 ) , .prog_clk_2_S_in ( p2943 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6849 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6850 ) ,
+ .prog_clk_3_S_in ( p3050 ) , .prog_clk_3_N_in ( p2961 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6851 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_2_N_in ( p3046 ) ,
+ .clk_2_S_in ( p384 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6853 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6854 ) , .clk_3_S_in ( p1682 ) ,
+ .clk_3_N_in ( p538 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6855 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6856 ) ) ;
+cby_1__1_ cby_7__2_ ( .chany_bottom_in ( sb_1__1__66_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__67_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_73_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__73_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__73_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__73_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6857 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6858 ) ,
+ .Test_en_W_in ( Test_enWires[58] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6859 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6860 ) ,
+ .Test_en_E_out ( Test_enWires[59] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[257] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[258] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6861 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[73] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6862 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[74] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6863 ) ,
+ .prog_clk_3_S_in ( p1430 ) , .prog_clk_3_N_in ( p298 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6864 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6865 ) ,
+ .clk_2_N_in ( clk_2_wires[73] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6866 ) ,
+ .clk_2_S_out ( clk_2_wires[74] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_3_S_in ( p1376 ) ,
+ .clk_3_N_in ( p1162 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6868 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6869 ) ) ;
+cby_1__1_ cby_7__3_ ( .chany_bottom_in ( sb_1__1__67_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__68_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_74_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__74_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__74_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__74_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6870 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6871 ) ,
+ .Test_en_W_in ( Test_enWires[80] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6872 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6873 ) ,
+ .Test_en_E_out ( Test_enWires[81] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[260] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[261] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6874 ) ,
+ .prog_clk_2_N_in ( p2777 ) , .prog_clk_2_S_in ( p3153 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6875 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6876 ) ,
+ .prog_clk_3_S_in ( p3206 ) , .prog_clk_3_N_in ( p2676 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6877 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6878 ) , .clk_2_N_in ( p2545 ) ,
+ .clk_2_S_in ( p509 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6879 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6880 ) , .clk_3_S_in ( p2146 ) ,
+ .clk_3_N_in ( p342 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6881 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6882 ) ) ;
+cby_1__1_ cby_7__4_ ( .chany_bottom_in ( sb_1__1__68_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__69_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_75_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__75_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__75_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__75_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6883 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6884 ) ,
+ .Test_en_W_in ( Test_enWires[102] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6885 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6886 ) ,
+ .Test_en_E_out ( Test_enWires[103] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[263] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[264] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6887 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[84] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6888 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[85] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6889 ) ,
+ .prog_clk_3_S_in ( p1815 ) , .prog_clk_3_N_in ( p1246 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6890 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6891 ) ,
+ .clk_2_N_in ( clk_2_wires[84] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6892 ) ,
+ .clk_2_S_out ( clk_2_wires[85] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6893 ) , .clk_3_S_in ( p1415 ) ,
+ .clk_3_N_in ( p33 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6894 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6895 ) ) ;
+cby_1__1_ cby_7__5_ ( .chany_bottom_in ( sb_1__1__69_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__70_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_76_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__76_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__76_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__76_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6896 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6897 ) ,
+ .Test_en_W_in ( Test_enWires[124] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6898 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6899 ) ,
+ .Test_en_E_out ( Test_enWires[125] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[266] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[267] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6900 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6901 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[82] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6902 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p1516 ) ,
+ .prog_clk_3_N_in ( p528 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6903 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6904 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6905 ) ,
+ .clk_2_S_in ( clk_2_wires[82] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6906 ) ,
+ .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p1516 ) ,
+ .clk_3_N_in ( p1079 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6907 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6908 ) ) ;
+cby_1__1_ cby_7__6_ ( .chany_bottom_in ( sb_1__1__70_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__71_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_77_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__77_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__77_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__77_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6909 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6910 ) ,
+ .Test_en_W_in ( Test_enWires[146] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6911 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6912 ) ,
+ .Test_en_E_out ( Test_enWires[147] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[269] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[270] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6913 ) ,
+ .prog_clk_2_N_in ( p2598 ) , .prog_clk_2_S_in ( p2806 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6914 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6915 ) ,
+ .prog_clk_3_S_in ( p2911 ) , .prog_clk_3_N_in ( p3456 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6916 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6917 ) , .clk_2_N_in ( p3465 ) ,
+ .clk_2_S_in ( p763 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6918 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6919 ) , .clk_3_S_in ( p2045 ) ,
+ .clk_3_N_in ( p1217 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6920 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6921 ) ) ;
+cby_1__1_ cby_7__7_ ( .chany_bottom_in ( sb_1__1__71_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__72_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_78_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__78_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__78_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__78_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6922 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6923 ) ,
+ .Test_en_W_in ( Test_enWires[168] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6924 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6925 ) ,
+ .Test_en_E_out ( Test_enWires[169] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[272] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[273] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6926 ) ,
+ .prog_clk_2_N_in ( p3027 ) , .prog_clk_2_S_in ( p2203 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6927 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6928 ) ,
+ .prog_clk_3_S_in ( p2299 ) , .prog_clk_3_N_in ( p2968 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6929 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6930 ) , .clk_2_N_in ( p3029 ) ,
+ .clk_2_S_in ( p596 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6931 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6932 ) , .clk_3_S_in ( p1838 ) ,
+ .clk_3_N_in ( p821 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6933 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6934 ) ) ;
+cby_1__1_ cby_7__8_ ( .chany_bottom_in ( sb_1__1__72_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__73_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_79_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__79_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__79_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__79_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6935 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6936 ) ,
+ .Test_en_W_in ( Test_enWires[190] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6937 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6938 ) ,
+ .Test_en_E_out ( Test_enWires[191] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[275] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[276] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6939 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[97] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6940 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[98] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6941 ) ,
+ .prog_clk_3_S_in ( p1784 ) , .prog_clk_3_N_in ( p627 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6942 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6943 ) ,
+ .clk_2_N_in ( clk_2_wires[97] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6944 ) ,
+ .clk_2_S_out ( clk_2_wires[98] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6945 ) , .clk_3_S_in ( p2129 ) ,
+ .clk_3_N_in ( p1116 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6946 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6947 ) ) ;
+cby_1__1_ cby_7__9_ ( .chany_bottom_in ( sb_1__1__73_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__74_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_80_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__80_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__80_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__80_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6948 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6949 ) ,
+ .Test_en_W_in ( Test_enWires[212] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6950 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6951 ) ,
+ .Test_en_E_out ( Test_enWires[213] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[278] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[279] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6952 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6953 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[95] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6954 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p2172 ) ,
+ .prog_clk_3_N_in ( p386 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6955 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6956 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6957 ) ,
+ .clk_2_S_in ( clk_2_wires[95] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6958 ) ,
+ .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p2009 ) ,
+ .clk_3_N_in ( p1169 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6959 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6960 ) ) ;
+cby_1__1_ cby_7__10_ ( .chany_bottom_in ( sb_1__1__74_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__75_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_81_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__81_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__81_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__81_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6961 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6962 ) ,
+ .Test_en_W_in ( Test_enWires[234] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6963 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6964 ) ,
+ .Test_en_E_out ( Test_enWires[235] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[281] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[282] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6965 ) ,
+ .prog_clk_2_N_in ( p3332 ) , .prog_clk_2_S_in ( p2224 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6966 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6967 ) ,
+ .prog_clk_3_S_in ( p2352 ) , .prog_clk_3_N_in ( p3310 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6968 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6969 ) , .clk_2_N_in ( p3005 ) ,
+ .clk_2_S_in ( p922 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6970 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6971 ) , .clk_3_S_in ( p2346 ) ,
+ .clk_3_N_in ( p537 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6972 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6973 ) ) ;
+cby_1__1_ cby_7__11_ ( .chany_bottom_in ( sb_1__1__75_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__76_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_82_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__82_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__82_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__82_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6974 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6975 ) ,
+ .Test_en_W_in ( Test_enWires[256] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6976 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6977 ) ,
+ .Test_en_E_out ( Test_enWires[257] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[284] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[285] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6978 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6979 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[108] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6980 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1831 ) ,
+ .prog_clk_3_N_in ( p691 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6981 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6982 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6983 ) ,
+ .clk_2_S_in ( clk_2_wires[108] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6984 ) ,
+ .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p2341 ) ,
+ .clk_3_N_in ( p875 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6985 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6986 ) ) ;
+cby_1__1_ cby_7__12_ ( .chany_bottom_in ( sb_1__1__76_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_83_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__83_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__83_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__83_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6987 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6988 ) ,
+ .Test_en_W_in ( Test_enWires[278] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6989 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6990 ) ,
+ .Test_en_E_out ( Test_enWires[279] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[287] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[288] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p3293 ) ,
+ .prog_clk_2_S_in ( p2491 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6991 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6992 ) ,
+ .prog_clk_3_S_in ( p2582 ) , .prog_clk_3_N_in ( p3244 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6993 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6994 ) , .clk_2_N_in ( p2778 ) ,
+ .clk_2_S_in ( p660 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6995 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6996 ) , .clk_3_S_in ( p1830 ) ,
+ .clk_3_N_in ( p996 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6997 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6998 ) ) ;
+cby_1__1_ cby_8__1_ ( .chany_bottom_in ( sb_1__0__7_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__77_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_84_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__84_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__84_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__84_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6999 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7000 ) ,
+ .Test_en_W_in ( Test_enWires[38] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7001 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7002 ) ,
+ .Test_en_E_out ( Test_enWires[39] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[292] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[293] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7003 ) ,
+ .prog_clk_2_N_in ( p3386 ) , .prog_clk_2_S_in ( p3077 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7004 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7005 ) ,
+ .prog_clk_3_S_in ( p3107 ) , .prog_clk_3_N_in ( p3359 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7006 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7007 ) , .clk_2_N_in ( p2106 ) ,
+ .clk_2_S_in ( p2685 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7008 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7009 ) , .clk_3_S_in ( p2746 ) ,
+ .clk_3_N_in ( p801 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7010 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7011 ) ) ;
+cby_1__1_ cby_8__2_ ( .chany_bottom_in ( sb_1__1__77_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__78_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_85_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__85_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__85_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__85_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7012 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7013 ) ,
+ .Test_en_W_in ( Test_enWires[60] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7014 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7015 ) ,
+ .Test_en_E_out ( Test_enWires[61] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[295] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[296] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7016 ) ,
+ .prog_clk_2_N_in ( p3193 ) , .prog_clk_2_S_in ( p979 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7017 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7018 ) ,
+ .prog_clk_3_S_in ( p1713 ) , .prog_clk_3_N_in ( p3176 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7019 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7020 ) , .clk_2_N_in ( p2918 ) ,
+ .clk_2_S_in ( p34 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7021 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7022 ) , .clk_3_S_in ( p1856 ) ,
+ .clk_3_N_in ( p710 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7023 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7024 ) ) ;
+cby_1__1_ cby_8__3_ ( .chany_bottom_in ( sb_1__1__78_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__79_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_86_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__86_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__86_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__86_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7025 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7026 ) ,
+ .Test_en_W_in ( Test_enWires[82] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7027 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7028 ) ,
+ .Test_en_E_out ( Test_enWires[83] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[298] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[299] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7029 ) ,
+ .prog_clk_2_N_in ( p2085 ) , .prog_clk_2_S_in ( p146 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7030 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7031 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7032 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[42] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7033 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p2085 ) ,
+ .clk_2_S_in ( p468 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7034 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7035 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7036 ) ,
+ .clk_3_N_in ( clk_3_wires[42] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7037 ) ,
+ .clk_3_S_out ( clk_3_wires[43] ) ) ;
+cby_1__1_ cby_8__4_ ( .chany_bottom_in ( sb_1__1__79_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__80_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_87_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__87_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__87_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__87_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7038 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7039 ) ,
+ .Test_en_W_in ( Test_enWires[104] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7040 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7041 ) ,
+ .Test_en_E_out ( Test_enWires[105] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[301] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[302] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7042 ) ,
+ .prog_clk_2_N_in ( p1225 ) , .prog_clk_2_S_in ( p243 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7043 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7044 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7045 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[38] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7046 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1225 ) ,
+ .clk_2_S_in ( p1893 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7047 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7048 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7049 ) ,
+ .clk_3_N_in ( clk_3_wires[38] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7050 ) ,
+ .clk_3_S_out ( clk_3_wires[39] ) ) ;
+cby_1__1_ cby_8__5_ ( .chany_bottom_in ( sb_1__1__80_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__81_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_88_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__88_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__88_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__88_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7051 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7052 ) ,
+ .Test_en_W_in ( Test_enWires[126] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7053 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7054 ) ,
+ .Test_en_E_out ( Test_enWires[127] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[304] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[305] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7055 ) ,
+ .prog_clk_2_N_in ( p1873 ) , .prog_clk_2_S_in ( p143 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7056 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7057 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7058 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[32] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7059 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p1873 ) ,
+ .clk_2_S_in ( p1918 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7060 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7061 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7062 ) ,
+ .clk_3_N_in ( clk_3_wires[32] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7063 ) ,
+ .clk_3_S_out ( clk_3_wires[33] ) ) ;
+cby_1__1_ cby_8__6_ ( .chany_bottom_in ( sb_1__1__81_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__82_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_89_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__89_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__89_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__89_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7064 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7065 ) ,
+ .Test_en_W_in ( Test_enWires[148] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7066 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7067 ) ,
+ .Test_en_E_out ( Test_enWires[149] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[307] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[308] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7068 ) ,
+ .prog_clk_2_N_in ( p2287 ) , .prog_clk_2_S_in ( p474 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7069 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7070 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7071 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[28] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7072 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p2381 ) ,
+ .clk_2_S_in ( p1004 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7073 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7074 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7075 ) ,
+ .clk_3_N_in ( clk_3_wires[28] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7076 ) ,
+ .clk_3_S_out ( clk_3_wires[29] ) ) ;
+cby_1__1_ cby_8__7_ ( .chany_bottom_in ( sb_1__1__82_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__83_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_90_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__90_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__90_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__90_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7077 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7078 ) ,
+ .Test_en_W_in ( Test_enWires[170] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7079 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7080 ) ,
+ .Test_en_E_out ( Test_enWires[171] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[310] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[311] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7081 ) ,
+ .prog_clk_2_N_in ( p2584 ) , .prog_clk_2_S_in ( p292 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7082 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7083 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[26] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7084 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[27] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7085 ) , .clk_2_N_in ( p2508 ) ,
+ .clk_2_S_in ( p1051 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7086 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7087 ) ,
+ .clk_3_S_in ( clk_3_wires[26] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7088 ) ,
+ .clk_3_N_out ( clk_3_wires[27] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7089 ) ) ;
+cby_1__1_ cby_8__8_ ( .chany_bottom_in ( sb_1__1__83_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__84_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_91_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__91_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__91_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__91_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7090 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7091 ) ,
+ .Test_en_W_in ( Test_enWires[192] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7092 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7093 ) ,
+ .Test_en_E_out ( Test_enWires[193] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[313] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[314] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7094 ) ,
+ .prog_clk_2_N_in ( p1586 ) , .prog_clk_2_S_in ( p469 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7095 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7096 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[30] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7097 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[31] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7098 ) , .clk_2_N_in ( p1586 ) ,
+ .clk_2_S_in ( p980 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7099 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7100 ) ,
+ .clk_3_S_in ( clk_3_wires[30] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7101 ) ,
+ .clk_3_N_out ( clk_3_wires[31] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7102 ) ) ;
+cby_1__1_ cby_8__9_ ( .chany_bottom_in ( sb_1__1__84_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__85_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_92_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__92_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__92_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__92_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7103 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7104 ) ,
+ .Test_en_W_in ( Test_enWires[214] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7105 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7106 ) ,
+ .Test_en_E_out ( Test_enWires[215] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[316] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[317] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7107 ) ,
+ .prog_clk_2_N_in ( p1645 ) , .prog_clk_2_S_in ( p388 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7108 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7109 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[36] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7110 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[37] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7111 ) , .clk_2_N_in ( p1645 ) ,
+ .clk_2_S_in ( p1033 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7112 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7113 ) ,
+ .clk_3_S_in ( clk_3_wires[36] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7114 ) ,
+ .clk_3_N_out ( clk_3_wires[37] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7115 ) ) ;
+cby_1__1_ cby_8__10_ ( .chany_bottom_in ( sb_1__1__85_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__86_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_93_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__93_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__93_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__93_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7116 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7117 ) ,
+ .Test_en_W_in ( Test_enWires[236] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7118 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7119 ) ,
+ .Test_en_E_out ( Test_enWires[237] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[319] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[320] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7120 ) ,
+ .prog_clk_2_N_in ( p1850 ) , .prog_clk_2_S_in ( p1141 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7121 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7122 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[40] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7123 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[41] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7124 ) , .clk_2_N_in ( p1695 ) ,
+ .clk_2_S_in ( p313 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7125 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7126 ) ,
+ .clk_3_S_in ( clk_3_wires[40] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7127 ) ,
+ .clk_3_N_out ( clk_3_wires[41] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7128 ) ) ;
+cby_1__1_ cby_8__11_ ( .chany_bottom_in ( sb_1__1__86_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__87_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_94_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__94_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__94_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__94_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7129 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7130 ) ,
+ .Test_en_W_in ( Test_enWires[258] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7131 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7132 ) ,
+ .Test_en_E_out ( Test_enWires[259] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[322] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[323] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7133 ) ,
+ .prog_clk_2_N_in ( p2733 ) , .prog_clk_2_S_in ( p3184 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7134 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7135 ) ,
+ .prog_clk_3_S_in ( p3198 ) , .prog_clk_3_N_in ( p2661 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7136 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7137 ) , .clk_2_N_in ( p2754 ) ,
+ .clk_2_S_in ( p473 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7138 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7139 ) , .clk_3_S_in ( p2301 ) ,
+ .clk_3_N_in ( p1151 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7140 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7141 ) ) ;
+cby_1__1_ cby_8__12_ ( .chany_bottom_in ( sb_1__1__87_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_95_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__95_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__95_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__95_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7142 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7143 ) ,
+ .Test_en_W_in ( Test_enWires[280] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7144 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7145 ) ,
+ .Test_en_E_out ( Test_enWires[281] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[325] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[326] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p3103 ) ,
+ .prog_clk_2_S_in ( p2650 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7146 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7147 ) ,
+ .prog_clk_3_S_in ( p2740 ) , .prog_clk_3_N_in ( p3063 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7148 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7149 ) , .clk_2_N_in ( p2888 ) ,
+ .clk_2_S_in ( p712 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7150 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_3_S_in ( p1451 ) ,
+ .clk_3_N_in ( p35 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7152 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7153 ) ) ;
+cby_1__1_ cby_9__1_ ( .chany_bottom_in ( sb_1__0__8_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__88_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_96_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__96_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__96_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__96_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7154 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7155 ) ,
+ .Test_en_W_in ( Test_enWires[40] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7156 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7157 ) ,
+ .Test_en_E_out ( Test_enWires[41] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[330] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[331] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7158 ) ,
+ .prog_clk_2_N_in ( p3220 ) , .prog_clk_2_S_in ( p2827 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7159 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7160 ) ,
+ .prog_clk_3_S_in ( p2869 ) , .prog_clk_3_N_in ( p3169 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7161 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7162 ) , .clk_2_N_in ( p2705 ) ,
+ .clk_2_S_in ( p72 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7163 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7164 ) , .clk_3_S_in ( p1813 ) ,
+ .clk_3_N_in ( p616 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7165 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7166 ) ) ;
+cby_1__1_ cby_9__2_ ( .chany_bottom_in ( sb_1__1__88_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__89_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_97_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__97_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__97_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__97_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7167 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7168 ) ,
+ .Test_en_W_in ( Test_enWires[62] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7169 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7170 ) ,
+ .Test_en_E_out ( Test_enWires[63] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[333] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[334] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7171 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[75] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7172 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[76] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7173 ) ,
+ .prog_clk_3_S_in ( p1998 ) , .prog_clk_3_N_in ( p1327 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7174 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7175 ) ,
+ .clk_2_N_in ( clk_2_wires[75] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7176 ) ,
+ .clk_2_S_out ( clk_2_wires[76] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7177 ) , .clk_3_S_in ( p1998 ) ,
+ .clk_3_N_in ( p713 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7178 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7179 ) ) ;
+cby_1__1_ cby_9__3_ ( .chany_bottom_in ( sb_1__1__89_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__90_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_98_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__98_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__98_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__98_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7180 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7181 ) ,
+ .Test_en_W_in ( Test_enWires[84] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7182 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7183 ) ,
+ .Test_en_E_out ( Test_enWires[85] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[336] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[337] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7184 ) ,
+ .prog_clk_2_N_in ( p3229 ) , .prog_clk_2_S_in ( p3236 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7185 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7186 ) ,
+ .prog_clk_3_S_in ( p3282 ) , .prog_clk_3_N_in ( p3188 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7187 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7188 ) , .clk_2_N_in ( p3098 ) ,
+ .clk_2_S_in ( p351 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7189 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7190 ) , .clk_3_S_in ( p2370 ) ,
+ .clk_3_N_in ( p1315 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7191 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7192 ) ) ;
+cby_1__1_ cby_9__4_ ( .chany_bottom_in ( sb_1__1__90_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__91_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_99_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__99_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__99_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__99_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7193 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7194 ) ,
+ .Test_en_W_in ( Test_enWires[106] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7195 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7196 ) ,
+ .Test_en_E_out ( Test_enWires[107] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[339] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[340] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7197 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[88] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7198 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[89] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7199 ) ,
+ .prog_clk_3_S_in ( p793 ) , .prog_clk_3_N_in ( p1041 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7200 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7201 ) ,
+ .clk_2_N_in ( clk_2_wires[88] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7202 ) ,
+ .clk_2_S_out ( clk_2_wires[89] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7203 ) , .clk_3_S_in ( p1603 ) ,
+ .clk_3_N_in ( p66 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7204 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7205 ) ) ;
+cby_1__1_ cby_9__5_ ( .chany_bottom_in ( sb_1__1__91_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__92_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_100_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__100_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__100_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__100_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7206 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7207 ) ,
+ .Test_en_W_in ( Test_enWires[128] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7208 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7209 ) ,
+ .Test_en_E_out ( Test_enWires[129] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[342] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[343] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7210 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7211 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[86] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7212 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p1479 ) ,
+ .prog_clk_3_N_in ( p1179 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7213 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7214 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7215 ) ,
+ .clk_2_S_in ( clk_2_wires[86] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7216 ) ,
+ .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p1479 ) ,
+ .clk_3_N_in ( p15 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7217 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7218 ) ) ;
+cby_1__1_ cby_9__6_ ( .chany_bottom_in ( sb_1__1__92_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__93_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_101_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__101_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__101_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__101_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7219 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7220 ) ,
+ .Test_en_W_in ( Test_enWires[150] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7221 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7222 ) ,
+ .Test_en_E_out ( Test_enWires[151] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[345] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[346] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7223 ) ,
+ .prog_clk_2_N_in ( p3109 ) , .prog_clk_2_S_in ( p2946 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7224 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7225 ) ,
+ .prog_clk_3_S_in ( p3002 ) , .prog_clk_3_N_in ( p3080 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7226 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7227 ) , .clk_2_N_in ( p2585 ) ,
+ .clk_2_S_in ( p440 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7228 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7229 ) , .clk_3_S_in ( p2717 ) ,
+ .clk_3_N_in ( p1233 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7230 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7231 ) ) ;
+cby_1__1_ cby_9__7_ ( .chany_bottom_in ( sb_1__1__93_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__94_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_102_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__102_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__102_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__102_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7232 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7233 ) ,
+ .Test_en_W_in ( Test_enWires[172] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7234 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7235 ) ,
+ .Test_en_E_out ( Test_enWires[173] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[348] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[349] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7236 ) ,
+ .prog_clk_2_N_in ( p3297 ) , .prog_clk_2_S_in ( p2954 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7237 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7238 ) ,
+ .prog_clk_3_S_in ( p3019 ) , .prog_clk_3_N_in ( p3356 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7239 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7240 ) , .clk_2_N_in ( p3377 ) ,
+ .clk_2_S_in ( p522 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7241 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7242 ) , .clk_3_S_in ( p1852 ) ,
+ .clk_3_N_in ( p632 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7243 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7244 ) ) ;
+cby_1__1_ cby_9__8_ ( .chany_bottom_in ( sb_1__1__94_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__95_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_103_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__103_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__103_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__103_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7245 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7246 ) ,
+ .Test_en_W_in ( Test_enWires[194] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7247 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7248 ) ,
+ .Test_en_E_out ( Test_enWires[195] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[351] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[352] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7249 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[101] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7250 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[102] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7251 ) ,
+ .prog_clk_3_S_in ( p1624 ) , .prog_clk_3_N_in ( p69 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7252 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7253 ) ,
+ .clk_2_N_in ( clk_2_wires[101] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7254 ) ,
+ .clk_2_S_out ( clk_2_wires[102] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7255 ) , .clk_3_S_in ( p2515 ) ,
+ .clk_3_N_in ( p1258 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7256 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7257 ) ) ;
+cby_1__1_ cby_9__9_ ( .chany_bottom_in ( sb_1__1__95_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__96_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_104_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__104_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__104_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__104_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7258 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7259 ) ,
+ .Test_en_W_in ( Test_enWires[216] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7260 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7261 ) ,
+ .Test_en_E_out ( Test_enWires[217] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[354] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[355] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7262 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7263 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[99] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7264 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1757 ) ,
+ .prog_clk_3_N_in ( p479 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7265 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7266 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7267 ) ,
+ .clk_2_S_in ( clk_2_wires[99] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7268 ) ,
+ .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1987 ) ,
+ .clk_3_N_in ( p562 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7269 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7270 ) ) ;
+cby_1__1_ cby_9__10_ ( .chany_bottom_in ( sb_1__1__96_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__97_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_105_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__105_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__105_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__105_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7271 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7272 ) ,
+ .Test_en_W_in ( Test_enWires[238] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7273 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7274 ) ,
+ .Test_en_E_out ( Test_enWires[239] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[357] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[358] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7275 ) ,
+ .prog_clk_2_N_in ( p3119 ) , .prog_clk_2_S_in ( p3255 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7276 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7277 ) ,
+ .prog_clk_3_S_in ( p3295 ) , .prog_clk_3_N_in ( p3307 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7278 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_2_N_in ( p3335 ) ,
+ .clk_2_S_in ( p251 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7280 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_3_S_in ( p2547 ) ,
+ .clk_3_N_in ( p294 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7282 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7283 ) ) ;
+cby_1__1_ cby_9__11_ ( .chany_bottom_in ( sb_1__1__97_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__98_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_106_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__106_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__106_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__106_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7284 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7285 ) ,
+ .Test_en_W_in ( Test_enWires[260] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7286 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7287 ) ,
+ .Test_en_E_out ( Test_enWires[261] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[360] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[361] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7288 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7289 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[110] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7290 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1880 ) ,
+ .prog_clk_3_N_in ( p819 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7291 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7292 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7293 ) ,
+ .clk_2_S_in ( clk_2_wires[110] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7294 ) ,
+ .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p2760 ) ,
+ .clk_3_N_in ( p829 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7295 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7296 ) ) ;
+cby_1__1_ cby_9__12_ ( .chany_bottom_in ( sb_1__1__98_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_107_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__107_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__107_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__107_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7297 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7298 ) ,
+ .Test_en_W_in ( Test_enWires[282] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7299 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7300 ) ,
+ .Test_en_E_out ( Test_enWires[283] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[363] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[364] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p2021 ) ,
+ .prog_clk_2_S_in ( p2473 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7301 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7302 ) ,
+ .prog_clk_3_S_in ( p2525 ) , .prog_clk_3_N_in ( p2814 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7303 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7304 ) , .clk_2_N_in ( p2916 ) ,
+ .clk_2_S_in ( p619 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7305 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7306 ) , .clk_3_S_in ( p1693 ) ,
+ .clk_3_N_in ( p816 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7307 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7308 ) ) ;
+cby_1__1_ cby_10__1_ ( .chany_bottom_in ( sb_1__0__9_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__99_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_108_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__108_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__108_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__108_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7309 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7310 ) ,
+ .Test_en_W_in ( Test_enWires[42] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7311 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7312 ) ,
+ .Test_en_E_out ( Test_enWires[43] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[368] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[369] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7313 ) ,
+ .prog_clk_2_N_in ( p3281 ) , .prog_clk_2_S_in ( p1891 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7314 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7315 ) ,
+ .prog_clk_3_S_in ( p1740 ) , .prog_clk_3_N_in ( p3239 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7316 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7317 ) , .clk_2_N_in ( p2766 ) ,
+ .clk_2_S_in ( p1988 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7318 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7319 ) , .clk_3_S_in ( p1996 ) ,
+ .clk_3_N_in ( p752 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7320 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7321 ) ) ;
+cby_1__1_ cby_10__2_ ( .chany_bottom_in ( sb_1__1__99_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__100_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_109_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__109_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__109_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__109_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7322 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7323 ) ,
+ .Test_en_W_in ( Test_enWires[64] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7324 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7325 ) ,
+ .Test_en_E_out ( Test_enWires[65] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[371] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[372] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7326 ) ,
+ .prog_clk_2_N_in ( p3133 ) , .prog_clk_2_S_in ( p2218 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7327 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7328 ) ,
+ .prog_clk_3_S_in ( p2395 ) , .prog_clk_3_N_in ( p3060 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7329 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7330 ) , .clk_2_N_in ( p2886 ) ,
+ .clk_2_S_in ( p1018 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7331 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7332 ) , .clk_3_S_in ( p2043 ) ,
+ .clk_3_N_in ( p985 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7333 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7334 ) ) ;
+cby_1__1_ cby_10__3_ ( .chany_bottom_in ( sb_1__1__100_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__101_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_110_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__110_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__110_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__110_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7335 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7336 ) ,
+ .Test_en_W_in ( Test_enWires[86] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7337 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7338 ) ,
+ .Test_en_E_out ( Test_enWires[87] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[374] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[375] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7339 ) ,
+ .prog_clk_2_N_in ( p2093 ) , .prog_clk_2_S_in ( p506 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7340 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7341 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7342 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[86] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7343 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p2093 ) ,
+ .clk_2_S_in ( p171 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7344 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7345 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7346 ) ,
+ .clk_3_N_in ( clk_3_wires[86] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7347 ) ,
+ .clk_3_S_out ( clk_3_wires[87] ) ) ;
+cby_1__1_ cby_10__4_ ( .chany_bottom_in ( sb_1__1__101_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__102_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_111_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__111_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__111_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__111_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7348 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7349 ) ,
+ .Test_en_W_in ( Test_enWires[108] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7350 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7351 ) ,
+ .Test_en_E_out ( Test_enWires[109] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[377] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[378] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7352 ) ,
+ .prog_clk_2_N_in ( p1557 ) , .prog_clk_2_S_in ( p487 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7353 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7354 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7355 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[82] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7356 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( p1557 ) ,
+ .clk_2_S_in ( p597 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7357 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7358 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7359 ) ,
+ .clk_3_N_in ( clk_3_wires[82] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7360 ) ,
+ .clk_3_S_out ( clk_3_wires[83] ) ) ;
+cby_1__1_ cby_10__5_ ( .chany_bottom_in ( sb_1__1__102_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__103_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_112_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__112_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__112_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__112_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7361 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7362 ) ,
+ .Test_en_W_in ( Test_enWires[130] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7363 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7364 ) ,
+ .Test_en_E_out ( Test_enWires[131] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[380] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[381] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7365 ) ,
+ .prog_clk_2_N_in ( p1875 ) , .prog_clk_2_S_in ( p717 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7366 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7367 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7368 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[76] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7369 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1875 ) ,
+ .clk_2_S_in ( p186 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7370 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7371 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7372 ) ,
+ .clk_3_N_in ( clk_3_wires[76] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7373 ) ,
+ .clk_3_S_out ( clk_3_wires[77] ) ) ;
+cby_1__1_ cby_10__6_ ( .chany_bottom_in ( sb_1__1__103_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__104_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_113_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__113_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__113_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__113_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7374 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7375 ) ,
+ .Test_en_W_in ( Test_enWires[152] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7376 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7377 ) ,
+ .Test_en_E_out ( Test_enWires[153] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[383] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[384] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7378 ) ,
+ .prog_clk_2_N_in ( p2389 ) , .prog_clk_2_S_in ( p1283 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7379 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7380 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7381 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[72] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7382 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p2389 ) ,
+ .clk_2_S_in ( p478 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7383 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7384 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7385 ) ,
+ .clk_3_N_in ( clk_3_wires[72] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7386 ) ,
+ .clk_3_S_out ( clk_3_wires[73] ) ) ;
+cby_1__1_ cby_10__7_ ( .chany_bottom_in ( sb_1__1__104_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__105_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_114_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__114_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__114_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__114_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7387 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7388 ) ,
+ .Test_en_W_in ( Test_enWires[174] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7389 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7390 ) ,
+ .Test_en_E_out ( Test_enWires[175] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[386] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[387] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7391 ) ,
+ .prog_clk_2_N_in ( p2420 ) , .prog_clk_2_S_in ( p741 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7392 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7393 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[70] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7394 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[71] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7395 ) , .clk_2_N_in ( p2420 ) ,
+ .clk_2_S_in ( p308 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7396 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7397 ) ,
+ .clk_3_S_in ( clk_3_wires[70] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7398 ) ,
+ .clk_3_N_out ( clk_3_wires[71] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7399 ) ) ;
+cby_1__1_ cby_10__8_ ( .chany_bottom_in ( sb_1__1__105_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__106_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_115_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__115_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__115_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__115_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7400 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7401 ) ,
+ .Test_en_W_in ( Test_enWires[196] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7402 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7403 ) ,
+ .Test_en_E_out ( Test_enWires[197] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[389] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[390] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7404 ) ,
+ .prog_clk_2_N_in ( p1825 ) , .prog_clk_2_S_in ( p1177 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7405 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7406 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[74] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7407 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[75] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7408 ) , .clk_2_N_in ( p1774 ) ,
+ .clk_2_S_in ( p345 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7409 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7410 ) ,
+ .clk_3_S_in ( clk_3_wires[74] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7411 ) ,
+ .clk_3_N_out ( clk_3_wires[75] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7412 ) ) ;
+cby_1__1_ cby_10__9_ ( .chany_bottom_in ( sb_1__1__106_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__107_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_116_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__116_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__116_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__116_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7413 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7414 ) ,
+ .Test_en_W_in ( Test_enWires[218] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7415 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7416 ) ,
+ .Test_en_E_out ( Test_enWires[219] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[392] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[393] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7417 ) ,
+ .prog_clk_2_N_in ( p2094 ) , .prog_clk_2_S_in ( p260 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7418 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7419 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[80] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7420 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[81] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7421 ) , .clk_2_N_in ( p2094 ) ,
+ .clk_2_S_in ( p907 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7422 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7423 ) ,
+ .clk_3_S_in ( clk_3_wires[80] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7424 ) ,
+ .clk_3_N_out ( clk_3_wires[81] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7425 ) ) ;
+cby_1__1_ cby_10__10_ ( .chany_bottom_in ( sb_1__1__107_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__108_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_117_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__117_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__117_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__117_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7426 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7427 ) ,
+ .Test_en_W_in ( Test_enWires[240] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7428 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7429 ) ,
+ .Test_en_E_out ( Test_enWires[241] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[395] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[396] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7430 ) ,
+ .prog_clk_2_N_in ( p1606 ) , .prog_clk_2_S_in ( p77 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7431 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7432 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[84] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7433 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[85] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7434 ) , .clk_2_N_in ( p1606 ) ,
+ .clk_2_S_in ( p770 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7435 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7436 ) ,
+ .clk_3_S_in ( clk_3_wires[84] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7437 ) ,
+ .clk_3_N_out ( clk_3_wires[85] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7438 ) ) ;
+cby_1__1_ cby_10__11_ ( .chany_bottom_in ( sb_1__1__108_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__109_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_118_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__118_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__118_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__118_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7439 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7440 ) ,
+ .Test_en_W_in ( Test_enWires[262] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7441 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7442 ) ,
+ .Test_en_E_out ( Test_enWires[263] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[398] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[399] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7443 ) ,
+ .prog_clk_2_N_in ( p2865 ) , .prog_clk_2_S_in ( p2687 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7444 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7445 ) ,
+ .prog_clk_3_S_in ( p2718 ) , .prog_clk_3_N_in ( p2851 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7446 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7447 ) , .clk_2_N_in ( p2907 ) ,
+ .clk_2_S_in ( p936 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7448 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7449 ) , .clk_3_S_in ( p2142 ) ,
+ .clk_3_N_in ( p560 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7450 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7451 ) ) ;
+cby_1__1_ cby_10__12_ ( .chany_bottom_in ( sb_1__1__109_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_119_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__119_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__119_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__119_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7452 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7453 ) ,
+ .Test_en_W_in ( Test_enWires[284] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7454 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7455 ) ,
+ .Test_en_E_out ( Test_enWires[285] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[401] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[402] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p3108 ) ,
+ .prog_clk_2_S_in ( p3093 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7456 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7457 ) ,
+ .prog_clk_3_S_in ( p3128 ) , .prog_clk_3_N_in ( p3056 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7458 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7459 ) , .clk_2_N_in ( p2882 ) ,
+ .clk_2_S_in ( p134 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7460 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7461 ) , .clk_3_S_in ( p2533 ) ,
+ .clk_3_N_in ( p322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7462 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7463 ) ) ;
+cby_1__1_ cby_11__1_ ( .chany_bottom_in ( sb_1__0__10_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__110_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_120_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__120_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__120_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__120_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7464 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7465 ) ,
+ .Test_en_W_in ( Test_enWires[44] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7466 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7467 ) ,
+ .Test_en_E_out ( Test_enWires[45] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[406] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[407] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7468 ) ,
+ .prog_clk_2_N_in ( p3126 ) , .prog_clk_2_S_in ( p2647 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7469 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7470 ) ,
+ .prog_clk_3_S_in ( p2762 ) , .prog_clk_3_N_in ( p3258 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7471 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7472 ) , .clk_2_N_in ( p3277 ) ,
+ .clk_2_S_in ( p2185 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7473 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7474 ) , .clk_3_S_in ( p2390 ) ,
+ .clk_3_N_in ( p1306 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7475 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7476 ) ) ;
+cby_1__1_ cby_11__2_ ( .chany_bottom_in ( sb_1__1__110_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__111_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_121_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__121_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__121_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__121_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7477 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7478 ) ,
+ .Test_en_W_in ( Test_enWires[66] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7479 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7480 ) ,
+ .Test_en_E_out ( Test_enWires[67] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[409] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[410] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7481 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[115] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7482 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[116] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7483 ) ,
+ .prog_clk_3_S_in ( p1674 ) , .prog_clk_3_N_in ( p1087 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7484 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7485 ) ,
+ .clk_2_N_in ( clk_2_wires[115] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7486 ) ,
+ .clk_2_S_out ( clk_2_wires[116] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7487 ) , .clk_3_S_in ( p2397 ) ,
+ .clk_3_N_in ( p464 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7488 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7489 ) ) ;
+cby_1__1_ cby_11__3_ ( .chany_bottom_in ( sb_1__1__111_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__112_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_122_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__122_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__122_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__122_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7490 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7491 ) ,
+ .Test_en_W_in ( Test_enWires[88] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7492 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7493 ) ,
+ .Test_en_E_out ( Test_enWires[89] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[412] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[413] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7494 ) ,
+ .prog_clk_2_N_in ( p2895 ) , .prog_clk_2_S_in ( p2659 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7495 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7496 ) ,
+ .prog_clk_3_S_in ( p2749 ) , .prog_clk_3_N_in ( p2964 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7497 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7498 ) , .clk_2_N_in ( p2998 ) ,
+ .clk_2_S_in ( p45 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7499 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7500 ) , .clk_3_S_in ( p2055 ) ,
+ .clk_3_N_in ( p1249 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7501 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7502 ) ) ;
+cby_1__1_ cby_11__4_ ( .chany_bottom_in ( sb_1__1__112_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__113_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_123_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__123_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__123_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__123_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7503 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7504 ) ,
+ .Test_en_W_in ( Test_enWires[110] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7505 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7506 ) ,
+ .Test_en_E_out ( Test_enWires[111] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[415] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[416] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7507 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[122] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7508 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[123] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7509 ) ,
+ .prog_clk_3_S_in ( p1634 ) , .prog_clk_3_N_in ( p724 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7510 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7511 ) ,
+ .clk_2_N_in ( clk_2_wires[122] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7512 ) ,
+ .clk_2_S_out ( clk_2_wires[123] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7513 ) , .clk_3_S_in ( p2334 ) ,
+ .clk_3_N_in ( p316 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7514 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7515 ) ) ;
+cby_1__1_ cby_11__5_ ( .chany_bottom_in ( sb_1__1__113_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__114_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_124_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__124_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__124_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__124_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7516 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7517 ) ,
+ .Test_en_W_in ( Test_enWires[132] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7518 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7519 ) ,
+ .Test_en_E_out ( Test_enWires[133] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[418] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[419] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7520 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7521 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[120] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7522 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1700 ) ,
+ .prog_clk_3_N_in ( p1053 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7523 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7524 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7525 ) ,
+ .clk_2_S_in ( clk_2_wires[120] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7526 ) ,
+ .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1700 ) ,
+ .clk_3_N_in ( p548 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7527 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7528 ) ) ;
+cby_1__1_ cby_11__6_ ( .chany_bottom_in ( sb_1__1__114_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__115_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_125_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__125_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__125_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__125_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7529 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7530 ) ,
+ .Test_en_W_in ( Test_enWires[154] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7531 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7532 ) ,
+ .Test_en_E_out ( Test_enWires[155] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[421] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[422] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7533 ) ,
+ .prog_clk_2_N_in ( p3219 ) , .prog_clk_2_S_in ( p3065 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7534 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7535 ) ,
+ .prog_clk_3_S_in ( p3136 ) , .prog_clk_3_N_in ( p3186 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7536 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_2_N_in ( p3124 ) ,
+ .clk_2_S_in ( p286 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7538 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7539 ) , .clk_3_S_in ( p1761 ) ,
+ .clk_3_N_in ( p1090 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7540 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7541 ) ) ;
+cby_1__1_ cby_11__7_ ( .chany_bottom_in ( sb_1__1__115_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__116_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_126_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__126_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__126_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__126_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7542 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7543 ) ,
+ .Test_en_W_in ( Test_enWires[176] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7544 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7545 ) ,
+ .Test_en_E_out ( Test_enWires[177] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[424] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[425] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7546 ) ,
+ .prog_clk_2_N_in ( p3340 ) , .prog_clk_2_S_in ( p2633 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7547 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7548 ) ,
+ .prog_clk_3_S_in ( p2796 ) , .prog_clk_3_N_in ( p3306 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7549 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7550 ) , .clk_2_N_in ( p3294 ) ,
+ .clk_2_S_in ( p242 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7551 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_S_in ( p1730 ) ,
+ .clk_3_N_in ( p1029 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7553 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7554 ) ) ;
+cby_1__1_ cby_11__8_ ( .chany_bottom_in ( sb_1__1__116_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__117_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_127_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__127_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__127_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__127_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7555 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7556 ) ,
+ .Test_en_W_in ( Test_enWires[198] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7557 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7558 ) ,
+ .Test_en_E_out ( Test_enWires[199] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[427] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[428] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7559 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[129] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7560 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[130] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7561 ) ,
+ .prog_clk_3_S_in ( p1521 ) , .prog_clk_3_N_in ( p508 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7562 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7563 ) ,
+ .clk_2_N_in ( clk_2_wires[129] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7564 ) ,
+ .clk_2_S_out ( clk_2_wires[130] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_3_S_in ( p2720 ) ,
+ .clk_3_N_in ( p1062 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7566 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7567 ) ) ;
+cby_1__1_ cby_11__9_ ( .chany_bottom_in ( sb_1__1__117_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__118_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_128_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__128_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__128_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__128_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7568 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7569 ) ,
+ .Test_en_W_in ( Test_enWires[220] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7570 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7571 ) ,
+ .Test_en_E_out ( Test_enWires[221] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[430] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[431] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7572 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7573 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[127] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7574 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1722 ) ,
+ .prog_clk_3_N_in ( p401 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7575 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7576 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7577 ) ,
+ .clk_2_S_in ( clk_2_wires[127] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7578 ) ,
+ .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p2075 ) ,
+ .clk_3_N_in ( p974 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7579 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7580 ) ) ;
+cby_1__1_ cby_11__10_ ( .chany_bottom_in ( sb_1__1__118_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__119_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_129_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__129_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__129_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__129_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7581 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7582 ) ,
+ .Test_en_W_in ( Test_enWires[242] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7583 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7584 ) ,
+ .Test_en_E_out ( Test_enWires[243] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[433] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[434] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7585 ) ,
+ .prog_clk_2_N_in ( p3418 ) , .prog_clk_2_S_in ( p3058 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7586 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7587 ) ,
+ .prog_clk_3_S_in ( p3150 ) , .prog_clk_3_N_in ( p3400 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7588 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7589 ) , .clk_2_N_in ( p3274 ) ,
+ .clk_2_S_in ( p651 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7590 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7591 ) , .clk_3_S_in ( p1776 ) ,
+ .clk_3_N_in ( p1329 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7592 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7593 ) ) ;
+cby_1__1_ cby_11__11_ ( .chany_bottom_in ( sb_1__1__119_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__120_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_130_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__130_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__130_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__130_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7594 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7595 ) ,
+ .Test_en_W_in ( Test_enWires[264] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7596 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7597 ) ,
+ .Test_en_E_out ( Test_enWires[265] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[436] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[437] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7598 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7599 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[134] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7600 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1252 ) ,
+ .prog_clk_3_N_in ( p1244 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7601 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7602 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7603 ) ,
+ .clk_2_S_in ( clk_2_wires[134] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7604 ) ,
+ .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p2308 ) ,
+ .clk_3_N_in ( p644 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7605 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7606 ) ) ;
+cby_1__1_ cby_11__12_ ( .chany_bottom_in ( sb_1__1__120_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_131_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__131_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__131_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__131_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7607 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7608 ) ,
+ .Test_en_W_in ( Test_enWires[286] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7609 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7610 ) ,
+ .Test_en_E_out ( Test_enWires[287] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[439] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[440] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p3345 ) ,
+ .prog_clk_2_S_in ( p3304 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7611 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7612 ) ,
+ .prog_clk_3_S_in ( p3327 ) , .prog_clk_3_N_in ( p3313 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7613 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7614 ) , .clk_2_N_in ( p2904 ) ,
+ .clk_2_S_in ( p828 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7615 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_S_in ( p2322 ) ,
+ .clk_3_N_in ( p2002 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7617 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7618 ) ) ;
+cby_2__1_ cby_12__1_ ( .chany_bottom_in ( sb_12__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_132_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__0_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[444] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[445] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7619 ) ) ;
+cby_2__1_ cby_12__2_ ( .chany_bottom_in ( sb_12__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_133_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__1_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[447] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[448] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7620 ) ) ;
+cby_2__1_ cby_12__3_ ( .chany_bottom_in ( sb_12__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_134_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__2_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[450] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[451] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7621 ) ) ;
+cby_2__1_ cby_12__4_ ( .chany_bottom_in ( sb_12__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_135_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__3_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[453] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[454] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7622 ) ) ;
+cby_2__1_ cby_12__5_ ( .chany_bottom_in ( sb_12__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_136_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__4_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[456] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[457] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7623 ) ) ;
+cby_2__1_ cby_12__6_ ( .chany_bottom_in ( sb_12__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_137_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__5_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[459] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[460] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7624 ) ) ;
+cby_2__1_ cby_12__7_ ( .chany_bottom_in ( sb_12__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_138_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__6_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[462] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[463] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7625 ) ) ;
+cby_2__1_ cby_12__8_ ( .chany_bottom_in ( sb_12__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_139_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__7_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[465] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[466] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7626 ) ) ;
+cby_2__1_ cby_12__9_ ( .chany_bottom_in ( sb_12__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_140_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__8_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[468] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[469] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7627 ) ) ;
+cby_2__1_ cby_12__10_ ( .chany_bottom_in ( sb_12__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_141_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__9_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[471] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[472] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7628 ) ) ;
+cby_2__1_ cby_12__11_ ( .chany_bottom_in ( sb_12__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_142_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__10_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[474] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[475] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7629 ) ) ;
+cby_2__1_ cby_12__12_ ( .chany_bottom_in ( sb_12__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_12__12__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_143_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__11_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[477] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[478] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[480] ) ) ;
+endmodule
+
+
+module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 ,
+ vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i ,
+ wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in ,
+ la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ ,
+ analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ ,
+ analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ ,
+ analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ ,
+ analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ ,
+ analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ ,
+ analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ ,
+ analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ ,
+ analog_io_9_ , user_clock2 ) ;
+inout vdda1 ;
+inout vdda2 ;
+inout vssa1 ;
+inout vssa2 ;
+inout vccd1 ;
+inout vccd2 ;
+inout vssd1 ;
+inout vssd2 ;
+input wb_clk_i ;
+input wb_rst_i ;
+input wbs_stb_i ;
+input wbs_cyc_i ;
+input wbs_we_i ;
+input [3:0] wbs_sel_i ;
+input [31:0] wbs_dat_i ;
+input [31:0] wbs_adr_i ;
+output wbs_ack_o ;
+output [31:0] wbs_dat_o ;
+input [127:0] la_data_in ;
+output [127:0] la_data_out ;
+input [127:0] la_oen ;
+input [37:0] io_in ;
+output [37:0] io_out ;
+output [37:0] io_oeb ;
+inout analog_io_0_ ;
+inout analog_io_10_ ;
+inout analog_io_11_ ;
+inout analog_io_12_ ;
+inout analog_io_13_ ;
+inout analog_io_14_ ;
+inout analog_io_15_ ;
+inout analog_io_16_ ;
+inout analog_io_17_ ;
+inout analog_io_18_ ;
+inout analog_io_19_ ;
+inout analog_io_1_ ;
+inout analog_io_20_ ;
+inout analog_io_21_ ;
+inout analog_io_22_ ;
+inout analog_io_23_ ;
+inout analog_io_24_ ;
+inout analog_io_25_ ;
+inout analog_io_26_ ;
+inout analog_io_27_ ;
+inout analog_io_28_ ;
+inout analog_io_29_ ;
+inout analog_io_2_ ;
+inout analog_io_30_ ;
+inout analog_io_3_ ;
+inout analog_io_4_ ;
+inout analog_io_5_ ;
+inout analog_io_6_ ;
+inout analog_io_7_ ;
+inout analog_io_8_ ;
+inout analog_io_9_ ;
+input user_clock2 ;
+
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+wire ccff_head ;
+wire sc_tail ;
+wire io_isol_n ;
+wire Test_en ;
+wire prog_clk ;
+wire clk ;
+wire ccff_tail ;
+wire sc_head ;
+wire wb_la_switch ;
+
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ;
+assign ccff_head = io_in[12] ;
+assign sc_tail = io_out[11] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = io_in[3] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = io_in[2] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = io_out[3] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = io_out[2] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] = io_oeb[3] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] = io_oeb[2] ;
+assign io_isol_n = io_in[1] ;
+assign Test_en = io_in[0] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[25] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[26] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[36] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[37] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[38] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[39] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[40] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[41] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[42] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[43] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[44] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[45] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[46] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[47] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[48] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[49] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[50] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[51] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[52] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[53] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[54] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[55] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[56] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[57] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[58] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[59] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[60] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[61] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[62] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[63] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[64] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[65] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[66] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[67] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[68] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[69] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[70] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[71] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[72] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[73] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[74] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[75] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[76] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[77] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[78] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[79] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[80] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[81] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[82] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[83] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[84] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[85] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[86] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[87] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[88] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[89] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[90] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[91] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[92] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[93] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[94] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[95] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[96] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[97] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[98] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[99] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[100] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[101] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[102] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[103] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[104] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[105] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[106] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[107] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[108] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[109] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[110] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[111] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[112] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[113] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[114] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[115] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[116] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[127] ;
+assign prog_clk = io_in[37] ;
+assign clk = io_in[36] ;
+assign ccff_tail = io_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ;
+assign sc_head = io_in[26] ;
+assign wb_la_switch = io_in[25] ;
+
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[13] ) ,
+ .A1 ( wb_clk_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[14] ) ,
+ .A1 ( wb_rst_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_ack_o ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[15] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[16] ) ,
+ .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[17] ) ,
+ .A1 ( wbs_stb_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[18] ) ,
+ .A1 ( wbs_we_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[19] ) ,
+ .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[20] ) ,
+ .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[21] ) ,
+ .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[22] ) ,
+ .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[23] ) ,
+ .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[24] ) ,
+ .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[25] ) ,
+ .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[26] ) ,
+ .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[27] ) ,
+ .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[28] ) ,
+ .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[29] ) ,
+ .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[30] ) ,
+ .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[31] ) ,
+ .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[32] ) ,
+ .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[33] ) ,
+ .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[34] ) ,
+ .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[35] ) ,
+ .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[36] ) ,
+ .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[37] ) ,
+ .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[38] ) ,
+ .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[39] ) ,
+ .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[40] ) ,
+ .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[41] ) ,
+ .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[42] ) ,
+ .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[43] ) ,
+ .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[44] ) ,
+ .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[45] ) ,
+ .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[46] ) ,
+ .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[47] ) ,
+ .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[48] ) ,
+ .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[49] ) ,
+ .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[50] ) ,
+ .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[51] ) ,
+ .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[52] ) ,
+ .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[53] ) ,
+ .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[54] ) ,
+ .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[55] ) ,
+ .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[56] ) ,
+ .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[57] ) ,
+ .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[58] ) ,
+ .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[59] ) ,
+ .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[60] ) ,
+ .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[61] ) ,
+ .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[62] ) ,
+ .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[63] ) ,
+ .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[64] ) ,
+ .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[65] ) ,
+ .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[66] ) ,
+ .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[67] ) ,
+ .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[68] ) ,
+ .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[69] ) ,
+ .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[70] ) ,
+ .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[71] ) ,
+ .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[72] ) ,
+ .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[73] ) ,
+ .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[74] ) ,
+ .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[75] ) ,
+ .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[76] ) ,
+ .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[77] ) ,
+ .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[78] ) ,
+ .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[79] ) ,
+ .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[80] ) ,
+ .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[81] ) ,
+ .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[82] ) ,
+ .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[83] ) ,
+ .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[84] ) ,
+ .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[85] ) ,
+ .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[86] ) ,
+ .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[0] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[87] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[1] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[88] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[2] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[89] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[3] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[90] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[4] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[91] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[5] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[92] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[6] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[93] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[7] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[94] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[8] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[95] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[9] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[96] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[10] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[97] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[11] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[98] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[12] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[99] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[13] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[100] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[14] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[101] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[15] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[102] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[16] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[103] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[17] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[104] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[18] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[105] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[19] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[106] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[20] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[107] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[21] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[108] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[22] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[109] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[23] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[110] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[24] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[111] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[25] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[112] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[26] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[113] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[27] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[114] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[28] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[115] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[29] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[116] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[30] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[117] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[31] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[118] ) ) ;
+fpga_core fpga_core_uut ( .prog_clk ( io_in[37] ) , .Test_en ( io_in[0] ) ,
+ .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] ,
+ io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] ,
+ io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] ,
+ io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] , io_in[3] ,
+ io_in[2] , la_data_in[127] , la_data_in[126] , la_data_in[125] ,
+ la_data_in[124] , la_data_in[123] , la_data_in[122] ,
+ la_data_in[121] , la_data_in[120] , la_data_in[119] ,
+ la_data_in[118] , la_data_in[117] , la_data_in[116] ,
+ la_data_in[115] , la_data_in[114] , la_data_in[113] ,
+ la_data_in[112] , la_data_in[111] , la_data_in[110] ,
+ la_data_in[109] , la_data_in[108] , la_data_in[107] ,
+ la_data_in[106] , la_data_in[105] , la_data_in[104] ,
+ la_data_in[103] , la_data_in[102] , la_data_in[101] ,
+ la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] ,
+ la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] ,
+ la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] ,
+ la_data_in[88] , la_data_in[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[15] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] ,
+ io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] ,
+ io_in[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] ,
+ io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] ,
+ io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] ,
+ io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] ,
+ io_out[5] , io_out[4] , io_out[3] , io_out[2] , la_data_out[127] ,
+ la_data_out[126] , la_data_out[125] , la_data_out[124] ,
+ la_data_out[123] , la_data_out[122] , la_data_out[121] ,
+ la_data_out[120] , la_data_out[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[86] ,
+ la_data_out[85] , la_data_out[84] , la_data_out[83] ,
+ la_data_out[82] , la_data_out[81] , la_data_out[80] ,
+ la_data_out[79] , la_data_out[78] , la_data_out[77] ,
+ la_data_out[76] , la_data_out[75] , la_data_out[74] ,
+ la_data_out[73] , la_data_out[72] , la_data_out[71] ,
+ la_data_out[70] , la_data_out[69] , la_data_out[68] ,
+ la_data_out[67] , la_data_out[66] , la_data_out[65] ,
+ la_data_out[64] , la_data_out[63] , la_data_out[62] ,
+ la_data_out[61] , la_data_out[60] , la_data_out[59] ,
+ la_data_out[58] , la_data_out[57] , la_data_out[56] ,
+ la_data_out[55] , la_data_out[54] , la_data_out[53] ,
+ la_data_out[52] , la_data_out[51] , la_data_out[50] ,
+ la_data_out[49] , la_data_out[48] , la_data_out[47] ,
+ la_data_out[46] , la_data_out[45] , la_data_out[44] ,
+ la_data_out[43] , la_data_out[42] , la_data_out[41] ,
+ la_data_out[40] , la_data_out[39] , la_data_out[38] ,
+ la_data_out[37] , la_data_out[36] , la_data_out[35] ,
+ la_data_out[34] , la_data_out[33] , la_data_out[32] ,
+ la_data_out[31] , la_data_out[30] , la_data_out[29] ,
+ la_data_out[28] , la_data_out[27] , la_data_out[26] ,
+ la_data_out[25] , la_data_out[24] , la_data_out[23] ,
+ la_data_out[22] , la_data_out[21] , la_data_out[20] ,
+ la_data_out[19] , la_data_out[18] , la_data_out[17] ,
+ la_data_out[16] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ,
+ la_data_out[14] , la_data_out[13] , io_out[34] , io_out[33] ,
+ io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] ,
+ io_out[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] ,
+ io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] ,
+ io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] ,
+ io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] ,
+ io_oeb[5] , io_oeb[4] , io_oeb[3] , io_oeb[2] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] ,
+ io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] ,
+ io_oeb[27] } ) ,
+ .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) ,
+ .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) ,
+ .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , .p0 ( optlc_net_16 ) ,
+ .p1 ( optlc_net_17 ) , .p2 ( optlc_net_18 ) , .p3 ( optlc_net_19 ) ,
+ .p4 ( optlc_net_20 ) , .p5 ( optlc_net_21 ) , .p6 ( optlc_net_22 ) ,
+ .p7 ( optlc_net_23 ) , .p8 ( optlc_net_24 ) , .p9 ( optlc_net_25 ) ,
+ .p10 ( optlc_net_26 ) , .p11 ( optlc_net_27 ) , .p12 ( optlc_net_28 ) ,
+ .p13 ( optlc_net_29 ) , .p14 ( optlc_net_30 ) , .p15 ( optlc_net_31 ) ,
+ .p16 ( optlc_net_32 ) , .p17 ( optlc_net_33 ) , .p18 ( optlc_net_34 ) ,
+ .p19 ( optlc_net_35 ) , .p20 ( optlc_net_36 ) , .p21 ( optlc_net_37 ) ,
+ .p22 ( optlc_net_38 ) , .p23 ( optlc_net_39 ) , .p24 ( optlc_net_40 ) ,
+ .p25 ( optlc_net_41 ) , .p26 ( optlc_net_42 ) , .p27 ( optlc_net_43 ) ,
+ .p28 ( optlc_net_44 ) , .p29 ( optlc_net_45 ) , .p30 ( optlc_net_46 ) ,
+ .p31 ( optlc_net_47 ) , .p32 ( optlc_net_48 ) , .p33 ( optlc_net_49 ) ,
+ .p34 ( optlc_net_50 ) , .p35 ( optlc_net_51 ) , .p36 ( optlc_net_52 ) ,
+ .p37 ( optlc_net_53 ) , .p38 ( optlc_net_54 ) , .p39 ( optlc_net_55 ) ,
+ .p40 ( optlc_net_56 ) , .p41 ( optlc_net_57 ) , .p42 ( optlc_net_58 ) ,
+ .p43 ( optlc_net_59 ) , .p44 ( optlc_net_60 ) , .p45 ( optlc_net_61 ) ,
+ .p46 ( optlc_net_62 ) , .p47 ( optlc_net_63 ) , .p48 ( optlc_net_64 ) ,
+ .p49 ( optlc_net_65 ) , .p50 ( optlc_net_66 ) , .p51 ( optlc_net_67 ) ,
+ .p52 ( optlc_net_68 ) , .p53 ( optlc_net_69 ) , .p54 ( optlc_net_70 ) ,
+ .p55 ( optlc_net_71 ) , .p56 ( optlc_net_72 ) , .p57 ( optlc_net_73 ) ,
+ .p58 ( optlc_net_74 ) , .p59 ( optlc_net_75 ) , .p60 ( optlc_net_76 ) ,
+ .p61 ( optlc_net_77 ) , .p62 ( optlc_net_78 ) , .p63 ( optlc_net_79 ) ,
+ .p64 ( optlc_net_80 ) , .p65 ( optlc_net_81 ) , .p66 ( optlc_net_82 ) ,
+ .p67 ( optlc_net_83 ) , .p68 ( optlc_net_84 ) , .p69 ( optlc_net_85 ) ,
+ .p70 ( optlc_net_86 ) , .p71 ( optlc_net_87 ) , .p72 ( optlc_net_88 ) ,
+ .p73 ( optlc_net_89 ) , .p74 ( optlc_net_90 ) , .p75 ( optlc_net_91 ) ,
+ .p76 ( optlc_net_92 ) , .p77 ( optlc_net_93 ) , .p78 ( optlc_net_94 ) ,
+ .p79 ( optlc_net_95 ) , .p80 ( optlc_net_96 ) , .p81 ( optlc_net_97 ) ,
+ .p82 ( optlc_net_98 ) , .p83 ( optlc_net_99 ) , .p84 ( optlc_net_100 ) ,
+ .p85 ( optlc_net_101 ) , .p86 ( optlc_net_102 ) , .p87 ( optlc_net_103 ) ,
+ .p88 ( optlc_net_104 ) , .p89 ( optlc_net_105 ) , .p90 ( optlc_net_106 ) ,
+ .p91 ( optlc_net_107 ) , .p92 ( optlc_net_108 ) , .p93 ( optlc_net_109 ) ,
+ .p94 ( optlc_net_110 ) , .p95 ( optlc_net_111 ) , .p96 ( optlc_net_112 ) ,
+ .p97 ( optlc_net_113 ) , .p98 ( optlc_net_114 ) , .p99 ( optlc_net_115 ) ,
+ .p100 ( optlc_net_116 ) , .p101 ( optlc_net_117 ) ,
+ .p102 ( optlc_net_118 ) , .p103 ( optlc_net_119 ) ,
+ .p104 ( optlc_net_120 ) , .p105 ( optlc_net_121 ) ,
+ .p106 ( optlc_net_122 ) , .p107 ( optlc_net_123 ) ,
+ .p108 ( optlc_net_124 ) , .p109 ( optlc_net_125 ) ,
+ .p110 ( optlc_net_126 ) , .p111 ( optlc_net_127 ) ,
+ .p112 ( optlc_net_128 ) , .p113 ( optlc_net_129 ) ,
+ .p114 ( optlc_net_130 ) , .p115 ( optlc_net_131 ) ,
+ .p116 ( optlc_net_132 ) , .p117 ( optlc_net_133 ) ,
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+ .p712 ( optlc_net_728 ) , .p713 ( optlc_net_729 ) ,
+ .p714 ( optlc_net_730 ) , .p715 ( optlc_net_731 ) ,
+ .p716 ( optlc_net_732 ) , .p717 ( optlc_net_733 ) ,
+ .p718 ( optlc_net_734 ) , .p719 ( optlc_net_735 ) ,
+ .p720 ( optlc_net_736 ) , .p721 ( optlc_net_737 ) ,
+ .p722 ( optlc_net_738 ) , .p723 ( optlc_net_739 ) ,
+ .p724 ( optlc_net_740 ) , .p725 ( optlc_net_741 ) ,
+ .p726 ( optlc_net_742 ) , .p727 ( optlc_net_743 ) ,
+ .p728 ( optlc_net_744 ) , .p729 ( optlc_net_745 ) ,
+ .p730 ( optlc_net_746 ) , .p731 ( optlc_net_747 ) ,
+ .p732 ( optlc_net_748 ) , .p733 ( optlc_net_749 ) ,
+ .p734 ( optlc_net_750 ) , .p735 ( optlc_net_751 ) ,
+ .p736 ( optlc_net_752 ) , .p737 ( optlc_net_753 ) ,
+ .p738 ( optlc_net_754 ) , .p739 ( optlc_net_755 ) ,
+ .p740 ( optlc_net_756 ) , .p741 ( optlc_net_757 ) ,
+ .p742 ( optlc_net_758 ) , .p743 ( optlc_net_759 ) ,
+ .p744 ( optlc_net_760 ) , .p745 ( optlc_net_761 ) ,
+ .p746 ( optlc_net_762 ) , .p747 ( optlc_net_763 ) ,
+ .p748 ( optlc_net_764 ) , .p749 ( optlc_net_765 ) ,
+ .p750 ( optlc_net_766 ) , .p751 ( optlc_net_767 ) ,
+ .p752 ( optlc_net_768 ) , .p753 ( optlc_net_769 ) ,
+ .p754 ( optlc_net_770 ) , .p755 ( optlc_net_771 ) ,
+ .p756 ( optlc_net_772 ) , .p757 ( optlc_net_773 ) ,
+ .p758 ( optlc_net_774 ) , .p759 ( optlc_net_775 ) ,
+ .p760 ( optlc_net_776 ) , .p761 ( optlc_net_777 ) ,
+ .p762 ( optlc_net_778 ) , .p763 ( optlc_net_779 ) ,
+ .p764 ( optlc_net_780 ) , .p765 ( optlc_net_781 ) ,
+ .p766 ( optlc_net_782 ) , .p767 ( optlc_net_783 ) ,
+ .p768 ( optlc_net_784 ) , .p769 ( optlc_net_785 ) ,
+ .p770 ( optlc_net_786 ) , .p771 ( optlc_net_787 ) ,
+ .p772 ( optlc_net_788 ) , .p773 ( optlc_net_789 ) ,
+ .p774 ( optlc_net_790 ) , .p775 ( optlc_net_791 ) ,
+ .p776 ( optlc_net_792 ) , .p777 ( optlc_net_793 ) ,
+ .p778 ( optlc_net_794 ) , .p779 ( optlc_net_795 ) ,
+ .p780 ( optlc_net_796 ) , .p781 ( optlc_net_797 ) ,
+ .p782 ( optlc_net_798 ) , .p783 ( optlc_net_799 ) ,
+ .p784 ( optlc_net_800 ) , .p785 ( optlc_net_801 ) ,
+ .p786 ( optlc_net_802 ) , .p787 ( optlc_net_803 ) ,
+ .p788 ( optlc_net_804 ) , .p789 ( optlc_net_805 ) ,
+ .p790 ( optlc_net_806 ) , .p791 ( optlc_net_807 ) ,
+ .p792 ( optlc_net_808 ) , .p793 ( optlc_net_809 ) ,
+ .p794 ( optlc_net_810 ) , .p795 ( optlc_net_811 ) ,
+ .p796 ( optlc_net_812 ) , .p797 ( optlc_net_813 ) ,
+ .p798 ( optlc_net_814 ) , .p799 ( optlc_net_815 ) ,
+ .p800 ( optlc_net_816 ) , .p801 ( optlc_net_817 ) ,
+ .p802 ( optlc_net_818 ) , .p803 ( optlc_net_819 ) ,
+ .p804 ( optlc_net_820 ) , .p805 ( optlc_net_821 ) ,
+ .p806 ( optlc_net_822 ) , .p807 ( optlc_net_823 ) ,
+ .p808 ( optlc_net_824 ) , .p809 ( optlc_net_825 ) ,
+ .p810 ( optlc_net_826 ) , .p811 ( optlc_net_827 ) ,
+ .p812 ( optlc_net_828 ) , .p813 ( optlc_net_829 ) ,
+ .p814 ( optlc_net_830 ) , .p815 ( optlc_net_831 ) ,
+ .p816 ( optlc_net_832 ) , .p817 ( optlc_net_833 ) ,
+ .p818 ( optlc_net_834 ) , .p819 ( optlc_net_835 ) ,
+ .p820 ( optlc_net_836 ) , .p821 ( optlc_net_837 ) ,
+ .p822 ( optlc_net_838 ) , .p823 ( optlc_net_839 ) ,
+ .p824 ( optlc_net_840 ) , .p825 ( optlc_net_841 ) ,
+ .p826 ( optlc_net_842 ) , .p827 ( optlc_net_843 ) ,
+ .p828 ( optlc_net_844 ) , .p829 ( optlc_net_845 ) ,
+ .p830 ( optlc_net_846 ) , .p831 ( optlc_net_847 ) ,
+ .p832 ( optlc_net_848 ) , .p833 ( optlc_net_849 ) ,
+ .p834 ( optlc_net_850 ) , .p835 ( optlc_net_851 ) ,
+ .p836 ( optlc_net_852 ) , .p837 ( optlc_net_853 ) ,
+ .p838 ( optlc_net_854 ) , .p839 ( optlc_net_855 ) ,
+ .p840 ( optlc_net_856 ) , .p841 ( optlc_net_857 ) ,
+ .p842 ( optlc_net_858 ) , .p843 ( optlc_net_859 ) ,
+ .p844 ( optlc_net_860 ) , .p845 ( optlc_net_861 ) ,
+ .p846 ( optlc_net_862 ) , .p847 ( optlc_net_863 ) ,
+ .p848 ( optlc_net_864 ) , .p849 ( optlc_net_865 ) ,
+ .p850 ( optlc_net_866 ) , .p851 ( optlc_net_867 ) ,
+ .p852 ( optlc_net_868 ) , .p853 ( optlc_net_869 ) ,
+ .p854 ( optlc_net_870 ) , .p855 ( optlc_net_871 ) ,
+ .p856 ( optlc_net_872 ) , .p857 ( optlc_net_873 ) ,
+ .p858 ( optlc_net_874 ) , .p859 ( optlc_net_875 ) ,
+ .p860 ( optlc_net_876 ) , .p861 ( optlc_net_877 ) ,
+ .p862 ( optlc_net_878 ) , .p863 ( optlc_net_879 ) ,
+ .p864 ( optlc_net_880 ) , .p865 ( optlc_net_881 ) ,
+ .p866 ( optlc_net_882 ) , .p867 ( optlc_net_883 ) ,
+ .p868 ( optlc_net_884 ) , .p869 ( optlc_net_885 ) ,
+ .p870 ( optlc_net_886 ) , .p871 ( optlc_net_887 ) ,
+ .p872 ( optlc_net_888 ) , .p873 ( optlc_net_889 ) ,
+ .p874 ( optlc_net_890 ) , .p875 ( optlc_net_891 ) ,
+ .p876 ( optlc_net_892 ) , .p877 ( optlc_net_893 ) ,
+ .p878 ( optlc_net_894 ) , .p879 ( optlc_net_895 ) ,
+ .p880 ( optlc_net_896 ) , .p881 ( optlc_net_897 ) ,
+ .p882 ( optlc_net_898 ) , .p883 ( optlc_net_899 ) ,
+ .p884 ( optlc_net_900 ) , .p885 ( optlc_net_901 ) ,
+ .p886 ( optlc_net_902 ) , .p887 ( optlc_net_903 ) ,
+ .p888 ( optlc_net_904 ) , .p889 ( optlc_net_905 ) ,
+ .p890 ( optlc_net_906 ) , .p891 ( optlc_net_907 ) ,
+ .p892 ( optlc_net_908 ) , .p893 ( optlc_net_909 ) ,
+ .p894 ( optlc_net_910 ) , .p895 ( optlc_net_911 ) ,
+ .p896 ( optlc_net_912 ) , .p897 ( optlc_net_913 ) ,
+ .p898 ( optlc_net_914 ) , .p899 ( optlc_net_915 ) ,
+ .p900 ( optlc_net_916 ) , .p901 ( optlc_net_917 ) ,
+ .p902 ( optlc_net_918 ) , .p903 ( optlc_net_919 ) ,
+ .p904 ( optlc_net_920 ) , .p905 ( optlc_net_921 ) ,
+ .p906 ( optlc_net_922 ) , .p907 ( optlc_net_923 ) ,
+ .p908 ( optlc_net_924 ) , .p909 ( optlc_net_925 ) ,
+ .p910 ( optlc_net_926 ) , .p911 ( optlc_net_927 ) ,
+ .p912 ( optlc_net_928 ) , .p913 ( optlc_net_929 ) ,
+ .p914 ( optlc_net_930 ) , .p915 ( optlc_net_931 ) ,
+ .p916 ( optlc_net_932 ) , .p917 ( optlc_net_933 ) ,
+ .p918 ( optlc_net_934 ) , .p919 ( optlc_net_935 ) ,
+ .p920 ( optlc_net_936 ) , .p921 ( optlc_net_937 ) ,
+ .p922 ( optlc_net_938 ) , .p923 ( optlc_net_939 ) ,
+ .p924 ( optlc_net_940 ) , .p925 ( optlc_net_941 ) ,
+ .p926 ( optlc_net_942 ) , .p927 ( optlc_net_943 ) ,
+ .p928 ( optlc_net_944 ) , .p929 ( optlc_net_945 ) ,
+ .p930 ( optlc_net_946 ) , .p931 ( optlc_net_947 ) ,
+ .p932 ( optlc_net_948 ) , .p933 ( optlc_net_949 ) ,
+ .p934 ( optlc_net_950 ) , .p935 ( optlc_net_951 ) ,
+ .p936 ( optlc_net_952 ) , .p937 ( optlc_net_953 ) ,
+ .p938 ( optlc_net_954 ) , .p939 ( optlc_net_955 ) ,
+ .p940 ( optlc_net_956 ) , .p941 ( optlc_net_957 ) ,
+ .p942 ( optlc_net_958 ) , .p943 ( optlc_net_959 ) ,
+ .p944 ( optlc_net_960 ) , .p945 ( optlc_net_961 ) ,
+ .p946 ( optlc_net_962 ) , .p947 ( optlc_net_963 ) ,
+ .p948 ( optlc_net_964 ) , .p949 ( optlc_net_965 ) ,
+ .p950 ( optlc_net_966 ) , .p951 ( optlc_net_967 ) ,
+ .p952 ( optlc_net_968 ) , .p953 ( optlc_net_969 ) ,
+ .p954 ( optlc_net_970 ) , .p955 ( optlc_net_971 ) ,
+ .p956 ( optlc_net_972 ) , .p957 ( optlc_net_973 ) ,
+ .p958 ( optlc_net_974 ) , .p959 ( optlc_net_975 ) ,
+ .p960 ( optlc_net_976 ) , .p961 ( optlc_net_977 ) ,
+ .p962 ( optlc_net_978 ) , .p963 ( optlc_net_979 ) ,
+ .p964 ( optlc_net_980 ) , .p965 ( optlc_net_981 ) ,
+ .p966 ( optlc_net_982 ) , .p967 ( optlc_net_983 ) ,
+ .p968 ( optlc_net_984 ) , .p969 ( optlc_net_985 ) ,
+ .p970 ( optlc_net_986 ) , .p971 ( optlc_net_987 ) ,
+ .p972 ( optlc_net_988 ) , .p973 ( optlc_net_989 ) ,
+ .p974 ( optlc_net_990 ) , .p975 ( optlc_net_991 ) ,
+ .p976 ( optlc_net_992 ) , .p977 ( optlc_net_993 ) ,
+ .p978 ( optlc_net_994 ) , .p979 ( optlc_net_995 ) ,
+ .p980 ( optlc_net_996 ) , .p981 ( optlc_net_997 ) ,
+ .p982 ( optlc_net_998 ) , .p983 ( optlc_net_999 ) ,
+ .p984 ( optlc_net_1000 ) , .p985 ( optlc_net_1001 ) ,
+ .p986 ( optlc_net_1002 ) , .p987 ( optlc_net_1003 ) ,
+ .p988 ( optlc_net_1004 ) , .p989 ( optlc_net_1005 ) ,
+ .p990 ( optlc_net_1006 ) , .p991 ( optlc_net_1007 ) ,
+ .p992 ( optlc_net_1008 ) , .p993 ( optlc_net_1009 ) ,
+ .p994 ( optlc_net_1010 ) , .p995 ( optlc_net_1011 ) ,
+ .p996 ( optlc_net_1012 ) , .p997 ( optlc_net_1013 ) ,
+ .p998 ( optlc_net_1014 ) , .p999 ( optlc_net_1015 ) ,
+ .p1000 ( optlc_net_1016 ) , .p1001 ( optlc_net_1017 ) ,
+ .p1002 ( optlc_net_1018 ) , .p1003 ( optlc_net_1019 ) ,
+ .p1004 ( optlc_net_1020 ) , .p1005 ( optlc_net_1021 ) ,
+ .p1006 ( optlc_net_1022 ) , .p1007 ( optlc_net_1023 ) ,
+ .p1008 ( optlc_net_1024 ) , .p1009 ( optlc_net_1025 ) ,
+ .p1010 ( optlc_net_1026 ) , .p1011 ( optlc_net_1027 ) ,
+ .p1012 ( optlc_net_1028 ) , .p1013 ( optlc_net_1029 ) ,
+ .p1014 ( optlc_net_1030 ) , .p1015 ( optlc_net_1031 ) ,
+ .p1016 ( optlc_net_1032 ) , .p1017 ( optlc_net_1033 ) ,
+ .p1018 ( optlc_net_1034 ) , .p1019 ( optlc_net_1035 ) ,
+ .p1020 ( optlc_net_1036 ) , .p1021 ( optlc_net_1037 ) ,
+ .p1022 ( optlc_net_1038 ) , .p1023 ( optlc_net_1039 ) ,
+ .p1024 ( optlc_net_1040 ) , .p1025 ( optlc_net_1041 ) ,
+ .p1026 ( optlc_net_1042 ) , .p1027 ( optlc_net_1043 ) ,
+ .p1028 ( optlc_net_1044 ) , .p1029 ( optlc_net_1045 ) ,
+ .p1030 ( optlc_net_1046 ) , .p1031 ( optlc_net_1047 ) ,
+ .p1032 ( optlc_net_1048 ) , .p1033 ( optlc_net_1049 ) ,
+ .p1034 ( optlc_net_1050 ) , .p1035 ( optlc_net_1051 ) ,
+ .p1036 ( optlc_net_1052 ) , .p1037 ( optlc_net_1053 ) ,
+ .p1038 ( optlc_net_1054 ) , .p1039 ( optlc_net_1055 ) ,
+ .p1040 ( optlc_net_1056 ) , .p1041 ( optlc_net_1057 ) ,
+ .p1042 ( optlc_net_1058 ) , .p1043 ( optlc_net_1059 ) ,
+ .p1044 ( optlc_net_1060 ) , .p1045 ( optlc_net_1061 ) ,
+ .p1046 ( optlc_net_1062 ) , .p1047 ( optlc_net_1063 ) ,
+ .p1048 ( optlc_net_1064 ) , .p1049 ( optlc_net_1065 ) ,
+ .p1050 ( optlc_net_1066 ) , .p1051 ( optlc_net_1067 ) ,
+ .p1052 ( optlc_net_1068 ) , .p1053 ( optlc_net_1069 ) ,
+ .p1054 ( optlc_net_1070 ) , .p1055 ( optlc_net_1071 ) ,
+ .p1056 ( optlc_net_1072 ) , .p1057 ( optlc_net_1073 ) ,
+ .p1058 ( optlc_net_1074 ) , .p1059 ( optlc_net_1075 ) ,
+ .p1060 ( optlc_net_1076 ) , .p1061 ( optlc_net_1077 ) ,
+ .p1062 ( optlc_net_1078 ) , .p1063 ( optlc_net_1079 ) ,
+ .p1064 ( optlc_net_1080 ) , .p1065 ( optlc_net_1081 ) ,
+ .p1066 ( optlc_net_1082 ) , .p1067 ( optlc_net_1083 ) ,
+ .p1068 ( optlc_net_1084 ) , .p1069 ( optlc_net_1085 ) ,
+ .p1070 ( optlc_net_1086 ) , .p1071 ( optlc_net_1087 ) ,
+ .p1072 ( optlc_net_1088 ) , .p1073 ( optlc_net_1089 ) ,
+ .p1074 ( optlc_net_1090 ) , .p1075 ( optlc_net_1091 ) ,
+ .p1076 ( optlc_net_1092 ) , .p1077 ( optlc_net_1093 ) ,
+ .p1078 ( optlc_net_1094 ) , .p1079 ( optlc_net_1095 ) ,
+ .p1080 ( optlc_net_1096 ) , .p1081 ( optlc_net_1097 ) ,
+ .p1082 ( optlc_net_1098 ) , .p1083 ( optlc_net_1099 ) ,
+ .p1084 ( optlc_net_1100 ) , .p1085 ( optlc_net_1101 ) ,
+ .p1086 ( optlc_net_1102 ) , .p1087 ( optlc_net_1103 ) ,
+ .p1088 ( optlc_net_1104 ) , .p1089 ( optlc_net_1105 ) ,
+ .p1090 ( optlc_net_1106 ) , .p1091 ( optlc_net_1107 ) ,
+ .p1092 ( optlc_net_1108 ) , .p1093 ( optlc_net_1109 ) ,
+ .p1094 ( optlc_net_1110 ) , .p1095 ( optlc_net_1111 ) ,
+ .p1096 ( optlc_net_1112 ) , .p1097 ( optlc_net_1113 ) ,
+ .p1098 ( optlc_net_1114 ) , .p1099 ( optlc_net_1115 ) ,
+ .p1100 ( optlc_net_1116 ) , .p1101 ( optlc_net_1117 ) ,
+ .p1102 ( optlc_net_1118 ) , .p1103 ( optlc_net_1119 ) ,
+ .p1104 ( optlc_net_1120 ) , .p1105 ( optlc_net_1121 ) ,
+ .p1106 ( optlc_net_1122 ) , .p1107 ( optlc_net_1123 ) ,
+ .p1108 ( optlc_net_1124 ) , .p1109 ( optlc_net_1125 ) ,
+ .p1110 ( optlc_net_1126 ) , .p1111 ( optlc_net_1127 ) ,
+ .p1112 ( optlc_net_1128 ) , .p1113 ( optlc_net_1129 ) ,
+ .p1114 ( optlc_net_1130 ) , .p1115 ( optlc_net_1131 ) ,
+ .p1116 ( optlc_net_1132 ) , .p1117 ( optlc_net_1133 ) ,
+ .p1118 ( optlc_net_1134 ) , .p1119 ( optlc_net_1135 ) ,
+ .p1120 ( optlc_net_1136 ) , .p1121 ( optlc_net_1137 ) ,
+ .p1122 ( optlc_net_1138 ) , .p1123 ( optlc_net_1139 ) ,
+ .p1124 ( optlc_net_1140 ) , .p1125 ( optlc_net_1141 ) ,
+ .p1126 ( optlc_net_1142 ) , .p1127 ( optlc_net_1143 ) ,
+ .p1128 ( optlc_net_1144 ) , .p1129 ( optlc_net_1145 ) ,
+ .p1130 ( optlc_net_1146 ) , .p1131 ( optlc_net_1147 ) ,
+ .p1132 ( optlc_net_1148 ) , .p1133 ( optlc_net_1149 ) ,
+ .p1134 ( optlc_net_1150 ) , .p1135 ( optlc_net_1151 ) ,
+ .p1136 ( optlc_net_1152 ) , .p1137 ( optlc_net_1153 ) ,
+ .p1138 ( optlc_net_1154 ) , .p1139 ( optlc_net_1155 ) ,
+ .p1140 ( optlc_net_1156 ) , .p1141 ( optlc_net_1157 ) ,
+ .p1142 ( optlc_net_1158 ) , .p1143 ( optlc_net_1159 ) ,
+ .p1144 ( optlc_net_1160 ) , .p1145 ( optlc_net_1161 ) ,
+ .p1146 ( optlc_net_1162 ) , .p1147 ( optlc_net_1163 ) ,
+ .p1148 ( optlc_net_1164 ) , .p1149 ( optlc_net_1165 ) ,
+ .p1150 ( optlc_net_1166 ) , .p1151 ( optlc_net_1167 ) ,
+ .p1152 ( optlc_net_1168 ) , .p1153 ( optlc_net_1169 ) ,
+ .p1154 ( optlc_net_1170 ) , .p1155 ( optlc_net_1171 ) ,
+ .p1156 ( optlc_net_1172 ) , .p1157 ( optlc_net_1173 ) ,
+ .p1158 ( optlc_net_1174 ) , .p1159 ( optlc_net_1175 ) ,
+ .p1160 ( optlc_net_1176 ) , .p1161 ( optlc_net_1177 ) ,
+ .p1162 ( optlc_net_1178 ) , .p1163 ( optlc_net_1179 ) ,
+ .p1164 ( optlc_net_1180 ) , .p1165 ( optlc_net_1181 ) ,
+ .p1166 ( optlc_net_1182 ) , .p1167 ( optlc_net_1183 ) ,
+ .p1168 ( optlc_net_1184 ) , .p1169 ( optlc_net_1185 ) ,
+ .p1170 ( optlc_net_1186 ) , .p1171 ( optlc_net_1187 ) ,
+ .p1172 ( optlc_net_1188 ) , .p1173 ( optlc_net_1189 ) ,
+ .p1174 ( optlc_net_1190 ) , .p1175 ( optlc_net_1191 ) ,
+ .p1176 ( optlc_net_1192 ) , .p1177 ( optlc_net_1193 ) ,
+ .p1178 ( optlc_net_1194 ) , .p1179 ( optlc_net_1195 ) ,
+ .p1180 ( optlc_net_1196 ) , .p1181 ( optlc_net_1197 ) ,
+ .p1182 ( optlc_net_1198 ) , .p1183 ( optlc_net_1199 ) ,
+ .p1184 ( optlc_net_1200 ) , .p1185 ( optlc_net_1201 ) ,
+ .p1186 ( optlc_net_1202 ) , .p1187 ( optlc_net_1203 ) ,
+ .p1188 ( optlc_net_1204 ) , .p1189 ( optlc_net_1205 ) ,
+ .p1190 ( optlc_net_1206 ) , .p1191 ( optlc_net_1207 ) ,
+ .p1192 ( optlc_net_1208 ) , .p1193 ( optlc_net_1209 ) ,
+ .p1194 ( optlc_net_1210 ) , .p1195 ( optlc_net_1211 ) ,
+ .p1196 ( optlc_net_1212 ) , .p1197 ( optlc_net_1213 ) ,
+ .p1198 ( optlc_net_1214 ) , .p1199 ( optlc_net_1215 ) ,
+ .p1200 ( optlc_net_1216 ) , .p1201 ( optlc_net_1217 ) ,
+ .p1202 ( optlc_net_1218 ) , .p1203 ( optlc_net_1219 ) ,
+ .p1204 ( optlc_net_1220 ) , .p1205 ( optlc_net_1221 ) ,
+ .p1206 ( optlc_net_1222 ) , .p1207 ( optlc_net_1223 ) ,
+ .p1208 ( optlc_net_1224 ) , .p1209 ( optlc_net_1225 ) ,
+ .p1210 ( optlc_net_1226 ) , .p1211 ( optlc_net_1227 ) ,
+ .p1212 ( optlc_net_1228 ) , .p1213 ( optlc_net_1229 ) ,
+ .p1214 ( optlc_net_1230 ) , .p1215 ( optlc_net_1231 ) ,
+ .p1216 ( optlc_net_1232 ) , .p1217 ( optlc_net_1233 ) ,
+ .p1218 ( optlc_net_1234 ) , .p1219 ( optlc_net_1235 ) ,
+ .p1220 ( optlc_net_1236 ) , .p1221 ( optlc_net_1237 ) ,
+ .p1222 ( optlc_net_1238 ) , .p1223 ( optlc_net_1239 ) ,
+ .p1224 ( optlc_net_1240 ) , .p1225 ( optlc_net_1241 ) ,
+ .p1226 ( optlc_net_1242 ) , .p1227 ( optlc_net_1243 ) ,
+ .p1228 ( optlc_net_1244 ) , .p1229 ( optlc_net_1245 ) ,
+ .p1230 ( optlc_net_1246 ) , .p1231 ( optlc_net_1247 ) ,
+ .p1232 ( optlc_net_1248 ) , .p1233 ( optlc_net_1249 ) ,
+ .p1234 ( optlc_net_1250 ) , .p1235 ( optlc_net_1251 ) ,
+ .p1236 ( optlc_net_1252 ) , .p1237 ( optlc_net_1253 ) ,
+ .p1238 ( optlc_net_1254 ) , .p1239 ( optlc_net_1255 ) ,
+ .p1240 ( optlc_net_1256 ) , .p1241 ( optlc_net_1257 ) ,
+ .p1242 ( optlc_net_1258 ) , .p1243 ( optlc_net_1259 ) ,
+ .p1244 ( optlc_net_1260 ) , .p1245 ( optlc_net_1261 ) ,
+ .p1246 ( optlc_net_1262 ) , .p1247 ( optlc_net_1263 ) ,
+ .p1248 ( optlc_net_1264 ) , .p1249 ( optlc_net_1265 ) ,
+ .p1250 ( optlc_net_1266 ) , .p1251 ( optlc_net_1267 ) ,
+ .p1252 ( optlc_net_1268 ) , .p1253 ( optlc_net_1269 ) ,
+ .p1254 ( optlc_net_1270 ) , .p1255 ( optlc_net_1271 ) ,
+ .p1256 ( optlc_net_1272 ) , .p1257 ( optlc_net_1273 ) ,
+ .p1258 ( optlc_net_1274 ) , .p1259 ( optlc_net_1275 ) ,
+ .p1260 ( optlc_net_1276 ) , .p1261 ( optlc_net_1277 ) ,
+ .p1262 ( optlc_net_1278 ) , .p1263 ( optlc_net_1279 ) ,
+ .p1264 ( optlc_net_1280 ) , .p1265 ( optlc_net_1281 ) ,
+ .p1266 ( optlc_net_1282 ) , .p1267 ( optlc_net_1283 ) ,
+ .p1268 ( optlc_net_1284 ) , .p1269 ( optlc_net_1285 ) ,
+ .p1270 ( optlc_net_1286 ) , .p1271 ( optlc_net_1287 ) ,
+ .p1272 ( optlc_net_1288 ) , .p1273 ( optlc_net_1289 ) ,
+ .p1274 ( optlc_net_1290 ) , .p1275 ( optlc_net_1291 ) ,
+ .p1276 ( optlc_net_1292 ) , .p1277 ( optlc_net_1293 ) ,
+ .p1278 ( optlc_net_1294 ) , .p1279 ( optlc_net_1295 ) ,
+ .p1280 ( optlc_net_1296 ) , .p1281 ( optlc_net_1297 ) ,
+ .p1282 ( optlc_net_1298 ) , .p1283 ( optlc_net_1299 ) ,
+ .p1284 ( optlc_net_1300 ) , .p1285 ( optlc_net_1301 ) ,
+ .p1286 ( optlc_net_1302 ) , .p1287 ( optlc_net_1303 ) ,
+ .p1288 ( optlc_net_1304 ) , .p1289 ( optlc_net_1305 ) ,
+ .p1290 ( optlc_net_1306 ) , .p1291 ( optlc_net_1307 ) ,
+ .p1292 ( optlc_net_1308 ) , .p1293 ( optlc_net_1309 ) ,
+ .p1294 ( optlc_net_1310 ) , .p1295 ( optlc_net_1311 ) ,
+ .p1296 ( optlc_net_1312 ) , .p1297 ( optlc_net_1313 ) ,
+ .p1298 ( optlc_net_1314 ) , .p1299 ( optlc_net_1315 ) ,
+ .p1300 ( optlc_net_1316 ) , .p1301 ( optlc_net_1317 ) ,
+ .p1302 ( optlc_net_1318 ) , .p1303 ( optlc_net_1319 ) ,
+ .p1304 ( optlc_net_1320 ) , .p1305 ( optlc_net_1321 ) ,
+ .p1306 ( optlc_net_1322 ) , .p1307 ( optlc_net_1323 ) ,
+ .p1308 ( optlc_net_1324 ) , .p1309 ( optlc_net_1325 ) ,
+ .p1310 ( optlc_net_1326 ) , .p1311 ( optlc_net_1327 ) ,
+ .p1312 ( optlc_net_1328 ) , .p1313 ( optlc_net_1329 ) ,
+ .p1314 ( optlc_net_1330 ) , .p1315 ( optlc_net_1331 ) ,
+ .p1316 ( optlc_net_1332 ) , .p1317 ( optlc_net_1333 ) ,
+ .p1318 ( optlc_net_1334 ) , .p1319 ( optlc_net_1335 ) ,
+ .p1320 ( optlc_net_1336 ) , .p1321 ( optlc_net_1337 ) ,
+ .p1322 ( optlc_net_1338 ) , .p1323 ( optlc_net_1339 ) ,
+ .p1324 ( optlc_net_1340 ) , .p1325 ( optlc_net_1341 ) ,
+ .p1326 ( optlc_net_1342 ) , .p1327 ( optlc_net_1343 ) ,
+ .p1328 ( optlc_net_1344 ) , .p1329 ( optlc_net_1345 ) ,
+ .p1330 ( optlc_net_1346 ) , .p1331 ( optlc_net_1347 ) ,
+ .p1332 ( optlc_net_1348 ) , .p1333 ( optlc_net_1349 ) ,
+ .p1334 ( optlc_net_1350 ) , .p1335 ( optlc_net_1351 ) ,
+ .p1336 ( optlc_net_1352 ) , .p1337 ( optlc_net_1353 ) ,
+ .p1338 ( optlc_net_1354 ) , .p1339 ( optlc_net_1355 ) ,
+ .p1340 ( optlc_net_1356 ) , .p1341 ( optlc_net_1357 ) ,
+ .p1342 ( optlc_net_1358 ) , .p1343 ( optlc_net_1359 ) ,
+ .p1344 ( optlc_net_1360 ) , .p1345 ( optlc_net_1361 ) ,
+ .p1346 ( optlc_net_1362 ) , .p1347 ( optlc_net_1363 ) ,
+ .p1348 ( optlc_net_1364 ) , .p1349 ( optlc_net_1365 ) ,
+ .p1350 ( optlc_net_1366 ) , .p1351 ( optlc_net_1367 ) ,
+ .p1352 ( optlc_net_1368 ) , .p1353 ( optlc_net_1369 ) ,
+ .p1354 ( optlc_net_1370 ) , .p1355 ( optlc_net_1371 ) ,
+ .p1356 ( optlc_net_1372 ) , .p1357 ( optlc_net_1373 ) ,
+ .p1358 ( optlc_net_1374 ) , .p1359 ( optlc_net_1375 ) ,
+ .p1360 ( optlc_net_1376 ) , .p1361 ( optlc_net_1377 ) ,
+ .p1362 ( optlc_net_1378 ) , .p1363 ( optlc_net_1379 ) ,
+ .p1364 ( optlc_net_1380 ) , .p1365 ( optlc_net_1381 ) ,
+ .p1366 ( optlc_net_1382 ) , .p1367 ( optlc_net_1383 ) ,
+ .p1368 ( optlc_net_1384 ) , .p1369 ( optlc_net_1385 ) ,
+ .p1370 ( optlc_net_1386 ) , .p1371 ( optlc_net_1387 ) ,
+ .p1372 ( optlc_net_1388 ) , .p1373 ( optlc_net_1389 ) ,
+ .p1374 ( optlc_net_1390 ) , .p1375 ( optlc_net_1391 ) ,
+ .p1376 ( optlc_net_1392 ) , .p1377 ( optlc_net_1393 ) ,
+ .p1378 ( optlc_net_1394 ) , .p1379 ( optlc_net_1395 ) ,
+ .p1380 ( optlc_net_1396 ) , .p1381 ( optlc_net_1397 ) ,
+ .p1382 ( optlc_net_1398 ) , .p1383 ( optlc_net_1399 ) ,
+ .p1384 ( optlc_net_1400 ) , .p1385 ( optlc_net_1401 ) ,
+ .p1386 ( optlc_net_1402 ) , .p1387 ( optlc_net_1403 ) ,
+ .p1388 ( optlc_net_1404 ) , .p1389 ( optlc_net_1405 ) ,
+ .p1390 ( optlc_net_1406 ) , .p1391 ( optlc_net_1407 ) ,
+ .p1392 ( optlc_net_1408 ) , .p1393 ( optlc_net_1409 ) ,
+ .p1394 ( optlc_net_1410 ) , .p1395 ( optlc_net_1411 ) ,
+ .p1396 ( optlc_net_1412 ) , .p1397 ( optlc_net_1413 ) ,
+ .p1398 ( optlc_net_1414 ) , .p1399 ( optlc_net_1415 ) ,
+ .p1400 ( optlc_net_1416 ) , .p1401 ( optlc_net_1417 ) ,
+ .p1402 ( optlc_net_1418 ) , .p1403 ( optlc_net_1419 ) ,
+ .p1404 ( optlc_net_1420 ) , .p1405 ( optlc_net_1421 ) ,
+ .p1406 ( optlc_net_1422 ) , .p1407 ( optlc_net_1423 ) ,
+ .p1408 ( optlc_net_1424 ) , .p1409 ( optlc_net_1425 ) ,
+ .p1410 ( optlc_net_1426 ) , .p1411 ( optlc_net_1427 ) ,
+ .p1412 ( optlc_net_1428 ) , .p1413 ( optlc_net_1429 ) ,
+ .p1414 ( optlc_net_1430 ) , .p1415 ( optlc_net_1431 ) ,
+ .p1416 ( optlc_net_1432 ) , .p1417 ( optlc_net_1433 ) ,
+ .p1418 ( optlc_net_1434 ) , .p1419 ( optlc_net_1435 ) ,
+ .p1420 ( optlc_net_1436 ) , .p1421 ( optlc_net_1437 ) ,
+ .p1422 ( optlc_net_1438 ) , .p1423 ( optlc_net_1439 ) ,
+ .p1424 ( optlc_net_1440 ) , .p1425 ( optlc_net_1441 ) ,
+ .p1426 ( optlc_net_1442 ) , .p1427 ( optlc_net_1443 ) ,
+ .p1428 ( optlc_net_1444 ) , .p1429 ( optlc_net_1445 ) ,
+ .p1430 ( optlc_net_1446 ) , .p1431 ( optlc_net_1447 ) ,
+ .p1432 ( optlc_net_1448 ) , .p1433 ( optlc_net_1449 ) ,
+ .p1434 ( optlc_net_1450 ) , .p1435 ( optlc_net_1451 ) ,
+ .p1436 ( optlc_net_1452 ) , .p1437 ( optlc_net_1453 ) ,
+ .p1438 ( optlc_net_1454 ) , .p1439 ( optlc_net_1455 ) ,
+ .p1440 ( optlc_net_1456 ) , .p1441 ( optlc_net_1457 ) ,
+ .p1442 ( optlc_net_1458 ) , .p1443 ( optlc_net_1459 ) ,
+ .p1444 ( optlc_net_1460 ) , .p1445 ( optlc_net_1461 ) ,
+ .p1446 ( optlc_net_1462 ) , .p1447 ( optlc_net_1463 ) ,
+ .p1448 ( optlc_net_1464 ) , .p1449 ( optlc_net_1465 ) ,
+ .p1450 ( optlc_net_1466 ) , .p1451 ( optlc_net_1467 ) ,
+ .p1452 ( optlc_net_1468 ) , .p1453 ( optlc_net_1469 ) ,
+ .p1454 ( optlc_net_1470 ) , .p1455 ( optlc_net_1471 ) ,
+ .p1456 ( optlc_net_1472 ) , .p1457 ( optlc_net_1473 ) ,
+ .p1458 ( optlc_net_1474 ) , .p1459 ( optlc_net_1475 ) ,
+ .p1460 ( optlc_net_1476 ) , .p1461 ( optlc_net_1477 ) ,
+ .p1462 ( optlc_net_1478 ) , .p1463 ( optlc_net_1479 ) ,
+ .p1464 ( optlc_net_1480 ) , .p1465 ( optlc_net_1481 ) ,
+ .p1466 ( optlc_net_1482 ) , .p1467 ( optlc_net_1483 ) ,
+ .p1468 ( optlc_net_1484 ) , .p1469 ( optlc_net_1485 ) ,
+ .p1470 ( optlc_net_1486 ) , .p1471 ( optlc_net_1487 ) ,
+ .p1472 ( optlc_net_1488 ) , .p1473 ( optlc_net_1489 ) ,
+ .p1474 ( optlc_net_1490 ) , .p1475 ( optlc_net_1491 ) ,
+ .p1476 ( optlc_net_1492 ) , .p1477 ( optlc_net_1493 ) ,
+ .p1478 ( optlc_net_1494 ) , .p1479 ( optlc_net_1495 ) ,
+ .p1480 ( optlc_net_1496 ) , .p1481 ( optlc_net_1497 ) ,
+ .p1482 ( optlc_net_1498 ) , .p1483 ( optlc_net_1499 ) ,
+ .p1484 ( optlc_net_1500 ) , .p1485 ( optlc_net_1501 ) ,
+ .p1486 ( optlc_net_1502 ) , .p1487 ( optlc_net_1503 ) ,
+ .p1488 ( optlc_net_1504 ) , .p1489 ( optlc_net_1505 ) ,
+ .p1490 ( optlc_net_1506 ) , .p1491 ( optlc_net_1507 ) ,
+ .p1492 ( optlc_net_1508 ) , .p1493 ( optlc_net_1509 ) ,
+ .p1494 ( optlc_net_1510 ) , .p1495 ( optlc_net_1511 ) ,
+ .p1496 ( optlc_net_1512 ) , .p1497 ( optlc_net_1513 ) ,
+ .p1498 ( optlc_net_1514 ) , .p1499 ( optlc_net_1515 ) ,
+ .p1500 ( optlc_net_1516 ) , .p1501 ( optlc_net_1517 ) ,
+ .p1502 ( optlc_net_1518 ) , .p1503 ( optlc_net_1519 ) ,
+ .p1504 ( optlc_net_1520 ) , .p1505 ( optlc_net_1521 ) ,
+ .p1506 ( optlc_net_1522 ) , .p1507 ( optlc_net_1523 ) ,
+ .p1508 ( optlc_net_1524 ) , .p1509 ( optlc_net_1525 ) ,
+ .p1510 ( optlc_net_1526 ) , .p1511 ( optlc_net_1527 ) ,
+ .p1512 ( optlc_net_1528 ) , .p1513 ( optlc_net_1529 ) ,
+ .p1514 ( optlc_net_1530 ) , .p1515 ( optlc_net_1531 ) ,
+ .p1516 ( optlc_net_1532 ) , .p1517 ( optlc_net_1533 ) ,
+ .p1518 ( optlc_net_1534 ) , .p1519 ( optlc_net_1535 ) ,
+ .p1520 ( optlc_net_1536 ) , .p1521 ( optlc_net_1537 ) ,
+ .p1522 ( optlc_net_1538 ) , .p1523 ( optlc_net_1539 ) ,
+ .p1524 ( optlc_net_1540 ) , .p1525 ( optlc_net_1541 ) ,
+ .p1526 ( optlc_net_1542 ) , .p1527 ( optlc_net_1543 ) ,
+ .p1528 ( optlc_net_1544 ) , .p1529 ( optlc_net_1545 ) ,
+ .p1530 ( optlc_net_1546 ) , .p1531 ( optlc_net_1547 ) ,
+ .p1532 ( optlc_net_1548 ) , .p1533 ( optlc_net_1549 ) ,
+ .p1534 ( optlc_net_1550 ) , .p1535 ( optlc_net_1551 ) ,
+ .p1536 ( optlc_net_1552 ) , .p1537 ( optlc_net_1553 ) ,
+ .p1538 ( optlc_net_1554 ) , .p1539 ( optlc_net_1555 ) ,
+ .p1540 ( optlc_net_1556 ) , .p1541 ( optlc_net_1557 ) ,
+ .p1542 ( optlc_net_1558 ) , .p1543 ( optlc_net_1559 ) ,
+ .p1544 ( optlc_net_1560 ) , .p1545 ( optlc_net_1561 ) ,
+ .p1546 ( optlc_net_1562 ) , .p1547 ( optlc_net_1563 ) ,
+ .p1548 ( optlc_net_1564 ) , .p1549 ( optlc_net_1565 ) ,
+ .p1550 ( optlc_net_1566 ) , .p1551 ( optlc_net_1567 ) ,
+ .p1552 ( optlc_net_1568 ) , .p1553 ( optlc_net_1569 ) ,
+ .p1554 ( optlc_net_1570 ) , .p1555 ( optlc_net_1571 ) ,
+ .p1556 ( optlc_net_1572 ) , .p1557 ( optlc_net_1573 ) ,
+ .p1558 ( optlc_net_1574 ) , .p1559 ( optlc_net_1575 ) ,
+ .p1560 ( optlc_net_1576 ) , .p1561 ( optlc_net_1577 ) ,
+ .p1562 ( optlc_net_1578 ) , .p1563 ( optlc_net_1579 ) ,
+ .p1564 ( optlc_net_1580 ) , .p1565 ( optlc_net_1581 ) ,
+ .p1566 ( optlc_net_1582 ) , .p1567 ( optlc_net_1583 ) ,
+ .p1568 ( optlc_net_1584 ) , .p1569 ( optlc_net_1585 ) ,
+ .p1570 ( optlc_net_1586 ) , .p1571 ( optlc_net_1587 ) ,
+ .p1572 ( optlc_net_1588 ) , .p1573 ( optlc_net_1589 ) ,
+ .p1574 ( optlc_net_1590 ) , .p1575 ( optlc_net_1591 ) ,
+ .p1576 ( optlc_net_1592 ) , .p1577 ( optlc_net_1593 ) ,
+ .p1578 ( optlc_net_1594 ) , .p1579 ( optlc_net_1595 ) ,
+ .p1580 ( optlc_net_1596 ) , .p1581 ( optlc_net_1597 ) ,
+ .p1582 ( optlc_net_1598 ) , .p1583 ( optlc_net_1599 ) ,
+ .p1584 ( optlc_net_1600 ) , .p1585 ( optlc_net_1601 ) ,
+ .p1586 ( optlc_net_1602 ) , .p1587 ( optlc_net_1603 ) ,
+ .p1588 ( optlc_net_1604 ) , .p1589 ( optlc_net_1605 ) ,
+ .p1590 ( optlc_net_1606 ) , .p1591 ( optlc_net_1607 ) ,
+ .p1592 ( optlc_net_1608 ) , .p1593 ( optlc_net_1609 ) ,
+ .p1594 ( optlc_net_1610 ) , .p1595 ( optlc_net_1611 ) ,
+ .p1596 ( optlc_net_1612 ) , .p1597 ( optlc_net_1613 ) ,
+ .p1598 ( optlc_net_1614 ) , .p1599 ( optlc_net_1615 ) ,
+ .p1600 ( optlc_net_1616 ) , .p1601 ( optlc_net_1617 ) ,
+ .p1602 ( optlc_net_1618 ) , .p1603 ( optlc_net_1619 ) ,
+ .p1604 ( optlc_net_1620 ) , .p1605 ( optlc_net_1621 ) ,
+ .p1606 ( optlc_net_1622 ) , .p1607 ( optlc_net_1623 ) ,
+ .p1608 ( optlc_net_1624 ) , .p1609 ( optlc_net_1625 ) ,
+ .p1610 ( optlc_net_1626 ) , .p1611 ( optlc_net_1627 ) ,
+ .p1612 ( optlc_net_1628 ) , .p1613 ( optlc_net_1629 ) ,
+ .p1614 ( optlc_net_1630 ) , .p1615 ( optlc_net_1631 ) ,
+ .p1616 ( optlc_net_1632 ) , .p1617 ( optlc_net_1633 ) ,
+ .p1618 ( optlc_net_1634 ) , .p1619 ( optlc_net_1635 ) ,
+ .p1620 ( optlc_net_1636 ) , .p1621 ( optlc_net_1637 ) ,
+ .p1622 ( optlc_net_1638 ) , .p1623 ( optlc_net_1639 ) ,
+ .p1624 ( optlc_net_1640 ) , .p1625 ( optlc_net_1641 ) ,
+ .p1626 ( optlc_net_1642 ) , .p1627 ( optlc_net_1643 ) ,
+ .p1628 ( optlc_net_1644 ) , .p1629 ( optlc_net_1645 ) ,
+ .p1630 ( optlc_net_1646 ) , .p1631 ( optlc_net_1647 ) ,
+ .p1632 ( optlc_net_1648 ) , .p1633 ( optlc_net_1649 ) ,
+ .p1634 ( optlc_net_1650 ) , .p1635 ( optlc_net_1651 ) ,
+ .p1636 ( optlc_net_1652 ) , .p1637 ( optlc_net_1653 ) ,
+ .p1638 ( optlc_net_1654 ) , .p1639 ( optlc_net_1655 ) ,
+ .p1640 ( optlc_net_1656 ) , .p1641 ( optlc_net_1657 ) ,
+ .p1642 ( optlc_net_1658 ) , .p1643 ( optlc_net_1659 ) ,
+ .p1644 ( optlc_net_1660 ) , .p1645 ( optlc_net_1661 ) ,
+ .p1646 ( optlc_net_1662 ) , .p1647 ( optlc_net_1663 ) ,
+ .p1648 ( optlc_net_1664 ) , .p1649 ( optlc_net_1665 ) ,
+ .p1650 ( optlc_net_1666 ) , .p1651 ( optlc_net_1667 ) ,
+ .p1652 ( optlc_net_1668 ) , .p1653 ( optlc_net_1669 ) ,
+ .p1654 ( optlc_net_1670 ) , .p1655 ( optlc_net_1671 ) ,
+ .p1656 ( optlc_net_1672 ) , .p1657 ( optlc_net_1673 ) ,
+ .p1658 ( optlc_net_1674 ) , .p1659 ( optlc_net_1675 ) ,
+ .p1660 ( optlc_net_1676 ) , .p1661 ( optlc_net_1677 ) ,
+ .p1662 ( optlc_net_1678 ) , .p1663 ( optlc_net_1679 ) ,
+ .p1664 ( optlc_net_1680 ) , .p1665 ( optlc_net_1681 ) ,
+ .p1666 ( optlc_net_1682 ) , .p1667 ( optlc_net_1683 ) ,
+ .p1668 ( optlc_net_1684 ) , .p1669 ( optlc_net_1685 ) ,
+ .p1670 ( optlc_net_1686 ) , .p1671 ( optlc_net_1687 ) ,
+ .p1672 ( optlc_net_1688 ) , .p1673 ( optlc_net_1689 ) ,
+ .p1674 ( optlc_net_1690 ) , .p1675 ( optlc_net_1691 ) ,
+ .p1676 ( optlc_net_1692 ) , .p1677 ( optlc_net_1693 ) ,
+ .p1678 ( optlc_net_1694 ) , .p1679 ( optlc_net_1695 ) ,
+ .p1680 ( optlc_net_1696 ) , .p1681 ( optlc_net_1697 ) ,
+ .p1682 ( optlc_net_1698 ) , .p1683 ( optlc_net_1699 ) ,
+ .p1684 ( optlc_net_1700 ) , .p1685 ( optlc_net_1701 ) ,
+ .p1686 ( optlc_net_1702 ) , .p1687 ( optlc_net_1703 ) ,
+ .p1688 ( optlc_net_1704 ) , .p1689 ( optlc_net_1705 ) ,
+ .p1690 ( optlc_net_1706 ) , .p1691 ( optlc_net_1707 ) ,
+ .p1692 ( optlc_net_1708 ) , .p1693 ( optlc_net_1709 ) ,
+ .p1694 ( optlc_net_1710 ) , .p1695 ( optlc_net_1711 ) ,
+ .p1696 ( optlc_net_1712 ) , .p1697 ( optlc_net_1713 ) ,
+ .p1698 ( optlc_net_1714 ) , .p1699 ( optlc_net_1715 ) ,
+ .p1700 ( optlc_net_1716 ) , .p1701 ( optlc_net_1717 ) ,
+ .p1702 ( optlc_net_1718 ) , .p1703 ( optlc_net_1719 ) ,
+ .p1704 ( optlc_net_1720 ) , .p1705 ( optlc_net_1721 ) ,
+ .p1706 ( optlc_net_1722 ) , .p1707 ( optlc_net_1723 ) ,
+ .p1708 ( optlc_net_1724 ) , .p1709 ( optlc_net_1725 ) ,
+ .p1710 ( optlc_net_1726 ) , .p1711 ( optlc_net_1727 ) ,
+ .p1712 ( optlc_net_1728 ) , .p1713 ( optlc_net_1729 ) ,
+ .p1714 ( optlc_net_1730 ) , .p1715 ( optlc_net_1731 ) ,
+ .p1716 ( optlc_net_1732 ) , .p1717 ( optlc_net_1733 ) ,
+ .p1718 ( optlc_net_1734 ) , .p1719 ( optlc_net_1735 ) ,
+ .p1720 ( optlc_net_1736 ) , .p1721 ( optlc_net_1737 ) ,
+ .p1722 ( optlc_net_1738 ) , .p1723 ( optlc_net_1739 ) ,
+ .p1724 ( optlc_net_1740 ) , .p1725 ( optlc_net_1741 ) ,
+ .p1726 ( optlc_net_1742 ) , .p1727 ( optlc_net_1743 ) ,
+ .p1728 ( optlc_net_1744 ) , .p1729 ( optlc_net_1745 ) ,
+ .p1730 ( optlc_net_1746 ) , .p1731 ( optlc_net_1747 ) ,
+ .p1732 ( optlc_net_1748 ) , .p1733 ( optlc_net_1749 ) ,
+ .p1734 ( optlc_net_1750 ) , .p1735 ( optlc_net_1751 ) ,
+ .p1736 ( optlc_net_1752 ) , .p1737 ( optlc_net_1753 ) ,
+ .p1738 ( optlc_net_1754 ) , .p1739 ( optlc_net_1755 ) ,
+ .p1740 ( optlc_net_1756 ) , .p1741 ( optlc_net_1757 ) ,
+ .p1742 ( optlc_net_1758 ) , .p1743 ( optlc_net_1759 ) ,
+ .p1744 ( optlc_net_1760 ) , .p1745 ( optlc_net_1761 ) ,
+ .p1746 ( optlc_net_1762 ) , .p1747 ( optlc_net_1763 ) ,
+ .p1748 ( optlc_net_1764 ) , .p1749 ( optlc_net_1765 ) ,
+ .p1750 ( optlc_net_1766 ) , .p1751 ( optlc_net_1767 ) ,
+ .p1752 ( optlc_net_1768 ) , .p1753 ( optlc_net_1769 ) ,
+ .p1754 ( optlc_net_1770 ) , .p1755 ( optlc_net_1771 ) ,
+ .p1756 ( optlc_net_1772 ) , .p1757 ( optlc_net_1773 ) ,
+ .p1758 ( optlc_net_1774 ) , .p1759 ( optlc_net_1775 ) ,
+ .p1760 ( optlc_net_1776 ) , .p1761 ( optlc_net_1777 ) ,
+ .p1762 ( optlc_net_1778 ) , .p1763 ( optlc_net_1779 ) ,
+ .p1764 ( optlc_net_1780 ) , .p1765 ( optlc_net_1781 ) ,
+ .p1766 ( optlc_net_1782 ) , .p1767 ( optlc_net_1783 ) ,
+ .p1768 ( optlc_net_1784 ) , .p1769 ( optlc_net_1785 ) ,
+ .p1770 ( optlc_net_1786 ) , .p1771 ( optlc_net_1787 ) ,
+ .p1772 ( optlc_net_1788 ) , .p1773 ( optlc_net_1789 ) ,
+ .p1774 ( optlc_net_1790 ) , .p1775 ( optlc_net_1791 ) ,
+ .p1776 ( optlc_net_1792 ) , .p1777 ( optlc_net_1793 ) ,
+ .p1778 ( optlc_net_1794 ) , .p1779 ( optlc_net_1795 ) ,
+ .p1780 ( optlc_net_1796 ) , .p1781 ( optlc_net_1797 ) ,
+ .p1782 ( optlc_net_1798 ) , .p1783 ( optlc_net_1799 ) ,
+ .p1784 ( optlc_net_1800 ) , .p1785 ( optlc_net_1801 ) ,
+ .p1786 ( optlc_net_1802 ) , .p1787 ( optlc_net_1803 ) ,
+ .p1788 ( optlc_net_1804 ) , .p1789 ( optlc_net_1805 ) ,
+ .p1790 ( optlc_net_1806 ) , .p1791 ( optlc_net_1807 ) ,
+ .p1792 ( optlc_net_1808 ) , .p1793 ( optlc_net_1809 ) ,
+ .p1794 ( optlc_net_1810 ) , .p1795 ( optlc_net_1811 ) ,
+ .p1796 ( optlc_net_1812 ) , .p1797 ( optlc_net_1813 ) ,
+ .p1798 ( optlc_net_1814 ) , .p1799 ( optlc_net_1815 ) ,
+ .p1800 ( optlc_net_1816 ) , .p1801 ( optlc_net_1817 ) ,
+ .p1802 ( optlc_net_1818 ) , .p1803 ( optlc_net_1819 ) ,
+ .p1804 ( optlc_net_1820 ) , .p1805 ( optlc_net_1821 ) ,
+ .p1806 ( optlc_net_1822 ) , .p1807 ( optlc_net_1823 ) ,
+ .p1808 ( optlc_net_1824 ) , .p1809 ( optlc_net_1825 ) ,
+ .p1810 ( optlc_net_1826 ) , .p1811 ( optlc_net_1827 ) ,
+ .p1812 ( optlc_net_1828 ) , .p1813 ( optlc_net_1829 ) ,
+ .p1814 ( optlc_net_1830 ) , .p1815 ( optlc_net_1831 ) ,
+ .p1816 ( optlc_net_1832 ) , .p1817 ( optlc_net_1833 ) ,
+ .p1818 ( optlc_net_1834 ) , .p1819 ( optlc_net_1835 ) ,
+ .p1820 ( optlc_net_1836 ) , .p1821 ( optlc_net_1837 ) ,
+ .p1822 ( optlc_net_1838 ) , .p1823 ( optlc_net_1839 ) ,
+ .p1824 ( optlc_net_1840 ) , .p1825 ( optlc_net_1841 ) ,
+ .p1826 ( optlc_net_1842 ) , .p1827 ( optlc_net_1843 ) ,
+ .p1828 ( optlc_net_1844 ) , .p1829 ( optlc_net_1845 ) ,
+ .p1830 ( optlc_net_1846 ) , .p1831 ( optlc_net_1847 ) ,
+ .p1832 ( optlc_net_1848 ) , .p1833 ( optlc_net_1849 ) ,
+ .p1834 ( optlc_net_1850 ) , .p1835 ( optlc_net_1851 ) ,
+ .p1836 ( optlc_net_1852 ) , .p1837 ( optlc_net_1853 ) ,
+ .p1838 ( optlc_net_1854 ) , .p1839 ( optlc_net_1855 ) ,
+ .p1840 ( optlc_net_1856 ) , .p1841 ( optlc_net_1857 ) ,
+ .p1842 ( optlc_net_1858 ) , .p1843 ( optlc_net_1859 ) ,
+ .p1844 ( optlc_net_1860 ) , .p1845 ( optlc_net_1861 ) ,
+ .p1846 ( optlc_net_1862 ) , .p1847 ( optlc_net_1863 ) ,
+ .p1848 ( optlc_net_1864 ) , .p1849 ( optlc_net_1865 ) ,
+ .p1850 ( optlc_net_1866 ) , .p1851 ( optlc_net_1867 ) ,
+ .p1852 ( optlc_net_1868 ) , .p1853 ( optlc_net_1869 ) ,
+ .p1854 ( optlc_net_1870 ) , .p1855 ( optlc_net_1871 ) ,
+ .p1856 ( optlc_net_1872 ) , .p1857 ( optlc_net_1873 ) ,
+ .p1858 ( optlc_net_1874 ) , .p1859 ( optlc_net_1875 ) ,
+ .p1860 ( optlc_net_1876 ) , .p1861 ( optlc_net_1877 ) ,
+ .p1862 ( optlc_net_1878 ) , .p1863 ( optlc_net_1879 ) ,
+ .p1864 ( optlc_net_1880 ) , .p1865 ( optlc_net_1881 ) ,
+ .p1866 ( optlc_net_1882 ) , .p1867 ( optlc_net_1883 ) ,
+ .p1868 ( optlc_net_1884 ) , .p1869 ( optlc_net_1885 ) ,
+ .p1870 ( optlc_net_1886 ) , .p1871 ( optlc_net_1887 ) ,
+ .p1872 ( optlc_net_1888 ) , .p1873 ( optlc_net_1889 ) ,
+ .p1874 ( optlc_net_1890 ) , .p1875 ( optlc_net_1891 ) ,
+ .p1876 ( optlc_net_1892 ) , .p1877 ( optlc_net_1893 ) ,
+ .p1878 ( optlc_net_1894 ) , .p1879 ( optlc_net_1895 ) ,
+ .p1880 ( optlc_net_1896 ) , .p1881 ( optlc_net_1897 ) ,
+ .p1882 ( optlc_net_1898 ) , .p1883 ( optlc_net_1899 ) ,
+ .p1884 ( optlc_net_1900 ) , .p1885 ( optlc_net_1901 ) ,
+ .p1886 ( optlc_net_1902 ) , .p1887 ( optlc_net_1903 ) ,
+ .p1888 ( optlc_net_1904 ) , .p1889 ( optlc_net_1905 ) ,
+ .p1890 ( optlc_net_1906 ) , .p1891 ( optlc_net_1907 ) ,
+ .p1892 ( optlc_net_1908 ) , .p1893 ( optlc_net_1909 ) ,
+ .p1894 ( optlc_net_1910 ) , .p1895 ( optlc_net_1911 ) ,
+ .p1896 ( optlc_net_1912 ) , .p1897 ( optlc_net_1913 ) ,
+ .p1898 ( optlc_net_1914 ) , .p1899 ( optlc_net_1915 ) ,
+ .p1900 ( optlc_net_1916 ) , .p1901 ( optlc_net_1917 ) ,
+ .p1902 ( optlc_net_1918 ) , .p1903 ( optlc_net_1919 ) ,
+ .p1904 ( optlc_net_1920 ) , .p1905 ( optlc_net_1921 ) ,
+ .p1906 ( optlc_net_1922 ) , .p1907 ( optlc_net_1923 ) ,
+ .p1908 ( optlc_net_1924 ) , .p1909 ( optlc_net_1925 ) ,
+ .p1910 ( optlc_net_1926 ) , .p1911 ( optlc_net_1927 ) ,
+ .p1912 ( optlc_net_1928 ) , .p1913 ( optlc_net_1929 ) ,
+ .p1914 ( optlc_net_1930 ) , .p1915 ( optlc_net_1931 ) ,
+ .p1916 ( optlc_net_1932 ) , .p1917 ( optlc_net_1933 ) ,
+ .p1918 ( optlc_net_1934 ) , .p1919 ( optlc_net_1935 ) ,
+ .p1920 ( optlc_net_1936 ) , .p1921 ( optlc_net_1937 ) ,
+ .p1922 ( optlc_net_1938 ) , .p1923 ( optlc_net_1939 ) ,
+ .p1924 ( optlc_net_1940 ) , .p1925 ( optlc_net_1941 ) ,
+ .p1926 ( optlc_net_1942 ) , .p1927 ( optlc_net_1943 ) ,
+ .p1928 ( optlc_net_1944 ) , .p1929 ( optlc_net_1945 ) ,
+ .p1930 ( optlc_net_1946 ) , .p1931 ( optlc_net_1947 ) ,
+ .p1932 ( optlc_net_1948 ) , .p1933 ( optlc_net_1949 ) ,
+ .p1934 ( optlc_net_1950 ) , .p1935 ( optlc_net_1951 ) ,
+ .p1936 ( optlc_net_1952 ) , .p1937 ( optlc_net_1953 ) ,
+ .p1938 ( optlc_net_1954 ) , .p1939 ( optlc_net_1955 ) ,
+ .p1940 ( optlc_net_1956 ) , .p1941 ( optlc_net_1957 ) ,
+ .p1942 ( optlc_net_1958 ) , .p1943 ( optlc_net_1959 ) ,
+ .p1944 ( optlc_net_1960 ) , .p1945 ( optlc_net_1961 ) ,
+ .p1946 ( optlc_net_1962 ) , .p1947 ( optlc_net_1963 ) ,
+ .p1948 ( optlc_net_1964 ) , .p1949 ( optlc_net_1965 ) ,
+ .p1950 ( optlc_net_1966 ) , .p1951 ( optlc_net_1967 ) ,
+ .p1952 ( optlc_net_1968 ) , .p1953 ( optlc_net_1969 ) ,
+ .p1954 ( optlc_net_1970 ) , .p1955 ( optlc_net_1971 ) ,
+ .p1956 ( optlc_net_1972 ) , .p1957 ( optlc_net_1973 ) ,
+ .p1958 ( optlc_net_1974 ) , .p1959 ( optlc_net_1975 ) ,
+ .p1960 ( optlc_net_1976 ) , .p1961 ( optlc_net_1977 ) ,
+ .p1962 ( optlc_net_1978 ) , .p1963 ( optlc_net_1979 ) ,
+ .p1964 ( optlc_net_1980 ) , .p1965 ( optlc_net_1981 ) ,
+ .p1966 ( optlc_net_1982 ) , .p1967 ( optlc_net_1983 ) ,
+ .p1968 ( optlc_net_1984 ) , .p1969 ( optlc_net_1985 ) ,
+ .p1970 ( optlc_net_1986 ) , .p1971 ( optlc_net_1987 ) ,
+ .p1972 ( optlc_net_1988 ) , .p1973 ( optlc_net_1989 ) ,
+ .p1974 ( optlc_net_1990 ) , .p1975 ( optlc_net_1991 ) ,
+ .p1976 ( optlc_net_1992 ) , .p1977 ( optlc_net_1993 ) ,
+ .p1978 ( optlc_net_1994 ) , .p1979 ( optlc_net_1995 ) ,
+ .p1980 ( optlc_net_1996 ) , .p1981 ( optlc_net_1997 ) ,
+ .p1982 ( optlc_net_1998 ) , .p1983 ( optlc_net_1999 ) ,
+ .p1984 ( optlc_net_2000 ) , .p1985 ( optlc_net_2001 ) ,
+ .p1986 ( optlc_net_2002 ) , .p1987 ( optlc_net_2003 ) ,
+ .p1988 ( optlc_net_2004 ) , .p1989 ( optlc_net_2005 ) ,
+ .p1990 ( optlc_net_2006 ) , .p1991 ( optlc_net_2007 ) ,
+ .p1992 ( optlc_net_2008 ) , .p1993 ( optlc_net_2009 ) ,
+ .p1994 ( optlc_net_2010 ) , .p1995 ( optlc_net_2011 ) ,
+ .p1996 ( optlc_net_2012 ) , .p1997 ( optlc_net_2013 ) ,
+ .p1998 ( optlc_net_2014 ) , .p1999 ( optlc_net_2015 ) ,
+ .p2000 ( optlc_net_2016 ) , .p2001 ( optlc_net_2017 ) ,
+ .p2002 ( optlc_net_2018 ) , .p2003 ( optlc_net_2019 ) ,
+ .p2004 ( optlc_net_2020 ) , .p2005 ( optlc_net_2021 ) ,
+ .p2006 ( optlc_net_2022 ) , .p2007 ( optlc_net_2023 ) ,
+ .p2008 ( optlc_net_2024 ) , .p2009 ( optlc_net_2025 ) ,
+ .p2010 ( optlc_net_2026 ) , .p2011 ( optlc_net_2027 ) ,
+ .p2012 ( optlc_net_2028 ) , .p2013 ( optlc_net_2029 ) ,
+ .p2014 ( optlc_net_2030 ) , .p2015 ( optlc_net_2031 ) ,
+ .p2016 ( optlc_net_2032 ) , .p2017 ( optlc_net_2033 ) ,
+ .p2018 ( optlc_net_2034 ) , .p2019 ( optlc_net_2035 ) ,
+ .p2020 ( optlc_net_2036 ) , .p2021 ( optlc_net_2037 ) ,
+ .p2022 ( optlc_net_2038 ) , .p2023 ( optlc_net_2039 ) ,
+ .p2024 ( optlc_net_2040 ) , .p2025 ( optlc_net_2041 ) ,
+ .p2026 ( optlc_net_2042 ) , .p2027 ( optlc_net_2043 ) ,
+ .p2028 ( optlc_net_2044 ) , .p2029 ( optlc_net_2045 ) ,
+ .p2030 ( optlc_net_2046 ) , .p2031 ( optlc_net_2047 ) ,
+ .p2032 ( optlc_net_2048 ) , .p2033 ( optlc_net_2049 ) ,
+ .p2034 ( optlc_net_2050 ) , .p2035 ( optlc_net_2051 ) ,
+ .p2036 ( optlc_net_2052 ) , .p2037 ( optlc_net_2053 ) ,
+ .p2038 ( optlc_net_2054 ) , .p2039 ( optlc_net_2055 ) ,
+ .p2040 ( optlc_net_2056 ) , .p2041 ( optlc_net_2057 ) ,
+ .p2042 ( optlc_net_2058 ) , .p2043 ( optlc_net_2059 ) ,
+ .p2044 ( optlc_net_2060 ) , .p2045 ( optlc_net_2061 ) ,
+ .p2046 ( optlc_net_2062 ) , .p2047 ( optlc_net_2063 ) ,
+ .p2048 ( optlc_net_2064 ) , .p2049 ( optlc_net_2065 ) ,
+ .p2050 ( optlc_net_2066 ) , .p2051 ( optlc_net_2067 ) ,
+ .p2052 ( optlc_net_2068 ) , .p2053 ( optlc_net_2069 ) ,
+ .p2054 ( optlc_net_2070 ) , .p2055 ( optlc_net_2071 ) ,
+ .p2056 ( optlc_net_2072 ) , .p2057 ( optlc_net_2073 ) ,
+ .p2058 ( optlc_net_2074 ) , .p2059 ( optlc_net_2075 ) ,
+ .p2060 ( optlc_net_2076 ) , .p2061 ( optlc_net_2077 ) ,
+ .p2062 ( optlc_net_2078 ) , .p2063 ( optlc_net_2079 ) ,
+ .p2064 ( optlc_net_2080 ) , .p2065 ( optlc_net_2081 ) ,
+ .p2066 ( optlc_net_2082 ) , .p2067 ( optlc_net_2083 ) ,
+ .p2068 ( optlc_net_2084 ) , .p2069 ( optlc_net_2085 ) ,
+ .p2070 ( optlc_net_2086 ) , .p2071 ( optlc_net_2087 ) ,
+ .p2072 ( optlc_net_2088 ) , .p2073 ( optlc_net_2089 ) ,
+ .p2074 ( optlc_net_2090 ) , .p2075 ( optlc_net_2091 ) ,
+ .p2076 ( optlc_net_2092 ) , .p2077 ( optlc_net_2093 ) ,
+ .p2078 ( optlc_net_2094 ) , .p2079 ( optlc_net_2095 ) ,
+ .p2080 ( optlc_net_2096 ) , .p2081 ( optlc_net_2097 ) ,
+ .p2082 ( optlc_net_2098 ) , .p2083 ( optlc_net_2099 ) ,
+ .p2084 ( optlc_net_2100 ) , .p2085 ( optlc_net_2101 ) ,
+ .p2086 ( optlc_net_2102 ) , .p2087 ( optlc_net_2103 ) ,
+ .p2088 ( optlc_net_2104 ) , .p2089 ( optlc_net_2105 ) ,
+ .p2090 ( optlc_net_2106 ) , .p2091 ( optlc_net_2107 ) ,
+ .p2092 ( optlc_net_2108 ) , .p2093 ( optlc_net_2109 ) ,
+ .p2094 ( optlc_net_2110 ) , .p2095 ( optlc_net_2111 ) ,
+ .p2096 ( optlc_net_2112 ) , .p2097 ( optlc_net_2113 ) ,
+ .p2098 ( optlc_net_2114 ) , .p2099 ( optlc_net_2115 ) ,
+ .p2100 ( optlc_net_2116 ) , .p2101 ( optlc_net_2117 ) ,
+ .p2102 ( optlc_net_2118 ) , .p2103 ( optlc_net_2119 ) ,
+ .p2104 ( optlc_net_2120 ) , .p2105 ( optlc_net_2121 ) ,
+ .p2106 ( optlc_net_2122 ) , .p2107 ( optlc_net_2123 ) ,
+ .p2108 ( optlc_net_2124 ) , .p2109 ( optlc_net_2125 ) ,
+ .p2110 ( optlc_net_2126 ) , .p2111 ( optlc_net_2127 ) ,
+ .p2112 ( optlc_net_2128 ) , .p2113 ( optlc_net_2129 ) ,
+ .p2114 ( optlc_net_2130 ) , .p2115 ( optlc_net_2131 ) ,
+ .p2116 ( optlc_net_2132 ) , .p2117 ( optlc_net_2133 ) ,
+ .p2118 ( optlc_net_2134 ) , .p2119 ( optlc_net_2135 ) ,
+ .p2120 ( optlc_net_2136 ) , .p2121 ( optlc_net_2137 ) ,
+ .p2122 ( optlc_net_2138 ) , .p2123 ( optlc_net_2139 ) ,
+ .p2124 ( optlc_net_2140 ) , .p2125 ( optlc_net_2141 ) ,
+ .p2126 ( optlc_net_2142 ) , .p2127 ( optlc_net_2143 ) ,
+ .p2128 ( optlc_net_2144 ) , .p2129 ( optlc_net_2145 ) ,
+ .p2130 ( optlc_net_2146 ) , .p2131 ( optlc_net_2147 ) ,
+ .p2132 ( optlc_net_2148 ) , .p2133 ( optlc_net_2149 ) ,
+ .p2134 ( optlc_net_2150 ) , .p2135 ( optlc_net_2151 ) ,
+ .p2136 ( optlc_net_2152 ) , .p2137 ( optlc_net_2153 ) ,
+ .p2138 ( optlc_net_2154 ) , .p2139 ( optlc_net_2155 ) ,
+ .p2140 ( optlc_net_2156 ) , .p2141 ( optlc_net_2157 ) ,
+ .p2142 ( optlc_net_2158 ) , .p2143 ( optlc_net_2159 ) ,
+ .p2144 ( optlc_net_2160 ) , .p2145 ( optlc_net_2161 ) ,
+ .p2146 ( optlc_net_2162 ) , .p2147 ( optlc_net_2163 ) ,
+ .p2148 ( optlc_net_2164 ) , .p2149 ( optlc_net_2165 ) ,
+ .p2150 ( optlc_net_2166 ) , .p2151 ( optlc_net_2167 ) ,
+ .p2152 ( optlc_net_2168 ) , .p2153 ( optlc_net_2169 ) ,
+ .p2154 ( optlc_net_2170 ) , .p2155 ( optlc_net_2171 ) ,
+ .p2156 ( optlc_net_2172 ) , .p2157 ( optlc_net_2173 ) ,
+ .p2158 ( optlc_net_2174 ) , .p2159 ( optlc_net_2175 ) ,
+ .p2160 ( optlc_net_2176 ) , .p2161 ( optlc_net_2177 ) ,
+ .p2162 ( optlc_net_2178 ) , .p2163 ( optlc_net_2179 ) ,
+ .p2164 ( optlc_net_2180 ) , .p2165 ( optlc_net_2181 ) ,
+ .p2166 ( optlc_net_2182 ) , .p2167 ( optlc_net_2183 ) ,
+ .p2168 ( optlc_net_2184 ) , .p2169 ( optlc_net_2185 ) ,
+ .p2170 ( optlc_net_2186 ) , .p2171 ( optlc_net_2187 ) ,
+ .p2172 ( optlc_net_2188 ) , .p2173 ( optlc_net_2189 ) ,
+ .p2174 ( optlc_net_2190 ) , .p2175 ( optlc_net_2191 ) ,
+ .p2176 ( optlc_net_2192 ) , .p2177 ( optlc_net_2193 ) ,
+ .p2178 ( optlc_net_2194 ) , .p2179 ( optlc_net_2195 ) ,
+ .p2180 ( optlc_net_2196 ) , .p2181 ( optlc_net_2197 ) ,
+ .p2182 ( optlc_net_2198 ) , .p2183 ( optlc_net_2199 ) ,
+ .p2184 ( optlc_net_2200 ) , .p2185 ( optlc_net_2201 ) ,
+ .p2186 ( optlc_net_2202 ) , .p2187 ( optlc_net_2203 ) ,
+ .p2188 ( optlc_net_2204 ) , .p2189 ( optlc_net_2205 ) ,
+ .p2190 ( optlc_net_2206 ) , .p2191 ( optlc_net_2207 ) ,
+ .p2192 ( optlc_net_2208 ) , .p2193 ( optlc_net_2209 ) ,
+ .p2194 ( optlc_net_2210 ) , .p2195 ( optlc_net_2211 ) ,
+ .p2196 ( optlc_net_2212 ) , .p2197 ( optlc_net_2213 ) ,
+ .p2198 ( optlc_net_2214 ) , .p2199 ( optlc_net_2215 ) ,
+ .p2200 ( optlc_net_2216 ) , .p2201 ( optlc_net_2217 ) ,
+ .p2202 ( optlc_net_2218 ) , .p2203 ( optlc_net_2219 ) ,
+ .p2204 ( optlc_net_2220 ) , .p2205 ( optlc_net_2221 ) ,
+ .p2206 ( optlc_net_2222 ) , .p2207 ( optlc_net_2223 ) ,
+ .p2208 ( optlc_net_2224 ) , .p2209 ( optlc_net_2225 ) ,
+ .p2210 ( optlc_net_2226 ) , .p2211 ( optlc_net_2227 ) ,
+ .p2212 ( optlc_net_2228 ) , .p2213 ( optlc_net_2229 ) ,
+ .p2214 ( optlc_net_2230 ) , .p2215 ( optlc_net_2231 ) ,
+ .p2216 ( optlc_net_2232 ) , .p2217 ( optlc_net_2233 ) ,
+ .p2218 ( optlc_net_2234 ) , .p2219 ( optlc_net_2235 ) ,
+ .p2220 ( optlc_net_2236 ) , .p2221 ( optlc_net_2237 ) ,
+ .p2222 ( optlc_net_2238 ) , .p2223 ( optlc_net_2239 ) ,
+ .p2224 ( optlc_net_2240 ) , .p2225 ( optlc_net_2241 ) ,
+ .p2226 ( optlc_net_2242 ) , .p2227 ( optlc_net_2243 ) ,
+ .p2228 ( optlc_net_2244 ) , .p2229 ( optlc_net_2245 ) ,
+ .p2230 ( optlc_net_2246 ) , .p2231 ( optlc_net_2247 ) ,
+ .p2232 ( optlc_net_2248 ) , .p2233 ( optlc_net_2249 ) ,
+ .p2234 ( optlc_net_2250 ) , .p2235 ( optlc_net_2251 ) ,
+ .p2236 ( optlc_net_2252 ) , .p2237 ( optlc_net_2253 ) ,
+ .p2238 ( optlc_net_2254 ) , .p2239 ( optlc_net_2255 ) ,
+ .p2240 ( optlc_net_2256 ) , .p2241 ( optlc_net_2257 ) ,
+ .p2242 ( optlc_net_2258 ) , .p2243 ( optlc_net_2259 ) ,
+ .p2244 ( optlc_net_2260 ) , .p2245 ( optlc_net_2261 ) ,
+ .p2246 ( optlc_net_2262 ) , .p2247 ( optlc_net_2263 ) ,
+ .p2248 ( optlc_net_2264 ) , .p2249 ( optlc_net_2265 ) ,
+ .p2250 ( optlc_net_2266 ) , .p2251 ( optlc_net_2267 ) ,
+ .p2252 ( optlc_net_2268 ) , .p2253 ( optlc_net_2269 ) ,
+ .p2254 ( optlc_net_2270 ) , .p2255 ( optlc_net_2271 ) ,
+ .p2256 ( optlc_net_2272 ) , .p2257 ( optlc_net_2273 ) ,
+ .p2258 ( optlc_net_2274 ) , .p2259 ( optlc_net_2275 ) ,
+ .p2260 ( optlc_net_2276 ) , .p2261 ( optlc_net_2277 ) ,
+ .p2262 ( optlc_net_2278 ) , .p2263 ( optlc_net_2279 ) ,
+ .p2264 ( optlc_net_2280 ) , .p2265 ( optlc_net_2281 ) ,
+ .p2266 ( optlc_net_2282 ) , .p2267 ( optlc_net_2283 ) ,
+ .p2268 ( optlc_net_2284 ) , .p2269 ( optlc_net_2285 ) ,
+ .p2270 ( optlc_net_2286 ) , .p2271 ( optlc_net_2287 ) ,
+ .p2272 ( optlc_net_2288 ) , .p2273 ( optlc_net_2289 ) ,
+ .p2274 ( optlc_net_2290 ) , .p2275 ( optlc_net_2291 ) ,
+ .p2276 ( optlc_net_2292 ) , .p2277 ( optlc_net_2293 ) ,
+ .p2278 ( optlc_net_2294 ) , .p2279 ( optlc_net_2295 ) ,
+ .p2280 ( optlc_net_2296 ) , .p2281 ( optlc_net_2297 ) ,
+ .p2282 ( optlc_net_2298 ) , .p2283 ( optlc_net_2299 ) ,
+ .p2284 ( optlc_net_2300 ) , .p2285 ( optlc_net_2301 ) ,
+ .p2286 ( optlc_net_2302 ) , .p2287 ( optlc_net_2303 ) ,
+ .p2288 ( optlc_net_2304 ) , .p2289 ( optlc_net_2305 ) ,
+ .p2290 ( optlc_net_2306 ) , .p2291 ( optlc_net_2307 ) ,
+ .p2292 ( optlc_net_2308 ) , .p2293 ( optlc_net_2309 ) ,
+ .p2294 ( optlc_net_2310 ) , .p2295 ( optlc_net_2311 ) ,
+ .p2296 ( optlc_net_2312 ) , .p2297 ( optlc_net_2313 ) ,
+ .p2298 ( optlc_net_2314 ) , .p2299 ( optlc_net_2315 ) ,
+ .p2300 ( optlc_net_2316 ) , .p2301 ( optlc_net_2317 ) ,
+ .p2302 ( optlc_net_2318 ) , .p2303 ( optlc_net_2319 ) ,
+ .p2304 ( optlc_net_2320 ) , .p2305 ( optlc_net_2321 ) ,
+ .p2306 ( optlc_net_2322 ) , .p2307 ( optlc_net_2323 ) ,
+ .p2308 ( optlc_net_2324 ) , .p2309 ( optlc_net_2325 ) ,
+ .p2310 ( optlc_net_2326 ) , .p2311 ( optlc_net_2327 ) ,
+ .p2312 ( optlc_net_2328 ) , .p2313 ( optlc_net_2329 ) ,
+ .p2314 ( optlc_net_2330 ) , .p2315 ( optlc_net_2331 ) ,
+ .p2316 ( optlc_net_2332 ) , .p2317 ( optlc_net_2333 ) ,
+ .p2318 ( optlc_net_2334 ) , .p2319 ( optlc_net_2335 ) ,
+ .p2320 ( optlc_net_2336 ) , .p2321 ( optlc_net_2337 ) ,
+ .p2322 ( optlc_net_2338 ) , .p2323 ( optlc_net_2339 ) ,
+ .p2324 ( optlc_net_2340 ) , .p2325 ( optlc_net_2341 ) ,
+ .p2326 ( optlc_net_2342 ) , .p2327 ( optlc_net_2343 ) ,
+ .p2328 ( optlc_net_2344 ) , .p2329 ( optlc_net_2345 ) ,
+ .p2330 ( optlc_net_2346 ) , .p2331 ( optlc_net_2347 ) ,
+ .p2332 ( optlc_net_2348 ) , .p2333 ( optlc_net_2349 ) ,
+ .p2334 ( optlc_net_2350 ) , .p2335 ( optlc_net_2351 ) ,
+ .p2336 ( optlc_net_2352 ) , .p2337 ( optlc_net_2353 ) ,
+ .p2338 ( optlc_net_2354 ) , .p2339 ( optlc_net_2355 ) ,
+ .p2340 ( optlc_net_2356 ) , .p2341 ( optlc_net_2357 ) ,
+ .p2342 ( optlc_net_2358 ) , .p2343 ( optlc_net_2359 ) ,
+ .p2344 ( optlc_net_2360 ) , .p2345 ( optlc_net_2361 ) ,
+ .p2346 ( optlc_net_2362 ) , .p2347 ( optlc_net_2363 ) ,
+ .p2348 ( optlc_net_2364 ) , .p2349 ( optlc_net_2365 ) ,
+ .p2350 ( optlc_net_2366 ) , .p2351 ( optlc_net_2367 ) ,
+ .p2352 ( optlc_net_2368 ) , .p2353 ( optlc_net_2369 ) ,
+ .p2354 ( optlc_net_2370 ) , .p2355 ( optlc_net_2371 ) ,
+ .p2356 ( optlc_net_2372 ) , .p2357 ( optlc_net_2373 ) ,
+ .p2358 ( optlc_net_2374 ) , .p2359 ( optlc_net_2375 ) ,
+ .p2360 ( optlc_net_2376 ) , .p2361 ( optlc_net_2377 ) ,
+ .p2362 ( optlc_net_2378 ) , .p2363 ( optlc_net_2379 ) ,
+ .p2364 ( optlc_net_2380 ) , .p2365 ( optlc_net_2381 ) ,
+ .p2366 ( optlc_net_2382 ) , .p2367 ( optlc_net_2383 ) ,
+ .p2368 ( optlc_net_2384 ) , .p2369 ( optlc_net_2385 ) ,
+ .p2370 ( optlc_net_2386 ) , .p2371 ( optlc_net_2387 ) ,
+ .p2372 ( optlc_net_2388 ) , .p2373 ( optlc_net_2389 ) ,
+ .p2374 ( optlc_net_2390 ) , .p2375 ( optlc_net_2391 ) ,
+ .p2376 ( optlc_net_2392 ) , .p2377 ( optlc_net_2393 ) ,
+ .p2378 ( optlc_net_2394 ) , .p2379 ( optlc_net_2395 ) ,
+ .p2380 ( optlc_net_2396 ) , .p2381 ( optlc_net_2397 ) ,
+ .p2382 ( optlc_net_2398 ) , .p2383 ( optlc_net_2399 ) ,
+ .p2384 ( optlc_net_2400 ) , .p2385 ( optlc_net_2401 ) ,
+ .p2386 ( optlc_net_2402 ) , .p2387 ( optlc_net_2403 ) ,
+ .p2388 ( optlc_net_2404 ) , .p2389 ( optlc_net_2405 ) ,
+ .p2390 ( optlc_net_2406 ) , .p2391 ( optlc_net_2407 ) ,
+ .p2392 ( optlc_net_2408 ) , .p2393 ( optlc_net_2409 ) ,
+ .p2394 ( optlc_net_2410 ) , .p2395 ( optlc_net_2411 ) ,
+ .p2396 ( optlc_net_2412 ) , .p2397 ( optlc_net_2413 ) ,
+ .p2398 ( optlc_net_2414 ) , .p2399 ( optlc_net_2415 ) ,
+ .p2400 ( optlc_net_2416 ) , .p2401 ( optlc_net_2417 ) ,
+ .p2402 ( optlc_net_2418 ) , .p2403 ( optlc_net_2419 ) ,
+ .p2404 ( optlc_net_2420 ) , .p2405 ( optlc_net_2421 ) ,
+ .p2406 ( optlc_net_2422 ) , .p2407 ( optlc_net_2423 ) ,
+ .p2408 ( optlc_net_2424 ) , .p2409 ( optlc_net_2425 ) ,
+ .p2410 ( optlc_net_2426 ) , .p2411 ( optlc_net_2427 ) ,
+ .p2412 ( optlc_net_2428 ) , .p2413 ( optlc_net_2429 ) ,
+ .p2414 ( optlc_net_2430 ) , .p2415 ( optlc_net_2431 ) ,
+ .p2416 ( optlc_net_2432 ) , .p2417 ( optlc_net_2433 ) ,
+ .p2418 ( optlc_net_2434 ) , .p2419 ( optlc_net_2435 ) ,
+ .p2420 ( optlc_net_2436 ) , .p2421 ( optlc_net_2437 ) ,
+ .p2422 ( optlc_net_2438 ) , .p2423 ( optlc_net_2439 ) ,
+ .p2424 ( optlc_net_2440 ) , .p2425 ( optlc_net_2441 ) ,
+ .p2426 ( optlc_net_2442 ) , .p2427 ( optlc_net_2443 ) ,
+ .p2428 ( optlc_net_2444 ) , .p2429 ( optlc_net_2445 ) ,
+ .p2430 ( optlc_net_2446 ) , .p2431 ( optlc_net_2447 ) ,
+ .p2432 ( optlc_net_2448 ) , .p2433 ( optlc_net_2449 ) ,
+ .p2434 ( optlc_net_2450 ) , .p2435 ( optlc_net_2451 ) ,
+ .p2436 ( optlc_net_2452 ) , .p2437 ( optlc_net_2453 ) ,
+ .p2438 ( optlc_net_2454 ) , .p2439 ( optlc_net_2455 ) ,
+ .p2440 ( optlc_net_2456 ) , .p2441 ( optlc_net_2457 ) ,
+ .p2442 ( optlc_net_2458 ) , .p2443 ( optlc_net_2459 ) ,
+ .p2444 ( optlc_net_2460 ) , .p2445 ( optlc_net_2461 ) ,
+ .p2446 ( optlc_net_2462 ) , .p2447 ( optlc_net_2463 ) ,
+ .p2448 ( optlc_net_2464 ) , .p2449 ( optlc_net_2465 ) ,
+ .p2450 ( optlc_net_2466 ) , .p2451 ( optlc_net_2467 ) ,
+ .p2452 ( optlc_net_2468 ) , .p2453 ( optlc_net_2469 ) ,
+ .p2454 ( optlc_net_2470 ) , .p2455 ( optlc_net_2471 ) ,
+ .p2456 ( optlc_net_2472 ) , .p2457 ( optlc_net_2473 ) ,
+ .p2458 ( optlc_net_2474 ) , .p2459 ( optlc_net_2475 ) ,
+ .p2460 ( optlc_net_2476 ) , .p2461 ( optlc_net_2477 ) ,
+ .p2462 ( optlc_net_2478 ) , .p2463 ( optlc_net_2479 ) ,
+ .p2464 ( optlc_net_2480 ) , .p2465 ( optlc_net_2481 ) ,
+ .p2466 ( optlc_net_2482 ) , .p2467 ( optlc_net_2483 ) ,
+ .p2468 ( optlc_net_2484 ) , .p2469 ( optlc_net_2485 ) ,
+ .p2470 ( optlc_net_2486 ) , .p2471 ( optlc_net_2487 ) ,
+ .p2472 ( optlc_net_2488 ) , .p2473 ( optlc_net_2489 ) ,
+ .p2474 ( optlc_net_2490 ) , .p2475 ( optlc_net_2491 ) ,
+ .p2476 ( optlc_net_2492 ) , .p2477 ( optlc_net_2493 ) ,
+ .p2478 ( optlc_net_2494 ) , .p2479 ( optlc_net_2495 ) ,
+ .p2480 ( optlc_net_2496 ) , .p2481 ( optlc_net_2497 ) ,
+ .p2482 ( optlc_net_2498 ) , .p2483 ( optlc_net_2499 ) ,
+ .p2484 ( optlc_net_2500 ) , .p2485 ( optlc_net_2501 ) ,
+ .p2486 ( optlc_net_2502 ) , .p2487 ( optlc_net_2503 ) ,
+ .p2488 ( optlc_net_2504 ) , .p2489 ( optlc_net_2505 ) ,
+ .p2490 ( optlc_net_2506 ) , .p2491 ( optlc_net_2507 ) ,
+ .p2492 ( optlc_net_2508 ) , .p2493 ( optlc_net_2509 ) ,
+ .p2494 ( optlc_net_2510 ) , .p2495 ( optlc_net_2511 ) ,
+ .p2496 ( optlc_net_2512 ) , .p2497 ( optlc_net_2513 ) ,
+ .p2498 ( optlc_net_2514 ) , .p2499 ( optlc_net_2515 ) ,
+ .p2500 ( optlc_net_2516 ) , .p2501 ( optlc_net_2517 ) ,
+ .p2502 ( optlc_net_2518 ) , .p2503 ( optlc_net_2519 ) ,
+ .p2504 ( optlc_net_2520 ) , .p2505 ( optlc_net_2521 ) ,
+ .p2506 ( optlc_net_2522 ) , .p2507 ( optlc_net_2523 ) ,
+ .p2508 ( optlc_net_2524 ) , .p2509 ( optlc_net_2525 ) ,
+ .p2510 ( optlc_net_2526 ) , .p2511 ( optlc_net_2527 ) ,
+ .p2512 ( optlc_net_2528 ) , .p2513 ( optlc_net_2529 ) ,
+ .p2514 ( optlc_net_2530 ) , .p2515 ( optlc_net_2531 ) ,
+ .p2516 ( optlc_net_2532 ) , .p2517 ( optlc_net_2533 ) ,
+ .p2518 ( optlc_net_2534 ) , .p2519 ( optlc_net_2535 ) ,
+ .p2520 ( optlc_net_2536 ) , .p2521 ( optlc_net_2537 ) ,
+ .p2522 ( optlc_net_2538 ) , .p2523 ( optlc_net_2539 ) ,
+ .p2524 ( optlc_net_2540 ) , .p2525 ( optlc_net_2541 ) ,
+ .p2526 ( optlc_net_2542 ) , .p2527 ( optlc_net_2543 ) ,
+ .p2528 ( optlc_net_2544 ) , .p2529 ( optlc_net_2545 ) ,
+ .p2530 ( optlc_net_2546 ) , .p2531 ( optlc_net_2547 ) ,
+ .p2532 ( optlc_net_2548 ) , .p2533 ( optlc_net_2549 ) ,
+ .p2534 ( optlc_net_2550 ) , .p2535 ( optlc_net_2551 ) ,
+ .p2536 ( optlc_net_2552 ) , .p2537 ( optlc_net_2553 ) ,
+ .p2538 ( optlc_net_2554 ) , .p2539 ( optlc_net_2555 ) ,
+ .p2540 ( optlc_net_2556 ) , .p2541 ( optlc_net_2557 ) ,
+ .p2542 ( optlc_net_2558 ) , .p2543 ( optlc_net_2559 ) ,
+ .p2544 ( optlc_net_2560 ) , .p2545 ( optlc_net_2561 ) ,
+ .p2546 ( optlc_net_2562 ) , .p2547 ( optlc_net_2563 ) ,
+ .p2548 ( optlc_net_2564 ) , .p2549 ( optlc_net_2565 ) ,
+ .p2550 ( optlc_net_2566 ) , .p2551 ( optlc_net_2567 ) ,
+ .p2552 ( optlc_net_2568 ) , .p2553 ( optlc_net_2569 ) ,
+ .p2554 ( optlc_net_2570 ) , .p2555 ( optlc_net_2571 ) ,
+ .p2556 ( optlc_net_2572 ) , .p2557 ( optlc_net_2573 ) ,
+ .p2558 ( optlc_net_2574 ) , .p2559 ( optlc_net_2575 ) ,
+ .p2560 ( optlc_net_2576 ) , .p2561 ( optlc_net_2577 ) ,
+ .p2562 ( optlc_net_2578 ) , .p2563 ( optlc_net_2579 ) ,
+ .p2564 ( optlc_net_2580 ) , .p2565 ( optlc_net_2581 ) ,
+ .p2566 ( optlc_net_2582 ) , .p2567 ( optlc_net_2583 ) ,
+ .p2568 ( optlc_net_2584 ) , .p2569 ( optlc_net_2585 ) ,
+ .p2570 ( optlc_net_2586 ) , .p2571 ( optlc_net_2587 ) ,
+ .p2572 ( optlc_net_2588 ) , .p2573 ( optlc_net_2589 ) ,
+ .p2574 ( optlc_net_2590 ) , .p2575 ( optlc_net_2591 ) ,
+ .p2576 ( optlc_net_2592 ) , .p2577 ( optlc_net_2593 ) ,
+ .p2578 ( optlc_net_2594 ) , .p2579 ( optlc_net_2595 ) ,
+ .p2580 ( optlc_net_2596 ) , .p2581 ( optlc_net_2597 ) ,
+ .p2582 ( optlc_net_2598 ) , .p2583 ( optlc_net_2599 ) ,
+ .p2584 ( optlc_net_2600 ) , .p2585 ( optlc_net_2601 ) ,
+ .p2586 ( optlc_net_2602 ) , .p2587 ( optlc_net_2603 ) ,
+ .p2588 ( optlc_net_2604 ) , .p2589 ( optlc_net_2605 ) ,
+ .p2590 ( optlc_net_2606 ) , .p2591 ( optlc_net_2607 ) ,
+ .p2592 ( optlc_net_2608 ) , .p2593 ( optlc_net_2609 ) ,
+ .p2594 ( optlc_net_2610 ) , .p2595 ( optlc_net_2611 ) ,
+ .p2596 ( optlc_net_2612 ) , .p2597 ( optlc_net_2613 ) ,
+ .p2598 ( optlc_net_2614 ) , .p2599 ( optlc_net_2615 ) ,
+ .p2600 ( optlc_net_2616 ) , .p2601 ( optlc_net_2617 ) ,
+ .p2602 ( optlc_net_2618 ) , .p2603 ( optlc_net_2619 ) ,
+ .p2604 ( optlc_net_2620 ) , .p2605 ( optlc_net_2621 ) ,
+ .p2606 ( optlc_net_2622 ) , .p2607 ( optlc_net_2623 ) ,
+ .p2608 ( optlc_net_2624 ) , .p2609 ( optlc_net_2625 ) ,
+ .p2610 ( optlc_net_2626 ) , .p2611 ( optlc_net_2627 ) ,
+ .p2612 ( optlc_net_2628 ) , .p2613 ( optlc_net_2629 ) ,
+ .p2614 ( optlc_net_2630 ) , .p2615 ( optlc_net_2631 ) ,
+ .p2616 ( optlc_net_2632 ) , .p2617 ( optlc_net_2633 ) ,
+ .p2618 ( optlc_net_2634 ) , .p2619 ( optlc_net_2635 ) ,
+ .p2620 ( optlc_net_2636 ) , .p2621 ( optlc_net_2637 ) ,
+ .p2622 ( optlc_net_2638 ) , .p2623 ( optlc_net_2639 ) ,
+ .p2624 ( optlc_net_2640 ) , .p2625 ( optlc_net_2641 ) ,
+ .p2626 ( optlc_net_2642 ) , .p2627 ( optlc_net_2643 ) ,
+ .p2628 ( optlc_net_2644 ) , .p2629 ( optlc_net_2645 ) ,
+ .p2630 ( optlc_net_2646 ) , .p2631 ( optlc_net_2647 ) ,
+ .p2632 ( optlc_net_2648 ) , .p2633 ( optlc_net_2649 ) ,
+ .p2634 ( optlc_net_2650 ) , .p2635 ( optlc_net_2651 ) ,
+ .p2636 ( optlc_net_2652 ) , .p2637 ( optlc_net_2653 ) ,
+ .p2638 ( optlc_net_2654 ) , .p2639 ( optlc_net_2655 ) ,
+ .p2640 ( optlc_net_2656 ) , .p2641 ( optlc_net_2657 ) ,
+ .p2642 ( optlc_net_2658 ) , .p2643 ( optlc_net_2659 ) ,
+ .p2644 ( optlc_net_2660 ) , .p2645 ( optlc_net_2661 ) ,
+ .p2646 ( optlc_net_2662 ) , .p2647 ( optlc_net_2663 ) ,
+ .p2648 ( optlc_net_2664 ) , .p2649 ( optlc_net_2665 ) ,
+ .p2650 ( optlc_net_2666 ) , .p2651 ( optlc_net_2667 ) ,
+ .p2652 ( optlc_net_2668 ) , .p2653 ( optlc_net_2669 ) ,
+ .p2654 ( optlc_net_2670 ) , .p2655 ( optlc_net_2671 ) ,
+ .p2656 ( optlc_net_2672 ) , .p2657 ( optlc_net_2673 ) ,
+ .p2658 ( optlc_net_2674 ) , .p2659 ( optlc_net_2675 ) ,
+ .p2660 ( optlc_net_2676 ) , .p2661 ( optlc_net_2677 ) ,
+ .p2662 ( optlc_net_2678 ) , .p2663 ( optlc_net_2679 ) ,
+ .p2664 ( optlc_net_2680 ) , .p2665 ( optlc_net_2681 ) ,
+ .p2666 ( optlc_net_2682 ) , .p2667 ( optlc_net_2683 ) ,
+ .p2668 ( optlc_net_2684 ) , .p2669 ( optlc_net_2685 ) ,
+ .p2670 ( optlc_net_2686 ) , .p2671 ( optlc_net_2687 ) ,
+ .p2672 ( optlc_net_2688 ) , .p2673 ( optlc_net_2689 ) ,
+ .p2674 ( optlc_net_2690 ) , .p2675 ( optlc_net_2691 ) ,
+ .p2676 ( optlc_net_2692 ) , .p2677 ( optlc_net_2693 ) ,
+ .p2678 ( optlc_net_2694 ) , .p2679 ( optlc_net_2695 ) ,
+ .p2680 ( optlc_net_2696 ) , .p2681 ( optlc_net_2697 ) ,
+ .p2682 ( optlc_net_2698 ) , .p2683 ( optlc_net_2699 ) ,
+ .p2684 ( optlc_net_2700 ) , .p2685 ( optlc_net_2701 ) ,
+ .p2686 ( optlc_net_2702 ) , .p2687 ( optlc_net_2703 ) ,
+ .p2688 ( optlc_net_2704 ) , .p2689 ( optlc_net_2705 ) ,
+ .p2690 ( optlc_net_2706 ) , .p2691 ( optlc_net_2707 ) ,
+ .p2692 ( optlc_net_2708 ) , .p2693 ( optlc_net_2709 ) ,
+ .p2694 ( optlc_net_2710 ) , .p2695 ( optlc_net_2711 ) ,
+ .p2696 ( optlc_net_2712 ) , .p2697 ( optlc_net_2713 ) ,
+ .p2698 ( optlc_net_2714 ) , .p2699 ( optlc_net_2715 ) ,
+ .p2700 ( optlc_net_2716 ) , .p2701 ( optlc_net_2717 ) ,
+ .p2702 ( optlc_net_2718 ) , .p2703 ( optlc_net_2719 ) ,
+ .p2704 ( optlc_net_2720 ) , .p2705 ( optlc_net_2721 ) ,
+ .p2706 ( optlc_net_2722 ) , .p2707 ( optlc_net_2723 ) ,
+ .p2708 ( optlc_net_2724 ) , .p2709 ( optlc_net_2725 ) ,
+ .p2710 ( optlc_net_2726 ) , .p2711 ( optlc_net_2727 ) ,
+ .p2712 ( optlc_net_2728 ) , .p2713 ( optlc_net_2729 ) ,
+ .p2714 ( optlc_net_2730 ) , .p2715 ( optlc_net_2731 ) ,
+ .p2716 ( optlc_net_2732 ) , .p2717 ( optlc_net_2733 ) ,
+ .p2718 ( optlc_net_2734 ) , .p2719 ( optlc_net_2735 ) ,
+ .p2720 ( optlc_net_2736 ) , .p2721 ( optlc_net_2737 ) ,
+ .p2722 ( optlc_net_2738 ) , .p2723 ( optlc_net_2739 ) ,
+ .p2724 ( optlc_net_2740 ) , .p2725 ( optlc_net_2741 ) ,
+ .p2726 ( optlc_net_2742 ) , .p2727 ( optlc_net_2743 ) ,
+ .p2728 ( optlc_net_2744 ) , .p2729 ( optlc_net_2745 ) ,
+ .p2730 ( optlc_net_2746 ) , .p2731 ( optlc_net_2747 ) ,
+ .p2732 ( optlc_net_2748 ) , .p2733 ( optlc_net_2749 ) ,
+ .p2734 ( optlc_net_2750 ) , .p2735 ( optlc_net_2751 ) ,
+ .p2736 ( optlc_net_2752 ) , .p2737 ( optlc_net_2753 ) ,
+ .p2738 ( optlc_net_2754 ) , .p2739 ( optlc_net_2755 ) ,
+ .p2740 ( optlc_net_2756 ) , .p2741 ( optlc_net_2757 ) ,
+ .p2742 ( optlc_net_2758 ) , .p2743 ( optlc_net_2759 ) ,
+ .p2744 ( optlc_net_2760 ) , .p2745 ( optlc_net_2761 ) ,
+ .p2746 ( optlc_net_2762 ) , .p2747 ( optlc_net_2763 ) ,
+ .p2748 ( optlc_net_2764 ) , .p2749 ( optlc_net_2765 ) ,
+ .p2750 ( optlc_net_2766 ) , .p2751 ( optlc_net_2767 ) ,
+ .p2752 ( optlc_net_2768 ) , .p2753 ( optlc_net_2769 ) ,
+ .p2754 ( optlc_net_2770 ) , .p2755 ( optlc_net_2771 ) ,
+ .p2756 ( optlc_net_2772 ) , .p2757 ( optlc_net_2773 ) ,
+ .p2758 ( optlc_net_2774 ) , .p2759 ( optlc_net_2775 ) ,
+ .p2760 ( optlc_net_2776 ) , .p2761 ( optlc_net_2777 ) ,
+ .p2762 ( optlc_net_2778 ) , .p2763 ( optlc_net_2779 ) ,
+ .p2764 ( optlc_net_2780 ) , .p2765 ( optlc_net_2781 ) ,
+ .p2766 ( optlc_net_2782 ) , .p2767 ( optlc_net_2783 ) ,
+ .p2768 ( optlc_net_2784 ) , .p2769 ( optlc_net_2785 ) ,
+ .p2770 ( optlc_net_2786 ) , .p2771 ( optlc_net_2787 ) ,
+ .p2772 ( optlc_net_2788 ) , .p2773 ( optlc_net_2789 ) ,
+ .p2774 ( optlc_net_2790 ) , .p2775 ( optlc_net_2791 ) ,
+ .p2776 ( optlc_net_2792 ) , .p2777 ( optlc_net_2793 ) ,
+ .p2778 ( optlc_net_2794 ) , .p2779 ( optlc_net_2795 ) ,
+ .p2780 ( optlc_net_2796 ) , .p2781 ( optlc_net_2797 ) ,
+ .p2782 ( optlc_net_2798 ) , .p2783 ( optlc_net_2799 ) ,
+ .p2784 ( optlc_net_2800 ) , .p2785 ( optlc_net_2801 ) ,
+ .p2786 ( optlc_net_2802 ) , .p2787 ( optlc_net_2803 ) ,
+ .p2788 ( optlc_net_2804 ) , .p2789 ( optlc_net_2805 ) ,
+ .p2790 ( optlc_net_2806 ) , .p2791 ( optlc_net_2807 ) ,
+ .p2792 ( optlc_net_2808 ) , .p2793 ( optlc_net_2809 ) ,
+ .p2794 ( optlc_net_2810 ) , .p2795 ( optlc_net_2811 ) ,
+ .p2796 ( optlc_net_2812 ) , .p2797 ( optlc_net_2813 ) ,
+ .p2798 ( optlc_net_2814 ) , .p2799 ( optlc_net_2815 ) ,
+ .p2800 ( optlc_net_2816 ) , .p2801 ( optlc_net_2817 ) ,
+ .p2802 ( optlc_net_2818 ) , .p2803 ( optlc_net_2819 ) ,
+ .p2804 ( optlc_net_2820 ) , .p2805 ( optlc_net_2821 ) ,
+ .p2806 ( optlc_net_2822 ) , .p2807 ( optlc_net_2823 ) ,
+ .p2808 ( optlc_net_2824 ) , .p2809 ( optlc_net_2825 ) ,
+ .p2810 ( optlc_net_2826 ) , .p2811 ( optlc_net_2827 ) ,
+ .p2812 ( optlc_net_2828 ) , .p2813 ( optlc_net_2829 ) ,
+ .p2814 ( optlc_net_2830 ) , .p2815 ( optlc_net_2831 ) ,
+ .p2816 ( optlc_net_2832 ) , .p2817 ( optlc_net_2833 ) ,
+ .p2818 ( optlc_net_2834 ) , .p2819 ( optlc_net_2835 ) ,
+ .p2820 ( optlc_net_2836 ) , .p2821 ( optlc_net_2837 ) ,
+ .p2822 ( optlc_net_2838 ) , .p2823 ( optlc_net_2839 ) ,
+ .p2824 ( optlc_net_2840 ) , .p2825 ( optlc_net_2841 ) ,
+ .p2826 ( optlc_net_2842 ) , .p2827 ( optlc_net_2843 ) ,
+ .p2828 ( optlc_net_2844 ) , .p2829 ( optlc_net_2845 ) ,
+ .p2830 ( optlc_net_2846 ) , .p2831 ( optlc_net_2847 ) ,
+ .p2832 ( optlc_net_2848 ) , .p2833 ( optlc_net_2849 ) ,
+ .p2834 ( optlc_net_2850 ) , .p2835 ( optlc_net_2851 ) ,
+ .p2836 ( optlc_net_2852 ) , .p2837 ( optlc_net_2853 ) ,
+ .p2838 ( optlc_net_2854 ) , .p2839 ( optlc_net_2855 ) ,
+ .p2840 ( optlc_net_2856 ) , .p2841 ( optlc_net_2857 ) ,
+ .p2842 ( optlc_net_2858 ) , .p2843 ( optlc_net_2859 ) ,
+ .p2844 ( optlc_net_2860 ) , .p2845 ( optlc_net_2861 ) ,
+ .p2846 ( optlc_net_2862 ) , .p2847 ( optlc_net_2863 ) ,
+ .p2848 ( optlc_net_2864 ) , .p2849 ( optlc_net_2865 ) ,
+ .p2850 ( optlc_net_2866 ) , .p2851 ( optlc_net_2867 ) ,
+ .p2852 ( optlc_net_2868 ) , .p2853 ( optlc_net_2869 ) ,
+ .p2854 ( optlc_net_2870 ) , .p2855 ( optlc_net_2871 ) ,
+ .p2856 ( optlc_net_2872 ) , .p2857 ( optlc_net_2873 ) ,
+ .p2858 ( optlc_net_2874 ) , .p2859 ( optlc_net_2875 ) ,
+ .p2860 ( optlc_net_2876 ) , .p2861 ( optlc_net_2877 ) ,
+ .p2862 ( optlc_net_2878 ) , .p2863 ( optlc_net_2879 ) ,
+ .p2864 ( optlc_net_2880 ) , .p2865 ( optlc_net_2881 ) ,
+ .p2866 ( optlc_net_2882 ) , .p2867 ( optlc_net_2883 ) ,
+ .p2868 ( optlc_net_2884 ) , .p2869 ( optlc_net_2885 ) ,
+ .p2870 ( optlc_net_2886 ) , .p2871 ( optlc_net_2887 ) ,
+ .p2872 ( optlc_net_2888 ) , .p2873 ( optlc_net_2889 ) ,
+ .p2874 ( optlc_net_2890 ) , .p2875 ( optlc_net_2891 ) ,
+ .p2876 ( optlc_net_2892 ) , .p2877 ( optlc_net_2893 ) ,
+ .p2878 ( optlc_net_2894 ) , .p2879 ( optlc_net_2895 ) ,
+ .p2880 ( optlc_net_2896 ) , .p2881 ( optlc_net_2897 ) ,
+ .p2882 ( optlc_net_2898 ) , .p2883 ( optlc_net_2899 ) ,
+ .p2884 ( optlc_net_2900 ) , .p2885 ( optlc_net_2901 ) ,
+ .p2886 ( optlc_net_2902 ) , .p2887 ( optlc_net_2903 ) ,
+ .p2888 ( optlc_net_2904 ) , .p2889 ( optlc_net_2905 ) ,
+ .p2890 ( optlc_net_2906 ) , .p2891 ( optlc_net_2907 ) ,
+ .p2892 ( optlc_net_2908 ) , .p2893 ( optlc_net_2909 ) ,
+ .p2894 ( optlc_net_2910 ) , .p2895 ( optlc_net_2911 ) ,
+ .p2896 ( optlc_net_2912 ) , .p2897 ( optlc_net_2913 ) ,
+ .p2898 ( optlc_net_2914 ) , .p2899 ( optlc_net_2915 ) ,
+ .p2900 ( optlc_net_2916 ) , .p2901 ( optlc_net_2917 ) ,
+ .p2902 ( optlc_net_2918 ) , .p2903 ( optlc_net_2919 ) ,
+ .p2904 ( optlc_net_2920 ) , .p2905 ( optlc_net_2921 ) ,
+ .p2906 ( optlc_net_2922 ) , .p2907 ( optlc_net_2923 ) ,
+ .p2908 ( optlc_net_2924 ) , .p2909 ( optlc_net_2925 ) ,
+ .p2910 ( optlc_net_2926 ) , .p2911 ( optlc_net_2927 ) ,
+ .p2912 ( optlc_net_2928 ) , .p2913 ( optlc_net_2929 ) ,
+ .p2914 ( optlc_net_2930 ) , .p2915 ( optlc_net_2931 ) ,
+ .p2916 ( optlc_net_2932 ) , .p2917 ( optlc_net_2933 ) ,
+ .p2918 ( optlc_net_2934 ) , .p2919 ( optlc_net_2935 ) ,
+ .p2920 ( optlc_net_2936 ) , .p2921 ( optlc_net_2937 ) ,
+ .p2922 ( optlc_net_2938 ) , .p2923 ( optlc_net_2939 ) ,
+ .p2924 ( optlc_net_2940 ) , .p2925 ( optlc_net_2941 ) ,
+ .p2926 ( optlc_net_2942 ) , .p2927 ( optlc_net_2943 ) ,
+ .p2928 ( optlc_net_2944 ) , .p2929 ( optlc_net_2945 ) ,
+ .p2930 ( optlc_net_2946 ) , .p2931 ( optlc_net_2947 ) ,
+ .p2932 ( optlc_net_2948 ) , .p2933 ( optlc_net_2949 ) ,
+ .p2934 ( optlc_net_2950 ) , .p2935 ( optlc_net_2951 ) ,
+ .p2936 ( optlc_net_2952 ) , .p2937 ( optlc_net_2953 ) ,
+ .p2938 ( optlc_net_2954 ) , .p2939 ( optlc_net_2955 ) ,
+ .p2940 ( optlc_net_2956 ) , .p2941 ( optlc_net_2957 ) ,
+ .p2942 ( optlc_net_2958 ) , .p2943 ( optlc_net_2959 ) ,
+ .p2944 ( optlc_net_2960 ) , .p2945 ( optlc_net_2961 ) ,
+ .p2946 ( optlc_net_2962 ) , .p2947 ( optlc_net_2963 ) ,
+ .p2948 ( optlc_net_2964 ) , .p2949 ( optlc_net_2965 ) ,
+ .p2950 ( optlc_net_2966 ) , .p2951 ( optlc_net_2967 ) ,
+ .p2952 ( optlc_net_2968 ) , .p2953 ( optlc_net_2969 ) ,
+ .p2954 ( optlc_net_2970 ) , .p2955 ( optlc_net_2971 ) ,
+ .p2956 ( optlc_net_2972 ) , .p2957 ( optlc_net_2973 ) ,
+ .p2958 ( optlc_net_2974 ) , .p2959 ( optlc_net_2975 ) ,
+ .p2960 ( optlc_net_2976 ) , .p2961 ( optlc_net_2977 ) ,
+ .p2962 ( optlc_net_2978 ) , .p2963 ( optlc_net_2979 ) ,
+ .p2964 ( optlc_net_2980 ) , .p2965 ( optlc_net_2981 ) ,
+ .p2966 ( optlc_net_2982 ) , .p2967 ( optlc_net_2983 ) ,
+ .p2968 ( optlc_net_2984 ) , .p2969 ( optlc_net_2985 ) ,
+ .p2970 ( optlc_net_2986 ) , .p2971 ( optlc_net_2987 ) ,
+ .p2972 ( optlc_net_2988 ) , .p2973 ( optlc_net_2989 ) ,
+ .p2974 ( optlc_net_2990 ) , .p2975 ( optlc_net_2991 ) ,
+ .p2976 ( optlc_net_2992 ) , .p2977 ( optlc_net_2993 ) ,
+ .p2978 ( optlc_net_2994 ) , .p2979 ( optlc_net_2995 ) ,
+ .p2980 ( optlc_net_2996 ) , .p2981 ( optlc_net_2997 ) ,
+ .p2982 ( optlc_net_2998 ) , .p2983 ( optlc_net_2999 ) ,
+ .p2984 ( optlc_net_3000 ) , .p2985 ( optlc_net_3001 ) ,
+ .p2986 ( optlc_net_3002 ) , .p2987 ( optlc_net_3003 ) ,
+ .p2988 ( optlc_net_3004 ) , .p2989 ( optlc_net_3005 ) ,
+ .p2990 ( optlc_net_3006 ) , .p2991 ( optlc_net_3007 ) ,
+ .p2992 ( optlc_net_3008 ) , .p2993 ( optlc_net_3009 ) ,
+ .p2994 ( optlc_net_3010 ) , .p2995 ( optlc_net_3011 ) ,
+ .p2996 ( optlc_net_3012 ) , .p2997 ( optlc_net_3013 ) ,
+ .p2998 ( optlc_net_3014 ) , .p2999 ( optlc_net_3015 ) ,
+ .p3000 ( optlc_net_3016 ) , .p3001 ( optlc_net_3017 ) ,
+ .p3002 ( optlc_net_3018 ) , .p3003 ( optlc_net_3019 ) ,
+ .p3004 ( optlc_net_3020 ) , .p3005 ( optlc_net_3021 ) ,
+ .p3006 ( optlc_net_3022 ) , .p3007 ( optlc_net_3023 ) ,
+ .p3008 ( optlc_net_3024 ) , .p3009 ( optlc_net_3025 ) ,
+ .p3010 ( optlc_net_3026 ) , .p3011 ( optlc_net_3027 ) ,
+ .p3012 ( optlc_net_3028 ) , .p3013 ( optlc_net_3029 ) ,
+ .p3014 ( optlc_net_3030 ) , .p3015 ( optlc_net_3031 ) ,
+ .p3016 ( optlc_net_3032 ) , .p3017 ( optlc_net_3033 ) ,
+ .p3018 ( optlc_net_3034 ) , .p3019 ( optlc_net_3035 ) ,
+ .p3020 ( optlc_net_3036 ) , .p3021 ( optlc_net_3037 ) ,
+ .p3022 ( optlc_net_3038 ) , .p3023 ( optlc_net_3039 ) ,
+ .p3024 ( optlc_net_3040 ) , .p3025 ( optlc_net_3041 ) ,
+ .p3026 ( optlc_net_3042 ) , .p3027 ( optlc_net_3043 ) ,
+ .p3028 ( optlc_net_3044 ) , .p3029 ( optlc_net_3045 ) ,
+ .p3030 ( optlc_net_3046 ) , .p3031 ( optlc_net_3047 ) ,
+ .p3032 ( optlc_net_3048 ) , .p3033 ( optlc_net_3049 ) ,
+ .p3034 ( optlc_net_3050 ) , .p3035 ( optlc_net_3051 ) ,
+ .p3036 ( optlc_net_3052 ) , .p3037 ( optlc_net_3053 ) ,
+ .p3038 ( optlc_net_3054 ) , .p3039 ( optlc_net_3055 ) ,
+ .p3040 ( optlc_net_3056 ) , .p3041 ( optlc_net_3057 ) ,
+ .p3042 ( optlc_net_3058 ) , .p3043 ( optlc_net_3059 ) ,
+ .p3044 ( optlc_net_3060 ) , .p3045 ( optlc_net_3061 ) ,
+ .p3046 ( optlc_net_3062 ) , .p3047 ( optlc_net_3063 ) ,
+ .p3048 ( optlc_net_3064 ) , .p3049 ( optlc_net_3065 ) ,
+ .p3050 ( optlc_net_3066 ) , .p3051 ( optlc_net_3067 ) ,
+ .p3052 ( optlc_net_3068 ) , .p3053 ( optlc_net_3069 ) ,
+ .p3054 ( optlc_net_3070 ) , .p3055 ( optlc_net_3071 ) ,
+ .p3056 ( optlc_net_3072 ) , .p3057 ( optlc_net_3073 ) ,
+ .p3058 ( optlc_net_3074 ) , .p3059 ( optlc_net_3075 ) ,
+ .p3060 ( optlc_net_3076 ) , .p3061 ( optlc_net_3077 ) ,
+ .p3062 ( optlc_net_3078 ) , .p3063 ( optlc_net_3079 ) ,
+ .p3064 ( optlc_net_3080 ) , .p3065 ( optlc_net_3081 ) ,
+ .p3066 ( optlc_net_3082 ) , .p3067 ( optlc_net_3083 ) ,
+ .p3068 ( optlc_net_3084 ) , .p3069 ( optlc_net_3085 ) ,
+ .p3070 ( optlc_net_3086 ) , .p3071 ( optlc_net_3087 ) ,
+ .p3072 ( optlc_net_3088 ) , .p3073 ( optlc_net_3089 ) ,
+ .p3074 ( optlc_net_3090 ) , .p3075 ( optlc_net_3091 ) ,
+ .p3076 ( optlc_net_3092 ) , .p3077 ( optlc_net_3093 ) ,
+ .p3078 ( optlc_net_3094 ) , .p3079 ( optlc_net_3095 ) ,
+ .p3080 ( optlc_net_3096 ) , .p3081 ( optlc_net_3097 ) ,
+ .p3082 ( optlc_net_3098 ) , .p3083 ( optlc_net_3099 ) ,
+ .p3084 ( optlc_net_3100 ) , .p3085 ( optlc_net_3101 ) ,
+ .p3086 ( optlc_net_3102 ) , .p3087 ( optlc_net_3103 ) ,
+ .p3088 ( optlc_net_3104 ) , .p3089 ( optlc_net_3105 ) ,
+ .p3090 ( optlc_net_3106 ) , .p3091 ( optlc_net_3107 ) ,
+ .p3092 ( optlc_net_3108 ) , .p3093 ( optlc_net_3109 ) ,
+ .p3094 ( optlc_net_3110 ) , .p3095 ( optlc_net_3111 ) ,
+ .p3096 ( optlc_net_3112 ) , .p3097 ( optlc_net_3113 ) ,
+ .p3098 ( optlc_net_3114 ) , .p3099 ( optlc_net_3115 ) ,
+ .p3100 ( optlc_net_3116 ) , .p3101 ( optlc_net_3117 ) ,
+ .p3102 ( optlc_net_3118 ) , .p3103 ( optlc_net_3119 ) ,
+ .p3104 ( optlc_net_3120 ) , .p3105 ( optlc_net_3121 ) ,
+ .p3106 ( optlc_net_3122 ) , .p3107 ( optlc_net_3123 ) ,
+ .p3108 ( optlc_net_3124 ) , .p3109 ( optlc_net_3125 ) ,
+ .p3110 ( optlc_net_3126 ) , .p3111 ( optlc_net_3127 ) ,
+ .p3112 ( optlc_net_3128 ) , .p3113 ( optlc_net_3129 ) ,
+ .p3114 ( optlc_net_3130 ) , .p3115 ( optlc_net_3131 ) ,
+ .p3116 ( optlc_net_3132 ) , .p3117 ( optlc_net_3133 ) ,
+ .p3118 ( optlc_net_3134 ) , .p3119 ( optlc_net_3135 ) ,
+ .p3120 ( optlc_net_3136 ) , .p3121 ( optlc_net_3137 ) ,
+ .p3122 ( optlc_net_3138 ) , .p3123 ( optlc_net_3139 ) ,
+ .p3124 ( optlc_net_3140 ) , .p3125 ( optlc_net_3141 ) ,
+ .p3126 ( optlc_net_3142 ) , .p3127 ( optlc_net_3143 ) ,
+ .p3128 ( optlc_net_3144 ) , .p3129 ( optlc_net_3145 ) ,
+ .p3130 ( optlc_net_3146 ) , .p3131 ( optlc_net_3147 ) ,
+ .p3132 ( optlc_net_3148 ) , .p3133 ( optlc_net_3149 ) ,
+ .p3134 ( optlc_net_3150 ) , .p3135 ( optlc_net_3151 ) ,
+ .p3136 ( optlc_net_3152 ) , .p3137 ( optlc_net_3153 ) ,
+ .p3138 ( optlc_net_3154 ) , .p3139 ( optlc_net_3155 ) ,
+ .p3140 ( optlc_net_3156 ) , .p3141 ( optlc_net_3157 ) ,
+ .p3142 ( optlc_net_3158 ) , .p3143 ( optlc_net_3159 ) ,
+ .p3144 ( optlc_net_3160 ) , .p3145 ( optlc_net_3161 ) ,
+ .p3146 ( optlc_net_3162 ) , .p3147 ( optlc_net_3163 ) ,
+ .p3148 ( optlc_net_3164 ) , .p3149 ( optlc_net_3165 ) ,
+ .p3150 ( optlc_net_3166 ) , .p3151 ( optlc_net_3167 ) ,
+ .p3152 ( optlc_net_3168 ) , .p3153 ( optlc_net_3169 ) ,
+ .p3154 ( optlc_net_3170 ) , .p3155 ( optlc_net_3171 ) ,
+ .p3156 ( optlc_net_3172 ) , .p3157 ( optlc_net_3173 ) ,
+ .p3158 ( optlc_net_3174 ) , .p3159 ( optlc_net_3175 ) ,
+ .p3160 ( optlc_net_3176 ) , .p3161 ( optlc_net_3177 ) ,
+ .p3162 ( optlc_net_3178 ) , .p3163 ( optlc_net_3179 ) ,
+ .p3164 ( optlc_net_3180 ) , .p3165 ( optlc_net_3181 ) ,
+ .p3166 ( optlc_net_3182 ) , .p3167 ( optlc_net_3183 ) ,
+ .p3168 ( optlc_net_3184 ) , .p3169 ( optlc_net_3185 ) ,
+ .p3170 ( optlc_net_3186 ) , .p3171 ( optlc_net_3187 ) ,
+ .p3172 ( optlc_net_3188 ) , .p3173 ( optlc_net_3189 ) ,
+ .p3174 ( optlc_net_3190 ) , .p3175 ( optlc_net_3191 ) ,
+ .p3176 ( optlc_net_3192 ) , .p3177 ( optlc_net_3193 ) ,
+ .p3178 ( optlc_net_3194 ) , .p3179 ( optlc_net_3195 ) ,
+ .p3180 ( optlc_net_3196 ) , .p3181 ( optlc_net_3197 ) ,
+ .p3182 ( optlc_net_3198 ) , .p3183 ( optlc_net_3199 ) ,
+ .p3184 ( optlc_net_3200 ) , .p3185 ( optlc_net_3201 ) ,
+ .p3186 ( optlc_net_3202 ) , .p3187 ( optlc_net_3203 ) ,
+ .p3188 ( optlc_net_3204 ) , .p3189 ( optlc_net_3205 ) ,
+ .p3190 ( optlc_net_3206 ) , .p3191 ( optlc_net_3207 ) ,
+ .p3192 ( optlc_net_3208 ) , .p3193 ( optlc_net_3209 ) ,
+ .p3194 ( optlc_net_3210 ) , .p3195 ( optlc_net_3211 ) ,
+ .p3196 ( optlc_net_3212 ) , .p3197 ( optlc_net_3213 ) ,
+ .p3198 ( optlc_net_3214 ) , .p3199 ( optlc_net_3215 ) ,
+ .p3200 ( optlc_net_3216 ) , .p3201 ( optlc_net_3217 ) ,
+ .p3202 ( optlc_net_3218 ) , .p3203 ( optlc_net_3219 ) ,
+ .p3204 ( optlc_net_3220 ) , .p3205 ( optlc_net_3221 ) ,
+ .p3206 ( optlc_net_3222 ) , .p3207 ( optlc_net_3223 ) ,
+ .p3208 ( optlc_net_3224 ) , .p3209 ( optlc_net_3225 ) ,
+ .p3210 ( optlc_net_3226 ) , .p3211 ( optlc_net_3227 ) ,
+ .p3212 ( optlc_net_3228 ) , .p3213 ( optlc_net_3229 ) ,
+ .p3214 ( optlc_net_3230 ) , .p3215 ( optlc_net_3231 ) ,
+ .p3216 ( optlc_net_3232 ) , .p3217 ( optlc_net_3233 ) ,
+ .p3218 ( optlc_net_3234 ) , .p3219 ( optlc_net_3235 ) ,
+ .p3220 ( optlc_net_3236 ) , .p3221 ( optlc_net_3237 ) ,
+ .p3222 ( optlc_net_3238 ) , .p3223 ( optlc_net_3239 ) ,
+ .p3224 ( optlc_net_3240 ) , .p3225 ( optlc_net_3241 ) ,
+ .p3226 ( optlc_net_3242 ) , .p3227 ( optlc_net_3243 ) ,
+ .p3228 ( optlc_net_3244 ) , .p3229 ( optlc_net_3245 ) ,
+ .p3230 ( optlc_net_3246 ) , .p3231 ( optlc_net_3247 ) ,
+ .p3232 ( optlc_net_3248 ) , .p3233 ( optlc_net_3249 ) ,
+ .p3234 ( optlc_net_3250 ) , .p3235 ( optlc_net_3251 ) ,
+ .p3236 ( optlc_net_3252 ) , .p3237 ( optlc_net_3253 ) ,
+ .p3238 ( optlc_net_3254 ) , .p3239 ( optlc_net_3255 ) ,
+ .p3240 ( optlc_net_3256 ) , .p3241 ( optlc_net_3257 ) ,
+ .p3242 ( optlc_net_3258 ) , .p3243 ( optlc_net_3259 ) ,
+ .p3244 ( optlc_net_3260 ) , .p3245 ( optlc_net_3261 ) ,
+ .p3246 ( optlc_net_3262 ) , .p3247 ( optlc_net_3263 ) ,
+ .p3248 ( optlc_net_3264 ) , .p3249 ( optlc_net_3265 ) ,
+ .p3250 ( optlc_net_3266 ) , .p3251 ( optlc_net_3267 ) ,
+ .p3252 ( optlc_net_3268 ) , .p3253 ( optlc_net_3269 ) ,
+ .p3254 ( optlc_net_3270 ) , .p3255 ( optlc_net_3271 ) ,
+ .p3256 ( optlc_net_3272 ) , .p3257 ( optlc_net_3273 ) ,
+ .p3258 ( optlc_net_3274 ) , .p3259 ( optlc_net_3275 ) ,
+ .p3260 ( optlc_net_3276 ) , .p3261 ( optlc_net_3277 ) ,
+ .p3262 ( optlc_net_3278 ) , .p3263 ( optlc_net_3279 ) ,
+ .p3264 ( optlc_net_3280 ) , .p3265 ( optlc_net_3281 ) ,
+ .p3266 ( optlc_net_3282 ) , .p3267 ( optlc_net_3283 ) ,
+ .p3268 ( optlc_net_3284 ) , .p3269 ( optlc_net_3285 ) ,
+ .p3270 ( optlc_net_3286 ) , .p3271 ( optlc_net_3287 ) ,
+ .p3272 ( optlc_net_3288 ) , .p3273 ( optlc_net_3289 ) ,
+ .p3274 ( optlc_net_3290 ) , .p3275 ( optlc_net_3291 ) ,
+ .p3276 ( optlc_net_3292 ) , .p3277 ( optlc_net_3293 ) ,
+ .p3278 ( optlc_net_3294 ) , .p3279 ( optlc_net_3295 ) ,
+ .p3280 ( optlc_net_3296 ) , .p3281 ( optlc_net_3297 ) ,
+ .p3282 ( optlc_net_3298 ) , .p3283 ( optlc_net_3299 ) ,
+ .p3284 ( optlc_net_3300 ) , .p3285 ( optlc_net_3301 ) ,
+ .p3286 ( optlc_net_3302 ) , .p3287 ( optlc_net_3303 ) ,
+ .p3288 ( optlc_net_3304 ) , .p3289 ( optlc_net_3305 ) ,
+ .p3290 ( optlc_net_3306 ) , .p3291 ( optlc_net_3307 ) ,
+ .p3292 ( optlc_net_3308 ) , .p3293 ( optlc_net_3309 ) ,
+ .p3294 ( optlc_net_3310 ) , .p3295 ( optlc_net_3311 ) ,
+ .p3296 ( optlc_net_3312 ) , .p3297 ( optlc_net_3313 ) ,
+ .p3298 ( optlc_net_3314 ) , .p3299 ( optlc_net_3315 ) ,
+ .p3300 ( optlc_net_3316 ) , .p3301 ( optlc_net_3317 ) ,
+ .p3302 ( optlc_net_3318 ) , .p3303 ( optlc_net_3319 ) ,
+ .p3304 ( optlc_net_3320 ) , .p3305 ( optlc_net_3321 ) ,
+ .p3306 ( optlc_net_3322 ) , .p3307 ( optlc_net_3323 ) ,
+ .p3308 ( optlc_net_3324 ) , .p3309 ( optlc_net_3325 ) ,
+ .p3310 ( optlc_net_3326 ) , .p3311 ( optlc_net_3327 ) ,
+ .p3312 ( optlc_net_3328 ) , .p3313 ( optlc_net_3329 ) ,
+ .p3314 ( optlc_net_3330 ) , .p3315 ( optlc_net_3331 ) ,
+ .p3316 ( optlc_net_3332 ) , .p3317 ( optlc_net_3333 ) ,
+ .p3318 ( optlc_net_3334 ) , .p3319 ( optlc_net_3335 ) ,
+ .p3320 ( optlc_net_3336 ) , .p3321 ( optlc_net_3337 ) ,
+ .p3322 ( optlc_net_3338 ) , .p3323 ( optlc_net_3339 ) ,
+ .p3324 ( optlc_net_3340 ) , .p3325 ( optlc_net_3341 ) ,
+ .p3326 ( optlc_net_3342 ) , .p3327 ( optlc_net_3343 ) ,
+ .p3328 ( optlc_net_3344 ) , .p3329 ( optlc_net_3345 ) ,
+ .p3330 ( optlc_net_3346 ) , .p3331 ( optlc_net_3347 ) ,
+ .p3332 ( optlc_net_3348 ) , .p3333 ( optlc_net_3349 ) ,
+ .p3334 ( optlc_net_3350 ) , .p3335 ( optlc_net_3351 ) ,
+ .p3336 ( optlc_net_3352 ) , .p3337 ( optlc_net_3353 ) ,
+ .p3338 ( optlc_net_3354 ) , .p3339 ( optlc_net_3355 ) ,
+ .p3340 ( optlc_net_3356 ) , .p3341 ( optlc_net_3357 ) ,
+ .p3342 ( optlc_net_3358 ) , .p3343 ( optlc_net_3359 ) ,
+ .p3344 ( optlc_net_3360 ) , .p3345 ( optlc_net_3361 ) ,
+ .p3346 ( optlc_net_3362 ) , .p3347 ( optlc_net_3363 ) ,
+ .p3348 ( optlc_net_3364 ) , .p3349 ( optlc_net_3365 ) ,
+ .p3350 ( optlc_net_3366 ) , .p3351 ( optlc_net_3367 ) ,
+ .p3352 ( optlc_net_3368 ) , .p3353 ( optlc_net_3369 ) ,
+ .p3354 ( optlc_net_3370 ) , .p3355 ( optlc_net_3371 ) ,
+ .p3356 ( optlc_net_3372 ) , .p3357 ( optlc_net_3373 ) ,
+ .p3358 ( optlc_net_3374 ) , .p3359 ( optlc_net_3375 ) ,
+ .p3360 ( optlc_net_3376 ) , .p3361 ( optlc_net_3377 ) ,
+ .p3362 ( optlc_net_3378 ) , .p3363 ( optlc_net_3379 ) ,
+ .p3364 ( optlc_net_3380 ) , .p3365 ( optlc_net_3381 ) ,
+ .p3366 ( optlc_net_3382 ) , .p3367 ( optlc_net_3383 ) ,
+ .p3368 ( optlc_net_3384 ) , .p3369 ( optlc_net_3385 ) ,
+ .p3370 ( optlc_net_3386 ) , .p3371 ( optlc_net_3387 ) ,
+ .p3372 ( optlc_net_3388 ) , .p3373 ( optlc_net_3389 ) ,
+ .p3374 ( optlc_net_3390 ) , .p3375 ( optlc_net_3391 ) ,
+ .p3376 ( optlc_net_3392 ) , .p3377 ( optlc_net_3393 ) ,
+ .p3378 ( optlc_net_3394 ) , .p3379 ( optlc_net_3395 ) ,
+ .p3380 ( optlc_net_3396 ) , .p3381 ( optlc_net_3397 ) ,
+ .p3382 ( optlc_net_3398 ) , .p3383 ( optlc_net_3399 ) ,
+ .p3384 ( optlc_net_3400 ) , .p3385 ( optlc_net_3401 ) ,
+ .p3386 ( optlc_net_3402 ) , .p3387 ( optlc_net_3403 ) ,
+ .p3388 ( optlc_net_3404 ) , .p3389 ( optlc_net_3405 ) ,
+ .p3390 ( optlc_net_3406 ) , .p3391 ( optlc_net_3407 ) ,
+ .p3392 ( optlc_net_3408 ) , .p3393 ( optlc_net_3409 ) ,
+ .p3394 ( optlc_net_3410 ) , .p3395 ( optlc_net_3411 ) ,
+ .p3396 ( optlc_net_3412 ) , .p3397 ( optlc_net_3413 ) ,
+ .p3398 ( optlc_net_3414 ) , .p3399 ( optlc_net_3415 ) ,
+ .p3400 ( optlc_net_3416 ) , .p3401 ( optlc_net_3417 ) ,
+ .p3402 ( optlc_net_3418 ) , .p3403 ( optlc_net_3419 ) ,
+ .p3404 ( optlc_net_3420 ) , .p3405 ( optlc_net_3421 ) ,
+ .p3406 ( optlc_net_3422 ) , .p3407 ( optlc_net_3423 ) ,
+ .p3408 ( optlc_net_3424 ) , .p3409 ( optlc_net_3425 ) ,
+ .p3410 ( optlc_net_3426 ) , .p3411 ( optlc_net_3427 ) ,
+ .p3412 ( optlc_net_3428 ) , .p3413 ( optlc_net_3429 ) ,
+ .p3414 ( optlc_net_3430 ) , .p3415 ( optlc_net_3431 ) ,
+ .p3416 ( optlc_net_3432 ) , .p3417 ( optlc_net_3433 ) ,
+ .p3418 ( optlc_net_3434 ) , .p3419 ( optlc_net_3435 ) ,
+ .p3420 ( optlc_net_3436 ) , .p3421 ( optlc_net_3437 ) ,
+ .p3422 ( optlc_net_3438 ) , .p3423 ( optlc_net_3439 ) ,
+ .p3424 ( optlc_net_3440 ) , .p3425 ( optlc_net_3441 ) ,
+ .p3426 ( optlc_net_3442 ) , .p3427 ( optlc_net_3443 ) ,
+ .p3428 ( optlc_net_3444 ) , .p3429 ( optlc_net_3445 ) ,
+ .p3430 ( optlc_net_3446 ) , .p3431 ( optlc_net_3447 ) ,
+ .p3432 ( optlc_net_3448 ) , .p3433 ( optlc_net_3449 ) ,
+ .p3434 ( optlc_net_3450 ) , .p3435 ( optlc_net_3451 ) ,
+ .p3436 ( optlc_net_3452 ) , .p3437 ( optlc_net_3453 ) ,
+ .p3438 ( optlc_net_3454 ) , .p3439 ( optlc_net_3455 ) ,
+ .p3440 ( optlc_net_3456 ) , .p3441 ( optlc_net_3457 ) ,
+ .p3442 ( optlc_net_3458 ) , .p3443 ( optlc_net_3459 ) ,
+ .p3444 ( optlc_net_3460 ) , .p3445 ( optlc_net_3461 ) ,
+ .p3446 ( optlc_net_3462 ) , .p3447 ( optlc_net_3463 ) ,
+ .p3448 ( optlc_net_3464 ) , .p3449 ( optlc_net_3465 ) ,
+ .p3450 ( optlc_net_3466 ) , .p3451 ( optlc_net_3467 ) ,
+ .p3452 ( optlc_net_3468 ) , .p3453 ( optlc_net_3469 ) ,
+ .p3454 ( optlc_net_3470 ) , .p3455 ( optlc_net_3471 ) ,
+ .p3456 ( optlc_net_3472 ) , .p3457 ( optlc_net_3473 ) ,
+ .p3458 ( optlc_net_3474 ) , .p3459 ( optlc_net_3475 ) ,
+ .p3460 ( optlc_net_3476 ) , .p3461 ( optlc_net_3477 ) ,
+ .p3462 ( optlc_net_3478 ) , .p3463 ( optlc_net_3479 ) ,
+ .p3464 ( optlc_net_3480 ) , .p3465 ( optlc_net_3481 ) ,
+ .p3466 ( optlc_net_3482 ) , .p3467 ( optlc_net_3483 ) ,
+ .p3468 ( optlc_net_3484 ) , .p3469 ( optlc_net_3485 ) ,
+ .p3470 ( optlc_net_3486 ) , .p3471 ( optlc_net_3487 ) ,
+ .p3472 ( optlc_net_3488 ) , .p3473 ( optlc_net_3489 ) ,
+ .p3474 ( optlc_net_3490 ) , .p3475 ( optlc_net_3491 ) ,
+ .p3476 ( optlc_net_3492 ) , .p3477 ( optlc_net_3493 ) ,
+ .p3478 ( optlc_net_3494 ) , .p3479 ( optlc_net_3495 ) ,
+ .p3480 ( optlc_net_3496 ) , .p3481 ( optlc_net_3497 ) ,
+ .p3482 ( optlc_net_3498 ) , .p3483 ( optlc_net_3499 ) ,
+ .p3484 ( optlc_net_3500 ) , .p3485 ( optlc_net_3501 ) ,
+ .p3486 ( optlc_net_3502 ) , .p3487 ( optlc_net_3503 ) ,
+ .p3488 ( optlc_net_3504 ) , .p3489 ( optlc_net_3505 ) ,
+ .p3490 ( optlc_net_3506 ) , .p3491 ( optlc_net_3507 ) ,
+ .p3492 ( optlc_net_3508 ) , .p3493 ( optlc_net_3509 ) ,
+ .p3494 ( optlc_net_3510 ) , .p3495 ( optlc_net_3511 ) ,
+ .p3496 ( optlc_net_3512 ) , .p3497 ( optlc_net_3513 ) ,
+ .p3498 ( optlc_net_3514 ) , .p3499 ( optlc_net_3515 ) ,
+ .p3500 ( optlc_net_3516 ) , .p3501 ( optlc_net_3517 ) ,
+ .p3502 ( optlc_net_3518 ) , .p3503 ( optlc_net_3519 ) ,
+ .p3504 ( optlc_net_3520 ) , .p3505 ( optlc_net_3521 ) ,
+ .p3506 ( optlc_net_3522 ) , .p3507 ( optlc_net_3523 ) ,
+ .p3508 ( optlc_net_3524 ) , .p3509 ( optlc_net_3525 ) ,
+ .p3510 ( optlc_net_3526 ) , .p3511 ( optlc_net_3527 ) ,
+ .p3512 ( optlc_net_3528 ) , .p3513 ( optlc_net_3529 ) ,
+ .p3514 ( optlc_net_3530 ) , .p3515 ( optlc_net_3531 ) ,
+ .p3516 ( optlc_net_3532 ) , .p3517 ( optlc_net_3533 ) ,
+ .p3518 ( optlc_net_3534 ) , .p3519 ( optlc_net_3535 ) ,
+ .p3520 ( optlc_net_3536 ) , .p3521 ( optlc_net_3537 ) ,
+ .p3522 ( optlc_net_3538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( io_oeb[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( io_oeb[1] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( io_oeb[12] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( io_oeb[25] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .HI ( io_oeb[26] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .HI ( io_oeb[36] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .HI ( io_oeb[37] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( io_oeb[11] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_9 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( io_oeb[35] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_10 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_out[0] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_out[1] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[12] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[25] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[26] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[36] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[37] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( optlc_net_16 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( optlc_net_17 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( optlc_net_18 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_20 ( .LO ( optlc_net_19 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_39 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_40 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_41 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_42 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_43 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_44 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_46 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_47 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_48 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_74 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( optlc_net_75 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( optlc_net_76 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( optlc_net_77 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_79 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( optlc_net_78 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_80 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( optlc_net_79 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_81 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( optlc_net_80 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_82 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( optlc_net_81 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( optlc_net_82 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( optlc_net_83 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( optlc_net_84 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_86 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( optlc_net_85 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_87 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_87 ( .LO ( optlc_net_86 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( optlc_net_87 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( optlc_net_88 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( optlc_net_89 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( optlc_net_90 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( optlc_net_91 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( optlc_net_92 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( optlc_net_93 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( optlc_net_94 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( optlc_net_95 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( optlc_net_96 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( optlc_net_97 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( optlc_net_98 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( optlc_net_99 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( optlc_net_100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( optlc_net_101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( optlc_net_102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( optlc_net_103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( optlc_net_104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( optlc_net_105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( optlc_net_106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( optlc_net_107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( optlc_net_108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( optlc_net_109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( optlc_net_110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( optlc_net_111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( optlc_net_112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( optlc_net_113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( optlc_net_114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( optlc_net_115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( optlc_net_116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( optlc_net_117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( optlc_net_118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( optlc_net_119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( optlc_net_120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( optlc_net_121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( optlc_net_122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( optlc_net_123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( optlc_net_124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( optlc_net_125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( optlc_net_126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( optlc_net_127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( optlc_net_128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( optlc_net_129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( optlc_net_130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( optlc_net_131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( optlc_net_132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( optlc_net_133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( optlc_net_134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( optlc_net_135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( optlc_net_136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( optlc_net_137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( optlc_net_138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( optlc_net_139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( optlc_net_140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( optlc_net_141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( optlc_net_142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( optlc_net_143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( optlc_net_144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( optlc_net_145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( optlc_net_146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( optlc_net_147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( optlc_net_148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( optlc_net_149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( optlc_net_150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( optlc_net_151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( optlc_net_152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( optlc_net_153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( optlc_net_154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( optlc_net_155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( optlc_net_156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( optlc_net_157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( optlc_net_158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( optlc_net_159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( optlc_net_160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( optlc_net_161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_163 ( .LO ( optlc_net_162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( optlc_net_163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( optlc_net_164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( optlc_net_165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( optlc_net_166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( optlc_net_167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_169 ( .LO ( optlc_net_168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( optlc_net_169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( optlc_net_170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( optlc_net_171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( optlc_net_172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( optlc_net_173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( optlc_net_174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( optlc_net_175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( optlc_net_176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( optlc_net_177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( optlc_net_178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( optlc_net_179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( optlc_net_180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( optlc_net_181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_183 ( .LO ( optlc_net_182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( optlc_net_183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( optlc_net_184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( optlc_net_185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( optlc_net_186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( optlc_net_187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( optlc_net_188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( optlc_net_189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( optlc_net_190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( optlc_net_191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( optlc_net_192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( optlc_net_193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( optlc_net_194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( optlc_net_195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( optlc_net_196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_198 ( .LO ( optlc_net_197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( optlc_net_198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( optlc_net_199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( optlc_net_200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( optlc_net_201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( optlc_net_202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( optlc_net_203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( optlc_net_204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( optlc_net_205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( optlc_net_206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( optlc_net_207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( optlc_net_208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( optlc_net_209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( optlc_net_210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( optlc_net_211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( optlc_net_212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( optlc_net_213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( optlc_net_214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( optlc_net_215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( optlc_net_216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( optlc_net_217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( optlc_net_218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( optlc_net_219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( optlc_net_220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( optlc_net_221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( optlc_net_222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( optlc_net_223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( optlc_net_224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( optlc_net_225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( optlc_net_226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( optlc_net_227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( optlc_net_228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( optlc_net_229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_231 ( .LO ( optlc_net_230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( optlc_net_231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( optlc_net_232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_234 ( .LO ( optlc_net_233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( optlc_net_234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_236 ( .LO ( optlc_net_235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( optlc_net_236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_238 ( .LO ( optlc_net_237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( optlc_net_238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_240 ( .LO ( optlc_net_239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_241 ( .LO ( optlc_net_240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_242 ( .LO ( optlc_net_241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_243 ( .LO ( optlc_net_242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_244 ( .LO ( optlc_net_243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_245 ( .LO ( optlc_net_244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_246 ( .LO ( optlc_net_245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_247 ( .LO ( optlc_net_246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_248 ( .LO ( optlc_net_247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_249 ( .LO ( optlc_net_248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_250 ( .LO ( optlc_net_249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_251 ( .LO ( optlc_net_250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_252 ( .LO ( optlc_net_251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_253 ( .LO ( optlc_net_252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_254 ( .LO ( optlc_net_253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_255 ( .LO ( optlc_net_254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_256 ( .LO ( optlc_net_255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_257 ( .LO ( optlc_net_256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_258 ( .LO ( optlc_net_257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_259 ( .LO ( optlc_net_258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_260 ( .LO ( optlc_net_259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_261 ( .LO ( optlc_net_260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_262 ( .LO ( optlc_net_261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_263 ( .LO ( optlc_net_262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_264 ( .LO ( optlc_net_263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_265 ( .LO ( optlc_net_264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_266 ( .LO ( optlc_net_265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_267 ( .LO ( optlc_net_266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_268 ( .LO ( optlc_net_267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_269 ( .LO ( optlc_net_268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_274 ( .LO ( optlc_net_273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_280 ( .LO ( optlc_net_279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_284 ( .LO ( optlc_net_283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_295 ( .LO ( optlc_net_294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_298 ( .LO ( optlc_net_297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_311 ( .LO ( optlc_net_310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_313 ( .LO ( optlc_net_312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_315 ( .LO ( optlc_net_314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_327 ( .LO ( optlc_net_326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_330 ( .LO ( optlc_net_329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_334 ( .LO ( optlc_net_333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_336 ( .LO ( optlc_net_335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_342 ( .LO ( optlc_net_341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_351 ( .LO ( optlc_net_350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_353 ( .LO ( optlc_net_352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_355 ( .LO ( optlc_net_354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_361 ( .LO ( optlc_net_360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_365 ( .LO ( optlc_net_364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_367 ( .LO ( optlc_net_366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_401 ( .LO ( optlc_net_400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_403 ( .LO ( optlc_net_402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_413 ( .LO ( optlc_net_412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_415 ( .LO ( optlc_net_414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_751 ( .LO ( optlc_net_749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_935 ( .LO ( optlc_net_931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_937 ( .LO ( optlc_net_933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_939 ( .LO ( optlc_net_935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_943 ( .LO ( optlc_net_939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_944 ( .LO ( optlc_net_940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_966 ( .LO ( optlc_net_961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_971 ( .LO ( optlc_net_965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_977 ( .LO ( optlc_net_971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_982 ( .LO ( optlc_net_976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_986 ( .LO ( optlc_net_980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_990 ( .LO ( optlc_net_984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_996 ( .LO ( optlc_net_990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1003 ( .LO ( optlc_net_997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1005 ( .LO ( optlc_net_999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_1000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_1001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_1002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1009 ( .LO ( optlc_net_1003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_1004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1011 ( .LO ( optlc_net_1005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1012 ( .LO ( optlc_net_1006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_1007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1014 ( .LO ( optlc_net_1008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1015 ( .LO ( optlc_net_1009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1016 ( .LO ( optlc_net_1010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1017 ( .LO ( optlc_net_1011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1018 ( .LO ( optlc_net_1012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1019 ( .LO ( optlc_net_1013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1020 ( .LO ( optlc_net_1014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1021 ( .LO ( optlc_net_1015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1022 ( .LO ( optlc_net_1016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1023 ( .LO ( optlc_net_1017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1024 ( .LO ( optlc_net_1018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1025 ( .LO ( optlc_net_1019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1026 ( .LO ( optlc_net_1020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1027 ( .LO ( optlc_net_1021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1028 ( .LO ( optlc_net_1022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1029 ( .LO ( optlc_net_1023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1030 ( .LO ( optlc_net_1024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1031 ( .LO ( optlc_net_1025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1032 ( .LO ( optlc_net_1026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1033 ( .LO ( optlc_net_1027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1034 ( .LO ( optlc_net_1028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1035 ( .LO ( optlc_net_1029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1036 ( .LO ( optlc_net_1030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1037 ( .LO ( optlc_net_1031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1038 ( .LO ( optlc_net_1032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1039 ( .LO ( optlc_net_1033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1040 ( .LO ( optlc_net_1034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1041 ( .LO ( optlc_net_1035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1042 ( .LO ( optlc_net_1036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1044 ( .LO ( optlc_net_1037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1045 ( .LO ( optlc_net_1038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1046 ( .LO ( optlc_net_1039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1047 ( .LO ( optlc_net_1040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1048 ( .LO ( optlc_net_1041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1049 ( .LO ( optlc_net_1042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1050 ( .LO ( optlc_net_1043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1051 ( .LO ( optlc_net_1044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1052 ( .LO ( optlc_net_1045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1053 ( .LO ( optlc_net_1046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1054 ( .LO ( optlc_net_1047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1055 ( .LO ( optlc_net_1048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1056 ( .LO ( optlc_net_1049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1057 ( .LO ( optlc_net_1050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1058 ( .LO ( optlc_net_1051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1059 ( .LO ( optlc_net_1052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1060 ( .LO ( optlc_net_1053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1061 ( .LO ( optlc_net_1054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1062 ( .LO ( optlc_net_1055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1063 ( .LO ( optlc_net_1056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1064 ( .LO ( optlc_net_1057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1065 ( .LO ( optlc_net_1058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1066 ( .LO ( optlc_net_1059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1067 ( .LO ( optlc_net_1060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1068 ( .LO ( optlc_net_1061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1069 ( .LO ( optlc_net_1062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1070 ( .LO ( optlc_net_1063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1072 ( .LO ( optlc_net_1064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1073 ( .LO ( optlc_net_1065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1074 ( .LO ( optlc_net_1066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1075 ( .LO ( optlc_net_1067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1077 ( .LO ( optlc_net_1068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1078 ( .LO ( optlc_net_1069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1079 ( .LO ( optlc_net_1070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1080 ( .LO ( optlc_net_1071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1081 ( .LO ( optlc_net_1072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1082 ( .LO ( optlc_net_1073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1083 ( .LO ( optlc_net_1074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1084 ( .LO ( optlc_net_1075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1085 ( .LO ( optlc_net_1076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1086 ( .LO ( optlc_net_1077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1087 ( .LO ( optlc_net_1078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1088 ( .LO ( optlc_net_1079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1089 ( .LO ( optlc_net_1080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1090 ( .LO ( optlc_net_1081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1091 ( .LO ( optlc_net_1082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1092 ( .LO ( optlc_net_1083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1093 ( .LO ( optlc_net_1084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1094 ( .LO ( optlc_net_1085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1095 ( .LO ( optlc_net_1086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1096 ( .LO ( optlc_net_1087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1097 ( .LO ( optlc_net_1088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1098 ( .LO ( optlc_net_1089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1099 ( .LO ( optlc_net_1090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1100 ( .LO ( optlc_net_1091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1101 ( .LO ( optlc_net_1092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1102 ( .LO ( optlc_net_1093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1103 ( .LO ( optlc_net_1094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1104 ( .LO ( optlc_net_1095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1105 ( .LO ( optlc_net_1096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1106 ( .LO ( optlc_net_1097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1107 ( .LO ( optlc_net_1098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1108 ( .LO ( optlc_net_1099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1109 ( .LO ( optlc_net_1100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1110 ( .LO ( optlc_net_1101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1111 ( .LO ( optlc_net_1102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1112 ( .LO ( optlc_net_1103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1113 ( .LO ( optlc_net_1104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1114 ( .LO ( optlc_net_1105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1115 ( .LO ( optlc_net_1106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1116 ( .LO ( optlc_net_1107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1117 ( .LO ( optlc_net_1108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1118 ( .LO ( optlc_net_1109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1119 ( .LO ( optlc_net_1110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1120 ( .LO ( optlc_net_1111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1121 ( .LO ( optlc_net_1112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1122 ( .LO ( optlc_net_1113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1123 ( .LO ( optlc_net_1114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1124 ( .LO ( optlc_net_1115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1125 ( .LO ( optlc_net_1116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1126 ( .LO ( optlc_net_1117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1127 ( .LO ( optlc_net_1118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1128 ( .LO ( optlc_net_1119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1129 ( .LO ( optlc_net_1120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1130 ( .LO ( optlc_net_1121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1131 ( .LO ( optlc_net_1122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1132 ( .LO ( optlc_net_1123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1133 ( .LO ( optlc_net_1124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1134 ( .LO ( optlc_net_1125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1135 ( .LO ( optlc_net_1126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1136 ( .LO ( optlc_net_1127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1137 ( .LO ( optlc_net_1128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1138 ( .LO ( optlc_net_1129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1139 ( .LO ( optlc_net_1130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1140 ( .LO ( optlc_net_1131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1141 ( .LO ( optlc_net_1132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1142 ( .LO ( optlc_net_1133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1143 ( .LO ( optlc_net_1134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1144 ( .LO ( optlc_net_1135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1145 ( .LO ( optlc_net_1136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1146 ( .LO ( optlc_net_1137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1147 ( .LO ( optlc_net_1138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1148 ( .LO ( optlc_net_1139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1149 ( .LO ( optlc_net_1140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1150 ( .LO ( optlc_net_1141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1151 ( .LO ( optlc_net_1142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1152 ( .LO ( optlc_net_1143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1154 ( .LO ( optlc_net_1144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1155 ( .LO ( optlc_net_1145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1156 ( .LO ( optlc_net_1146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1157 ( .LO ( optlc_net_1147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1158 ( .LO ( optlc_net_1148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1159 ( .LO ( optlc_net_1149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1160 ( .LO ( optlc_net_1150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1161 ( .LO ( optlc_net_1151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1162 ( .LO ( optlc_net_1152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1163 ( .LO ( optlc_net_1153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1164 ( .LO ( optlc_net_1154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1165 ( .LO ( optlc_net_1155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1166 ( .LO ( optlc_net_1156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1167 ( .LO ( optlc_net_1157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1168 ( .LO ( optlc_net_1158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1169 ( .LO ( optlc_net_1159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1170 ( .LO ( optlc_net_1160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1171 ( .LO ( optlc_net_1161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1172 ( .LO ( optlc_net_1162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1173 ( .LO ( optlc_net_1163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1174 ( .LO ( optlc_net_1164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1175 ( .LO ( optlc_net_1165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1176 ( .LO ( optlc_net_1166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1177 ( .LO ( optlc_net_1167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1178 ( .LO ( optlc_net_1168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1179 ( .LO ( optlc_net_1169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1180 ( .LO ( optlc_net_1170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1181 ( .LO ( optlc_net_1171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1182 ( .LO ( optlc_net_1172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1183 ( .LO ( optlc_net_1173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1184 ( .LO ( optlc_net_1174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1185 ( .LO ( optlc_net_1175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1186 ( .LO ( optlc_net_1176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1187 ( .LO ( optlc_net_1177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1188 ( .LO ( optlc_net_1178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1189 ( .LO ( optlc_net_1179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1190 ( .LO ( optlc_net_1180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1191 ( .LO ( optlc_net_1181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1192 ( .LO ( optlc_net_1182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1193 ( .LO ( optlc_net_1183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1194 ( .LO ( optlc_net_1184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1195 ( .LO ( optlc_net_1185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1196 ( .LO ( optlc_net_1186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1197 ( .LO ( optlc_net_1187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1198 ( .LO ( optlc_net_1188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1199 ( .LO ( optlc_net_1189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1200 ( .LO ( optlc_net_1190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1201 ( .LO ( optlc_net_1191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1202 ( .LO ( optlc_net_1192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1203 ( .LO ( optlc_net_1193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1204 ( .LO ( optlc_net_1194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1205 ( .LO ( optlc_net_1195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1207 ( .LO ( optlc_net_1196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1208 ( .LO ( optlc_net_1197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1209 ( .LO ( optlc_net_1198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1210 ( .LO ( optlc_net_1199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1211 ( .LO ( optlc_net_1200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1212 ( .LO ( optlc_net_1201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1213 ( .LO ( optlc_net_1202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1214 ( .LO ( optlc_net_1203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1215 ( .LO ( optlc_net_1204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1216 ( .LO ( optlc_net_1205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1217 ( .LO ( optlc_net_1206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1218 ( .LO ( optlc_net_1207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1219 ( .LO ( optlc_net_1208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1220 ( .LO ( optlc_net_1209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1221 ( .LO ( optlc_net_1210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1222 ( .LO ( optlc_net_1211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1223 ( .LO ( optlc_net_1212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1224 ( .LO ( optlc_net_1213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1225 ( .LO ( optlc_net_1214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1226 ( .LO ( optlc_net_1215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1227 ( .LO ( optlc_net_1216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1228 ( .LO ( optlc_net_1217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1229 ( .LO ( optlc_net_1218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1230 ( .LO ( optlc_net_1219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1231 ( .LO ( optlc_net_1220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1232 ( .LO ( optlc_net_1221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1233 ( .LO ( optlc_net_1222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1234 ( .LO ( optlc_net_1223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1235 ( .LO ( optlc_net_1224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1236 ( .LO ( optlc_net_1225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1237 ( .LO ( optlc_net_1226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1238 ( .LO ( optlc_net_1227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1239 ( .LO ( optlc_net_1228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1241 ( .LO ( optlc_net_1229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1243 ( .LO ( optlc_net_1230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1244 ( .LO ( optlc_net_1231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1245 ( .LO ( optlc_net_1232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1246 ( .LO ( optlc_net_1233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1247 ( .LO ( optlc_net_1234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1248 ( .LO ( optlc_net_1235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1250 ( .LO ( optlc_net_1236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1252 ( .LO ( optlc_net_1237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1253 ( .LO ( optlc_net_1238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1254 ( .LO ( optlc_net_1239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1255 ( .LO ( optlc_net_1240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1257 ( .LO ( optlc_net_1241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1258 ( .LO ( optlc_net_1242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1260 ( .LO ( optlc_net_1243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1261 ( .LO ( optlc_net_1244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1262 ( .LO ( optlc_net_1245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1263 ( .LO ( optlc_net_1246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1264 ( .LO ( optlc_net_1247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1265 ( .LO ( optlc_net_1248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1266 ( .LO ( optlc_net_1249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1267 ( .LO ( optlc_net_1250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1268 ( .LO ( optlc_net_1251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1269 ( .LO ( optlc_net_1252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1270 ( .LO ( optlc_net_1253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1271 ( .LO ( optlc_net_1254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1272 ( .LO ( optlc_net_1255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1273 ( .LO ( optlc_net_1256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1274 ( .LO ( optlc_net_1257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1276 ( .LO ( optlc_net_1258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1277 ( .LO ( optlc_net_1259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1278 ( .LO ( optlc_net_1260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1280 ( .LO ( optlc_net_1261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1281 ( .LO ( optlc_net_1262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1282 ( .LO ( optlc_net_1263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1283 ( .LO ( optlc_net_1264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1284 ( .LO ( optlc_net_1265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1285 ( .LO ( optlc_net_1266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1286 ( .LO ( optlc_net_1267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1287 ( .LO ( optlc_net_1268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1288 ( .LO ( optlc_net_1269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1289 ( .LO ( optlc_net_1270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1290 ( .LO ( optlc_net_1271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1291 ( .LO ( optlc_net_1272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1292 ( .LO ( optlc_net_1273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1293 ( .LO ( optlc_net_1274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1294 ( .LO ( optlc_net_1275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1295 ( .LO ( optlc_net_1276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1296 ( .LO ( optlc_net_1277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1297 ( .LO ( optlc_net_1278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1298 ( .LO ( optlc_net_1279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1299 ( .LO ( optlc_net_1280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1300 ( .LO ( optlc_net_1281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1301 ( .LO ( optlc_net_1282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1302 ( .LO ( optlc_net_1283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1303 ( .LO ( optlc_net_1284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1304 ( .LO ( optlc_net_1285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1305 ( .LO ( optlc_net_1286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1306 ( .LO ( optlc_net_1287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1307 ( .LO ( optlc_net_1288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1308 ( .LO ( optlc_net_1289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1309 ( .LO ( optlc_net_1290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1310 ( .LO ( optlc_net_1291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1311 ( .LO ( optlc_net_1292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1312 ( .LO ( optlc_net_1293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1313 ( .LO ( optlc_net_1294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1314 ( .LO ( optlc_net_1295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1315 ( .LO ( optlc_net_1296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1316 ( .LO ( optlc_net_1297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1317 ( .LO ( optlc_net_1298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1318 ( .LO ( optlc_net_1299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1319 ( .LO ( optlc_net_1300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1320 ( .LO ( optlc_net_1301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1321 ( .LO ( optlc_net_1302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1322 ( .LO ( optlc_net_1303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1323 ( .LO ( optlc_net_1304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1324 ( .LO ( optlc_net_1305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1326 ( .LO ( optlc_net_1306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1327 ( .LO ( optlc_net_1307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1328 ( .LO ( optlc_net_1308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1329 ( .LO ( optlc_net_1309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1330 ( .LO ( optlc_net_1310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1331 ( .LO ( optlc_net_1311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1332 ( .LO ( optlc_net_1312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1333 ( .LO ( optlc_net_1313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1334 ( .LO ( optlc_net_1314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1335 ( .LO ( optlc_net_1315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1336 ( .LO ( optlc_net_1316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1337 ( .LO ( optlc_net_1317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1338 ( .LO ( optlc_net_1318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1339 ( .LO ( optlc_net_1319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1340 ( .LO ( optlc_net_1320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1342 ( .LO ( optlc_net_1321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1343 ( .LO ( optlc_net_1322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1344 ( .LO ( optlc_net_1323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1345 ( .LO ( optlc_net_1324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1346 ( .LO ( optlc_net_1325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1347 ( .LO ( optlc_net_1326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1348 ( .LO ( optlc_net_1327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1350 ( .LO ( optlc_net_1328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1351 ( .LO ( optlc_net_1329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1352 ( .LO ( optlc_net_1330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1353 ( .LO ( optlc_net_1331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1354 ( .LO ( optlc_net_1332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1355 ( .LO ( optlc_net_1333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1356 ( .LO ( optlc_net_1334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1357 ( .LO ( optlc_net_1335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1358 ( .LO ( optlc_net_1336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1359 ( .LO ( optlc_net_1337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1360 ( .LO ( optlc_net_1338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1361 ( .LO ( optlc_net_1339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1362 ( .LO ( optlc_net_1340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1363 ( .LO ( optlc_net_1341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1364 ( .LO ( optlc_net_1342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1365 ( .LO ( optlc_net_1343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1366 ( .LO ( optlc_net_1344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1367 ( .LO ( optlc_net_1345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1368 ( .LO ( optlc_net_1346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1369 ( .LO ( optlc_net_1347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1370 ( .LO ( optlc_net_1348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1371 ( .LO ( optlc_net_1349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1372 ( .LO ( optlc_net_1350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1373 ( .LO ( optlc_net_1351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1374 ( .LO ( optlc_net_1352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1375 ( .LO ( optlc_net_1353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1376 ( .LO ( optlc_net_1354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1377 ( .LO ( optlc_net_1355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1378 ( .LO ( optlc_net_1356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1379 ( .LO ( optlc_net_1357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1380 ( .LO ( optlc_net_1358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1381 ( .LO ( optlc_net_1359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1382 ( .LO ( optlc_net_1360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1383 ( .LO ( optlc_net_1361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1384 ( .LO ( optlc_net_1362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1385 ( .LO ( optlc_net_1363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1387 ( .LO ( optlc_net_1364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1388 ( .LO ( optlc_net_1365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1389 ( .LO ( optlc_net_1366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1391 ( .LO ( optlc_net_1367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1393 ( .LO ( optlc_net_1368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1394 ( .LO ( optlc_net_1369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1395 ( .LO ( optlc_net_1370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1396 ( .LO ( optlc_net_1371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1397 ( .LO ( optlc_net_1372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1398 ( .LO ( optlc_net_1373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1399 ( .LO ( optlc_net_1374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1400 ( .LO ( optlc_net_1375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1401 ( .LO ( optlc_net_1376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1402 ( .LO ( optlc_net_1377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1404 ( .LO ( optlc_net_1378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1405 ( .LO ( optlc_net_1379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1406 ( .LO ( optlc_net_1380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1407 ( .LO ( optlc_net_1381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1408 ( .LO ( optlc_net_1382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1409 ( .LO ( optlc_net_1383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1411 ( .LO ( optlc_net_1384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1412 ( .LO ( optlc_net_1385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1414 ( .LO ( optlc_net_1386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1416 ( .LO ( optlc_net_1387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1417 ( .LO ( optlc_net_1388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1418 ( .LO ( optlc_net_1389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1419 ( .LO ( optlc_net_1390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1420 ( .LO ( optlc_net_1391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1421 ( .LO ( optlc_net_1392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1422 ( .LO ( optlc_net_1393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1424 ( .LO ( optlc_net_1394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1425 ( .LO ( optlc_net_1395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1426 ( .LO ( optlc_net_1396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1427 ( .LO ( optlc_net_1397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1428 ( .LO ( optlc_net_1398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1429 ( .LO ( optlc_net_1399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1430 ( .LO ( optlc_net_1400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1431 ( .LO ( optlc_net_1401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1433 ( .LO ( optlc_net_1402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1434 ( .LO ( optlc_net_1403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1436 ( .LO ( optlc_net_1404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1437 ( .LO ( optlc_net_1405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1438 ( .LO ( optlc_net_1406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1439 ( .LO ( optlc_net_1407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1440 ( .LO ( optlc_net_1408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1442 ( .LO ( optlc_net_1409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1443 ( .LO ( optlc_net_1410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1444 ( .LO ( optlc_net_1411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1446 ( .LO ( optlc_net_1412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1447 ( .LO ( optlc_net_1413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1448 ( .LO ( optlc_net_1414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1450 ( .LO ( optlc_net_1415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1452 ( .LO ( optlc_net_1416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1453 ( .LO ( optlc_net_1417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1454 ( .LO ( optlc_net_1418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1455 ( .LO ( optlc_net_1419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1457 ( .LO ( optlc_net_1420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1459 ( .LO ( optlc_net_1421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1460 ( .LO ( optlc_net_1422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1463 ( .LO ( optlc_net_1424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1467 ( .LO ( optlc_net_1427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1468 ( .LO ( optlc_net_1428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1469 ( .LO ( optlc_net_1429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1471 ( .LO ( optlc_net_1430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1474 ( .LO ( optlc_net_1432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1475 ( .LO ( optlc_net_1433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1477 ( .LO ( optlc_net_1434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1478 ( .LO ( optlc_net_1435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1479 ( .LO ( optlc_net_1436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1480 ( .LO ( optlc_net_1437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1482 ( .LO ( optlc_net_1438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1486 ( .LO ( optlc_net_1441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1488 ( .LO ( optlc_net_1442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1491 ( .LO ( optlc_net_1445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1492 ( .LO ( optlc_net_1446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1493 ( .LO ( optlc_net_1447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1494 ( .LO ( optlc_net_1448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1496 ( .LO ( optlc_net_1449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1497 ( .LO ( optlc_net_1450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1499 ( .LO ( optlc_net_1451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1501 ( .LO ( optlc_net_1452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1502 ( .LO ( optlc_net_1453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1503 ( .LO ( optlc_net_1454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1505 ( .LO ( optlc_net_1455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1506 ( .LO ( optlc_net_1456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1507 ( .LO ( optlc_net_1457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1508 ( .LO ( optlc_net_1458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1509 ( .LO ( optlc_net_1459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1510 ( .LO ( optlc_net_1460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1512 ( .LO ( optlc_net_1461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1513 ( .LO ( optlc_net_1462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1514 ( .LO ( optlc_net_1463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1515 ( .LO ( optlc_net_1464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1516 ( .LO ( optlc_net_1465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1517 ( .LO ( optlc_net_1466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1518 ( .LO ( optlc_net_1467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1519 ( .LO ( optlc_net_1468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1521 ( .LO ( optlc_net_1469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1523 ( .LO ( optlc_net_1470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1524 ( .LO ( optlc_net_1471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1525 ( .LO ( optlc_net_1472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1527 ( .LO ( optlc_net_1473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1528 ( .LO ( optlc_net_1474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1529 ( .LO ( optlc_net_1475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1530 ( .LO ( optlc_net_1476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1531 ( .LO ( optlc_net_1477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1532 ( .LO ( optlc_net_1478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1533 ( .LO ( optlc_net_1479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1534 ( .LO ( optlc_net_1480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1536 ( .LO ( optlc_net_1481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1538 ( .LO ( optlc_net_1482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1539 ( .LO ( optlc_net_1483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1540 ( .LO ( optlc_net_1484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1542 ( .LO ( optlc_net_1485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1543 ( .LO ( optlc_net_1486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1544 ( .LO ( optlc_net_1487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1545 ( .LO ( optlc_net_1488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1547 ( .LO ( optlc_net_1489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1549 ( .LO ( optlc_net_1490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1551 ( .LO ( optlc_net_1491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1552 ( .LO ( optlc_net_1492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1553 ( .LO ( optlc_net_1493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1555 ( .LO ( optlc_net_1494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1557 ( .LO ( optlc_net_1495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1559 ( .LO ( optlc_net_1496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1560 ( .LO ( optlc_net_1497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1561 ( .LO ( optlc_net_1498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1562 ( .LO ( optlc_net_1499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1563 ( .LO ( optlc_net_1500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1564 ( .LO ( optlc_net_1501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1566 ( .LO ( optlc_net_1502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1567 ( .LO ( optlc_net_1503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1568 ( .LO ( optlc_net_1504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1570 ( .LO ( optlc_net_1505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1571 ( .LO ( optlc_net_1506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1572 ( .LO ( optlc_net_1507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1573 ( .LO ( optlc_net_1508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1575 ( .LO ( optlc_net_1509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1577 ( .LO ( optlc_net_1510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1578 ( .LO ( optlc_net_1511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1580 ( .LO ( optlc_net_1512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1582 ( .LO ( optlc_net_1513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1583 ( .LO ( optlc_net_1514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1585 ( .LO ( optlc_net_1515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1586 ( .LO ( optlc_net_1516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1588 ( .LO ( optlc_net_1517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1590 ( .LO ( optlc_net_1518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1591 ( .LO ( optlc_net_1519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1592 ( .LO ( optlc_net_1520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1594 ( .LO ( optlc_net_1521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1595 ( .LO ( optlc_net_1522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1597 ( .LO ( optlc_net_1523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1598 ( .LO ( optlc_net_1524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1599 ( .LO ( optlc_net_1525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1600 ( .LO ( optlc_net_1526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1602 ( .LO ( optlc_net_1527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1603 ( .LO ( optlc_net_1528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1605 ( .LO ( optlc_net_1529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1606 ( .LO ( optlc_net_1530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1608 ( .LO ( optlc_net_1531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1610 ( .LO ( optlc_net_1532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1611 ( .LO ( optlc_net_1533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1612 ( .LO ( optlc_net_1534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1613 ( .LO ( optlc_net_1535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1614 ( .LO ( optlc_net_1536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1615 ( .LO ( optlc_net_1537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1617 ( .LO ( optlc_net_1538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1619 ( .LO ( optlc_net_1539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1621 ( .LO ( optlc_net_1540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1623 ( .LO ( optlc_net_1541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1625 ( .LO ( optlc_net_1542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1626 ( .LO ( optlc_net_1543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1627 ( .LO ( optlc_net_1544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1628 ( .LO ( optlc_net_1545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1629 ( .LO ( optlc_net_1546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1630 ( .LO ( optlc_net_1547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1631 ( .LO ( optlc_net_1548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1633 ( .LO ( optlc_net_1549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1634 ( .LO ( optlc_net_1550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1636 ( .LO ( optlc_net_1551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1637 ( .LO ( optlc_net_1552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1639 ( .LO ( optlc_net_1553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1641 ( .LO ( optlc_net_1554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1642 ( .LO ( optlc_net_1555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1643 ( .LO ( optlc_net_1556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1645 ( .LO ( optlc_net_1557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1646 ( .LO ( optlc_net_1558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1647 ( .LO ( optlc_net_1559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1648 ( .LO ( optlc_net_1560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1649 ( .LO ( optlc_net_1561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1650 ( .LO ( optlc_net_1562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1651 ( .LO ( optlc_net_1563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1652 ( .LO ( optlc_net_1564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1654 ( .LO ( optlc_net_1565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1655 ( .LO ( optlc_net_1566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1656 ( .LO ( optlc_net_1567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1657 ( .LO ( optlc_net_1568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1659 ( .LO ( optlc_net_1569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1661 ( .LO ( optlc_net_1570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1662 ( .LO ( optlc_net_1571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1663 ( .LO ( optlc_net_1572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1665 ( .LO ( optlc_net_1573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1667 ( .LO ( optlc_net_1574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1669 ( .LO ( optlc_net_1575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1671 ( .LO ( optlc_net_1576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1672 ( .LO ( optlc_net_1577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1674 ( .LO ( optlc_net_1578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1675 ( .LO ( optlc_net_1579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1676 ( .LO ( optlc_net_1580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1677 ( .LO ( optlc_net_1581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1679 ( .LO ( optlc_net_1582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1681 ( .LO ( optlc_net_1583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1683 ( .LO ( optlc_net_1584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1685 ( .LO ( optlc_net_1585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1687 ( .LO ( optlc_net_1586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1689 ( .LO ( optlc_net_1587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1691 ( .LO ( optlc_net_1588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1692 ( .LO ( optlc_net_1589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1693 ( .LO ( optlc_net_1590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1695 ( .LO ( optlc_net_1591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1696 ( .LO ( optlc_net_1592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1698 ( .LO ( optlc_net_1593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1700 ( .LO ( optlc_net_1594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1701 ( .LO ( optlc_net_1595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1702 ( .LO ( optlc_net_1596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1704 ( .LO ( optlc_net_1597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1706 ( .LO ( optlc_net_1598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1707 ( .LO ( optlc_net_1599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1708 ( .LO ( optlc_net_1600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1710 ( .LO ( optlc_net_1601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1712 ( .LO ( optlc_net_1602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1713 ( .LO ( optlc_net_1603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1714 ( .LO ( optlc_net_1604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1715 ( .LO ( optlc_net_1605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1716 ( .LO ( optlc_net_1606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1717 ( .LO ( optlc_net_1607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1718 ( .LO ( optlc_net_1608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1719 ( .LO ( optlc_net_1609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1721 ( .LO ( optlc_net_1610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1722 ( .LO ( optlc_net_1611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1723 ( .LO ( optlc_net_1612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1725 ( .LO ( optlc_net_1613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1726 ( .LO ( optlc_net_1614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1728 ( .LO ( optlc_net_1615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1730 ( .LO ( optlc_net_1616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1731 ( .LO ( optlc_net_1617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1732 ( .LO ( optlc_net_1618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1733 ( .LO ( optlc_net_1619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1734 ( .LO ( optlc_net_1620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1735 ( .LO ( optlc_net_1621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1737 ( .LO ( optlc_net_1622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1739 ( .LO ( optlc_net_1623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1741 ( .LO ( optlc_net_1624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1743 ( .LO ( optlc_net_1625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1745 ( .LO ( optlc_net_1626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1746 ( .LO ( optlc_net_1627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1748 ( .LO ( optlc_net_1628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1750 ( .LO ( optlc_net_1629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1751 ( .LO ( optlc_net_1630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1752 ( .LO ( optlc_net_1631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1753 ( .LO ( optlc_net_1632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1755 ( .LO ( optlc_net_1633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1757 ( .LO ( optlc_net_1634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1759 ( .LO ( optlc_net_1635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1760 ( .LO ( optlc_net_1636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1761 ( .LO ( optlc_net_1637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1762 ( .LO ( optlc_net_1638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1763 ( .LO ( optlc_net_1639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1764 ( .LO ( optlc_net_1640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1765 ( .LO ( optlc_net_1641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1766 ( .LO ( optlc_net_1642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1768 ( .LO ( optlc_net_1643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1769 ( .LO ( optlc_net_1644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1771 ( .LO ( optlc_net_1645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1772 ( .LO ( optlc_net_1646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1773 ( .LO ( optlc_net_1647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1775 ( .LO ( optlc_net_1648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1776 ( .LO ( optlc_net_1649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1777 ( .LO ( optlc_net_1650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1778 ( .LO ( optlc_net_1651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1780 ( .LO ( optlc_net_1652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1782 ( .LO ( optlc_net_1653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1783 ( .LO ( optlc_net_1654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1784 ( .LO ( optlc_net_1655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1785 ( .LO ( optlc_net_1656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1787 ( .LO ( optlc_net_1657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1788 ( .LO ( optlc_net_1658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1790 ( .LO ( optlc_net_1659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1791 ( .LO ( optlc_net_1660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1793 ( .LO ( optlc_net_1661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1794 ( .LO ( optlc_net_1662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1796 ( .LO ( optlc_net_1663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1797 ( .LO ( optlc_net_1664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1799 ( .LO ( optlc_net_1665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1801 ( .LO ( optlc_net_1666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1803 ( .LO ( optlc_net_1667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1805 ( .LO ( optlc_net_1668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1806 ( .LO ( optlc_net_1669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1807 ( .LO ( optlc_net_1670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1808 ( .LO ( optlc_net_1671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1810 ( .LO ( optlc_net_1672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1812 ( .LO ( optlc_net_1673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1813 ( .LO ( optlc_net_1674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1814 ( .LO ( optlc_net_1675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1816 ( .LO ( optlc_net_1676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1817 ( .LO ( optlc_net_1677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1818 ( .LO ( optlc_net_1678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1819 ( .LO ( optlc_net_1679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1820 ( .LO ( optlc_net_1680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1822 ( .LO ( optlc_net_1681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1823 ( .LO ( optlc_net_1682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1824 ( .LO ( optlc_net_1683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1825 ( .LO ( optlc_net_1684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1826 ( .LO ( optlc_net_1685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1828 ( .LO ( optlc_net_1686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1829 ( .LO ( optlc_net_1687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1831 ( .LO ( optlc_net_1688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1832 ( .LO ( optlc_net_1689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1833 ( .LO ( optlc_net_1690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1834 ( .LO ( optlc_net_1691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1836 ( .LO ( optlc_net_1692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1838 ( .LO ( optlc_net_1693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1839 ( .LO ( optlc_net_1694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1840 ( .LO ( optlc_net_1695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1842 ( .LO ( optlc_net_1696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1843 ( .LO ( optlc_net_1697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1844 ( .LO ( optlc_net_1698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1846 ( .LO ( optlc_net_1699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1847 ( .LO ( optlc_net_1700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1848 ( .LO ( optlc_net_1701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1850 ( .LO ( optlc_net_1702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1851 ( .LO ( optlc_net_1703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1853 ( .LO ( optlc_net_1704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1854 ( .LO ( optlc_net_1705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1856 ( .LO ( optlc_net_1706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1858 ( .LO ( optlc_net_1707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1860 ( .LO ( optlc_net_1708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1861 ( .LO ( optlc_net_1709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1862 ( .LO ( optlc_net_1710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1863 ( .LO ( optlc_net_1711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1864 ( .LO ( optlc_net_1712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1866 ( .LO ( optlc_net_1713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1867 ( .LO ( optlc_net_1714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1869 ( .LO ( optlc_net_1715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1871 ( .LO ( optlc_net_1716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1872 ( .LO ( optlc_net_1717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1873 ( .LO ( optlc_net_1718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1875 ( .LO ( optlc_net_1719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1877 ( .LO ( optlc_net_1720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1878 ( .LO ( optlc_net_1721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1879 ( .LO ( optlc_net_1722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1881 ( .LO ( optlc_net_1723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1882 ( .LO ( optlc_net_1724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1883 ( .LO ( optlc_net_1725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1885 ( .LO ( optlc_net_1726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1886 ( .LO ( optlc_net_1727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1887 ( .LO ( optlc_net_1728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1888 ( .LO ( optlc_net_1729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1889 ( .LO ( optlc_net_1730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1890 ( .LO ( optlc_net_1731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1892 ( .LO ( optlc_net_1732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1893 ( .LO ( optlc_net_1733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1894 ( .LO ( optlc_net_1734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1895 ( .LO ( optlc_net_1735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1896 ( .LO ( optlc_net_1736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1897 ( .LO ( optlc_net_1737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1898 ( .LO ( optlc_net_1738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1900 ( .LO ( optlc_net_1739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1901 ( .LO ( optlc_net_1740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1903 ( .LO ( optlc_net_1741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1905 ( .LO ( optlc_net_1742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1906 ( .LO ( optlc_net_1743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1907 ( .LO ( optlc_net_1744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1908 ( .LO ( optlc_net_1745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1909 ( .LO ( optlc_net_1746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1910 ( .LO ( optlc_net_1747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1912 ( .LO ( optlc_net_1748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1913 ( .LO ( optlc_net_1749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1914 ( .LO ( optlc_net_1750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1915 ( .LO ( optlc_net_1751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1916 ( .LO ( optlc_net_1752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1917 ( .LO ( optlc_net_1753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1919 ( .LO ( optlc_net_1754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1920 ( .LO ( optlc_net_1755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1921 ( .LO ( optlc_net_1756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1922 ( .LO ( optlc_net_1757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1923 ( .LO ( optlc_net_1758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1924 ( .LO ( optlc_net_1759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1926 ( .LO ( optlc_net_1760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1928 ( .LO ( optlc_net_1761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1929 ( .LO ( optlc_net_1762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1931 ( .LO ( optlc_net_1763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1933 ( .LO ( optlc_net_1764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1934 ( .LO ( optlc_net_1765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1935 ( .LO ( optlc_net_1766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1936 ( .LO ( optlc_net_1767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1937 ( .LO ( optlc_net_1768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1938 ( .LO ( optlc_net_1769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1939 ( .LO ( optlc_net_1770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1941 ( .LO ( optlc_net_1771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1942 ( .LO ( optlc_net_1772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1943 ( .LO ( optlc_net_1773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1944 ( .LO ( optlc_net_1774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1945 ( .LO ( optlc_net_1775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1946 ( .LO ( optlc_net_1776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1947 ( .LO ( optlc_net_1777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1948 ( .LO ( optlc_net_1778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1950 ( .LO ( optlc_net_1779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1951 ( .LO ( optlc_net_1780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1952 ( .LO ( optlc_net_1781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1954 ( .LO ( optlc_net_1782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1955 ( .LO ( optlc_net_1783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1957 ( .LO ( optlc_net_1784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1959 ( .LO ( optlc_net_1785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1961 ( .LO ( optlc_net_1786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1963 ( .LO ( optlc_net_1787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1964 ( .LO ( optlc_net_1788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1965 ( .LO ( optlc_net_1789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1967 ( .LO ( optlc_net_1790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1968 ( .LO ( optlc_net_1791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1969 ( .LO ( optlc_net_1792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1970 ( .LO ( optlc_net_1793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1971 ( .LO ( optlc_net_1794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1972 ( .LO ( optlc_net_1795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1973 ( .LO ( optlc_net_1796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1974 ( .LO ( optlc_net_1797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1975 ( .LO ( optlc_net_1798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1976 ( .LO ( optlc_net_1799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1977 ( .LO ( optlc_net_1800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1978 ( .LO ( optlc_net_1801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1979 ( .LO ( optlc_net_1802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1980 ( .LO ( optlc_net_1803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1981 ( .LO ( optlc_net_1804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1983 ( .LO ( optlc_net_1805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1984 ( .LO ( optlc_net_1806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1986 ( .LO ( optlc_net_1807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1988 ( .LO ( optlc_net_1808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1990 ( .LO ( optlc_net_1809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1992 ( .LO ( optlc_net_1810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1993 ( .LO ( optlc_net_1811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1995 ( .LO ( optlc_net_1812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1996 ( .LO ( optlc_net_1813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1998 ( .LO ( optlc_net_1814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1999 ( .LO ( optlc_net_1815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2001 ( .LO ( optlc_net_1816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2003 ( .LO ( optlc_net_1817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2005 ( .LO ( optlc_net_1818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2006 ( .LO ( optlc_net_1819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2008 ( .LO ( optlc_net_1820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2010 ( .LO ( optlc_net_1821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2011 ( .LO ( optlc_net_1822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2013 ( .LO ( optlc_net_1823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2014 ( .LO ( optlc_net_1824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2015 ( .LO ( optlc_net_1825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2016 ( .LO ( optlc_net_1826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2017 ( .LO ( optlc_net_1827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2018 ( .LO ( optlc_net_1828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2019 ( .LO ( optlc_net_1829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2020 ( .LO ( optlc_net_1830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2021 ( .LO ( optlc_net_1831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2022 ( .LO ( optlc_net_1832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2023 ( .LO ( optlc_net_1833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2024 ( .LO ( optlc_net_1834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2026 ( .LO ( optlc_net_1835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2027 ( .LO ( optlc_net_1836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2028 ( .LO ( optlc_net_1837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2029 ( .LO ( optlc_net_1838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2030 ( .LO ( optlc_net_1839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2031 ( .LO ( optlc_net_1840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2032 ( .LO ( optlc_net_1841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2034 ( .LO ( optlc_net_1842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2035 ( .LO ( optlc_net_1843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2036 ( .LO ( optlc_net_1844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2037 ( .LO ( optlc_net_1845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2038 ( .LO ( optlc_net_1846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2039 ( .LO ( optlc_net_1847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2041 ( .LO ( optlc_net_1848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2042 ( .LO ( optlc_net_1849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2043 ( .LO ( optlc_net_1850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2044 ( .LO ( optlc_net_1851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2046 ( .LO ( optlc_net_1852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2047 ( .LO ( optlc_net_1853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2049 ( .LO ( optlc_net_1854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2050 ( .LO ( optlc_net_1855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2052 ( .LO ( optlc_net_1856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2053 ( .LO ( optlc_net_1857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2054 ( .LO ( optlc_net_1858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2055 ( .LO ( optlc_net_1859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2056 ( .LO ( optlc_net_1860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2058 ( .LO ( optlc_net_1861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2060 ( .LO ( optlc_net_1862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2062 ( .LO ( optlc_net_1863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2063 ( .LO ( optlc_net_1864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2064 ( .LO ( optlc_net_1865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2065 ( .LO ( optlc_net_1866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2066 ( .LO ( optlc_net_1867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2068 ( .LO ( optlc_net_1868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2069 ( .LO ( optlc_net_1869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2071 ( .LO ( optlc_net_1870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2072 ( .LO ( optlc_net_1871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2073 ( .LO ( optlc_net_1872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2075 ( .LO ( optlc_net_1873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2076 ( .LO ( optlc_net_1874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2077 ( .LO ( optlc_net_1875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2078 ( .LO ( optlc_net_1876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2079 ( .LO ( optlc_net_1877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2081 ( .LO ( optlc_net_1878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2082 ( .LO ( optlc_net_1879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2083 ( .LO ( optlc_net_1880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2085 ( .LO ( optlc_net_1881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2086 ( .LO ( optlc_net_1882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2088 ( .LO ( optlc_net_1883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2089 ( .LO ( optlc_net_1884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2091 ( .LO ( optlc_net_1885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2093 ( .LO ( optlc_net_1886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2094 ( .LO ( optlc_net_1887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2095 ( .LO ( optlc_net_1888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2097 ( .LO ( optlc_net_1889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2099 ( .LO ( optlc_net_1890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2101 ( .LO ( optlc_net_1891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2102 ( .LO ( optlc_net_1892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2103 ( .LO ( optlc_net_1893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2104 ( .LO ( optlc_net_1894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2105 ( .LO ( optlc_net_1895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2106 ( .LO ( optlc_net_1896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2108 ( .LO ( optlc_net_1897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2110 ( .LO ( optlc_net_1898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2112 ( .LO ( optlc_net_1899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2113 ( .LO ( optlc_net_1900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2115 ( .LO ( optlc_net_1901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2116 ( .LO ( optlc_net_1902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2117 ( .LO ( optlc_net_1903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2118 ( .LO ( optlc_net_1904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2119 ( .LO ( optlc_net_1905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2120 ( .LO ( optlc_net_1906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2121 ( .LO ( optlc_net_1907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2122 ( .LO ( optlc_net_1908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2123 ( .LO ( optlc_net_1909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2124 ( .LO ( optlc_net_1910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2125 ( .LO ( optlc_net_1911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2126 ( .LO ( optlc_net_1912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2127 ( .LO ( optlc_net_1913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2128 ( .LO ( optlc_net_1914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2129 ( .LO ( optlc_net_1915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2130 ( .LO ( optlc_net_1916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2132 ( .LO ( optlc_net_1918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2134 ( .LO ( optlc_net_1920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2135 ( .LO ( optlc_net_1921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2138 ( .LO ( optlc_net_1924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2140 ( .LO ( optlc_net_1926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2141 ( .LO ( optlc_net_1927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2142 ( .LO ( optlc_net_1928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2143 ( .LO ( optlc_net_1929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2144 ( .LO ( optlc_net_1930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2146 ( .LO ( optlc_net_1932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2147 ( .LO ( optlc_net_1933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2149 ( .LO ( optlc_net_1935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2153 ( .LO ( optlc_net_1939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2154 ( .LO ( optlc_net_1940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2155 ( .LO ( optlc_net_1941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2156 ( .LO ( optlc_net_1942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2157 ( .LO ( optlc_net_1943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2158 ( .LO ( optlc_net_1944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2159 ( .LO ( optlc_net_1945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2160 ( .LO ( optlc_net_1946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2164 ( .LO ( optlc_net_1950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2166 ( .LO ( optlc_net_1952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2168 ( .LO ( optlc_net_1954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2170 ( .LO ( optlc_net_1956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2172 ( .LO ( optlc_net_1958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2174 ( .LO ( optlc_net_1960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2176 ( .LO ( optlc_net_1962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2178 ( .LO ( optlc_net_1964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2182 ( .LO ( optlc_net_1968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2183 ( .LO ( optlc_net_1969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2185 ( .LO ( optlc_net_1971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2189 ( .LO ( optlc_net_1975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2191 ( .LO ( optlc_net_1977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2193 ( .LO ( optlc_net_1979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2195 ( .LO ( optlc_net_1981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2197 ( .LO ( optlc_net_1983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2199 ( .LO ( optlc_net_1985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2201 ( .LO ( optlc_net_1987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2208 ( .LO ( optlc_net_1993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2213 ( .LO ( optlc_net_1998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2215 ( .LO ( optlc_net_2000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_2001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2217 ( .LO ( optlc_net_2002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_2003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2219 ( .LO ( optlc_net_2004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_2005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_2006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2223 ( .LO ( optlc_net_2007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_2008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_2009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_2010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2228 ( .LO ( optlc_net_2011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2229 ( .LO ( optlc_net_2012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2230 ( .LO ( optlc_net_2013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2232 ( .LO ( optlc_net_2014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_2015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2234 ( .LO ( optlc_net_2016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_2017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_2018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_2019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_2020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_2021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_2022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2241 ( .LO ( optlc_net_2023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_2024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_2025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2244 ( .LO ( optlc_net_2026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2246 ( .LO ( optlc_net_2027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_2028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_2029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2249 ( .LO ( optlc_net_2030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2250 ( .LO ( optlc_net_2031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2251 ( .LO ( optlc_net_2032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2252 ( .LO ( optlc_net_2033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2253 ( .LO ( optlc_net_2034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2254 ( .LO ( optlc_net_2035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2255 ( .LO ( optlc_net_2036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2256 ( .LO ( optlc_net_2037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2257 ( .LO ( optlc_net_2038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2258 ( .LO ( optlc_net_2039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2260 ( .LO ( optlc_net_2040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2261 ( .LO ( optlc_net_2041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2262 ( .LO ( optlc_net_2042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2263 ( .LO ( optlc_net_2043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2264 ( .LO ( optlc_net_2044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2265 ( .LO ( optlc_net_2045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2266 ( .LO ( optlc_net_2046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2267 ( .LO ( optlc_net_2047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2268 ( .LO ( optlc_net_2048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2269 ( .LO ( optlc_net_2049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2271 ( .LO ( optlc_net_2050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2272 ( .LO ( optlc_net_2051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2273 ( .LO ( optlc_net_2052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2274 ( .LO ( optlc_net_2053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2275 ( .LO ( optlc_net_2054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2277 ( .LO ( optlc_net_2055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2278 ( .LO ( optlc_net_2056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2279 ( .LO ( optlc_net_2057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2280 ( .LO ( optlc_net_2058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2281 ( .LO ( optlc_net_2059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2283 ( .LO ( optlc_net_2060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2284 ( .LO ( optlc_net_2061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2285 ( .LO ( optlc_net_2062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2286 ( .LO ( optlc_net_2063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2287 ( .LO ( optlc_net_2064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2289 ( .LO ( optlc_net_2065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2290 ( .LO ( optlc_net_2066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2291 ( .LO ( optlc_net_2067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2293 ( .LO ( optlc_net_2068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2294 ( .LO ( optlc_net_2069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2295 ( .LO ( optlc_net_2070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2296 ( .LO ( optlc_net_2071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2297 ( .LO ( optlc_net_2072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2299 ( .LO ( optlc_net_2073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2300 ( .LO ( optlc_net_2074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2301 ( .LO ( optlc_net_2075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2302 ( .LO ( optlc_net_2076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2303 ( .LO ( optlc_net_2077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2305 ( .LO ( optlc_net_2078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2306 ( .LO ( optlc_net_2079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2308 ( .LO ( optlc_net_2080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2309 ( .LO ( optlc_net_2081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2310 ( .LO ( optlc_net_2082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2311 ( .LO ( optlc_net_2083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2312 ( .LO ( optlc_net_2084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2313 ( .LO ( optlc_net_2085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2314 ( .LO ( optlc_net_2086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2315 ( .LO ( optlc_net_2087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2316 ( .LO ( optlc_net_2088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2317 ( .LO ( optlc_net_2089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2318 ( .LO ( optlc_net_2090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2319 ( .LO ( optlc_net_2091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2320 ( .LO ( optlc_net_2092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2321 ( .LO ( optlc_net_2093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2322 ( .LO ( optlc_net_2094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2323 ( .LO ( optlc_net_2095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2324 ( .LO ( optlc_net_2096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2326 ( .LO ( optlc_net_2097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2328 ( .LO ( optlc_net_2098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2329 ( .LO ( optlc_net_2099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2330 ( .LO ( optlc_net_2100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2332 ( .LO ( optlc_net_2101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2334 ( .LO ( optlc_net_2102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2335 ( .LO ( optlc_net_2103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2336 ( .LO ( optlc_net_2104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2337 ( .LO ( optlc_net_2105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2338 ( .LO ( optlc_net_2106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2340 ( .LO ( optlc_net_2107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2341 ( .LO ( optlc_net_2108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2343 ( .LO ( optlc_net_2109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2345 ( .LO ( optlc_net_2110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2346 ( .LO ( optlc_net_2111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2347 ( .LO ( optlc_net_2112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2348 ( .LO ( optlc_net_2113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2349 ( .LO ( optlc_net_2114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2351 ( .LO ( optlc_net_2115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2352 ( .LO ( optlc_net_2116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2353 ( .LO ( optlc_net_2117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2355 ( .LO ( optlc_net_2118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2357 ( .LO ( optlc_net_2119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2359 ( .LO ( optlc_net_2120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2360 ( .LO ( optlc_net_2121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2361 ( .LO ( optlc_net_2122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2362 ( .LO ( optlc_net_2123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2364 ( .LO ( optlc_net_2124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2365 ( .LO ( optlc_net_2125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2367 ( .LO ( optlc_net_2126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2368 ( .LO ( optlc_net_2127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2370 ( .LO ( optlc_net_2128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2371 ( .LO ( optlc_net_2129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2373 ( .LO ( optlc_net_2130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2374 ( .LO ( optlc_net_2131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2375 ( .LO ( optlc_net_2132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2376 ( .LO ( optlc_net_2133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2377 ( .LO ( optlc_net_2134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2378 ( .LO ( optlc_net_2135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2379 ( .LO ( optlc_net_2136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2380 ( .LO ( optlc_net_2137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2381 ( .LO ( optlc_net_2138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2382 ( .LO ( optlc_net_2139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2384 ( .LO ( optlc_net_2140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2386 ( .LO ( optlc_net_2141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2387 ( .LO ( optlc_net_2142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2388 ( .LO ( optlc_net_2143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2389 ( .LO ( optlc_net_2144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2390 ( .LO ( optlc_net_2145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2391 ( .LO ( optlc_net_2146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2393 ( .LO ( optlc_net_2147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2394 ( .LO ( optlc_net_2148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2395 ( .LO ( optlc_net_2149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2397 ( .LO ( optlc_net_2150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2398 ( .LO ( optlc_net_2151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2400 ( .LO ( optlc_net_2152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2401 ( .LO ( optlc_net_2153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2402 ( .LO ( optlc_net_2154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2403 ( .LO ( optlc_net_2155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2404 ( .LO ( optlc_net_2156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2405 ( .LO ( optlc_net_2157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2406 ( .LO ( optlc_net_2158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2407 ( .LO ( optlc_net_2159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2408 ( .LO ( optlc_net_2160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2409 ( .LO ( optlc_net_2161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2410 ( .LO ( optlc_net_2162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2411 ( .LO ( optlc_net_2163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2412 ( .LO ( optlc_net_2164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2413 ( .LO ( optlc_net_2165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2415 ( .LO ( optlc_net_2166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2416 ( .LO ( optlc_net_2167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2417 ( .LO ( optlc_net_2168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2418 ( .LO ( optlc_net_2169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2419 ( .LO ( optlc_net_2170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2420 ( .LO ( optlc_net_2171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2421 ( .LO ( optlc_net_2172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2422 ( .LO ( optlc_net_2173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2423 ( .LO ( optlc_net_2174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2424 ( .LO ( optlc_net_2175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2425 ( .LO ( optlc_net_2176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2426 ( .LO ( optlc_net_2177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2428 ( .LO ( optlc_net_2178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2430 ( .LO ( optlc_net_2179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2431 ( .LO ( optlc_net_2180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2432 ( .LO ( optlc_net_2181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2433 ( .LO ( optlc_net_2182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2434 ( .LO ( optlc_net_2183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2435 ( .LO ( optlc_net_2184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2436 ( .LO ( optlc_net_2185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2438 ( .LO ( optlc_net_2186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2439 ( .LO ( optlc_net_2187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2440 ( .LO ( optlc_net_2188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2441 ( .LO ( optlc_net_2189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2442 ( .LO ( optlc_net_2190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2443 ( .LO ( optlc_net_2191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2444 ( .LO ( optlc_net_2192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2445 ( .LO ( optlc_net_2193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2446 ( .LO ( optlc_net_2194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2447 ( .LO ( optlc_net_2195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2448 ( .LO ( optlc_net_2196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2449 ( .LO ( optlc_net_2197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2450 ( .LO ( optlc_net_2198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2451 ( .LO ( optlc_net_2199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2452 ( .LO ( optlc_net_2200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2453 ( .LO ( optlc_net_2201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2454 ( .LO ( optlc_net_2202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2455 ( .LO ( optlc_net_2203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2456 ( .LO ( optlc_net_2204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2457 ( .LO ( optlc_net_2205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2458 ( .LO ( optlc_net_2206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2459 ( .LO ( optlc_net_2207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2460 ( .LO ( optlc_net_2208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2461 ( .LO ( optlc_net_2209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2462 ( .LO ( optlc_net_2210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2463 ( .LO ( optlc_net_2211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2464 ( .LO ( optlc_net_2212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2465 ( .LO ( optlc_net_2213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2466 ( .LO ( optlc_net_2214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2467 ( .LO ( optlc_net_2215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2468 ( .LO ( optlc_net_2216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2469 ( .LO ( optlc_net_2217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2470 ( .LO ( optlc_net_2218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2471 ( .LO ( optlc_net_2219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2472 ( .LO ( optlc_net_2220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2473 ( .LO ( optlc_net_2221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2474 ( .LO ( optlc_net_2222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2475 ( .LO ( optlc_net_2223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2476 ( .LO ( optlc_net_2224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2477 ( .LO ( optlc_net_2225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2478 ( .LO ( optlc_net_2226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2479 ( .LO ( optlc_net_2227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2480 ( .LO ( optlc_net_2228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2481 ( .LO ( optlc_net_2229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2482 ( .LO ( optlc_net_2230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2483 ( .LO ( optlc_net_2231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2484 ( .LO ( optlc_net_2232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2485 ( .LO ( optlc_net_2233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2486 ( .LO ( optlc_net_2234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2487 ( .LO ( optlc_net_2235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2488 ( .LO ( optlc_net_2236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2489 ( .LO ( optlc_net_2237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2490 ( .LO ( optlc_net_2238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2491 ( .LO ( optlc_net_2239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2492 ( .LO ( optlc_net_2240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2493 ( .LO ( optlc_net_2241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2494 ( .LO ( optlc_net_2242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2495 ( .LO ( optlc_net_2243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2496 ( .LO ( optlc_net_2244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2497 ( .LO ( optlc_net_2245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2498 ( .LO ( optlc_net_2246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2499 ( .LO ( optlc_net_2247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2500 ( .LO ( optlc_net_2248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2501 ( .LO ( optlc_net_2249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2502 ( .LO ( optlc_net_2250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2503 ( .LO ( optlc_net_2251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2504 ( .LO ( optlc_net_2252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2505 ( .LO ( optlc_net_2253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2506 ( .LO ( optlc_net_2254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2507 ( .LO ( optlc_net_2255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2508 ( .LO ( optlc_net_2256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2509 ( .LO ( optlc_net_2257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2510 ( .LO ( optlc_net_2258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2511 ( .LO ( optlc_net_2259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2512 ( .LO ( optlc_net_2260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2513 ( .LO ( optlc_net_2261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2514 ( .LO ( optlc_net_2262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2515 ( .LO ( optlc_net_2263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2516 ( .LO ( optlc_net_2264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2517 ( .LO ( optlc_net_2265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2518 ( .LO ( optlc_net_2266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2519 ( .LO ( optlc_net_2267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2520 ( .LO ( optlc_net_2268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2521 ( .LO ( optlc_net_2269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2522 ( .LO ( optlc_net_2270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2523 ( .LO ( optlc_net_2271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2524 ( .LO ( optlc_net_2272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2525 ( .LO ( optlc_net_2273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2526 ( .LO ( optlc_net_2274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2527 ( .LO ( optlc_net_2275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2528 ( .LO ( optlc_net_2276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2529 ( .LO ( optlc_net_2277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2530 ( .LO ( optlc_net_2278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2531 ( .LO ( optlc_net_2279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2532 ( .LO ( optlc_net_2280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2533 ( .LO ( optlc_net_2281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2534 ( .LO ( optlc_net_2282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2536 ( .LO ( optlc_net_2283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2537 ( .LO ( optlc_net_2284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2538 ( .LO ( optlc_net_2285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2539 ( .LO ( optlc_net_2286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2541 ( .LO ( optlc_net_2287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2542 ( .LO ( optlc_net_2288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2543 ( .LO ( optlc_net_2289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2544 ( .LO ( optlc_net_2290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2545 ( .LO ( optlc_net_2291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2546 ( .LO ( optlc_net_2292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2547 ( .LO ( optlc_net_2293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2548 ( .LO ( optlc_net_2294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2549 ( .LO ( optlc_net_2295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2550 ( .LO ( optlc_net_2296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2551 ( .LO ( optlc_net_2297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2552 ( .LO ( optlc_net_2298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2554 ( .LO ( optlc_net_2299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2555 ( .LO ( optlc_net_2300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2556 ( .LO ( optlc_net_2301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2557 ( .LO ( optlc_net_2302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2558 ( .LO ( optlc_net_2303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2559 ( .LO ( optlc_net_2304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2560 ( .LO ( optlc_net_2305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2561 ( .LO ( optlc_net_2306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2562 ( .LO ( optlc_net_2307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2563 ( .LO ( optlc_net_2308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2564 ( .LO ( optlc_net_2309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2565 ( .LO ( optlc_net_2310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2566 ( .LO ( optlc_net_2311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2567 ( .LO ( optlc_net_2312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2569 ( .LO ( optlc_net_2313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2570 ( .LO ( optlc_net_2314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2571 ( .LO ( optlc_net_2315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2572 ( .LO ( optlc_net_2316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2573 ( .LO ( optlc_net_2317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2574 ( .LO ( optlc_net_2318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2575 ( .LO ( optlc_net_2319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2576 ( .LO ( optlc_net_2320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2577 ( .LO ( optlc_net_2321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2578 ( .LO ( optlc_net_2322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2580 ( .LO ( optlc_net_2323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2581 ( .LO ( optlc_net_2324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2582 ( .LO ( optlc_net_2325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2583 ( .LO ( optlc_net_2326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2584 ( .LO ( optlc_net_2327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2586 ( .LO ( optlc_net_2328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2587 ( .LO ( optlc_net_2329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2588 ( .LO ( optlc_net_2330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2589 ( .LO ( optlc_net_2331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2590 ( .LO ( optlc_net_2332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2591 ( .LO ( optlc_net_2333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2592 ( .LO ( optlc_net_2334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2593 ( .LO ( optlc_net_2335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2595 ( .LO ( optlc_net_2336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2596 ( .LO ( optlc_net_2337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2597 ( .LO ( optlc_net_2338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2598 ( .LO ( optlc_net_2339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2600 ( .LO ( optlc_net_2340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2601 ( .LO ( optlc_net_2341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2602 ( .LO ( optlc_net_2342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2603 ( .LO ( optlc_net_2343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2604 ( .LO ( optlc_net_2344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2605 ( .LO ( optlc_net_2345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2607 ( .LO ( optlc_net_2346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2608 ( .LO ( optlc_net_2347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2610 ( .LO ( optlc_net_2348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2611 ( .LO ( optlc_net_2349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2612 ( .LO ( optlc_net_2350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2613 ( .LO ( optlc_net_2351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2614 ( .LO ( optlc_net_2352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2615 ( .LO ( optlc_net_2353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2616 ( .LO ( optlc_net_2354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2617 ( .LO ( optlc_net_2355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2619 ( .LO ( optlc_net_2356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2620 ( .LO ( optlc_net_2357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2621 ( .LO ( optlc_net_2358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2622 ( .LO ( optlc_net_2359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2623 ( .LO ( optlc_net_2360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2624 ( .LO ( optlc_net_2361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2625 ( .LO ( optlc_net_2362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2626 ( .LO ( optlc_net_2363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2627 ( .LO ( optlc_net_2364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2629 ( .LO ( optlc_net_2365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2630 ( .LO ( optlc_net_2366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2631 ( .LO ( optlc_net_2367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2632 ( .LO ( optlc_net_2368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2633 ( .LO ( optlc_net_2369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2634 ( .LO ( optlc_net_2370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2636 ( .LO ( optlc_net_2371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2637 ( .LO ( optlc_net_2372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2639 ( .LO ( optlc_net_2373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2640 ( .LO ( optlc_net_2374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2642 ( .LO ( optlc_net_2375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2644 ( .LO ( optlc_net_2376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2645 ( .LO ( optlc_net_2377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2646 ( .LO ( optlc_net_2378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2647 ( .LO ( optlc_net_2379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2648 ( .LO ( optlc_net_2380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2649 ( .LO ( optlc_net_2381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2650 ( .LO ( optlc_net_2382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2651 ( .LO ( optlc_net_2383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2652 ( .LO ( optlc_net_2384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2653 ( .LO ( optlc_net_2385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2654 ( .LO ( optlc_net_2386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2655 ( .LO ( optlc_net_2387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2656 ( .LO ( optlc_net_2388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2657 ( .LO ( optlc_net_2389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2658 ( .LO ( optlc_net_2390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2660 ( .LO ( optlc_net_2391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2661 ( .LO ( optlc_net_2392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2663 ( .LO ( optlc_net_2393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2665 ( .LO ( optlc_net_2394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2666 ( .LO ( optlc_net_2395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2667 ( .LO ( optlc_net_2396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2668 ( .LO ( optlc_net_2397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2669 ( .LO ( optlc_net_2398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2671 ( .LO ( optlc_net_2399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2672 ( .LO ( optlc_net_2400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2673 ( .LO ( optlc_net_2401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2674 ( .LO ( optlc_net_2402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2675 ( .LO ( optlc_net_2403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2676 ( .LO ( optlc_net_2404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2678 ( .LO ( optlc_net_2405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2679 ( .LO ( optlc_net_2406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2680 ( .LO ( optlc_net_2407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2682 ( .LO ( optlc_net_2408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2683 ( .LO ( optlc_net_2409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2684 ( .LO ( optlc_net_2410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2685 ( .LO ( optlc_net_2411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2686 ( .LO ( optlc_net_2412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2687 ( .LO ( optlc_net_2413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2688 ( .LO ( optlc_net_2414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2689 ( .LO ( optlc_net_2415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2690 ( .LO ( optlc_net_2416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2691 ( .LO ( optlc_net_2417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2692 ( .LO ( optlc_net_2418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2693 ( .LO ( optlc_net_2419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2694 ( .LO ( optlc_net_2420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2695 ( .LO ( optlc_net_2421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2696 ( .LO ( optlc_net_2422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2698 ( .LO ( optlc_net_2423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2700 ( .LO ( optlc_net_2424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2701 ( .LO ( optlc_net_2425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2702 ( .LO ( optlc_net_2426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2703 ( .LO ( optlc_net_2427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2704 ( .LO ( optlc_net_2428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2705 ( .LO ( optlc_net_2429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2706 ( .LO ( optlc_net_2430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2707 ( .LO ( optlc_net_2431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2708 ( .LO ( optlc_net_2432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2709 ( .LO ( optlc_net_2433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2710 ( .LO ( optlc_net_2434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2711 ( .LO ( optlc_net_2435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2713 ( .LO ( optlc_net_2436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2714 ( .LO ( optlc_net_2437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2716 ( .LO ( optlc_net_2438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2718 ( .LO ( optlc_net_2439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2719 ( .LO ( optlc_net_2440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2720 ( .LO ( optlc_net_2441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2721 ( .LO ( optlc_net_2442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2722 ( .LO ( optlc_net_2443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2723 ( .LO ( optlc_net_2444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2724 ( .LO ( optlc_net_2445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2725 ( .LO ( optlc_net_2446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2726 ( .LO ( optlc_net_2447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2727 ( .LO ( optlc_net_2448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2728 ( .LO ( optlc_net_2449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2729 ( .LO ( optlc_net_2450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2730 ( .LO ( optlc_net_2451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2731 ( .LO ( optlc_net_2452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2732 ( .LO ( optlc_net_2453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2733 ( .LO ( optlc_net_2454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2734 ( .LO ( optlc_net_2455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2735 ( .LO ( optlc_net_2456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2736 ( .LO ( optlc_net_2457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2737 ( .LO ( optlc_net_2458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2738 ( .LO ( optlc_net_2459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2739 ( .LO ( optlc_net_2460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2740 ( .LO ( optlc_net_2461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2741 ( .LO ( optlc_net_2462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2742 ( .LO ( optlc_net_2463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2743 ( .LO ( optlc_net_2464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2744 ( .LO ( optlc_net_2465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2745 ( .LO ( optlc_net_2466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2746 ( .LO ( optlc_net_2467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2747 ( .LO ( optlc_net_2468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2748 ( .LO ( optlc_net_2469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2749 ( .LO ( optlc_net_2470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2750 ( .LO ( optlc_net_2471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2751 ( .LO ( optlc_net_2472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2752 ( .LO ( optlc_net_2473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2753 ( .LO ( optlc_net_2474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2754 ( .LO ( optlc_net_2475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2755 ( .LO ( optlc_net_2476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2756 ( .LO ( optlc_net_2477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2757 ( .LO ( optlc_net_2478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2758 ( .LO ( optlc_net_2479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2759 ( .LO ( optlc_net_2480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2760 ( .LO ( optlc_net_2481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2761 ( .LO ( optlc_net_2482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2762 ( .LO ( optlc_net_2483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2763 ( .LO ( optlc_net_2484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2764 ( .LO ( optlc_net_2485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2765 ( .LO ( optlc_net_2486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2766 ( .LO ( optlc_net_2487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2767 ( .LO ( optlc_net_2488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2768 ( .LO ( optlc_net_2489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2769 ( .LO ( optlc_net_2490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2770 ( .LO ( optlc_net_2491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2771 ( .LO ( optlc_net_2492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2772 ( .LO ( optlc_net_2493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2773 ( .LO ( optlc_net_2494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2774 ( .LO ( optlc_net_2495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2775 ( .LO ( optlc_net_2496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2776 ( .LO ( optlc_net_2497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2777 ( .LO ( optlc_net_2498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2778 ( .LO ( optlc_net_2499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2779 ( .LO ( optlc_net_2500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2780 ( .LO ( optlc_net_2501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2781 ( .LO ( optlc_net_2502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2782 ( .LO ( optlc_net_2503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2783 ( .LO ( optlc_net_2504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2784 ( .LO ( optlc_net_2505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2785 ( .LO ( optlc_net_2506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2786 ( .LO ( optlc_net_2507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2787 ( .LO ( optlc_net_2508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2788 ( .LO ( optlc_net_2509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2789 ( .LO ( optlc_net_2510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2790 ( .LO ( optlc_net_2511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2791 ( .LO ( optlc_net_2512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2792 ( .LO ( optlc_net_2513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2793 ( .LO ( optlc_net_2514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2794 ( .LO ( optlc_net_2515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2795 ( .LO ( optlc_net_2516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2796 ( .LO ( optlc_net_2517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2797 ( .LO ( optlc_net_2518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2798 ( .LO ( optlc_net_2519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2799 ( .LO ( optlc_net_2520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2800 ( .LO ( optlc_net_2521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2801 ( .LO ( optlc_net_2522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2802 ( .LO ( optlc_net_2523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2803 ( .LO ( optlc_net_2524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2804 ( .LO ( optlc_net_2525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2805 ( .LO ( optlc_net_2526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2806 ( .LO ( optlc_net_2527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2808 ( .LO ( optlc_net_2528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2809 ( .LO ( optlc_net_2529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2811 ( .LO ( optlc_net_2530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2812 ( .LO ( optlc_net_2531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2813 ( .LO ( optlc_net_2532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2814 ( .LO ( optlc_net_2533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2815 ( .LO ( optlc_net_2534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2816 ( .LO ( optlc_net_2535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2817 ( .LO ( optlc_net_2536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2818 ( .LO ( optlc_net_2537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2820 ( .LO ( optlc_net_2538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2821 ( .LO ( optlc_net_2539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2822 ( .LO ( optlc_net_2540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2823 ( .LO ( optlc_net_2541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2824 ( .LO ( optlc_net_2542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2825 ( .LO ( optlc_net_2543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2826 ( .LO ( optlc_net_2544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2827 ( .LO ( optlc_net_2545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2828 ( .LO ( optlc_net_2546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2829 ( .LO ( optlc_net_2547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2830 ( .LO ( optlc_net_2548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2831 ( .LO ( optlc_net_2549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2832 ( .LO ( optlc_net_2550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2833 ( .LO ( optlc_net_2551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2835 ( .LO ( optlc_net_2552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2836 ( .LO ( optlc_net_2553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2837 ( .LO ( optlc_net_2554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2838 ( .LO ( optlc_net_2555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2839 ( .LO ( optlc_net_2556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2840 ( .LO ( optlc_net_2557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2841 ( .LO ( optlc_net_2558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2843 ( .LO ( optlc_net_2559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2844 ( .LO ( optlc_net_2560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2845 ( .LO ( optlc_net_2561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2846 ( .LO ( optlc_net_2562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2847 ( .LO ( optlc_net_2563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2848 ( .LO ( optlc_net_2564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2849 ( .LO ( optlc_net_2565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2850 ( .LO ( optlc_net_2566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2851 ( .LO ( optlc_net_2567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2852 ( .LO ( optlc_net_2568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2853 ( .LO ( optlc_net_2569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2855 ( .LO ( optlc_net_2570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2856 ( .LO ( optlc_net_2571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2857 ( .LO ( optlc_net_2572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2859 ( .LO ( optlc_net_2573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2861 ( .LO ( optlc_net_2574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2862 ( .LO ( optlc_net_2575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2864 ( .LO ( optlc_net_2576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2865 ( .LO ( optlc_net_2577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2866 ( .LO ( optlc_net_2578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2867 ( .LO ( optlc_net_2579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2868 ( .LO ( optlc_net_2580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2869 ( .LO ( optlc_net_2581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2870 ( .LO ( optlc_net_2582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2871 ( .LO ( optlc_net_2583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2872 ( .LO ( optlc_net_2584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2873 ( .LO ( optlc_net_2585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2874 ( .LO ( optlc_net_2586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2875 ( .LO ( optlc_net_2587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2876 ( .LO ( optlc_net_2588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2877 ( .LO ( optlc_net_2589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2878 ( .LO ( optlc_net_2590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2879 ( .LO ( optlc_net_2591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2880 ( .LO ( optlc_net_2592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2882 ( .LO ( optlc_net_2593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2884 ( .LO ( optlc_net_2594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2885 ( .LO ( optlc_net_2595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2886 ( .LO ( optlc_net_2596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2887 ( .LO ( optlc_net_2597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2888 ( .LO ( optlc_net_2598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2889 ( .LO ( optlc_net_2599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2890 ( .LO ( optlc_net_2600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2891 ( .LO ( optlc_net_2601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2892 ( .LO ( optlc_net_2602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2893 ( .LO ( optlc_net_2603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2894 ( .LO ( optlc_net_2604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2895 ( .LO ( optlc_net_2605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2896 ( .LO ( optlc_net_2606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2897 ( .LO ( optlc_net_2607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2898 ( .LO ( optlc_net_2608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2899 ( .LO ( optlc_net_2609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2900 ( .LO ( optlc_net_2610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2901 ( .LO ( optlc_net_2611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2902 ( .LO ( optlc_net_2612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2903 ( .LO ( optlc_net_2613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2904 ( .LO ( optlc_net_2614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2906 ( .LO ( optlc_net_2615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2907 ( .LO ( optlc_net_2616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2908 ( .LO ( optlc_net_2617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2909 ( .LO ( optlc_net_2618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2910 ( .LO ( optlc_net_2619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2911 ( .LO ( optlc_net_2620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2913 ( .LO ( optlc_net_2621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2915 ( .LO ( optlc_net_2622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2917 ( .LO ( optlc_net_2623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2918 ( .LO ( optlc_net_2624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2919 ( .LO ( optlc_net_2625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2920 ( .LO ( optlc_net_2626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2921 ( .LO ( optlc_net_2627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2922 ( .LO ( optlc_net_2628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2923 ( .LO ( optlc_net_2629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2924 ( .LO ( optlc_net_2630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2926 ( .LO ( optlc_net_2631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2927 ( .LO ( optlc_net_2632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2928 ( .LO ( optlc_net_2633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2929 ( .LO ( optlc_net_2634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2930 ( .LO ( optlc_net_2635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2931 ( .LO ( optlc_net_2636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2932 ( .LO ( optlc_net_2637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2933 ( .LO ( optlc_net_2638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2934 ( .LO ( optlc_net_2639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2935 ( .LO ( optlc_net_2640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2936 ( .LO ( optlc_net_2641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2937 ( .LO ( optlc_net_2642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2938 ( .LO ( optlc_net_2643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2939 ( .LO ( optlc_net_2644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2940 ( .LO ( optlc_net_2645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2941 ( .LO ( optlc_net_2646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2942 ( .LO ( optlc_net_2647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2943 ( .LO ( optlc_net_2648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2944 ( .LO ( optlc_net_2649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2945 ( .LO ( optlc_net_2650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2946 ( .LO ( optlc_net_2651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2947 ( .LO ( optlc_net_2652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2948 ( .LO ( optlc_net_2653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2949 ( .LO ( optlc_net_2654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2950 ( .LO ( optlc_net_2655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2951 ( .LO ( optlc_net_2656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2952 ( .LO ( optlc_net_2657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2953 ( .LO ( optlc_net_2658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2954 ( .LO ( optlc_net_2659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2955 ( .LO ( optlc_net_2660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2956 ( .LO ( optlc_net_2661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2957 ( .LO ( optlc_net_2662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2958 ( .LO ( optlc_net_2663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2959 ( .LO ( optlc_net_2664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2960 ( .LO ( optlc_net_2665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2961 ( .LO ( optlc_net_2666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2962 ( .LO ( optlc_net_2667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2963 ( .LO ( optlc_net_2668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2964 ( .LO ( optlc_net_2669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2965 ( .LO ( optlc_net_2670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2966 ( .LO ( optlc_net_2671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2967 ( .LO ( optlc_net_2672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2968 ( .LO ( optlc_net_2673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2969 ( .LO ( optlc_net_2674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2970 ( .LO ( optlc_net_2675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2971 ( .LO ( optlc_net_2676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2972 ( .LO ( optlc_net_2677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2973 ( .LO ( optlc_net_2678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2974 ( .LO ( optlc_net_2679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2975 ( .LO ( optlc_net_2680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2976 ( .LO ( optlc_net_2681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2977 ( .LO ( optlc_net_2682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2978 ( .LO ( optlc_net_2683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2979 ( .LO ( optlc_net_2684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2980 ( .LO ( optlc_net_2685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2981 ( .LO ( optlc_net_2686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2982 ( .LO ( optlc_net_2687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2983 ( .LO ( optlc_net_2688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2984 ( .LO ( optlc_net_2689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2985 ( .LO ( optlc_net_2690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2986 ( .LO ( optlc_net_2691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2987 ( .LO ( optlc_net_2692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2988 ( .LO ( optlc_net_2693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2989 ( .LO ( optlc_net_2694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2990 ( .LO ( optlc_net_2695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2991 ( .LO ( optlc_net_2696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2992 ( .LO ( optlc_net_2697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2993 ( .LO ( optlc_net_2698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2994 ( .LO ( optlc_net_2699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2995 ( .LO ( optlc_net_2700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2996 ( .LO ( optlc_net_2701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2997 ( .LO ( optlc_net_2702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2998 ( .LO ( optlc_net_2703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2999 ( .LO ( optlc_net_2704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3000 ( .LO ( optlc_net_2705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3001 ( .LO ( optlc_net_2706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3002 ( .LO ( optlc_net_2707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3003 ( .LO ( optlc_net_2708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3004 ( .LO ( optlc_net_2709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3005 ( .LO ( optlc_net_2710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3006 ( .LO ( optlc_net_2711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3007 ( .LO ( optlc_net_2712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3008 ( .LO ( optlc_net_2713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3010 ( .LO ( optlc_net_2714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3011 ( .LO ( optlc_net_2715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3012 ( .LO ( optlc_net_2716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3013 ( .LO ( optlc_net_2717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3014 ( .LO ( optlc_net_2718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3015 ( .LO ( optlc_net_2719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3016 ( .LO ( optlc_net_2720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3017 ( .LO ( optlc_net_2721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3018 ( .LO ( optlc_net_2722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3020 ( .LO ( optlc_net_2723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3021 ( .LO ( optlc_net_2724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3022 ( .LO ( optlc_net_2725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3023 ( .LO ( optlc_net_2726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3024 ( .LO ( optlc_net_2727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3025 ( .LO ( optlc_net_2728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3026 ( .LO ( optlc_net_2729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3028 ( .LO ( optlc_net_2730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3029 ( .LO ( optlc_net_2731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3030 ( .LO ( optlc_net_2732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3031 ( .LO ( optlc_net_2733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3032 ( .LO ( optlc_net_2734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3033 ( .LO ( optlc_net_2735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3034 ( .LO ( optlc_net_2736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3035 ( .LO ( optlc_net_2737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3036 ( .LO ( optlc_net_2738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3037 ( .LO ( optlc_net_2739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3038 ( .LO ( optlc_net_2740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3039 ( .LO ( optlc_net_2741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3040 ( .LO ( optlc_net_2742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3041 ( .LO ( optlc_net_2743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3042 ( .LO ( optlc_net_2744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3043 ( .LO ( optlc_net_2745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3044 ( .LO ( optlc_net_2746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3045 ( .LO ( optlc_net_2747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3046 ( .LO ( optlc_net_2748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3047 ( .LO ( optlc_net_2749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3048 ( .LO ( optlc_net_2750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3049 ( .LO ( optlc_net_2751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3050 ( .LO ( optlc_net_2752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3051 ( .LO ( optlc_net_2753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3052 ( .LO ( optlc_net_2754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3053 ( .LO ( optlc_net_2755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3054 ( .LO ( optlc_net_2756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3055 ( .LO ( optlc_net_2757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3056 ( .LO ( optlc_net_2758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3057 ( .LO ( optlc_net_2759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3058 ( .LO ( optlc_net_2760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3059 ( .LO ( optlc_net_2761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3060 ( .LO ( optlc_net_2762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3061 ( .LO ( optlc_net_2763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3062 ( .LO ( optlc_net_2764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3063 ( .LO ( optlc_net_2765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3064 ( .LO ( optlc_net_2766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3065 ( .LO ( optlc_net_2767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3066 ( .LO ( optlc_net_2768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3067 ( .LO ( optlc_net_2769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3068 ( .LO ( optlc_net_2770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3069 ( .LO ( optlc_net_2771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3070 ( .LO ( optlc_net_2772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3071 ( .LO ( optlc_net_2773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3072 ( .LO ( optlc_net_2774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3073 ( .LO ( optlc_net_2775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3074 ( .LO ( optlc_net_2776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3075 ( .LO ( optlc_net_2777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3076 ( .LO ( optlc_net_2778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3077 ( .LO ( optlc_net_2779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3078 ( .LO ( optlc_net_2780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3079 ( .LO ( optlc_net_2781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3080 ( .LO ( optlc_net_2782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3081 ( .LO ( optlc_net_2783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3082 ( .LO ( optlc_net_2784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3083 ( .LO ( optlc_net_2785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3084 ( .LO ( optlc_net_2786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3086 ( .LO ( optlc_net_2787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3087 ( .LO ( optlc_net_2788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3088 ( .LO ( optlc_net_2789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3089 ( .LO ( optlc_net_2790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3090 ( .LO ( optlc_net_2791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3091 ( .LO ( optlc_net_2792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3092 ( .LO ( optlc_net_2793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3093 ( .LO ( optlc_net_2794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3094 ( .LO ( optlc_net_2795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3095 ( .LO ( optlc_net_2796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3096 ( .LO ( optlc_net_2797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3097 ( .LO ( optlc_net_2798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3098 ( .LO ( optlc_net_2799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3099 ( .LO ( optlc_net_2800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3100 ( .LO ( optlc_net_2801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3101 ( .LO ( optlc_net_2802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3103 ( .LO ( optlc_net_2803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3104 ( .LO ( optlc_net_2804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3105 ( .LO ( optlc_net_2805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3106 ( .LO ( optlc_net_2806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3107 ( .LO ( optlc_net_2807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3108 ( .LO ( optlc_net_2808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3109 ( .LO ( optlc_net_2809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3110 ( .LO ( optlc_net_2810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3111 ( .LO ( optlc_net_2811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3112 ( .LO ( optlc_net_2812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3113 ( .LO ( optlc_net_2813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3114 ( .LO ( optlc_net_2814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3115 ( .LO ( optlc_net_2815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3116 ( .LO ( optlc_net_2816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3117 ( .LO ( optlc_net_2817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3118 ( .LO ( optlc_net_2818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3119 ( .LO ( optlc_net_2819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3120 ( .LO ( optlc_net_2820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3121 ( .LO ( optlc_net_2821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3122 ( .LO ( optlc_net_2822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3123 ( .LO ( optlc_net_2823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3124 ( .LO ( optlc_net_2824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3125 ( .LO ( optlc_net_2825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3126 ( .LO ( optlc_net_2826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3127 ( .LO ( optlc_net_2827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3128 ( .LO ( optlc_net_2828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3129 ( .LO ( optlc_net_2829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3130 ( .LO ( optlc_net_2830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3131 ( .LO ( optlc_net_2831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3132 ( .LO ( optlc_net_2832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3133 ( .LO ( optlc_net_2833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3134 ( .LO ( optlc_net_2834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3135 ( .LO ( optlc_net_2835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3136 ( .LO ( optlc_net_2836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3137 ( .LO ( optlc_net_2837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3138 ( .LO ( optlc_net_2838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3139 ( .LO ( optlc_net_2839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3140 ( .LO ( optlc_net_2840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3141 ( .LO ( optlc_net_2841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3142 ( .LO ( optlc_net_2842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3143 ( .LO ( optlc_net_2843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3144 ( .LO ( optlc_net_2844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3145 ( .LO ( optlc_net_2845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3146 ( .LO ( optlc_net_2846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3147 ( .LO ( optlc_net_2847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3148 ( .LO ( optlc_net_2848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3149 ( .LO ( optlc_net_2849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3150 ( .LO ( optlc_net_2850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3151 ( .LO ( optlc_net_2851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3152 ( .LO ( optlc_net_2852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3153 ( .LO ( optlc_net_2853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3154 ( .LO ( optlc_net_2854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3155 ( .LO ( optlc_net_2855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3156 ( .LO ( optlc_net_2856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3157 ( .LO ( optlc_net_2857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3158 ( .LO ( optlc_net_2858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3159 ( .LO ( optlc_net_2859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3160 ( .LO ( optlc_net_2860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3161 ( .LO ( optlc_net_2861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3162 ( .LO ( optlc_net_2862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3163 ( .LO ( optlc_net_2863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3164 ( .LO ( optlc_net_2864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3165 ( .LO ( optlc_net_2865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3166 ( .LO ( optlc_net_2866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3167 ( .LO ( optlc_net_2867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3168 ( .LO ( optlc_net_2868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3169 ( .LO ( optlc_net_2869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3170 ( .LO ( optlc_net_2870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3171 ( .LO ( optlc_net_2871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3172 ( .LO ( optlc_net_2872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3173 ( .LO ( optlc_net_2873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3174 ( .LO ( optlc_net_2874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3175 ( .LO ( optlc_net_2875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3176 ( .LO ( optlc_net_2876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3177 ( .LO ( optlc_net_2877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3178 ( .LO ( optlc_net_2878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3179 ( .LO ( optlc_net_2879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3180 ( .LO ( optlc_net_2880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3181 ( .LO ( optlc_net_2881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3182 ( .LO ( optlc_net_2882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3183 ( .LO ( optlc_net_2883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3184 ( .LO ( optlc_net_2884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3185 ( .LO ( optlc_net_2885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3186 ( .LO ( optlc_net_2886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3187 ( .LO ( optlc_net_2887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3188 ( .LO ( optlc_net_2888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3189 ( .LO ( optlc_net_2889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3190 ( .LO ( optlc_net_2890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3191 ( .LO ( optlc_net_2891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3192 ( .LO ( optlc_net_2892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3193 ( .LO ( optlc_net_2893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3194 ( .LO ( optlc_net_2894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3195 ( .LO ( optlc_net_2895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3196 ( .LO ( optlc_net_2896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3197 ( .LO ( optlc_net_2897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3198 ( .LO ( optlc_net_2898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3199 ( .LO ( optlc_net_2899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3200 ( .LO ( optlc_net_2900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3201 ( .LO ( optlc_net_2901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3202 ( .LO ( optlc_net_2902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3203 ( .LO ( optlc_net_2903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3204 ( .LO ( optlc_net_2904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3205 ( .LO ( optlc_net_2905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3206 ( .LO ( optlc_net_2906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3207 ( .LO ( optlc_net_2907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3208 ( .LO ( optlc_net_2908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3209 ( .LO ( optlc_net_2909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3210 ( .LO ( optlc_net_2910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3211 ( .LO ( optlc_net_2911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3212 ( .LO ( optlc_net_2912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3213 ( .LO ( optlc_net_2913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3214 ( .LO ( optlc_net_2914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3215 ( .LO ( optlc_net_2915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3216 ( .LO ( optlc_net_2916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3217 ( .LO ( optlc_net_2917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3218 ( .LO ( optlc_net_2918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3219 ( .LO ( optlc_net_2919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3220 ( .LO ( optlc_net_2920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3221 ( .LO ( optlc_net_2921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3222 ( .LO ( optlc_net_2922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3223 ( .LO ( optlc_net_2923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3224 ( .LO ( optlc_net_2924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3225 ( .LO ( optlc_net_2925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3226 ( .LO ( optlc_net_2926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3227 ( .LO ( optlc_net_2927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3228 ( .LO ( optlc_net_2928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3229 ( .LO ( optlc_net_2929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3230 ( .LO ( optlc_net_2930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3231 ( .LO ( optlc_net_2931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3232 ( .LO ( optlc_net_2932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3233 ( .LO ( optlc_net_2933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3234 ( .LO ( optlc_net_2934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3235 ( .LO ( optlc_net_2935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3236 ( .LO ( optlc_net_2936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3237 ( .LO ( optlc_net_2937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3238 ( .LO ( optlc_net_2938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3239 ( .LO ( optlc_net_2939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3240 ( .LO ( optlc_net_2940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3241 ( .LO ( optlc_net_2941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3242 ( .LO ( optlc_net_2942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3243 ( .LO ( optlc_net_2943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3244 ( .LO ( optlc_net_2944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3245 ( .LO ( optlc_net_2945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3246 ( .LO ( optlc_net_2946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3247 ( .LO ( optlc_net_2947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3248 ( .LO ( optlc_net_2948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3249 ( .LO ( optlc_net_2949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3250 ( .LO ( optlc_net_2950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3251 ( .LO ( optlc_net_2951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3252 ( .LO ( optlc_net_2952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3253 ( .LO ( optlc_net_2953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3254 ( .LO ( optlc_net_2954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3255 ( .LO ( optlc_net_2955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3256 ( .LO ( optlc_net_2956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3257 ( .LO ( optlc_net_2957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3258 ( .LO ( optlc_net_2958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3259 ( .LO ( optlc_net_2959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3260 ( .LO ( optlc_net_2960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3261 ( .LO ( optlc_net_2961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3262 ( .LO ( optlc_net_2962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3263 ( .LO ( optlc_net_2963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3264 ( .LO ( optlc_net_2964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3265 ( .LO ( optlc_net_2965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3266 ( .LO ( optlc_net_2966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3267 ( .LO ( optlc_net_2967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3268 ( .LO ( optlc_net_2968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3269 ( .LO ( optlc_net_2969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3270 ( .LO ( optlc_net_2970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3271 ( .LO ( optlc_net_2971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3272 ( .LO ( optlc_net_2972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3273 ( .LO ( optlc_net_2973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3274 ( .LO ( optlc_net_2974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3275 ( .LO ( optlc_net_2975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3276 ( .LO ( optlc_net_2976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3277 ( .LO ( optlc_net_2977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3278 ( .LO ( optlc_net_2978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3279 ( .LO ( optlc_net_2979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3280 ( .LO ( optlc_net_2980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3281 ( .LO ( optlc_net_2981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3282 ( .LO ( optlc_net_2982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3283 ( .LO ( optlc_net_2983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3284 ( .LO ( optlc_net_2984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3285 ( .LO ( optlc_net_2985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3286 ( .LO ( optlc_net_2986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3287 ( .LO ( optlc_net_2987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3288 ( .LO ( optlc_net_2988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3289 ( .LO ( optlc_net_2989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3290 ( .LO ( optlc_net_2990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3291 ( .LO ( optlc_net_2991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3292 ( .LO ( optlc_net_2992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3293 ( .LO ( optlc_net_2993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3294 ( .LO ( optlc_net_2994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3295 ( .LO ( optlc_net_2995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3296 ( .LO ( optlc_net_2996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3297 ( .LO ( optlc_net_2997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3298 ( .LO ( optlc_net_2998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3299 ( .LO ( optlc_net_2999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3300 ( .LO ( optlc_net_3000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3301 ( .LO ( optlc_net_3001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3302 ( .LO ( optlc_net_3002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3303 ( .LO ( optlc_net_3003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3304 ( .LO ( optlc_net_3004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3305 ( .LO ( optlc_net_3005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3306 ( .LO ( optlc_net_3006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3307 ( .LO ( optlc_net_3007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3308 ( .LO ( optlc_net_3008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3309 ( .LO ( optlc_net_3009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3310 ( .LO ( optlc_net_3010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3311 ( .LO ( optlc_net_3011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3312 ( .LO ( optlc_net_3012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3313 ( .LO ( optlc_net_3013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3314 ( .LO ( optlc_net_3014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3315 ( .LO ( optlc_net_3015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3316 ( .LO ( optlc_net_3016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3317 ( .LO ( optlc_net_3017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3318 ( .LO ( optlc_net_3018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3319 ( .LO ( optlc_net_3019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3320 ( .LO ( optlc_net_3020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3321 ( .LO ( optlc_net_3021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3322 ( .LO ( optlc_net_3022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3323 ( .LO ( optlc_net_3023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3324 ( .LO ( optlc_net_3024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3325 ( .LO ( optlc_net_3025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3327 ( .LO ( optlc_net_3026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3328 ( .LO ( optlc_net_3027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3329 ( .LO ( optlc_net_3028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3330 ( .LO ( optlc_net_3029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3331 ( .LO ( optlc_net_3030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3332 ( .LO ( optlc_net_3031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3333 ( .LO ( optlc_net_3032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3334 ( .LO ( optlc_net_3033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3335 ( .LO ( optlc_net_3034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3336 ( .LO ( optlc_net_3035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3337 ( .LO ( optlc_net_3036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3338 ( .LO ( optlc_net_3037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3339 ( .LO ( optlc_net_3038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3340 ( .LO ( optlc_net_3039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3341 ( .LO ( optlc_net_3040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3342 ( .LO ( optlc_net_3041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3343 ( .LO ( optlc_net_3042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3344 ( .LO ( optlc_net_3043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3345 ( .LO ( optlc_net_3044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3346 ( .LO ( optlc_net_3045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3347 ( .LO ( optlc_net_3046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3348 ( .LO ( optlc_net_3047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3349 ( .LO ( optlc_net_3048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3350 ( .LO ( optlc_net_3049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3351 ( .LO ( optlc_net_3050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3352 ( .LO ( optlc_net_3051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3353 ( .LO ( optlc_net_3052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3354 ( .LO ( optlc_net_3053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3355 ( .LO ( optlc_net_3054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3356 ( .LO ( optlc_net_3055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3357 ( .LO ( optlc_net_3056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3358 ( .LO ( optlc_net_3057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3359 ( .LO ( optlc_net_3058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3360 ( .LO ( optlc_net_3059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3361 ( .LO ( optlc_net_3060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3362 ( .LO ( optlc_net_3061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3363 ( .LO ( optlc_net_3062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3364 ( .LO ( optlc_net_3063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3365 ( .LO ( optlc_net_3064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3366 ( .LO ( optlc_net_3065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3367 ( .LO ( optlc_net_3066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3368 ( .LO ( optlc_net_3067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3369 ( .LO ( optlc_net_3068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3370 ( .LO ( optlc_net_3069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3371 ( .LO ( optlc_net_3070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3372 ( .LO ( optlc_net_3071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3373 ( .LO ( optlc_net_3072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3374 ( .LO ( optlc_net_3073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3375 ( .LO ( optlc_net_3074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3376 ( .LO ( optlc_net_3075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3377 ( .LO ( optlc_net_3076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3378 ( .LO ( optlc_net_3077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3379 ( .LO ( optlc_net_3078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3380 ( .LO ( optlc_net_3079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3381 ( .LO ( optlc_net_3080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3382 ( .LO ( optlc_net_3081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3383 ( .LO ( optlc_net_3082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3384 ( .LO ( optlc_net_3083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3385 ( .LO ( optlc_net_3084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3386 ( .LO ( optlc_net_3085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3387 ( .LO ( optlc_net_3086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3388 ( .LO ( optlc_net_3087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3389 ( .LO ( optlc_net_3088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3390 ( .LO ( optlc_net_3089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3391 ( .LO ( optlc_net_3090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3392 ( .LO ( optlc_net_3091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3393 ( .LO ( optlc_net_3092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3394 ( .LO ( optlc_net_3093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3395 ( .LO ( optlc_net_3094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3396 ( .LO ( optlc_net_3095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3397 ( .LO ( optlc_net_3096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3398 ( .LO ( optlc_net_3097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3399 ( .LO ( optlc_net_3098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3400 ( .LO ( optlc_net_3099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3401 ( .LO ( optlc_net_3100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3402 ( .LO ( optlc_net_3101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3403 ( .LO ( optlc_net_3102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3404 ( .LO ( optlc_net_3103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3405 ( .LO ( optlc_net_3104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3406 ( .LO ( optlc_net_3105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3407 ( .LO ( optlc_net_3106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3408 ( .LO ( optlc_net_3107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3409 ( .LO ( optlc_net_3108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3410 ( .LO ( optlc_net_3109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3411 ( .LO ( optlc_net_3110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3412 ( .LO ( optlc_net_3111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3413 ( .LO ( optlc_net_3112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3414 ( .LO ( optlc_net_3113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3415 ( .LO ( optlc_net_3114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3416 ( .LO ( optlc_net_3115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3417 ( .LO ( optlc_net_3116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3418 ( .LO ( optlc_net_3117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3419 ( .LO ( optlc_net_3118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3420 ( .LO ( optlc_net_3119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3421 ( .LO ( optlc_net_3120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3422 ( .LO ( optlc_net_3121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3423 ( .LO ( optlc_net_3122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3424 ( .LO ( optlc_net_3123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3425 ( .LO ( optlc_net_3124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3426 ( .LO ( optlc_net_3125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3427 ( .LO ( optlc_net_3126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3428 ( .LO ( optlc_net_3127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3429 ( .LO ( optlc_net_3128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3430 ( .LO ( optlc_net_3129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3431 ( .LO ( optlc_net_3130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3432 ( .LO ( optlc_net_3131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3433 ( .LO ( optlc_net_3132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3434 ( .LO ( optlc_net_3133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3435 ( .LO ( optlc_net_3134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3436 ( .LO ( optlc_net_3135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3437 ( .LO ( optlc_net_3136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3438 ( .LO ( optlc_net_3137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3439 ( .LO ( optlc_net_3138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3440 ( .LO ( optlc_net_3139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3441 ( .LO ( optlc_net_3140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3442 ( .LO ( optlc_net_3141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3443 ( .LO ( optlc_net_3142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3444 ( .LO ( optlc_net_3143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3445 ( .LO ( optlc_net_3144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3446 ( .LO ( optlc_net_3145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3447 ( .LO ( optlc_net_3146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3448 ( .LO ( optlc_net_3147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3449 ( .LO ( optlc_net_3148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3450 ( .LO ( optlc_net_3149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3451 ( .LO ( optlc_net_3150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3452 ( .LO ( optlc_net_3151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3453 ( .LO ( optlc_net_3152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3454 ( .LO ( optlc_net_3153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3455 ( .LO ( optlc_net_3154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3456 ( .LO ( optlc_net_3155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3457 ( .LO ( optlc_net_3156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3458 ( .LO ( optlc_net_3157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3459 ( .LO ( optlc_net_3158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3460 ( .LO ( optlc_net_3159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3461 ( .LO ( optlc_net_3160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3462 ( .LO ( optlc_net_3161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3463 ( .LO ( optlc_net_3162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3464 ( .LO ( optlc_net_3163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3465 ( .LO ( optlc_net_3164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3466 ( .LO ( optlc_net_3165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3467 ( .LO ( optlc_net_3166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3468 ( .LO ( optlc_net_3167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3469 ( .LO ( optlc_net_3168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3470 ( .LO ( optlc_net_3169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3471 ( .LO ( optlc_net_3170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3472 ( .LO ( optlc_net_3171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3473 ( .LO ( optlc_net_3172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3474 ( .LO ( optlc_net_3173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3475 ( .LO ( optlc_net_3174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3476 ( .LO ( optlc_net_3175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3477 ( .LO ( optlc_net_3176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3478 ( .LO ( optlc_net_3177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3479 ( .LO ( optlc_net_3178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3480 ( .LO ( optlc_net_3179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3481 ( .LO ( optlc_net_3180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3482 ( .LO ( optlc_net_3181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3483 ( .LO ( optlc_net_3182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3484 ( .LO ( optlc_net_3183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3485 ( .LO ( optlc_net_3184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3486 ( .LO ( optlc_net_3185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3487 ( .LO ( optlc_net_3186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3488 ( .LO ( optlc_net_3187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3489 ( .LO ( optlc_net_3188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3490 ( .LO ( optlc_net_3189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3491 ( .LO ( optlc_net_3190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3492 ( .LO ( optlc_net_3191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3493 ( .LO ( optlc_net_3192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3494 ( .LO ( optlc_net_3193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3495 ( .LO ( optlc_net_3194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3496 ( .LO ( optlc_net_3195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3497 ( .LO ( optlc_net_3196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3498 ( .LO ( optlc_net_3197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3499 ( .LO ( optlc_net_3198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3500 ( .LO ( optlc_net_3199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3501 ( .LO ( optlc_net_3200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3502 ( .LO ( optlc_net_3201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3503 ( .LO ( optlc_net_3202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3504 ( .LO ( optlc_net_3203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3505 ( .LO ( optlc_net_3204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3506 ( .LO ( optlc_net_3205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3507 ( .LO ( optlc_net_3206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3508 ( .LO ( optlc_net_3207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3509 ( .LO ( optlc_net_3208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3510 ( .LO ( optlc_net_3209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3511 ( .LO ( optlc_net_3210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3512 ( .LO ( optlc_net_3211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3513 ( .LO ( optlc_net_3212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3514 ( .LO ( optlc_net_3213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3515 ( .LO ( optlc_net_3214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3516 ( .LO ( optlc_net_3215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3517 ( .LO ( optlc_net_3216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3518 ( .LO ( optlc_net_3217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3519 ( .LO ( optlc_net_3218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3520 ( .LO ( optlc_net_3219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3521 ( .LO ( optlc_net_3220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3522 ( .LO ( optlc_net_3221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3523 ( .LO ( optlc_net_3222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3524 ( .LO ( optlc_net_3223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3525 ( .LO ( optlc_net_3224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3526 ( .LO ( optlc_net_3225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3527 ( .LO ( optlc_net_3226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3528 ( .LO ( optlc_net_3227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3529 ( .LO ( optlc_net_3228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3530 ( .LO ( optlc_net_3229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3531 ( .LO ( optlc_net_3230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3532 ( .LO ( optlc_net_3231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3533 ( .LO ( optlc_net_3232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3534 ( .LO ( optlc_net_3233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3535 ( .LO ( optlc_net_3234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3536 ( .LO ( optlc_net_3235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3537 ( .LO ( optlc_net_3236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3538 ( .LO ( optlc_net_3237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3539 ( .LO ( optlc_net_3238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3540 ( .LO ( optlc_net_3239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3541 ( .LO ( optlc_net_3240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3542 ( .LO ( optlc_net_3241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3543 ( .LO ( optlc_net_3242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3544 ( .LO ( optlc_net_3243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3545 ( .LO ( optlc_net_3244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3546 ( .LO ( optlc_net_3245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3547 ( .LO ( optlc_net_3246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3548 ( .LO ( optlc_net_3247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3549 ( .LO ( optlc_net_3248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3550 ( .LO ( optlc_net_3249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3551 ( .LO ( optlc_net_3250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3552 ( .LO ( optlc_net_3251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3553 ( .LO ( optlc_net_3252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3554 ( .LO ( optlc_net_3253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3555 ( .LO ( optlc_net_3254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3556 ( .LO ( optlc_net_3255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3557 ( .LO ( optlc_net_3256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3558 ( .LO ( optlc_net_3257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3559 ( .LO ( optlc_net_3258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3560 ( .LO ( optlc_net_3259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3561 ( .LO ( optlc_net_3260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3562 ( .LO ( optlc_net_3261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3563 ( .LO ( optlc_net_3262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3564 ( .LO ( optlc_net_3263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3565 ( .LO ( optlc_net_3264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3566 ( .LO ( optlc_net_3265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3567 ( .LO ( optlc_net_3266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3568 ( .LO ( optlc_net_3267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3569 ( .LO ( optlc_net_3268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3570 ( .LO ( optlc_net_3269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3571 ( .LO ( optlc_net_3270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3572 ( .LO ( optlc_net_3271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3573 ( .LO ( optlc_net_3272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3574 ( .LO ( optlc_net_3273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3575 ( .LO ( optlc_net_3274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3576 ( .LO ( optlc_net_3275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3577 ( .LO ( optlc_net_3276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3578 ( .LO ( optlc_net_3277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3579 ( .LO ( optlc_net_3278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3580 ( .LO ( optlc_net_3279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3581 ( .LO ( optlc_net_3280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3582 ( .LO ( optlc_net_3281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3583 ( .LO ( optlc_net_3282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3584 ( .LO ( optlc_net_3283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3585 ( .LO ( optlc_net_3284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3586 ( .LO ( optlc_net_3285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3587 ( .LO ( optlc_net_3286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3588 ( .LO ( optlc_net_3287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3589 ( .LO ( optlc_net_3288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3590 ( .LO ( optlc_net_3289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3591 ( .LO ( optlc_net_3290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3592 ( .LO ( optlc_net_3291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3593 ( .LO ( optlc_net_3292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3594 ( .LO ( optlc_net_3293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3595 ( .LO ( optlc_net_3294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3596 ( .LO ( optlc_net_3295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3597 ( .LO ( optlc_net_3296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3598 ( .LO ( optlc_net_3297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3599 ( .LO ( optlc_net_3298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3600 ( .LO ( optlc_net_3299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3601 ( .LO ( optlc_net_3300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3602 ( .LO ( optlc_net_3301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3603 ( .LO ( optlc_net_3302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3604 ( .LO ( optlc_net_3303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3605 ( .LO ( optlc_net_3304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3606 ( .LO ( optlc_net_3305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3607 ( .LO ( optlc_net_3306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3608 ( .LO ( optlc_net_3307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3609 ( .LO ( optlc_net_3308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3610 ( .LO ( optlc_net_3309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3611 ( .LO ( optlc_net_3310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3612 ( .LO ( optlc_net_3311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3613 ( .LO ( optlc_net_3312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3614 ( .LO ( optlc_net_3313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3615 ( .LO ( optlc_net_3314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3616 ( .LO ( optlc_net_3315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3617 ( .LO ( optlc_net_3316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3618 ( .LO ( optlc_net_3317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3619 ( .LO ( optlc_net_3318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3620 ( .LO ( optlc_net_3319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3621 ( .LO ( optlc_net_3320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3622 ( .LO ( optlc_net_3321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3623 ( .LO ( optlc_net_3322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3624 ( .LO ( optlc_net_3323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3625 ( .LO ( optlc_net_3324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3626 ( .LO ( optlc_net_3325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3627 ( .LO ( optlc_net_3326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3628 ( .LO ( optlc_net_3327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3629 ( .LO ( optlc_net_3328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3630 ( .LO ( optlc_net_3329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3631 ( .LO ( optlc_net_3330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3632 ( .LO ( optlc_net_3331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3633 ( .LO ( optlc_net_3332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3634 ( .LO ( optlc_net_3333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3635 ( .LO ( optlc_net_3334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3636 ( .LO ( optlc_net_3335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3637 ( .LO ( optlc_net_3336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3638 ( .LO ( optlc_net_3337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3639 ( .LO ( optlc_net_3338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3640 ( .LO ( optlc_net_3339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3641 ( .LO ( optlc_net_3340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3642 ( .LO ( optlc_net_3341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3643 ( .LO ( optlc_net_3342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3644 ( .LO ( optlc_net_3343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3645 ( .LO ( optlc_net_3344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3646 ( .LO ( optlc_net_3345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3647 ( .LO ( optlc_net_3346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3648 ( .LO ( optlc_net_3347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3649 ( .LO ( optlc_net_3348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3650 ( .LO ( optlc_net_3349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3651 ( .LO ( optlc_net_3350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3652 ( .LO ( optlc_net_3351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3653 ( .LO ( optlc_net_3352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3654 ( .LO ( optlc_net_3353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3655 ( .LO ( optlc_net_3354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3656 ( .LO ( optlc_net_3355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3657 ( .LO ( optlc_net_3356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3658 ( .LO ( optlc_net_3357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3659 ( .LO ( optlc_net_3358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3660 ( .LO ( optlc_net_3359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3661 ( .LO ( optlc_net_3360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3662 ( .LO ( optlc_net_3361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3663 ( .LO ( optlc_net_3362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3664 ( .LO ( optlc_net_3363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3665 ( .LO ( optlc_net_3364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3666 ( .LO ( optlc_net_3365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3667 ( .LO ( optlc_net_3366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3668 ( .LO ( optlc_net_3367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3669 ( .LO ( optlc_net_3368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3670 ( .LO ( optlc_net_3369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3671 ( .LO ( optlc_net_3370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3672 ( .LO ( optlc_net_3371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3673 ( .LO ( optlc_net_3372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3674 ( .LO ( optlc_net_3373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3675 ( .LO ( optlc_net_3374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3676 ( .LO ( optlc_net_3375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3677 ( .LO ( optlc_net_3376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3678 ( .LO ( optlc_net_3377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3679 ( .LO ( optlc_net_3378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3680 ( .LO ( optlc_net_3379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3681 ( .LO ( optlc_net_3380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3682 ( .LO ( optlc_net_3381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3683 ( .LO ( optlc_net_3382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3684 ( .LO ( optlc_net_3383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3685 ( .LO ( optlc_net_3384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3686 ( .LO ( optlc_net_3385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3687 ( .LO ( optlc_net_3386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3688 ( .LO ( optlc_net_3387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3689 ( .LO ( optlc_net_3388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3690 ( .LO ( optlc_net_3389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3691 ( .LO ( optlc_net_3390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3692 ( .LO ( optlc_net_3391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3693 ( .LO ( optlc_net_3392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3694 ( .LO ( optlc_net_3393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3695 ( .LO ( optlc_net_3394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3696 ( .LO ( optlc_net_3395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3697 ( .LO ( optlc_net_3396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3698 ( .LO ( optlc_net_3397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3699 ( .LO ( optlc_net_3398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3700 ( .LO ( optlc_net_3399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3701 ( .LO ( optlc_net_3400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3702 ( .LO ( optlc_net_3401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3703 ( .LO ( optlc_net_3402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3704 ( .LO ( optlc_net_3403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3705 ( .LO ( optlc_net_3404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3706 ( .LO ( optlc_net_3405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3707 ( .LO ( optlc_net_3406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3708 ( .LO ( optlc_net_3407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3709 ( .LO ( optlc_net_3408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3710 ( .LO ( optlc_net_3409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3711 ( .LO ( optlc_net_3410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3712 ( .LO ( optlc_net_3411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3713 ( .LO ( optlc_net_3412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3714 ( .LO ( optlc_net_3413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3715 ( .LO ( optlc_net_3414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3716 ( .LO ( optlc_net_3415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3717 ( .LO ( optlc_net_3416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3718 ( .LO ( optlc_net_3417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3719 ( .LO ( optlc_net_3418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3720 ( .LO ( optlc_net_3419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3721 ( .LO ( optlc_net_3420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3722 ( .LO ( optlc_net_3421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3723 ( .LO ( optlc_net_3422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3724 ( .LO ( optlc_net_3423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3725 ( .LO ( optlc_net_3424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3726 ( .LO ( optlc_net_3425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3727 ( .LO ( optlc_net_3426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3728 ( .LO ( optlc_net_3427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3729 ( .LO ( optlc_net_3428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3730 ( .LO ( optlc_net_3429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3731 ( .LO ( optlc_net_3430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3732 ( .LO ( optlc_net_3431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3733 ( .LO ( optlc_net_3432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3734 ( .LO ( optlc_net_3433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3735 ( .LO ( optlc_net_3434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3736 ( .LO ( optlc_net_3435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3737 ( .LO ( optlc_net_3436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3738 ( .LO ( optlc_net_3437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3739 ( .LO ( optlc_net_3438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3740 ( .LO ( optlc_net_3439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3741 ( .LO ( optlc_net_3440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3742 ( .LO ( optlc_net_3441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3743 ( .LO ( optlc_net_3442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3744 ( .LO ( optlc_net_3443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3745 ( .LO ( optlc_net_3444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3746 ( .LO ( optlc_net_3445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3747 ( .LO ( optlc_net_3446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3748 ( .LO ( optlc_net_3447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3749 ( .LO ( optlc_net_3448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3750 ( .LO ( optlc_net_3449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3751 ( .LO ( optlc_net_3450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3752 ( .LO ( optlc_net_3451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3753 ( .LO ( optlc_net_3452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3754 ( .LO ( optlc_net_3453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3755 ( .LO ( optlc_net_3454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3756 ( .LO ( optlc_net_3455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3757 ( .LO ( optlc_net_3456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3758 ( .LO ( optlc_net_3457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3759 ( .LO ( optlc_net_3458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3760 ( .LO ( optlc_net_3459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3761 ( .LO ( optlc_net_3460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3762 ( .LO ( optlc_net_3461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3763 ( .LO ( optlc_net_3462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3764 ( .LO ( optlc_net_3463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3765 ( .LO ( optlc_net_3464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3766 ( .LO ( optlc_net_3465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3767 ( .LO ( optlc_net_3466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3768 ( .LO ( optlc_net_3467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3769 ( .LO ( optlc_net_3468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3770 ( .LO ( optlc_net_3469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3771 ( .LO ( optlc_net_3470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3772 ( .LO ( optlc_net_3471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3773 ( .LO ( optlc_net_3472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3774 ( .LO ( optlc_net_3473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3775 ( .LO ( optlc_net_3474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3776 ( .LO ( optlc_net_3475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3777 ( .LO ( optlc_net_3476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3778 ( .LO ( optlc_net_3477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3779 ( .LO ( optlc_net_3478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3780 ( .LO ( optlc_net_3479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3781 ( .LO ( optlc_net_3480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3782 ( .LO ( optlc_net_3481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3783 ( .LO ( optlc_net_3482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3784 ( .LO ( optlc_net_3483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3785 ( .LO ( optlc_net_3484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3786 ( .LO ( optlc_net_3485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3787 ( .LO ( optlc_net_3486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3788 ( .LO ( optlc_net_3487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3789 ( .LO ( optlc_net_3488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3790 ( .LO ( optlc_net_3489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3791 ( .LO ( optlc_net_3490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3792 ( .LO ( optlc_net_3491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3793 ( .LO ( optlc_net_3492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3794 ( .LO ( optlc_net_3493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3795 ( .LO ( optlc_net_3494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3796 ( .LO ( optlc_net_3495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3797 ( .LO ( optlc_net_3496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3798 ( .LO ( optlc_net_3497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3799 ( .LO ( optlc_net_3498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3800 ( .LO ( optlc_net_3499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3801 ( .LO ( optlc_net_3500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3802 ( .LO ( optlc_net_3501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3803 ( .LO ( optlc_net_3502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3804 ( .LO ( optlc_net_3503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3805 ( .LO ( optlc_net_3504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3806 ( .LO ( optlc_net_3505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3807 ( .LO ( optlc_net_3506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3808 ( .LO ( optlc_net_3507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3809 ( .LO ( optlc_net_3508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3810 ( .LO ( optlc_net_3509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3811 ( .LO ( optlc_net_3510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3812 ( .LO ( optlc_net_3511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3813 ( .LO ( optlc_net_3512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3814 ( .LO ( optlc_net_3513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3815 ( .LO ( optlc_net_3514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3816 ( .LO ( optlc_net_3515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3817 ( .LO ( optlc_net_3516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3818 ( .LO ( optlc_net_3517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3819 ( .LO ( optlc_net_3518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3820 ( .LO ( optlc_net_3519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3821 ( .LO ( optlc_net_3520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3822 ( .LO ( optlc_net_3521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3823 ( .LO ( optlc_net_3522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3824 ( .LO ( optlc_net_3523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3825 ( .LO ( optlc_net_3524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3826 ( .LO ( optlc_net_3525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3827 ( .LO ( optlc_net_3526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3828 ( .LO ( optlc_net_3527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3829 ( .LO ( optlc_net_3528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3830 ( .LO ( optlc_net_3529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3831 ( .LO ( optlc_net_3530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3832 ( .LO ( optlc_net_3531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3833 ( .LO ( optlc_net_3532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3834 ( .LO ( optlc_net_3533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3835 ( .LO ( optlc_net_3534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3836 ( .LO ( optlc_net_3535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3837 ( .LO ( optlc_net_3536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3838 ( .LO ( optlc_net_3537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3839 ( .LO ( optlc_net_3538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ;
+endmodule
+
+
diff --git a/SOFA_HD/fpga_top/fpga_top_icv_in_design.top_only.pt.v b/SOFA_HD/fpga_top/fpga_top_icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..da8eb77
--- /dev/null
+++ b/SOFA_HD/fpga_top/fpga_top_icv_in_design.top_only.pt.v
@@ -0,0 +1,9838 @@
+//
+//
+//
+//
+//
+//
+module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 ,
+ vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i ,
+ wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in ,
+ la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ ,
+ analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ ,
+ analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ ,
+ analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ ,
+ analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ ,
+ analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ ,
+ analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ ,
+ analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ ,
+ analog_io_9_ , user_clock2 ) ;
+inout vdda1 ;
+inout vdda2 ;
+inout vssa1 ;
+inout vssa2 ;
+inout vccd1 ;
+inout vccd2 ;
+inout vssd1 ;
+inout vssd2 ;
+input wb_clk_i ;
+input wb_rst_i ;
+input wbs_stb_i ;
+input wbs_cyc_i ;
+input wbs_we_i ;
+input [3:0] wbs_sel_i ;
+input [31:0] wbs_dat_i ;
+input [31:0] wbs_adr_i ;
+output wbs_ack_o ;
+output [31:0] wbs_dat_o ;
+input [127:0] la_data_in ;
+output [127:0] la_data_out ;
+input [127:0] la_oen ;
+input [37:0] io_in ;
+output [37:0] io_out ;
+output [37:0] io_oeb ;
+inout analog_io_0_ ;
+inout analog_io_10_ ;
+inout analog_io_11_ ;
+inout analog_io_12_ ;
+inout analog_io_13_ ;
+inout analog_io_14_ ;
+inout analog_io_15_ ;
+inout analog_io_16_ ;
+inout analog_io_17_ ;
+inout analog_io_18_ ;
+inout analog_io_19_ ;
+inout analog_io_1_ ;
+inout analog_io_20_ ;
+inout analog_io_21_ ;
+inout analog_io_22_ ;
+inout analog_io_23_ ;
+inout analog_io_24_ ;
+inout analog_io_25_ ;
+inout analog_io_26_ ;
+inout analog_io_27_ ;
+inout analog_io_28_ ;
+inout analog_io_29_ ;
+inout analog_io_2_ ;
+inout analog_io_30_ ;
+inout analog_io_3_ ;
+inout analog_io_4_ ;
+inout analog_io_5_ ;
+inout analog_io_6_ ;
+inout analog_io_7_ ;
+inout analog_io_8_ ;
+inout analog_io_9_ ;
+input user_clock2 ;
+
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+wire ccff_head ;
+wire sc_tail ;
+wire io_isol_n ;
+wire Test_en ;
+wire prog_clk ;
+wire clk ;
+wire ccff_tail ;
+wire sc_head ;
+wire wb_la_switch ;
+
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ;
+assign ccff_head = io_in[12] ;
+assign sc_tail = io_out[11] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = io_in[3] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = io_in[2] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = io_out[3] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = io_out[2] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] = io_oeb[3] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] = io_oeb[2] ;
+assign io_isol_n = io_in[1] ;
+assign Test_en = io_in[0] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[25] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[26] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[36] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[37] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[38] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[39] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[40] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[41] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[42] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[43] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[44] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[45] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[46] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[47] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[48] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[49] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[50] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[51] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[52] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[53] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[54] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[55] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[56] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[57] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[58] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[59] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[60] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[61] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[62] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[63] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[64] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[65] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[66] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[67] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[68] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[69] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[70] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[71] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[72] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[73] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[74] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[75] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[76] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[77] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[78] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[79] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[80] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[81] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[82] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[83] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[84] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[85] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[86] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[87] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[88] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[89] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[90] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[91] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[92] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[93] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[94] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[95] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[96] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[97] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[98] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[99] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[100] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[101] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[102] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[103] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[104] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[105] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[106] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[107] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[108] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[109] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[110] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[111] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[112] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[113] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[114] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[115] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[116] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[127] ;
+assign prog_clk = io_in[37] ;
+assign clk = io_in[36] ;
+assign ccff_tail = io_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ;
+assign sc_head = io_in[26] ;
+assign wb_la_switch = io_in[25] ;
+
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[13] ) ,
+ .A1 ( wb_clk_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[14] ) ,
+ .A1 ( wb_rst_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_ack_o ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[15] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[16] ) ,
+ .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[17] ) ,
+ .A1 ( wbs_stb_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[18] ) ,
+ .A1 ( wbs_we_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[19] ) ,
+ .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[20] ) ,
+ .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[21] ) ,
+ .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[22] ) ,
+ .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[23] ) ,
+ .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[24] ) ,
+ .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[25] ) ,
+ .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[26] ) ,
+ .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[27] ) ,
+ .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[28] ) ,
+ .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[29] ) ,
+ .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[30] ) ,
+ .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[31] ) ,
+ .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[32] ) ,
+ .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[33] ) ,
+ .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[34] ) ,
+ .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[35] ) ,
+ .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[36] ) ,
+ .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[37] ) ,
+ .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[38] ) ,
+ .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[39] ) ,
+ .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[40] ) ,
+ .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[41] ) ,
+ .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[42] ) ,
+ .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[43] ) ,
+ .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[44] ) ,
+ .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[45] ) ,
+ .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[46] ) ,
+ .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[47] ) ,
+ .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[48] ) ,
+ .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[49] ) ,
+ .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[50] ) ,
+ .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[51] ) ,
+ .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[52] ) ,
+ .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[53] ) ,
+ .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[54] ) ,
+ .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[55] ) ,
+ .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[56] ) ,
+ .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[57] ) ,
+ .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[58] ) ,
+ .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[59] ) ,
+ .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[60] ) ,
+ .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[61] ) ,
+ .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[62] ) ,
+ .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[63] ) ,
+ .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[64] ) ,
+ .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[65] ) ,
+ .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[66] ) ,
+ .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[67] ) ,
+ .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[68] ) ,
+ .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[69] ) ,
+ .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[70] ) ,
+ .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[71] ) ,
+ .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[72] ) ,
+ .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[73] ) ,
+ .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[74] ) ,
+ .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[75] ) ,
+ .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[76] ) ,
+ .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[77] ) ,
+ .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[78] ) ,
+ .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[79] ) ,
+ .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[80] ) ,
+ .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[81] ) ,
+ .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[82] ) ,
+ .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[83] ) ,
+ .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[84] ) ,
+ .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[85] ) ,
+ .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[86] ) ,
+ .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[0] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[87] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[1] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[88] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[2] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[89] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[3] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[90] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[4] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[91] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[5] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[92] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[6] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[93] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[7] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[94] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[8] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[95] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[9] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[96] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[10] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[97] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[11] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[98] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[12] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[99] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[13] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[100] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[14] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[101] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[15] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[102] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[16] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[103] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[17] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[104] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[18] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[105] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[19] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[106] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[20] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[107] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[21] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[108] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[22] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[109] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[23] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[110] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[24] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[111] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[25] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[112] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[26] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[113] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[27] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[114] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[28] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[115] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[29] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[116] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[30] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[117] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[31] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[118] ) ) ;
+fpga_core fpga_core_uut ( .prog_clk ( io_in[37] ) , .Test_en ( io_in[0] ) ,
+ .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] ,
+ io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] ,
+ io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] ,
+ io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] , io_in[3] ,
+ io_in[2] , la_data_in[127] , la_data_in[126] , la_data_in[125] ,
+ la_data_in[124] , la_data_in[123] , la_data_in[122] ,
+ la_data_in[121] , la_data_in[120] , la_data_in[119] ,
+ la_data_in[118] , la_data_in[117] , la_data_in[116] ,
+ la_data_in[115] , la_data_in[114] , la_data_in[113] ,
+ la_data_in[112] , la_data_in[111] , la_data_in[110] ,
+ la_data_in[109] , la_data_in[108] , la_data_in[107] ,
+ la_data_in[106] , la_data_in[105] , la_data_in[104] ,
+ la_data_in[103] , la_data_in[102] , la_data_in[101] ,
+ la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] ,
+ la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] ,
+ la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] ,
+ la_data_in[88] , la_data_in[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[15] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] ,
+ io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] ,
+ io_in[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] ,
+ io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] ,
+ io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] ,
+ io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] ,
+ io_out[5] , io_out[4] , io_out[3] , io_out[2] , la_data_out[127] ,
+ la_data_out[126] , la_data_out[125] , la_data_out[124] ,
+ la_data_out[123] , la_data_out[122] , la_data_out[121] ,
+ la_data_out[120] , la_data_out[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[86] ,
+ la_data_out[85] , la_data_out[84] , la_data_out[83] ,
+ la_data_out[82] , la_data_out[81] , la_data_out[80] ,
+ la_data_out[79] , la_data_out[78] , la_data_out[77] ,
+ la_data_out[76] , la_data_out[75] , la_data_out[74] ,
+ la_data_out[73] , la_data_out[72] , la_data_out[71] ,
+ la_data_out[70] , la_data_out[69] , la_data_out[68] ,
+ la_data_out[67] , la_data_out[66] , la_data_out[65] ,
+ la_data_out[64] , la_data_out[63] , la_data_out[62] ,
+ la_data_out[61] , la_data_out[60] , la_data_out[59] ,
+ la_data_out[58] , la_data_out[57] , la_data_out[56] ,
+ la_data_out[55] , la_data_out[54] , la_data_out[53] ,
+ la_data_out[52] , la_data_out[51] , la_data_out[50] ,
+ la_data_out[49] , la_data_out[48] , la_data_out[47] ,
+ la_data_out[46] , la_data_out[45] , la_data_out[44] ,
+ la_data_out[43] , la_data_out[42] , la_data_out[41] ,
+ la_data_out[40] , la_data_out[39] , la_data_out[38] ,
+ la_data_out[37] , la_data_out[36] , la_data_out[35] ,
+ la_data_out[34] , la_data_out[33] , la_data_out[32] ,
+ la_data_out[31] , la_data_out[30] , la_data_out[29] ,
+ la_data_out[28] , la_data_out[27] , la_data_out[26] ,
+ la_data_out[25] , la_data_out[24] , la_data_out[23] ,
+ la_data_out[22] , la_data_out[21] , la_data_out[20] ,
+ la_data_out[19] , la_data_out[18] , la_data_out[17] ,
+ la_data_out[16] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ,
+ la_data_out[14] , la_data_out[13] , io_out[34] , io_out[33] ,
+ io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] ,
+ io_out[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] ,
+ io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] ,
+ io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] ,
+ io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] ,
+ io_oeb[5] , io_oeb[4] , io_oeb[3] , io_oeb[2] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] ,
+ io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] ,
+ io_oeb[27] } ) ,
+ .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) ,
+ .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) ,
+ .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , .p0 ( optlc_net_16 ) ,
+ .p1 ( optlc_net_17 ) , .p2 ( optlc_net_18 ) , .p3 ( optlc_net_19 ) ,
+ .p4 ( optlc_net_20 ) , .p5 ( optlc_net_21 ) , .p6 ( optlc_net_22 ) ,
+ .p7 ( optlc_net_23 ) , .p8 ( optlc_net_24 ) , .p9 ( optlc_net_25 ) ,
+ .p10 ( optlc_net_26 ) , .p11 ( optlc_net_27 ) , .p12 ( optlc_net_28 ) ,
+ .p13 ( optlc_net_29 ) , .p14 ( optlc_net_30 ) , .p15 ( optlc_net_31 ) ,
+ .p16 ( optlc_net_32 ) , .p17 ( optlc_net_33 ) , .p18 ( optlc_net_34 ) ,
+ .p19 ( optlc_net_35 ) , .p20 ( optlc_net_36 ) , .p21 ( optlc_net_37 ) ,
+ .p22 ( optlc_net_38 ) , .p23 ( optlc_net_39 ) , .p24 ( optlc_net_40 ) ,
+ .p25 ( optlc_net_41 ) , .p26 ( optlc_net_42 ) , .p27 ( optlc_net_43 ) ,
+ .p28 ( optlc_net_44 ) , .p29 ( optlc_net_45 ) , .p30 ( optlc_net_46 ) ,
+ .p31 ( optlc_net_47 ) , .p32 ( optlc_net_48 ) , .p33 ( optlc_net_49 ) ,
+ .p34 ( optlc_net_50 ) , .p35 ( optlc_net_51 ) , .p36 ( optlc_net_52 ) ,
+ .p37 ( optlc_net_53 ) , .p38 ( optlc_net_54 ) , .p39 ( optlc_net_55 ) ,
+ .p40 ( optlc_net_56 ) , .p41 ( optlc_net_57 ) , .p42 ( optlc_net_58 ) ,
+ .p43 ( optlc_net_59 ) , .p44 ( optlc_net_60 ) , .p45 ( optlc_net_61 ) ,
+ .p46 ( optlc_net_62 ) , .p47 ( optlc_net_63 ) , .p48 ( optlc_net_64 ) ,
+ .p49 ( optlc_net_65 ) , .p50 ( optlc_net_66 ) , .p51 ( optlc_net_67 ) ,
+ .p52 ( optlc_net_68 ) , .p53 ( optlc_net_69 ) , .p54 ( optlc_net_70 ) ,
+ .p55 ( optlc_net_71 ) , .p56 ( optlc_net_72 ) , .p57 ( optlc_net_73 ) ,
+ .p58 ( optlc_net_74 ) , .p59 ( optlc_net_75 ) , .p60 ( optlc_net_76 ) ,
+ .p61 ( optlc_net_77 ) , .p62 ( optlc_net_78 ) , .p63 ( optlc_net_79 ) ,
+ .p64 ( optlc_net_80 ) , .p65 ( optlc_net_81 ) , .p66 ( optlc_net_82 ) ,
+ .p67 ( optlc_net_83 ) , .p68 ( optlc_net_84 ) , .p69 ( optlc_net_85 ) ,
+ .p70 ( optlc_net_86 ) , .p71 ( optlc_net_87 ) , .p72 ( optlc_net_88 ) ,
+ .p73 ( optlc_net_89 ) , .p74 ( optlc_net_90 ) , .p75 ( optlc_net_91 ) ,
+ .p76 ( optlc_net_92 ) , .p77 ( optlc_net_93 ) , .p78 ( optlc_net_94 ) ,
+ .p79 ( optlc_net_95 ) , .p80 ( optlc_net_96 ) , .p81 ( optlc_net_97 ) ,
+ .p82 ( optlc_net_98 ) , .p83 ( optlc_net_99 ) , .p84 ( optlc_net_100 ) ,
+ .p85 ( optlc_net_101 ) , .p86 ( optlc_net_102 ) , .p87 ( optlc_net_103 ) ,
+ .p88 ( optlc_net_104 ) , .p89 ( optlc_net_105 ) , .p90 ( optlc_net_106 ) ,
+ .p91 ( optlc_net_107 ) , .p92 ( optlc_net_108 ) , .p93 ( optlc_net_109 ) ,
+ .p94 ( optlc_net_110 ) , .p95 ( optlc_net_111 ) , .p96 ( optlc_net_112 ) ,
+ .p97 ( optlc_net_113 ) , .p98 ( optlc_net_114 ) , .p99 ( optlc_net_115 ) ,
+ .p100 ( optlc_net_116 ) , .p101 ( optlc_net_117 ) ,
+ .p102 ( optlc_net_118 ) , .p103 ( optlc_net_119 ) ,
+ .p104 ( optlc_net_120 ) , .p105 ( optlc_net_121 ) ,
+ .p106 ( optlc_net_122 ) , .p107 ( optlc_net_123 ) ,
+ .p108 ( optlc_net_124 ) , .p109 ( optlc_net_125 ) ,
+ .p110 ( optlc_net_126 ) , .p111 ( optlc_net_127 ) ,
+ .p112 ( optlc_net_128 ) , .p113 ( optlc_net_129 ) ,
+ .p114 ( optlc_net_130 ) , .p115 ( optlc_net_131 ) ,
+ .p116 ( optlc_net_132 ) , .p117 ( optlc_net_133 ) ,
+ .p118 ( optlc_net_134 ) , .p119 ( optlc_net_135 ) ,
+ .p120 ( optlc_net_136 ) , .p121 ( optlc_net_137 ) ,
+ .p122 ( optlc_net_138 ) , .p123 ( optlc_net_139 ) ,
+ .p124 ( optlc_net_140 ) , .p125 ( optlc_net_141 ) ,
+ .p126 ( optlc_net_142 ) , .p127 ( optlc_net_143 ) ,
+ .p128 ( optlc_net_144 ) , .p129 ( optlc_net_145 ) ,
+ .p130 ( optlc_net_146 ) , .p131 ( optlc_net_147 ) ,
+ .p132 ( optlc_net_148 ) , .p133 ( optlc_net_149 ) ,
+ .p134 ( optlc_net_150 ) , .p135 ( optlc_net_151 ) ,
+ .p136 ( optlc_net_152 ) , .p137 ( optlc_net_153 ) ,
+ .p138 ( optlc_net_154 ) , .p139 ( optlc_net_155 ) ,
+ .p140 ( optlc_net_156 ) , .p141 ( optlc_net_157 ) ,
+ .p142 ( optlc_net_158 ) , .p143 ( optlc_net_159 ) ,
+ .p144 ( optlc_net_160 ) , .p145 ( optlc_net_161 ) ,
+ .p146 ( optlc_net_162 ) , .p147 ( optlc_net_163 ) ,
+ .p148 ( optlc_net_164 ) , .p149 ( optlc_net_165 ) ,
+ .p150 ( optlc_net_166 ) , .p151 ( optlc_net_167 ) ,
+ .p152 ( optlc_net_168 ) , .p153 ( optlc_net_169 ) ,
+ .p154 ( optlc_net_170 ) , .p155 ( optlc_net_171 ) ,
+ .p156 ( optlc_net_172 ) , .p157 ( optlc_net_173 ) ,
+ .p158 ( optlc_net_174 ) , .p159 ( optlc_net_175 ) ,
+ .p160 ( optlc_net_176 ) , .p161 ( optlc_net_177 ) ,
+ .p162 ( optlc_net_178 ) , .p163 ( optlc_net_179 ) ,
+ .p164 ( optlc_net_180 ) , .p165 ( optlc_net_181 ) ,
+ .p166 ( optlc_net_182 ) , .p167 ( optlc_net_183 ) ,
+ .p168 ( optlc_net_184 ) , .p169 ( optlc_net_185 ) ,
+ .p170 ( optlc_net_186 ) , .p171 ( optlc_net_187 ) ,
+ .p172 ( optlc_net_188 ) , .p173 ( optlc_net_189 ) ,
+ .p174 ( optlc_net_190 ) , .p175 ( optlc_net_191 ) ,
+ .p176 ( optlc_net_192 ) , .p177 ( optlc_net_193 ) ,
+ .p178 ( optlc_net_194 ) , .p179 ( optlc_net_195 ) ,
+ .p180 ( optlc_net_196 ) , .p181 ( optlc_net_197 ) ,
+ .p182 ( optlc_net_198 ) , .p183 ( optlc_net_199 ) ,
+ .p184 ( optlc_net_200 ) , .p185 ( optlc_net_201 ) ,
+ .p186 ( optlc_net_202 ) , .p187 ( optlc_net_203 ) ,
+ .p188 ( optlc_net_204 ) , .p189 ( optlc_net_205 ) ,
+ .p190 ( optlc_net_206 ) , .p191 ( optlc_net_207 ) ,
+ .p192 ( optlc_net_208 ) , .p193 ( optlc_net_209 ) ,
+ .p194 ( optlc_net_210 ) , .p195 ( optlc_net_211 ) ,
+ .p196 ( optlc_net_212 ) , .p197 ( optlc_net_213 ) ,
+ .p198 ( optlc_net_214 ) , .p199 ( optlc_net_215 ) ,
+ .p200 ( optlc_net_216 ) , .p201 ( optlc_net_217 ) ,
+ .p202 ( optlc_net_218 ) , .p203 ( optlc_net_219 ) ,
+ .p204 ( optlc_net_220 ) , .p205 ( optlc_net_221 ) ,
+ .p206 ( optlc_net_222 ) , .p207 ( optlc_net_223 ) ,
+ .p208 ( optlc_net_224 ) , .p209 ( optlc_net_225 ) ,
+ .p210 ( optlc_net_226 ) , .p211 ( optlc_net_227 ) ,
+ .p212 ( optlc_net_228 ) , .p213 ( optlc_net_229 ) ,
+ .p214 ( optlc_net_230 ) , .p215 ( optlc_net_231 ) ,
+ .p216 ( optlc_net_232 ) , .p217 ( optlc_net_233 ) ,
+ .p218 ( optlc_net_234 ) , .p219 ( optlc_net_235 ) ,
+ .p220 ( optlc_net_236 ) , .p221 ( optlc_net_237 ) ,
+ .p222 ( optlc_net_238 ) , .p223 ( optlc_net_239 ) ,
+ .p224 ( optlc_net_240 ) , .p225 ( optlc_net_241 ) ,
+ .p226 ( optlc_net_242 ) , .p227 ( optlc_net_243 ) ,
+ .p228 ( optlc_net_244 ) , .p229 ( optlc_net_245 ) ,
+ .p230 ( optlc_net_246 ) , .p231 ( optlc_net_247 ) ,
+ .p232 ( optlc_net_248 ) , .p233 ( optlc_net_249 ) ,
+ .p234 ( optlc_net_250 ) , .p235 ( optlc_net_251 ) ,
+ .p236 ( optlc_net_252 ) , .p237 ( optlc_net_253 ) ,
+ .p238 ( optlc_net_254 ) , .p239 ( optlc_net_255 ) ,
+ .p240 ( optlc_net_256 ) , .p241 ( optlc_net_257 ) ,
+ .p242 ( optlc_net_258 ) , .p243 ( optlc_net_259 ) ,
+ .p244 ( optlc_net_260 ) , .p245 ( optlc_net_261 ) ,
+ .p246 ( optlc_net_262 ) , .p247 ( optlc_net_263 ) ,
+ .p248 ( optlc_net_264 ) , .p249 ( optlc_net_265 ) ,
+ .p250 ( optlc_net_266 ) , .p251 ( optlc_net_267 ) ,
+ .p252 ( optlc_net_268 ) , .p253 ( optlc_net_269 ) ,
+ .p254 ( optlc_net_270 ) , .p255 ( optlc_net_271 ) ,
+ .p256 ( optlc_net_272 ) , .p257 ( optlc_net_273 ) ,
+ .p258 ( optlc_net_274 ) , .p259 ( optlc_net_275 ) ,
+ .p260 ( optlc_net_276 ) , .p261 ( optlc_net_277 ) ,
+ .p262 ( optlc_net_278 ) , .p263 ( optlc_net_279 ) ,
+ .p264 ( optlc_net_280 ) , .p265 ( optlc_net_281 ) ,
+ .p266 ( optlc_net_282 ) , .p267 ( optlc_net_283 ) ,
+ .p268 ( optlc_net_284 ) , .p269 ( optlc_net_285 ) ,
+ .p270 ( optlc_net_286 ) , .p271 ( optlc_net_287 ) ,
+ .p272 ( optlc_net_288 ) , .p273 ( optlc_net_289 ) ,
+ .p274 ( optlc_net_290 ) , .p275 ( optlc_net_291 ) ,
+ .p276 ( optlc_net_292 ) , .p277 ( optlc_net_293 ) ,
+ .p278 ( optlc_net_294 ) , .p279 ( optlc_net_295 ) ,
+ .p280 ( optlc_net_296 ) , .p281 ( optlc_net_297 ) ,
+ .p282 ( optlc_net_298 ) , .p283 ( optlc_net_299 ) ,
+ .p284 ( optlc_net_300 ) , .p285 ( optlc_net_301 ) ,
+ .p286 ( optlc_net_302 ) , .p287 ( optlc_net_303 ) ,
+ .p288 ( optlc_net_304 ) , .p289 ( optlc_net_305 ) ,
+ .p290 ( optlc_net_306 ) , .p291 ( optlc_net_307 ) ,
+ .p292 ( optlc_net_308 ) , .p293 ( optlc_net_309 ) ,
+ .p294 ( optlc_net_310 ) , .p295 ( optlc_net_311 ) ,
+ .p296 ( optlc_net_312 ) , .p297 ( optlc_net_313 ) ,
+ .p298 ( optlc_net_314 ) , .p299 ( optlc_net_315 ) ,
+ .p300 ( optlc_net_316 ) , .p301 ( optlc_net_317 ) ,
+ .p302 ( optlc_net_318 ) , .p303 ( optlc_net_319 ) ,
+ .p304 ( optlc_net_320 ) , .p305 ( optlc_net_321 ) ,
+ .p306 ( optlc_net_322 ) , .p307 ( optlc_net_323 ) ,
+ .p308 ( optlc_net_324 ) , .p309 ( optlc_net_325 ) ,
+ .p310 ( optlc_net_326 ) , .p311 ( optlc_net_327 ) ,
+ .p312 ( optlc_net_328 ) , .p313 ( optlc_net_329 ) ,
+ .p314 ( optlc_net_330 ) , .p315 ( optlc_net_331 ) ,
+ .p316 ( optlc_net_332 ) , .p317 ( optlc_net_333 ) ,
+ .p318 ( optlc_net_334 ) , .p319 ( optlc_net_335 ) ,
+ .p320 ( optlc_net_336 ) , .p321 ( optlc_net_337 ) ,
+ .p322 ( optlc_net_338 ) , .p323 ( optlc_net_339 ) ,
+ .p324 ( optlc_net_340 ) , .p325 ( optlc_net_341 ) ,
+ .p326 ( optlc_net_342 ) , .p327 ( optlc_net_343 ) ,
+ .p328 ( optlc_net_344 ) , .p329 ( optlc_net_345 ) ,
+ .p330 ( optlc_net_346 ) , .p331 ( optlc_net_347 ) ,
+ .p332 ( optlc_net_348 ) , .p333 ( optlc_net_349 ) ,
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+ .p336 ( optlc_net_352 ) , .p337 ( optlc_net_353 ) ,
+ .p338 ( optlc_net_354 ) , .p339 ( optlc_net_355 ) ,
+ .p340 ( optlc_net_356 ) , .p341 ( optlc_net_357 ) ,
+ .p342 ( optlc_net_358 ) , .p343 ( optlc_net_359 ) ,
+ .p344 ( optlc_net_360 ) , .p345 ( optlc_net_361 ) ,
+ .p346 ( optlc_net_362 ) , .p347 ( optlc_net_363 ) ,
+ .p348 ( optlc_net_364 ) , .p349 ( optlc_net_365 ) ,
+ .p350 ( optlc_net_366 ) , .p351 ( optlc_net_367 ) ,
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+ .p654 ( optlc_net_670 ) , .p655 ( optlc_net_671 ) ,
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+ .p680 ( optlc_net_696 ) , .p681 ( optlc_net_697 ) ,
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+ .p688 ( optlc_net_704 ) , .p689 ( optlc_net_705 ) ,
+ .p690 ( optlc_net_706 ) , .p691 ( optlc_net_707 ) ,
+ .p692 ( optlc_net_708 ) , .p693 ( optlc_net_709 ) ,
+ .p694 ( optlc_net_710 ) , .p695 ( optlc_net_711 ) ,
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+ .p698 ( optlc_net_714 ) , .p699 ( optlc_net_715 ) ,
+ .p700 ( optlc_net_716 ) , .p701 ( optlc_net_717 ) ,
+ .p702 ( optlc_net_718 ) , .p703 ( optlc_net_719 ) ,
+ .p704 ( optlc_net_720 ) , .p705 ( optlc_net_721 ) ,
+ .p706 ( optlc_net_722 ) , .p707 ( optlc_net_723 ) ,
+ .p708 ( optlc_net_724 ) , .p709 ( optlc_net_725 ) ,
+ .p710 ( optlc_net_726 ) , .p711 ( optlc_net_727 ) ,
+ .p712 ( optlc_net_728 ) , .p713 ( optlc_net_729 ) ,
+ .p714 ( optlc_net_730 ) , .p715 ( optlc_net_731 ) ,
+ .p716 ( optlc_net_732 ) , .p717 ( optlc_net_733 ) ,
+ .p718 ( optlc_net_734 ) , .p719 ( optlc_net_735 ) ,
+ .p720 ( optlc_net_736 ) , .p721 ( optlc_net_737 ) ,
+ .p722 ( optlc_net_738 ) , .p723 ( optlc_net_739 ) ,
+ .p724 ( optlc_net_740 ) , .p725 ( optlc_net_741 ) ,
+ .p726 ( optlc_net_742 ) , .p727 ( optlc_net_743 ) ,
+ .p728 ( optlc_net_744 ) , .p729 ( optlc_net_745 ) ,
+ .p730 ( optlc_net_746 ) , .p731 ( optlc_net_747 ) ,
+ .p732 ( optlc_net_748 ) , .p733 ( optlc_net_749 ) ,
+ .p734 ( optlc_net_750 ) , .p735 ( optlc_net_751 ) ,
+ .p736 ( optlc_net_752 ) , .p737 ( optlc_net_753 ) ,
+ .p738 ( optlc_net_754 ) , .p739 ( optlc_net_755 ) ,
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+ .p744 ( optlc_net_760 ) , .p745 ( optlc_net_761 ) ,
+ .p746 ( optlc_net_762 ) , .p747 ( optlc_net_763 ) ,
+ .p748 ( optlc_net_764 ) , .p749 ( optlc_net_765 ) ,
+ .p750 ( optlc_net_766 ) , .p751 ( optlc_net_767 ) ,
+ .p752 ( optlc_net_768 ) , .p753 ( optlc_net_769 ) ,
+ .p754 ( optlc_net_770 ) , .p755 ( optlc_net_771 ) ,
+ .p756 ( optlc_net_772 ) , .p757 ( optlc_net_773 ) ,
+ .p758 ( optlc_net_774 ) , .p759 ( optlc_net_775 ) ,
+ .p760 ( optlc_net_776 ) , .p761 ( optlc_net_777 ) ,
+ .p762 ( optlc_net_778 ) , .p763 ( optlc_net_779 ) ,
+ .p764 ( optlc_net_780 ) , .p765 ( optlc_net_781 ) ,
+ .p766 ( optlc_net_782 ) , .p767 ( optlc_net_783 ) ,
+ .p768 ( optlc_net_784 ) , .p769 ( optlc_net_785 ) ,
+ .p770 ( optlc_net_786 ) , .p771 ( optlc_net_787 ) ,
+ .p772 ( optlc_net_788 ) , .p773 ( optlc_net_789 ) ,
+ .p774 ( optlc_net_790 ) , .p775 ( optlc_net_791 ) ,
+ .p776 ( optlc_net_792 ) , .p777 ( optlc_net_793 ) ,
+ .p778 ( optlc_net_794 ) , .p779 ( optlc_net_795 ) ,
+ .p780 ( optlc_net_796 ) , .p781 ( optlc_net_797 ) ,
+ .p782 ( optlc_net_798 ) , .p783 ( optlc_net_799 ) ,
+ .p784 ( optlc_net_800 ) , .p785 ( optlc_net_801 ) ,
+ .p786 ( optlc_net_802 ) , .p787 ( optlc_net_803 ) ,
+ .p788 ( optlc_net_804 ) , .p789 ( optlc_net_805 ) ,
+ .p790 ( optlc_net_806 ) , .p791 ( optlc_net_807 ) ,
+ .p792 ( optlc_net_808 ) , .p793 ( optlc_net_809 ) ,
+ .p794 ( optlc_net_810 ) , .p795 ( optlc_net_811 ) ,
+ .p796 ( optlc_net_812 ) , .p797 ( optlc_net_813 ) ,
+ .p798 ( optlc_net_814 ) , .p799 ( optlc_net_815 ) ,
+ .p800 ( optlc_net_816 ) , .p801 ( optlc_net_817 ) ,
+ .p802 ( optlc_net_818 ) , .p803 ( optlc_net_819 ) ,
+ .p804 ( optlc_net_820 ) , .p805 ( optlc_net_821 ) ,
+ .p806 ( optlc_net_822 ) , .p807 ( optlc_net_823 ) ,
+ .p808 ( optlc_net_824 ) , .p809 ( optlc_net_825 ) ,
+ .p810 ( optlc_net_826 ) , .p811 ( optlc_net_827 ) ,
+ .p812 ( optlc_net_828 ) , .p813 ( optlc_net_829 ) ,
+ .p814 ( optlc_net_830 ) , .p815 ( optlc_net_831 ) ,
+ .p816 ( optlc_net_832 ) , .p817 ( optlc_net_833 ) ,
+ .p818 ( optlc_net_834 ) , .p819 ( optlc_net_835 ) ,
+ .p820 ( optlc_net_836 ) , .p821 ( optlc_net_837 ) ,
+ .p822 ( optlc_net_838 ) , .p823 ( optlc_net_839 ) ,
+ .p824 ( optlc_net_840 ) , .p825 ( optlc_net_841 ) ,
+ .p826 ( optlc_net_842 ) , .p827 ( optlc_net_843 ) ,
+ .p828 ( optlc_net_844 ) , .p829 ( optlc_net_845 ) ,
+ .p830 ( optlc_net_846 ) , .p831 ( optlc_net_847 ) ,
+ .p832 ( optlc_net_848 ) , .p833 ( optlc_net_849 ) ,
+ .p834 ( optlc_net_850 ) , .p835 ( optlc_net_851 ) ,
+ .p836 ( optlc_net_852 ) , .p837 ( optlc_net_853 ) ,
+ .p838 ( optlc_net_854 ) , .p839 ( optlc_net_855 ) ,
+ .p840 ( optlc_net_856 ) , .p841 ( optlc_net_857 ) ,
+ .p842 ( optlc_net_858 ) , .p843 ( optlc_net_859 ) ,
+ .p844 ( optlc_net_860 ) , .p845 ( optlc_net_861 ) ,
+ .p846 ( optlc_net_862 ) , .p847 ( optlc_net_863 ) ,
+ .p848 ( optlc_net_864 ) , .p849 ( optlc_net_865 ) ,
+ .p850 ( optlc_net_866 ) , .p851 ( optlc_net_867 ) ,
+ .p852 ( optlc_net_868 ) , .p853 ( optlc_net_869 ) ,
+ .p854 ( optlc_net_870 ) , .p855 ( optlc_net_871 ) ,
+ .p856 ( optlc_net_872 ) , .p857 ( optlc_net_873 ) ,
+ .p858 ( optlc_net_874 ) , .p859 ( optlc_net_875 ) ,
+ .p860 ( optlc_net_876 ) , .p861 ( optlc_net_877 ) ,
+ .p862 ( optlc_net_878 ) , .p863 ( optlc_net_879 ) ,
+ .p864 ( optlc_net_880 ) , .p865 ( optlc_net_881 ) ,
+ .p866 ( optlc_net_882 ) , .p867 ( optlc_net_883 ) ,
+ .p868 ( optlc_net_884 ) , .p869 ( optlc_net_885 ) ,
+ .p870 ( optlc_net_886 ) , .p871 ( optlc_net_887 ) ,
+ .p872 ( optlc_net_888 ) , .p873 ( optlc_net_889 ) ,
+ .p874 ( optlc_net_890 ) , .p875 ( optlc_net_891 ) ,
+ .p876 ( optlc_net_892 ) , .p877 ( optlc_net_893 ) ,
+ .p878 ( optlc_net_894 ) , .p879 ( optlc_net_895 ) ,
+ .p880 ( optlc_net_896 ) , .p881 ( optlc_net_897 ) ,
+ .p882 ( optlc_net_898 ) , .p883 ( optlc_net_899 ) ,
+ .p884 ( optlc_net_900 ) , .p885 ( optlc_net_901 ) ,
+ .p886 ( optlc_net_902 ) , .p887 ( optlc_net_903 ) ,
+ .p888 ( optlc_net_904 ) , .p889 ( optlc_net_905 ) ,
+ .p890 ( optlc_net_906 ) , .p891 ( optlc_net_907 ) ,
+ .p892 ( optlc_net_908 ) , .p893 ( optlc_net_909 ) ,
+ .p894 ( optlc_net_910 ) , .p895 ( optlc_net_911 ) ,
+ .p896 ( optlc_net_912 ) , .p897 ( optlc_net_913 ) ,
+ .p898 ( optlc_net_914 ) , .p899 ( optlc_net_915 ) ,
+ .p900 ( optlc_net_916 ) , .p901 ( optlc_net_917 ) ,
+ .p902 ( optlc_net_918 ) , .p903 ( optlc_net_919 ) ,
+ .p904 ( optlc_net_920 ) , .p905 ( optlc_net_921 ) ,
+ .p906 ( optlc_net_922 ) , .p907 ( optlc_net_923 ) ,
+ .p908 ( optlc_net_924 ) , .p909 ( optlc_net_925 ) ,
+ .p910 ( optlc_net_926 ) , .p911 ( optlc_net_927 ) ,
+ .p912 ( optlc_net_928 ) , .p913 ( optlc_net_929 ) ,
+ .p914 ( optlc_net_930 ) , .p915 ( optlc_net_931 ) ,
+ .p916 ( optlc_net_932 ) , .p917 ( optlc_net_933 ) ,
+ .p918 ( optlc_net_934 ) , .p919 ( optlc_net_935 ) ,
+ .p920 ( optlc_net_936 ) , .p921 ( optlc_net_937 ) ,
+ .p922 ( optlc_net_938 ) , .p923 ( optlc_net_939 ) ,
+ .p924 ( optlc_net_940 ) , .p925 ( optlc_net_941 ) ,
+ .p926 ( optlc_net_942 ) , .p927 ( optlc_net_943 ) ,
+ .p928 ( optlc_net_944 ) , .p929 ( optlc_net_945 ) ,
+ .p930 ( optlc_net_946 ) , .p931 ( optlc_net_947 ) ,
+ .p932 ( optlc_net_948 ) , .p933 ( optlc_net_949 ) ,
+ .p934 ( optlc_net_950 ) , .p935 ( optlc_net_951 ) ,
+ .p936 ( optlc_net_952 ) , .p937 ( optlc_net_953 ) ,
+ .p938 ( optlc_net_954 ) , .p939 ( optlc_net_955 ) ,
+ .p940 ( optlc_net_956 ) , .p941 ( optlc_net_957 ) ,
+ .p942 ( optlc_net_958 ) , .p943 ( optlc_net_959 ) ,
+ .p944 ( optlc_net_960 ) , .p945 ( optlc_net_961 ) ,
+ .p946 ( optlc_net_962 ) , .p947 ( optlc_net_963 ) ,
+ .p948 ( optlc_net_964 ) , .p949 ( optlc_net_965 ) ,
+ .p950 ( optlc_net_966 ) , .p951 ( optlc_net_967 ) ,
+ .p952 ( optlc_net_968 ) , .p953 ( optlc_net_969 ) ,
+ .p954 ( optlc_net_970 ) , .p955 ( optlc_net_971 ) ,
+ .p956 ( optlc_net_972 ) , .p957 ( optlc_net_973 ) ,
+ .p958 ( optlc_net_974 ) , .p959 ( optlc_net_975 ) ,
+ .p960 ( optlc_net_976 ) , .p961 ( optlc_net_977 ) ,
+ .p962 ( optlc_net_978 ) , .p963 ( optlc_net_979 ) ,
+ .p964 ( optlc_net_980 ) , .p965 ( optlc_net_981 ) ,
+ .p966 ( optlc_net_982 ) , .p967 ( optlc_net_983 ) ,
+ .p968 ( optlc_net_984 ) , .p969 ( optlc_net_985 ) ,
+ .p970 ( optlc_net_986 ) , .p971 ( optlc_net_987 ) ,
+ .p972 ( optlc_net_988 ) , .p973 ( optlc_net_989 ) ,
+ .p974 ( optlc_net_990 ) , .p975 ( optlc_net_991 ) ,
+ .p976 ( optlc_net_992 ) , .p977 ( optlc_net_993 ) ,
+ .p978 ( optlc_net_994 ) , .p979 ( optlc_net_995 ) ,
+ .p980 ( optlc_net_996 ) , .p981 ( optlc_net_997 ) ,
+ .p982 ( optlc_net_998 ) , .p983 ( optlc_net_999 ) ,
+ .p984 ( optlc_net_1000 ) , .p985 ( optlc_net_1001 ) ,
+ .p986 ( optlc_net_1002 ) , .p987 ( optlc_net_1003 ) ,
+ .p988 ( optlc_net_1004 ) , .p989 ( optlc_net_1005 ) ,
+ .p990 ( optlc_net_1006 ) , .p991 ( optlc_net_1007 ) ,
+ .p992 ( optlc_net_1008 ) , .p993 ( optlc_net_1009 ) ,
+ .p994 ( optlc_net_1010 ) , .p995 ( optlc_net_1011 ) ,
+ .p996 ( optlc_net_1012 ) , .p997 ( optlc_net_1013 ) ,
+ .p998 ( optlc_net_1014 ) , .p999 ( optlc_net_1015 ) ,
+ .p1000 ( optlc_net_1016 ) , .p1001 ( optlc_net_1017 ) ,
+ .p1002 ( optlc_net_1018 ) , .p1003 ( optlc_net_1019 ) ,
+ .p1004 ( optlc_net_1020 ) , .p1005 ( optlc_net_1021 ) ,
+ .p1006 ( optlc_net_1022 ) , .p1007 ( optlc_net_1023 ) ,
+ .p1008 ( optlc_net_1024 ) , .p1009 ( optlc_net_1025 ) ,
+ .p1010 ( optlc_net_1026 ) , .p1011 ( optlc_net_1027 ) ,
+ .p1012 ( optlc_net_1028 ) , .p1013 ( optlc_net_1029 ) ,
+ .p1014 ( optlc_net_1030 ) , .p1015 ( optlc_net_1031 ) ,
+ .p1016 ( optlc_net_1032 ) , .p1017 ( optlc_net_1033 ) ,
+ .p1018 ( optlc_net_1034 ) , .p1019 ( optlc_net_1035 ) ,
+ .p1020 ( optlc_net_1036 ) , .p1021 ( optlc_net_1037 ) ,
+ .p1022 ( optlc_net_1038 ) , .p1023 ( optlc_net_1039 ) ,
+ .p1024 ( optlc_net_1040 ) , .p1025 ( optlc_net_1041 ) ,
+ .p1026 ( optlc_net_1042 ) , .p1027 ( optlc_net_1043 ) ,
+ .p1028 ( optlc_net_1044 ) , .p1029 ( optlc_net_1045 ) ,
+ .p1030 ( optlc_net_1046 ) , .p1031 ( optlc_net_1047 ) ,
+ .p1032 ( optlc_net_1048 ) , .p1033 ( optlc_net_1049 ) ,
+ .p1034 ( optlc_net_1050 ) , .p1035 ( optlc_net_1051 ) ,
+ .p1036 ( optlc_net_1052 ) , .p1037 ( optlc_net_1053 ) ,
+ .p1038 ( optlc_net_1054 ) , .p1039 ( optlc_net_1055 ) ,
+ .p1040 ( optlc_net_1056 ) , .p1041 ( optlc_net_1057 ) ,
+ .p1042 ( optlc_net_1058 ) , .p1043 ( optlc_net_1059 ) ,
+ .p1044 ( optlc_net_1060 ) , .p1045 ( optlc_net_1061 ) ,
+ .p1046 ( optlc_net_1062 ) , .p1047 ( optlc_net_1063 ) ,
+ .p1048 ( optlc_net_1064 ) , .p1049 ( optlc_net_1065 ) ,
+ .p1050 ( optlc_net_1066 ) , .p1051 ( optlc_net_1067 ) ,
+ .p1052 ( optlc_net_1068 ) , .p1053 ( optlc_net_1069 ) ,
+ .p1054 ( optlc_net_1070 ) , .p1055 ( optlc_net_1071 ) ,
+ .p1056 ( optlc_net_1072 ) , .p1057 ( optlc_net_1073 ) ,
+ .p1058 ( optlc_net_1074 ) , .p1059 ( optlc_net_1075 ) ,
+ .p1060 ( optlc_net_1076 ) , .p1061 ( optlc_net_1077 ) ,
+ .p1062 ( optlc_net_1078 ) , .p1063 ( optlc_net_1079 ) ,
+ .p1064 ( optlc_net_1080 ) , .p1065 ( optlc_net_1081 ) ,
+ .p1066 ( optlc_net_1082 ) , .p1067 ( optlc_net_1083 ) ,
+ .p1068 ( optlc_net_1084 ) , .p1069 ( optlc_net_1085 ) ,
+ .p1070 ( optlc_net_1086 ) , .p1071 ( optlc_net_1087 ) ,
+ .p1072 ( optlc_net_1088 ) , .p1073 ( optlc_net_1089 ) ,
+ .p1074 ( optlc_net_1090 ) , .p1075 ( optlc_net_1091 ) ,
+ .p1076 ( optlc_net_1092 ) , .p1077 ( optlc_net_1093 ) ,
+ .p1078 ( optlc_net_1094 ) , .p1079 ( optlc_net_1095 ) ,
+ .p1080 ( optlc_net_1096 ) , .p1081 ( optlc_net_1097 ) ,
+ .p1082 ( optlc_net_1098 ) , .p1083 ( optlc_net_1099 ) ,
+ .p1084 ( optlc_net_1100 ) , .p1085 ( optlc_net_1101 ) ,
+ .p1086 ( optlc_net_1102 ) , .p1087 ( optlc_net_1103 ) ,
+ .p1088 ( optlc_net_1104 ) , .p1089 ( optlc_net_1105 ) ,
+ .p1090 ( optlc_net_1106 ) , .p1091 ( optlc_net_1107 ) ,
+ .p1092 ( optlc_net_1108 ) , .p1093 ( optlc_net_1109 ) ,
+ .p1094 ( optlc_net_1110 ) , .p1095 ( optlc_net_1111 ) ,
+ .p1096 ( optlc_net_1112 ) , .p1097 ( optlc_net_1113 ) ,
+ .p1098 ( optlc_net_1114 ) , .p1099 ( optlc_net_1115 ) ,
+ .p1100 ( optlc_net_1116 ) , .p1101 ( optlc_net_1117 ) ,
+ .p1102 ( optlc_net_1118 ) , .p1103 ( optlc_net_1119 ) ,
+ .p1104 ( optlc_net_1120 ) , .p1105 ( optlc_net_1121 ) ,
+ .p1106 ( optlc_net_1122 ) , .p1107 ( optlc_net_1123 ) ,
+ .p1108 ( optlc_net_1124 ) , .p1109 ( optlc_net_1125 ) ,
+ .p1110 ( optlc_net_1126 ) , .p1111 ( optlc_net_1127 ) ,
+ .p1112 ( optlc_net_1128 ) , .p1113 ( optlc_net_1129 ) ,
+ .p1114 ( optlc_net_1130 ) , .p1115 ( optlc_net_1131 ) ,
+ .p1116 ( optlc_net_1132 ) , .p1117 ( optlc_net_1133 ) ,
+ .p1118 ( optlc_net_1134 ) , .p1119 ( optlc_net_1135 ) ,
+ .p1120 ( optlc_net_1136 ) , .p1121 ( optlc_net_1137 ) ,
+ .p1122 ( optlc_net_1138 ) , .p1123 ( optlc_net_1139 ) ,
+ .p1124 ( optlc_net_1140 ) , .p1125 ( optlc_net_1141 ) ,
+ .p1126 ( optlc_net_1142 ) , .p1127 ( optlc_net_1143 ) ,
+ .p1128 ( optlc_net_1144 ) , .p1129 ( optlc_net_1145 ) ,
+ .p1130 ( optlc_net_1146 ) , .p1131 ( optlc_net_1147 ) ,
+ .p1132 ( optlc_net_1148 ) , .p1133 ( optlc_net_1149 ) ,
+ .p1134 ( optlc_net_1150 ) , .p1135 ( optlc_net_1151 ) ,
+ .p1136 ( optlc_net_1152 ) , .p1137 ( optlc_net_1153 ) ,
+ .p1138 ( optlc_net_1154 ) , .p1139 ( optlc_net_1155 ) ,
+ .p1140 ( optlc_net_1156 ) , .p1141 ( optlc_net_1157 ) ,
+ .p1142 ( optlc_net_1158 ) , .p1143 ( optlc_net_1159 ) ,
+ .p1144 ( optlc_net_1160 ) , .p1145 ( optlc_net_1161 ) ,
+ .p1146 ( optlc_net_1162 ) , .p1147 ( optlc_net_1163 ) ,
+ .p1148 ( optlc_net_1164 ) , .p1149 ( optlc_net_1165 ) ,
+ .p1150 ( optlc_net_1166 ) , .p1151 ( optlc_net_1167 ) ,
+ .p1152 ( optlc_net_1168 ) , .p1153 ( optlc_net_1169 ) ,
+ .p1154 ( optlc_net_1170 ) , .p1155 ( optlc_net_1171 ) ,
+ .p1156 ( optlc_net_1172 ) , .p1157 ( optlc_net_1173 ) ,
+ .p1158 ( optlc_net_1174 ) , .p1159 ( optlc_net_1175 ) ,
+ .p1160 ( optlc_net_1176 ) , .p1161 ( optlc_net_1177 ) ,
+ .p1162 ( optlc_net_1178 ) , .p1163 ( optlc_net_1179 ) ,
+ .p1164 ( optlc_net_1180 ) , .p1165 ( optlc_net_1181 ) ,
+ .p1166 ( optlc_net_1182 ) , .p1167 ( optlc_net_1183 ) ,
+ .p1168 ( optlc_net_1184 ) , .p1169 ( optlc_net_1185 ) ,
+ .p1170 ( optlc_net_1186 ) , .p1171 ( optlc_net_1187 ) ,
+ .p1172 ( optlc_net_1188 ) , .p1173 ( optlc_net_1189 ) ,
+ .p1174 ( optlc_net_1190 ) , .p1175 ( optlc_net_1191 ) ,
+ .p1176 ( optlc_net_1192 ) , .p1177 ( optlc_net_1193 ) ,
+ .p1178 ( optlc_net_1194 ) , .p1179 ( optlc_net_1195 ) ,
+ .p1180 ( optlc_net_1196 ) , .p1181 ( optlc_net_1197 ) ,
+ .p1182 ( optlc_net_1198 ) , .p1183 ( optlc_net_1199 ) ,
+ .p1184 ( optlc_net_1200 ) , .p1185 ( optlc_net_1201 ) ,
+ .p1186 ( optlc_net_1202 ) , .p1187 ( optlc_net_1203 ) ,
+ .p1188 ( optlc_net_1204 ) , .p1189 ( optlc_net_1205 ) ,
+ .p1190 ( optlc_net_1206 ) , .p1191 ( optlc_net_1207 ) ,
+ .p1192 ( optlc_net_1208 ) , .p1193 ( optlc_net_1209 ) ,
+ .p1194 ( optlc_net_1210 ) , .p1195 ( optlc_net_1211 ) ,
+ .p1196 ( optlc_net_1212 ) , .p1197 ( optlc_net_1213 ) ,
+ .p1198 ( optlc_net_1214 ) , .p1199 ( optlc_net_1215 ) ,
+ .p1200 ( optlc_net_1216 ) , .p1201 ( optlc_net_1217 ) ,
+ .p1202 ( optlc_net_1218 ) , .p1203 ( optlc_net_1219 ) ,
+ .p1204 ( optlc_net_1220 ) , .p1205 ( optlc_net_1221 ) ,
+ .p1206 ( optlc_net_1222 ) , .p1207 ( optlc_net_1223 ) ,
+ .p1208 ( optlc_net_1224 ) , .p1209 ( optlc_net_1225 ) ,
+ .p1210 ( optlc_net_1226 ) , .p1211 ( optlc_net_1227 ) ,
+ .p1212 ( optlc_net_1228 ) , .p1213 ( optlc_net_1229 ) ,
+ .p1214 ( optlc_net_1230 ) , .p1215 ( optlc_net_1231 ) ,
+ .p1216 ( optlc_net_1232 ) , .p1217 ( optlc_net_1233 ) ,
+ .p1218 ( optlc_net_1234 ) , .p1219 ( optlc_net_1235 ) ,
+ .p1220 ( optlc_net_1236 ) , .p1221 ( optlc_net_1237 ) ,
+ .p1222 ( optlc_net_1238 ) , .p1223 ( optlc_net_1239 ) ,
+ .p1224 ( optlc_net_1240 ) , .p1225 ( optlc_net_1241 ) ,
+ .p1226 ( optlc_net_1242 ) , .p1227 ( optlc_net_1243 ) ,
+ .p1228 ( optlc_net_1244 ) , .p1229 ( optlc_net_1245 ) ,
+ .p1230 ( optlc_net_1246 ) , .p1231 ( optlc_net_1247 ) ,
+ .p1232 ( optlc_net_1248 ) , .p1233 ( optlc_net_1249 ) ,
+ .p1234 ( optlc_net_1250 ) , .p1235 ( optlc_net_1251 ) ,
+ .p1236 ( optlc_net_1252 ) , .p1237 ( optlc_net_1253 ) ,
+ .p1238 ( optlc_net_1254 ) , .p1239 ( optlc_net_1255 ) ,
+ .p1240 ( optlc_net_1256 ) , .p1241 ( optlc_net_1257 ) ,
+ .p1242 ( optlc_net_1258 ) , .p1243 ( optlc_net_1259 ) ,
+ .p1244 ( optlc_net_1260 ) , .p1245 ( optlc_net_1261 ) ,
+ .p1246 ( optlc_net_1262 ) , .p1247 ( optlc_net_1263 ) ,
+ .p1248 ( optlc_net_1264 ) , .p1249 ( optlc_net_1265 ) ,
+ .p1250 ( optlc_net_1266 ) , .p1251 ( optlc_net_1267 ) ,
+ .p1252 ( optlc_net_1268 ) , .p1253 ( optlc_net_1269 ) ,
+ .p1254 ( optlc_net_1270 ) , .p1255 ( optlc_net_1271 ) ,
+ .p1256 ( optlc_net_1272 ) , .p1257 ( optlc_net_1273 ) ,
+ .p1258 ( optlc_net_1274 ) , .p1259 ( optlc_net_1275 ) ,
+ .p1260 ( optlc_net_1276 ) , .p1261 ( optlc_net_1277 ) ,
+ .p1262 ( optlc_net_1278 ) , .p1263 ( optlc_net_1279 ) ,
+ .p1264 ( optlc_net_1280 ) , .p1265 ( optlc_net_1281 ) ,
+ .p1266 ( optlc_net_1282 ) , .p1267 ( optlc_net_1283 ) ,
+ .p1268 ( optlc_net_1284 ) , .p1269 ( optlc_net_1285 ) ,
+ .p1270 ( optlc_net_1286 ) , .p1271 ( optlc_net_1287 ) ,
+ .p1272 ( optlc_net_1288 ) , .p1273 ( optlc_net_1289 ) ,
+ .p1274 ( optlc_net_1290 ) , .p1275 ( optlc_net_1291 ) ,
+ .p1276 ( optlc_net_1292 ) , .p1277 ( optlc_net_1293 ) ,
+ .p1278 ( optlc_net_1294 ) , .p1279 ( optlc_net_1295 ) ,
+ .p1280 ( optlc_net_1296 ) , .p1281 ( optlc_net_1297 ) ,
+ .p1282 ( optlc_net_1298 ) , .p1283 ( optlc_net_1299 ) ,
+ .p1284 ( optlc_net_1300 ) , .p1285 ( optlc_net_1301 ) ,
+ .p1286 ( optlc_net_1302 ) , .p1287 ( optlc_net_1303 ) ,
+ .p1288 ( optlc_net_1304 ) , .p1289 ( optlc_net_1305 ) ,
+ .p1290 ( optlc_net_1306 ) , .p1291 ( optlc_net_1307 ) ,
+ .p1292 ( optlc_net_1308 ) , .p1293 ( optlc_net_1309 ) ,
+ .p1294 ( optlc_net_1310 ) , .p1295 ( optlc_net_1311 ) ,
+ .p1296 ( optlc_net_1312 ) , .p1297 ( optlc_net_1313 ) ,
+ .p1298 ( optlc_net_1314 ) , .p1299 ( optlc_net_1315 ) ,
+ .p1300 ( optlc_net_1316 ) , .p1301 ( optlc_net_1317 ) ,
+ .p1302 ( optlc_net_1318 ) , .p1303 ( optlc_net_1319 ) ,
+ .p1304 ( optlc_net_1320 ) , .p1305 ( optlc_net_1321 ) ,
+ .p1306 ( optlc_net_1322 ) , .p1307 ( optlc_net_1323 ) ,
+ .p1308 ( optlc_net_1324 ) , .p1309 ( optlc_net_1325 ) ,
+ .p1310 ( optlc_net_1326 ) , .p1311 ( optlc_net_1327 ) ,
+ .p1312 ( optlc_net_1328 ) , .p1313 ( optlc_net_1329 ) ,
+ .p1314 ( optlc_net_1330 ) , .p1315 ( optlc_net_1331 ) ,
+ .p1316 ( optlc_net_1332 ) , .p1317 ( optlc_net_1333 ) ,
+ .p1318 ( optlc_net_1334 ) , .p1319 ( optlc_net_1335 ) ,
+ .p1320 ( optlc_net_1336 ) , .p1321 ( optlc_net_1337 ) ,
+ .p1322 ( optlc_net_1338 ) , .p1323 ( optlc_net_1339 ) ,
+ .p1324 ( optlc_net_1340 ) , .p1325 ( optlc_net_1341 ) ,
+ .p1326 ( optlc_net_1342 ) , .p1327 ( optlc_net_1343 ) ,
+ .p1328 ( optlc_net_1344 ) , .p1329 ( optlc_net_1345 ) ,
+ .p1330 ( optlc_net_1346 ) , .p1331 ( optlc_net_1347 ) ,
+ .p1332 ( optlc_net_1348 ) , .p1333 ( optlc_net_1349 ) ,
+ .p1334 ( optlc_net_1350 ) , .p1335 ( optlc_net_1351 ) ,
+ .p1336 ( optlc_net_1352 ) , .p1337 ( optlc_net_1353 ) ,
+ .p1338 ( optlc_net_1354 ) , .p1339 ( optlc_net_1355 ) ,
+ .p1340 ( optlc_net_1356 ) , .p1341 ( optlc_net_1357 ) ,
+ .p1342 ( optlc_net_1358 ) , .p1343 ( optlc_net_1359 ) ,
+ .p1344 ( optlc_net_1360 ) , .p1345 ( optlc_net_1361 ) ,
+ .p1346 ( optlc_net_1362 ) , .p1347 ( optlc_net_1363 ) ,
+ .p1348 ( optlc_net_1364 ) , .p1349 ( optlc_net_1365 ) ,
+ .p1350 ( optlc_net_1366 ) , .p1351 ( optlc_net_1367 ) ,
+ .p1352 ( optlc_net_1368 ) , .p1353 ( optlc_net_1369 ) ,
+ .p1354 ( optlc_net_1370 ) , .p1355 ( optlc_net_1371 ) ,
+ .p1356 ( optlc_net_1372 ) , .p1357 ( optlc_net_1373 ) ,
+ .p1358 ( optlc_net_1374 ) , .p1359 ( optlc_net_1375 ) ,
+ .p1360 ( optlc_net_1376 ) , .p1361 ( optlc_net_1377 ) ,
+ .p1362 ( optlc_net_1378 ) , .p1363 ( optlc_net_1379 ) ,
+ .p1364 ( optlc_net_1380 ) , .p1365 ( optlc_net_1381 ) ,
+ .p1366 ( optlc_net_1382 ) , .p1367 ( optlc_net_1383 ) ,
+ .p1368 ( optlc_net_1384 ) , .p1369 ( optlc_net_1385 ) ,
+ .p1370 ( optlc_net_1386 ) , .p1371 ( optlc_net_1387 ) ,
+ .p1372 ( optlc_net_1388 ) , .p1373 ( optlc_net_1389 ) ,
+ .p1374 ( optlc_net_1390 ) , .p1375 ( optlc_net_1391 ) ,
+ .p1376 ( optlc_net_1392 ) , .p1377 ( optlc_net_1393 ) ,
+ .p1378 ( optlc_net_1394 ) , .p1379 ( optlc_net_1395 ) ,
+ .p1380 ( optlc_net_1396 ) , .p1381 ( optlc_net_1397 ) ,
+ .p1382 ( optlc_net_1398 ) , .p1383 ( optlc_net_1399 ) ,
+ .p1384 ( optlc_net_1400 ) , .p1385 ( optlc_net_1401 ) ,
+ .p1386 ( optlc_net_1402 ) , .p1387 ( optlc_net_1403 ) ,
+ .p1388 ( optlc_net_1404 ) , .p1389 ( optlc_net_1405 ) ,
+ .p1390 ( optlc_net_1406 ) , .p1391 ( optlc_net_1407 ) ,
+ .p1392 ( optlc_net_1408 ) , .p1393 ( optlc_net_1409 ) ,
+ .p1394 ( optlc_net_1410 ) , .p1395 ( optlc_net_1411 ) ,
+ .p1396 ( optlc_net_1412 ) , .p1397 ( optlc_net_1413 ) ,
+ .p1398 ( optlc_net_1414 ) , .p1399 ( optlc_net_1415 ) ,
+ .p1400 ( optlc_net_1416 ) , .p1401 ( optlc_net_1417 ) ,
+ .p1402 ( optlc_net_1418 ) , .p1403 ( optlc_net_1419 ) ,
+ .p1404 ( optlc_net_1420 ) , .p1405 ( optlc_net_1421 ) ,
+ .p1406 ( optlc_net_1422 ) , .p1407 ( optlc_net_1423 ) ,
+ .p1408 ( optlc_net_1424 ) , .p1409 ( optlc_net_1425 ) ,
+ .p1410 ( optlc_net_1426 ) , .p1411 ( optlc_net_1427 ) ,
+ .p1412 ( optlc_net_1428 ) , .p1413 ( optlc_net_1429 ) ,
+ .p1414 ( optlc_net_1430 ) , .p1415 ( optlc_net_1431 ) ,
+ .p1416 ( optlc_net_1432 ) , .p1417 ( optlc_net_1433 ) ,
+ .p1418 ( optlc_net_1434 ) , .p1419 ( optlc_net_1435 ) ,
+ .p1420 ( optlc_net_1436 ) , .p1421 ( optlc_net_1437 ) ,
+ .p1422 ( optlc_net_1438 ) , .p1423 ( optlc_net_1439 ) ,
+ .p1424 ( optlc_net_1440 ) , .p1425 ( optlc_net_1441 ) ,
+ .p1426 ( optlc_net_1442 ) , .p1427 ( optlc_net_1443 ) ,
+ .p1428 ( optlc_net_1444 ) , .p1429 ( optlc_net_1445 ) ,
+ .p1430 ( optlc_net_1446 ) , .p1431 ( optlc_net_1447 ) ,
+ .p1432 ( optlc_net_1448 ) , .p1433 ( optlc_net_1449 ) ,
+ .p1434 ( optlc_net_1450 ) , .p1435 ( optlc_net_1451 ) ,
+ .p1436 ( optlc_net_1452 ) , .p1437 ( optlc_net_1453 ) ,
+ .p1438 ( optlc_net_1454 ) , .p1439 ( optlc_net_1455 ) ,
+ .p1440 ( optlc_net_1456 ) , .p1441 ( optlc_net_1457 ) ,
+ .p1442 ( optlc_net_1458 ) , .p1443 ( optlc_net_1459 ) ,
+ .p1444 ( optlc_net_1460 ) , .p1445 ( optlc_net_1461 ) ,
+ .p1446 ( optlc_net_1462 ) , .p1447 ( optlc_net_1463 ) ,
+ .p1448 ( optlc_net_1464 ) , .p1449 ( optlc_net_1465 ) ,
+ .p1450 ( optlc_net_1466 ) , .p1451 ( optlc_net_1467 ) ,
+ .p1452 ( optlc_net_1468 ) , .p1453 ( optlc_net_1469 ) ,
+ .p1454 ( optlc_net_1470 ) , .p1455 ( optlc_net_1471 ) ,
+ .p1456 ( optlc_net_1472 ) , .p1457 ( optlc_net_1473 ) ,
+ .p1458 ( optlc_net_1474 ) , .p1459 ( optlc_net_1475 ) ,
+ .p1460 ( optlc_net_1476 ) , .p1461 ( optlc_net_1477 ) ,
+ .p1462 ( optlc_net_1478 ) , .p1463 ( optlc_net_1479 ) ,
+ .p1464 ( optlc_net_1480 ) , .p1465 ( optlc_net_1481 ) ,
+ .p1466 ( optlc_net_1482 ) , .p1467 ( optlc_net_1483 ) ,
+ .p1468 ( optlc_net_1484 ) , .p1469 ( optlc_net_1485 ) ,
+ .p1470 ( optlc_net_1486 ) , .p1471 ( optlc_net_1487 ) ,
+ .p1472 ( optlc_net_1488 ) , .p1473 ( optlc_net_1489 ) ,
+ .p1474 ( optlc_net_1490 ) , .p1475 ( optlc_net_1491 ) ,
+ .p1476 ( optlc_net_1492 ) , .p1477 ( optlc_net_1493 ) ,
+ .p1478 ( optlc_net_1494 ) , .p1479 ( optlc_net_1495 ) ,
+ .p1480 ( optlc_net_1496 ) , .p1481 ( optlc_net_1497 ) ,
+ .p1482 ( optlc_net_1498 ) , .p1483 ( optlc_net_1499 ) ,
+ .p1484 ( optlc_net_1500 ) , .p1485 ( optlc_net_1501 ) ,
+ .p1486 ( optlc_net_1502 ) , .p1487 ( optlc_net_1503 ) ,
+ .p1488 ( optlc_net_1504 ) , .p1489 ( optlc_net_1505 ) ,
+ .p1490 ( optlc_net_1506 ) , .p1491 ( optlc_net_1507 ) ,
+ .p1492 ( optlc_net_1508 ) , .p1493 ( optlc_net_1509 ) ,
+ .p1494 ( optlc_net_1510 ) , .p1495 ( optlc_net_1511 ) ,
+ .p1496 ( optlc_net_1512 ) , .p1497 ( optlc_net_1513 ) ,
+ .p1498 ( optlc_net_1514 ) , .p1499 ( optlc_net_1515 ) ,
+ .p1500 ( optlc_net_1516 ) , .p1501 ( optlc_net_1517 ) ,
+ .p1502 ( optlc_net_1518 ) , .p1503 ( optlc_net_1519 ) ,
+ .p1504 ( optlc_net_1520 ) , .p1505 ( optlc_net_1521 ) ,
+ .p1506 ( optlc_net_1522 ) , .p1507 ( optlc_net_1523 ) ,
+ .p1508 ( optlc_net_1524 ) , .p1509 ( optlc_net_1525 ) ,
+ .p1510 ( optlc_net_1526 ) , .p1511 ( optlc_net_1527 ) ,
+ .p1512 ( optlc_net_1528 ) , .p1513 ( optlc_net_1529 ) ,
+ .p1514 ( optlc_net_1530 ) , .p1515 ( optlc_net_1531 ) ,
+ .p1516 ( optlc_net_1532 ) , .p1517 ( optlc_net_1533 ) ,
+ .p1518 ( optlc_net_1534 ) , .p1519 ( optlc_net_1535 ) ,
+ .p1520 ( optlc_net_1536 ) , .p1521 ( optlc_net_1537 ) ,
+ .p1522 ( optlc_net_1538 ) , .p1523 ( optlc_net_1539 ) ,
+ .p1524 ( optlc_net_1540 ) , .p1525 ( optlc_net_1541 ) ,
+ .p1526 ( optlc_net_1542 ) , .p1527 ( optlc_net_1543 ) ,
+ .p1528 ( optlc_net_1544 ) , .p1529 ( optlc_net_1545 ) ,
+ .p1530 ( optlc_net_1546 ) , .p1531 ( optlc_net_1547 ) ,
+ .p1532 ( optlc_net_1548 ) , .p1533 ( optlc_net_1549 ) ,
+ .p1534 ( optlc_net_1550 ) , .p1535 ( optlc_net_1551 ) ,
+ .p1536 ( optlc_net_1552 ) , .p1537 ( optlc_net_1553 ) ,
+ .p1538 ( optlc_net_1554 ) , .p1539 ( optlc_net_1555 ) ,
+ .p1540 ( optlc_net_1556 ) , .p1541 ( optlc_net_1557 ) ,
+ .p1542 ( optlc_net_1558 ) , .p1543 ( optlc_net_1559 ) ,
+ .p1544 ( optlc_net_1560 ) , .p1545 ( optlc_net_1561 ) ,
+ .p1546 ( optlc_net_1562 ) , .p1547 ( optlc_net_1563 ) ,
+ .p1548 ( optlc_net_1564 ) , .p1549 ( optlc_net_1565 ) ,
+ .p1550 ( optlc_net_1566 ) , .p1551 ( optlc_net_1567 ) ,
+ .p1552 ( optlc_net_1568 ) , .p1553 ( optlc_net_1569 ) ,
+ .p1554 ( optlc_net_1570 ) , .p1555 ( optlc_net_1571 ) ,
+ .p1556 ( optlc_net_1572 ) , .p1557 ( optlc_net_1573 ) ,
+ .p1558 ( optlc_net_1574 ) , .p1559 ( optlc_net_1575 ) ,
+ .p1560 ( optlc_net_1576 ) , .p1561 ( optlc_net_1577 ) ,
+ .p1562 ( optlc_net_1578 ) , .p1563 ( optlc_net_1579 ) ,
+ .p1564 ( optlc_net_1580 ) , .p1565 ( optlc_net_1581 ) ,
+ .p1566 ( optlc_net_1582 ) , .p1567 ( optlc_net_1583 ) ,
+ .p1568 ( optlc_net_1584 ) , .p1569 ( optlc_net_1585 ) ,
+ .p1570 ( optlc_net_1586 ) , .p1571 ( optlc_net_1587 ) ,
+ .p1572 ( optlc_net_1588 ) , .p1573 ( optlc_net_1589 ) ,
+ .p1574 ( optlc_net_1590 ) , .p1575 ( optlc_net_1591 ) ,
+ .p1576 ( optlc_net_1592 ) , .p1577 ( optlc_net_1593 ) ,
+ .p1578 ( optlc_net_1594 ) , .p1579 ( optlc_net_1595 ) ,
+ .p1580 ( optlc_net_1596 ) , .p1581 ( optlc_net_1597 ) ,
+ .p1582 ( optlc_net_1598 ) , .p1583 ( optlc_net_1599 ) ,
+ .p1584 ( optlc_net_1600 ) , .p1585 ( optlc_net_1601 ) ,
+ .p1586 ( optlc_net_1602 ) , .p1587 ( optlc_net_1603 ) ,
+ .p1588 ( optlc_net_1604 ) , .p1589 ( optlc_net_1605 ) ,
+ .p1590 ( optlc_net_1606 ) , .p1591 ( optlc_net_1607 ) ,
+ .p1592 ( optlc_net_1608 ) , .p1593 ( optlc_net_1609 ) ,
+ .p1594 ( optlc_net_1610 ) , .p1595 ( optlc_net_1611 ) ,
+ .p1596 ( optlc_net_1612 ) , .p1597 ( optlc_net_1613 ) ,
+ .p1598 ( optlc_net_1614 ) , .p1599 ( optlc_net_1615 ) ,
+ .p1600 ( optlc_net_1616 ) , .p1601 ( optlc_net_1617 ) ,
+ .p1602 ( optlc_net_1618 ) , .p1603 ( optlc_net_1619 ) ,
+ .p1604 ( optlc_net_1620 ) , .p1605 ( optlc_net_1621 ) ,
+ .p1606 ( optlc_net_1622 ) , .p1607 ( optlc_net_1623 ) ,
+ .p1608 ( optlc_net_1624 ) , .p1609 ( optlc_net_1625 ) ,
+ .p1610 ( optlc_net_1626 ) , .p1611 ( optlc_net_1627 ) ,
+ .p1612 ( optlc_net_1628 ) , .p1613 ( optlc_net_1629 ) ,
+ .p1614 ( optlc_net_1630 ) , .p1615 ( optlc_net_1631 ) ,
+ .p1616 ( optlc_net_1632 ) , .p1617 ( optlc_net_1633 ) ,
+ .p1618 ( optlc_net_1634 ) , .p1619 ( optlc_net_1635 ) ,
+ .p1620 ( optlc_net_1636 ) , .p1621 ( optlc_net_1637 ) ,
+ .p1622 ( optlc_net_1638 ) , .p1623 ( optlc_net_1639 ) ,
+ .p1624 ( optlc_net_1640 ) , .p1625 ( optlc_net_1641 ) ,
+ .p1626 ( optlc_net_1642 ) , .p1627 ( optlc_net_1643 ) ,
+ .p1628 ( optlc_net_1644 ) , .p1629 ( optlc_net_1645 ) ,
+ .p1630 ( optlc_net_1646 ) , .p1631 ( optlc_net_1647 ) ,
+ .p1632 ( optlc_net_1648 ) , .p1633 ( optlc_net_1649 ) ,
+ .p1634 ( optlc_net_1650 ) , .p1635 ( optlc_net_1651 ) ,
+ .p1636 ( optlc_net_1652 ) , .p1637 ( optlc_net_1653 ) ,
+ .p1638 ( optlc_net_1654 ) , .p1639 ( optlc_net_1655 ) ,
+ .p1640 ( optlc_net_1656 ) , .p1641 ( optlc_net_1657 ) ,
+ .p1642 ( optlc_net_1658 ) , .p1643 ( optlc_net_1659 ) ,
+ .p1644 ( optlc_net_1660 ) , .p1645 ( optlc_net_1661 ) ,
+ .p1646 ( optlc_net_1662 ) , .p1647 ( optlc_net_1663 ) ,
+ .p1648 ( optlc_net_1664 ) , .p1649 ( optlc_net_1665 ) ,
+ .p1650 ( optlc_net_1666 ) , .p1651 ( optlc_net_1667 ) ,
+ .p1652 ( optlc_net_1668 ) , .p1653 ( optlc_net_1669 ) ,
+ .p1654 ( optlc_net_1670 ) , .p1655 ( optlc_net_1671 ) ,
+ .p1656 ( optlc_net_1672 ) , .p1657 ( optlc_net_1673 ) ,
+ .p1658 ( optlc_net_1674 ) , .p1659 ( optlc_net_1675 ) ,
+ .p1660 ( optlc_net_1676 ) , .p1661 ( optlc_net_1677 ) ,
+ .p1662 ( optlc_net_1678 ) , .p1663 ( optlc_net_1679 ) ,
+ .p1664 ( optlc_net_1680 ) , .p1665 ( optlc_net_1681 ) ,
+ .p1666 ( optlc_net_1682 ) , .p1667 ( optlc_net_1683 ) ,
+ .p1668 ( optlc_net_1684 ) , .p1669 ( optlc_net_1685 ) ,
+ .p1670 ( optlc_net_1686 ) , .p1671 ( optlc_net_1687 ) ,
+ .p1672 ( optlc_net_1688 ) , .p1673 ( optlc_net_1689 ) ,
+ .p1674 ( optlc_net_1690 ) , .p1675 ( optlc_net_1691 ) ,
+ .p1676 ( optlc_net_1692 ) , .p1677 ( optlc_net_1693 ) ,
+ .p1678 ( optlc_net_1694 ) , .p1679 ( optlc_net_1695 ) ,
+ .p1680 ( optlc_net_1696 ) , .p1681 ( optlc_net_1697 ) ,
+ .p1682 ( optlc_net_1698 ) , .p1683 ( optlc_net_1699 ) ,
+ .p1684 ( optlc_net_1700 ) , .p1685 ( optlc_net_1701 ) ,
+ .p1686 ( optlc_net_1702 ) , .p1687 ( optlc_net_1703 ) ,
+ .p1688 ( optlc_net_1704 ) , .p1689 ( optlc_net_1705 ) ,
+ .p1690 ( optlc_net_1706 ) , .p1691 ( optlc_net_1707 ) ,
+ .p1692 ( optlc_net_1708 ) , .p1693 ( optlc_net_1709 ) ,
+ .p1694 ( optlc_net_1710 ) , .p1695 ( optlc_net_1711 ) ,
+ .p1696 ( optlc_net_1712 ) , .p1697 ( optlc_net_1713 ) ,
+ .p1698 ( optlc_net_1714 ) , .p1699 ( optlc_net_1715 ) ,
+ .p1700 ( optlc_net_1716 ) , .p1701 ( optlc_net_1717 ) ,
+ .p1702 ( optlc_net_1718 ) , .p1703 ( optlc_net_1719 ) ,
+ .p1704 ( optlc_net_1720 ) , .p1705 ( optlc_net_1721 ) ,
+ .p1706 ( optlc_net_1722 ) , .p1707 ( optlc_net_1723 ) ,
+ .p1708 ( optlc_net_1724 ) , .p1709 ( optlc_net_1725 ) ,
+ .p1710 ( optlc_net_1726 ) , .p1711 ( optlc_net_1727 ) ,
+ .p1712 ( optlc_net_1728 ) , .p1713 ( optlc_net_1729 ) ,
+ .p1714 ( optlc_net_1730 ) , .p1715 ( optlc_net_1731 ) ,
+ .p1716 ( optlc_net_1732 ) , .p1717 ( optlc_net_1733 ) ,
+ .p1718 ( optlc_net_1734 ) , .p1719 ( optlc_net_1735 ) ,
+ .p1720 ( optlc_net_1736 ) , .p1721 ( optlc_net_1737 ) ,
+ .p1722 ( optlc_net_1738 ) , .p1723 ( optlc_net_1739 ) ,
+ .p1724 ( optlc_net_1740 ) , .p1725 ( optlc_net_1741 ) ,
+ .p1726 ( optlc_net_1742 ) , .p1727 ( optlc_net_1743 ) ,
+ .p1728 ( optlc_net_1744 ) , .p1729 ( optlc_net_1745 ) ,
+ .p1730 ( optlc_net_1746 ) , .p1731 ( optlc_net_1747 ) ,
+ .p1732 ( optlc_net_1748 ) , .p1733 ( optlc_net_1749 ) ,
+ .p1734 ( optlc_net_1750 ) , .p1735 ( optlc_net_1751 ) ,
+ .p1736 ( optlc_net_1752 ) , .p1737 ( optlc_net_1753 ) ,
+ .p1738 ( optlc_net_1754 ) , .p1739 ( optlc_net_1755 ) ,
+ .p1740 ( optlc_net_1756 ) , .p1741 ( optlc_net_1757 ) ,
+ .p1742 ( optlc_net_1758 ) , .p1743 ( optlc_net_1759 ) ,
+ .p1744 ( optlc_net_1760 ) , .p1745 ( optlc_net_1761 ) ,
+ .p1746 ( optlc_net_1762 ) , .p1747 ( optlc_net_1763 ) ,
+ .p1748 ( optlc_net_1764 ) , .p1749 ( optlc_net_1765 ) ,
+ .p1750 ( optlc_net_1766 ) , .p1751 ( optlc_net_1767 ) ,
+ .p1752 ( optlc_net_1768 ) , .p1753 ( optlc_net_1769 ) ,
+ .p1754 ( optlc_net_1770 ) , .p1755 ( optlc_net_1771 ) ,
+ .p1756 ( optlc_net_1772 ) , .p1757 ( optlc_net_1773 ) ,
+ .p1758 ( optlc_net_1774 ) , .p1759 ( optlc_net_1775 ) ,
+ .p1760 ( optlc_net_1776 ) , .p1761 ( optlc_net_1777 ) ,
+ .p1762 ( optlc_net_1778 ) , .p1763 ( optlc_net_1779 ) ,
+ .p1764 ( optlc_net_1780 ) , .p1765 ( optlc_net_1781 ) ,
+ .p1766 ( optlc_net_1782 ) , .p1767 ( optlc_net_1783 ) ,
+ .p1768 ( optlc_net_1784 ) , .p1769 ( optlc_net_1785 ) ,
+ .p1770 ( optlc_net_1786 ) , .p1771 ( optlc_net_1787 ) ,
+ .p1772 ( optlc_net_1788 ) , .p1773 ( optlc_net_1789 ) ,
+ .p1774 ( optlc_net_1790 ) , .p1775 ( optlc_net_1791 ) ,
+ .p1776 ( optlc_net_1792 ) , .p1777 ( optlc_net_1793 ) ,
+ .p1778 ( optlc_net_1794 ) , .p1779 ( optlc_net_1795 ) ,
+ .p1780 ( optlc_net_1796 ) , .p1781 ( optlc_net_1797 ) ,
+ .p1782 ( optlc_net_1798 ) , .p1783 ( optlc_net_1799 ) ,
+ .p1784 ( optlc_net_1800 ) , .p1785 ( optlc_net_1801 ) ,
+ .p1786 ( optlc_net_1802 ) , .p1787 ( optlc_net_1803 ) ,
+ .p1788 ( optlc_net_1804 ) , .p1789 ( optlc_net_1805 ) ,
+ .p1790 ( optlc_net_1806 ) , .p1791 ( optlc_net_1807 ) ,
+ .p1792 ( optlc_net_1808 ) , .p1793 ( optlc_net_1809 ) ,
+ .p1794 ( optlc_net_1810 ) , .p1795 ( optlc_net_1811 ) ,
+ .p1796 ( optlc_net_1812 ) , .p1797 ( optlc_net_1813 ) ,
+ .p1798 ( optlc_net_1814 ) , .p1799 ( optlc_net_1815 ) ,
+ .p1800 ( optlc_net_1816 ) , .p1801 ( optlc_net_1817 ) ,
+ .p1802 ( optlc_net_1818 ) , .p1803 ( optlc_net_1819 ) ,
+ .p1804 ( optlc_net_1820 ) , .p1805 ( optlc_net_1821 ) ,
+ .p1806 ( optlc_net_1822 ) , .p1807 ( optlc_net_1823 ) ,
+ .p1808 ( optlc_net_1824 ) , .p1809 ( optlc_net_1825 ) ,
+ .p1810 ( optlc_net_1826 ) , .p1811 ( optlc_net_1827 ) ,
+ .p1812 ( optlc_net_1828 ) , .p1813 ( optlc_net_1829 ) ,
+ .p1814 ( optlc_net_1830 ) , .p1815 ( optlc_net_1831 ) ,
+ .p1816 ( optlc_net_1832 ) , .p1817 ( optlc_net_1833 ) ,
+ .p1818 ( optlc_net_1834 ) , .p1819 ( optlc_net_1835 ) ,
+ .p1820 ( optlc_net_1836 ) , .p1821 ( optlc_net_1837 ) ,
+ .p1822 ( optlc_net_1838 ) , .p1823 ( optlc_net_1839 ) ,
+ .p1824 ( optlc_net_1840 ) , .p1825 ( optlc_net_1841 ) ,
+ .p1826 ( optlc_net_1842 ) , .p1827 ( optlc_net_1843 ) ,
+ .p1828 ( optlc_net_1844 ) , .p1829 ( optlc_net_1845 ) ,
+ .p1830 ( optlc_net_1846 ) , .p1831 ( optlc_net_1847 ) ,
+ .p1832 ( optlc_net_1848 ) , .p1833 ( optlc_net_1849 ) ,
+ .p1834 ( optlc_net_1850 ) , .p1835 ( optlc_net_1851 ) ,
+ .p1836 ( optlc_net_1852 ) , .p1837 ( optlc_net_1853 ) ,
+ .p1838 ( optlc_net_1854 ) , .p1839 ( optlc_net_1855 ) ,
+ .p1840 ( optlc_net_1856 ) , .p1841 ( optlc_net_1857 ) ,
+ .p1842 ( optlc_net_1858 ) , .p1843 ( optlc_net_1859 ) ,
+ .p1844 ( optlc_net_1860 ) , .p1845 ( optlc_net_1861 ) ,
+ .p1846 ( optlc_net_1862 ) , .p1847 ( optlc_net_1863 ) ,
+ .p1848 ( optlc_net_1864 ) , .p1849 ( optlc_net_1865 ) ,
+ .p1850 ( optlc_net_1866 ) , .p1851 ( optlc_net_1867 ) ,
+ .p1852 ( optlc_net_1868 ) , .p1853 ( optlc_net_1869 ) ,
+ .p1854 ( optlc_net_1870 ) , .p1855 ( optlc_net_1871 ) ,
+ .p1856 ( optlc_net_1872 ) , .p1857 ( optlc_net_1873 ) ,
+ .p1858 ( optlc_net_1874 ) , .p1859 ( optlc_net_1875 ) ,
+ .p1860 ( optlc_net_1876 ) , .p1861 ( optlc_net_1877 ) ,
+ .p1862 ( optlc_net_1878 ) , .p1863 ( optlc_net_1879 ) ,
+ .p1864 ( optlc_net_1880 ) , .p1865 ( optlc_net_1881 ) ,
+ .p1866 ( optlc_net_1882 ) , .p1867 ( optlc_net_1883 ) ,
+ .p1868 ( optlc_net_1884 ) , .p1869 ( optlc_net_1885 ) ,
+ .p1870 ( optlc_net_1886 ) , .p1871 ( optlc_net_1887 ) ,
+ .p1872 ( optlc_net_1888 ) , .p1873 ( optlc_net_1889 ) ,
+ .p1874 ( optlc_net_1890 ) , .p1875 ( optlc_net_1891 ) ,
+ .p1876 ( optlc_net_1892 ) , .p1877 ( optlc_net_1893 ) ,
+ .p1878 ( optlc_net_1894 ) , .p1879 ( optlc_net_1895 ) ,
+ .p1880 ( optlc_net_1896 ) , .p1881 ( optlc_net_1897 ) ,
+ .p1882 ( optlc_net_1898 ) , .p1883 ( optlc_net_1899 ) ,
+ .p1884 ( optlc_net_1900 ) , .p1885 ( optlc_net_1901 ) ,
+ .p1886 ( optlc_net_1902 ) , .p1887 ( optlc_net_1903 ) ,
+ .p1888 ( optlc_net_1904 ) , .p1889 ( optlc_net_1905 ) ,
+ .p1890 ( optlc_net_1906 ) , .p1891 ( optlc_net_1907 ) ,
+ .p1892 ( optlc_net_1908 ) , .p1893 ( optlc_net_1909 ) ,
+ .p1894 ( optlc_net_1910 ) , .p1895 ( optlc_net_1911 ) ,
+ .p1896 ( optlc_net_1912 ) , .p1897 ( optlc_net_1913 ) ,
+ .p1898 ( optlc_net_1914 ) , .p1899 ( optlc_net_1915 ) ,
+ .p1900 ( optlc_net_1916 ) , .p1901 ( optlc_net_1917 ) ,
+ .p1902 ( optlc_net_1918 ) , .p1903 ( optlc_net_1919 ) ,
+ .p1904 ( optlc_net_1920 ) , .p1905 ( optlc_net_1921 ) ,
+ .p1906 ( optlc_net_1922 ) , .p1907 ( optlc_net_1923 ) ,
+ .p1908 ( optlc_net_1924 ) , .p1909 ( optlc_net_1925 ) ,
+ .p1910 ( optlc_net_1926 ) , .p1911 ( optlc_net_1927 ) ,
+ .p1912 ( optlc_net_1928 ) , .p1913 ( optlc_net_1929 ) ,
+ .p1914 ( optlc_net_1930 ) , .p1915 ( optlc_net_1931 ) ,
+ .p1916 ( optlc_net_1932 ) , .p1917 ( optlc_net_1933 ) ,
+ .p1918 ( optlc_net_1934 ) , .p1919 ( optlc_net_1935 ) ,
+ .p1920 ( optlc_net_1936 ) , .p1921 ( optlc_net_1937 ) ,
+ .p1922 ( optlc_net_1938 ) , .p1923 ( optlc_net_1939 ) ,
+ .p1924 ( optlc_net_1940 ) , .p1925 ( optlc_net_1941 ) ,
+ .p1926 ( optlc_net_1942 ) , .p1927 ( optlc_net_1943 ) ,
+ .p1928 ( optlc_net_1944 ) , .p1929 ( optlc_net_1945 ) ,
+ .p1930 ( optlc_net_1946 ) , .p1931 ( optlc_net_1947 ) ,
+ .p1932 ( optlc_net_1948 ) , .p1933 ( optlc_net_1949 ) ,
+ .p1934 ( optlc_net_1950 ) , .p1935 ( optlc_net_1951 ) ,
+ .p1936 ( optlc_net_1952 ) , .p1937 ( optlc_net_1953 ) ,
+ .p1938 ( optlc_net_1954 ) , .p1939 ( optlc_net_1955 ) ,
+ .p1940 ( optlc_net_1956 ) , .p1941 ( optlc_net_1957 ) ,
+ .p1942 ( optlc_net_1958 ) , .p1943 ( optlc_net_1959 ) ,
+ .p1944 ( optlc_net_1960 ) , .p1945 ( optlc_net_1961 ) ,
+ .p1946 ( optlc_net_1962 ) , .p1947 ( optlc_net_1963 ) ,
+ .p1948 ( optlc_net_1964 ) , .p1949 ( optlc_net_1965 ) ,
+ .p1950 ( optlc_net_1966 ) , .p1951 ( optlc_net_1967 ) ,
+ .p1952 ( optlc_net_1968 ) , .p1953 ( optlc_net_1969 ) ,
+ .p1954 ( optlc_net_1970 ) , .p1955 ( optlc_net_1971 ) ,
+ .p1956 ( optlc_net_1972 ) , .p1957 ( optlc_net_1973 ) ,
+ .p1958 ( optlc_net_1974 ) , .p1959 ( optlc_net_1975 ) ,
+ .p1960 ( optlc_net_1976 ) , .p1961 ( optlc_net_1977 ) ,
+ .p1962 ( optlc_net_1978 ) , .p1963 ( optlc_net_1979 ) ,
+ .p1964 ( optlc_net_1980 ) , .p1965 ( optlc_net_1981 ) ,
+ .p1966 ( optlc_net_1982 ) , .p1967 ( optlc_net_1983 ) ,
+ .p1968 ( optlc_net_1984 ) , .p1969 ( optlc_net_1985 ) ,
+ .p1970 ( optlc_net_1986 ) , .p1971 ( optlc_net_1987 ) ,
+ .p1972 ( optlc_net_1988 ) , .p1973 ( optlc_net_1989 ) ,
+ .p1974 ( optlc_net_1990 ) , .p1975 ( optlc_net_1991 ) ,
+ .p1976 ( optlc_net_1992 ) , .p1977 ( optlc_net_1993 ) ,
+ .p1978 ( optlc_net_1994 ) , .p1979 ( optlc_net_1995 ) ,
+ .p1980 ( optlc_net_1996 ) , .p1981 ( optlc_net_1997 ) ,
+ .p1982 ( optlc_net_1998 ) , .p1983 ( optlc_net_1999 ) ,
+ .p1984 ( optlc_net_2000 ) , .p1985 ( optlc_net_2001 ) ,
+ .p1986 ( optlc_net_2002 ) , .p1987 ( optlc_net_2003 ) ,
+ .p1988 ( optlc_net_2004 ) , .p1989 ( optlc_net_2005 ) ,
+ .p1990 ( optlc_net_2006 ) , .p1991 ( optlc_net_2007 ) ,
+ .p1992 ( optlc_net_2008 ) , .p1993 ( optlc_net_2009 ) ,
+ .p1994 ( optlc_net_2010 ) , .p1995 ( optlc_net_2011 ) ,
+ .p1996 ( optlc_net_2012 ) , .p1997 ( optlc_net_2013 ) ,
+ .p1998 ( optlc_net_2014 ) , .p1999 ( optlc_net_2015 ) ,
+ .p2000 ( optlc_net_2016 ) , .p2001 ( optlc_net_2017 ) ,
+ .p2002 ( optlc_net_2018 ) , .p2003 ( optlc_net_2019 ) ,
+ .p2004 ( optlc_net_2020 ) , .p2005 ( optlc_net_2021 ) ,
+ .p2006 ( optlc_net_2022 ) , .p2007 ( optlc_net_2023 ) ,
+ .p2008 ( optlc_net_2024 ) , .p2009 ( optlc_net_2025 ) ,
+ .p2010 ( optlc_net_2026 ) , .p2011 ( optlc_net_2027 ) ,
+ .p2012 ( optlc_net_2028 ) , .p2013 ( optlc_net_2029 ) ,
+ .p2014 ( optlc_net_2030 ) , .p2015 ( optlc_net_2031 ) ,
+ .p2016 ( optlc_net_2032 ) , .p2017 ( optlc_net_2033 ) ,
+ .p2018 ( optlc_net_2034 ) , .p2019 ( optlc_net_2035 ) ,
+ .p2020 ( optlc_net_2036 ) , .p2021 ( optlc_net_2037 ) ,
+ .p2022 ( optlc_net_2038 ) , .p2023 ( optlc_net_2039 ) ,
+ .p2024 ( optlc_net_2040 ) , .p2025 ( optlc_net_2041 ) ,
+ .p2026 ( optlc_net_2042 ) , .p2027 ( optlc_net_2043 ) ,
+ .p2028 ( optlc_net_2044 ) , .p2029 ( optlc_net_2045 ) ,
+ .p2030 ( optlc_net_2046 ) , .p2031 ( optlc_net_2047 ) ,
+ .p2032 ( optlc_net_2048 ) , .p2033 ( optlc_net_2049 ) ,
+ .p2034 ( optlc_net_2050 ) , .p2035 ( optlc_net_2051 ) ,
+ .p2036 ( optlc_net_2052 ) , .p2037 ( optlc_net_2053 ) ,
+ .p2038 ( optlc_net_2054 ) , .p2039 ( optlc_net_2055 ) ,
+ .p2040 ( optlc_net_2056 ) , .p2041 ( optlc_net_2057 ) ,
+ .p2042 ( optlc_net_2058 ) , .p2043 ( optlc_net_2059 ) ,
+ .p2044 ( optlc_net_2060 ) , .p2045 ( optlc_net_2061 ) ,
+ .p2046 ( optlc_net_2062 ) , .p2047 ( optlc_net_2063 ) ,
+ .p2048 ( optlc_net_2064 ) , .p2049 ( optlc_net_2065 ) ,
+ .p2050 ( optlc_net_2066 ) , .p2051 ( optlc_net_2067 ) ,
+ .p2052 ( optlc_net_2068 ) , .p2053 ( optlc_net_2069 ) ,
+ .p2054 ( optlc_net_2070 ) , .p2055 ( optlc_net_2071 ) ,
+ .p2056 ( optlc_net_2072 ) , .p2057 ( optlc_net_2073 ) ,
+ .p2058 ( optlc_net_2074 ) , .p2059 ( optlc_net_2075 ) ,
+ .p2060 ( optlc_net_2076 ) , .p2061 ( optlc_net_2077 ) ,
+ .p2062 ( optlc_net_2078 ) , .p2063 ( optlc_net_2079 ) ,
+ .p2064 ( optlc_net_2080 ) , .p2065 ( optlc_net_2081 ) ,
+ .p2066 ( optlc_net_2082 ) , .p2067 ( optlc_net_2083 ) ,
+ .p2068 ( optlc_net_2084 ) , .p2069 ( optlc_net_2085 ) ,
+ .p2070 ( optlc_net_2086 ) , .p2071 ( optlc_net_2087 ) ,
+ .p2072 ( optlc_net_2088 ) , .p2073 ( optlc_net_2089 ) ,
+ .p2074 ( optlc_net_2090 ) , .p2075 ( optlc_net_2091 ) ,
+ .p2076 ( optlc_net_2092 ) , .p2077 ( optlc_net_2093 ) ,
+ .p2078 ( optlc_net_2094 ) , .p2079 ( optlc_net_2095 ) ,
+ .p2080 ( optlc_net_2096 ) , .p2081 ( optlc_net_2097 ) ,
+ .p2082 ( optlc_net_2098 ) , .p2083 ( optlc_net_2099 ) ,
+ .p2084 ( optlc_net_2100 ) , .p2085 ( optlc_net_2101 ) ,
+ .p2086 ( optlc_net_2102 ) , .p2087 ( optlc_net_2103 ) ,
+ .p2088 ( optlc_net_2104 ) , .p2089 ( optlc_net_2105 ) ,
+ .p2090 ( optlc_net_2106 ) , .p2091 ( optlc_net_2107 ) ,
+ .p2092 ( optlc_net_2108 ) , .p2093 ( optlc_net_2109 ) ,
+ .p2094 ( optlc_net_2110 ) , .p2095 ( optlc_net_2111 ) ,
+ .p2096 ( optlc_net_2112 ) , .p2097 ( optlc_net_2113 ) ,
+ .p2098 ( optlc_net_2114 ) , .p2099 ( optlc_net_2115 ) ,
+ .p2100 ( optlc_net_2116 ) , .p2101 ( optlc_net_2117 ) ,
+ .p2102 ( optlc_net_2118 ) , .p2103 ( optlc_net_2119 ) ,
+ .p2104 ( optlc_net_2120 ) , .p2105 ( optlc_net_2121 ) ,
+ .p2106 ( optlc_net_2122 ) , .p2107 ( optlc_net_2123 ) ,
+ .p2108 ( optlc_net_2124 ) , .p2109 ( optlc_net_2125 ) ,
+ .p2110 ( optlc_net_2126 ) , .p2111 ( optlc_net_2127 ) ,
+ .p2112 ( optlc_net_2128 ) , .p2113 ( optlc_net_2129 ) ,
+ .p2114 ( optlc_net_2130 ) , .p2115 ( optlc_net_2131 ) ,
+ .p2116 ( optlc_net_2132 ) , .p2117 ( optlc_net_2133 ) ,
+ .p2118 ( optlc_net_2134 ) , .p2119 ( optlc_net_2135 ) ,
+ .p2120 ( optlc_net_2136 ) , .p2121 ( optlc_net_2137 ) ,
+ .p2122 ( optlc_net_2138 ) , .p2123 ( optlc_net_2139 ) ,
+ .p2124 ( optlc_net_2140 ) , .p2125 ( optlc_net_2141 ) ,
+ .p2126 ( optlc_net_2142 ) , .p2127 ( optlc_net_2143 ) ,
+ .p2128 ( optlc_net_2144 ) , .p2129 ( optlc_net_2145 ) ,
+ .p2130 ( optlc_net_2146 ) , .p2131 ( optlc_net_2147 ) ,
+ .p2132 ( optlc_net_2148 ) , .p2133 ( optlc_net_2149 ) ,
+ .p2134 ( optlc_net_2150 ) , .p2135 ( optlc_net_2151 ) ,
+ .p2136 ( optlc_net_2152 ) , .p2137 ( optlc_net_2153 ) ,
+ .p2138 ( optlc_net_2154 ) , .p2139 ( optlc_net_2155 ) ,
+ .p2140 ( optlc_net_2156 ) , .p2141 ( optlc_net_2157 ) ,
+ .p2142 ( optlc_net_2158 ) , .p2143 ( optlc_net_2159 ) ,
+ .p2144 ( optlc_net_2160 ) , .p2145 ( optlc_net_2161 ) ,
+ .p2146 ( optlc_net_2162 ) , .p2147 ( optlc_net_2163 ) ,
+ .p2148 ( optlc_net_2164 ) , .p2149 ( optlc_net_2165 ) ,
+ .p2150 ( optlc_net_2166 ) , .p2151 ( optlc_net_2167 ) ,
+ .p2152 ( optlc_net_2168 ) , .p2153 ( optlc_net_2169 ) ,
+ .p2154 ( optlc_net_2170 ) , .p2155 ( optlc_net_2171 ) ,
+ .p2156 ( optlc_net_2172 ) , .p2157 ( optlc_net_2173 ) ,
+ .p2158 ( optlc_net_2174 ) , .p2159 ( optlc_net_2175 ) ,
+ .p2160 ( optlc_net_2176 ) , .p2161 ( optlc_net_2177 ) ,
+ .p2162 ( optlc_net_2178 ) , .p2163 ( optlc_net_2179 ) ,
+ .p2164 ( optlc_net_2180 ) , .p2165 ( optlc_net_2181 ) ,
+ .p2166 ( optlc_net_2182 ) , .p2167 ( optlc_net_2183 ) ,
+ .p2168 ( optlc_net_2184 ) , .p2169 ( optlc_net_2185 ) ,
+ .p2170 ( optlc_net_2186 ) , .p2171 ( optlc_net_2187 ) ,
+ .p2172 ( optlc_net_2188 ) , .p2173 ( optlc_net_2189 ) ,
+ .p2174 ( optlc_net_2190 ) , .p2175 ( optlc_net_2191 ) ,
+ .p2176 ( optlc_net_2192 ) , .p2177 ( optlc_net_2193 ) ,
+ .p2178 ( optlc_net_2194 ) , .p2179 ( optlc_net_2195 ) ,
+ .p2180 ( optlc_net_2196 ) , .p2181 ( optlc_net_2197 ) ,
+ .p2182 ( optlc_net_2198 ) , .p2183 ( optlc_net_2199 ) ,
+ .p2184 ( optlc_net_2200 ) , .p2185 ( optlc_net_2201 ) ,
+ .p2186 ( optlc_net_2202 ) , .p2187 ( optlc_net_2203 ) ,
+ .p2188 ( optlc_net_2204 ) , .p2189 ( optlc_net_2205 ) ,
+ .p2190 ( optlc_net_2206 ) , .p2191 ( optlc_net_2207 ) ,
+ .p2192 ( optlc_net_2208 ) , .p2193 ( optlc_net_2209 ) ,
+ .p2194 ( optlc_net_2210 ) , .p2195 ( optlc_net_2211 ) ,
+ .p2196 ( optlc_net_2212 ) , .p2197 ( optlc_net_2213 ) ,
+ .p2198 ( optlc_net_2214 ) , .p2199 ( optlc_net_2215 ) ,
+ .p2200 ( optlc_net_2216 ) , .p2201 ( optlc_net_2217 ) ,
+ .p2202 ( optlc_net_2218 ) , .p2203 ( optlc_net_2219 ) ,
+ .p2204 ( optlc_net_2220 ) , .p2205 ( optlc_net_2221 ) ,
+ .p2206 ( optlc_net_2222 ) , .p2207 ( optlc_net_2223 ) ,
+ .p2208 ( optlc_net_2224 ) , .p2209 ( optlc_net_2225 ) ,
+ .p2210 ( optlc_net_2226 ) , .p2211 ( optlc_net_2227 ) ,
+ .p2212 ( optlc_net_2228 ) , .p2213 ( optlc_net_2229 ) ,
+ .p2214 ( optlc_net_2230 ) , .p2215 ( optlc_net_2231 ) ,
+ .p2216 ( optlc_net_2232 ) , .p2217 ( optlc_net_2233 ) ,
+ .p2218 ( optlc_net_2234 ) , .p2219 ( optlc_net_2235 ) ,
+ .p2220 ( optlc_net_2236 ) , .p2221 ( optlc_net_2237 ) ,
+ .p2222 ( optlc_net_2238 ) , .p2223 ( optlc_net_2239 ) ,
+ .p2224 ( optlc_net_2240 ) , .p2225 ( optlc_net_2241 ) ,
+ .p2226 ( optlc_net_2242 ) , .p2227 ( optlc_net_2243 ) ,
+ .p2228 ( optlc_net_2244 ) , .p2229 ( optlc_net_2245 ) ,
+ .p2230 ( optlc_net_2246 ) , .p2231 ( optlc_net_2247 ) ,
+ .p2232 ( optlc_net_2248 ) , .p2233 ( optlc_net_2249 ) ,
+ .p2234 ( optlc_net_2250 ) , .p2235 ( optlc_net_2251 ) ,
+ .p2236 ( optlc_net_2252 ) , .p2237 ( optlc_net_2253 ) ,
+ .p2238 ( optlc_net_2254 ) , .p2239 ( optlc_net_2255 ) ,
+ .p2240 ( optlc_net_2256 ) , .p2241 ( optlc_net_2257 ) ,
+ .p2242 ( optlc_net_2258 ) , .p2243 ( optlc_net_2259 ) ,
+ .p2244 ( optlc_net_2260 ) , .p2245 ( optlc_net_2261 ) ,
+ .p2246 ( optlc_net_2262 ) , .p2247 ( optlc_net_2263 ) ,
+ .p2248 ( optlc_net_2264 ) , .p2249 ( optlc_net_2265 ) ,
+ .p2250 ( optlc_net_2266 ) , .p2251 ( optlc_net_2267 ) ,
+ .p2252 ( optlc_net_2268 ) , .p2253 ( optlc_net_2269 ) ,
+ .p2254 ( optlc_net_2270 ) , .p2255 ( optlc_net_2271 ) ,
+ .p2256 ( optlc_net_2272 ) , .p2257 ( optlc_net_2273 ) ,
+ .p2258 ( optlc_net_2274 ) , .p2259 ( optlc_net_2275 ) ,
+ .p2260 ( optlc_net_2276 ) , .p2261 ( optlc_net_2277 ) ,
+ .p2262 ( optlc_net_2278 ) , .p2263 ( optlc_net_2279 ) ,
+ .p2264 ( optlc_net_2280 ) , .p2265 ( optlc_net_2281 ) ,
+ .p2266 ( optlc_net_2282 ) , .p2267 ( optlc_net_2283 ) ,
+ .p2268 ( optlc_net_2284 ) , .p2269 ( optlc_net_2285 ) ,
+ .p2270 ( optlc_net_2286 ) , .p2271 ( optlc_net_2287 ) ,
+ .p2272 ( optlc_net_2288 ) , .p2273 ( optlc_net_2289 ) ,
+ .p2274 ( optlc_net_2290 ) , .p2275 ( optlc_net_2291 ) ,
+ .p2276 ( optlc_net_2292 ) , .p2277 ( optlc_net_2293 ) ,
+ .p2278 ( optlc_net_2294 ) , .p2279 ( optlc_net_2295 ) ,
+ .p2280 ( optlc_net_2296 ) , .p2281 ( optlc_net_2297 ) ,
+ .p2282 ( optlc_net_2298 ) , .p2283 ( optlc_net_2299 ) ,
+ .p2284 ( optlc_net_2300 ) , .p2285 ( optlc_net_2301 ) ,
+ .p2286 ( optlc_net_2302 ) , .p2287 ( optlc_net_2303 ) ,
+ .p2288 ( optlc_net_2304 ) , .p2289 ( optlc_net_2305 ) ,
+ .p2290 ( optlc_net_2306 ) , .p2291 ( optlc_net_2307 ) ,
+ .p2292 ( optlc_net_2308 ) , .p2293 ( optlc_net_2309 ) ,
+ .p2294 ( optlc_net_2310 ) , .p2295 ( optlc_net_2311 ) ,
+ .p2296 ( optlc_net_2312 ) , .p2297 ( optlc_net_2313 ) ,
+ .p2298 ( optlc_net_2314 ) , .p2299 ( optlc_net_2315 ) ,
+ .p2300 ( optlc_net_2316 ) , .p2301 ( optlc_net_2317 ) ,
+ .p2302 ( optlc_net_2318 ) , .p2303 ( optlc_net_2319 ) ,
+ .p2304 ( optlc_net_2320 ) , .p2305 ( optlc_net_2321 ) ,
+ .p2306 ( optlc_net_2322 ) , .p2307 ( optlc_net_2323 ) ,
+ .p2308 ( optlc_net_2324 ) , .p2309 ( optlc_net_2325 ) ,
+ .p2310 ( optlc_net_2326 ) , .p2311 ( optlc_net_2327 ) ,
+ .p2312 ( optlc_net_2328 ) , .p2313 ( optlc_net_2329 ) ,
+ .p2314 ( optlc_net_2330 ) , .p2315 ( optlc_net_2331 ) ,
+ .p2316 ( optlc_net_2332 ) , .p2317 ( optlc_net_2333 ) ,
+ .p2318 ( optlc_net_2334 ) , .p2319 ( optlc_net_2335 ) ,
+ .p2320 ( optlc_net_2336 ) , .p2321 ( optlc_net_2337 ) ,
+ .p2322 ( optlc_net_2338 ) , .p2323 ( optlc_net_2339 ) ,
+ .p2324 ( optlc_net_2340 ) , .p2325 ( optlc_net_2341 ) ,
+ .p2326 ( optlc_net_2342 ) , .p2327 ( optlc_net_2343 ) ,
+ .p2328 ( optlc_net_2344 ) , .p2329 ( optlc_net_2345 ) ,
+ .p2330 ( optlc_net_2346 ) , .p2331 ( optlc_net_2347 ) ,
+ .p2332 ( optlc_net_2348 ) , .p2333 ( optlc_net_2349 ) ,
+ .p2334 ( optlc_net_2350 ) , .p2335 ( optlc_net_2351 ) ,
+ .p2336 ( optlc_net_2352 ) , .p2337 ( optlc_net_2353 ) ,
+ .p2338 ( optlc_net_2354 ) , .p2339 ( optlc_net_2355 ) ,
+ .p2340 ( optlc_net_2356 ) , .p2341 ( optlc_net_2357 ) ,
+ .p2342 ( optlc_net_2358 ) , .p2343 ( optlc_net_2359 ) ,
+ .p2344 ( optlc_net_2360 ) , .p2345 ( optlc_net_2361 ) ,
+ .p2346 ( optlc_net_2362 ) , .p2347 ( optlc_net_2363 ) ,
+ .p2348 ( optlc_net_2364 ) , .p2349 ( optlc_net_2365 ) ,
+ .p2350 ( optlc_net_2366 ) , .p2351 ( optlc_net_2367 ) ,
+ .p2352 ( optlc_net_2368 ) , .p2353 ( optlc_net_2369 ) ,
+ .p2354 ( optlc_net_2370 ) , .p2355 ( optlc_net_2371 ) ,
+ .p2356 ( optlc_net_2372 ) , .p2357 ( optlc_net_2373 ) ,
+ .p2358 ( optlc_net_2374 ) , .p2359 ( optlc_net_2375 ) ,
+ .p2360 ( optlc_net_2376 ) , .p2361 ( optlc_net_2377 ) ,
+ .p2362 ( optlc_net_2378 ) , .p2363 ( optlc_net_2379 ) ,
+ .p2364 ( optlc_net_2380 ) , .p2365 ( optlc_net_2381 ) ,
+ .p2366 ( optlc_net_2382 ) , .p2367 ( optlc_net_2383 ) ,
+ .p2368 ( optlc_net_2384 ) , .p2369 ( optlc_net_2385 ) ,
+ .p2370 ( optlc_net_2386 ) , .p2371 ( optlc_net_2387 ) ,
+ .p2372 ( optlc_net_2388 ) , .p2373 ( optlc_net_2389 ) ,
+ .p2374 ( optlc_net_2390 ) , .p2375 ( optlc_net_2391 ) ,
+ .p2376 ( optlc_net_2392 ) , .p2377 ( optlc_net_2393 ) ,
+ .p2378 ( optlc_net_2394 ) , .p2379 ( optlc_net_2395 ) ,
+ .p2380 ( optlc_net_2396 ) , .p2381 ( optlc_net_2397 ) ,
+ .p2382 ( optlc_net_2398 ) , .p2383 ( optlc_net_2399 ) ,
+ .p2384 ( optlc_net_2400 ) , .p2385 ( optlc_net_2401 ) ,
+ .p2386 ( optlc_net_2402 ) , .p2387 ( optlc_net_2403 ) ,
+ .p2388 ( optlc_net_2404 ) , .p2389 ( optlc_net_2405 ) ,
+ .p2390 ( optlc_net_2406 ) , .p2391 ( optlc_net_2407 ) ,
+ .p2392 ( optlc_net_2408 ) , .p2393 ( optlc_net_2409 ) ,
+ .p2394 ( optlc_net_2410 ) , .p2395 ( optlc_net_2411 ) ,
+ .p2396 ( optlc_net_2412 ) , .p2397 ( optlc_net_2413 ) ,
+ .p2398 ( optlc_net_2414 ) , .p2399 ( optlc_net_2415 ) ,
+ .p2400 ( optlc_net_2416 ) , .p2401 ( optlc_net_2417 ) ,
+ .p2402 ( optlc_net_2418 ) , .p2403 ( optlc_net_2419 ) ,
+ .p2404 ( optlc_net_2420 ) , .p2405 ( optlc_net_2421 ) ,
+ .p2406 ( optlc_net_2422 ) , .p2407 ( optlc_net_2423 ) ,
+ .p2408 ( optlc_net_2424 ) , .p2409 ( optlc_net_2425 ) ,
+ .p2410 ( optlc_net_2426 ) , .p2411 ( optlc_net_2427 ) ,
+ .p2412 ( optlc_net_2428 ) , .p2413 ( optlc_net_2429 ) ,
+ .p2414 ( optlc_net_2430 ) , .p2415 ( optlc_net_2431 ) ,
+ .p2416 ( optlc_net_2432 ) , .p2417 ( optlc_net_2433 ) ,
+ .p2418 ( optlc_net_2434 ) , .p2419 ( optlc_net_2435 ) ,
+ .p2420 ( optlc_net_2436 ) , .p2421 ( optlc_net_2437 ) ,
+ .p2422 ( optlc_net_2438 ) , .p2423 ( optlc_net_2439 ) ,
+ .p2424 ( optlc_net_2440 ) , .p2425 ( optlc_net_2441 ) ,
+ .p2426 ( optlc_net_2442 ) , .p2427 ( optlc_net_2443 ) ,
+ .p2428 ( optlc_net_2444 ) , .p2429 ( optlc_net_2445 ) ,
+ .p2430 ( optlc_net_2446 ) , .p2431 ( optlc_net_2447 ) ,
+ .p2432 ( optlc_net_2448 ) , .p2433 ( optlc_net_2449 ) ,
+ .p2434 ( optlc_net_2450 ) , .p2435 ( optlc_net_2451 ) ,
+ .p2436 ( optlc_net_2452 ) , .p2437 ( optlc_net_2453 ) ,
+ .p2438 ( optlc_net_2454 ) , .p2439 ( optlc_net_2455 ) ,
+ .p2440 ( optlc_net_2456 ) , .p2441 ( optlc_net_2457 ) ,
+ .p2442 ( optlc_net_2458 ) , .p2443 ( optlc_net_2459 ) ,
+ .p2444 ( optlc_net_2460 ) , .p2445 ( optlc_net_2461 ) ,
+ .p2446 ( optlc_net_2462 ) , .p2447 ( optlc_net_2463 ) ,
+ .p2448 ( optlc_net_2464 ) , .p2449 ( optlc_net_2465 ) ,
+ .p2450 ( optlc_net_2466 ) , .p2451 ( optlc_net_2467 ) ,
+ .p2452 ( optlc_net_2468 ) , .p2453 ( optlc_net_2469 ) ,
+ .p2454 ( optlc_net_2470 ) , .p2455 ( optlc_net_2471 ) ,
+ .p2456 ( optlc_net_2472 ) , .p2457 ( optlc_net_2473 ) ,
+ .p2458 ( optlc_net_2474 ) , .p2459 ( optlc_net_2475 ) ,
+ .p2460 ( optlc_net_2476 ) , .p2461 ( optlc_net_2477 ) ,
+ .p2462 ( optlc_net_2478 ) , .p2463 ( optlc_net_2479 ) ,
+ .p2464 ( optlc_net_2480 ) , .p2465 ( optlc_net_2481 ) ,
+ .p2466 ( optlc_net_2482 ) , .p2467 ( optlc_net_2483 ) ,
+ .p2468 ( optlc_net_2484 ) , .p2469 ( optlc_net_2485 ) ,
+ .p2470 ( optlc_net_2486 ) , .p2471 ( optlc_net_2487 ) ,
+ .p2472 ( optlc_net_2488 ) , .p2473 ( optlc_net_2489 ) ,
+ .p2474 ( optlc_net_2490 ) , .p2475 ( optlc_net_2491 ) ,
+ .p2476 ( optlc_net_2492 ) , .p2477 ( optlc_net_2493 ) ,
+ .p2478 ( optlc_net_2494 ) , .p2479 ( optlc_net_2495 ) ,
+ .p2480 ( optlc_net_2496 ) , .p2481 ( optlc_net_2497 ) ,
+ .p2482 ( optlc_net_2498 ) , .p2483 ( optlc_net_2499 ) ,
+ .p2484 ( optlc_net_2500 ) , .p2485 ( optlc_net_2501 ) ,
+ .p2486 ( optlc_net_2502 ) , .p2487 ( optlc_net_2503 ) ,
+ .p2488 ( optlc_net_2504 ) , .p2489 ( optlc_net_2505 ) ,
+ .p2490 ( optlc_net_2506 ) , .p2491 ( optlc_net_2507 ) ,
+ .p2492 ( optlc_net_2508 ) , .p2493 ( optlc_net_2509 ) ,
+ .p2494 ( optlc_net_2510 ) , .p2495 ( optlc_net_2511 ) ,
+ .p2496 ( optlc_net_2512 ) , .p2497 ( optlc_net_2513 ) ,
+ .p2498 ( optlc_net_2514 ) , .p2499 ( optlc_net_2515 ) ,
+ .p2500 ( optlc_net_2516 ) , .p2501 ( optlc_net_2517 ) ,
+ .p2502 ( optlc_net_2518 ) , .p2503 ( optlc_net_2519 ) ,
+ .p2504 ( optlc_net_2520 ) , .p2505 ( optlc_net_2521 ) ,
+ .p2506 ( optlc_net_2522 ) , .p2507 ( optlc_net_2523 ) ,
+ .p2508 ( optlc_net_2524 ) , .p2509 ( optlc_net_2525 ) ,
+ .p2510 ( optlc_net_2526 ) , .p2511 ( optlc_net_2527 ) ,
+ .p2512 ( optlc_net_2528 ) , .p2513 ( optlc_net_2529 ) ,
+ .p2514 ( optlc_net_2530 ) , .p2515 ( optlc_net_2531 ) ,
+ .p2516 ( optlc_net_2532 ) , .p2517 ( optlc_net_2533 ) ,
+ .p2518 ( optlc_net_2534 ) , .p2519 ( optlc_net_2535 ) ,
+ .p2520 ( optlc_net_2536 ) , .p2521 ( optlc_net_2537 ) ,
+ .p2522 ( optlc_net_2538 ) , .p2523 ( optlc_net_2539 ) ,
+ .p2524 ( optlc_net_2540 ) , .p2525 ( optlc_net_2541 ) ,
+ .p2526 ( optlc_net_2542 ) , .p2527 ( optlc_net_2543 ) ,
+ .p2528 ( optlc_net_2544 ) , .p2529 ( optlc_net_2545 ) ,
+ .p2530 ( optlc_net_2546 ) , .p2531 ( optlc_net_2547 ) ,
+ .p2532 ( optlc_net_2548 ) , .p2533 ( optlc_net_2549 ) ,
+ .p2534 ( optlc_net_2550 ) , .p2535 ( optlc_net_2551 ) ,
+ .p2536 ( optlc_net_2552 ) , .p2537 ( optlc_net_2553 ) ,
+ .p2538 ( optlc_net_2554 ) , .p2539 ( optlc_net_2555 ) ,
+ .p2540 ( optlc_net_2556 ) , .p2541 ( optlc_net_2557 ) ,
+ .p2542 ( optlc_net_2558 ) , .p2543 ( optlc_net_2559 ) ,
+ .p2544 ( optlc_net_2560 ) , .p2545 ( optlc_net_2561 ) ,
+ .p2546 ( optlc_net_2562 ) , .p2547 ( optlc_net_2563 ) ,
+ .p2548 ( optlc_net_2564 ) , .p2549 ( optlc_net_2565 ) ,
+ .p2550 ( optlc_net_2566 ) , .p2551 ( optlc_net_2567 ) ,
+ .p2552 ( optlc_net_2568 ) , .p2553 ( optlc_net_2569 ) ,
+ .p2554 ( optlc_net_2570 ) , .p2555 ( optlc_net_2571 ) ,
+ .p2556 ( optlc_net_2572 ) , .p2557 ( optlc_net_2573 ) ,
+ .p2558 ( optlc_net_2574 ) , .p2559 ( optlc_net_2575 ) ,
+ .p2560 ( optlc_net_2576 ) , .p2561 ( optlc_net_2577 ) ,
+ .p2562 ( optlc_net_2578 ) , .p2563 ( optlc_net_2579 ) ,
+ .p2564 ( optlc_net_2580 ) , .p2565 ( optlc_net_2581 ) ,
+ .p2566 ( optlc_net_2582 ) , .p2567 ( optlc_net_2583 ) ,
+ .p2568 ( optlc_net_2584 ) , .p2569 ( optlc_net_2585 ) ,
+ .p2570 ( optlc_net_2586 ) , .p2571 ( optlc_net_2587 ) ,
+ .p2572 ( optlc_net_2588 ) , .p2573 ( optlc_net_2589 ) ,
+ .p2574 ( optlc_net_2590 ) , .p2575 ( optlc_net_2591 ) ,
+ .p2576 ( optlc_net_2592 ) , .p2577 ( optlc_net_2593 ) ,
+ .p2578 ( optlc_net_2594 ) , .p2579 ( optlc_net_2595 ) ,
+ .p2580 ( optlc_net_2596 ) , .p2581 ( optlc_net_2597 ) ,
+ .p2582 ( optlc_net_2598 ) , .p2583 ( optlc_net_2599 ) ,
+ .p2584 ( optlc_net_2600 ) , .p2585 ( optlc_net_2601 ) ,
+ .p2586 ( optlc_net_2602 ) , .p2587 ( optlc_net_2603 ) ,
+ .p2588 ( optlc_net_2604 ) , .p2589 ( optlc_net_2605 ) ,
+ .p2590 ( optlc_net_2606 ) , .p2591 ( optlc_net_2607 ) ,
+ .p2592 ( optlc_net_2608 ) , .p2593 ( optlc_net_2609 ) ,
+ .p2594 ( optlc_net_2610 ) , .p2595 ( optlc_net_2611 ) ,
+ .p2596 ( optlc_net_2612 ) , .p2597 ( optlc_net_2613 ) ,
+ .p2598 ( optlc_net_2614 ) , .p2599 ( optlc_net_2615 ) ,
+ .p2600 ( optlc_net_2616 ) , .p2601 ( optlc_net_2617 ) ,
+ .p2602 ( optlc_net_2618 ) , .p2603 ( optlc_net_2619 ) ,
+ .p2604 ( optlc_net_2620 ) , .p2605 ( optlc_net_2621 ) ,
+ .p2606 ( optlc_net_2622 ) , .p2607 ( optlc_net_2623 ) ,
+ .p2608 ( optlc_net_2624 ) , .p2609 ( optlc_net_2625 ) ,
+ .p2610 ( optlc_net_2626 ) , .p2611 ( optlc_net_2627 ) ,
+ .p2612 ( optlc_net_2628 ) , .p2613 ( optlc_net_2629 ) ,
+ .p2614 ( optlc_net_2630 ) , .p2615 ( optlc_net_2631 ) ,
+ .p2616 ( optlc_net_2632 ) , .p2617 ( optlc_net_2633 ) ,
+ .p2618 ( optlc_net_2634 ) , .p2619 ( optlc_net_2635 ) ,
+ .p2620 ( optlc_net_2636 ) , .p2621 ( optlc_net_2637 ) ,
+ .p2622 ( optlc_net_2638 ) , .p2623 ( optlc_net_2639 ) ,
+ .p2624 ( optlc_net_2640 ) , .p2625 ( optlc_net_2641 ) ,
+ .p2626 ( optlc_net_2642 ) , .p2627 ( optlc_net_2643 ) ,
+ .p2628 ( optlc_net_2644 ) , .p2629 ( optlc_net_2645 ) ,
+ .p2630 ( optlc_net_2646 ) , .p2631 ( optlc_net_2647 ) ,
+ .p2632 ( optlc_net_2648 ) , .p2633 ( optlc_net_2649 ) ,
+ .p2634 ( optlc_net_2650 ) , .p2635 ( optlc_net_2651 ) ,
+ .p2636 ( optlc_net_2652 ) , .p2637 ( optlc_net_2653 ) ,
+ .p2638 ( optlc_net_2654 ) , .p2639 ( optlc_net_2655 ) ,
+ .p2640 ( optlc_net_2656 ) , .p2641 ( optlc_net_2657 ) ,
+ .p2642 ( optlc_net_2658 ) , .p2643 ( optlc_net_2659 ) ,
+ .p2644 ( optlc_net_2660 ) , .p2645 ( optlc_net_2661 ) ,
+ .p2646 ( optlc_net_2662 ) , .p2647 ( optlc_net_2663 ) ,
+ .p2648 ( optlc_net_2664 ) , .p2649 ( optlc_net_2665 ) ,
+ .p2650 ( optlc_net_2666 ) , .p2651 ( optlc_net_2667 ) ,
+ .p2652 ( optlc_net_2668 ) , .p2653 ( optlc_net_2669 ) ,
+ .p2654 ( optlc_net_2670 ) , .p2655 ( optlc_net_2671 ) ,
+ .p2656 ( optlc_net_2672 ) , .p2657 ( optlc_net_2673 ) ,
+ .p2658 ( optlc_net_2674 ) , .p2659 ( optlc_net_2675 ) ,
+ .p2660 ( optlc_net_2676 ) , .p2661 ( optlc_net_2677 ) ,
+ .p2662 ( optlc_net_2678 ) , .p2663 ( optlc_net_2679 ) ,
+ .p2664 ( optlc_net_2680 ) , .p2665 ( optlc_net_2681 ) ,
+ .p2666 ( optlc_net_2682 ) , .p2667 ( optlc_net_2683 ) ,
+ .p2668 ( optlc_net_2684 ) , .p2669 ( optlc_net_2685 ) ,
+ .p2670 ( optlc_net_2686 ) , .p2671 ( optlc_net_2687 ) ,
+ .p2672 ( optlc_net_2688 ) , .p2673 ( optlc_net_2689 ) ,
+ .p2674 ( optlc_net_2690 ) , .p2675 ( optlc_net_2691 ) ,
+ .p2676 ( optlc_net_2692 ) , .p2677 ( optlc_net_2693 ) ,
+ .p2678 ( optlc_net_2694 ) , .p2679 ( optlc_net_2695 ) ,
+ .p2680 ( optlc_net_2696 ) , .p2681 ( optlc_net_2697 ) ,
+ .p2682 ( optlc_net_2698 ) , .p2683 ( optlc_net_2699 ) ,
+ .p2684 ( optlc_net_2700 ) , .p2685 ( optlc_net_2701 ) ,
+ .p2686 ( optlc_net_2702 ) , .p2687 ( optlc_net_2703 ) ,
+ .p2688 ( optlc_net_2704 ) , .p2689 ( optlc_net_2705 ) ,
+ .p2690 ( optlc_net_2706 ) , .p2691 ( optlc_net_2707 ) ,
+ .p2692 ( optlc_net_2708 ) , .p2693 ( optlc_net_2709 ) ,
+ .p2694 ( optlc_net_2710 ) , .p2695 ( optlc_net_2711 ) ,
+ .p2696 ( optlc_net_2712 ) , .p2697 ( optlc_net_2713 ) ,
+ .p2698 ( optlc_net_2714 ) , .p2699 ( optlc_net_2715 ) ,
+ .p2700 ( optlc_net_2716 ) , .p2701 ( optlc_net_2717 ) ,
+ .p2702 ( optlc_net_2718 ) , .p2703 ( optlc_net_2719 ) ,
+ .p2704 ( optlc_net_2720 ) , .p2705 ( optlc_net_2721 ) ,
+ .p2706 ( optlc_net_2722 ) , .p2707 ( optlc_net_2723 ) ,
+ .p2708 ( optlc_net_2724 ) , .p2709 ( optlc_net_2725 ) ,
+ .p2710 ( optlc_net_2726 ) , .p2711 ( optlc_net_2727 ) ,
+ .p2712 ( optlc_net_2728 ) , .p2713 ( optlc_net_2729 ) ,
+ .p2714 ( optlc_net_2730 ) , .p2715 ( optlc_net_2731 ) ,
+ .p2716 ( optlc_net_2732 ) , .p2717 ( optlc_net_2733 ) ,
+ .p2718 ( optlc_net_2734 ) , .p2719 ( optlc_net_2735 ) ,
+ .p2720 ( optlc_net_2736 ) , .p2721 ( optlc_net_2737 ) ,
+ .p2722 ( optlc_net_2738 ) , .p2723 ( optlc_net_2739 ) ,
+ .p2724 ( optlc_net_2740 ) , .p2725 ( optlc_net_2741 ) ,
+ .p2726 ( optlc_net_2742 ) , .p2727 ( optlc_net_2743 ) ,
+ .p2728 ( optlc_net_2744 ) , .p2729 ( optlc_net_2745 ) ,
+ .p2730 ( optlc_net_2746 ) , .p2731 ( optlc_net_2747 ) ,
+ .p2732 ( optlc_net_2748 ) , .p2733 ( optlc_net_2749 ) ,
+ .p2734 ( optlc_net_2750 ) , .p2735 ( optlc_net_2751 ) ,
+ .p2736 ( optlc_net_2752 ) , .p2737 ( optlc_net_2753 ) ,
+ .p2738 ( optlc_net_2754 ) , .p2739 ( optlc_net_2755 ) ,
+ .p2740 ( optlc_net_2756 ) , .p2741 ( optlc_net_2757 ) ,
+ .p2742 ( optlc_net_2758 ) , .p2743 ( optlc_net_2759 ) ,
+ .p2744 ( optlc_net_2760 ) , .p2745 ( optlc_net_2761 ) ,
+ .p2746 ( optlc_net_2762 ) , .p2747 ( optlc_net_2763 ) ,
+ .p2748 ( optlc_net_2764 ) , .p2749 ( optlc_net_2765 ) ,
+ .p2750 ( optlc_net_2766 ) , .p2751 ( optlc_net_2767 ) ,
+ .p2752 ( optlc_net_2768 ) , .p2753 ( optlc_net_2769 ) ,
+ .p2754 ( optlc_net_2770 ) , .p2755 ( optlc_net_2771 ) ,
+ .p2756 ( optlc_net_2772 ) , .p2757 ( optlc_net_2773 ) ,
+ .p2758 ( optlc_net_2774 ) , .p2759 ( optlc_net_2775 ) ,
+ .p2760 ( optlc_net_2776 ) , .p2761 ( optlc_net_2777 ) ,
+ .p2762 ( optlc_net_2778 ) , .p2763 ( optlc_net_2779 ) ,
+ .p2764 ( optlc_net_2780 ) , .p2765 ( optlc_net_2781 ) ,
+ .p2766 ( optlc_net_2782 ) , .p2767 ( optlc_net_2783 ) ,
+ .p2768 ( optlc_net_2784 ) , .p2769 ( optlc_net_2785 ) ,
+ .p2770 ( optlc_net_2786 ) , .p2771 ( optlc_net_2787 ) ,
+ .p2772 ( optlc_net_2788 ) , .p2773 ( optlc_net_2789 ) ,
+ .p2774 ( optlc_net_2790 ) , .p2775 ( optlc_net_2791 ) ,
+ .p2776 ( optlc_net_2792 ) , .p2777 ( optlc_net_2793 ) ,
+ .p2778 ( optlc_net_2794 ) , .p2779 ( optlc_net_2795 ) ,
+ .p2780 ( optlc_net_2796 ) , .p2781 ( optlc_net_2797 ) ,
+ .p2782 ( optlc_net_2798 ) , .p2783 ( optlc_net_2799 ) ,
+ .p2784 ( optlc_net_2800 ) , .p2785 ( optlc_net_2801 ) ,
+ .p2786 ( optlc_net_2802 ) , .p2787 ( optlc_net_2803 ) ,
+ .p2788 ( optlc_net_2804 ) , .p2789 ( optlc_net_2805 ) ,
+ .p2790 ( optlc_net_2806 ) , .p2791 ( optlc_net_2807 ) ,
+ .p2792 ( optlc_net_2808 ) , .p2793 ( optlc_net_2809 ) ,
+ .p2794 ( optlc_net_2810 ) , .p2795 ( optlc_net_2811 ) ,
+ .p2796 ( optlc_net_2812 ) , .p2797 ( optlc_net_2813 ) ,
+ .p2798 ( optlc_net_2814 ) , .p2799 ( optlc_net_2815 ) ,
+ .p2800 ( optlc_net_2816 ) , .p2801 ( optlc_net_2817 ) ,
+ .p2802 ( optlc_net_2818 ) , .p2803 ( optlc_net_2819 ) ,
+ .p2804 ( optlc_net_2820 ) , .p2805 ( optlc_net_2821 ) ,
+ .p2806 ( optlc_net_2822 ) , .p2807 ( optlc_net_2823 ) ,
+ .p2808 ( optlc_net_2824 ) , .p2809 ( optlc_net_2825 ) ,
+ .p2810 ( optlc_net_2826 ) , .p2811 ( optlc_net_2827 ) ,
+ .p2812 ( optlc_net_2828 ) , .p2813 ( optlc_net_2829 ) ,
+ .p2814 ( optlc_net_2830 ) , .p2815 ( optlc_net_2831 ) ,
+ .p2816 ( optlc_net_2832 ) , .p2817 ( optlc_net_2833 ) ,
+ .p2818 ( optlc_net_2834 ) , .p2819 ( optlc_net_2835 ) ,
+ .p2820 ( optlc_net_2836 ) , .p2821 ( optlc_net_2837 ) ,
+ .p2822 ( optlc_net_2838 ) , .p2823 ( optlc_net_2839 ) ,
+ .p2824 ( optlc_net_2840 ) , .p2825 ( optlc_net_2841 ) ,
+ .p2826 ( optlc_net_2842 ) , .p2827 ( optlc_net_2843 ) ,
+ .p2828 ( optlc_net_2844 ) , .p2829 ( optlc_net_2845 ) ,
+ .p2830 ( optlc_net_2846 ) , .p2831 ( optlc_net_2847 ) ,
+ .p2832 ( optlc_net_2848 ) , .p2833 ( optlc_net_2849 ) ,
+ .p2834 ( optlc_net_2850 ) , .p2835 ( optlc_net_2851 ) ,
+ .p2836 ( optlc_net_2852 ) , .p2837 ( optlc_net_2853 ) ,
+ .p2838 ( optlc_net_2854 ) , .p2839 ( optlc_net_2855 ) ,
+ .p2840 ( optlc_net_2856 ) , .p2841 ( optlc_net_2857 ) ,
+ .p2842 ( optlc_net_2858 ) , .p2843 ( optlc_net_2859 ) ,
+ .p2844 ( optlc_net_2860 ) , .p2845 ( optlc_net_2861 ) ,
+ .p2846 ( optlc_net_2862 ) , .p2847 ( optlc_net_2863 ) ,
+ .p2848 ( optlc_net_2864 ) , .p2849 ( optlc_net_2865 ) ,
+ .p2850 ( optlc_net_2866 ) , .p2851 ( optlc_net_2867 ) ,
+ .p2852 ( optlc_net_2868 ) , .p2853 ( optlc_net_2869 ) ,
+ .p2854 ( optlc_net_2870 ) , .p2855 ( optlc_net_2871 ) ,
+ .p2856 ( optlc_net_2872 ) , .p2857 ( optlc_net_2873 ) ,
+ .p2858 ( optlc_net_2874 ) , .p2859 ( optlc_net_2875 ) ,
+ .p2860 ( optlc_net_2876 ) , .p2861 ( optlc_net_2877 ) ,
+ .p2862 ( optlc_net_2878 ) , .p2863 ( optlc_net_2879 ) ,
+ .p2864 ( optlc_net_2880 ) , .p2865 ( optlc_net_2881 ) ,
+ .p2866 ( optlc_net_2882 ) , .p2867 ( optlc_net_2883 ) ,
+ .p2868 ( optlc_net_2884 ) , .p2869 ( optlc_net_2885 ) ,
+ .p2870 ( optlc_net_2886 ) , .p2871 ( optlc_net_2887 ) ,
+ .p2872 ( optlc_net_2888 ) , .p2873 ( optlc_net_2889 ) ,
+ .p2874 ( optlc_net_2890 ) , .p2875 ( optlc_net_2891 ) ,
+ .p2876 ( optlc_net_2892 ) , .p2877 ( optlc_net_2893 ) ,
+ .p2878 ( optlc_net_2894 ) , .p2879 ( optlc_net_2895 ) ,
+ .p2880 ( optlc_net_2896 ) , .p2881 ( optlc_net_2897 ) ,
+ .p2882 ( optlc_net_2898 ) , .p2883 ( optlc_net_2899 ) ,
+ .p2884 ( optlc_net_2900 ) , .p2885 ( optlc_net_2901 ) ,
+ .p2886 ( optlc_net_2902 ) , .p2887 ( optlc_net_2903 ) ,
+ .p2888 ( optlc_net_2904 ) , .p2889 ( optlc_net_2905 ) ,
+ .p2890 ( optlc_net_2906 ) , .p2891 ( optlc_net_2907 ) ,
+ .p2892 ( optlc_net_2908 ) , .p2893 ( optlc_net_2909 ) ,
+ .p2894 ( optlc_net_2910 ) , .p2895 ( optlc_net_2911 ) ,
+ .p2896 ( optlc_net_2912 ) , .p2897 ( optlc_net_2913 ) ,
+ .p2898 ( optlc_net_2914 ) , .p2899 ( optlc_net_2915 ) ,
+ .p2900 ( optlc_net_2916 ) , .p2901 ( optlc_net_2917 ) ,
+ .p2902 ( optlc_net_2918 ) , .p2903 ( optlc_net_2919 ) ,
+ .p2904 ( optlc_net_2920 ) , .p2905 ( optlc_net_2921 ) ,
+ .p2906 ( optlc_net_2922 ) , .p2907 ( optlc_net_2923 ) ,
+ .p2908 ( optlc_net_2924 ) , .p2909 ( optlc_net_2925 ) ,
+ .p2910 ( optlc_net_2926 ) , .p2911 ( optlc_net_2927 ) ,
+ .p2912 ( optlc_net_2928 ) , .p2913 ( optlc_net_2929 ) ,
+ .p2914 ( optlc_net_2930 ) , .p2915 ( optlc_net_2931 ) ,
+ .p2916 ( optlc_net_2932 ) , .p2917 ( optlc_net_2933 ) ,
+ .p2918 ( optlc_net_2934 ) , .p2919 ( optlc_net_2935 ) ,
+ .p2920 ( optlc_net_2936 ) , .p2921 ( optlc_net_2937 ) ,
+ .p2922 ( optlc_net_2938 ) , .p2923 ( optlc_net_2939 ) ,
+ .p2924 ( optlc_net_2940 ) , .p2925 ( optlc_net_2941 ) ,
+ .p2926 ( optlc_net_2942 ) , .p2927 ( optlc_net_2943 ) ,
+ .p2928 ( optlc_net_2944 ) , .p2929 ( optlc_net_2945 ) ,
+ .p2930 ( optlc_net_2946 ) , .p2931 ( optlc_net_2947 ) ,
+ .p2932 ( optlc_net_2948 ) , .p2933 ( optlc_net_2949 ) ,
+ .p2934 ( optlc_net_2950 ) , .p2935 ( optlc_net_2951 ) ,
+ .p2936 ( optlc_net_2952 ) , .p2937 ( optlc_net_2953 ) ,
+ .p2938 ( optlc_net_2954 ) , .p2939 ( optlc_net_2955 ) ,
+ .p2940 ( optlc_net_2956 ) , .p2941 ( optlc_net_2957 ) ,
+ .p2942 ( optlc_net_2958 ) , .p2943 ( optlc_net_2959 ) ,
+ .p2944 ( optlc_net_2960 ) , .p2945 ( optlc_net_2961 ) ,
+ .p2946 ( optlc_net_2962 ) , .p2947 ( optlc_net_2963 ) ,
+ .p2948 ( optlc_net_2964 ) , .p2949 ( optlc_net_2965 ) ,
+ .p2950 ( optlc_net_2966 ) , .p2951 ( optlc_net_2967 ) ,
+ .p2952 ( optlc_net_2968 ) , .p2953 ( optlc_net_2969 ) ,
+ .p2954 ( optlc_net_2970 ) , .p2955 ( optlc_net_2971 ) ,
+ .p2956 ( optlc_net_2972 ) , .p2957 ( optlc_net_2973 ) ,
+ .p2958 ( optlc_net_2974 ) , .p2959 ( optlc_net_2975 ) ,
+ .p2960 ( optlc_net_2976 ) , .p2961 ( optlc_net_2977 ) ,
+ .p2962 ( optlc_net_2978 ) , .p2963 ( optlc_net_2979 ) ,
+ .p2964 ( optlc_net_2980 ) , .p2965 ( optlc_net_2981 ) ,
+ .p2966 ( optlc_net_2982 ) , .p2967 ( optlc_net_2983 ) ,
+ .p2968 ( optlc_net_2984 ) , .p2969 ( optlc_net_2985 ) ,
+ .p2970 ( optlc_net_2986 ) , .p2971 ( optlc_net_2987 ) ,
+ .p2972 ( optlc_net_2988 ) , .p2973 ( optlc_net_2989 ) ,
+ .p2974 ( optlc_net_2990 ) , .p2975 ( optlc_net_2991 ) ,
+ .p2976 ( optlc_net_2992 ) , .p2977 ( optlc_net_2993 ) ,
+ .p2978 ( optlc_net_2994 ) , .p2979 ( optlc_net_2995 ) ,
+ .p2980 ( optlc_net_2996 ) , .p2981 ( optlc_net_2997 ) ,
+ .p2982 ( optlc_net_2998 ) , .p2983 ( optlc_net_2999 ) ,
+ .p2984 ( optlc_net_3000 ) , .p2985 ( optlc_net_3001 ) ,
+ .p2986 ( optlc_net_3002 ) , .p2987 ( optlc_net_3003 ) ,
+ .p2988 ( optlc_net_3004 ) , .p2989 ( optlc_net_3005 ) ,
+ .p2990 ( optlc_net_3006 ) , .p2991 ( optlc_net_3007 ) ,
+ .p2992 ( optlc_net_3008 ) , .p2993 ( optlc_net_3009 ) ,
+ .p2994 ( optlc_net_3010 ) , .p2995 ( optlc_net_3011 ) ,
+ .p2996 ( optlc_net_3012 ) , .p2997 ( optlc_net_3013 ) ,
+ .p2998 ( optlc_net_3014 ) , .p2999 ( optlc_net_3015 ) ,
+ .p3000 ( optlc_net_3016 ) , .p3001 ( optlc_net_3017 ) ,
+ .p3002 ( optlc_net_3018 ) , .p3003 ( optlc_net_3019 ) ,
+ .p3004 ( optlc_net_3020 ) , .p3005 ( optlc_net_3021 ) ,
+ .p3006 ( optlc_net_3022 ) , .p3007 ( optlc_net_3023 ) ,
+ .p3008 ( optlc_net_3024 ) , .p3009 ( optlc_net_3025 ) ,
+ .p3010 ( optlc_net_3026 ) , .p3011 ( optlc_net_3027 ) ,
+ .p3012 ( optlc_net_3028 ) , .p3013 ( optlc_net_3029 ) ,
+ .p3014 ( optlc_net_3030 ) , .p3015 ( optlc_net_3031 ) ,
+ .p3016 ( optlc_net_3032 ) , .p3017 ( optlc_net_3033 ) ,
+ .p3018 ( optlc_net_3034 ) , .p3019 ( optlc_net_3035 ) ,
+ .p3020 ( optlc_net_3036 ) , .p3021 ( optlc_net_3037 ) ,
+ .p3022 ( optlc_net_3038 ) , .p3023 ( optlc_net_3039 ) ,
+ .p3024 ( optlc_net_3040 ) , .p3025 ( optlc_net_3041 ) ,
+ .p3026 ( optlc_net_3042 ) , .p3027 ( optlc_net_3043 ) ,
+ .p3028 ( optlc_net_3044 ) , .p3029 ( optlc_net_3045 ) ,
+ .p3030 ( optlc_net_3046 ) , .p3031 ( optlc_net_3047 ) ,
+ .p3032 ( optlc_net_3048 ) , .p3033 ( optlc_net_3049 ) ,
+ .p3034 ( optlc_net_3050 ) , .p3035 ( optlc_net_3051 ) ,
+ .p3036 ( optlc_net_3052 ) , .p3037 ( optlc_net_3053 ) ,
+ .p3038 ( optlc_net_3054 ) , .p3039 ( optlc_net_3055 ) ,
+ .p3040 ( optlc_net_3056 ) , .p3041 ( optlc_net_3057 ) ,
+ .p3042 ( optlc_net_3058 ) , .p3043 ( optlc_net_3059 ) ,
+ .p3044 ( optlc_net_3060 ) , .p3045 ( optlc_net_3061 ) ,
+ .p3046 ( optlc_net_3062 ) , .p3047 ( optlc_net_3063 ) ,
+ .p3048 ( optlc_net_3064 ) , .p3049 ( optlc_net_3065 ) ,
+ .p3050 ( optlc_net_3066 ) , .p3051 ( optlc_net_3067 ) ,
+ .p3052 ( optlc_net_3068 ) , .p3053 ( optlc_net_3069 ) ,
+ .p3054 ( optlc_net_3070 ) , .p3055 ( optlc_net_3071 ) ,
+ .p3056 ( optlc_net_3072 ) , .p3057 ( optlc_net_3073 ) ,
+ .p3058 ( optlc_net_3074 ) , .p3059 ( optlc_net_3075 ) ,
+ .p3060 ( optlc_net_3076 ) , .p3061 ( optlc_net_3077 ) ,
+ .p3062 ( optlc_net_3078 ) , .p3063 ( optlc_net_3079 ) ,
+ .p3064 ( optlc_net_3080 ) , .p3065 ( optlc_net_3081 ) ,
+ .p3066 ( optlc_net_3082 ) , .p3067 ( optlc_net_3083 ) ,
+ .p3068 ( optlc_net_3084 ) , .p3069 ( optlc_net_3085 ) ,
+ .p3070 ( optlc_net_3086 ) , .p3071 ( optlc_net_3087 ) ,
+ .p3072 ( optlc_net_3088 ) , .p3073 ( optlc_net_3089 ) ,
+ .p3074 ( optlc_net_3090 ) , .p3075 ( optlc_net_3091 ) ,
+ .p3076 ( optlc_net_3092 ) , .p3077 ( optlc_net_3093 ) ,
+ .p3078 ( optlc_net_3094 ) , .p3079 ( optlc_net_3095 ) ,
+ .p3080 ( optlc_net_3096 ) , .p3081 ( optlc_net_3097 ) ,
+ .p3082 ( optlc_net_3098 ) , .p3083 ( optlc_net_3099 ) ,
+ .p3084 ( optlc_net_3100 ) , .p3085 ( optlc_net_3101 ) ,
+ .p3086 ( optlc_net_3102 ) , .p3087 ( optlc_net_3103 ) ,
+ .p3088 ( optlc_net_3104 ) , .p3089 ( optlc_net_3105 ) ,
+ .p3090 ( optlc_net_3106 ) , .p3091 ( optlc_net_3107 ) ,
+ .p3092 ( optlc_net_3108 ) , .p3093 ( optlc_net_3109 ) ,
+ .p3094 ( optlc_net_3110 ) , .p3095 ( optlc_net_3111 ) ,
+ .p3096 ( optlc_net_3112 ) , .p3097 ( optlc_net_3113 ) ,
+ .p3098 ( optlc_net_3114 ) , .p3099 ( optlc_net_3115 ) ,
+ .p3100 ( optlc_net_3116 ) , .p3101 ( optlc_net_3117 ) ,
+ .p3102 ( optlc_net_3118 ) , .p3103 ( optlc_net_3119 ) ,
+ .p3104 ( optlc_net_3120 ) , .p3105 ( optlc_net_3121 ) ,
+ .p3106 ( optlc_net_3122 ) , .p3107 ( optlc_net_3123 ) ,
+ .p3108 ( optlc_net_3124 ) , .p3109 ( optlc_net_3125 ) ,
+ .p3110 ( optlc_net_3126 ) , .p3111 ( optlc_net_3127 ) ,
+ .p3112 ( optlc_net_3128 ) , .p3113 ( optlc_net_3129 ) ,
+ .p3114 ( optlc_net_3130 ) , .p3115 ( optlc_net_3131 ) ,
+ .p3116 ( optlc_net_3132 ) , .p3117 ( optlc_net_3133 ) ,
+ .p3118 ( optlc_net_3134 ) , .p3119 ( optlc_net_3135 ) ,
+ .p3120 ( optlc_net_3136 ) , .p3121 ( optlc_net_3137 ) ,
+ .p3122 ( optlc_net_3138 ) , .p3123 ( optlc_net_3139 ) ,
+ .p3124 ( optlc_net_3140 ) , .p3125 ( optlc_net_3141 ) ,
+ .p3126 ( optlc_net_3142 ) , .p3127 ( optlc_net_3143 ) ,
+ .p3128 ( optlc_net_3144 ) , .p3129 ( optlc_net_3145 ) ,
+ .p3130 ( optlc_net_3146 ) , .p3131 ( optlc_net_3147 ) ,
+ .p3132 ( optlc_net_3148 ) , .p3133 ( optlc_net_3149 ) ,
+ .p3134 ( optlc_net_3150 ) , .p3135 ( optlc_net_3151 ) ,
+ .p3136 ( optlc_net_3152 ) , .p3137 ( optlc_net_3153 ) ,
+ .p3138 ( optlc_net_3154 ) , .p3139 ( optlc_net_3155 ) ,
+ .p3140 ( optlc_net_3156 ) , .p3141 ( optlc_net_3157 ) ,
+ .p3142 ( optlc_net_3158 ) , .p3143 ( optlc_net_3159 ) ,
+ .p3144 ( optlc_net_3160 ) , .p3145 ( optlc_net_3161 ) ,
+ .p3146 ( optlc_net_3162 ) , .p3147 ( optlc_net_3163 ) ,
+ .p3148 ( optlc_net_3164 ) , .p3149 ( optlc_net_3165 ) ,
+ .p3150 ( optlc_net_3166 ) , .p3151 ( optlc_net_3167 ) ,
+ .p3152 ( optlc_net_3168 ) , .p3153 ( optlc_net_3169 ) ,
+ .p3154 ( optlc_net_3170 ) , .p3155 ( optlc_net_3171 ) ,
+ .p3156 ( optlc_net_3172 ) , .p3157 ( optlc_net_3173 ) ,
+ .p3158 ( optlc_net_3174 ) , .p3159 ( optlc_net_3175 ) ,
+ .p3160 ( optlc_net_3176 ) , .p3161 ( optlc_net_3177 ) ,
+ .p3162 ( optlc_net_3178 ) , .p3163 ( optlc_net_3179 ) ,
+ .p3164 ( optlc_net_3180 ) , .p3165 ( optlc_net_3181 ) ,
+ .p3166 ( optlc_net_3182 ) , .p3167 ( optlc_net_3183 ) ,
+ .p3168 ( optlc_net_3184 ) , .p3169 ( optlc_net_3185 ) ,
+ .p3170 ( optlc_net_3186 ) , .p3171 ( optlc_net_3187 ) ,
+ .p3172 ( optlc_net_3188 ) , .p3173 ( optlc_net_3189 ) ,
+ .p3174 ( optlc_net_3190 ) , .p3175 ( optlc_net_3191 ) ,
+ .p3176 ( optlc_net_3192 ) , .p3177 ( optlc_net_3193 ) ,
+ .p3178 ( optlc_net_3194 ) , .p3179 ( optlc_net_3195 ) ,
+ .p3180 ( optlc_net_3196 ) , .p3181 ( optlc_net_3197 ) ,
+ .p3182 ( optlc_net_3198 ) , .p3183 ( optlc_net_3199 ) ,
+ .p3184 ( optlc_net_3200 ) , .p3185 ( optlc_net_3201 ) ,
+ .p3186 ( optlc_net_3202 ) , .p3187 ( optlc_net_3203 ) ,
+ .p3188 ( optlc_net_3204 ) , .p3189 ( optlc_net_3205 ) ,
+ .p3190 ( optlc_net_3206 ) , .p3191 ( optlc_net_3207 ) ,
+ .p3192 ( optlc_net_3208 ) , .p3193 ( optlc_net_3209 ) ,
+ .p3194 ( optlc_net_3210 ) , .p3195 ( optlc_net_3211 ) ,
+ .p3196 ( optlc_net_3212 ) , .p3197 ( optlc_net_3213 ) ,
+ .p3198 ( optlc_net_3214 ) , .p3199 ( optlc_net_3215 ) ,
+ .p3200 ( optlc_net_3216 ) , .p3201 ( optlc_net_3217 ) ,
+ .p3202 ( optlc_net_3218 ) , .p3203 ( optlc_net_3219 ) ,
+ .p3204 ( optlc_net_3220 ) , .p3205 ( optlc_net_3221 ) ,
+ .p3206 ( optlc_net_3222 ) , .p3207 ( optlc_net_3223 ) ,
+ .p3208 ( optlc_net_3224 ) , .p3209 ( optlc_net_3225 ) ,
+ .p3210 ( optlc_net_3226 ) , .p3211 ( optlc_net_3227 ) ,
+ .p3212 ( optlc_net_3228 ) , .p3213 ( optlc_net_3229 ) ,
+ .p3214 ( optlc_net_3230 ) , .p3215 ( optlc_net_3231 ) ,
+ .p3216 ( optlc_net_3232 ) , .p3217 ( optlc_net_3233 ) ,
+ .p3218 ( optlc_net_3234 ) , .p3219 ( optlc_net_3235 ) ,
+ .p3220 ( optlc_net_3236 ) , .p3221 ( optlc_net_3237 ) ,
+ .p3222 ( optlc_net_3238 ) , .p3223 ( optlc_net_3239 ) ,
+ .p3224 ( optlc_net_3240 ) , .p3225 ( optlc_net_3241 ) ,
+ .p3226 ( optlc_net_3242 ) , .p3227 ( optlc_net_3243 ) ,
+ .p3228 ( optlc_net_3244 ) , .p3229 ( optlc_net_3245 ) ,
+ .p3230 ( optlc_net_3246 ) , .p3231 ( optlc_net_3247 ) ,
+ .p3232 ( optlc_net_3248 ) , .p3233 ( optlc_net_3249 ) ,
+ .p3234 ( optlc_net_3250 ) , .p3235 ( optlc_net_3251 ) ,
+ .p3236 ( optlc_net_3252 ) , .p3237 ( optlc_net_3253 ) ,
+ .p3238 ( optlc_net_3254 ) , .p3239 ( optlc_net_3255 ) ,
+ .p3240 ( optlc_net_3256 ) , .p3241 ( optlc_net_3257 ) ,
+ .p3242 ( optlc_net_3258 ) , .p3243 ( optlc_net_3259 ) ,
+ .p3244 ( optlc_net_3260 ) , .p3245 ( optlc_net_3261 ) ,
+ .p3246 ( optlc_net_3262 ) , .p3247 ( optlc_net_3263 ) ,
+ .p3248 ( optlc_net_3264 ) , .p3249 ( optlc_net_3265 ) ,
+ .p3250 ( optlc_net_3266 ) , .p3251 ( optlc_net_3267 ) ,
+ .p3252 ( optlc_net_3268 ) , .p3253 ( optlc_net_3269 ) ,
+ .p3254 ( optlc_net_3270 ) , .p3255 ( optlc_net_3271 ) ,
+ .p3256 ( optlc_net_3272 ) , .p3257 ( optlc_net_3273 ) ,
+ .p3258 ( optlc_net_3274 ) , .p3259 ( optlc_net_3275 ) ,
+ .p3260 ( optlc_net_3276 ) , .p3261 ( optlc_net_3277 ) ,
+ .p3262 ( optlc_net_3278 ) , .p3263 ( optlc_net_3279 ) ,
+ .p3264 ( optlc_net_3280 ) , .p3265 ( optlc_net_3281 ) ,
+ .p3266 ( optlc_net_3282 ) , .p3267 ( optlc_net_3283 ) ,
+ .p3268 ( optlc_net_3284 ) , .p3269 ( optlc_net_3285 ) ,
+ .p3270 ( optlc_net_3286 ) , .p3271 ( optlc_net_3287 ) ,
+ .p3272 ( optlc_net_3288 ) , .p3273 ( optlc_net_3289 ) ,
+ .p3274 ( optlc_net_3290 ) , .p3275 ( optlc_net_3291 ) ,
+ .p3276 ( optlc_net_3292 ) , .p3277 ( optlc_net_3293 ) ,
+ .p3278 ( optlc_net_3294 ) , .p3279 ( optlc_net_3295 ) ,
+ .p3280 ( optlc_net_3296 ) , .p3281 ( optlc_net_3297 ) ,
+ .p3282 ( optlc_net_3298 ) , .p3283 ( optlc_net_3299 ) ,
+ .p3284 ( optlc_net_3300 ) , .p3285 ( optlc_net_3301 ) ,
+ .p3286 ( optlc_net_3302 ) , .p3287 ( optlc_net_3303 ) ,
+ .p3288 ( optlc_net_3304 ) , .p3289 ( optlc_net_3305 ) ,
+ .p3290 ( optlc_net_3306 ) , .p3291 ( optlc_net_3307 ) ,
+ .p3292 ( optlc_net_3308 ) , .p3293 ( optlc_net_3309 ) ,
+ .p3294 ( optlc_net_3310 ) , .p3295 ( optlc_net_3311 ) ,
+ .p3296 ( optlc_net_3312 ) , .p3297 ( optlc_net_3313 ) ,
+ .p3298 ( optlc_net_3314 ) , .p3299 ( optlc_net_3315 ) ,
+ .p3300 ( optlc_net_3316 ) , .p3301 ( optlc_net_3317 ) ,
+ .p3302 ( optlc_net_3318 ) , .p3303 ( optlc_net_3319 ) ,
+ .p3304 ( optlc_net_3320 ) , .p3305 ( optlc_net_3321 ) ,
+ .p3306 ( optlc_net_3322 ) , .p3307 ( optlc_net_3323 ) ,
+ .p3308 ( optlc_net_3324 ) , .p3309 ( optlc_net_3325 ) ,
+ .p3310 ( optlc_net_3326 ) , .p3311 ( optlc_net_3327 ) ,
+ .p3312 ( optlc_net_3328 ) , .p3313 ( optlc_net_3329 ) ,
+ .p3314 ( optlc_net_3330 ) , .p3315 ( optlc_net_3331 ) ,
+ .p3316 ( optlc_net_3332 ) , .p3317 ( optlc_net_3333 ) ,
+ .p3318 ( optlc_net_3334 ) , .p3319 ( optlc_net_3335 ) ,
+ .p3320 ( optlc_net_3336 ) , .p3321 ( optlc_net_3337 ) ,
+ .p3322 ( optlc_net_3338 ) , .p3323 ( optlc_net_3339 ) ,
+ .p3324 ( optlc_net_3340 ) , .p3325 ( optlc_net_3341 ) ,
+ .p3326 ( optlc_net_3342 ) , .p3327 ( optlc_net_3343 ) ,
+ .p3328 ( optlc_net_3344 ) , .p3329 ( optlc_net_3345 ) ,
+ .p3330 ( optlc_net_3346 ) , .p3331 ( optlc_net_3347 ) ,
+ .p3332 ( optlc_net_3348 ) , .p3333 ( optlc_net_3349 ) ,
+ .p3334 ( optlc_net_3350 ) , .p3335 ( optlc_net_3351 ) ,
+ .p3336 ( optlc_net_3352 ) , .p3337 ( optlc_net_3353 ) ,
+ .p3338 ( optlc_net_3354 ) , .p3339 ( optlc_net_3355 ) ,
+ .p3340 ( optlc_net_3356 ) , .p3341 ( optlc_net_3357 ) ,
+ .p3342 ( optlc_net_3358 ) , .p3343 ( optlc_net_3359 ) ,
+ .p3344 ( optlc_net_3360 ) , .p3345 ( optlc_net_3361 ) ,
+ .p3346 ( optlc_net_3362 ) , .p3347 ( optlc_net_3363 ) ,
+ .p3348 ( optlc_net_3364 ) , .p3349 ( optlc_net_3365 ) ,
+ .p3350 ( optlc_net_3366 ) , .p3351 ( optlc_net_3367 ) ,
+ .p3352 ( optlc_net_3368 ) , .p3353 ( optlc_net_3369 ) ,
+ .p3354 ( optlc_net_3370 ) , .p3355 ( optlc_net_3371 ) ,
+ .p3356 ( optlc_net_3372 ) , .p3357 ( optlc_net_3373 ) ,
+ .p3358 ( optlc_net_3374 ) , .p3359 ( optlc_net_3375 ) ,
+ .p3360 ( optlc_net_3376 ) , .p3361 ( optlc_net_3377 ) ,
+ .p3362 ( optlc_net_3378 ) , .p3363 ( optlc_net_3379 ) ,
+ .p3364 ( optlc_net_3380 ) , .p3365 ( optlc_net_3381 ) ,
+ .p3366 ( optlc_net_3382 ) , .p3367 ( optlc_net_3383 ) ,
+ .p3368 ( optlc_net_3384 ) , .p3369 ( optlc_net_3385 ) ,
+ .p3370 ( optlc_net_3386 ) , .p3371 ( optlc_net_3387 ) ,
+ .p3372 ( optlc_net_3388 ) , .p3373 ( optlc_net_3389 ) ,
+ .p3374 ( optlc_net_3390 ) , .p3375 ( optlc_net_3391 ) ,
+ .p3376 ( optlc_net_3392 ) , .p3377 ( optlc_net_3393 ) ,
+ .p3378 ( optlc_net_3394 ) , .p3379 ( optlc_net_3395 ) ,
+ .p3380 ( optlc_net_3396 ) , .p3381 ( optlc_net_3397 ) ,
+ .p3382 ( optlc_net_3398 ) , .p3383 ( optlc_net_3399 ) ,
+ .p3384 ( optlc_net_3400 ) , .p3385 ( optlc_net_3401 ) ,
+ .p3386 ( optlc_net_3402 ) , .p3387 ( optlc_net_3403 ) ,
+ .p3388 ( optlc_net_3404 ) , .p3389 ( optlc_net_3405 ) ,
+ .p3390 ( optlc_net_3406 ) , .p3391 ( optlc_net_3407 ) ,
+ .p3392 ( optlc_net_3408 ) , .p3393 ( optlc_net_3409 ) ,
+ .p3394 ( optlc_net_3410 ) , .p3395 ( optlc_net_3411 ) ,
+ .p3396 ( optlc_net_3412 ) , .p3397 ( optlc_net_3413 ) ,
+ .p3398 ( optlc_net_3414 ) , .p3399 ( optlc_net_3415 ) ,
+ .p3400 ( optlc_net_3416 ) , .p3401 ( optlc_net_3417 ) ,
+ .p3402 ( optlc_net_3418 ) , .p3403 ( optlc_net_3419 ) ,
+ .p3404 ( optlc_net_3420 ) , .p3405 ( optlc_net_3421 ) ,
+ .p3406 ( optlc_net_3422 ) , .p3407 ( optlc_net_3423 ) ,
+ .p3408 ( optlc_net_3424 ) , .p3409 ( optlc_net_3425 ) ,
+ .p3410 ( optlc_net_3426 ) , .p3411 ( optlc_net_3427 ) ,
+ .p3412 ( optlc_net_3428 ) , .p3413 ( optlc_net_3429 ) ,
+ .p3414 ( optlc_net_3430 ) , .p3415 ( optlc_net_3431 ) ,
+ .p3416 ( optlc_net_3432 ) , .p3417 ( optlc_net_3433 ) ,
+ .p3418 ( optlc_net_3434 ) , .p3419 ( optlc_net_3435 ) ,
+ .p3420 ( optlc_net_3436 ) , .p3421 ( optlc_net_3437 ) ,
+ .p3422 ( optlc_net_3438 ) , .p3423 ( optlc_net_3439 ) ,
+ .p3424 ( optlc_net_3440 ) , .p3425 ( optlc_net_3441 ) ,
+ .p3426 ( optlc_net_3442 ) , .p3427 ( optlc_net_3443 ) ,
+ .p3428 ( optlc_net_3444 ) , .p3429 ( optlc_net_3445 ) ,
+ .p3430 ( optlc_net_3446 ) , .p3431 ( optlc_net_3447 ) ,
+ .p3432 ( optlc_net_3448 ) , .p3433 ( optlc_net_3449 ) ,
+ .p3434 ( optlc_net_3450 ) , .p3435 ( optlc_net_3451 ) ,
+ .p3436 ( optlc_net_3452 ) , .p3437 ( optlc_net_3453 ) ,
+ .p3438 ( optlc_net_3454 ) , .p3439 ( optlc_net_3455 ) ,
+ .p3440 ( optlc_net_3456 ) , .p3441 ( optlc_net_3457 ) ,
+ .p3442 ( optlc_net_3458 ) , .p3443 ( optlc_net_3459 ) ,
+ .p3444 ( optlc_net_3460 ) , .p3445 ( optlc_net_3461 ) ,
+ .p3446 ( optlc_net_3462 ) , .p3447 ( optlc_net_3463 ) ,
+ .p3448 ( optlc_net_3464 ) , .p3449 ( optlc_net_3465 ) ,
+ .p3450 ( optlc_net_3466 ) , .p3451 ( optlc_net_3467 ) ,
+ .p3452 ( optlc_net_3468 ) , .p3453 ( optlc_net_3469 ) ,
+ .p3454 ( optlc_net_3470 ) , .p3455 ( optlc_net_3471 ) ,
+ .p3456 ( optlc_net_3472 ) , .p3457 ( optlc_net_3473 ) ,
+ .p3458 ( optlc_net_3474 ) , .p3459 ( optlc_net_3475 ) ,
+ .p3460 ( optlc_net_3476 ) , .p3461 ( optlc_net_3477 ) ,
+ .p3462 ( optlc_net_3478 ) , .p3463 ( optlc_net_3479 ) ,
+ .p3464 ( optlc_net_3480 ) , .p3465 ( optlc_net_3481 ) ,
+ .p3466 ( optlc_net_3482 ) , .p3467 ( optlc_net_3483 ) ,
+ .p3468 ( optlc_net_3484 ) , .p3469 ( optlc_net_3485 ) ,
+ .p3470 ( optlc_net_3486 ) , .p3471 ( optlc_net_3487 ) ,
+ .p3472 ( optlc_net_3488 ) , .p3473 ( optlc_net_3489 ) ,
+ .p3474 ( optlc_net_3490 ) , .p3475 ( optlc_net_3491 ) ,
+ .p3476 ( optlc_net_3492 ) , .p3477 ( optlc_net_3493 ) ,
+ .p3478 ( optlc_net_3494 ) , .p3479 ( optlc_net_3495 ) ,
+ .p3480 ( optlc_net_3496 ) , .p3481 ( optlc_net_3497 ) ,
+ .p3482 ( optlc_net_3498 ) , .p3483 ( optlc_net_3499 ) ,
+ .p3484 ( optlc_net_3500 ) , .p3485 ( optlc_net_3501 ) ,
+ .p3486 ( optlc_net_3502 ) , .p3487 ( optlc_net_3503 ) ,
+ .p3488 ( optlc_net_3504 ) , .p3489 ( optlc_net_3505 ) ,
+ .p3490 ( optlc_net_3506 ) , .p3491 ( optlc_net_3507 ) ,
+ .p3492 ( optlc_net_3508 ) , .p3493 ( optlc_net_3509 ) ,
+ .p3494 ( optlc_net_3510 ) , .p3495 ( optlc_net_3511 ) ,
+ .p3496 ( optlc_net_3512 ) , .p3497 ( optlc_net_3513 ) ,
+ .p3498 ( optlc_net_3514 ) , .p3499 ( optlc_net_3515 ) ,
+ .p3500 ( optlc_net_3516 ) , .p3501 ( optlc_net_3517 ) ,
+ .p3502 ( optlc_net_3518 ) , .p3503 ( optlc_net_3519 ) ,
+ .p3504 ( optlc_net_3520 ) , .p3505 ( optlc_net_3521 ) ,
+ .p3506 ( optlc_net_3522 ) , .p3507 ( optlc_net_3523 ) ,
+ .p3508 ( optlc_net_3524 ) , .p3509 ( optlc_net_3525 ) ,
+ .p3510 ( optlc_net_3526 ) , .p3511 ( optlc_net_3527 ) ,
+ .p3512 ( optlc_net_3528 ) , .p3513 ( optlc_net_3529 ) ,
+ .p3514 ( optlc_net_3530 ) , .p3515 ( optlc_net_3531 ) ,
+ .p3516 ( optlc_net_3532 ) , .p3517 ( optlc_net_3533 ) ,
+ .p3518 ( optlc_net_3534 ) , .p3519 ( optlc_net_3535 ) ,
+ .p3520 ( optlc_net_3536 ) , .p3521 ( optlc_net_3537 ) ,
+ .p3522 ( optlc_net_3538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( io_oeb[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( io_oeb[1] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( io_oeb[12] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( io_oeb[25] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .HI ( io_oeb[26] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .HI ( io_oeb[36] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .HI ( io_oeb[37] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( io_oeb[11] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_9 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( io_oeb[35] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_10 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_out[0] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_out[1] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[12] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[25] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[26] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[36] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[37] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( optlc_net_16 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( optlc_net_17 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( optlc_net_18 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_20 ( .LO ( optlc_net_19 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_39 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_40 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_41 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_42 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_43 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_44 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_46 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_47 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_48 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_74 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( optlc_net_75 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( optlc_net_76 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( optlc_net_77 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_79 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( optlc_net_78 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_80 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( optlc_net_79 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_81 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( optlc_net_80 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_82 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( optlc_net_81 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( optlc_net_82 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( optlc_net_83 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( optlc_net_84 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_86 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( optlc_net_85 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_87 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_87 ( .LO ( optlc_net_86 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( optlc_net_87 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( optlc_net_88 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( optlc_net_89 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( optlc_net_90 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( optlc_net_91 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( optlc_net_92 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( optlc_net_93 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( optlc_net_94 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( optlc_net_95 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( optlc_net_96 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( optlc_net_97 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( optlc_net_98 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( optlc_net_99 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( optlc_net_100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( optlc_net_101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( optlc_net_102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( optlc_net_103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( optlc_net_104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( optlc_net_105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( optlc_net_106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( optlc_net_107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( optlc_net_108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( optlc_net_109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( optlc_net_110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( optlc_net_111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( optlc_net_112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( optlc_net_113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( optlc_net_114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( optlc_net_115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( optlc_net_116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( optlc_net_117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( optlc_net_118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( optlc_net_119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( optlc_net_120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( optlc_net_121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( optlc_net_122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( optlc_net_123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( optlc_net_124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( optlc_net_125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( optlc_net_126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( optlc_net_127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( optlc_net_128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( optlc_net_129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( optlc_net_130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( optlc_net_131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( optlc_net_132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( optlc_net_133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( optlc_net_134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( optlc_net_135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( optlc_net_136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( optlc_net_137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( optlc_net_138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( optlc_net_139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( optlc_net_140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( optlc_net_141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( optlc_net_142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( optlc_net_143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( optlc_net_144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( optlc_net_145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( optlc_net_146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( optlc_net_147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( optlc_net_148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( optlc_net_149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( optlc_net_150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( optlc_net_151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( optlc_net_152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( optlc_net_153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( optlc_net_154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( optlc_net_155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( optlc_net_156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( optlc_net_157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( optlc_net_158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( optlc_net_159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( optlc_net_160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( optlc_net_161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_163 ( .LO ( optlc_net_162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( optlc_net_163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( optlc_net_164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( optlc_net_165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( optlc_net_166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( optlc_net_167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_169 ( .LO ( optlc_net_168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( optlc_net_169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( optlc_net_170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( optlc_net_171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( optlc_net_172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( optlc_net_173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( optlc_net_174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( optlc_net_175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( optlc_net_176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( optlc_net_177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( optlc_net_178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( optlc_net_179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( optlc_net_180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( optlc_net_181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_183 ( .LO ( optlc_net_182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( optlc_net_183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( optlc_net_184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( optlc_net_185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( optlc_net_186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( optlc_net_187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( optlc_net_188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( optlc_net_189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( optlc_net_190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( optlc_net_191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( optlc_net_192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( optlc_net_193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( optlc_net_194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( optlc_net_195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( optlc_net_196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_198 ( .LO ( optlc_net_197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( optlc_net_198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( optlc_net_199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( optlc_net_200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( optlc_net_201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( optlc_net_202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( optlc_net_203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( optlc_net_204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( optlc_net_205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( optlc_net_206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( optlc_net_207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( optlc_net_208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( optlc_net_209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( optlc_net_210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( optlc_net_211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( optlc_net_212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( optlc_net_213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( optlc_net_214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( optlc_net_215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( optlc_net_216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( optlc_net_217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( optlc_net_218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( optlc_net_219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( optlc_net_220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( optlc_net_221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( optlc_net_222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( optlc_net_223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( optlc_net_224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( optlc_net_225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( optlc_net_226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( optlc_net_227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( optlc_net_228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( optlc_net_229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_231 ( .LO ( optlc_net_230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( optlc_net_231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( optlc_net_232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_234 ( .LO ( optlc_net_233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( optlc_net_234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_236 ( .LO ( optlc_net_235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( optlc_net_236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_238 ( .LO ( optlc_net_237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( optlc_net_238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_240 ( .LO ( optlc_net_239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_241 ( .LO ( optlc_net_240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_242 ( .LO ( optlc_net_241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_243 ( .LO ( optlc_net_242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_244 ( .LO ( optlc_net_243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_245 ( .LO ( optlc_net_244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_246 ( .LO ( optlc_net_245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_247 ( .LO ( optlc_net_246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_248 ( .LO ( optlc_net_247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_249 ( .LO ( optlc_net_248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_250 ( .LO ( optlc_net_249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_251 ( .LO ( optlc_net_250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_252 ( .LO ( optlc_net_251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_253 ( .LO ( optlc_net_252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_254 ( .LO ( optlc_net_253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_255 ( .LO ( optlc_net_254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_256 ( .LO ( optlc_net_255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_257 ( .LO ( optlc_net_256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_258 ( .LO ( optlc_net_257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_259 ( .LO ( optlc_net_258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_260 ( .LO ( optlc_net_259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_261 ( .LO ( optlc_net_260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_262 ( .LO ( optlc_net_261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_263 ( .LO ( optlc_net_262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_264 ( .LO ( optlc_net_263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_265 ( .LO ( optlc_net_264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_266 ( .LO ( optlc_net_265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_267 ( .LO ( optlc_net_266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_268 ( .LO ( optlc_net_267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_269 ( .LO ( optlc_net_268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_274 ( .LO ( optlc_net_273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_280 ( .LO ( optlc_net_279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_284 ( .LO ( optlc_net_283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_295 ( .LO ( optlc_net_294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_298 ( .LO ( optlc_net_297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_311 ( .LO ( optlc_net_310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_313 ( .LO ( optlc_net_312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_315 ( .LO ( optlc_net_314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_327 ( .LO ( optlc_net_326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_330 ( .LO ( optlc_net_329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_334 ( .LO ( optlc_net_333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_336 ( .LO ( optlc_net_335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_342 ( .LO ( optlc_net_341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_351 ( .LO ( optlc_net_350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_353 ( .LO ( optlc_net_352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_355 ( .LO ( optlc_net_354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_361 ( .LO ( optlc_net_360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_365 ( .LO ( optlc_net_364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_367 ( .LO ( optlc_net_366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_401 ( .LO ( optlc_net_400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_403 ( .LO ( optlc_net_402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_413 ( .LO ( optlc_net_412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_415 ( .LO ( optlc_net_414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_751 ( .LO ( optlc_net_749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_935 ( .LO ( optlc_net_931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_937 ( .LO ( optlc_net_933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_939 ( .LO ( optlc_net_935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_943 ( .LO ( optlc_net_939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_944 ( .LO ( optlc_net_940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_966 ( .LO ( optlc_net_961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_971 ( .LO ( optlc_net_965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_977 ( .LO ( optlc_net_971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_982 ( .LO ( optlc_net_976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_986 ( .LO ( optlc_net_980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_990 ( .LO ( optlc_net_984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_996 ( .LO ( optlc_net_990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1003 ( .LO ( optlc_net_997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1005 ( .LO ( optlc_net_999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_1000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_1001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_1002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1009 ( .LO ( optlc_net_1003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_1004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1011 ( .LO ( optlc_net_1005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1012 ( .LO ( optlc_net_1006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_1007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1014 ( .LO ( optlc_net_1008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1015 ( .LO ( optlc_net_1009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1016 ( .LO ( optlc_net_1010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1017 ( .LO ( optlc_net_1011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1018 ( .LO ( optlc_net_1012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1019 ( .LO ( optlc_net_1013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1020 ( .LO ( optlc_net_1014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1021 ( .LO ( optlc_net_1015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1022 ( .LO ( optlc_net_1016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1023 ( .LO ( optlc_net_1017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1024 ( .LO ( optlc_net_1018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1025 ( .LO ( optlc_net_1019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1026 ( .LO ( optlc_net_1020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1027 ( .LO ( optlc_net_1021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1028 ( .LO ( optlc_net_1022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1029 ( .LO ( optlc_net_1023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1030 ( .LO ( optlc_net_1024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1031 ( .LO ( optlc_net_1025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1032 ( .LO ( optlc_net_1026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1033 ( .LO ( optlc_net_1027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1034 ( .LO ( optlc_net_1028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1035 ( .LO ( optlc_net_1029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1036 ( .LO ( optlc_net_1030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1037 ( .LO ( optlc_net_1031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1038 ( .LO ( optlc_net_1032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1039 ( .LO ( optlc_net_1033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1040 ( .LO ( optlc_net_1034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1041 ( .LO ( optlc_net_1035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1042 ( .LO ( optlc_net_1036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1044 ( .LO ( optlc_net_1037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1045 ( .LO ( optlc_net_1038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1046 ( .LO ( optlc_net_1039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1047 ( .LO ( optlc_net_1040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1048 ( .LO ( optlc_net_1041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1049 ( .LO ( optlc_net_1042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1050 ( .LO ( optlc_net_1043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1051 ( .LO ( optlc_net_1044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1052 ( .LO ( optlc_net_1045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1053 ( .LO ( optlc_net_1046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1054 ( .LO ( optlc_net_1047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1055 ( .LO ( optlc_net_1048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1056 ( .LO ( optlc_net_1049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1057 ( .LO ( optlc_net_1050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1058 ( .LO ( optlc_net_1051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1059 ( .LO ( optlc_net_1052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1060 ( .LO ( optlc_net_1053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1061 ( .LO ( optlc_net_1054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1062 ( .LO ( optlc_net_1055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1063 ( .LO ( optlc_net_1056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1064 ( .LO ( optlc_net_1057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1065 ( .LO ( optlc_net_1058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1066 ( .LO ( optlc_net_1059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1067 ( .LO ( optlc_net_1060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1068 ( .LO ( optlc_net_1061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1069 ( .LO ( optlc_net_1062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1070 ( .LO ( optlc_net_1063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1072 ( .LO ( optlc_net_1064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1073 ( .LO ( optlc_net_1065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1074 ( .LO ( optlc_net_1066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1075 ( .LO ( optlc_net_1067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1077 ( .LO ( optlc_net_1068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1078 ( .LO ( optlc_net_1069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1079 ( .LO ( optlc_net_1070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1080 ( .LO ( optlc_net_1071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1081 ( .LO ( optlc_net_1072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1082 ( .LO ( optlc_net_1073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1083 ( .LO ( optlc_net_1074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1084 ( .LO ( optlc_net_1075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1085 ( .LO ( optlc_net_1076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1086 ( .LO ( optlc_net_1077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1087 ( .LO ( optlc_net_1078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1088 ( .LO ( optlc_net_1079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1089 ( .LO ( optlc_net_1080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1090 ( .LO ( optlc_net_1081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1091 ( .LO ( optlc_net_1082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1092 ( .LO ( optlc_net_1083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1093 ( .LO ( optlc_net_1084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1094 ( .LO ( optlc_net_1085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1095 ( .LO ( optlc_net_1086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1096 ( .LO ( optlc_net_1087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1097 ( .LO ( optlc_net_1088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1098 ( .LO ( optlc_net_1089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1099 ( .LO ( optlc_net_1090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1100 ( .LO ( optlc_net_1091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1101 ( .LO ( optlc_net_1092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1102 ( .LO ( optlc_net_1093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1103 ( .LO ( optlc_net_1094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1104 ( .LO ( optlc_net_1095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1105 ( .LO ( optlc_net_1096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1106 ( .LO ( optlc_net_1097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1107 ( .LO ( optlc_net_1098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1108 ( .LO ( optlc_net_1099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1109 ( .LO ( optlc_net_1100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1110 ( .LO ( optlc_net_1101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1111 ( .LO ( optlc_net_1102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1112 ( .LO ( optlc_net_1103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1113 ( .LO ( optlc_net_1104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1114 ( .LO ( optlc_net_1105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1115 ( .LO ( optlc_net_1106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1116 ( .LO ( optlc_net_1107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1117 ( .LO ( optlc_net_1108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1118 ( .LO ( optlc_net_1109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1119 ( .LO ( optlc_net_1110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1120 ( .LO ( optlc_net_1111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1121 ( .LO ( optlc_net_1112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1122 ( .LO ( optlc_net_1113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1123 ( .LO ( optlc_net_1114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1124 ( .LO ( optlc_net_1115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1125 ( .LO ( optlc_net_1116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1126 ( .LO ( optlc_net_1117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1127 ( .LO ( optlc_net_1118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1128 ( .LO ( optlc_net_1119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1129 ( .LO ( optlc_net_1120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1130 ( .LO ( optlc_net_1121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1131 ( .LO ( optlc_net_1122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1132 ( .LO ( optlc_net_1123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1133 ( .LO ( optlc_net_1124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1134 ( .LO ( optlc_net_1125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1135 ( .LO ( optlc_net_1126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1136 ( .LO ( optlc_net_1127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1137 ( .LO ( optlc_net_1128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1138 ( .LO ( optlc_net_1129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1139 ( .LO ( optlc_net_1130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1140 ( .LO ( optlc_net_1131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1141 ( .LO ( optlc_net_1132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1142 ( .LO ( optlc_net_1133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1143 ( .LO ( optlc_net_1134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1144 ( .LO ( optlc_net_1135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1145 ( .LO ( optlc_net_1136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1146 ( .LO ( optlc_net_1137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1147 ( .LO ( optlc_net_1138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1148 ( .LO ( optlc_net_1139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1149 ( .LO ( optlc_net_1140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1150 ( .LO ( optlc_net_1141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1151 ( .LO ( optlc_net_1142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1152 ( .LO ( optlc_net_1143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1154 ( .LO ( optlc_net_1144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1155 ( .LO ( optlc_net_1145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1156 ( .LO ( optlc_net_1146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1157 ( .LO ( optlc_net_1147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1158 ( .LO ( optlc_net_1148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1159 ( .LO ( optlc_net_1149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1160 ( .LO ( optlc_net_1150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1161 ( .LO ( optlc_net_1151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1162 ( .LO ( optlc_net_1152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1163 ( .LO ( optlc_net_1153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1164 ( .LO ( optlc_net_1154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1165 ( .LO ( optlc_net_1155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1166 ( .LO ( optlc_net_1156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1167 ( .LO ( optlc_net_1157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1168 ( .LO ( optlc_net_1158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1169 ( .LO ( optlc_net_1159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1170 ( .LO ( optlc_net_1160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1171 ( .LO ( optlc_net_1161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1172 ( .LO ( optlc_net_1162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1173 ( .LO ( optlc_net_1163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1174 ( .LO ( optlc_net_1164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1175 ( .LO ( optlc_net_1165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1176 ( .LO ( optlc_net_1166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1177 ( .LO ( optlc_net_1167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1178 ( .LO ( optlc_net_1168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1179 ( .LO ( optlc_net_1169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1180 ( .LO ( optlc_net_1170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1181 ( .LO ( optlc_net_1171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1182 ( .LO ( optlc_net_1172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1183 ( .LO ( optlc_net_1173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1184 ( .LO ( optlc_net_1174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1185 ( .LO ( optlc_net_1175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1186 ( .LO ( optlc_net_1176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1187 ( .LO ( optlc_net_1177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1188 ( .LO ( optlc_net_1178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1189 ( .LO ( optlc_net_1179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1190 ( .LO ( optlc_net_1180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1191 ( .LO ( optlc_net_1181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1192 ( .LO ( optlc_net_1182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1193 ( .LO ( optlc_net_1183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1194 ( .LO ( optlc_net_1184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1195 ( .LO ( optlc_net_1185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1196 ( .LO ( optlc_net_1186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1197 ( .LO ( optlc_net_1187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1198 ( .LO ( optlc_net_1188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1199 ( .LO ( optlc_net_1189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1200 ( .LO ( optlc_net_1190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1201 ( .LO ( optlc_net_1191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1202 ( .LO ( optlc_net_1192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1203 ( .LO ( optlc_net_1193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1204 ( .LO ( optlc_net_1194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1205 ( .LO ( optlc_net_1195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1207 ( .LO ( optlc_net_1196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1208 ( .LO ( optlc_net_1197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1209 ( .LO ( optlc_net_1198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1210 ( .LO ( optlc_net_1199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1211 ( .LO ( optlc_net_1200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1212 ( .LO ( optlc_net_1201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1213 ( .LO ( optlc_net_1202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1214 ( .LO ( optlc_net_1203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1215 ( .LO ( optlc_net_1204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1216 ( .LO ( optlc_net_1205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1217 ( .LO ( optlc_net_1206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1218 ( .LO ( optlc_net_1207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1219 ( .LO ( optlc_net_1208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1220 ( .LO ( optlc_net_1209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1221 ( .LO ( optlc_net_1210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1222 ( .LO ( optlc_net_1211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1223 ( .LO ( optlc_net_1212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1224 ( .LO ( optlc_net_1213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1225 ( .LO ( optlc_net_1214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1226 ( .LO ( optlc_net_1215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1227 ( .LO ( optlc_net_1216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1228 ( .LO ( optlc_net_1217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1229 ( .LO ( optlc_net_1218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1230 ( .LO ( optlc_net_1219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1231 ( .LO ( optlc_net_1220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1232 ( .LO ( optlc_net_1221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1233 ( .LO ( optlc_net_1222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1234 ( .LO ( optlc_net_1223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1235 ( .LO ( optlc_net_1224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1236 ( .LO ( optlc_net_1225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1237 ( .LO ( optlc_net_1226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1238 ( .LO ( optlc_net_1227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1239 ( .LO ( optlc_net_1228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1241 ( .LO ( optlc_net_1229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1243 ( .LO ( optlc_net_1230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1244 ( .LO ( optlc_net_1231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1245 ( .LO ( optlc_net_1232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1246 ( .LO ( optlc_net_1233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1247 ( .LO ( optlc_net_1234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1248 ( .LO ( optlc_net_1235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1250 ( .LO ( optlc_net_1236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1252 ( .LO ( optlc_net_1237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1253 ( .LO ( optlc_net_1238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1254 ( .LO ( optlc_net_1239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1255 ( .LO ( optlc_net_1240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1257 ( .LO ( optlc_net_1241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1258 ( .LO ( optlc_net_1242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1260 ( .LO ( optlc_net_1243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1261 ( .LO ( optlc_net_1244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1262 ( .LO ( optlc_net_1245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1263 ( .LO ( optlc_net_1246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1264 ( .LO ( optlc_net_1247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1265 ( .LO ( optlc_net_1248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1266 ( .LO ( optlc_net_1249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1267 ( .LO ( optlc_net_1250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1268 ( .LO ( optlc_net_1251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1269 ( .LO ( optlc_net_1252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1270 ( .LO ( optlc_net_1253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1271 ( .LO ( optlc_net_1254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1272 ( .LO ( optlc_net_1255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1273 ( .LO ( optlc_net_1256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1274 ( .LO ( optlc_net_1257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1276 ( .LO ( optlc_net_1258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1277 ( .LO ( optlc_net_1259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1278 ( .LO ( optlc_net_1260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1280 ( .LO ( optlc_net_1261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1281 ( .LO ( optlc_net_1262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1282 ( .LO ( optlc_net_1263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1283 ( .LO ( optlc_net_1264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1284 ( .LO ( optlc_net_1265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1285 ( .LO ( optlc_net_1266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1286 ( .LO ( optlc_net_1267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1287 ( .LO ( optlc_net_1268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1288 ( .LO ( optlc_net_1269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1289 ( .LO ( optlc_net_1270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1290 ( .LO ( optlc_net_1271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1291 ( .LO ( optlc_net_1272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1292 ( .LO ( optlc_net_1273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1293 ( .LO ( optlc_net_1274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1294 ( .LO ( optlc_net_1275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1295 ( .LO ( optlc_net_1276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1296 ( .LO ( optlc_net_1277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1297 ( .LO ( optlc_net_1278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1298 ( .LO ( optlc_net_1279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1299 ( .LO ( optlc_net_1280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1300 ( .LO ( optlc_net_1281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1301 ( .LO ( optlc_net_1282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1302 ( .LO ( optlc_net_1283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1303 ( .LO ( optlc_net_1284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1304 ( .LO ( optlc_net_1285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1305 ( .LO ( optlc_net_1286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1306 ( .LO ( optlc_net_1287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1307 ( .LO ( optlc_net_1288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1308 ( .LO ( optlc_net_1289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1309 ( .LO ( optlc_net_1290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1310 ( .LO ( optlc_net_1291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1311 ( .LO ( optlc_net_1292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1312 ( .LO ( optlc_net_1293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1313 ( .LO ( optlc_net_1294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1314 ( .LO ( optlc_net_1295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1315 ( .LO ( optlc_net_1296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1316 ( .LO ( optlc_net_1297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1317 ( .LO ( optlc_net_1298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1318 ( .LO ( optlc_net_1299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1319 ( .LO ( optlc_net_1300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1320 ( .LO ( optlc_net_1301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1321 ( .LO ( optlc_net_1302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1322 ( .LO ( optlc_net_1303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1323 ( .LO ( optlc_net_1304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1324 ( .LO ( optlc_net_1305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1326 ( .LO ( optlc_net_1306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1327 ( .LO ( optlc_net_1307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1328 ( .LO ( optlc_net_1308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1329 ( .LO ( optlc_net_1309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1330 ( .LO ( optlc_net_1310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1331 ( .LO ( optlc_net_1311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1332 ( .LO ( optlc_net_1312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1333 ( .LO ( optlc_net_1313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1334 ( .LO ( optlc_net_1314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1335 ( .LO ( optlc_net_1315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1336 ( .LO ( optlc_net_1316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1337 ( .LO ( optlc_net_1317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1338 ( .LO ( optlc_net_1318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1339 ( .LO ( optlc_net_1319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1340 ( .LO ( optlc_net_1320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1342 ( .LO ( optlc_net_1321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1343 ( .LO ( optlc_net_1322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1344 ( .LO ( optlc_net_1323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1345 ( .LO ( optlc_net_1324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1346 ( .LO ( optlc_net_1325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1347 ( .LO ( optlc_net_1326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1348 ( .LO ( optlc_net_1327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1350 ( .LO ( optlc_net_1328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1351 ( .LO ( optlc_net_1329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1352 ( .LO ( optlc_net_1330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1353 ( .LO ( optlc_net_1331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1354 ( .LO ( optlc_net_1332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1355 ( .LO ( optlc_net_1333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1356 ( .LO ( optlc_net_1334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1357 ( .LO ( optlc_net_1335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1358 ( .LO ( optlc_net_1336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1359 ( .LO ( optlc_net_1337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1360 ( .LO ( optlc_net_1338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1361 ( .LO ( optlc_net_1339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1362 ( .LO ( optlc_net_1340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1363 ( .LO ( optlc_net_1341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1364 ( .LO ( optlc_net_1342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1365 ( .LO ( optlc_net_1343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1366 ( .LO ( optlc_net_1344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1367 ( .LO ( optlc_net_1345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1368 ( .LO ( optlc_net_1346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1369 ( .LO ( optlc_net_1347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1370 ( .LO ( optlc_net_1348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1371 ( .LO ( optlc_net_1349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1372 ( .LO ( optlc_net_1350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1373 ( .LO ( optlc_net_1351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1374 ( .LO ( optlc_net_1352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1375 ( .LO ( optlc_net_1353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1376 ( .LO ( optlc_net_1354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1377 ( .LO ( optlc_net_1355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1378 ( .LO ( optlc_net_1356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1379 ( .LO ( optlc_net_1357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1380 ( .LO ( optlc_net_1358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1381 ( .LO ( optlc_net_1359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1382 ( .LO ( optlc_net_1360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1383 ( .LO ( optlc_net_1361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1384 ( .LO ( optlc_net_1362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1385 ( .LO ( optlc_net_1363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1387 ( .LO ( optlc_net_1364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1388 ( .LO ( optlc_net_1365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1389 ( .LO ( optlc_net_1366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1391 ( .LO ( optlc_net_1367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1393 ( .LO ( optlc_net_1368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1394 ( .LO ( optlc_net_1369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1395 ( .LO ( optlc_net_1370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1396 ( .LO ( optlc_net_1371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1397 ( .LO ( optlc_net_1372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1398 ( .LO ( optlc_net_1373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1399 ( .LO ( optlc_net_1374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1400 ( .LO ( optlc_net_1375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1401 ( .LO ( optlc_net_1376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1402 ( .LO ( optlc_net_1377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1404 ( .LO ( optlc_net_1378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1405 ( .LO ( optlc_net_1379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1406 ( .LO ( optlc_net_1380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1407 ( .LO ( optlc_net_1381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1408 ( .LO ( optlc_net_1382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1409 ( .LO ( optlc_net_1383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1411 ( .LO ( optlc_net_1384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1412 ( .LO ( optlc_net_1385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1414 ( .LO ( optlc_net_1386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1416 ( .LO ( optlc_net_1387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1417 ( .LO ( optlc_net_1388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1418 ( .LO ( optlc_net_1389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1419 ( .LO ( optlc_net_1390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1420 ( .LO ( optlc_net_1391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1421 ( .LO ( optlc_net_1392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1422 ( .LO ( optlc_net_1393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1424 ( .LO ( optlc_net_1394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1425 ( .LO ( optlc_net_1395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1426 ( .LO ( optlc_net_1396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1427 ( .LO ( optlc_net_1397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1428 ( .LO ( optlc_net_1398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1429 ( .LO ( optlc_net_1399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1430 ( .LO ( optlc_net_1400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1431 ( .LO ( optlc_net_1401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1433 ( .LO ( optlc_net_1402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1434 ( .LO ( optlc_net_1403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1436 ( .LO ( optlc_net_1404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1437 ( .LO ( optlc_net_1405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1438 ( .LO ( optlc_net_1406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1439 ( .LO ( optlc_net_1407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1440 ( .LO ( optlc_net_1408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1442 ( .LO ( optlc_net_1409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1443 ( .LO ( optlc_net_1410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1444 ( .LO ( optlc_net_1411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1446 ( .LO ( optlc_net_1412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1447 ( .LO ( optlc_net_1413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1448 ( .LO ( optlc_net_1414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1450 ( .LO ( optlc_net_1415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1452 ( .LO ( optlc_net_1416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1453 ( .LO ( optlc_net_1417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1454 ( .LO ( optlc_net_1418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1455 ( .LO ( optlc_net_1419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1457 ( .LO ( optlc_net_1420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1459 ( .LO ( optlc_net_1421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1460 ( .LO ( optlc_net_1422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1463 ( .LO ( optlc_net_1424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1467 ( .LO ( optlc_net_1427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1468 ( .LO ( optlc_net_1428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1469 ( .LO ( optlc_net_1429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1471 ( .LO ( optlc_net_1430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1474 ( .LO ( optlc_net_1432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1475 ( .LO ( optlc_net_1433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1477 ( .LO ( optlc_net_1434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1478 ( .LO ( optlc_net_1435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1479 ( .LO ( optlc_net_1436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1480 ( .LO ( optlc_net_1437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1482 ( .LO ( optlc_net_1438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1486 ( .LO ( optlc_net_1441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1488 ( .LO ( optlc_net_1442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1491 ( .LO ( optlc_net_1445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1492 ( .LO ( optlc_net_1446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1493 ( .LO ( optlc_net_1447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1494 ( .LO ( optlc_net_1448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1496 ( .LO ( optlc_net_1449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1497 ( .LO ( optlc_net_1450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1499 ( .LO ( optlc_net_1451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1501 ( .LO ( optlc_net_1452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1502 ( .LO ( optlc_net_1453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1503 ( .LO ( optlc_net_1454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1505 ( .LO ( optlc_net_1455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1506 ( .LO ( optlc_net_1456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1507 ( .LO ( optlc_net_1457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1508 ( .LO ( optlc_net_1458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1509 ( .LO ( optlc_net_1459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1510 ( .LO ( optlc_net_1460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1512 ( .LO ( optlc_net_1461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1513 ( .LO ( optlc_net_1462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1514 ( .LO ( optlc_net_1463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1515 ( .LO ( optlc_net_1464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1516 ( .LO ( optlc_net_1465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1517 ( .LO ( optlc_net_1466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1518 ( .LO ( optlc_net_1467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1519 ( .LO ( optlc_net_1468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1521 ( .LO ( optlc_net_1469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1523 ( .LO ( optlc_net_1470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1524 ( .LO ( optlc_net_1471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1525 ( .LO ( optlc_net_1472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1527 ( .LO ( optlc_net_1473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1528 ( .LO ( optlc_net_1474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1529 ( .LO ( optlc_net_1475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1530 ( .LO ( optlc_net_1476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1531 ( .LO ( optlc_net_1477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1532 ( .LO ( optlc_net_1478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1533 ( .LO ( optlc_net_1479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1534 ( .LO ( optlc_net_1480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1536 ( .LO ( optlc_net_1481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1538 ( .LO ( optlc_net_1482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1539 ( .LO ( optlc_net_1483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1540 ( .LO ( optlc_net_1484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1542 ( .LO ( optlc_net_1485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1543 ( .LO ( optlc_net_1486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1544 ( .LO ( optlc_net_1487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1545 ( .LO ( optlc_net_1488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1547 ( .LO ( optlc_net_1489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1549 ( .LO ( optlc_net_1490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1551 ( .LO ( optlc_net_1491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1552 ( .LO ( optlc_net_1492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1553 ( .LO ( optlc_net_1493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1555 ( .LO ( optlc_net_1494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1557 ( .LO ( optlc_net_1495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1559 ( .LO ( optlc_net_1496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1560 ( .LO ( optlc_net_1497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1561 ( .LO ( optlc_net_1498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1562 ( .LO ( optlc_net_1499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1563 ( .LO ( optlc_net_1500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1564 ( .LO ( optlc_net_1501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1566 ( .LO ( optlc_net_1502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1567 ( .LO ( optlc_net_1503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1568 ( .LO ( optlc_net_1504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1570 ( .LO ( optlc_net_1505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1571 ( .LO ( optlc_net_1506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1572 ( .LO ( optlc_net_1507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1573 ( .LO ( optlc_net_1508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1575 ( .LO ( optlc_net_1509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1577 ( .LO ( optlc_net_1510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1578 ( .LO ( optlc_net_1511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1580 ( .LO ( optlc_net_1512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1582 ( .LO ( optlc_net_1513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1583 ( .LO ( optlc_net_1514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1585 ( .LO ( optlc_net_1515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1586 ( .LO ( optlc_net_1516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1588 ( .LO ( optlc_net_1517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1590 ( .LO ( optlc_net_1518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1591 ( .LO ( optlc_net_1519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1592 ( .LO ( optlc_net_1520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1594 ( .LO ( optlc_net_1521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1595 ( .LO ( optlc_net_1522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1597 ( .LO ( optlc_net_1523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1598 ( .LO ( optlc_net_1524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1599 ( .LO ( optlc_net_1525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1600 ( .LO ( optlc_net_1526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1602 ( .LO ( optlc_net_1527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1603 ( .LO ( optlc_net_1528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1605 ( .LO ( optlc_net_1529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1606 ( .LO ( optlc_net_1530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1608 ( .LO ( optlc_net_1531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1610 ( .LO ( optlc_net_1532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1611 ( .LO ( optlc_net_1533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1612 ( .LO ( optlc_net_1534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1613 ( .LO ( optlc_net_1535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1614 ( .LO ( optlc_net_1536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1615 ( .LO ( optlc_net_1537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1617 ( .LO ( optlc_net_1538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1619 ( .LO ( optlc_net_1539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1621 ( .LO ( optlc_net_1540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1623 ( .LO ( optlc_net_1541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1625 ( .LO ( optlc_net_1542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1626 ( .LO ( optlc_net_1543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1627 ( .LO ( optlc_net_1544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1628 ( .LO ( optlc_net_1545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1629 ( .LO ( optlc_net_1546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1630 ( .LO ( optlc_net_1547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1631 ( .LO ( optlc_net_1548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1633 ( .LO ( optlc_net_1549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1634 ( .LO ( optlc_net_1550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1636 ( .LO ( optlc_net_1551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1637 ( .LO ( optlc_net_1552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1639 ( .LO ( optlc_net_1553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1641 ( .LO ( optlc_net_1554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1642 ( .LO ( optlc_net_1555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1643 ( .LO ( optlc_net_1556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1645 ( .LO ( optlc_net_1557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1646 ( .LO ( optlc_net_1558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1647 ( .LO ( optlc_net_1559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1648 ( .LO ( optlc_net_1560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1649 ( .LO ( optlc_net_1561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1650 ( .LO ( optlc_net_1562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1651 ( .LO ( optlc_net_1563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1652 ( .LO ( optlc_net_1564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1654 ( .LO ( optlc_net_1565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1655 ( .LO ( optlc_net_1566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1656 ( .LO ( optlc_net_1567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1657 ( .LO ( optlc_net_1568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1659 ( .LO ( optlc_net_1569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1661 ( .LO ( optlc_net_1570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1662 ( .LO ( optlc_net_1571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1663 ( .LO ( optlc_net_1572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1665 ( .LO ( optlc_net_1573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1667 ( .LO ( optlc_net_1574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1669 ( .LO ( optlc_net_1575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1671 ( .LO ( optlc_net_1576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1672 ( .LO ( optlc_net_1577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1674 ( .LO ( optlc_net_1578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1675 ( .LO ( optlc_net_1579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1676 ( .LO ( optlc_net_1580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1677 ( .LO ( optlc_net_1581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1679 ( .LO ( optlc_net_1582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1681 ( .LO ( optlc_net_1583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1683 ( .LO ( optlc_net_1584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1685 ( .LO ( optlc_net_1585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1687 ( .LO ( optlc_net_1586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1689 ( .LO ( optlc_net_1587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1691 ( .LO ( optlc_net_1588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1692 ( .LO ( optlc_net_1589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1693 ( .LO ( optlc_net_1590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1695 ( .LO ( optlc_net_1591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1696 ( .LO ( optlc_net_1592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1698 ( .LO ( optlc_net_1593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1700 ( .LO ( optlc_net_1594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1701 ( .LO ( optlc_net_1595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1702 ( .LO ( optlc_net_1596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1704 ( .LO ( optlc_net_1597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1706 ( .LO ( optlc_net_1598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1707 ( .LO ( optlc_net_1599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1708 ( .LO ( optlc_net_1600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1710 ( .LO ( optlc_net_1601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1712 ( .LO ( optlc_net_1602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1713 ( .LO ( optlc_net_1603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1714 ( .LO ( optlc_net_1604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1715 ( .LO ( optlc_net_1605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1716 ( .LO ( optlc_net_1606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1717 ( .LO ( optlc_net_1607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1718 ( .LO ( optlc_net_1608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1719 ( .LO ( optlc_net_1609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1721 ( .LO ( optlc_net_1610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1722 ( .LO ( optlc_net_1611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1723 ( .LO ( optlc_net_1612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1725 ( .LO ( optlc_net_1613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1726 ( .LO ( optlc_net_1614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1728 ( .LO ( optlc_net_1615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1730 ( .LO ( optlc_net_1616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1731 ( .LO ( optlc_net_1617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1732 ( .LO ( optlc_net_1618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1733 ( .LO ( optlc_net_1619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1734 ( .LO ( optlc_net_1620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1735 ( .LO ( optlc_net_1621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1737 ( .LO ( optlc_net_1622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1739 ( .LO ( optlc_net_1623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1741 ( .LO ( optlc_net_1624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1743 ( .LO ( optlc_net_1625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1745 ( .LO ( optlc_net_1626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1746 ( .LO ( optlc_net_1627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1748 ( .LO ( optlc_net_1628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1750 ( .LO ( optlc_net_1629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1751 ( .LO ( optlc_net_1630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1752 ( .LO ( optlc_net_1631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1753 ( .LO ( optlc_net_1632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1755 ( .LO ( optlc_net_1633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1757 ( .LO ( optlc_net_1634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1759 ( .LO ( optlc_net_1635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1760 ( .LO ( optlc_net_1636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1761 ( .LO ( optlc_net_1637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1762 ( .LO ( optlc_net_1638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1763 ( .LO ( optlc_net_1639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1764 ( .LO ( optlc_net_1640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1765 ( .LO ( optlc_net_1641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1766 ( .LO ( optlc_net_1642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1768 ( .LO ( optlc_net_1643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1769 ( .LO ( optlc_net_1644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1771 ( .LO ( optlc_net_1645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1772 ( .LO ( optlc_net_1646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1773 ( .LO ( optlc_net_1647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1775 ( .LO ( optlc_net_1648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1776 ( .LO ( optlc_net_1649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1777 ( .LO ( optlc_net_1650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1778 ( .LO ( optlc_net_1651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1780 ( .LO ( optlc_net_1652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1782 ( .LO ( optlc_net_1653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1783 ( .LO ( optlc_net_1654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1784 ( .LO ( optlc_net_1655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1785 ( .LO ( optlc_net_1656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1787 ( .LO ( optlc_net_1657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1788 ( .LO ( optlc_net_1658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1790 ( .LO ( optlc_net_1659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1791 ( .LO ( optlc_net_1660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1793 ( .LO ( optlc_net_1661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1794 ( .LO ( optlc_net_1662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1796 ( .LO ( optlc_net_1663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1797 ( .LO ( optlc_net_1664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1799 ( .LO ( optlc_net_1665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1801 ( .LO ( optlc_net_1666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1803 ( .LO ( optlc_net_1667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1805 ( .LO ( optlc_net_1668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1806 ( .LO ( optlc_net_1669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1807 ( .LO ( optlc_net_1670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1808 ( .LO ( optlc_net_1671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1810 ( .LO ( optlc_net_1672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1812 ( .LO ( optlc_net_1673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1813 ( .LO ( optlc_net_1674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1814 ( .LO ( optlc_net_1675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1816 ( .LO ( optlc_net_1676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1817 ( .LO ( optlc_net_1677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1818 ( .LO ( optlc_net_1678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1819 ( .LO ( optlc_net_1679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1820 ( .LO ( optlc_net_1680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1822 ( .LO ( optlc_net_1681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1823 ( .LO ( optlc_net_1682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1824 ( .LO ( optlc_net_1683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1825 ( .LO ( optlc_net_1684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1826 ( .LO ( optlc_net_1685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1828 ( .LO ( optlc_net_1686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1829 ( .LO ( optlc_net_1687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1831 ( .LO ( optlc_net_1688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1832 ( .LO ( optlc_net_1689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1833 ( .LO ( optlc_net_1690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1834 ( .LO ( optlc_net_1691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1836 ( .LO ( optlc_net_1692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1838 ( .LO ( optlc_net_1693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1839 ( .LO ( optlc_net_1694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1840 ( .LO ( optlc_net_1695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1842 ( .LO ( optlc_net_1696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1843 ( .LO ( optlc_net_1697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1844 ( .LO ( optlc_net_1698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1846 ( .LO ( optlc_net_1699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1847 ( .LO ( optlc_net_1700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1848 ( .LO ( optlc_net_1701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1850 ( .LO ( optlc_net_1702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1851 ( .LO ( optlc_net_1703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1853 ( .LO ( optlc_net_1704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1854 ( .LO ( optlc_net_1705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1856 ( .LO ( optlc_net_1706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1858 ( .LO ( optlc_net_1707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1860 ( .LO ( optlc_net_1708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1861 ( .LO ( optlc_net_1709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1862 ( .LO ( optlc_net_1710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1863 ( .LO ( optlc_net_1711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1864 ( .LO ( optlc_net_1712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1866 ( .LO ( optlc_net_1713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1867 ( .LO ( optlc_net_1714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1869 ( .LO ( optlc_net_1715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1871 ( .LO ( optlc_net_1716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1872 ( .LO ( optlc_net_1717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1873 ( .LO ( optlc_net_1718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1875 ( .LO ( optlc_net_1719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1877 ( .LO ( optlc_net_1720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1878 ( .LO ( optlc_net_1721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1879 ( .LO ( optlc_net_1722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1881 ( .LO ( optlc_net_1723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1882 ( .LO ( optlc_net_1724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1883 ( .LO ( optlc_net_1725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1885 ( .LO ( optlc_net_1726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1886 ( .LO ( optlc_net_1727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1887 ( .LO ( optlc_net_1728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1888 ( .LO ( optlc_net_1729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1889 ( .LO ( optlc_net_1730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1890 ( .LO ( optlc_net_1731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1892 ( .LO ( optlc_net_1732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1893 ( .LO ( optlc_net_1733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1894 ( .LO ( optlc_net_1734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1895 ( .LO ( optlc_net_1735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1896 ( .LO ( optlc_net_1736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1897 ( .LO ( optlc_net_1737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1898 ( .LO ( optlc_net_1738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1900 ( .LO ( optlc_net_1739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1901 ( .LO ( optlc_net_1740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1903 ( .LO ( optlc_net_1741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1905 ( .LO ( optlc_net_1742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1906 ( .LO ( optlc_net_1743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1907 ( .LO ( optlc_net_1744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1908 ( .LO ( optlc_net_1745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1909 ( .LO ( optlc_net_1746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1910 ( .LO ( optlc_net_1747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1912 ( .LO ( optlc_net_1748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1913 ( .LO ( optlc_net_1749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1914 ( .LO ( optlc_net_1750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1915 ( .LO ( optlc_net_1751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1916 ( .LO ( optlc_net_1752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1917 ( .LO ( optlc_net_1753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1919 ( .LO ( optlc_net_1754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1920 ( .LO ( optlc_net_1755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1921 ( .LO ( optlc_net_1756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1922 ( .LO ( optlc_net_1757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1923 ( .LO ( optlc_net_1758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1924 ( .LO ( optlc_net_1759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1926 ( .LO ( optlc_net_1760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1928 ( .LO ( optlc_net_1761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1929 ( .LO ( optlc_net_1762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1931 ( .LO ( optlc_net_1763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1933 ( .LO ( optlc_net_1764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1934 ( .LO ( optlc_net_1765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1935 ( .LO ( optlc_net_1766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1936 ( .LO ( optlc_net_1767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1937 ( .LO ( optlc_net_1768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1938 ( .LO ( optlc_net_1769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1939 ( .LO ( optlc_net_1770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1941 ( .LO ( optlc_net_1771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1942 ( .LO ( optlc_net_1772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1943 ( .LO ( optlc_net_1773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1944 ( .LO ( optlc_net_1774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1945 ( .LO ( optlc_net_1775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1946 ( .LO ( optlc_net_1776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1947 ( .LO ( optlc_net_1777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1948 ( .LO ( optlc_net_1778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1950 ( .LO ( optlc_net_1779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1951 ( .LO ( optlc_net_1780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1952 ( .LO ( optlc_net_1781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1954 ( .LO ( optlc_net_1782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1955 ( .LO ( optlc_net_1783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1957 ( .LO ( optlc_net_1784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1959 ( .LO ( optlc_net_1785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1961 ( .LO ( optlc_net_1786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1963 ( .LO ( optlc_net_1787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1964 ( .LO ( optlc_net_1788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1965 ( .LO ( optlc_net_1789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1967 ( .LO ( optlc_net_1790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1968 ( .LO ( optlc_net_1791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1969 ( .LO ( optlc_net_1792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1970 ( .LO ( optlc_net_1793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1971 ( .LO ( optlc_net_1794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1972 ( .LO ( optlc_net_1795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1973 ( .LO ( optlc_net_1796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1974 ( .LO ( optlc_net_1797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1975 ( .LO ( optlc_net_1798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1976 ( .LO ( optlc_net_1799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1977 ( .LO ( optlc_net_1800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1978 ( .LO ( optlc_net_1801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1979 ( .LO ( optlc_net_1802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1980 ( .LO ( optlc_net_1803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1981 ( .LO ( optlc_net_1804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1983 ( .LO ( optlc_net_1805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1984 ( .LO ( optlc_net_1806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1986 ( .LO ( optlc_net_1807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1988 ( .LO ( optlc_net_1808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1990 ( .LO ( optlc_net_1809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1992 ( .LO ( optlc_net_1810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1993 ( .LO ( optlc_net_1811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1995 ( .LO ( optlc_net_1812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1996 ( .LO ( optlc_net_1813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1998 ( .LO ( optlc_net_1814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1999 ( .LO ( optlc_net_1815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2001 ( .LO ( optlc_net_1816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2003 ( .LO ( optlc_net_1817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2005 ( .LO ( optlc_net_1818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2006 ( .LO ( optlc_net_1819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2008 ( .LO ( optlc_net_1820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2010 ( .LO ( optlc_net_1821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2011 ( .LO ( optlc_net_1822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2013 ( .LO ( optlc_net_1823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2014 ( .LO ( optlc_net_1824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2015 ( .LO ( optlc_net_1825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2016 ( .LO ( optlc_net_1826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2017 ( .LO ( optlc_net_1827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2018 ( .LO ( optlc_net_1828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2019 ( .LO ( optlc_net_1829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2020 ( .LO ( optlc_net_1830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2021 ( .LO ( optlc_net_1831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2022 ( .LO ( optlc_net_1832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2023 ( .LO ( optlc_net_1833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2024 ( .LO ( optlc_net_1834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2026 ( .LO ( optlc_net_1835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2027 ( .LO ( optlc_net_1836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2028 ( .LO ( optlc_net_1837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2029 ( .LO ( optlc_net_1838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2030 ( .LO ( optlc_net_1839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2031 ( .LO ( optlc_net_1840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2032 ( .LO ( optlc_net_1841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2034 ( .LO ( optlc_net_1842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2035 ( .LO ( optlc_net_1843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2036 ( .LO ( optlc_net_1844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2037 ( .LO ( optlc_net_1845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2038 ( .LO ( optlc_net_1846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2039 ( .LO ( optlc_net_1847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2041 ( .LO ( optlc_net_1848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2042 ( .LO ( optlc_net_1849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2043 ( .LO ( optlc_net_1850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2044 ( .LO ( optlc_net_1851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2046 ( .LO ( optlc_net_1852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2047 ( .LO ( optlc_net_1853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2049 ( .LO ( optlc_net_1854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2050 ( .LO ( optlc_net_1855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2052 ( .LO ( optlc_net_1856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2053 ( .LO ( optlc_net_1857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2054 ( .LO ( optlc_net_1858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2055 ( .LO ( optlc_net_1859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2056 ( .LO ( optlc_net_1860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2058 ( .LO ( optlc_net_1861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2060 ( .LO ( optlc_net_1862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2062 ( .LO ( optlc_net_1863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2063 ( .LO ( optlc_net_1864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2064 ( .LO ( optlc_net_1865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2065 ( .LO ( optlc_net_1866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2066 ( .LO ( optlc_net_1867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2068 ( .LO ( optlc_net_1868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2069 ( .LO ( optlc_net_1869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2071 ( .LO ( optlc_net_1870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2072 ( .LO ( optlc_net_1871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2073 ( .LO ( optlc_net_1872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2075 ( .LO ( optlc_net_1873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2076 ( .LO ( optlc_net_1874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2077 ( .LO ( optlc_net_1875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2078 ( .LO ( optlc_net_1876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2079 ( .LO ( optlc_net_1877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2081 ( .LO ( optlc_net_1878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2082 ( .LO ( optlc_net_1879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2083 ( .LO ( optlc_net_1880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2085 ( .LO ( optlc_net_1881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2086 ( .LO ( optlc_net_1882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2088 ( .LO ( optlc_net_1883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2089 ( .LO ( optlc_net_1884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2091 ( .LO ( optlc_net_1885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2093 ( .LO ( optlc_net_1886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2094 ( .LO ( optlc_net_1887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2095 ( .LO ( optlc_net_1888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2097 ( .LO ( optlc_net_1889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2099 ( .LO ( optlc_net_1890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2101 ( .LO ( optlc_net_1891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2102 ( .LO ( optlc_net_1892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2103 ( .LO ( optlc_net_1893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2104 ( .LO ( optlc_net_1894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2105 ( .LO ( optlc_net_1895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2106 ( .LO ( optlc_net_1896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2108 ( .LO ( optlc_net_1897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2110 ( .LO ( optlc_net_1898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2112 ( .LO ( optlc_net_1899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2113 ( .LO ( optlc_net_1900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2115 ( .LO ( optlc_net_1901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2116 ( .LO ( optlc_net_1902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2117 ( .LO ( optlc_net_1903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2118 ( .LO ( optlc_net_1904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2119 ( .LO ( optlc_net_1905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2120 ( .LO ( optlc_net_1906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2121 ( .LO ( optlc_net_1907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2122 ( .LO ( optlc_net_1908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2123 ( .LO ( optlc_net_1909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2124 ( .LO ( optlc_net_1910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2125 ( .LO ( optlc_net_1911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2126 ( .LO ( optlc_net_1912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2127 ( .LO ( optlc_net_1913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2128 ( .LO ( optlc_net_1914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2129 ( .LO ( optlc_net_1915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2130 ( .LO ( optlc_net_1916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2132 ( .LO ( optlc_net_1918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2134 ( .LO ( optlc_net_1920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2135 ( .LO ( optlc_net_1921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2138 ( .LO ( optlc_net_1924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2140 ( .LO ( optlc_net_1926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2141 ( .LO ( optlc_net_1927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2142 ( .LO ( optlc_net_1928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2143 ( .LO ( optlc_net_1929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2144 ( .LO ( optlc_net_1930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2146 ( .LO ( optlc_net_1932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2147 ( .LO ( optlc_net_1933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2149 ( .LO ( optlc_net_1935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2153 ( .LO ( optlc_net_1939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2154 ( .LO ( optlc_net_1940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2155 ( .LO ( optlc_net_1941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2156 ( .LO ( optlc_net_1942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2157 ( .LO ( optlc_net_1943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2158 ( .LO ( optlc_net_1944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2159 ( .LO ( optlc_net_1945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2160 ( .LO ( optlc_net_1946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2164 ( .LO ( optlc_net_1950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2166 ( .LO ( optlc_net_1952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2168 ( .LO ( optlc_net_1954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2170 ( .LO ( optlc_net_1956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2172 ( .LO ( optlc_net_1958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2174 ( .LO ( optlc_net_1960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2176 ( .LO ( optlc_net_1962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2178 ( .LO ( optlc_net_1964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2182 ( .LO ( optlc_net_1968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2183 ( .LO ( optlc_net_1969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2185 ( .LO ( optlc_net_1971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2189 ( .LO ( optlc_net_1975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2191 ( .LO ( optlc_net_1977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2193 ( .LO ( optlc_net_1979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2195 ( .LO ( optlc_net_1981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2197 ( .LO ( optlc_net_1983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2199 ( .LO ( optlc_net_1985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2201 ( .LO ( optlc_net_1987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2208 ( .LO ( optlc_net_1993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2213 ( .LO ( optlc_net_1998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2215 ( .LO ( optlc_net_2000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_2001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2217 ( .LO ( optlc_net_2002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_2003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2219 ( .LO ( optlc_net_2004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_2005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_2006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2223 ( .LO ( optlc_net_2007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_2008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_2009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_2010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2228 ( .LO ( optlc_net_2011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2229 ( .LO ( optlc_net_2012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2230 ( .LO ( optlc_net_2013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2232 ( .LO ( optlc_net_2014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_2015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2234 ( .LO ( optlc_net_2016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_2017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_2018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_2019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_2020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_2021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_2022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2241 ( .LO ( optlc_net_2023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_2024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_2025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2244 ( .LO ( optlc_net_2026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2246 ( .LO ( optlc_net_2027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_2028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_2029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2249 ( .LO ( optlc_net_2030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2250 ( .LO ( optlc_net_2031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2251 ( .LO ( optlc_net_2032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2252 ( .LO ( optlc_net_2033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2253 ( .LO ( optlc_net_2034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2254 ( .LO ( optlc_net_2035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2255 ( .LO ( optlc_net_2036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2256 ( .LO ( optlc_net_2037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2257 ( .LO ( optlc_net_2038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2258 ( .LO ( optlc_net_2039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2260 ( .LO ( optlc_net_2040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2261 ( .LO ( optlc_net_2041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2262 ( .LO ( optlc_net_2042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2263 ( .LO ( optlc_net_2043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2264 ( .LO ( optlc_net_2044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2265 ( .LO ( optlc_net_2045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2266 ( .LO ( optlc_net_2046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2267 ( .LO ( optlc_net_2047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2268 ( .LO ( optlc_net_2048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2269 ( .LO ( optlc_net_2049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2271 ( .LO ( optlc_net_2050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2272 ( .LO ( optlc_net_2051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2273 ( .LO ( optlc_net_2052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2274 ( .LO ( optlc_net_2053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2275 ( .LO ( optlc_net_2054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2277 ( .LO ( optlc_net_2055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2278 ( .LO ( optlc_net_2056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2279 ( .LO ( optlc_net_2057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2280 ( .LO ( optlc_net_2058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2281 ( .LO ( optlc_net_2059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2283 ( .LO ( optlc_net_2060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2284 ( .LO ( optlc_net_2061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2285 ( .LO ( optlc_net_2062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2286 ( .LO ( optlc_net_2063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2287 ( .LO ( optlc_net_2064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2289 ( .LO ( optlc_net_2065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2290 ( .LO ( optlc_net_2066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2291 ( .LO ( optlc_net_2067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2293 ( .LO ( optlc_net_2068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2294 ( .LO ( optlc_net_2069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2295 ( .LO ( optlc_net_2070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2296 ( .LO ( optlc_net_2071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2297 ( .LO ( optlc_net_2072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2299 ( .LO ( optlc_net_2073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2300 ( .LO ( optlc_net_2074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2301 ( .LO ( optlc_net_2075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2302 ( .LO ( optlc_net_2076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2303 ( .LO ( optlc_net_2077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2305 ( .LO ( optlc_net_2078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2306 ( .LO ( optlc_net_2079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2308 ( .LO ( optlc_net_2080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2309 ( .LO ( optlc_net_2081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2310 ( .LO ( optlc_net_2082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2311 ( .LO ( optlc_net_2083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2312 ( .LO ( optlc_net_2084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2313 ( .LO ( optlc_net_2085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2314 ( .LO ( optlc_net_2086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2315 ( .LO ( optlc_net_2087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2316 ( .LO ( optlc_net_2088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2317 ( .LO ( optlc_net_2089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2318 ( .LO ( optlc_net_2090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2319 ( .LO ( optlc_net_2091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2320 ( .LO ( optlc_net_2092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2321 ( .LO ( optlc_net_2093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2322 ( .LO ( optlc_net_2094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2323 ( .LO ( optlc_net_2095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2324 ( .LO ( optlc_net_2096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2326 ( .LO ( optlc_net_2097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2328 ( .LO ( optlc_net_2098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2329 ( .LO ( optlc_net_2099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2330 ( .LO ( optlc_net_2100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2332 ( .LO ( optlc_net_2101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2334 ( .LO ( optlc_net_2102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2335 ( .LO ( optlc_net_2103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2336 ( .LO ( optlc_net_2104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2337 ( .LO ( optlc_net_2105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2338 ( .LO ( optlc_net_2106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2340 ( .LO ( optlc_net_2107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2341 ( .LO ( optlc_net_2108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2343 ( .LO ( optlc_net_2109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2345 ( .LO ( optlc_net_2110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2346 ( .LO ( optlc_net_2111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2347 ( .LO ( optlc_net_2112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2348 ( .LO ( optlc_net_2113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2349 ( .LO ( optlc_net_2114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2351 ( .LO ( optlc_net_2115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2352 ( .LO ( optlc_net_2116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2353 ( .LO ( optlc_net_2117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2355 ( .LO ( optlc_net_2118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2357 ( .LO ( optlc_net_2119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2359 ( .LO ( optlc_net_2120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2360 ( .LO ( optlc_net_2121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2361 ( .LO ( optlc_net_2122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2362 ( .LO ( optlc_net_2123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2364 ( .LO ( optlc_net_2124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2365 ( .LO ( optlc_net_2125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2367 ( .LO ( optlc_net_2126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2368 ( .LO ( optlc_net_2127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2370 ( .LO ( optlc_net_2128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2371 ( .LO ( optlc_net_2129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2373 ( .LO ( optlc_net_2130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2374 ( .LO ( optlc_net_2131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2375 ( .LO ( optlc_net_2132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2376 ( .LO ( optlc_net_2133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2377 ( .LO ( optlc_net_2134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2378 ( .LO ( optlc_net_2135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2379 ( .LO ( optlc_net_2136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2380 ( .LO ( optlc_net_2137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2381 ( .LO ( optlc_net_2138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2382 ( .LO ( optlc_net_2139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2384 ( .LO ( optlc_net_2140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2386 ( .LO ( optlc_net_2141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2387 ( .LO ( optlc_net_2142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2388 ( .LO ( optlc_net_2143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2389 ( .LO ( optlc_net_2144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2390 ( .LO ( optlc_net_2145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2391 ( .LO ( optlc_net_2146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2393 ( .LO ( optlc_net_2147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2394 ( .LO ( optlc_net_2148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2395 ( .LO ( optlc_net_2149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2397 ( .LO ( optlc_net_2150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2398 ( .LO ( optlc_net_2151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2400 ( .LO ( optlc_net_2152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2401 ( .LO ( optlc_net_2153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2402 ( .LO ( optlc_net_2154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2403 ( .LO ( optlc_net_2155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2404 ( .LO ( optlc_net_2156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2405 ( .LO ( optlc_net_2157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2406 ( .LO ( optlc_net_2158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2407 ( .LO ( optlc_net_2159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2408 ( .LO ( optlc_net_2160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2409 ( .LO ( optlc_net_2161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2410 ( .LO ( optlc_net_2162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2411 ( .LO ( optlc_net_2163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2412 ( .LO ( optlc_net_2164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2413 ( .LO ( optlc_net_2165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2415 ( .LO ( optlc_net_2166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2416 ( .LO ( optlc_net_2167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2417 ( .LO ( optlc_net_2168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2418 ( .LO ( optlc_net_2169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2419 ( .LO ( optlc_net_2170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2420 ( .LO ( optlc_net_2171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2421 ( .LO ( optlc_net_2172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2422 ( .LO ( optlc_net_2173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2423 ( .LO ( optlc_net_2174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2424 ( .LO ( optlc_net_2175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2425 ( .LO ( optlc_net_2176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2426 ( .LO ( optlc_net_2177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2428 ( .LO ( optlc_net_2178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2430 ( .LO ( optlc_net_2179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2431 ( .LO ( optlc_net_2180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2432 ( .LO ( optlc_net_2181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2433 ( .LO ( optlc_net_2182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2434 ( .LO ( optlc_net_2183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2435 ( .LO ( optlc_net_2184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2436 ( .LO ( optlc_net_2185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2438 ( .LO ( optlc_net_2186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2439 ( .LO ( optlc_net_2187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2440 ( .LO ( optlc_net_2188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2441 ( .LO ( optlc_net_2189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2442 ( .LO ( optlc_net_2190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2443 ( .LO ( optlc_net_2191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2444 ( .LO ( optlc_net_2192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2445 ( .LO ( optlc_net_2193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2446 ( .LO ( optlc_net_2194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2447 ( .LO ( optlc_net_2195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2448 ( .LO ( optlc_net_2196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2449 ( .LO ( optlc_net_2197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2450 ( .LO ( optlc_net_2198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2451 ( .LO ( optlc_net_2199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2452 ( .LO ( optlc_net_2200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2453 ( .LO ( optlc_net_2201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2454 ( .LO ( optlc_net_2202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2455 ( .LO ( optlc_net_2203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2456 ( .LO ( optlc_net_2204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2457 ( .LO ( optlc_net_2205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2458 ( .LO ( optlc_net_2206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2459 ( .LO ( optlc_net_2207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2460 ( .LO ( optlc_net_2208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2461 ( .LO ( optlc_net_2209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2462 ( .LO ( optlc_net_2210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2463 ( .LO ( optlc_net_2211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2464 ( .LO ( optlc_net_2212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2465 ( .LO ( optlc_net_2213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2466 ( .LO ( optlc_net_2214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2467 ( .LO ( optlc_net_2215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2468 ( .LO ( optlc_net_2216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2469 ( .LO ( optlc_net_2217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2470 ( .LO ( optlc_net_2218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2471 ( .LO ( optlc_net_2219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2472 ( .LO ( optlc_net_2220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2473 ( .LO ( optlc_net_2221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2474 ( .LO ( optlc_net_2222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2475 ( .LO ( optlc_net_2223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2476 ( .LO ( optlc_net_2224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2477 ( .LO ( optlc_net_2225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2478 ( .LO ( optlc_net_2226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2479 ( .LO ( optlc_net_2227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2480 ( .LO ( optlc_net_2228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2481 ( .LO ( optlc_net_2229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2482 ( .LO ( optlc_net_2230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2483 ( .LO ( optlc_net_2231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2484 ( .LO ( optlc_net_2232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2485 ( .LO ( optlc_net_2233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2486 ( .LO ( optlc_net_2234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2487 ( .LO ( optlc_net_2235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2488 ( .LO ( optlc_net_2236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2489 ( .LO ( optlc_net_2237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2490 ( .LO ( optlc_net_2238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2491 ( .LO ( optlc_net_2239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2492 ( .LO ( optlc_net_2240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2493 ( .LO ( optlc_net_2241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2494 ( .LO ( optlc_net_2242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2495 ( .LO ( optlc_net_2243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2496 ( .LO ( optlc_net_2244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2497 ( .LO ( optlc_net_2245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2498 ( .LO ( optlc_net_2246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2499 ( .LO ( optlc_net_2247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2500 ( .LO ( optlc_net_2248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2501 ( .LO ( optlc_net_2249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2502 ( .LO ( optlc_net_2250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2503 ( .LO ( optlc_net_2251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2504 ( .LO ( optlc_net_2252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2505 ( .LO ( optlc_net_2253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2506 ( .LO ( optlc_net_2254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2507 ( .LO ( optlc_net_2255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2508 ( .LO ( optlc_net_2256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2509 ( .LO ( optlc_net_2257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2510 ( .LO ( optlc_net_2258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2511 ( .LO ( optlc_net_2259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2512 ( .LO ( optlc_net_2260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2513 ( .LO ( optlc_net_2261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2514 ( .LO ( optlc_net_2262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2515 ( .LO ( optlc_net_2263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2516 ( .LO ( optlc_net_2264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2517 ( .LO ( optlc_net_2265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2518 ( .LO ( optlc_net_2266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2519 ( .LO ( optlc_net_2267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2520 ( .LO ( optlc_net_2268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2521 ( .LO ( optlc_net_2269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2522 ( .LO ( optlc_net_2270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2523 ( .LO ( optlc_net_2271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2524 ( .LO ( optlc_net_2272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2525 ( .LO ( optlc_net_2273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2526 ( .LO ( optlc_net_2274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2527 ( .LO ( optlc_net_2275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2528 ( .LO ( optlc_net_2276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2529 ( .LO ( optlc_net_2277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2530 ( .LO ( optlc_net_2278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2531 ( .LO ( optlc_net_2279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2532 ( .LO ( optlc_net_2280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2533 ( .LO ( optlc_net_2281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2534 ( .LO ( optlc_net_2282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2536 ( .LO ( optlc_net_2283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2537 ( .LO ( optlc_net_2284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2538 ( .LO ( optlc_net_2285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2539 ( .LO ( optlc_net_2286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2541 ( .LO ( optlc_net_2287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2542 ( .LO ( optlc_net_2288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2543 ( .LO ( optlc_net_2289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2544 ( .LO ( optlc_net_2290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2545 ( .LO ( optlc_net_2291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2546 ( .LO ( optlc_net_2292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2547 ( .LO ( optlc_net_2293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2548 ( .LO ( optlc_net_2294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2549 ( .LO ( optlc_net_2295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2550 ( .LO ( optlc_net_2296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2551 ( .LO ( optlc_net_2297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2552 ( .LO ( optlc_net_2298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2554 ( .LO ( optlc_net_2299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2555 ( .LO ( optlc_net_2300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2556 ( .LO ( optlc_net_2301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2557 ( .LO ( optlc_net_2302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2558 ( .LO ( optlc_net_2303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2559 ( .LO ( optlc_net_2304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2560 ( .LO ( optlc_net_2305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2561 ( .LO ( optlc_net_2306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2562 ( .LO ( optlc_net_2307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2563 ( .LO ( optlc_net_2308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2564 ( .LO ( optlc_net_2309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2565 ( .LO ( optlc_net_2310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2566 ( .LO ( optlc_net_2311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2567 ( .LO ( optlc_net_2312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2569 ( .LO ( optlc_net_2313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2570 ( .LO ( optlc_net_2314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2571 ( .LO ( optlc_net_2315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2572 ( .LO ( optlc_net_2316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2573 ( .LO ( optlc_net_2317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2574 ( .LO ( optlc_net_2318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2575 ( .LO ( optlc_net_2319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2576 ( .LO ( optlc_net_2320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2577 ( .LO ( optlc_net_2321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2578 ( .LO ( optlc_net_2322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2580 ( .LO ( optlc_net_2323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2581 ( .LO ( optlc_net_2324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2582 ( .LO ( optlc_net_2325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2583 ( .LO ( optlc_net_2326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2584 ( .LO ( optlc_net_2327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2586 ( .LO ( optlc_net_2328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2587 ( .LO ( optlc_net_2329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2588 ( .LO ( optlc_net_2330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2589 ( .LO ( optlc_net_2331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2590 ( .LO ( optlc_net_2332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2591 ( .LO ( optlc_net_2333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2592 ( .LO ( optlc_net_2334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2593 ( .LO ( optlc_net_2335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2595 ( .LO ( optlc_net_2336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2596 ( .LO ( optlc_net_2337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2597 ( .LO ( optlc_net_2338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2598 ( .LO ( optlc_net_2339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2600 ( .LO ( optlc_net_2340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2601 ( .LO ( optlc_net_2341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2602 ( .LO ( optlc_net_2342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2603 ( .LO ( optlc_net_2343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2604 ( .LO ( optlc_net_2344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2605 ( .LO ( optlc_net_2345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2607 ( .LO ( optlc_net_2346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2608 ( .LO ( optlc_net_2347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2610 ( .LO ( optlc_net_2348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2611 ( .LO ( optlc_net_2349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2612 ( .LO ( optlc_net_2350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2613 ( .LO ( optlc_net_2351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2614 ( .LO ( optlc_net_2352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2615 ( .LO ( optlc_net_2353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2616 ( .LO ( optlc_net_2354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2617 ( .LO ( optlc_net_2355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2619 ( .LO ( optlc_net_2356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2620 ( .LO ( optlc_net_2357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2621 ( .LO ( optlc_net_2358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2622 ( .LO ( optlc_net_2359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2623 ( .LO ( optlc_net_2360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2624 ( .LO ( optlc_net_2361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2625 ( .LO ( optlc_net_2362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2626 ( .LO ( optlc_net_2363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2627 ( .LO ( optlc_net_2364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2629 ( .LO ( optlc_net_2365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2630 ( .LO ( optlc_net_2366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2631 ( .LO ( optlc_net_2367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2632 ( .LO ( optlc_net_2368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2633 ( .LO ( optlc_net_2369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2634 ( .LO ( optlc_net_2370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2636 ( .LO ( optlc_net_2371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2637 ( .LO ( optlc_net_2372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2639 ( .LO ( optlc_net_2373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2640 ( .LO ( optlc_net_2374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2642 ( .LO ( optlc_net_2375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2644 ( .LO ( optlc_net_2376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2645 ( .LO ( optlc_net_2377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2646 ( .LO ( optlc_net_2378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2647 ( .LO ( optlc_net_2379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2648 ( .LO ( optlc_net_2380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2649 ( .LO ( optlc_net_2381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2650 ( .LO ( optlc_net_2382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2651 ( .LO ( optlc_net_2383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2652 ( .LO ( optlc_net_2384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2653 ( .LO ( optlc_net_2385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2654 ( .LO ( optlc_net_2386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2655 ( .LO ( optlc_net_2387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2656 ( .LO ( optlc_net_2388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2657 ( .LO ( optlc_net_2389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2658 ( .LO ( optlc_net_2390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2660 ( .LO ( optlc_net_2391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2661 ( .LO ( optlc_net_2392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2663 ( .LO ( optlc_net_2393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2665 ( .LO ( optlc_net_2394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2666 ( .LO ( optlc_net_2395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2667 ( .LO ( optlc_net_2396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2668 ( .LO ( optlc_net_2397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2669 ( .LO ( optlc_net_2398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2671 ( .LO ( optlc_net_2399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2672 ( .LO ( optlc_net_2400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2673 ( .LO ( optlc_net_2401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2674 ( .LO ( optlc_net_2402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2675 ( .LO ( optlc_net_2403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2676 ( .LO ( optlc_net_2404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2678 ( .LO ( optlc_net_2405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2679 ( .LO ( optlc_net_2406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2680 ( .LO ( optlc_net_2407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2682 ( .LO ( optlc_net_2408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2683 ( .LO ( optlc_net_2409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2684 ( .LO ( optlc_net_2410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2685 ( .LO ( optlc_net_2411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2686 ( .LO ( optlc_net_2412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2687 ( .LO ( optlc_net_2413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2688 ( .LO ( optlc_net_2414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2689 ( .LO ( optlc_net_2415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2690 ( .LO ( optlc_net_2416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2691 ( .LO ( optlc_net_2417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2692 ( .LO ( optlc_net_2418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2693 ( .LO ( optlc_net_2419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2694 ( .LO ( optlc_net_2420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2695 ( .LO ( optlc_net_2421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2696 ( .LO ( optlc_net_2422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2698 ( .LO ( optlc_net_2423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2700 ( .LO ( optlc_net_2424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2701 ( .LO ( optlc_net_2425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2702 ( .LO ( optlc_net_2426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2703 ( .LO ( optlc_net_2427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2704 ( .LO ( optlc_net_2428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2705 ( .LO ( optlc_net_2429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2706 ( .LO ( optlc_net_2430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2707 ( .LO ( optlc_net_2431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2708 ( .LO ( optlc_net_2432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2709 ( .LO ( optlc_net_2433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2710 ( .LO ( optlc_net_2434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2711 ( .LO ( optlc_net_2435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2713 ( .LO ( optlc_net_2436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2714 ( .LO ( optlc_net_2437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2716 ( .LO ( optlc_net_2438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2718 ( .LO ( optlc_net_2439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2719 ( .LO ( optlc_net_2440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2720 ( .LO ( optlc_net_2441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2721 ( .LO ( optlc_net_2442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2722 ( .LO ( optlc_net_2443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2723 ( .LO ( optlc_net_2444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2724 ( .LO ( optlc_net_2445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2725 ( .LO ( optlc_net_2446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2726 ( .LO ( optlc_net_2447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2727 ( .LO ( optlc_net_2448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2728 ( .LO ( optlc_net_2449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2729 ( .LO ( optlc_net_2450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2730 ( .LO ( optlc_net_2451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2731 ( .LO ( optlc_net_2452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2732 ( .LO ( optlc_net_2453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2733 ( .LO ( optlc_net_2454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2734 ( .LO ( optlc_net_2455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2735 ( .LO ( optlc_net_2456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2736 ( .LO ( optlc_net_2457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2737 ( .LO ( optlc_net_2458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2738 ( .LO ( optlc_net_2459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2739 ( .LO ( optlc_net_2460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2740 ( .LO ( optlc_net_2461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2741 ( .LO ( optlc_net_2462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2742 ( .LO ( optlc_net_2463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2743 ( .LO ( optlc_net_2464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2744 ( .LO ( optlc_net_2465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2745 ( .LO ( optlc_net_2466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2746 ( .LO ( optlc_net_2467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2747 ( .LO ( optlc_net_2468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2748 ( .LO ( optlc_net_2469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2749 ( .LO ( optlc_net_2470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2750 ( .LO ( optlc_net_2471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2751 ( .LO ( optlc_net_2472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2752 ( .LO ( optlc_net_2473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2753 ( .LO ( optlc_net_2474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2754 ( .LO ( optlc_net_2475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2755 ( .LO ( optlc_net_2476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2756 ( .LO ( optlc_net_2477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2757 ( .LO ( optlc_net_2478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2758 ( .LO ( optlc_net_2479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2759 ( .LO ( optlc_net_2480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2760 ( .LO ( optlc_net_2481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2761 ( .LO ( optlc_net_2482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2762 ( .LO ( optlc_net_2483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2763 ( .LO ( optlc_net_2484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2764 ( .LO ( optlc_net_2485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2765 ( .LO ( optlc_net_2486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2766 ( .LO ( optlc_net_2487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2767 ( .LO ( optlc_net_2488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2768 ( .LO ( optlc_net_2489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2769 ( .LO ( optlc_net_2490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2770 ( .LO ( optlc_net_2491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2771 ( .LO ( optlc_net_2492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2772 ( .LO ( optlc_net_2493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2773 ( .LO ( optlc_net_2494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2774 ( .LO ( optlc_net_2495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2775 ( .LO ( optlc_net_2496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2776 ( .LO ( optlc_net_2497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2777 ( .LO ( optlc_net_2498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2778 ( .LO ( optlc_net_2499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2779 ( .LO ( optlc_net_2500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2780 ( .LO ( optlc_net_2501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2781 ( .LO ( optlc_net_2502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2782 ( .LO ( optlc_net_2503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2783 ( .LO ( optlc_net_2504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2784 ( .LO ( optlc_net_2505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2785 ( .LO ( optlc_net_2506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2786 ( .LO ( optlc_net_2507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2787 ( .LO ( optlc_net_2508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2788 ( .LO ( optlc_net_2509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2789 ( .LO ( optlc_net_2510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2790 ( .LO ( optlc_net_2511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2791 ( .LO ( optlc_net_2512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2792 ( .LO ( optlc_net_2513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2793 ( .LO ( optlc_net_2514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2794 ( .LO ( optlc_net_2515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2795 ( .LO ( optlc_net_2516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2796 ( .LO ( optlc_net_2517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2797 ( .LO ( optlc_net_2518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2798 ( .LO ( optlc_net_2519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2799 ( .LO ( optlc_net_2520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2800 ( .LO ( optlc_net_2521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2801 ( .LO ( optlc_net_2522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2802 ( .LO ( optlc_net_2523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2803 ( .LO ( optlc_net_2524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2804 ( .LO ( optlc_net_2525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2805 ( .LO ( optlc_net_2526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2806 ( .LO ( optlc_net_2527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2808 ( .LO ( optlc_net_2528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2809 ( .LO ( optlc_net_2529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2811 ( .LO ( optlc_net_2530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2812 ( .LO ( optlc_net_2531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2813 ( .LO ( optlc_net_2532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2814 ( .LO ( optlc_net_2533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2815 ( .LO ( optlc_net_2534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2816 ( .LO ( optlc_net_2535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2817 ( .LO ( optlc_net_2536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2818 ( .LO ( optlc_net_2537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2820 ( .LO ( optlc_net_2538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2821 ( .LO ( optlc_net_2539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2822 ( .LO ( optlc_net_2540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2823 ( .LO ( optlc_net_2541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2824 ( .LO ( optlc_net_2542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2825 ( .LO ( optlc_net_2543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2826 ( .LO ( optlc_net_2544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2827 ( .LO ( optlc_net_2545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2828 ( .LO ( optlc_net_2546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2829 ( .LO ( optlc_net_2547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2830 ( .LO ( optlc_net_2548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2831 ( .LO ( optlc_net_2549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2832 ( .LO ( optlc_net_2550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2833 ( .LO ( optlc_net_2551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2835 ( .LO ( optlc_net_2552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2836 ( .LO ( optlc_net_2553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2837 ( .LO ( optlc_net_2554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2838 ( .LO ( optlc_net_2555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2839 ( .LO ( optlc_net_2556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2840 ( .LO ( optlc_net_2557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2841 ( .LO ( optlc_net_2558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2843 ( .LO ( optlc_net_2559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2844 ( .LO ( optlc_net_2560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2845 ( .LO ( optlc_net_2561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2846 ( .LO ( optlc_net_2562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2847 ( .LO ( optlc_net_2563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2848 ( .LO ( optlc_net_2564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2849 ( .LO ( optlc_net_2565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2850 ( .LO ( optlc_net_2566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2851 ( .LO ( optlc_net_2567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2852 ( .LO ( optlc_net_2568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2853 ( .LO ( optlc_net_2569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2855 ( .LO ( optlc_net_2570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2856 ( .LO ( optlc_net_2571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2857 ( .LO ( optlc_net_2572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2859 ( .LO ( optlc_net_2573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2861 ( .LO ( optlc_net_2574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2862 ( .LO ( optlc_net_2575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2864 ( .LO ( optlc_net_2576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2865 ( .LO ( optlc_net_2577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2866 ( .LO ( optlc_net_2578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2867 ( .LO ( optlc_net_2579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2868 ( .LO ( optlc_net_2580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2869 ( .LO ( optlc_net_2581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2870 ( .LO ( optlc_net_2582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2871 ( .LO ( optlc_net_2583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2872 ( .LO ( optlc_net_2584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2873 ( .LO ( optlc_net_2585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2874 ( .LO ( optlc_net_2586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2875 ( .LO ( optlc_net_2587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2876 ( .LO ( optlc_net_2588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2877 ( .LO ( optlc_net_2589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2878 ( .LO ( optlc_net_2590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2879 ( .LO ( optlc_net_2591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2880 ( .LO ( optlc_net_2592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2882 ( .LO ( optlc_net_2593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2884 ( .LO ( optlc_net_2594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2885 ( .LO ( optlc_net_2595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2886 ( .LO ( optlc_net_2596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2887 ( .LO ( optlc_net_2597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2888 ( .LO ( optlc_net_2598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2889 ( .LO ( optlc_net_2599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2890 ( .LO ( optlc_net_2600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2891 ( .LO ( optlc_net_2601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2892 ( .LO ( optlc_net_2602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2893 ( .LO ( optlc_net_2603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2894 ( .LO ( optlc_net_2604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2895 ( .LO ( optlc_net_2605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2896 ( .LO ( optlc_net_2606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2897 ( .LO ( optlc_net_2607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2898 ( .LO ( optlc_net_2608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2899 ( .LO ( optlc_net_2609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2900 ( .LO ( optlc_net_2610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2901 ( .LO ( optlc_net_2611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2902 ( .LO ( optlc_net_2612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2903 ( .LO ( optlc_net_2613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2904 ( .LO ( optlc_net_2614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2906 ( .LO ( optlc_net_2615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2907 ( .LO ( optlc_net_2616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2908 ( .LO ( optlc_net_2617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2909 ( .LO ( optlc_net_2618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2910 ( .LO ( optlc_net_2619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2911 ( .LO ( optlc_net_2620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2913 ( .LO ( optlc_net_2621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2915 ( .LO ( optlc_net_2622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2917 ( .LO ( optlc_net_2623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2918 ( .LO ( optlc_net_2624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2919 ( .LO ( optlc_net_2625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2920 ( .LO ( optlc_net_2626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2921 ( .LO ( optlc_net_2627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2922 ( .LO ( optlc_net_2628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2923 ( .LO ( optlc_net_2629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2924 ( .LO ( optlc_net_2630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2926 ( .LO ( optlc_net_2631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2927 ( .LO ( optlc_net_2632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2928 ( .LO ( optlc_net_2633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2929 ( .LO ( optlc_net_2634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2930 ( .LO ( optlc_net_2635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2931 ( .LO ( optlc_net_2636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2932 ( .LO ( optlc_net_2637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2933 ( .LO ( optlc_net_2638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2934 ( .LO ( optlc_net_2639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2935 ( .LO ( optlc_net_2640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2936 ( .LO ( optlc_net_2641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2937 ( .LO ( optlc_net_2642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2938 ( .LO ( optlc_net_2643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2939 ( .LO ( optlc_net_2644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2940 ( .LO ( optlc_net_2645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2941 ( .LO ( optlc_net_2646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2942 ( .LO ( optlc_net_2647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2943 ( .LO ( optlc_net_2648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2944 ( .LO ( optlc_net_2649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2945 ( .LO ( optlc_net_2650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2946 ( .LO ( optlc_net_2651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2947 ( .LO ( optlc_net_2652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2948 ( .LO ( optlc_net_2653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2949 ( .LO ( optlc_net_2654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2950 ( .LO ( optlc_net_2655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2951 ( .LO ( optlc_net_2656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2952 ( .LO ( optlc_net_2657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2953 ( .LO ( optlc_net_2658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2954 ( .LO ( optlc_net_2659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2955 ( .LO ( optlc_net_2660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2956 ( .LO ( optlc_net_2661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2957 ( .LO ( optlc_net_2662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2958 ( .LO ( optlc_net_2663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2959 ( .LO ( optlc_net_2664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2960 ( .LO ( optlc_net_2665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2961 ( .LO ( optlc_net_2666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2962 ( .LO ( optlc_net_2667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2963 ( .LO ( optlc_net_2668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2964 ( .LO ( optlc_net_2669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2965 ( .LO ( optlc_net_2670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2966 ( .LO ( optlc_net_2671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2967 ( .LO ( optlc_net_2672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2968 ( .LO ( optlc_net_2673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2969 ( .LO ( optlc_net_2674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2970 ( .LO ( optlc_net_2675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2971 ( .LO ( optlc_net_2676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2972 ( .LO ( optlc_net_2677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2973 ( .LO ( optlc_net_2678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2974 ( .LO ( optlc_net_2679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2975 ( .LO ( optlc_net_2680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2976 ( .LO ( optlc_net_2681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2977 ( .LO ( optlc_net_2682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2978 ( .LO ( optlc_net_2683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2979 ( .LO ( optlc_net_2684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2980 ( .LO ( optlc_net_2685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2981 ( .LO ( optlc_net_2686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2982 ( .LO ( optlc_net_2687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2983 ( .LO ( optlc_net_2688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2984 ( .LO ( optlc_net_2689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2985 ( .LO ( optlc_net_2690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2986 ( .LO ( optlc_net_2691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2987 ( .LO ( optlc_net_2692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2988 ( .LO ( optlc_net_2693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2989 ( .LO ( optlc_net_2694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2990 ( .LO ( optlc_net_2695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2991 ( .LO ( optlc_net_2696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2992 ( .LO ( optlc_net_2697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2993 ( .LO ( optlc_net_2698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2994 ( .LO ( optlc_net_2699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2995 ( .LO ( optlc_net_2700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2996 ( .LO ( optlc_net_2701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2997 ( .LO ( optlc_net_2702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2998 ( .LO ( optlc_net_2703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2999 ( .LO ( optlc_net_2704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3000 ( .LO ( optlc_net_2705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3001 ( .LO ( optlc_net_2706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3002 ( .LO ( optlc_net_2707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3003 ( .LO ( optlc_net_2708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3004 ( .LO ( optlc_net_2709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3005 ( .LO ( optlc_net_2710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3006 ( .LO ( optlc_net_2711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3007 ( .LO ( optlc_net_2712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3008 ( .LO ( optlc_net_2713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3010 ( .LO ( optlc_net_2714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3011 ( .LO ( optlc_net_2715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3012 ( .LO ( optlc_net_2716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3013 ( .LO ( optlc_net_2717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3014 ( .LO ( optlc_net_2718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3015 ( .LO ( optlc_net_2719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3016 ( .LO ( optlc_net_2720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3017 ( .LO ( optlc_net_2721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3018 ( .LO ( optlc_net_2722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3020 ( .LO ( optlc_net_2723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3021 ( .LO ( optlc_net_2724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3022 ( .LO ( optlc_net_2725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3023 ( .LO ( optlc_net_2726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3024 ( .LO ( optlc_net_2727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3025 ( .LO ( optlc_net_2728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3026 ( .LO ( optlc_net_2729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3028 ( .LO ( optlc_net_2730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3029 ( .LO ( optlc_net_2731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3030 ( .LO ( optlc_net_2732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3031 ( .LO ( optlc_net_2733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3032 ( .LO ( optlc_net_2734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3033 ( .LO ( optlc_net_2735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3034 ( .LO ( optlc_net_2736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3035 ( .LO ( optlc_net_2737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3036 ( .LO ( optlc_net_2738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3037 ( .LO ( optlc_net_2739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3038 ( .LO ( optlc_net_2740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3039 ( .LO ( optlc_net_2741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3040 ( .LO ( optlc_net_2742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3041 ( .LO ( optlc_net_2743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3042 ( .LO ( optlc_net_2744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3043 ( .LO ( optlc_net_2745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3044 ( .LO ( optlc_net_2746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3045 ( .LO ( optlc_net_2747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3046 ( .LO ( optlc_net_2748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3047 ( .LO ( optlc_net_2749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3048 ( .LO ( optlc_net_2750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3049 ( .LO ( optlc_net_2751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3050 ( .LO ( optlc_net_2752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3051 ( .LO ( optlc_net_2753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3052 ( .LO ( optlc_net_2754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3053 ( .LO ( optlc_net_2755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3054 ( .LO ( optlc_net_2756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3055 ( .LO ( optlc_net_2757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3056 ( .LO ( optlc_net_2758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3057 ( .LO ( optlc_net_2759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3058 ( .LO ( optlc_net_2760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3059 ( .LO ( optlc_net_2761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3060 ( .LO ( optlc_net_2762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3061 ( .LO ( optlc_net_2763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3062 ( .LO ( optlc_net_2764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3063 ( .LO ( optlc_net_2765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3064 ( .LO ( optlc_net_2766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3065 ( .LO ( optlc_net_2767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3066 ( .LO ( optlc_net_2768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3067 ( .LO ( optlc_net_2769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3068 ( .LO ( optlc_net_2770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3069 ( .LO ( optlc_net_2771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3070 ( .LO ( optlc_net_2772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3071 ( .LO ( optlc_net_2773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3072 ( .LO ( optlc_net_2774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3073 ( .LO ( optlc_net_2775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3074 ( .LO ( optlc_net_2776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3075 ( .LO ( optlc_net_2777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3076 ( .LO ( optlc_net_2778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3077 ( .LO ( optlc_net_2779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3078 ( .LO ( optlc_net_2780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3079 ( .LO ( optlc_net_2781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3080 ( .LO ( optlc_net_2782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3081 ( .LO ( optlc_net_2783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3082 ( .LO ( optlc_net_2784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3083 ( .LO ( optlc_net_2785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3084 ( .LO ( optlc_net_2786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3086 ( .LO ( optlc_net_2787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3087 ( .LO ( optlc_net_2788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3088 ( .LO ( optlc_net_2789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3089 ( .LO ( optlc_net_2790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3090 ( .LO ( optlc_net_2791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3091 ( .LO ( optlc_net_2792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3092 ( .LO ( optlc_net_2793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3093 ( .LO ( optlc_net_2794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3094 ( .LO ( optlc_net_2795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3095 ( .LO ( optlc_net_2796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3096 ( .LO ( optlc_net_2797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3097 ( .LO ( optlc_net_2798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3098 ( .LO ( optlc_net_2799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3099 ( .LO ( optlc_net_2800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3100 ( .LO ( optlc_net_2801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3101 ( .LO ( optlc_net_2802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3103 ( .LO ( optlc_net_2803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3104 ( .LO ( optlc_net_2804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3105 ( .LO ( optlc_net_2805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3106 ( .LO ( optlc_net_2806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3107 ( .LO ( optlc_net_2807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3108 ( .LO ( optlc_net_2808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3109 ( .LO ( optlc_net_2809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3110 ( .LO ( optlc_net_2810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3111 ( .LO ( optlc_net_2811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3112 ( .LO ( optlc_net_2812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3113 ( .LO ( optlc_net_2813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3114 ( .LO ( optlc_net_2814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3115 ( .LO ( optlc_net_2815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3116 ( .LO ( optlc_net_2816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3117 ( .LO ( optlc_net_2817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3118 ( .LO ( optlc_net_2818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3119 ( .LO ( optlc_net_2819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3120 ( .LO ( optlc_net_2820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3121 ( .LO ( optlc_net_2821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3122 ( .LO ( optlc_net_2822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3123 ( .LO ( optlc_net_2823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3124 ( .LO ( optlc_net_2824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3125 ( .LO ( optlc_net_2825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3126 ( .LO ( optlc_net_2826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3127 ( .LO ( optlc_net_2827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3128 ( .LO ( optlc_net_2828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3129 ( .LO ( optlc_net_2829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3130 ( .LO ( optlc_net_2830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3131 ( .LO ( optlc_net_2831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3132 ( .LO ( optlc_net_2832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3133 ( .LO ( optlc_net_2833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3134 ( .LO ( optlc_net_2834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3135 ( .LO ( optlc_net_2835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3136 ( .LO ( optlc_net_2836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3137 ( .LO ( optlc_net_2837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3138 ( .LO ( optlc_net_2838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3139 ( .LO ( optlc_net_2839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3140 ( .LO ( optlc_net_2840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3141 ( .LO ( optlc_net_2841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3142 ( .LO ( optlc_net_2842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3143 ( .LO ( optlc_net_2843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3144 ( .LO ( optlc_net_2844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3145 ( .LO ( optlc_net_2845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3146 ( .LO ( optlc_net_2846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3147 ( .LO ( optlc_net_2847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3148 ( .LO ( optlc_net_2848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3149 ( .LO ( optlc_net_2849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3150 ( .LO ( optlc_net_2850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3151 ( .LO ( optlc_net_2851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3152 ( .LO ( optlc_net_2852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3153 ( .LO ( optlc_net_2853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3154 ( .LO ( optlc_net_2854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3155 ( .LO ( optlc_net_2855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3156 ( .LO ( optlc_net_2856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3157 ( .LO ( optlc_net_2857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3158 ( .LO ( optlc_net_2858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3159 ( .LO ( optlc_net_2859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3160 ( .LO ( optlc_net_2860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3161 ( .LO ( optlc_net_2861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3162 ( .LO ( optlc_net_2862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3163 ( .LO ( optlc_net_2863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3164 ( .LO ( optlc_net_2864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3165 ( .LO ( optlc_net_2865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3166 ( .LO ( optlc_net_2866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3167 ( .LO ( optlc_net_2867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3168 ( .LO ( optlc_net_2868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3169 ( .LO ( optlc_net_2869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3170 ( .LO ( optlc_net_2870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3171 ( .LO ( optlc_net_2871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3172 ( .LO ( optlc_net_2872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3173 ( .LO ( optlc_net_2873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3174 ( .LO ( optlc_net_2874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3175 ( .LO ( optlc_net_2875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3176 ( .LO ( optlc_net_2876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3177 ( .LO ( optlc_net_2877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3178 ( .LO ( optlc_net_2878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3179 ( .LO ( optlc_net_2879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3180 ( .LO ( optlc_net_2880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3181 ( .LO ( optlc_net_2881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3182 ( .LO ( optlc_net_2882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3183 ( .LO ( optlc_net_2883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3184 ( .LO ( optlc_net_2884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3185 ( .LO ( optlc_net_2885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3186 ( .LO ( optlc_net_2886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3187 ( .LO ( optlc_net_2887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3188 ( .LO ( optlc_net_2888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3189 ( .LO ( optlc_net_2889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3190 ( .LO ( optlc_net_2890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3191 ( .LO ( optlc_net_2891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3192 ( .LO ( optlc_net_2892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3193 ( .LO ( optlc_net_2893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3194 ( .LO ( optlc_net_2894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3195 ( .LO ( optlc_net_2895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3196 ( .LO ( optlc_net_2896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3197 ( .LO ( optlc_net_2897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3198 ( .LO ( optlc_net_2898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3199 ( .LO ( optlc_net_2899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3200 ( .LO ( optlc_net_2900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3201 ( .LO ( optlc_net_2901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3202 ( .LO ( optlc_net_2902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3203 ( .LO ( optlc_net_2903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3204 ( .LO ( optlc_net_2904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3205 ( .LO ( optlc_net_2905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3206 ( .LO ( optlc_net_2906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3207 ( .LO ( optlc_net_2907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3208 ( .LO ( optlc_net_2908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3209 ( .LO ( optlc_net_2909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3210 ( .LO ( optlc_net_2910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3211 ( .LO ( optlc_net_2911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3212 ( .LO ( optlc_net_2912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3213 ( .LO ( optlc_net_2913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3214 ( .LO ( optlc_net_2914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3215 ( .LO ( optlc_net_2915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3216 ( .LO ( optlc_net_2916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3217 ( .LO ( optlc_net_2917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3218 ( .LO ( optlc_net_2918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3219 ( .LO ( optlc_net_2919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3220 ( .LO ( optlc_net_2920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3221 ( .LO ( optlc_net_2921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3222 ( .LO ( optlc_net_2922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3223 ( .LO ( optlc_net_2923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3224 ( .LO ( optlc_net_2924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3225 ( .LO ( optlc_net_2925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3226 ( .LO ( optlc_net_2926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3227 ( .LO ( optlc_net_2927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3228 ( .LO ( optlc_net_2928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3229 ( .LO ( optlc_net_2929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3230 ( .LO ( optlc_net_2930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3231 ( .LO ( optlc_net_2931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3232 ( .LO ( optlc_net_2932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3233 ( .LO ( optlc_net_2933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3234 ( .LO ( optlc_net_2934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3235 ( .LO ( optlc_net_2935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3236 ( .LO ( optlc_net_2936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3237 ( .LO ( optlc_net_2937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3238 ( .LO ( optlc_net_2938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3239 ( .LO ( optlc_net_2939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3240 ( .LO ( optlc_net_2940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3241 ( .LO ( optlc_net_2941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3242 ( .LO ( optlc_net_2942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3243 ( .LO ( optlc_net_2943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3244 ( .LO ( optlc_net_2944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3245 ( .LO ( optlc_net_2945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3246 ( .LO ( optlc_net_2946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3247 ( .LO ( optlc_net_2947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3248 ( .LO ( optlc_net_2948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3249 ( .LO ( optlc_net_2949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3250 ( .LO ( optlc_net_2950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3251 ( .LO ( optlc_net_2951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3252 ( .LO ( optlc_net_2952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3253 ( .LO ( optlc_net_2953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3254 ( .LO ( optlc_net_2954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3255 ( .LO ( optlc_net_2955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3256 ( .LO ( optlc_net_2956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3257 ( .LO ( optlc_net_2957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3258 ( .LO ( optlc_net_2958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3259 ( .LO ( optlc_net_2959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3260 ( .LO ( optlc_net_2960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3261 ( .LO ( optlc_net_2961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3262 ( .LO ( optlc_net_2962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3263 ( .LO ( optlc_net_2963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3264 ( .LO ( optlc_net_2964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3265 ( .LO ( optlc_net_2965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3266 ( .LO ( optlc_net_2966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3267 ( .LO ( optlc_net_2967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3268 ( .LO ( optlc_net_2968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3269 ( .LO ( optlc_net_2969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3270 ( .LO ( optlc_net_2970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3271 ( .LO ( optlc_net_2971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3272 ( .LO ( optlc_net_2972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3273 ( .LO ( optlc_net_2973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3274 ( .LO ( optlc_net_2974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3275 ( .LO ( optlc_net_2975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3276 ( .LO ( optlc_net_2976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3277 ( .LO ( optlc_net_2977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3278 ( .LO ( optlc_net_2978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3279 ( .LO ( optlc_net_2979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3280 ( .LO ( optlc_net_2980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3281 ( .LO ( optlc_net_2981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3282 ( .LO ( optlc_net_2982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3283 ( .LO ( optlc_net_2983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3284 ( .LO ( optlc_net_2984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3285 ( .LO ( optlc_net_2985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3286 ( .LO ( optlc_net_2986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3287 ( .LO ( optlc_net_2987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3288 ( .LO ( optlc_net_2988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3289 ( .LO ( optlc_net_2989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3290 ( .LO ( optlc_net_2990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3291 ( .LO ( optlc_net_2991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3292 ( .LO ( optlc_net_2992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3293 ( .LO ( optlc_net_2993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3294 ( .LO ( optlc_net_2994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3295 ( .LO ( optlc_net_2995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3296 ( .LO ( optlc_net_2996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3297 ( .LO ( optlc_net_2997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3298 ( .LO ( optlc_net_2998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3299 ( .LO ( optlc_net_2999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3300 ( .LO ( optlc_net_3000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3301 ( .LO ( optlc_net_3001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3302 ( .LO ( optlc_net_3002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3303 ( .LO ( optlc_net_3003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3304 ( .LO ( optlc_net_3004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3305 ( .LO ( optlc_net_3005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3306 ( .LO ( optlc_net_3006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3307 ( .LO ( optlc_net_3007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3308 ( .LO ( optlc_net_3008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3309 ( .LO ( optlc_net_3009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3310 ( .LO ( optlc_net_3010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3311 ( .LO ( optlc_net_3011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3312 ( .LO ( optlc_net_3012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3313 ( .LO ( optlc_net_3013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3314 ( .LO ( optlc_net_3014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3315 ( .LO ( optlc_net_3015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3316 ( .LO ( optlc_net_3016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3317 ( .LO ( optlc_net_3017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3318 ( .LO ( optlc_net_3018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3319 ( .LO ( optlc_net_3019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3320 ( .LO ( optlc_net_3020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3321 ( .LO ( optlc_net_3021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3322 ( .LO ( optlc_net_3022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3323 ( .LO ( optlc_net_3023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3324 ( .LO ( optlc_net_3024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3325 ( .LO ( optlc_net_3025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3327 ( .LO ( optlc_net_3026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3328 ( .LO ( optlc_net_3027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3329 ( .LO ( optlc_net_3028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3330 ( .LO ( optlc_net_3029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3331 ( .LO ( optlc_net_3030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3332 ( .LO ( optlc_net_3031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3333 ( .LO ( optlc_net_3032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3334 ( .LO ( optlc_net_3033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3335 ( .LO ( optlc_net_3034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3336 ( .LO ( optlc_net_3035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3337 ( .LO ( optlc_net_3036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3338 ( .LO ( optlc_net_3037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3339 ( .LO ( optlc_net_3038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3340 ( .LO ( optlc_net_3039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3341 ( .LO ( optlc_net_3040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3342 ( .LO ( optlc_net_3041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3343 ( .LO ( optlc_net_3042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3344 ( .LO ( optlc_net_3043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3345 ( .LO ( optlc_net_3044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3346 ( .LO ( optlc_net_3045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3347 ( .LO ( optlc_net_3046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3348 ( .LO ( optlc_net_3047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3349 ( .LO ( optlc_net_3048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3350 ( .LO ( optlc_net_3049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3351 ( .LO ( optlc_net_3050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3352 ( .LO ( optlc_net_3051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3353 ( .LO ( optlc_net_3052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3354 ( .LO ( optlc_net_3053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3355 ( .LO ( optlc_net_3054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3356 ( .LO ( optlc_net_3055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3357 ( .LO ( optlc_net_3056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3358 ( .LO ( optlc_net_3057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3359 ( .LO ( optlc_net_3058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3360 ( .LO ( optlc_net_3059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3361 ( .LO ( optlc_net_3060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3362 ( .LO ( optlc_net_3061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3363 ( .LO ( optlc_net_3062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3364 ( .LO ( optlc_net_3063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3365 ( .LO ( optlc_net_3064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3366 ( .LO ( optlc_net_3065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3367 ( .LO ( optlc_net_3066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3368 ( .LO ( optlc_net_3067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3369 ( .LO ( optlc_net_3068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3370 ( .LO ( optlc_net_3069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3371 ( .LO ( optlc_net_3070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3372 ( .LO ( optlc_net_3071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3373 ( .LO ( optlc_net_3072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3374 ( .LO ( optlc_net_3073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3375 ( .LO ( optlc_net_3074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3376 ( .LO ( optlc_net_3075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3377 ( .LO ( optlc_net_3076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3378 ( .LO ( optlc_net_3077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3379 ( .LO ( optlc_net_3078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3380 ( .LO ( optlc_net_3079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3381 ( .LO ( optlc_net_3080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3382 ( .LO ( optlc_net_3081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3383 ( .LO ( optlc_net_3082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3384 ( .LO ( optlc_net_3083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3385 ( .LO ( optlc_net_3084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3386 ( .LO ( optlc_net_3085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3387 ( .LO ( optlc_net_3086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3388 ( .LO ( optlc_net_3087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3389 ( .LO ( optlc_net_3088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3390 ( .LO ( optlc_net_3089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3391 ( .LO ( optlc_net_3090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3392 ( .LO ( optlc_net_3091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3393 ( .LO ( optlc_net_3092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3394 ( .LO ( optlc_net_3093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3395 ( .LO ( optlc_net_3094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3396 ( .LO ( optlc_net_3095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3397 ( .LO ( optlc_net_3096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3398 ( .LO ( optlc_net_3097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3399 ( .LO ( optlc_net_3098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3400 ( .LO ( optlc_net_3099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3401 ( .LO ( optlc_net_3100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3402 ( .LO ( optlc_net_3101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3403 ( .LO ( optlc_net_3102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3404 ( .LO ( optlc_net_3103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3405 ( .LO ( optlc_net_3104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3406 ( .LO ( optlc_net_3105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3407 ( .LO ( optlc_net_3106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3408 ( .LO ( optlc_net_3107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3409 ( .LO ( optlc_net_3108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3410 ( .LO ( optlc_net_3109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3411 ( .LO ( optlc_net_3110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3412 ( .LO ( optlc_net_3111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3413 ( .LO ( optlc_net_3112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3414 ( .LO ( optlc_net_3113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3415 ( .LO ( optlc_net_3114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3416 ( .LO ( optlc_net_3115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3417 ( .LO ( optlc_net_3116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3418 ( .LO ( optlc_net_3117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3419 ( .LO ( optlc_net_3118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3420 ( .LO ( optlc_net_3119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3421 ( .LO ( optlc_net_3120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3422 ( .LO ( optlc_net_3121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3423 ( .LO ( optlc_net_3122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3424 ( .LO ( optlc_net_3123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3425 ( .LO ( optlc_net_3124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3426 ( .LO ( optlc_net_3125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3427 ( .LO ( optlc_net_3126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3428 ( .LO ( optlc_net_3127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3429 ( .LO ( optlc_net_3128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3430 ( .LO ( optlc_net_3129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3431 ( .LO ( optlc_net_3130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3432 ( .LO ( optlc_net_3131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3433 ( .LO ( optlc_net_3132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3434 ( .LO ( optlc_net_3133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3435 ( .LO ( optlc_net_3134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3436 ( .LO ( optlc_net_3135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3437 ( .LO ( optlc_net_3136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3438 ( .LO ( optlc_net_3137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3439 ( .LO ( optlc_net_3138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3440 ( .LO ( optlc_net_3139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3441 ( .LO ( optlc_net_3140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3442 ( .LO ( optlc_net_3141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3443 ( .LO ( optlc_net_3142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3444 ( .LO ( optlc_net_3143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3445 ( .LO ( optlc_net_3144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3446 ( .LO ( optlc_net_3145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3447 ( .LO ( optlc_net_3146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3448 ( .LO ( optlc_net_3147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3449 ( .LO ( optlc_net_3148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3450 ( .LO ( optlc_net_3149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3451 ( .LO ( optlc_net_3150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3452 ( .LO ( optlc_net_3151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3453 ( .LO ( optlc_net_3152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3454 ( .LO ( optlc_net_3153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3455 ( .LO ( optlc_net_3154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3456 ( .LO ( optlc_net_3155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3457 ( .LO ( optlc_net_3156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3458 ( .LO ( optlc_net_3157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3459 ( .LO ( optlc_net_3158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3460 ( .LO ( optlc_net_3159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3461 ( .LO ( optlc_net_3160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3462 ( .LO ( optlc_net_3161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3463 ( .LO ( optlc_net_3162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3464 ( .LO ( optlc_net_3163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3465 ( .LO ( optlc_net_3164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3466 ( .LO ( optlc_net_3165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3467 ( .LO ( optlc_net_3166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3468 ( .LO ( optlc_net_3167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3469 ( .LO ( optlc_net_3168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3470 ( .LO ( optlc_net_3169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3471 ( .LO ( optlc_net_3170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3472 ( .LO ( optlc_net_3171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3473 ( .LO ( optlc_net_3172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3474 ( .LO ( optlc_net_3173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3475 ( .LO ( optlc_net_3174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3476 ( .LO ( optlc_net_3175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3477 ( .LO ( optlc_net_3176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3478 ( .LO ( optlc_net_3177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3479 ( .LO ( optlc_net_3178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3480 ( .LO ( optlc_net_3179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3481 ( .LO ( optlc_net_3180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3482 ( .LO ( optlc_net_3181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3483 ( .LO ( optlc_net_3182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3484 ( .LO ( optlc_net_3183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3485 ( .LO ( optlc_net_3184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3486 ( .LO ( optlc_net_3185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3487 ( .LO ( optlc_net_3186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3488 ( .LO ( optlc_net_3187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3489 ( .LO ( optlc_net_3188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3490 ( .LO ( optlc_net_3189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3491 ( .LO ( optlc_net_3190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3492 ( .LO ( optlc_net_3191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3493 ( .LO ( optlc_net_3192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3494 ( .LO ( optlc_net_3193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3495 ( .LO ( optlc_net_3194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3496 ( .LO ( optlc_net_3195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3497 ( .LO ( optlc_net_3196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3498 ( .LO ( optlc_net_3197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3499 ( .LO ( optlc_net_3198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3500 ( .LO ( optlc_net_3199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3501 ( .LO ( optlc_net_3200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3502 ( .LO ( optlc_net_3201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3503 ( .LO ( optlc_net_3202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3504 ( .LO ( optlc_net_3203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3505 ( .LO ( optlc_net_3204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3506 ( .LO ( optlc_net_3205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3507 ( .LO ( optlc_net_3206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3508 ( .LO ( optlc_net_3207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3509 ( .LO ( optlc_net_3208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3510 ( .LO ( optlc_net_3209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3511 ( .LO ( optlc_net_3210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3512 ( .LO ( optlc_net_3211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3513 ( .LO ( optlc_net_3212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3514 ( .LO ( optlc_net_3213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3515 ( .LO ( optlc_net_3214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3516 ( .LO ( optlc_net_3215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3517 ( .LO ( optlc_net_3216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3518 ( .LO ( optlc_net_3217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3519 ( .LO ( optlc_net_3218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3520 ( .LO ( optlc_net_3219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3521 ( .LO ( optlc_net_3220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3522 ( .LO ( optlc_net_3221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3523 ( .LO ( optlc_net_3222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3524 ( .LO ( optlc_net_3223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3525 ( .LO ( optlc_net_3224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3526 ( .LO ( optlc_net_3225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3527 ( .LO ( optlc_net_3226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3528 ( .LO ( optlc_net_3227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3529 ( .LO ( optlc_net_3228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3530 ( .LO ( optlc_net_3229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3531 ( .LO ( optlc_net_3230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3532 ( .LO ( optlc_net_3231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3533 ( .LO ( optlc_net_3232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3534 ( .LO ( optlc_net_3233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3535 ( .LO ( optlc_net_3234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3536 ( .LO ( optlc_net_3235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3537 ( .LO ( optlc_net_3236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3538 ( .LO ( optlc_net_3237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3539 ( .LO ( optlc_net_3238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3540 ( .LO ( optlc_net_3239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3541 ( .LO ( optlc_net_3240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3542 ( .LO ( optlc_net_3241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3543 ( .LO ( optlc_net_3242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3544 ( .LO ( optlc_net_3243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3545 ( .LO ( optlc_net_3244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3546 ( .LO ( optlc_net_3245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3547 ( .LO ( optlc_net_3246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3548 ( .LO ( optlc_net_3247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3549 ( .LO ( optlc_net_3248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3550 ( .LO ( optlc_net_3249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3551 ( .LO ( optlc_net_3250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3552 ( .LO ( optlc_net_3251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3553 ( .LO ( optlc_net_3252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3554 ( .LO ( optlc_net_3253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3555 ( .LO ( optlc_net_3254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3556 ( .LO ( optlc_net_3255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3557 ( .LO ( optlc_net_3256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3558 ( .LO ( optlc_net_3257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3559 ( .LO ( optlc_net_3258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3560 ( .LO ( optlc_net_3259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3561 ( .LO ( optlc_net_3260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3562 ( .LO ( optlc_net_3261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3563 ( .LO ( optlc_net_3262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3564 ( .LO ( optlc_net_3263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3565 ( .LO ( optlc_net_3264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3566 ( .LO ( optlc_net_3265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3567 ( .LO ( optlc_net_3266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3568 ( .LO ( optlc_net_3267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3569 ( .LO ( optlc_net_3268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3570 ( .LO ( optlc_net_3269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3571 ( .LO ( optlc_net_3270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3572 ( .LO ( optlc_net_3271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3573 ( .LO ( optlc_net_3272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3574 ( .LO ( optlc_net_3273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3575 ( .LO ( optlc_net_3274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3576 ( .LO ( optlc_net_3275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3577 ( .LO ( optlc_net_3276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3578 ( .LO ( optlc_net_3277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3579 ( .LO ( optlc_net_3278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3580 ( .LO ( optlc_net_3279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3581 ( .LO ( optlc_net_3280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3582 ( .LO ( optlc_net_3281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3583 ( .LO ( optlc_net_3282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3584 ( .LO ( optlc_net_3283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3585 ( .LO ( optlc_net_3284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3586 ( .LO ( optlc_net_3285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3587 ( .LO ( optlc_net_3286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3588 ( .LO ( optlc_net_3287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3589 ( .LO ( optlc_net_3288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3590 ( .LO ( optlc_net_3289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3591 ( .LO ( optlc_net_3290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3592 ( .LO ( optlc_net_3291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3593 ( .LO ( optlc_net_3292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3594 ( .LO ( optlc_net_3293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3595 ( .LO ( optlc_net_3294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3596 ( .LO ( optlc_net_3295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3597 ( .LO ( optlc_net_3296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3598 ( .LO ( optlc_net_3297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3599 ( .LO ( optlc_net_3298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3600 ( .LO ( optlc_net_3299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3601 ( .LO ( optlc_net_3300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3602 ( .LO ( optlc_net_3301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3603 ( .LO ( optlc_net_3302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3604 ( .LO ( optlc_net_3303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3605 ( .LO ( optlc_net_3304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3606 ( .LO ( optlc_net_3305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3607 ( .LO ( optlc_net_3306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3608 ( .LO ( optlc_net_3307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3609 ( .LO ( optlc_net_3308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3610 ( .LO ( optlc_net_3309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3611 ( .LO ( optlc_net_3310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3612 ( .LO ( optlc_net_3311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3613 ( .LO ( optlc_net_3312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3614 ( .LO ( optlc_net_3313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3615 ( .LO ( optlc_net_3314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3616 ( .LO ( optlc_net_3315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3617 ( .LO ( optlc_net_3316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3618 ( .LO ( optlc_net_3317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3619 ( .LO ( optlc_net_3318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3620 ( .LO ( optlc_net_3319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3621 ( .LO ( optlc_net_3320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3622 ( .LO ( optlc_net_3321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3623 ( .LO ( optlc_net_3322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3624 ( .LO ( optlc_net_3323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3625 ( .LO ( optlc_net_3324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3626 ( .LO ( optlc_net_3325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3627 ( .LO ( optlc_net_3326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3628 ( .LO ( optlc_net_3327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3629 ( .LO ( optlc_net_3328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3630 ( .LO ( optlc_net_3329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3631 ( .LO ( optlc_net_3330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3632 ( .LO ( optlc_net_3331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3633 ( .LO ( optlc_net_3332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3634 ( .LO ( optlc_net_3333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3635 ( .LO ( optlc_net_3334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3636 ( .LO ( optlc_net_3335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3637 ( .LO ( optlc_net_3336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3638 ( .LO ( optlc_net_3337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3639 ( .LO ( optlc_net_3338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3640 ( .LO ( optlc_net_3339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3641 ( .LO ( optlc_net_3340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3642 ( .LO ( optlc_net_3341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3643 ( .LO ( optlc_net_3342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3644 ( .LO ( optlc_net_3343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3645 ( .LO ( optlc_net_3344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3646 ( .LO ( optlc_net_3345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3647 ( .LO ( optlc_net_3346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3648 ( .LO ( optlc_net_3347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3649 ( .LO ( optlc_net_3348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3650 ( .LO ( optlc_net_3349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3651 ( .LO ( optlc_net_3350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3652 ( .LO ( optlc_net_3351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3653 ( .LO ( optlc_net_3352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3654 ( .LO ( optlc_net_3353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3655 ( .LO ( optlc_net_3354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3656 ( .LO ( optlc_net_3355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3657 ( .LO ( optlc_net_3356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3658 ( .LO ( optlc_net_3357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3659 ( .LO ( optlc_net_3358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3660 ( .LO ( optlc_net_3359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3661 ( .LO ( optlc_net_3360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3662 ( .LO ( optlc_net_3361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3663 ( .LO ( optlc_net_3362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3664 ( .LO ( optlc_net_3363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3665 ( .LO ( optlc_net_3364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3666 ( .LO ( optlc_net_3365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3667 ( .LO ( optlc_net_3366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3668 ( .LO ( optlc_net_3367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3669 ( .LO ( optlc_net_3368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3670 ( .LO ( optlc_net_3369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3671 ( .LO ( optlc_net_3370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3672 ( .LO ( optlc_net_3371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3673 ( .LO ( optlc_net_3372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3674 ( .LO ( optlc_net_3373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3675 ( .LO ( optlc_net_3374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3676 ( .LO ( optlc_net_3375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3677 ( .LO ( optlc_net_3376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3678 ( .LO ( optlc_net_3377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3679 ( .LO ( optlc_net_3378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3680 ( .LO ( optlc_net_3379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3681 ( .LO ( optlc_net_3380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3682 ( .LO ( optlc_net_3381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3683 ( .LO ( optlc_net_3382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3684 ( .LO ( optlc_net_3383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3685 ( .LO ( optlc_net_3384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3686 ( .LO ( optlc_net_3385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3687 ( .LO ( optlc_net_3386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3688 ( .LO ( optlc_net_3387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3689 ( .LO ( optlc_net_3388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3690 ( .LO ( optlc_net_3389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3691 ( .LO ( optlc_net_3390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3692 ( .LO ( optlc_net_3391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3693 ( .LO ( optlc_net_3392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3694 ( .LO ( optlc_net_3393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3695 ( .LO ( optlc_net_3394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3696 ( .LO ( optlc_net_3395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3697 ( .LO ( optlc_net_3396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3698 ( .LO ( optlc_net_3397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3699 ( .LO ( optlc_net_3398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3700 ( .LO ( optlc_net_3399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3701 ( .LO ( optlc_net_3400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3702 ( .LO ( optlc_net_3401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3703 ( .LO ( optlc_net_3402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3704 ( .LO ( optlc_net_3403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3705 ( .LO ( optlc_net_3404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3706 ( .LO ( optlc_net_3405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3707 ( .LO ( optlc_net_3406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3708 ( .LO ( optlc_net_3407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3709 ( .LO ( optlc_net_3408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3710 ( .LO ( optlc_net_3409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3711 ( .LO ( optlc_net_3410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3712 ( .LO ( optlc_net_3411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3713 ( .LO ( optlc_net_3412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3714 ( .LO ( optlc_net_3413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3715 ( .LO ( optlc_net_3414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3716 ( .LO ( optlc_net_3415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3717 ( .LO ( optlc_net_3416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3718 ( .LO ( optlc_net_3417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3719 ( .LO ( optlc_net_3418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3720 ( .LO ( optlc_net_3419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3721 ( .LO ( optlc_net_3420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3722 ( .LO ( optlc_net_3421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3723 ( .LO ( optlc_net_3422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3724 ( .LO ( optlc_net_3423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3725 ( .LO ( optlc_net_3424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3726 ( .LO ( optlc_net_3425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3727 ( .LO ( optlc_net_3426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3728 ( .LO ( optlc_net_3427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3729 ( .LO ( optlc_net_3428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3730 ( .LO ( optlc_net_3429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3731 ( .LO ( optlc_net_3430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3732 ( .LO ( optlc_net_3431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3733 ( .LO ( optlc_net_3432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3734 ( .LO ( optlc_net_3433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3735 ( .LO ( optlc_net_3434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3736 ( .LO ( optlc_net_3435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3737 ( .LO ( optlc_net_3436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3738 ( .LO ( optlc_net_3437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3739 ( .LO ( optlc_net_3438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3740 ( .LO ( optlc_net_3439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3741 ( .LO ( optlc_net_3440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3742 ( .LO ( optlc_net_3441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3743 ( .LO ( optlc_net_3442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3744 ( .LO ( optlc_net_3443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3745 ( .LO ( optlc_net_3444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3746 ( .LO ( optlc_net_3445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3747 ( .LO ( optlc_net_3446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3748 ( .LO ( optlc_net_3447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3749 ( .LO ( optlc_net_3448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3750 ( .LO ( optlc_net_3449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3751 ( .LO ( optlc_net_3450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3752 ( .LO ( optlc_net_3451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3753 ( .LO ( optlc_net_3452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3754 ( .LO ( optlc_net_3453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3755 ( .LO ( optlc_net_3454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3756 ( .LO ( optlc_net_3455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3757 ( .LO ( optlc_net_3456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3758 ( .LO ( optlc_net_3457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3759 ( .LO ( optlc_net_3458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3760 ( .LO ( optlc_net_3459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3761 ( .LO ( optlc_net_3460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3762 ( .LO ( optlc_net_3461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3763 ( .LO ( optlc_net_3462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3764 ( .LO ( optlc_net_3463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3765 ( .LO ( optlc_net_3464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3766 ( .LO ( optlc_net_3465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3767 ( .LO ( optlc_net_3466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3768 ( .LO ( optlc_net_3467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3769 ( .LO ( optlc_net_3468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3770 ( .LO ( optlc_net_3469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3771 ( .LO ( optlc_net_3470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3772 ( .LO ( optlc_net_3471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3773 ( .LO ( optlc_net_3472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3774 ( .LO ( optlc_net_3473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3775 ( .LO ( optlc_net_3474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3776 ( .LO ( optlc_net_3475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3777 ( .LO ( optlc_net_3476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3778 ( .LO ( optlc_net_3477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3779 ( .LO ( optlc_net_3478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3780 ( .LO ( optlc_net_3479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3781 ( .LO ( optlc_net_3480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3782 ( .LO ( optlc_net_3481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3783 ( .LO ( optlc_net_3482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3784 ( .LO ( optlc_net_3483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3785 ( .LO ( optlc_net_3484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3786 ( .LO ( optlc_net_3485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3787 ( .LO ( optlc_net_3486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3788 ( .LO ( optlc_net_3487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3789 ( .LO ( optlc_net_3488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3790 ( .LO ( optlc_net_3489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3791 ( .LO ( optlc_net_3490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3792 ( .LO ( optlc_net_3491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3793 ( .LO ( optlc_net_3492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3794 ( .LO ( optlc_net_3493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3795 ( .LO ( optlc_net_3494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3796 ( .LO ( optlc_net_3495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3797 ( .LO ( optlc_net_3496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3798 ( .LO ( optlc_net_3497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3799 ( .LO ( optlc_net_3498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3800 ( .LO ( optlc_net_3499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3801 ( .LO ( optlc_net_3500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3802 ( .LO ( optlc_net_3501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3803 ( .LO ( optlc_net_3502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3804 ( .LO ( optlc_net_3503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3805 ( .LO ( optlc_net_3504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3806 ( .LO ( optlc_net_3505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3807 ( .LO ( optlc_net_3506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3808 ( .LO ( optlc_net_3507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3809 ( .LO ( optlc_net_3508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3810 ( .LO ( optlc_net_3509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3811 ( .LO ( optlc_net_3510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3812 ( .LO ( optlc_net_3511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3813 ( .LO ( optlc_net_3512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3814 ( .LO ( optlc_net_3513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3815 ( .LO ( optlc_net_3514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3816 ( .LO ( optlc_net_3515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3817 ( .LO ( optlc_net_3516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3818 ( .LO ( optlc_net_3517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3819 ( .LO ( optlc_net_3518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3820 ( .LO ( optlc_net_3519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3821 ( .LO ( optlc_net_3520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3822 ( .LO ( optlc_net_3521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3823 ( .LO ( optlc_net_3522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3824 ( .LO ( optlc_net_3523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3825 ( .LO ( optlc_net_3524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3826 ( .LO ( optlc_net_3525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3827 ( .LO ( optlc_net_3526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3828 ( .LO ( optlc_net_3527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3829 ( .LO ( optlc_net_3528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3830 ( .LO ( optlc_net_3529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3831 ( .LO ( optlc_net_3530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3832 ( .LO ( optlc_net_3531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3833 ( .LO ( optlc_net_3532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3834 ( .LO ( optlc_net_3533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3835 ( .LO ( optlc_net_3534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3836 ( .LO ( optlc_net_3535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3837 ( .LO ( optlc_net_3536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3838 ( .LO ( optlc_net_3537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3839 ( .LO ( optlc_net_3538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ;
+endmodule
+
+
diff --git a/SOFA_QLHD/README.md b/SOFA_QLHD/README.md
new file mode 100644
index 0000000..ca8f1de
--- /dev/null
+++ b/SOFA_QLHD/README.md
@@ -0,0 +1,5 @@
+FPGA1212_FLAT_HD_SKY_PNR
+====================
+
+12x12 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`.
+Flat Module design style
\ No newline at end of file
diff --git a/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.gds.gz b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.gds.gz
new file mode 100644
index 0000000..df12726
--- /dev/null
+++ b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.gds.gz
Binary files differ
diff --git a/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.lef b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.lef
new file mode 100644
index 0000000..bc1a90d
--- /dev/null
+++ b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.lef
@@ -0,0 +1,352 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+
+UNITS
+ DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+LAYER li1
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.46 ;
+ WIDTH 0.17 ;
+END li1
+
+LAYER mcon
+ TYPE CUT ;
+END mcon
+
+LAYER met1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 0.34 ;
+ WIDTH 0.14 ;
+END met1
+
+LAYER via
+ TYPE CUT ;
+END via
+
+LAYER met2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.46 ;
+ WIDTH 0.14 ;
+END met2
+
+LAYER via2
+ TYPE CUT ;
+END via2
+
+LAYER met3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 0.68 ;
+ WIDTH 0.3 ;
+END met3
+
+LAYER via3
+ TYPE CUT ;
+END via3
+
+LAYER met4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+ PITCH 0.92 ;
+ WIDTH 0.3 ;
+END met4
+
+LAYER via4
+ TYPE CUT ;
+END via4
+
+LAYER met5
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+ PITCH 3.4 ;
+ WIDTH 1.6 ;
+END met5
+
+LAYER nwell
+ TYPE MASTERSLICE ;
+END nwell
+
+LAYER pwell
+ TYPE MASTERSLICE ;
+END pwell
+
+VIA L1M1_PR
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIA L1M1_PR_R
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIA L1M1_PR_M
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIA L1M1_PR_MR
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIA L1M1_PR_C
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIA M1M2_PR
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIA M1M2_PR_Enc
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_Enc
+
+VIA M1M2_PR_R
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIA M1M2_PR_R_Enc
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_R_Enc
+
+VIA M1M2_PR_M
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIA M1M2_PR_M_Enc
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_M_Enc
+
+VIA M1M2_PR_MR
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIA M1M2_PR_MR_Enc
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_MR_Enc
+
+VIA M1M2_PR_C
+ LAYER met1 ;
+ RECT -0.16 -0.16 0.16 0.16 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met2 ;
+ RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIA M2M3_PR
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIA M2M3_PR_R
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIA M2M3_PR_M
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIA M2M3_PR_MR
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIA M2M3_PR_C
+ LAYER met2 ;
+ RECT -0.185 -0.185 0.185 0.185 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIA M3M4_PR
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIA M3M4_PR_R
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIA M3M4_PR_M
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIA M3M4_PR_MR
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIA M3M4_PR_C
+ LAYER met3 ;
+ RECT -0.19 -0.19 0.19 0.19 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIA M4M5_PR
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIA M4M5_PR_R
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIA M4M5_PR_M
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIA M4M5_PR_MR
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIA M4M5_PR_C
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+SITE unit
+ CLASS CORE ;
+ SYMMETRY Y ;
+ SIZE 0.46 BY 2.72 ;
+END unit
+
+SITE unithddbl
+ CLASS CORE ;
+ SIZE 0.46 BY 5.44 ;
+END unithddbl
+
+END LIBRARY
diff --git a/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz
new file mode 100644
index 0000000..e2c6913
--- /dev/null
+++ b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz
Binary files differ
diff --git a/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.pt.v b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.pt.v
new file mode 100644
index 0000000..2939dc4
--- /dev/null
+++ b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.pt.v
@@ -0,0 +1,109568 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_102 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_105 ) ,
+ .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_107 ) ,
+ .X ( copt_net_105 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_107 ) ) ;
+endmodule
+
+
+module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_88 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_110 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_113 ) ,
+ .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1331 ( .A ( copt_net_99 ) ,
+ .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( ropt_net_111 ) ,
+ .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_96 ) ,
+ .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_97 ) ,
+ .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1343 ( .A ( copt_net_98 ) ,
+ .X ( ropt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_112 ) ,
+ .X ( ropt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( copt_net_100 ) ,
+ .X ( ropt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( copt_net_95 ) ,
+ .X ( ropt_net_113 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ ,
+ left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ ,
+ left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ ,
+ left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ ,
+ left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ ,
+ left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ,
+ IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper ,
+ left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in ,
+ prog_clk_0_S_out , prog_clk_0_N_out ) ;
+input [0:0] pReset ;
+input [0:29] chany_bottom_in ;
+input [0:29] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input pReset_S_in ;
+input prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:3] mux_tree_tapbuf_size12_8_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
+ chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_91 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
+ chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_92 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] ,
+ chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_89 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
+ chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_91 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
+ chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_92 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] ,
+ chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_89 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
+ chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_92 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
+ chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size12_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_92 ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] ,
+ chany_bottom_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_90 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] ,
+ chany_bottom_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_90 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] ,
+ chany_bottom_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] ,
+ chany_bottom_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] ,
+ chany_bottom_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] ,
+ chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] ,
+ chany_bottom_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] ,
+ chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] ,
+ chany_bottom_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
+ chany_bottom_out[22] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_92 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( left_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( { ropt_net_108 } ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_193 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_294 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 (
+ .A ( left_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .HI ( optlc_net_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .HI ( optlc_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
+ .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) ,
+ .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+wire copt_net_115 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_115 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_115 ) ,
+ .X ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) ,
+ .X ( copt_net_118 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( mem_out[3] ) ,
+ .X ( copt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) ,
+ .X ( copt_net_120 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_129 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_111 ) ,
+ .X ( copt_net_112 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_112 ) ,
+ .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_116 ) ,
+ .X ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) ,
+ .X ( copt_net_122 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) ,
+ .X ( copt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_123 ) ,
+ .X ( ropt_net_128 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1366 ( .A ( ropt_net_130 ) ,
+ .X ( ropt_net_129 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ropt_net_128 ) ,
+ .X ( ropt_net_130 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_82 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_78 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_103 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ ,
+ left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ ,
+ left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ ,
+ left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ ,
+ left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ ,
+ left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in ,
+ Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out ,
+ Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in ,
+ Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in ,
+ prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in ,
+ prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in ,
+ prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in ,
+ clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out ,
+ clk_3_S_out ) ;
+input [0:0] pReset ;
+input [0:29] chany_bottom_in ;
+input [0:29] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input Test_en_S_in ;
+input Test_en_E_in ;
+input Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input pReset_S_in ;
+output pReset_N_out ;
+input Reset_S_in ;
+input Reset_E_in ;
+input Reset_W_in ;
+output Reset_N_out ;
+output Reset_W_out ;
+output Reset_E_out ;
+input prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input prog_clk_2_N_in ;
+input prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input prog_clk_3_S_in ;
+input prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input clk_2_N_in ;
+input clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input clk_3_S_in ;
+input clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+
+assign Test_en_E_in = Test_en_S_in ;
+assign Test_en_E_in = Test_en_W_in ;
+assign Reset_E_in = Reset_S_in ;
+assign Reset_E_in = Reset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
+
+cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_108 ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
+ chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
+ chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_105 ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_108 ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
+ chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
+ chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ;
+cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
+ chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
+ chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_107 ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] ,
+ chany_bottom_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] ,
+ chany_bottom_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] ,
+ chany_bottom_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_108 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
+ chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] ,
+ chany_bottom_out[22] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_105 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] ,
+ chany_bottom_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
+ .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
+ chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
+ chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] ,
+ chany_bottom_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_105 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 (
+ .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
+ chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] ,
+ chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] ,
+ chany_bottom_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
+ chany_bottom_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_106 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) ,
+ .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) ,
+ .X ( Reset_E_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_1109 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
+ .X ( ctsbuf_net_2110 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) ,
+ .X ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) ,
+ .X ( ZBUF_4_f_0 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) ,
+ .X ( prog_clk_3_S_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) ,
+ .X ( clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) ,
+ .X ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) ,
+ .X ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) ,
+ .X ( clk_3_S_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_89 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_93 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_96 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) ,
+ .Y ( BUF_net_98 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) ,
+ .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
+ .HI ( optlc_net_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) ,
+ .HI ( optlc_net_107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) ,
+ .HI ( optlc_net_108 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) ,
+ .X ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) ,
+ .X ( prog_clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) ,
+ .X ( prog_clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_74 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) ,
+ .X ( copt_net_73 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) ,
+ .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) ,
+ .X ( copt_net_75 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) ,
+ .X ( copt_net_76 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) ,
+ .X ( copt_net_77 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) ,
+ .X ( copt_net_78 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) ,
+ .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_67 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) ,
+ .X ( copt_net_68 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) ,
+ .X ( copt_net_69 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) ,
+ .X ( copt_net_70 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) ,
+ .X ( copt_net_71 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) ,
+ .X ( copt_net_72 ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
+ chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail ,
+ IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper ,
+ right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_bottom_in ;
+input [0:29] chany_top_in ;
+input [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input pReset_N_in ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_120 ;
+wire ropt_net_118 ;
+wire ropt_net_136 ;
+wire ropt_net_117 ;
+wire ropt_net_121 ;
+wire ropt_net_125 ;
+wire ropt_net_124 ;
+wire ropt_net_122 ;
+wire ropt_net_115 ;
+wire ropt_net_116 ;
+wire ropt_net_126 ;
+wire ropt_net_119 ;
+wire ropt_net_123 ;
+wire ropt_net_114 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 (
+ .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
+ chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
+ chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
+ chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ;
+cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( right_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) ,
+ .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) ,
+ .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) ,
+ .X ( ropt_net_120 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) ,
+ .X ( ropt_net_118 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) ,
+ .X ( ropt_net_136 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) ,
+ .X ( ropt_net_117 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) ,
+ .X ( ropt_net_121 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) ,
+ .X ( ropt_net_125 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) ,
+ .X ( ropt_net_124 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) ,
+ .X ( ropt_net_122 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) ,
+ .X ( ropt_net_115 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) ,
+ .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) ,
+ .X ( ropt_net_116 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) ,
+ .X ( ropt_net_126 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) ,
+ .X ( ropt_net_119 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) ,
+ .X ( ropt_net_123 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) ,
+ .X ( ropt_net_114 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 (
+ .A ( right_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( optlc_net_66 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) ,
+ .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) ,
+ .X ( chany_top_out[8] ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_108 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_108 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_108 ) ,
+ .X ( mem_out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( BUF_net_83 ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_100 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_91 ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_97 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_89 ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_95 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__2__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_85 ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ ,
+ bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
+ bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
+ bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
+ ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper ,
+ bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT ,
+ SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out ,
+ pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+input [0:0] pReset ;
+input [0:29] chanx_left_in ;
+input [0:29] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:29] chanx_left_out ;
+output [0:29] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_W_out ;
+output pReset_S_out ;
+output pReset_E_out ;
+input prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:3] mux_tree_tapbuf_size12_8_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ;
+
+assign pReset_W_in = pReset_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
+ chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
+ chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size12_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] ,
+ chanx_left_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] ,
+ chanx_left_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] ,
+ chanx_left_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] ,
+ chanx_left_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] ,
+ chanx_left_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_102 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] ,
+ chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] ,
+ chanx_left_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] ,
+ chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] ,
+ chanx_left_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_101 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
+ chanx_left_out[22] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( bottom_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_1107 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 (
+ .A ( bottom_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .HI ( optlc_net_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .HI ( optlc_net_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
+ .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) ,
+ .HI ( optlc_net_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) ,
+ .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) ,
+ .HI ( optlc_net_106 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) ,
+ .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_101 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( copt_net_95 ) ,
+ .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( copt_net_96 ) ,
+ .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_97 ) ,
+ .X ( copt_net_98 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_98 ) ,
+ .X ( copt_net_101 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_84 ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
+ bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
+ bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
+ bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
+ ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP ,
+ REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH ,
+ COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out ,
+ pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out ,
+ prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out ,
+ prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out ,
+ prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out ,
+ clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in ,
+ clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in ,
+ clk_3_E_out , clk_3_W_out ) ;
+input [0:0] pReset ;
+input [0:29] chanx_left_in ;
+input [0:29] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:29] chanx_left_out ;
+output [0:29] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input REGIN_FEEDTHROUGH ;
+output REGOUT_FEEDTHROUGH ;
+input CIN_FEEDTHROUGH ;
+output COUT_FEEDTHROUGH ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_W_out ;
+output pReset_S_out ;
+output pReset_E_out ;
+input prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input prog_clk_1_W_in ;
+input prog_clk_1_E_in ;
+output prog_clk_1_N_out ;
+output prog_clk_1_S_out ;
+input prog_clk_2_E_in ;
+input prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_E_out ;
+input prog_clk_3_W_in ;
+input prog_clk_3_E_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+input clk_1_W_in ;
+input clk_1_E_in ;
+output clk_1_N_out ;
+output clk_1_S_out ;
+input clk_2_E_in ;
+input clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_E_out ;
+input clk_3_W_in ;
+input clk_3_E_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+
+assign pReset_W_in = pReset_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign clk_1_E_in = clk_1_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
+
+cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_92 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_91 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
+ chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_89 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_92 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_89 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
+ chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_89 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_92 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_91 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] ,
+ chanx_left_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_89 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] ,
+ chanx_left_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_92 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] ,
+ chanx_left_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_91 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] ,
+ chanx_left_out[22] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_91 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] ,
+ chanx_left_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_92 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] ,
+ chanx_left_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_90 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] ,
+ chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] ,
+ chanx_left_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_90 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_92 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( { copt_net_100 } ) ,
+ .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
+ .X ( ctsbuf_net_193 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) ,
+ .X ( prog_clk_1_N_out ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) ,
+ .X ( prog_clk_1_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) ,
+ .X ( prog_clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) ,
+ .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) ,
+ .X ( prog_clk_3_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) ,
+ .X ( clk_1_N_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) ,
+ .X ( clk_1_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) ,
+ .X ( clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) ,
+ .X ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) ,
+ .X ( clk_3_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[22] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) ,
+ .X ( REGOUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) ,
+ .X ( COUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .HI ( optlc_net_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
+ .HI ( optlc_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) ,
+ .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) ,
+ .HI ( optlc_net_92 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) ,
+ .X ( clk_2_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) ,
+ .X ( prog_clk_2_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) ,
+ .X ( clk_3_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) ,
+ .X ( prog_clk_3_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) ,
+ .X ( copt_net_102 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_113 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_110 ) ,
+ .X ( copt_net_109 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_111 ) ,
+ .X ( copt_net_110 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_113 ) ,
+ .X ( copt_net_111 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_109 ) ,
+ .X ( mem_out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_898_f_0 ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+input ZBUF_898_f_0 ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_898_f_0 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_898_f_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_898_f_0 ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ,
+ .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail , ZBUF_898_f_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_898_f_0 ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ,
+ .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_208_0 ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+input ZBUF_208_0 ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_208_0 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( ZBUF_208_0 ) , .Z ( SOC_OUT ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_208_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_208_0 ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ,
+ .ZBUF_208_0 ( ZBUF_208_0 ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail , ZBUF_208_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_208_0 ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ,
+ .ZBUF_208_0 ( ZBUF_208_0 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_96 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( net_net_96 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_217_0 ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+input ZBUF_217_0 ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_217_0 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( ZBUF_217_0 ) , .Z ( SOC_OUT ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_217_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_217_0 ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ,
+ .ZBUF_217_0 ( ZBUF_217_0 ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail , ZBUF_217_0 ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input ZBUF_217_0 ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ,
+ .ZBUF_217_0 ( ZBUF_217_0 ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_95 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_91 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_90 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset ,
+ prog_clk , ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
+ FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input FPGA_OUT ;
+input FPGA_DIR ;
+input IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
+ .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
+ .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
+ .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset ,
+ prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
+ iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] iopad_outpad ;
+input [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ (
+ .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
+ .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
+ ccff_tail ) ;
+input [0:0] IO_ISOL_N ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] io_outpad ;
+input [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
+ .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
+ .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_114 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_116 ) ,
+ .X ( copt_net_115 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_114 ) ,
+ .X ( copt_net_116 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( copt_net_115 ) ,
+ .X ( copt_net_117 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 copt_h_inst_1359 ( .A ( ropt_net_124 ) ,
+ .X ( copt_net_118 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_117 ) ,
+ .X ( copt_net_119 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_118 ) ,
+ .X ( ropt_net_123 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_119 ) ,
+ .X ( ropt_net_124 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
+ chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
+ bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ ,
+ bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ ,
+ bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ ,
+ top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ ,
+ top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ ,
+ top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ ,
+ top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ ,
+ top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower ,
+ top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower ,
+ top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower ,
+ top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower ,
+ top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower ,
+ top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower ,
+ top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower ,
+ top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower ,
+ top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower ,
+ SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in ,
+ pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in ,
+ prog_clk_0_W_out ) ;
+input [0:0] pReset ;
+input [0:29] chanx_left_in ;
+input [0:29] chanx_right_in ;
+input [0:0] ccff_head ;
+output [0:29] chanx_left_out ;
+output [0:29] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_16_ ;
+output [0:0] ccff_tail ;
+input [0:0] IO_ISOL_N ;
+input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] top_width_0_height_0__pin_0_ ;
+input [0:0] top_width_0_height_0__pin_2_ ;
+input [0:0] top_width_0_height_0__pin_4_ ;
+input [0:0] top_width_0_height_0__pin_6_ ;
+input [0:0] top_width_0_height_0__pin_8_ ;
+input [0:0] top_width_0_height_0__pin_10_ ;
+input [0:0] top_width_0_height_0__pin_12_ ;
+input [0:0] top_width_0_height_0__pin_14_ ;
+input [0:0] top_width_0_height_0__pin_16_ ;
+output [0:0] top_width_0_height_0__pin_1_upper ;
+output [0:0] top_width_0_height_0__pin_1_lower ;
+output [0:0] top_width_0_height_0__pin_3_upper ;
+output [0:0] top_width_0_height_0__pin_3_lower ;
+output [0:0] top_width_0_height_0__pin_5_upper ;
+output [0:0] top_width_0_height_0__pin_5_lower ;
+output [0:0] top_width_0_height_0__pin_7_upper ;
+output [0:0] top_width_0_height_0__pin_7_lower ;
+output [0:0] top_width_0_height_0__pin_9_upper ;
+output [0:0] top_width_0_height_0__pin_9_lower ;
+output [0:0] top_width_0_height_0__pin_11_upper ;
+output [0:0] top_width_0_height_0__pin_11_lower ;
+output [0:0] top_width_0_height_0__pin_13_upper ;
+output [0:0] top_width_0_height_0__pin_13_lower ;
+output [0:0] top_width_0_height_0__pin_15_upper ;
+output [0:0] top_width_0_height_0__pin_15_lower ;
+output [0:0] top_width_0_height_0__pin_17_upper ;
+output [0:0] top_width_0_height_0__pin_17_lower ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_W_out ;
+output pReset_E_out ;
+input prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:3] mux_tree_tapbuf_size12_8_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+
+assign pReset_W_in = pReset_E_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
+ chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
+ chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
+ chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
+ chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_105 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
+ chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
+ chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 (
+ .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
+ chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
+ chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
+ chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_104 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 (
+ .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
+ chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
+ chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
+ chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_104 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 (
+ .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
+ chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
+ chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
+ chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
+ .sram ( mux_tree_tapbuf_size12_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( { ccff_tail_mid } ) ,
+ .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ;
+cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .io_outpad ( top_width_0_height_0__pin_0_ ) ,
+ .ccff_head ( { ccff_tail_mid } ) ,
+ .io_inpad ( top_width_0_height_0__pin_1_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) ,
+ .io_outpad ( top_width_0_height_0__pin_2_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_3_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ,
+ .io_outpad ( top_width_0_height_0__pin_4_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_5_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) ,
+ .io_outpad ( top_width_0_height_0__pin_6_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_7_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ,
+ .io_outpad ( top_width_0_height_0__pin_8_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_9_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) ,
+ .io_outpad ( top_width_0_height_0__pin_10_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_11_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ,
+ .ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ;
+cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) ,
+ .io_outpad ( top_width_0_height_0__pin_12_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_13_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) ,
+ .io_outpad ( top_width_0_height_0__pin_14_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_15_lower ) ,
+ .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ,
+ .ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ;
+cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 (
+ .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) ,
+ .io_outpad ( top_width_0_height_0__pin_16_ ) ,
+ .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) ,
+ .io_inpad ( top_width_0_height_0__pin_17_lower ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
+ .X ( ctsbuf_net_1106 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
+ .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
+ .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
+ .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
+ .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) ,
+ .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) ,
+ .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) ,
+ .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) ,
+ .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[22] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 (
+ .A ( top_width_0_height_0__pin_1_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 (
+ .A ( top_width_0_height_0__pin_3_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_81__80 (
+ .A ( top_width_0_height_0__pin_5_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_82__81 (
+ .A ( top_width_0_height_0__pin_7_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_83__82 (
+ .A ( top_width_0_height_0__pin_9_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_84__83 (
+ .A ( top_width_0_height_0__pin_11_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_85__84 (
+ .A ( top_width_0_height_0__pin_13_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_86__85 (
+ .A ( top_width_0_height_0__pin_15_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_87__86 (
+ .A ( top_width_0_height_0__pin_17_lower[0] ) ,
+ .X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) ,
+ .HI ( optlc_net_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) ,
+ .HI ( optlc_net_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) ,
+ .HI ( optlc_net_105 ) ) ;
+sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ;
+sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_140 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_138 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_136 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( copt_net_165 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_165 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_35 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_134 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_35 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_132 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_130 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_128 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_126 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_124 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_122 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_120 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_118 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_116 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_114 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_148 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_109 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_105 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_103 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_99 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_81 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_195 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_156 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_156 ) ,
+ .X ( copt_net_157 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_157 ) ,
+ .X ( copt_net_158 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_158 ) ,
+ .X ( copt_net_159 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_198 ) ,
+ .X ( copt_net_160 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_160 ) ,
+ .X ( copt_net_161 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_161 ) ,
+ .X ( ropt_net_195 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_159 ) ,
+ .X ( ropt_net_196 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_196 ) ,
+ .X ( ropt_net_197 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_199 ) ,
+ .X ( ropt_net_198 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( ropt_net_197 ) ,
+ .X ( ropt_net_199 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_74 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_2__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ ,
+ bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
+ bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
+ bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ ,
+ bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in ,
+ left_top_grid_pin_1_ , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
+ left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out ,
+ ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_right_grid_pin_1_ ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:0] bottom_left_grid_pin_50_ ;
+input [0:0] bottom_left_grid_pin_51_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_top_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] left_bottom_grid_pin_42_ ;
+input [0:0] left_bottom_grid_pin_43_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_bottom_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_BOT ;
+output SC_OUT_BOT ;
+input pReset_W_in ;
+input prog_clk_0_S_in ;
+
+wire ropt_net_177 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_24_sram ;
+wire [0:1] mux_tree_tapbuf_size2_25_sram ;
+wire [0:1] mux_tree_tapbuf_size2_26_sram ;
+wire [0:1] mux_tree_tapbuf_size2_27_sram ;
+wire [0:1] mux_tree_tapbuf_size2_28_sram ;
+wire [0:1] mux_tree_tapbuf_size2_29_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_30_sram ;
+wire [0:1] mux_tree_tapbuf_size2_31_sram ;
+wire [0:1] mux_tree_tapbuf_size2_32_sram ;
+wire [0:1] mux_tree_tapbuf_size2_33_sram ;
+wire [0:1] mux_tree_tapbuf_size2_34_sram ;
+wire [0:1] mux_tree_tapbuf_size2_35_sram ;
+wire [0:1] mux_tree_tapbuf_size2_36_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_35_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_10_sram ;
+wire [0:2] mux_tree_tapbuf_size4_11_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:2] mux_tree_tapbuf_size4_7_sram ;
+wire [0:2] mux_tree_tapbuf_size4_8_sram ;
+wire [0:2] mux_tree_tapbuf_size4_9_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_154 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 (
+ .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_154 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 (
+ .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_154 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 (
+ .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_155 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 (
+ .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_155 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 (
+ .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
+ SYNOPSYS_UNCONNECTED_21 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 (
+ .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
+ SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 (
+ .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 (
+ .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
+ SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 (
+ .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
+ SYNOPSYS_UNCONNECTED_33 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 (
+ .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
+ SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 (
+ .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 (
+ .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 (
+ .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 (
+ .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 (
+ .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 (
+ .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_154 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 (
+ .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 (
+ .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 (
+ .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 (
+ .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 (
+ .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 (
+ .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) ,
+ .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_155 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 (
+ .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_154 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 (
+ .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) ,
+ .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 (
+ .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) ,
+ .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 (
+ .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_153 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 (
+ .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 (
+ .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_153 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 (
+ .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 (
+ .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 (
+ .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 (
+ .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 (
+ .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chanx_left_out[13] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 (
+ .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 (
+ .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_24_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_153 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 (
+ .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_25_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_153 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 (
+ .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_26_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_153 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 (
+ .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_27_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_left_out[19] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 (
+ .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_28_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+ .out ( chanx_left_out[20] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 (
+ .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_29_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_left_out[21] ) , .p0 ( optlc_net_152 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 (
+ .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_30_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 (
+ .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_31_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chanx_left_out[23] ) , .p0 ( optlc_net_153 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 (
+ .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_32_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
+ .out ( chanx_left_out[24] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 (
+ .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_33_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chanx_left_out[25] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 (
+ .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_34_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
+ .out ( chanx_left_out[27] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 (
+ .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_35_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chanx_left_out[28] ) , .p0 ( optlc_net_155 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 (
+ .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_36_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
+ .out ( chanx_left_out[29] ) , .p0 ( optlc_net_155 ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_15 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_17 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_19 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_23 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_25 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_39 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_41 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_bottom_track_43 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_bottom_track_47 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_bottom_track_49 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_bottom_track_51 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_17 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_19 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_21 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_23 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_25 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_27 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_23 mem_left_track_31 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_24 mem_left_track_33 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_25 mem_left_track_35 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_26 mem_left_track_37 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_27 mem_left_track_39 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_28 mem_left_track_41 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_29 mem_left_track_43 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_30 mem_left_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_31 mem_left_track_47 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_32 mem_left_track_49 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_33 mem_left_track_51 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_34 mem_left_track_55 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem_35 mem_left_track_57 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_36_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_154 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 (
+ .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] ,
+ chanx_left_in[23] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_155 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 (
+ .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 (
+ .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_151 ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[0] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chanx_left_in[16] ) ,
+ .X ( ropt_net_177 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[19] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) ,
+ .HI ( optlc_net_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) ,
+ .HI ( optlc_net_152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) ,
+ .HI ( optlc_net_153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) ,
+ .HI ( optlc_net_154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) ,
+ .HI ( optlc_net_155 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_177 ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_134 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_131 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_129 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_127 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_125 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_123 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_121 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_119 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_117 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_114 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_112 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_109 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_105 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_103 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_99 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_172 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_149 ) ,
+ .X ( copt_net_145 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_148 ) ,
+ .X ( copt_net_146 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_146 ) ,
+ .X ( copt_net_147 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) ,
+ .X ( copt_net_148 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_149 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_174 ) ,
+ .X ( copt_net_150 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) ,
+ .X ( copt_net_158 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1343 ( .A ( copt_net_150 ) ,
+ .X ( ropt_net_172 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_158 ) ,
+ .X ( ropt_net_173 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_173 ) ,
+ .X ( ropt_net_174 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
+ top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
+ top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
+ top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in ,
+ bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ ,
+ bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ ,
+ bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ ,
+ bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ ,
+ bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
+ left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out ,
+ chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out ,
+ prog_clk_0_N_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_left_grid_pin_50_ ;
+input [0:0] top_left_grid_pin_51_ ;
+input [0:0] top_right_grid_pin_1_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_right_grid_pin_1_ ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:0] bottom_left_grid_pin_50_ ;
+input [0:0] bottom_left_grid_pin_51_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] left_bottom_grid_pin_42_ ;
+input [0:0] left_bottom_grid_pin_43_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chany_bottom_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input pReset_W_in ;
+output pReset_N_out ;
+input prog_clk_0_N_in ;
+
+wire ropt_net_162 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:1] mux_tree_tapbuf_size3_6_sram ;
+wire [0:1] mux_tree_tapbuf_size3_7_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:2] mux_tree_tapbuf_size4_7_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:2] mux_tree_tapbuf_size5_5_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:2] mux_tree_tapbuf_size6_4_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:3] mux_tree_tapbuf_size9_2_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] ,
+ chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_1 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[4] , chany_bottom_out[20] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] ,
+ chanx_left_in[23] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_2 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[21] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] ,
+ chanx_left_in[24] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_out[23] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] ,
+ chanx_left_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_bottom_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem_2 mem_bottom_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_2 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] ,
+ chanx_left_in[10] , chanx_left_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_4 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] ,
+ chanx_left_in[9] , chanx_left_in[20] } ) ,
+ .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 ,
+ SYNOPSYS_UNCONNECTED_22 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_2 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] ,
+ chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] ,
+ chanx_left_in[17] , chanx_left_in[28] } ) ,
+ .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 ,
+ SYNOPSYS_UNCONNECTED_25 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_3 mux_top_track_20 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] ,
+ chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] ,
+ chanx_left_in[16] , chanx_left_in[27] } ) ,
+ .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 ,
+ SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_4 mux_top_track_28 (
+ .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] ,
+ chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] ,
+ chanx_left_in[15] , chanx_left_in[26] } ) ,
+ .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_5 mux_bottom_track_13 (
+ .in ( { chany_bottom_out[12] , chany_bottom_out[27] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] ,
+ chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) ,
+ .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 ,
+ SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7 mux_bottom_track_21 (
+ .in ( { chany_bottom_out[13] , chany_bottom_out[28] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 ,
+ SYNOPSYS_UNCONNECTED_37 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_0 mux_top_track_6 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] ,
+ top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] ,
+ top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] ,
+ chanx_left_in[8] , chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 ,
+ SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] ,
+ chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] ,
+ chanx_left_in[18] , chanx_left_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 ,
+ SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 (
+ .in ( { ropt_net_162 , chany_bottom_out[25] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) ,
+ .sram ( mux_tree_tapbuf_size9_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
+ SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_0 mux_top_track_36 (
+ .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] ,
+ chanx_left_in[14] , chanx_left_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 ,
+ SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_1 mux_top_track_44 (
+ .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] ,
+ chanx_left_in[13] , chanx_left_in[24] } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_2 mux_top_track_52 (
+ .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] ,
+ chanx_left_in[12] , chanx_left_in[23] } ) ,
+ .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 ,
+ SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chany_top_out[26] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_3 mux_bottom_track_53 (
+ .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] ,
+ chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) ,
+ .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 ,
+ SYNOPSYS_UNCONNECTED_61 } ) ,
+ .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_4 mux_left_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] ,
+ left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 ,
+ SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_144 ) ) ;
+sb_2__1__mux_tree_tapbuf_size5 mux_left_track_11 (
+ .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] ,
+ left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size5_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_143 ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_7 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[24] ,
+ bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] ,
+ chanx_left_in[26] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 ,
+ SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_29 (
+ .in ( { chany_bottom_out[15] , chany_bottom_out[29] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[8] , chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 ,
+ SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_1 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 ,
+ SYNOPSYS_UNCONNECTED_77 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_2 mux_left_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 ,
+ SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 (
+ .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
+ SYNOPSYS_UNCONNECTED_83 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_143 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 (
+ .in ( { ropt_net_162 , chany_bottom_in[4] , chany_top_out[11] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 ,
+ SYNOPSYS_UNCONNECTED_86 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_143 ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_0 mux_bottom_track_37 (
+ .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] ,
+ chanx_left_in[9] , chanx_left_in[20] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 ,
+ SYNOPSYS_UNCONNECTED_89 } ) ,
+ .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_1 mux_bottom_track_45 (
+ .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] ,
+ chanx_left_in[10] , chanx_left_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 ,
+ SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 (
+ .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] ,
+ left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
+ SYNOPSYS_UNCONNECTED_95 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_3 mux_left_track_15 (
+ .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] ,
+ left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 ,
+ SYNOPSYS_UNCONNECTED_98 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_144 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_4 mux_left_track_17 (
+ .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] ,
+ left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 ,
+ SYNOPSYS_UNCONNECTED_101 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_144 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_5 mux_left_track_19 (
+ .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 ,
+ SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_144 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_6 mux_left_track_21 (
+ .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 ,
+ SYNOPSYS_UNCONNECTED_107 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4 mux_left_track_23 (
+ .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] ,
+ chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 ,
+ SYNOPSYS_UNCONNECTED_110 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_144 ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_3 mem_left_track_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_4 mem_left_track_17 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_5 mem_left_track_19 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem_6 mem_left_track_21 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_25 (
+ .in ( { chany_bottom_out[21] , chany_top_out[21] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_144 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_27 (
+ .in ( { chany_bottom_out[23] , chany_top_out[23] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
+ .out ( chanx_left_out[13] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_29 (
+ .in ( { chany_bottom_out[24] , chany_top_out[24] ,
+ left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_31 (
+ .in ( { chany_bottom_out[25] , chany_top_out[25] ,
+ left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_4 mux_left_track_33 (
+ .in ( { chany_bottom_out[27] , chany_top_out[27] ,
+ left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_5 mux_left_track_35 (
+ .in ( { chany_bottom_out[28] , chany_top_out[28] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_6 mux_left_track_37 (
+ .in ( { chany_bottom_out[29] , chany_top_out[29] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3 mux_left_track_51 (
+ .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
+ .out ( chanx_left_out[25] ) , .p0 ( optlc_net_142 ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_27 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_31 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_4 mem_left_track_33 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_5 mem_left_track_35 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem_6 mem_left_track_37 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_41 (
+ .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chanx_left_out[20] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_45 (
+ .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_47 (
+ .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
+ .out ( chanx_left_out[23] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_49 (
+ .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) ,
+ .out ( chanx_left_out[24] ) , .p0 ( optlc_net_141 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_53 (
+ .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_5 mux_left_track_55 (
+ .in ( { chany_top_in[4] , chanx_left_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) ,
+ .out ( chanx_left_out[27] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2 mux_left_track_57 (
+ .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
+ .out ( chanx_left_out[28] ) , .p0 ( optlc_net_140 ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_47 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_49 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem_5 mem_left_track_55 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_6 pReset_N_FTB01 ( .A ( pReset_W_in ) ,
+ .X ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( chany_top_in[10] ) ,
+ .X ( ropt_net_162 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[25] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( left_bottom_grid_pin_41_[0] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) ,
+ .HI ( optlc_net_140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) ,
+ .HI ( optlc_net_141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) ,
+ .HI ( optlc_net_142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) ,
+ .HI ( optlc_net_143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) ,
+ .HI ( optlc_net_144 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1336 ( .A ( ropt_net_162 ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_181 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_181 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_181 ) ,
+ .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_124 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_159 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_122 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_119 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_116 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_157 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_113 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_155 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_111 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_153 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_108 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_106 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_103 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_99 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_97 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_95 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_93 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_90 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_88 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_86 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_84 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_82 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_78 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_76 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_170 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_172 ) ,
+ .X ( copt_net_171 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_170 ) ,
+ .X ( copt_net_172 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_175 ) ,
+ .X ( copt_net_173 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_173 ) ,
+ .X ( copt_net_174 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_171 ) ,
+ .X ( copt_net_175 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_174 ) ,
+ .X ( ropt_net_197 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_197 ) ,
+ .X ( ropt_net_198 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_198 ) ,
+ .X ( ropt_net_199 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_199 ) ,
+ .X ( ropt_net_200 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1365 ( .A ( ropt_net_200 ) ,
+ .X ( ropt_net_201 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_74 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_164 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_164 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_61 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_161 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
+ top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
+ top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
+ top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in ,
+ left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
+ left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
+ left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
+ left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
+ left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out ,
+ ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_left_grid_pin_50_ ;
+input [0:0] top_left_grid_pin_51_ ;
+input [0:0] top_right_grid_pin_1_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_3_ ;
+input [0:0] left_bottom_grid_pin_5_ ;
+input [0:0] left_bottom_grid_pin_7_ ;
+input [0:0] left_bottom_grid_pin_9_ ;
+input [0:0] left_bottom_grid_pin_11_ ;
+input [0:0] left_bottom_grid_pin_13_ ;
+input [0:0] left_bottom_grid_pin_15_ ;
+input [0:0] left_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input pReset_W_in ;
+output pReset_N_out ;
+input prog_clk_0_N_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_24_sram ;
+wire [0:1] mux_tree_tapbuf_size2_25_sram ;
+wire [0:1] mux_tree_tapbuf_size2_26_sram ;
+wire [0:1] mux_tree_tapbuf_size2_27_sram ;
+wire [0:1] mux_tree_tapbuf_size2_28_sram ;
+wire [0:1] mux_tree_tapbuf_size2_29_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_30_sram ;
+wire [0:1] mux_tree_tapbuf_size2_31_sram ;
+wire [0:1] mux_tree_tapbuf_size2_32_sram ;
+wire [0:1] mux_tree_tapbuf_size2_33_sram ;
+wire [0:1] mux_tree_tapbuf_size2_34_sram ;
+wire [0:1] mux_tree_tapbuf_size2_35_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_10_sram ;
+wire [0:2] mux_tree_tapbuf_size4_11_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:2] mux_tree_tapbuf_size4_7_sram ;
+wire [0:2] mux_tree_tapbuf_size4_8_sram ;
+wire [0:2] mux_tree_tapbuf_size4_9_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_left_in[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_left_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ top_right_grid_pin_1_[0] , chanx_left_in[28] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_left_in[27] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_left_in[26] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ top_right_grid_pin_1_[0] , chanx_left_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 (
+ .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
+ SYNOPSYS_UNCONNECTED_21 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 (
+ .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
+ SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_165 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 (
+ .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 (
+ .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
+ SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_165 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 (
+ .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
+ SYNOPSYS_UNCONNECTED_33 } ) ,
+ .out ( chanx_left_out[4] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 (
+ .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
+ SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] ,
+ chanx_left_in[24] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 (
+ .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] ,
+ chanx_left_in[8] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 (
+ .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 (
+ .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 (
+ .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 (
+ .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chany_top_out[7] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chany_top_out[9] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chany_top_out[11] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 (
+ .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 (
+ .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_top_out[13] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 (
+ .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 (
+ .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 (
+ .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chany_top_out[19] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chany_top_out[20] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) ,
+ .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chany_top_out[21] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chany_top_out[23] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 (
+ .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) ,
+ .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chany_top_out[24] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 (
+ .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) ,
+ .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_top_out[25] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 (
+ .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chanx_left_out[7] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 (
+ .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_left_out[8] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 (
+ .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chanx_left_out[9] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 (
+ .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 (
+ .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
+ .out ( chanx_left_out[11] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 (
+ .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chanx_left_out[12] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 (
+ .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
+ .out ( chanx_left_out[13] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 (
+ .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_left_out[15] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 (
+ .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
+ .out ( chanx_left_out[16] ) , .p0 ( optlc_net_166 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 (
+ .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_24_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_left_out[17] ) , .p0 ( optlc_net_169 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 (
+ .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_25_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 (
+ .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_26_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chanx_left_out[19] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 (
+ .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_27_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
+ .out ( chanx_left_out[20] ) , .p0 ( optlc_net_165 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 (
+ .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_28_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chanx_left_out[21] ) , .p0 ( optlc_net_165 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 (
+ .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_29_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
+ .out ( chanx_left_out[23] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 (
+ .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_30_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chanx_left_out[24] ) , .p0 ( optlc_net_167 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 (
+ .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_31_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
+ .out ( chanx_left_out[25] ) , .p0 ( optlc_net_165 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 (
+ .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_32_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 (
+ .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_33_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
+ .out ( chanx_left_out[27] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 (
+ .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_34_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chanx_left_out[28] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 (
+ .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_35_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
+ .out ( chanx_left_out[29] ) , .p0 ( optlc_net_168 ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ;
+sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) ,
+ .HI ( optlc_net_165 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) ,
+ .HI ( optlc_net_166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) ,
+ .HI ( optlc_net_167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) ,
+ .HI ( optlc_net_168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) ,
+ .HI ( optlc_net_169 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_134 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_132 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_129 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_124 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_122 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_120 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_118 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_117 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( copt_net_158 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( mem_out[2] ) ,
+ .X ( copt_net_153 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_153 ) ,
+ .X ( copt_net_154 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_154 ) ,
+ .X ( copt_net_155 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_155 ) ,
+ .X ( copt_net_156 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_156 ) ,
+ .X ( copt_net_157 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_157 ) ,
+ .X ( copt_net_158 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_115 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_113 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_145 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_111 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_108 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_143 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_105 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_141 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_187 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1415 ( .A ( ccff_head[0] ) ,
+ .X ( ropt_net_182 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( ropt_net_182 ) ,
+ .X ( ropt_net_183 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_185 ) ,
+ .X ( ropt_net_184 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_183 ) ,
+ .X ( ropt_net_185 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( ropt_net_184 ) ,
+ .X ( ropt_net_186 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_186 ) ,
+ .X ( ropt_net_187 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_99 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_97 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_139 ) ) ;
+endmodule
+
+
+module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ ,
+ right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
+ right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
+ bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
+ bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
+ bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ ,
+ bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in ,
+ left_top_grid_pin_1_ , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
+ left_bottom_grid_pin_43_ , ccff_head , chanx_right_out ,
+ chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT ,
+ pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out ,
+ prog_clk_0_S_in ) ;
+input [0:0] pReset ;
+input [0:29] chanx_right_in ;
+input [0:0] right_top_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:0] right_bottom_grid_pin_42_ ;
+input [0:0] right_bottom_grid_pin_43_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:0] bottom_left_grid_pin_50_ ;
+input [0:0] bottom_left_grid_pin_51_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_top_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] left_bottom_grid_pin_42_ ;
+input [0:0] left_bottom_grid_pin_43_ ;
+input [0:0] ccff_head ;
+output [0:29] chanx_right_out ;
+output [0:29] chany_bottom_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_BOT ;
+output SC_OUT_BOT ;
+input pReset_S_in ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_W_out ;
+output pReset_E_out ;
+input prog_clk_0_S_in ;
+
+wire ropt_net_166 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:2] mux_tree_tapbuf_size4_7_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:2] mux_tree_tapbuf_size7_7_sram ;
+wire [0:2] mux_tree_tapbuf_size7_8_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[9] ,
+ chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_bottom_in[8] ,
+ chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] ,
+ chanx_right_out[12] , chanx_right_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_148 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] ,
+ chanx_right_out[13] , chanx_right_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_148 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 (
+ .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] ,
+ chanx_right_out[15] , chanx_right_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 (
+ .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] ,
+ chany_bottom_in[21] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 (
+ .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] ,
+ chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
+ SYNOPSYS_UNCONNECTED_21 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 (
+ .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] ,
+ chany_bottom_in[16] , chany_bottom_in[27] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
+ SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 (
+ .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] ,
+ chany_bottom_in[17] , chany_bottom_in[28] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 (
+ .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_bottom_in[7] ,
+ chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] ,
+ chanx_right_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
+ SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 (
+ .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] ,
+ chany_bottom_in[11] , chany_bottom_in[22] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 ,
+ SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 (
+ .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] ,
+ chany_bottom_in[12] , chany_bottom_in[23] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 ,
+ SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] ,
+ right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_bottom_in[6] ,
+ chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] ,
+ chanx_right_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
+ SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_148 ) ) ;
+sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 (
+ .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] ,
+ chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] ,
+ left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 ,
+ SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] ,
+ chanx_right_out[11] , chanx_right_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 ,
+ SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_148 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 (
+ .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] ,
+ chany_bottom_in[14] , chany_bottom_in[25] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 ,
+ SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] ,
+ chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 ,
+ SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_148 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] ,
+ chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 ,
+ SYNOPSYS_UNCONNECTED_61 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 (
+ .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) ,
+ .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 ,
+ SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 (
+ .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_49_[0] , chanx_right_out[12] ,
+ chanx_left_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 (
+ .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] ,
+ chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 ,
+ SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] ,
+ chany_bottom_in[21] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 ,
+ SYNOPSYS_UNCONNECTED_73 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 (
+ .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] ,
+ chanx_right_out[13] , chanx_left_in[17] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 ,
+ SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 (
+ .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] ,
+ chanx_right_out[15] , chanx_left_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
+ SYNOPSYS_UNCONNECTED_79 } ) ,
+ .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 (
+ .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] ,
+ chanx_right_out[16] , chanx_left_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 ,
+ SYNOPSYS_UNCONNECTED_82 } ) ,
+ .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 (
+ .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 ,
+ chanx_left_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 ,
+ SYNOPSYS_UNCONNECTED_85 } ) ,
+ .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 (
+ .in ( { chanx_left_out[29] , chanx_right_in[29] ,
+ bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 ,
+ SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 (
+ .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
+ SYNOPSYS_UNCONNECTED_91 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 (
+ .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 ,
+ SYNOPSYS_UNCONNECTED_94 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
+ .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[1] , chanx_right_out[4] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 ,
+ SYNOPSYS_UNCONNECTED_97 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 (
+ .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] ,
+ bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[2] , chanx_right_out[7] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 ,
+ SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 (
+ .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] ,
+ bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[5] , chanx_right_out[9] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
+ SYNOPSYS_UNCONNECTED_103 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 (
+ .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] ,
+ bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[9] , chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 ,
+ SYNOPSYS_UNCONNECTED_106 } ) ,
+ .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_146 ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 (
+ .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] ,
+ chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 (
+ .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] ,
+ chanx_right_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
+ .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 (
+ .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] ,
+ chanx_right_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 (
+ .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] ,
+ chanx_right_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
+ .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 (
+ .in ( { chanx_left_out[24] , chanx_right_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 (
+ .in ( { chanx_left_out[25] , chanx_right_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
+ .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 (
+ .in ( { chanx_left_out[27] , chanx_right_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 (
+ .in ( { chanx_left_out[28] , chanx_right_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
+ .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 (
+ .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 (
+ .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
+ .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 (
+ .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 (
+ .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_147 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 (
+ .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
+ .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 (
+ .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) ,
+ .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 (
+ .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
+ .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( net_net_137 ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) ,
+ .X ( ropt_net_166 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) ,
+ .HI ( optlc_net_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) ,
+ .HI ( optlc_net_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) ,
+ .HI ( optlc_net_148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) ,
+ .HI ( optlc_net_149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) ,
+ .HI ( optlc_net_150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) ,
+ .HI ( optlc_net_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) ,
+ .HI ( optlc_net_152 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) ,
+ .X ( chanx_right_out[17] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_150 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_149 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_147 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_145 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size9_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_155 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_143 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_140 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_138 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_136 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:11] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ,
+ .Y ( BUF_net_134 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_132 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_130 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_128 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_127 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_153 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_176 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) ,
+ .X ( ropt_net_178 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) ,
+ .X ( copt_net_172 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ropt_net_181 ) ,
+ .X ( copt_net_173 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_174 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( ropt_net_183 ) ,
+ .X ( copt_net_175 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) ,
+ .X ( copt_net_176 ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_h_inst_1371 ( .A ( ropt_net_180 ) ,
+ .X ( ropt_net_183 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_173 ) ,
+ .X ( ropt_net_179 ) ) ;
+sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( ropt_net_179 ) ,
+ .X ( ropt_net_180 ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( copt_net_172 ) ,
+ .X ( ropt_net_181 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_124 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .Y ( BUF_net_123 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
+ .Y ( BUF_net_121 ) ) ;
+endmodule
+
+
+module sb_1__1__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:10] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
+endmodule
+
+
+module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
+ top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
+ top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
+ top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ ,
+ right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ ,
+ right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ ,
+ right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ ,
+ right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ ,
+ bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ ,
+ bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ ,
+ bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ ,
+ bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ ,
+ left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
+ left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
+ left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
+ left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out ,
+ chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in ,
+ Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out ,
+ pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in ,
+ prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out ,
+ prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in ,
+ prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out ,
+ prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in ,
+ prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out ,
+ prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out ,
+ clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out ,
+ clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in ,
+ clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out ,
+ clk_3_S_out ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_left_grid_pin_50_ ;
+input [0:0] top_left_grid_pin_51_ ;
+input [0:29] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:0] right_bottom_grid_pin_42_ ;
+input [0:0] right_bottom_grid_pin_43_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_44_ ;
+input [0:0] bottom_left_grid_pin_45_ ;
+input [0:0] bottom_left_grid_pin_46_ ;
+input [0:0] bottom_left_grid_pin_47_ ;
+input [0:0] bottom_left_grid_pin_48_ ;
+input [0:0] bottom_left_grid_pin_49_ ;
+input [0:0] bottom_left_grid_pin_50_ ;
+input [0:0] bottom_left_grid_pin_51_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_36_ ;
+input [0:0] left_bottom_grid_pin_37_ ;
+input [0:0] left_bottom_grid_pin_38_ ;
+input [0:0] left_bottom_grid_pin_39_ ;
+input [0:0] left_bottom_grid_pin_40_ ;
+input [0:0] left_bottom_grid_pin_41_ ;
+input [0:0] left_bottom_grid_pin_42_ ;
+input [0:0] left_bottom_grid_pin_43_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_right_out ;
+output [0:29] chany_bottom_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input Test_en_S_in ;
+output Test_en_N_out ;
+input pReset_S_in ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_N_out ;
+output pReset_W_out ;
+output pReset_E_out ;
+input Reset_S_in ;
+output Reset_N_out ;
+input prog_clk_0_N_in ;
+input prog_clk_1_N_in ;
+input prog_clk_1_S_in ;
+output prog_clk_1_E_out ;
+output prog_clk_1_W_out ;
+input prog_clk_2_N_in ;
+input prog_clk_2_E_in ;
+input prog_clk_2_S_in ;
+input prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+output prog_clk_2_E_out ;
+input prog_clk_3_W_in ;
+input prog_clk_3_E_in ;
+input prog_clk_3_S_in ;
+input prog_clk_3_N_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input clk_1_N_in ;
+input clk_1_S_in ;
+output clk_1_E_out ;
+output clk_1_W_out ;
+input clk_2_N_in ;
+input clk_2_E_in ;
+input clk_2_S_in ;
+input clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+output clk_2_E_out ;
+input clk_3_W_in ;
+input clk_3_E_in ;
+input clk_3_S_in ;
+input clk_3_N_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_10_sram ;
+wire [0:3] mux_tree_tapbuf_size10_11_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:3] mux_tree_tapbuf_size10_9_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size11_0_sram ;
+wire [0:3] mux_tree_tapbuf_size11_1_sram ;
+wire [0:3] mux_tree_tapbuf_size11_2_sram ;
+wire [0:3] mux_tree_tapbuf_size11_3_sram ;
+wire [0:3] mux_tree_tapbuf_size11_4_sram ;
+wire [0:3] mux_tree_tapbuf_size11_5_sram ;
+wire [0:3] mux_tree_tapbuf_size11_6_sram ;
+wire [0:3] mux_tree_tapbuf_size11_7_sram ;
+wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size12_0_sram ;
+wire [0:3] mux_tree_tapbuf_size12_1_sram ;
+wire [0:3] mux_tree_tapbuf_size12_2_sram ;
+wire [0:3] mux_tree_tapbuf_size12_3_sram ;
+wire [0:3] mux_tree_tapbuf_size12_4_sram ;
+wire [0:3] mux_tree_tapbuf_size12_5_sram ;
+wire [0:3] mux_tree_tapbuf_size12_6_sram ;
+wire [0:3] mux_tree_tapbuf_size12_7_sram ;
+wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_10_sram ;
+wire [0:2] mux_tree_tapbuf_size6_11_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:2] mux_tree_tapbuf_size6_4_sram ;
+wire [0:2] mux_tree_tapbuf_size6_5_sram ;
+wire [0:2] mux_tree_tapbuf_size6_6_sram ;
+wire [0:2] mux_tree_tapbuf_size6_7_sram ;
+wire [0:2] mux_tree_tapbuf_size6_8_sram ;
+wire [0:2] mux_tree_tapbuf_size6_9_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:3] mux_tree_tapbuf_size9_2_sram ;
+wire [0:3] mux_tree_tapbuf_size9_3_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail ;
+
+assign prog_clk_1_E_out = prog_clk_1_S_in ;
+assign prog_clk_1_W_out = prog_clk_1_S_in ;
+assign prog_clk_2_W_out = prog_clk_2_E_in ;
+assign prog_clk_2_S_out = prog_clk_2_E_in ;
+assign prog_clk_2_N_out = prog_clk_2_E_in ;
+assign prog_clk_2_E_out = prog_clk_2_E_in ;
+assign prog_clk_3_E_out = prog_clk_3_E_in ;
+assign prog_clk_3_W_out = prog_clk_3_E_in ;
+assign prog_clk_3_N_out = prog_clk_3_E_in ;
+assign prog_clk_3_S_out = prog_clk_3_E_in ;
+assign clk_1_E_out = clk_1_S_in ;
+assign clk_1_W_out = clk_1_S_in ;
+assign clk_2_W_out = clk_2_E_in ;
+assign clk_2_S_out = clk_2_E_in ;
+assign clk_2_N_out = clk_2_E_in ;
+assign clk_2_E_out = clk_2_E_in ;
+assign clk_3_E_out = clk_3_E_in ;
+assign clk_3_W_out = clk_3_E_in ;
+assign clk_3_N_out = clk_3_E_in ;
+assign clk_3_S_out = clk_3_E_in ;
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_S_in = prog_clk_1_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_S_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_S_in ;
+assign prog_clk_3_E_in = prog_clk_3_N_in ;
+assign clk_1_S_in = clk_1_N_in ;
+assign clk_2_E_in = clk_2_N_in ;
+assign clk_2_E_in = clk_2_S_in ;
+assign clk_2_E_in = clk_2_W_in ;
+assign clk_3_E_in = clk_3_W_in ;
+assign clk_3_E_in = clk_3_S_in ;
+assign clk_3_E_in = clk_3_N_in ;
+
+sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] ,
+ chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] ,
+ chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size11_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_161 ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_1 mux_top_track_2 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] ,
+ chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] ,
+ chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size11_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_2 mux_right_track_0 (
+ .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] ,
+ chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size11_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_161 ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_3 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] ,
+ chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size11_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_158 ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_4 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] ,
+ chanx_left_out[20] , chanx_right_in[25] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] ,
+ chanx_right_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size11_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
+ SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_158 ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_5 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] ,
+ chanx_left_out[21] , chanx_right_in[21] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] ,
+ bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] ,
+ chanx_right_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size11_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
+ SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_6 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] ,
+ chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] ,
+ chany_top_out[20] , chany_bottom_in[29] ,
+ left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size11_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_159 ) ) ;
+sb_1__1__mux_tree_tapbuf_size11 mux_left_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] ,
+ chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] ,
+ chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size11_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
+ SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_mem_2 mem_right_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size11_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_mem_3 mem_right_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size11_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_mem_4 mem_bottom_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size11_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_mem_5 mem_bottom_track_3 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size11_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_mem_6 mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size11_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size11_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_4 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] ,
+ chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] ,
+ chanx_right_out[23] , chanx_left_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
+ SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] ,
+ chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] ,
+ chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] ,
+ chanx_left_in[13] , chanx_right_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_20 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] ,
+ chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] ,
+ chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] ,
+ chanx_right_out[13] , chanx_right_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
+ SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] ,
+ chanx_right_out[8] , chanx_right_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
+ SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_160 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_12 (
+ .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] ,
+ chanx_right_out[12] , chanx_right_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_158 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_20 (
+ .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] ,
+ chanx_right_out[13] , chanx_right_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_158 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] ,
+ chanx_right_in[17] , chanx_left_out[23] ,
+ bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] ,
+ chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
+ SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_160 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_13 (
+ .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] ,
+ chanx_left_out[12] , chanx_left_out[27] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_21 (
+ .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] ,
+ chanx_left_out[13] , chanx_left_out[28] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] ,
+ chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] ,
+ chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size10_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
+ SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 (
+ .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] ,
+ chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] ,
+ chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size10_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10 mux_left_track_21 (
+ .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] ,
+ chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] ,
+ chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size10_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
+ SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_159 ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_12 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_20 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_5 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_6 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] ,
+ top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] ,
+ chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] ,
+ chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] ,
+ chanx_left_in[21] , chanx_right_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
+ SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_10 (
+ .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] ,
+ chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] ,
+ chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] ,
+ chanx_left_in[17] , chanx_right_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
+ SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_6 (
+ .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] ,
+ chanx_right_out[9] , chanx_right_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
+ SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_158 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_10 (
+ .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] ,
+ chanx_right_out[11] , chanx_right_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
+ SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_158 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_7 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] ,
+ chanx_right_in[13] , chanx_left_out[24] ,
+ bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] ,
+ bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] ,
+ chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size12_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 ,
+ SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_160 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_11 (
+ .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] ,
+ chanx_left_out[11] , chanx_left_out[25] ,
+ bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
+ bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] ,
+ chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size12_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
+ SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 (
+ .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] ,
+ chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] ,
+ chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] ,
+ left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] ,
+ left_bottom_grid_pin_42_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size12_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 ,
+ SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( { ropt_net_182 } ) ,
+ .p0 ( optlc_net_159 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 (
+ .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] ,
+ chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] ,
+ chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] ,
+ left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] ,
+ left_bottom_grid_pin_43_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size12_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 ,
+ SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_10 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size9_0 mux_top_track_28 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] ,
+ chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] ,
+ chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] ,
+ chanx_right_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 ,
+ SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_157 ) ) ;
+sb_1__1__mux_tree_tapbuf_size9_1 mux_right_track_28 (
+ .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] ,
+ right_bottom_grid_pin_38_[0] , chany_bottom_in[2] ,
+ chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] ,
+ chanx_right_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 ,
+ SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_161 ) ) ;
+sb_1__1__mux_tree_tapbuf_size9_2 mux_bottom_track_29 (
+ .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] ,
+ chanx_left_out[15] , chanx_left_out[29] ,
+ bottom_left_grid_pin_46_[0] , chanx_right_out[15] ,
+ chanx_left_in[21] , chanx_right_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size9_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 ,
+ SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_157 ) ) ;
+sb_1__1__mux_tree_tapbuf_size9 mux_left_track_29 (
+ .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] ,
+ chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] ,
+ chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size9_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 ,
+ SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_160 ) ) ;
+sb_1__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size9_mem_1 mem_right_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size9_mem_2 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_0 mux_top_track_36 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] ,
+ chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] ,
+ chanx_right_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 ,
+ SYNOPSYS_UNCONNECTED_131 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_157 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_1 mux_top_track_44 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] ,
+ chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 ,
+ SYNOPSYS_UNCONNECTED_134 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_157 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_2 mux_top_track_52 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] ,
+ chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] ,
+ chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 ,
+ SYNOPSYS_UNCONNECTED_137 } ) ,
+ .out ( chany_top_out[26] ) , .p0 ( optlc_net_157 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_3 mux_right_track_36 (
+ .in ( { chany_bottom_out[16] , chany_top_in[17] ,
+ right_bottom_grid_pin_39_[0] , chany_bottom_in[1] ,
+ chany_top_out[16] , chanx_right_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 ,
+ SYNOPSYS_UNCONNECTED_140 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_161 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 (
+ .in ( { chany_bottom_out[17] , chany_top_in[21] ,
+ right_bottom_grid_pin_40_[0] , chany_bottom_in[0] ,
+ chany_top_out[17] , chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size6_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 ,
+ SYNOPSYS_UNCONNECTED_143 } ) ,
+ .out ( { ZBUF_6_f_0 } ) ,
+ .p0 ( optlc_net_158 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 (
+ .in ( { chany_bottom_out[19] , chany_top_in[25] ,
+ right_bottom_grid_pin_41_[0] , chany_top_out[19] ,
+ chany_bottom_in[29] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size6_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_144 , SYNOPSYS_UNCONNECTED_145 ,
+ SYNOPSYS_UNCONNECTED_146 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_158 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_6 mux_bottom_track_37 (
+ .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] ,
+ bottom_left_grid_pin_47_[0] , chanx_right_out[16] ,
+ chanx_left_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size6_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 ,
+ SYNOPSYS_UNCONNECTED_149 } ) ,
+ .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_157 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_7 mux_bottom_track_45 (
+ .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] ,
+ bottom_left_grid_pin_48_[0] , chanx_right_out[17] ,
+ chanx_left_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size6_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 ,
+ SYNOPSYS_UNCONNECTED_152 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_160 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_8 mux_bottom_track_53 (
+ .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] ,
+ bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size6_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 ,
+ SYNOPSYS_UNCONNECTED_155 } ) ,
+ .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_160 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_9 mux_left_track_37 (
+ .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] ,
+ chany_top_out[16] , chany_bottom_in[17] ,
+ left_bottom_grid_pin_39_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_156 , SYNOPSYS_UNCONNECTED_157 ,
+ SYNOPSYS_UNCONNECTED_158 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_10 mux_left_track_45 (
+ .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] ,
+ chany_top_out[17] , chany_bottom_in[21] ,
+ left_bottom_grid_pin_40_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 ,
+ SYNOPSYS_UNCONNECTED_161 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_160 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6 mux_left_track_53 (
+ .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] ,
+ chany_top_out[19] , chany_bottom_in[25] ,
+ left_bottom_grid_pin_41_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 ,
+ SYNOPSYS_UNCONNECTED_164 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_159 ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_7 mem_bottom_track_45 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_8 mem_bottom_track_53 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_8_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_9 mem_left_track_37 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_9_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_10_sram ) ) ;
+sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ;
+sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) ,
+ .X ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( net_net_151 ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 Reset_N_FTB01 ( .A ( Reset_S_in ) ,
+ .X ( Reset_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) ,
+ .X ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) ,
+ .HI ( optlc_net_156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) ,
+ .HI ( optlc_net_157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) ,
+ .HI ( optlc_net_158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) ,
+ .HI ( optlc_net_159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) ,
+ .HI ( optlc_net_160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) ,
+ .HI ( optlc_net_161 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1350 ( .A ( ZBUF_6_f_0 ) ,
+ .X ( chanx_right_out[22] ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_mt_inst_1370 ( .A ( ropt_net_182 ) ,
+ .X ( chanx_left_out[3] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_148 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:8] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .Y ( BUF_net_136 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:9] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .Y ( BUF_net_134 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .Y ( BUF_net_132 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:7] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .Y ( BUF_net_130 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_128 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_125 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_123 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_121 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_119 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_117 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_115 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_113 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_111 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_109 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_105 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_103 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_193 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_159 ) ,
+ .X ( copt_net_157 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_157 ) ,
+ .X ( copt_net_158 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_160 ) ,
+ .X ( copt_net_159 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_160 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_158 ) ,
+ .X ( copt_net_161 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_161 ) ,
+ .X ( copt_net_162 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_162 ) ,
+ .X ( ropt_net_190 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_192 ) ,
+ .X ( ropt_net_191 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( ropt_net_190 ) ,
+ .X ( ropt_net_192 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_194 ) ,
+ .X ( ropt_net_193 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_191 ) ,
+ .X ( ropt_net_194 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_96 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:6] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
+ .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
+ top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
+ top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
+ top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ ,
+ right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ ,
+ right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ ,
+ right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ ,
+ right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in ,
+ left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
+ left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
+ left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
+ left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
+ left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
+ chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in ,
+ Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out ,
+ pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in ,
+ prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_44_ ;
+input [0:0] top_left_grid_pin_45_ ;
+input [0:0] top_left_grid_pin_46_ ;
+input [0:0] top_left_grid_pin_47_ ;
+input [0:0] top_left_grid_pin_48_ ;
+input [0:0] top_left_grid_pin_49_ ;
+input [0:0] top_left_grid_pin_50_ ;
+input [0:0] top_left_grid_pin_51_ ;
+input [0:29] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_3_ ;
+input [0:0] right_bottom_grid_pin_5_ ;
+input [0:0] right_bottom_grid_pin_7_ ;
+input [0:0] right_bottom_grid_pin_9_ ;
+input [0:0] right_bottom_grid_pin_11_ ;
+input [0:0] right_bottom_grid_pin_13_ ;
+input [0:0] right_bottom_grid_pin_15_ ;
+input [0:0] right_bottom_grid_pin_17_ ;
+input [0:29] chanx_left_in ;
+input [0:0] left_bottom_grid_pin_1_ ;
+input [0:0] left_bottom_grid_pin_3_ ;
+input [0:0] left_bottom_grid_pin_5_ ;
+input [0:0] left_bottom_grid_pin_7_ ;
+input [0:0] left_bottom_grid_pin_9_ ;
+input [0:0] left_bottom_grid_pin_11_ ;
+input [0:0] left_bottom_grid_pin_13_ ;
+input [0:0] left_bottom_grid_pin_15_ ;
+input [0:0] left_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_right_out ;
+output [0:29] chanx_left_out ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_TOP ;
+input Test_en_S_in ;
+output Test_en_N_out ;
+input pReset_S_in ;
+input pReset_E_in ;
+input pReset_W_in ;
+output pReset_N_out ;
+output pReset_W_out ;
+output pReset_E_out ;
+input Reset_S_in ;
+output Reset_N_out ;
+input prog_clk_0_N_in ;
+input prog_clk_3_S_in ;
+output prog_clk_3_N_out ;
+input clk_3_S_in ;
+output clk_3_N_out ;
+
+wire ropt_net_176 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:2] mux_tree_tapbuf_size5_5_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size7_0_sram ;
+wire [0:2] mux_tree_tapbuf_size7_1_sram ;
+wire [0:2] mux_tree_tapbuf_size7_2_sram ;
+wire [0:2] mux_tree_tapbuf_size7_3_sram ;
+wire [0:2] mux_tree_tapbuf_size7_4_sram ;
+wire [0:2] mux_tree_tapbuf_size7_5_sram ;
+wire [0:2] mux_tree_tapbuf_size7_6_sram ;
+wire [0:2] mux_tree_tapbuf_size7_7_sram ;
+wire [0:2] mux_tree_tapbuf_size7_8_sram ;
+wire [0:2] mux_tree_tapbuf_size7_9_sram ;
+wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size9_0_sram ;
+wire [0:3] mux_tree_tapbuf_size9_1_sram ;
+wire [0:3] mux_tree_tapbuf_size9_2_sram ;
+wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
+
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] ,
+ chanx_left_in[0] , chanx_right_out[4] } ) ,
+ .sram ( mux_tree_tapbuf_size7_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_154 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 (
+ .in ( { chany_top_in[10] , chany_top_in[21] ,
+ right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] ,
+ right_bottom_grid_pin_13_[0] , chanx_right_out[4] ,
+ chanx_right_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size7_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_154 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 (
+ .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] ,
+ right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] ,
+ chanx_right_out[12] , chanx_right_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size7_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_154 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 (
+ .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] ,
+ right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] ,
+ chanx_right_out[13] , chanx_right_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size7_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 (
+ .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] ,
+ chanx_right_out[15] , chanx_right_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size7_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 (
+ .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] ,
+ chanx_left_out[21] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 (
+ .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] ,
+ chanx_left_out[23] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
+ SYNOPSYS_UNCONNECTED_21 } ) ,
+ .out ( chanx_left_out[2] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 (
+ .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] ,
+ chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
+ SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 (
+ .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] ,
+ chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 } ) ,
+ .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 (
+ .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] ,
+ chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] ,
+ left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size7_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
+ SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_left_out[14] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size7_9_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 (
+ .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] ,
+ chanx_right_out[7] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
+ SYNOPSYS_UNCONNECTED_33 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_152 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 (
+ .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
+ top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] ,
+ chanx_right_out[9] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
+ SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 (
+ .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] ,
+ top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] ,
+ chanx_right_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 } ) ,
+ .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
+ SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 (
+ .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
+ chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
+ SYNOPSYS_UNCONNECTED_45 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_155 ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 (
+ .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] ,
+ right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
+ SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 (
+ .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] ,
+ chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 } ) ,
+ .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 (
+ .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] ,
+ chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 ,
+ SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 (
+ .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] ,
+ chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 ,
+ SYNOPSYS_UNCONNECTED_57 } ) ,
+ .out ( chanx_left_out[26] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 (
+ .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] ,
+ chanx_right_in[17] , chanx_right_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 ,
+ SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 (
+ .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] ,
+ chanx_right_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 } ) ,
+ .out ( chany_top_out[7] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] ,
+ chanx_right_in[25] , chanx_right_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 ,
+ SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] ,
+ chanx_right_in[29] , chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 ,
+ SYNOPSYS_UNCONNECTED_69 } ) ,
+ .out ( chany_top_out[9] ) , .p0 ( optlc_net_155 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 (
+ .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] ,
+ chanx_right_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 ,
+ SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 (
+ .in ( { chany_top_in[9] , chany_top_in[20] ,
+ right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] ,
+ chanx_right_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_155 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] ,
+ chanx_right_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) ,
+ .out ( chany_top_out[11] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 (
+ .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] ,
+ chanx_right_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) ,
+ .out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 (
+ .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] ,
+ chanx_right_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) ,
+ .out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 (
+ .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] ,
+ chanx_right_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 (
+ .in ( { chanx_left_out[24] , chanx_right_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_155 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 (
+ .in ( { chanx_left_out[25] , chanx_right_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) ,
+ .out ( chany_top_out[15] ) , .p0 ( optlc_net_152 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 (
+ .in ( { chanx_left_out[27] , chanx_right_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) ,
+ .out ( chany_top_out[16] ) , .p0 ( optlc_net_155 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 (
+ .in ( { chanx_left_out[28] , chanx_right_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) ,
+ .out ( chany_top_out[17] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 (
+ .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) ,
+ .out ( chany_top_out[20] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 (
+ .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) ,
+ .out ( chany_top_out[21] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 (
+ .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 (
+ .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) ,
+ .out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 (
+ .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) ,
+ .out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 (
+ .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) ,
+ .out ( chany_top_out[25] ) , .p0 ( optlc_net_155 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 (
+ .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) ,
+ .out ( chany_top_out[29] ) , .p0 ( optlc_net_154 ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] ,
+ right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] ,
+ right_bottom_grid_pin_15_[0] , chanx_right_out[7] ,
+ chanx_right_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 ,
+ SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] ,
+ right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] ,
+ right_bottom_grid_pin_17_[0] , chanx_right_out[8] ,
+ chanx_right_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 ,
+ SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_150 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 (
+ .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] ,
+ chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 ,
+ SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) ,
+ .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 (
+ .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] ,
+ right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] ,
+ right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] ,
+ right_bottom_grid_pin_17_[0] , chanx_right_out[9] ,
+ chanx_right_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 ,
+ SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ;
+sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 (
+ .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] ,
+ right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] ,
+ right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] ,
+ chanx_right_out[11] , chanx_right_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size9_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 ,
+ SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_153 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 (
+ .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] ,
+ chanx_left_out[24] , left_bottom_grid_pin_1_[0] ,
+ left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
+ left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size9_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 ,
+ SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) ,
+ .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 (
+ .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] ,
+ chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] ,
+ left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
+ left_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size9_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 ,
+ SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) ,
+ .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
+sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) ,
+ .HI ( optlc_net_149 ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( pReset_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( pReset_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) ,
+ .HI ( optlc_net_150 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) ,
+ .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) ,
+ .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) ,
+ .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) ,
+ .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) ,
+ .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) ,
+ .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) ,
+ .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) ,
+ .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) ,
+ .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) ,
+ .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) ,
+ .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) ,
+ .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) ,
+ .X ( chanx_left_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) ,
+ .X ( chanx_left_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) ,
+ .X ( chanx_left_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) ,
+ .X ( chanx_left_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) ,
+ .X ( chanx_left_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) ,
+ .X ( chanx_left_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) ,
+ .X ( chanx_left_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) ,
+ .X ( chanx_left_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) ,
+ .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) ,
+ .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) ,
+ .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) ,
+ .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) ,
+ .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) ,
+ .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) ,
+ .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) ,
+ .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) ,
+ .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) ,
+ .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) ,
+ .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) ,
+ .X ( chanx_right_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) ,
+ .X ( chanx_right_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) ,
+ .X ( chanx_right_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) ,
+ .X ( chanx_right_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) ,
+ .X ( chanx_right_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) ,
+ .X ( chanx_right_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) ,
+ .X ( chanx_right_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) ,
+ .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_140 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) ,
+ .Y ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_144 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) ,
+ .HI ( optlc_net_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) ,
+ .HI ( optlc_net_152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) ,
+ .HI ( optlc_net_153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) ,
+ .HI ( optlc_net_154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) ,
+ .HI ( optlc_net_155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) ,
+ .HI ( optlc_net_156 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) ,
+ .X ( SC_OUT_TOP ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_103 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_103 ) ,
+ .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) ,
+ .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_100 ) ,
+ .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_74 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_72 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_70 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_68 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_190 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_94 ) ,
+ .X ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_92 ) ,
+ .X ( copt_net_93 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) ,
+ .X ( copt_net_94 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_95 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) ,
+ .X ( copt_net_96 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_93 ) ,
+ .X ( copt_net_97 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( copt_net_97 ) ,
+ .X ( ropt_net_188 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1352 ( .A ( ropt_net_188 ) ,
+ .X ( ropt_net_189 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1353 ( .A ( ropt_net_189 ) ,
+ .X ( ropt_net_190 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_66 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_64 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_62 ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ ,
+ right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
+ right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
+ bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out ,
+ ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out ,
+ prog_clk_0_E_in ) ;
+input [0:0] pReset ;
+input [0:29] chanx_right_in ;
+input [0:0] right_top_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:0] right_bottom_grid_pin_42_ ;
+input [0:0] right_bottom_grid_pin_43_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_1_ ;
+input [0:0] ccff_head ;
+output [0:29] chanx_right_out ;
+output [0:29] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+output SC_OUT_BOT ;
+input pReset_E_in ;
+output pReset_S_out ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_129 ;
+wire ropt_net_130 ;
+wire ropt_net_131 ;
+wire ropt_net_128 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_24_sram ;
+wire [0:1] mux_tree_tapbuf_size2_25_sram ;
+wire [0:1] mux_tree_tapbuf_size2_26_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 (
+ .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
+ right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 (
+ .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 (
+ .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 (
+ .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_89 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_89 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_89 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 (
+ .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) ,
+ .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) ,
+ .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_right_out[19] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) ,
+ .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chanx_right_out[20] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_right_out[21] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 (
+ .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) ,
+ .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) ,
+ .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_right_out[23] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) ,
+ .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chanx_right_out[24] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
+ .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+ .out ( chanx_right_out[25] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chanx_right_out[27] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chanx_right_out[28] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
+ .out ( chanx_right_out[29] ) , .p0 ( optlc_net_88 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 (
+ .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 (
+ .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_91 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 (
+ .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_24_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_89 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 (
+ .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_25_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_89 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 (
+ .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_26_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_89 ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 (
+ .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[14] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 (
+ .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[2] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_90 ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) ,
+ .HI ( optlc_net_88 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) ,
+ .X ( chany_bottom_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) ,
+ .X ( ropt_net_129 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) ,
+ .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) ,
+ .X ( ropt_net_130 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) ,
+ .X ( ropt_net_131 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) ,
+ .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) ,
+ .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) ,
+ .X ( ropt_net_128 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) ,
+ .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) ,
+ .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) ,
+ .HI ( optlc_net_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) ,
+ .HI ( optlc_net_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) ,
+ .HI ( optlc_net_91 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_142 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_140 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_138 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_136 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+wire copt_net_160 ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_160 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( copt_net_160 ) ,
+ .X ( mem_out[1] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_133 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_130 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_128 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_126 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .Y ( BUF_net_124 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_121 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_119 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_116 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_113 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_111 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_109 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_105 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_102 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_100 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:4] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_168 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ropt_net_172 ) ,
+ .X ( copt_net_149 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_149 ) ,
+ .X ( copt_net_150 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( ropt_net_170 ) ,
+ .X ( copt_net_151 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_153 ) ,
+ .X ( copt_net_152 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_150 ) ,
+ .X ( copt_net_153 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_154 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1340 ( .A ( copt_net_151 ) ,
+ .X ( ropt_net_166 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_166 ) ,
+ .X ( ropt_net_167 ) ) ;
+sky130_fd_sc_hd__buf_2 ropt_h_inst_1342 ( .A ( ropt_net_167 ) ,
+ .X ( ropt_net_168 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_152 ) ,
+ .X ( ropt_net_169 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_171 ) ,
+ .X ( ropt_net_170 ) ) ;
+sky130_fd_sc_hd__buf_4 ropt_h_inst_1345 ( .A ( ropt_net_169 ) ,
+ .X ( ropt_net_171 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( copt_net_154 ) ,
+ .X ( ropt_net_172 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_96 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_94 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+endmodule
+
+
+module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:5] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .Y ( BUF_net_90 ) ) ;
+endmodule
+
+
+module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ ,
+ chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
+ right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
+ right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
+ right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
+ bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out ,
+ chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out ,
+ prog_clk_0_E_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_1_ ;
+input [0:29] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_36_ ;
+input [0:0] right_bottom_grid_pin_37_ ;
+input [0:0] right_bottom_grid_pin_38_ ;
+input [0:0] right_bottom_grid_pin_39_ ;
+input [0:0] right_bottom_grid_pin_40_ ;
+input [0:0] right_bottom_grid_pin_41_ ;
+input [0:0] right_bottom_grid_pin_42_ ;
+input [0:0] right_bottom_grid_pin_43_ ;
+input [0:29] chany_bottom_in ;
+input [0:0] bottom_left_grid_pin_1_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_right_out ;
+output [0:29] chany_bottom_out ;
+output [0:0] ccff_tail ;
+input pReset_E_in ;
+output pReset_S_out ;
+input prog_clk_0_E_in ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:1] mux_tree_tapbuf_size3_3_sram ;
+wire [0:1] mux_tree_tapbuf_size3_4_sram ;
+wire [0:1] mux_tree_tapbuf_size3_5_sram ;
+wire [0:1] mux_tree_tapbuf_size3_6_sram ;
+wire [0:1] mux_tree_tapbuf_size3_7_sram ;
+wire [0:1] mux_tree_tapbuf_size3_8_sram ;
+wire [0:1] mux_tree_tapbuf_size3_9_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_10_sram ;
+wire [0:2] mux_tree_tapbuf_size4_11_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:2] mux_tree_tapbuf_size4_6_sram ;
+wire [0:2] mux_tree_tapbuf_size4_7_sram ;
+wire [0:2] mux_tree_tapbuf_size4_8_sram ;
+wire [0:2] mux_tree_tapbuf_size4_9_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size5_0_sram ;
+wire [0:2] mux_tree_tapbuf_size5_10_sram ;
+wire [0:2] mux_tree_tapbuf_size5_11_sram ;
+wire [0:2] mux_tree_tapbuf_size5_1_sram ;
+wire [0:2] mux_tree_tapbuf_size5_2_sram ;
+wire [0:2] mux_tree_tapbuf_size5_3_sram ;
+wire [0:2] mux_tree_tapbuf_size5_4_sram ;
+wire [0:2] mux_tree_tapbuf_size5_5_sram ;
+wire [0:2] mux_tree_tapbuf_size5_6_sram ;
+wire [0:2] mux_tree_tapbuf_size5_7_sram ;
+wire [0:2] mux_tree_tapbuf_size5_8_sram ;
+wire [0:2] mux_tree_tapbuf_size5_9_sram ;
+wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size6_0_sram ;
+wire [0:2] mux_tree_tapbuf_size6_1_sram ;
+wire [0:2] mux_tree_tapbuf_size6_2_sram ;
+wire [0:2] mux_tree_tapbuf_size6_3_sram ;
+wire [0:2] mux_tree_tapbuf_size6_4_sram ;
+wire [0:2] mux_tree_tapbuf_size6_5_sram ;
+wire [0:2] mux_tree_tapbuf_size6_6_sram ;
+wire [0:2] mux_tree_tapbuf_size6_7_sram ;
+wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] ,
+ chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size6_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] ,
+ chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size6_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
+ SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_146 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] ,
+ chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size6_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_146 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 (
+ .in ( { chany_top_in[0] , chany_bottom_out[7] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) ,
+ .sram ( mux_tree_tapbuf_size6_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
+ SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 (
+ .in ( { chany_top_in[2] , chany_bottom_out[9] ,
+ right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
+ right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) ,
+ .sram ( mux_tree_tapbuf_size6_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 (
+ .in ( { chany_top_in[4] , chany_bottom_out[11] ,
+ right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
+ right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) ,
+ .sram ( mux_tree_tapbuf_size6_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
+ SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_147 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 (
+ .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] ,
+ chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
+ SYNOPSYS_UNCONNECTED_21 } ) ,
+ .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_145 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 (
+ .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] ,
+ chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size6_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
+ SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_145 ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 (
+ .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] ,
+ chany_top_out[7] , chany_top_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size5_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
+ SYNOPSYS_UNCONNECTED_27 } ) ,
+ .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 (
+ .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] ,
+ chany_top_out[8] , chany_top_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size5_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
+ SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chany_top_out[2] ) , .p0 ( optlc_net_146 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 (
+ .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] ,
+ chany_top_out[11] , chany_top_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size5_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
+ SYNOPSYS_UNCONNECTED_33 } ) ,
+ .out ( chany_top_out[5] ) , .p0 ( optlc_net_146 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 (
+ .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] ,
+ chany_top_out[13] , chany_top_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size5_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
+ SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chany_top_out[10] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 (
+ .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] ,
+ right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] ,
+ chany_top_out[4] } ) ,
+ .sram ( mux_tree_tapbuf_size5_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
+ SYNOPSYS_UNCONNECTED_39 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 (
+ .in ( { chany_top_in[1] , chany_bottom_out[8] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[8] } ) ,
+ .sram ( mux_tree_tapbuf_size5_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
+ SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 (
+ .in ( { chany_top_in[5] , chany_bottom_out[12] ,
+ right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] ,
+ chany_top_out[12] } ) ,
+ .sram ( mux_tree_tapbuf_size5_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
+ SYNOPSYS_UNCONNECTED_45 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_147 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 (
+ .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] ,
+ chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size5_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
+ SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 (
+ .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] ,
+ chanx_right_in[18] , chanx_right_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size5_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
+ SYNOPSYS_UNCONNECTED_51 } ) ,
+ .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_145 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 (
+ .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] ,
+ chanx_right_in[16] , chanx_right_in[27] } ) ,
+ .sram ( mux_tree_tapbuf_size5_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 ,
+ SYNOPSYS_UNCONNECTED_54 } ) ,
+ .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_145 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 (
+ .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] ,
+ chanx_right_in[14] , chanx_right_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size5_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 ,
+ SYNOPSYS_UNCONNECTED_57 } ) ,
+ .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 (
+ .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] ,
+ chanx_right_in[13] , chanx_right_in[24] } ) ,
+ .sram ( mux_tree_tapbuf_size5_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 ,
+ SYNOPSYS_UNCONNECTED_60 } ) ,
+ .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_7_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_8_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_9_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_10_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size5_11_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 (
+ .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] ,
+ chany_top_out[29] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
+ SYNOPSYS_UNCONNECTED_63 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 (
+ .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] ,
+ chany_top_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 ,
+ SYNOPSYS_UNCONNECTED_66 } ) ,
+ .out ( chany_top_out[26] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 (
+ .in ( { chany_top_in[9] , chany_bottom_out[13] ,
+ right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 ,
+ SYNOPSYS_UNCONNECTED_69 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_147 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 (
+ .in ( { chany_top_in[13] , chany_bottom_out[15] ,
+ right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 ,
+ SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 (
+ .in ( { chany_bottom_out[16] , chany_top_in[17] ,
+ right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
+ SYNOPSYS_UNCONNECTED_75 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 (
+ .in ( { chany_bottom_out[17] , chany_top_in[21] ,
+ right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 ,
+ SYNOPSYS_UNCONNECTED_78 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 (
+ .in ( { chany_bottom_out[19] , chany_top_in[25] ,
+ right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 ,
+ SYNOPSYS_UNCONNECTED_81 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_146 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 (
+ .in ( { chany_bottom_out[20] , chany_top_in[29] ,
+ right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) ,
+ .sram ( mux_tree_tapbuf_size4_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 ,
+ SYNOPSYS_UNCONNECTED_84 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_146 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 (
+ .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] ,
+ chany_top_out[29] , chany_bottom_in[29] } ) ,
+ .sram ( mux_tree_tapbuf_size4_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
+ SYNOPSYS_UNCONNECTED_87 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 (
+ .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] ,
+ chanx_right_in[19] } ) ,
+ .sram ( mux_tree_tapbuf_size4_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 ,
+ SYNOPSYS_UNCONNECTED_90 } ) ,
+ .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 (
+ .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] ,
+ chanx_right_in[23] } ) ,
+ .sram ( mux_tree_tapbuf_size4_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 ,
+ SYNOPSYS_UNCONNECTED_93 } ) ,
+ .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 (
+ .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] ,
+ chanx_right_in[22] } ) ,
+ .sram ( mux_tree_tapbuf_size4_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 ,
+ SYNOPSYS_UNCONNECTED_96 } ) ,
+ .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 (
+ .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
+ .out ( chany_top_out[18] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 (
+ .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 (
+ .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] ,
+ chany_top_out[21] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_146 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 (
+ .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] ,
+ chany_top_out[23] } ) ,
+ .sram ( mux_tree_tapbuf_size3_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_147 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 (
+ .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] ,
+ chany_top_out[24] } ) ,
+ .sram ( mux_tree_tapbuf_size3_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 (
+ .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] ,
+ chany_top_out[25] } ) ,
+ .sram ( mux_tree_tapbuf_size3_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_148 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 (
+ .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] ,
+ chany_top_out[27] } ) ,
+ .sram ( mux_tree_tapbuf_size3_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_147 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 (
+ .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] ,
+ chany_top_out[28] } ) ,
+ .sram ( mux_tree_tapbuf_size3_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_144 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 (
+ .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] ,
+ chany_bottom_in[4] } ) ,
+ .sram ( mux_tree_tapbuf_size3_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
+ .out ( chanx_right_out[25] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 (
+ .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size3_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
+ .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_8_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
+ .out ( chanx_right_out[19] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
+ .out ( chanx_right_out[20] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 (
+ .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 (
+ .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
+ .out ( chanx_right_out[23] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 (
+ .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
+ .out ( chanx_right_out[24] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 (
+ .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 (
+ .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
+ .out ( chanx_right_out[27] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 (
+ .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
+ .out ( chanx_right_out[28] ) , .p0 ( optlc_net_143 ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) ,
+ .X ( pReset_S_out ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) ,
+ .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) ,
+ .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) ,
+ .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) ,
+ .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) ,
+ .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) ,
+ .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) ,
+ .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) ,
+ .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) ,
+ .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) ,
+ .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) ,
+ .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) ,
+ .X ( chany_bottom_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) ,
+ .X ( chany_bottom_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) ,
+ .X ( chany_bottom_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) ,
+ .X ( chany_bottom_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) ,
+ .X ( chany_bottom_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) ,
+ .X ( chany_bottom_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) ,
+ .X ( chany_bottom_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) ,
+ .X ( chany_bottom_out[29] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) ,
+ .X ( chanx_right_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) ,
+ .HI ( optlc_net_143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) ,
+ .HI ( optlc_net_144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) ,
+ .HI ( optlc_net_145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) ,
+ .HI ( optlc_net_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) ,
+ .HI ( optlc_net_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) ,
+ .HI ( optlc_net_148 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:2] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:2] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_87 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_91 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .Y ( BUF_net_85 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:3] in ;
+input [0:2] sram ;
+input [0:2] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) ,
+ .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( copt_net_108 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_106 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_106 ) ,
+ .X ( copt_net_107 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_107 ) ,
+ .X ( copt_net_108 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_99 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) ,
+ .X ( copt_net_100 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_103 ) ,
+ .X ( copt_net_101 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) ,
+ .X ( copt_net_102 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_100 ) ,
+ .X ( copt_net_103 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_102 ) ,
+ .X ( copt_net_104 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1355 ( .A ( copt_net_104 ) ,
+ .X ( ropt_net_189 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( ropt_net_189 ) ,
+ .X ( ropt_net_190 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_190 ) ,
+ .X ( ropt_net_191 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_80 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_78 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_76 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_72 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .X ( out[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_69 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_67 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
+ .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_65 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_63 ) ) ;
+endmodule
+
+
+module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .Y ( BUF_net_61 ) ) ;
+endmodule
+
+
+module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ ,
+ chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ ,
+ right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ ,
+ right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ ,
+ right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ ,
+ right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
+ ccff_tail , pReset_E_in , prog_clk_0_E_in ) ;
+input [0:0] pReset ;
+input [0:29] chany_top_in ;
+input [0:0] top_left_grid_pin_1_ ;
+input [0:29] chanx_right_in ;
+input [0:0] right_bottom_grid_pin_1_ ;
+input [0:0] right_bottom_grid_pin_3_ ;
+input [0:0] right_bottom_grid_pin_5_ ;
+input [0:0] right_bottom_grid_pin_7_ ;
+input [0:0] right_bottom_grid_pin_9_ ;
+input [0:0] right_bottom_grid_pin_11_ ;
+input [0:0] right_bottom_grid_pin_13_ ;
+input [0:0] right_bottom_grid_pin_15_ ;
+input [0:0] right_bottom_grid_pin_17_ ;
+input [0:0] ccff_head ;
+output [0:29] chany_top_out ;
+output [0:29] chanx_right_out ;
+output [0:0] ccff_tail ;
+input pReset_E_in ;
+input prog_clk_0_E_in ;
+
+wire ropt_net_141 ;
+wire ropt_net_133 ;
+wire ropt_net_134 ;
+wire ropt_net_135 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:1] mux_tree_tapbuf_size2_0_sram ;
+wire [0:1] mux_tree_tapbuf_size2_10_sram ;
+wire [0:1] mux_tree_tapbuf_size2_11_sram ;
+wire [0:1] mux_tree_tapbuf_size2_12_sram ;
+wire [0:1] mux_tree_tapbuf_size2_13_sram ;
+wire [0:1] mux_tree_tapbuf_size2_14_sram ;
+wire [0:1] mux_tree_tapbuf_size2_15_sram ;
+wire [0:1] mux_tree_tapbuf_size2_16_sram ;
+wire [0:1] mux_tree_tapbuf_size2_17_sram ;
+wire [0:1] mux_tree_tapbuf_size2_18_sram ;
+wire [0:1] mux_tree_tapbuf_size2_19_sram ;
+wire [0:1] mux_tree_tapbuf_size2_1_sram ;
+wire [0:1] mux_tree_tapbuf_size2_20_sram ;
+wire [0:1] mux_tree_tapbuf_size2_21_sram ;
+wire [0:1] mux_tree_tapbuf_size2_22_sram ;
+wire [0:1] mux_tree_tapbuf_size2_23_sram ;
+wire [0:1] mux_tree_tapbuf_size2_24_sram ;
+wire [0:1] mux_tree_tapbuf_size2_25_sram ;
+wire [0:1] mux_tree_tapbuf_size2_2_sram ;
+wire [0:1] mux_tree_tapbuf_size2_3_sram ;
+wire [0:1] mux_tree_tapbuf_size2_4_sram ;
+wire [0:1] mux_tree_tapbuf_size2_5_sram ;
+wire [0:1] mux_tree_tapbuf_size2_6_sram ;
+wire [0:1] mux_tree_tapbuf_size2_7_sram ;
+wire [0:1] mux_tree_tapbuf_size2_8_sram ;
+wire [0:1] mux_tree_tapbuf_size2_9_sram ;
+wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
+wire [0:1] mux_tree_tapbuf_size3_0_sram ;
+wire [0:1] mux_tree_tapbuf_size3_1_sram ;
+wire [0:1] mux_tree_tapbuf_size3_2_sram ;
+wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
+wire [0:2] mux_tree_tapbuf_size4_0_sram ;
+wire [0:2] mux_tree_tapbuf_size4_1_sram ;
+wire [0:2] mux_tree_tapbuf_size4_2_sram ;
+wire [0:2] mux_tree_tapbuf_size4_3_sram ;
+wire [0:2] mux_tree_tapbuf_size4_4_sram ;
+wire [0:2] mux_tree_tapbuf_size4_5_sram ;
+wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
+ .sram ( mux_tree_tapbuf_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) ,
+ .sram ( mux_tree_tapbuf_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( chany_top_out[3] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) ,
+ .sram ( mux_tree_tapbuf_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( chany_top_out[6] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) ,
+ .sram ( mux_tree_tapbuf_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( chany_top_out[14] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 (
+ .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) ,
+ .sram ( mux_tree_tapbuf_size2_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
+ .out ( chany_top_out[22] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 (
+ .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+ .out ( chanx_right_out[7] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 (
+ .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_6_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
+ .out ( chanx_right_out[8] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 (
+ .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_7_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .out ( chanx_right_out[9] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 (
+ .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_8_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
+ .out ( chanx_right_out[10] ) , .p0 ( optlc_net_96 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 (
+ .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_9_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+ .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 (
+ .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_10_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
+ .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 (
+ .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_11_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+ .out ( chanx_right_out[13] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 (
+ .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_12_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
+ .out ( chanx_right_out[15] ) , .p0 ( optlc_net_98 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 (
+ .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_13_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+ .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 (
+ .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_14_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
+ .out ( chanx_right_out[17] ) , .p0 ( optlc_net_96 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 (
+ .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_15_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+ .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 (
+ .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_16_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
+ .out ( chanx_right_out[19] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 (
+ .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_17_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+ .out ( chanx_right_out[20] ) , .p0 ( optlc_net_96 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 (
+ .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_18_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
+ .out ( chanx_right_out[21] ) , .p0 ( optlc_net_96 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 (
+ .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_19_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+ .out ( chanx_right_out[23] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 (
+ .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_20_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
+ .out ( chanx_right_out[24] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 (
+ .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_21_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+ .out ( chanx_right_out[25] ) , .p0 ( optlc_net_95 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 (
+ .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_22_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
+ .out ( chanx_right_out[26] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 (
+ .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_23_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+ .out ( chanx_right_out[27] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 (
+ .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_24_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
+ .out ( chanx_right_out[28] ) , .p0 ( optlc_net_98 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 (
+ .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size2_25_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+ .out ( chanx_right_out[29] ) , .p0 ( optlc_net_94 ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 (
+ .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
+ SYNOPSYS_UNCONNECTED_55 } ) ,
+ .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 (
+ .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] ,
+ right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 ,
+ SYNOPSYS_UNCONNECTED_58 } ) ,
+ .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 (
+ .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] ,
+ right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 ,
+ SYNOPSYS_UNCONNECTED_61 } ) ,
+ .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 (
+ .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 ,
+ SYNOPSYS_UNCONNECTED_64 } ) ,
+ .out ( chanx_right_out[3] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 (
+ .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] ,
+ right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_4_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
+ SYNOPSYS_UNCONNECTED_67 } ) ,
+ .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 (
+ .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] ,
+ right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size4_5_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 ,
+ SYNOPSYS_UNCONNECTED_70 } ) ,
+ .out ( chanx_right_out[5] ) , .p0 ( optlc_net_97 ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 (
+ .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
+ .out ( chanx_right_out[6] ) , .p0 ( optlc_net_98 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 (
+ .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
+ .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 (
+ .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] ,
+ right_bottom_grid_pin_17_[0] } ) ,
+ .sram ( mux_tree_tapbuf_size3_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
+ .out ( chanx_right_out[22] ) , .p0 ( optlc_net_98 ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
+sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
+ .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
+ .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) ,
+ .X ( chany_top_out[29] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) ,
+ .X ( ropt_net_141 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) ,
+ .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) ,
+ .X ( ropt_net_133 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) ,
+ .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) ,
+ .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) ,
+ .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) ,
+ .X ( ropt_net_134 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) ,
+ .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) ,
+ .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) ,
+ .X ( ropt_net_135 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) ,
+ .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) ,
+ .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) ,
+ .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) ,
+ .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) ,
+ .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) ,
+ .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) ,
+ .X ( chany_top_out[20] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) ,
+ .X ( chany_top_out[21] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) ,
+ .X ( chany_top_out[23] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) ,
+ .X ( chany_top_out[24] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) ,
+ .X ( chany_top_out[25] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) ,
+ .X ( chany_top_out[26] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) ,
+ .X ( chany_top_out[27] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) ,
+ .X ( chany_top_out[28] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) ,
+ .HI ( optlc_net_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) ,
+ .HI ( optlc_net_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) ,
+ .HI ( optlc_net_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) ,
+ .HI ( optlc_net_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) ,
+ .HI ( optlc_net_98 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) ,
+ .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) ,
+ .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) ,
+ .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) ,
+ .X ( chany_top_out[1] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_198 ) ,
+ .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1638 ( .A ( copt_net_199 ) ,
+ .X ( copt_net_197 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( copt_net_197 ) ,
+ .X ( copt_net_198 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_200 ) ,
+ .X ( copt_net_199 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_201 ) ,
+ .X ( copt_net_200 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1642 ( .A ( mem_out[1] ) ,
+ .X ( copt_net_201 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_46 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_45 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_44 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_46 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_45 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_522_ ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_522_ ) ,
+ .Y ( BUF_net_131 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_44 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_521_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_521_ ) ,
+ .Y ( BUF_net_128 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+output p_abuf0 ;
+output p_abuf1 ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_43 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_42 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_43 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_42 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) ,
+ .X ( aps_rename_519_ ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( X ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_519_ ) ,
+ .Y ( BUF_net_133 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p0 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:0] mux_tree_size2_1_out ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_tree_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_tree_size2_42 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_43 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_42 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_43 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf2 , p_abuf3 , p0 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf2 ;
+output p_abuf3 ;
+input p0 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ;
+grid_clb_mux_tree_size2_44 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_45 mux_fabric_out_1 (
+ .in ( { p_abuf1 ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_46 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_45 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_46 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_64__63 ( .A ( p_abuf1 ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+output p_abuf2 ;
+input p0 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) ,
+ .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_41 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_40 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_39 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_38 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_41 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_39 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_518_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) ,
+ .Y ( BUF_net_125 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_517_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) ,
+ .Y ( BUF_net_122 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_37 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_36 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_36 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p0 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p0 ;
+input p3 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:0] mux_tree_size2_1_out ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_tree_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_tree_size2_36 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_37 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p0 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p3 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p0 ( p0 ) , .p3 ( p3 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_38 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_39 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_40 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_41 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_39 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_40 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_41 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p3 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_35 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_34 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_33 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_32 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_35 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , p_abuf0 ,
+ p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_516_ ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) ,
+ .Y ( BUF_net_119 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_32 ( in , sram , sram_inv , out , p_abuf0 ,
+ p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_515_ ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) ,
+ .Y ( BUF_net_116 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_31 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_30 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_31 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p3 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:0] mux_tree_size2_1_out ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_tree_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_31 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_31 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p3 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p3 ( p3 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_32 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_33 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_34 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_35 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_mem_32 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_33 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_34 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_35 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p3 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_29 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_28 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_27 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_26 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p_abuf0 ,
+ p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_514_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) ,
+ .Y ( BUF_net_113 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p_abuf0 ,
+ p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_513_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) ,
+ .Y ( BUF_net_110 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_25 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_24 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p3 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p3 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p2 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p2 ;
+input p3 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:0] mux_tree_size2_1_out ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_tree_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_25 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p0 , p2 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p2 ;
+input p3 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p2 ( p2 ) , .p3 ( p3 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_26 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_27 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_28 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_29 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ;
+grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_27 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_28 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_29 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p2 ;
+input p3 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) ,
+ .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_23 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_22 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_21 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_20 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 ,
+ p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_512_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) ,
+ .Y ( BUF_net_107 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p_abuf0 ,
+ p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_511_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) ,
+ .Y ( BUF_net_104 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_19 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_18 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p2 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:0] mux_tree_size2_1_out ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_tree_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_tree_size2_18 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_19 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_mem_18 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_19 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p2 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p2 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p2 ( p2 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_20 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_21 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_22 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_23 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_mem_20 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_21 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_22 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_23 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p2 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p2 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_17 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_16 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_15 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_14 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p2 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p2 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 ,
+ p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_510_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) ,
+ .Y ( BUF_net_101 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p_abuf0 ,
+ p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p4 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_509_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) ,
+ .Y ( BUF_net_98 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_13 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_12 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p4 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:0] mux_tree_size2_1_out ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_tree_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ;
+grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ;
+grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_13 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p0 , p2 , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p2 ;
+input p4 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p4 ( p4 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_14 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ;
+grid_clb_mux_tree_size2_15 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_16 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_17 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ;
+grid_clb_mux_tree_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_15 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_16 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_17 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p2 ;
+input p4 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) ,
+ .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_11 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_10 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_9 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_8 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_508_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) ,
+ .Y ( BUF_net_95 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_507_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) ,
+ .Y ( BUF_net_92 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_7 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_6 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p1 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p1 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:0] mux_tree_size2_1_out ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_tree_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_tree_size2_6 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_7 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_tree_size2_1_out ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_mem_6 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_7 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p0 , p1 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p1 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p1 ( p1 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_8 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_9 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_10 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_11 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_9 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_11 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p1 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_5 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_4 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_3 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_2 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) ,
+ .Y ( BUF_net_89 ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+output p_abuf0 ;
+input p1 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) ,
+ .Y ( BUF_net_86 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+input [0:0] Test_en ;
+input [0:0] ff_D ;
+input [0:0] ff_DI ;
+input [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input [0:0] ff_clk ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) ,
+ .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) ,
+ .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_1 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_mem_0 ( pReset , prog_clk , ccff_head ,
+ ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p4 ) ;
+input [0:1] in ;
+input [0:1] sram ;
+input [0:1] sram_inv ;
+output [0:0] out ;
+input p4 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
+endmodule
+
+
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 ( A0 , A1 , S , X ) ;
+input A0 ;
+input A1 ;
+input S ;
+output X ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ carry_follower_a , carry_follower_b , carry_follower_cin ,
+ carry_follower_cout ) ;
+input [0:0] carry_follower_a ;
+input [0:0] carry_follower_b ;
+input [0:0] carry_follower_cin ;
+output [0:0] carry_follower_cout ;
+
+grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ (
+ .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) ,
+ .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , prog_clk ,
+ ccff_head , ccff_tail , mem_out ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:16] mem_out ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_203 ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) ,
+ .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( ccff_head[0] ) ,
+ .X ( copt_net_190 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_195 ) ,
+ .X ( copt_net_191 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_191 ) ,
+ .X ( copt_net_192 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_190 ) ,
+ .X ( copt_net_193 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_192 ) ,
+ .X ( copt_net_194 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1636 ( .A ( copt_net_193 ) ,
+ .X ( copt_net_195 ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1644 ( .A ( copt_net_194 ) ,
+ .X ( ropt_net_203 ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut2_out , lut3_out ,
+ lut4_out ) ;
+input [0:15] in ;
+input [0:3] sram ;
+input [0:3] sram_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) ,
+ .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
+ .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) ,
+ .X ( lut2_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
+ .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
+ .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) ,
+ .X ( lut3_out[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) ,
+ .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) ,
+ .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv ,
+ lut2_out , lut3_out , lut4_out ) ;
+input [0:3] in ;
+input [0:15] sram ;
+input [0:15] sram_inv ;
+input [0:0] mode ;
+input [0:0] mode_inv ;
+output [0:1] lut2_out ;
+output [0:1] lut3_out ;
+output [0:0] lut4_out ;
+
+wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
+wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
+wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+
+sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) ,
+ .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
+ .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) ,
+ .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) ,
+ .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out ,
+ frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_lut4_in ;
+input [0:0] ccff_head ;
+output [0:1] frac_lut4_lut2_out ;
+output [0:1] frac_lut4_lut3_out ;
+output [0:0] frac_lut4_lut4_out ;
+output [0:0] ccff_tail ;
+
+wire [0:0] frac_lut4_0_mode ;
+wire [0:15] frac_lut4_0_sram ;
+
+grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) ,
+ .sram ( frac_lut4_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
+ SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 ,
+ SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
+ SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
+ SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
+ SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 ,
+ SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
+ SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+ .mode ( frac_lut4_0_mode ) ,
+ .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) ,
+ .lut4_out ( frac_lut4_lut4_out ) ) ;
+grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+ .ccff_tail ( ccff_tail ) ,
+ .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] ,
+ frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] ,
+ frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] ,
+ frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] ,
+ frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] ,
+ frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head ,
+ frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:3] frac_logic_in ;
+input [0:0] frac_logic_cin ;
+input [0:0] ccff_head ;
+output [0:1] frac_logic_out ;
+output [0:0] frac_logic_cout ;
+output [0:0] ccff_tail ;
+input p4 ;
+
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:0] mux_tree_size2_1_out ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] ,
+ mux_tree_size2_1_out[0] , frac_logic_in[3] } ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) ,
+ .frac_lut4_lut3_out ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] ,
+ frac_logic_out[1] } ) ,
+
+ .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
+ .carry_follower_a ( direct_interc_5_out ) ,
+ .carry_follower_b ( frac_logic_cin ) ,
+ .carry_follower_cin ( direct_interc_7_out ) ,
+ .carry_follower_cout ( frac_logic_cout ) ) ;
+grid_clb_mux_tree_size2_0 mux_frac_logic_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ;
+grid_clb_mux_tree_size2_1 mux_frac_lut4_0_in_2 (
+ .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ;
+grid_clb_mux_tree_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_1 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in ,
+ fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out ,
+ fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 ,
+ p_abuf1 , p0 , p1 , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fabric_in ;
+input [0:0] fabric_reg_in ;
+input [0:0] fabric_sc_in ;
+input [0:0] fabric_cin ;
+input [0:0] fabric_reset ;
+input [0:0] fabric_clk ;
+input [0:0] ccff_head ;
+output [0:1] fabric_out ;
+output [0:0] fabric_reg_out ;
+output [0:0] fabric_sc_out ;
+output [0:0] fabric_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p1 ;
+input p4 ;
+
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
+wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
+wire [0:1] mux_tree_size2_0_sram ;
+wire [0:1] mux_tree_size2_1_sram ;
+wire [0:0] mux_tree_size2_2_out ;
+wire [0:1] mux_tree_size2_2_sram ;
+wire [0:0] mux_tree_size2_3_out ;
+wire [0:1] mux_tree_size2_3_sram ;
+wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_1_ccff_tail ;
+wire [0:0] mux_tree_size2_mem_2_ccff_tail ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
+ .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) ,
+ .ccff_head ( ccff_head ) ,
+ .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
+ .frac_logic_cout ( fabric_cout ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .p4 ( p4 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) ,
+ .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) ,
+ .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
+ .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) ,
+ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
+ .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) ,
+ .ff_clk ( fabric_clk ) ) ;
+grid_clb_mux_tree_size2_2 mux_fabric_out_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
+ } ) ,
+ .sram ( mux_tree_size2_0_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+ .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_3 mux_fabric_out_1 (
+ .in ( { fabric_sc_out[0] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
+ } ) ,
+ .sram ( mux_tree_size2_1_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+ .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ;
+grid_clb_mux_tree_size2_4 mux_ff_0_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] ,
+ fabric_reg_in[0] } ) ,
+ .sram ( mux_tree_size2_2_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+ .out ( mux_tree_size2_2_out ) , .p4 ( p4 ) ) ;
+grid_clb_mux_tree_size2_5 mux_ff_1_D_0 (
+ .in ( {
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ,
+ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
+ } ) ,
+ .sram ( mux_tree_size2_3_sram ) ,
+ .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+ .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ;
+grid_clb_mux_tree_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_0_sram ) ) ;
+grid_clb_mux_tree_size2_mem_3 mem_fabric_out_1 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_1_sram ) ) ;
+grid_clb_mux_tree_size2_mem_4 mem_ff_0_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) ,
+ .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .mem_out ( mux_tree_size2_2_sram ) ) ;
+grid_clb_mux_tree_size2_mem_5 mem_ff_1_D_0 ( .pReset ( pReset ) ,
+ .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) ,
+ .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( fabric_sc_out[0] ) ,
+ .X ( fabric_reg_out[0] ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk ,
+ Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset ,
+ fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p4 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:3] fle_in ;
+input [0:0] fle_reg_in ;
+input [0:0] fle_sc_in ;
+input [0:0] fle_cin ;
+input [0:0] fle_reset ;
+input [0:0] fle_clk ;
+input [0:0] ccff_head ;
+output [0:1] fle_out ;
+output [0:0] fle_reg_out ;
+output [0:0] fle_sc_out ;
+output [0:0] fle_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+input p0 ;
+input p1 ;
+input p4 ;
+
+grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) ,
+ .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) ,
+ .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) ,
+ .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) ,
+ .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
+ .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) ,
+ .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) ,
+ .p4 ( p4 ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_clb_ ( pReset , prog_clk , Test_en ,
+ clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 ,
+ clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i ,
+ clb_I7 , clb_I7i , clb_reg_in , clb_sc_in , clb_cin , clb_reset ,
+ clb_clk , ccff_head , clb_O , clb_reg_out , clb_sc_out , clb_cout ,
+ ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 ,
+ p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 ,
+ p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , p1 , p2 , p3 , p4 , p5 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:1] clb_I0 ;
+input [0:1] clb_I0i ;
+input [0:1] clb_I1 ;
+input [0:1] clb_I1i ;
+input [0:1] clb_I2 ;
+input [0:1] clb_I2i ;
+input [0:1] clb_I3 ;
+input [0:1] clb_I3i ;
+input [0:1] clb_I4 ;
+input [0:1] clb_I4i ;
+input [0:1] clb_I5 ;
+input [0:1] clb_I5i ;
+input [0:1] clb_I6 ;
+input [0:1] clb_I6i ;
+input [0:1] clb_I7 ;
+input [0:1] clb_I7i ;
+input [0:0] clb_reg_in ;
+input [0:0] clb_sc_in ;
+input [0:0] clb_cin ;
+input [0:0] clb_reset ;
+input [0:0] clb_clk ;
+input [0:0] ccff_head ;
+output [0:15] clb_O ;
+output [0:0] clb_reg_out ;
+output [0:0] clb_sc_out ;
+output [0:0] clb_cout ;
+output [0:0] ccff_tail ;
+output p_abuf0 ;
+output p_abuf1 ;
+output p_abuf2 ;
+output p_abuf3 ;
+output p_abuf4 ;
+output p_abuf5 ;
+output p_abuf6 ;
+output p_abuf7 ;
+output p_abuf8 ;
+output p_abuf9 ;
+output p_abuf10 ;
+output p_abuf11 ;
+output p_abuf12 ;
+output p_abuf13 ;
+output p_abuf14 ;
+output p_abuf15 ;
+output p_abuf16 ;
+input p0 ;
+input p1 ;
+input p2 ;
+input p3 ;
+input p4 ;
+input p5 ;
+
+wire [0:0] direct_interc_32_out ;
+wire [0:0] direct_interc_34_out ;
+wire [0:0] direct_interc_41_out ;
+wire [0:0] direct_interc_43_out ;
+wire [0:0] direct_interc_50_out ;
+wire [0:0] direct_interc_52_out ;
+wire [0:0] direct_interc_59_out ;
+wire [0:0] direct_interc_61_out ;
+wire [0:0] direct_interc_68_out ;
+wire [0:0] direct_interc_70_out ;
+wire [0:0] direct_interc_77_out ;
+wire [0:0] direct_interc_79_out ;
+wire [0:0] direct_interc_86_out ;
+wire [0:0] direct_interc_88_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ;
+wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ;
+wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ;
+
+grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) ,
+ .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) ,
+ .fle_cin ( clb_cin ) , .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) ,
+ .ccff_head ( ccff_head ) ,
+ .fle_out ( { clb_O[1] , clb_O[0] } ) ,
+ .fle_reg_out ( direct_interc_32_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ,
+ .fle_cout ( direct_interc_34_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) ,
+ .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p2 ) ,
+ .p4 ( p5 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) ,
+ .fle_reg_in ( direct_interc_32_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ,
+ .fle_cin ( direct_interc_34_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) ,
+ .fle_out ( { clb_O[3] , clb_O[2] } ) ,
+ .fle_reg_out ( direct_interc_41_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ,
+ .fle_cout ( direct_interc_43_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) ,
+ .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) ,
+ .fle_reg_in ( direct_interc_41_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ,
+ .fle_cin ( direct_interc_43_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) ,
+ .fle_out ( { clb_O[5] , clb_O[4] } ) ,
+ .fle_reg_out ( direct_interc_50_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ,
+ .fle_cout ( direct_interc_52_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) ,
+ .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) , .p2 ( p3 ) ,
+ .p4 ( p5 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) ,
+ .fle_reg_in ( direct_interc_50_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ,
+ .fle_cin ( direct_interc_52_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) ,
+ .fle_out ( { clb_O[7] , clb_O[6] } ) ,
+ .fle_reg_out ( direct_interc_59_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ,
+ .fle_cout ( direct_interc_61_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) ,
+ .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) ,
+ .fle_reg_in ( direct_interc_59_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ,
+ .fle_cin ( direct_interc_61_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) ,
+ .fle_out ( { clb_O[9] , clb_O[8] } ) ,
+ .fle_reg_out ( direct_interc_68_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ,
+ .fle_cout ( direct_interc_70_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) ,
+ .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) ,
+ .p3 ( p4 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) ,
+ .fle_reg_in ( direct_interc_68_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ,
+ .fle_cin ( direct_interc_70_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) ,
+ .fle_out ( { clb_O[11] , clb_O[10] } ) ,
+ .fle_reg_out ( direct_interc_77_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ,
+ .fle_cout ( direct_interc_79_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) ,
+ .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) ,
+ .fle_reg_in ( direct_interc_77_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ,
+ .fle_cin ( direct_interc_79_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) ,
+ .fle_out ( { clb_O[13] , clb_O[12] } ) ,
+ .fle_reg_out ( direct_interc_86_out ) ,
+ .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ,
+ .fle_cout ( direct_interc_88_out ) ,
+ .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) ,
+ .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ;
+grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
+ .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
+ .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) ,
+ .fle_reg_in ( direct_interc_86_out ) ,
+ .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ,
+ .fle_cin ( direct_interc_88_out ) , .fle_reset ( clb_reset ) ,
+ .fle_clk ( clb_clk ) ,
+ .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) ,
+ .fle_out ( { clb_O[15] , clb_O[14] } ) ,
+ .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) ,
+ .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ,
+ .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p1 ) ) ;
+endmodule
+
+
+module grid_clb ( pReset , top_width_0_height_0__pin_0_ ,
+ top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ ,
+ top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ ,
+ top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ ,
+ top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ ,
+ top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ ,
+ top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ ,
+ top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ ,
+ top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ ,
+ top_width_0_height_0__pin_33_ , top_width_0_height_0__pin_34_ ,
+ right_width_0_height_0__pin_16_ , right_width_0_height_0__pin_17_ ,
+ right_width_0_height_0__pin_18_ , right_width_0_height_0__pin_19_ ,
+ right_width_0_height_0__pin_20_ , right_width_0_height_0__pin_21_ ,
+ right_width_0_height_0__pin_22_ , right_width_0_height_0__pin_23_ ,
+ right_width_0_height_0__pin_24_ , right_width_0_height_0__pin_25_ ,
+ right_width_0_height_0__pin_26_ , right_width_0_height_0__pin_27_ ,
+ right_width_0_height_0__pin_28_ , right_width_0_height_0__pin_29_ ,
+ right_width_0_height_0__pin_30_ , right_width_0_height_0__pin_31_ ,
+ Reset , ccff_head , top_width_0_height_0__pin_36_upper ,
+ top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper ,
+ top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper ,
+ top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper ,
+ top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper ,
+ top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper ,
+ top_width_0_height_0__pin_41_lower , top_width_0_height_0__pin_42_upper ,
+ top_width_0_height_0__pin_42_lower , top_width_0_height_0__pin_43_upper ,
+ top_width_0_height_0__pin_43_lower ,
+ right_width_0_height_0__pin_44_upper ,
+ right_width_0_height_0__pin_44_lower ,
+ right_width_0_height_0__pin_45_upper ,
+ right_width_0_height_0__pin_45_lower ,
+ right_width_0_height_0__pin_46_upper ,
+ right_width_0_height_0__pin_46_lower ,
+ right_width_0_height_0__pin_47_upper ,
+ right_width_0_height_0__pin_47_lower ,
+ right_width_0_height_0__pin_48_upper ,
+ right_width_0_height_0__pin_48_lower ,
+ right_width_0_height_0__pin_49_upper ,
+ right_width_0_height_0__pin_49_lower ,
+ right_width_0_height_0__pin_50_upper ,
+ right_width_0_height_0__pin_50_lower ,
+ right_width_0_height_0__pin_51_upper ,
+ right_width_0_height_0__pin_51_lower , bottom_width_0_height_0__pin_52_ ,
+ bottom_width_0_height_0__pin_53_ , bottom_width_0_height_0__pin_54_ ,
+ ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ,
+ Test_en_E_in , Test_en_W_in , Test_en_W_out , Test_en_E_out ,
+ pReset_N_in , Reset_E_in , Reset_W_in , Reset_W_out , Reset_E_out ,
+ prog_clk_0_N_in , prog_clk_0_S_in , prog_clk_0_S_out , prog_clk_0_E_out ,
+ prog_clk_0_W_out , prog_clk_0_N_out , clk_0_N_in , clk_0_S_in ) ;
+input [0:0] pReset ;
+input [0:0] top_width_0_height_0__pin_0_ ;
+input [0:0] top_width_0_height_0__pin_1_ ;
+input [0:0] top_width_0_height_0__pin_2_ ;
+input [0:0] top_width_0_height_0__pin_3_ ;
+input [0:0] top_width_0_height_0__pin_4_ ;
+input [0:0] top_width_0_height_0__pin_5_ ;
+input [0:0] top_width_0_height_0__pin_6_ ;
+input [0:0] top_width_0_height_0__pin_7_ ;
+input [0:0] top_width_0_height_0__pin_8_ ;
+input [0:0] top_width_0_height_0__pin_9_ ;
+input [0:0] top_width_0_height_0__pin_10_ ;
+input [0:0] top_width_0_height_0__pin_11_ ;
+input [0:0] top_width_0_height_0__pin_12_ ;
+input [0:0] top_width_0_height_0__pin_13_ ;
+input [0:0] top_width_0_height_0__pin_14_ ;
+input [0:0] top_width_0_height_0__pin_15_ ;
+input [0:0] top_width_0_height_0__pin_32_ ;
+input [0:0] top_width_0_height_0__pin_33_ ;
+input [0:0] top_width_0_height_0__pin_34_ ;
+input [0:0] right_width_0_height_0__pin_16_ ;
+input [0:0] right_width_0_height_0__pin_17_ ;
+input [0:0] right_width_0_height_0__pin_18_ ;
+input [0:0] right_width_0_height_0__pin_19_ ;
+input [0:0] right_width_0_height_0__pin_20_ ;
+input [0:0] right_width_0_height_0__pin_21_ ;
+input [0:0] right_width_0_height_0__pin_22_ ;
+input [0:0] right_width_0_height_0__pin_23_ ;
+input [0:0] right_width_0_height_0__pin_24_ ;
+input [0:0] right_width_0_height_0__pin_25_ ;
+input [0:0] right_width_0_height_0__pin_26_ ;
+input [0:0] right_width_0_height_0__pin_27_ ;
+input [0:0] right_width_0_height_0__pin_28_ ;
+input [0:0] right_width_0_height_0__pin_29_ ;
+input [0:0] right_width_0_height_0__pin_30_ ;
+input [0:0] right_width_0_height_0__pin_31_ ;
+input [0:0] Reset ;
+input [0:0] ccff_head ;
+output [0:0] top_width_0_height_0__pin_36_upper ;
+output [0:0] top_width_0_height_0__pin_36_lower ;
+output [0:0] top_width_0_height_0__pin_37_upper ;
+output [0:0] top_width_0_height_0__pin_37_lower ;
+output [0:0] top_width_0_height_0__pin_38_upper ;
+output [0:0] top_width_0_height_0__pin_38_lower ;
+output [0:0] top_width_0_height_0__pin_39_upper ;
+output [0:0] top_width_0_height_0__pin_39_lower ;
+output [0:0] top_width_0_height_0__pin_40_upper ;
+output [0:0] top_width_0_height_0__pin_40_lower ;
+output [0:0] top_width_0_height_0__pin_41_upper ;
+output [0:0] top_width_0_height_0__pin_41_lower ;
+output [0:0] top_width_0_height_0__pin_42_upper ;
+output [0:0] top_width_0_height_0__pin_42_lower ;
+output [0:0] top_width_0_height_0__pin_43_upper ;
+output [0:0] top_width_0_height_0__pin_43_lower ;
+output [0:0] right_width_0_height_0__pin_44_upper ;
+output [0:0] right_width_0_height_0__pin_44_lower ;
+output [0:0] right_width_0_height_0__pin_45_upper ;
+output [0:0] right_width_0_height_0__pin_45_lower ;
+output [0:0] right_width_0_height_0__pin_46_upper ;
+output [0:0] right_width_0_height_0__pin_46_lower ;
+output [0:0] right_width_0_height_0__pin_47_upper ;
+output [0:0] right_width_0_height_0__pin_47_lower ;
+output [0:0] right_width_0_height_0__pin_48_upper ;
+output [0:0] right_width_0_height_0__pin_48_lower ;
+output [0:0] right_width_0_height_0__pin_49_upper ;
+output [0:0] right_width_0_height_0__pin_49_lower ;
+output [0:0] right_width_0_height_0__pin_50_upper ;
+output [0:0] right_width_0_height_0__pin_50_lower ;
+output [0:0] right_width_0_height_0__pin_51_upper ;
+output [0:0] right_width_0_height_0__pin_51_lower ;
+output [0:0] bottom_width_0_height_0__pin_52_ ;
+output [0:0] bottom_width_0_height_0__pin_53_ ;
+output [0:0] bottom_width_0_height_0__pin_54_ ;
+output [0:0] ccff_tail ;
+input SC_IN_TOP ;
+input SC_IN_BOT ;
+output SC_OUT_TOP ;
+output SC_OUT_BOT ;
+input Test_en_E_in ;
+input Test_en_W_in ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input pReset_N_in ;
+input Reset_E_in ;
+input Reset_W_in ;
+output Reset_W_out ;
+output Reset_E_out ;
+input prog_clk_0_N_in ;
+input prog_clk_0_S_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_E_out ;
+output prog_clk_0_W_out ;
+output prog_clk_0_N_out ;
+input clk_0_N_in ;
+input clk_0_S_in ;
+
+wire p_abuf12 ;
+wire p_abuf11 ;
+wire p_abuf16 ;
+wire prog_clk_0 ;
+wire [0:0] prog_clk ;
+wire [0:0] clk ;
+wire clk_0 ;
+wire [0:0] Test_en ;
+
+assign SC_IN_BOT = SC_IN_TOP ;
+assign Test_en_W_in = Test_en_E_in ;
+assign Reset_W_in = Reset_E_in ;
+assign prog_clk[0] = prog_clk_0 ;
+assign prog_clk_0_S_in = prog_clk_0_N_in ;
+assign clk_0 = clk[0] ;
+assign clk_0_S_in = clk_0_N_in ;
+
+grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
+ .pReset ( pReset ) ,
+ .prog_clk ( { prog_clk_0 } ) ,
+ .Test_en ( Test_en ) ,
+ .clb_I0 ( { top_width_0_height_0__pin_0_[0] ,
+ top_width_0_height_0__pin_1_[0] } ) ,
+ .clb_I0i ( { top_width_0_height_0__pin_2_[0] ,
+ top_width_0_height_0__pin_3_[0] } ) ,
+ .clb_I1 ( { top_width_0_height_0__pin_4_[0] ,
+ top_width_0_height_0__pin_5_[0] } ) ,
+ .clb_I1i ( { top_width_0_height_0__pin_6_[0] ,
+ top_width_0_height_0__pin_7_[0] } ) ,
+ .clb_I2 ( { top_width_0_height_0__pin_8_[0] ,
+ top_width_0_height_0__pin_9_[0] } ) ,
+ .clb_I2i ( { top_width_0_height_0__pin_10_[0] ,
+ top_width_0_height_0__pin_11_[0] } ) ,
+ .clb_I3 ( { top_width_0_height_0__pin_12_[0] ,
+ top_width_0_height_0__pin_13_[0] } ) ,
+ .clb_I3i ( { top_width_0_height_0__pin_14_[0] ,
+ top_width_0_height_0__pin_15_[0] } ) ,
+ .clb_I4 ( { right_width_0_height_0__pin_16_[0] ,
+ right_width_0_height_0__pin_17_[0] } ) ,
+ .clb_I4i ( { right_width_0_height_0__pin_18_[0] ,
+ right_width_0_height_0__pin_19_[0] } ) ,
+ .clb_I5 ( { right_width_0_height_0__pin_20_[0] ,
+ right_width_0_height_0__pin_21_[0] } ) ,
+ .clb_I5i ( { right_width_0_height_0__pin_22_[0] ,
+ right_width_0_height_0__pin_23_[0] } ) ,
+ .clb_I6 ( { right_width_0_height_0__pin_24_[0] ,
+ right_width_0_height_0__pin_25_[0] } ) ,
+ .clb_I6i ( { right_width_0_height_0__pin_26_[0] ,
+ right_width_0_height_0__pin_27_[0] } ) ,
+ .clb_I7 ( { right_width_0_height_0__pin_28_[0] ,
+ right_width_0_height_0__pin_29_[0] } ) ,
+ .clb_I7i ( { right_width_0_height_0__pin_30_[0] ,
+ right_width_0_height_0__pin_31_[0] } ) ,
+ .clb_reg_in ( top_width_0_height_0__pin_32_ ) ,
+ .clb_sc_in ( { SC_IN_BOT } ) ,
+ .clb_cin ( top_width_0_height_0__pin_34_ ) , .clb_reset ( Reset ) ,
+ .clb_clk ( clk ) , .ccff_head ( ccff_head ) ,
+ .clb_O ( { aps_rename_523_ , aps_rename_524_ , aps_rename_525_ ,
+ aps_rename_526_ , aps_rename_527_ , aps_rename_528_ ,
+ aps_rename_529_ , aps_rename_530_ , aps_rename_531_ ,
+ aps_rename_532_ , right_width_0_height_0__pin_46_lower[0] ,
+ right_width_0_height_0__pin_47_lower[0] , aps_rename_535_ ,
+ aps_rename_536_ , right_width_0_height_0__pin_50_lower[0] ,
+ aps_rename_538_ } ) ,
+ .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) ,
+ .clb_sc_out ( { aps_rename_539_ } ) ,
+ .clb_cout ( bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( ccff_tail ) , .p_abuf0 ( SC_OUT_BOT ) ,
+ .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) ,
+ .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) ,
+ .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) ,
+ .p_abuf4 ( top_width_0_height_0__pin_38_lower[0] ) ,
+ .p_abuf5 ( top_width_0_height_0__pin_41_lower[0] ) ,
+ .p_abuf6 ( top_width_0_height_0__pin_40_lower[0] ) ,
+ .p_abuf7 ( top_width_0_height_0__pin_43_lower[0] ) ,
+ .p_abuf8 ( top_width_0_height_0__pin_42_lower[0] ) ,
+ .p_abuf9 ( right_width_0_height_0__pin_45_lower[0] ) ,
+ .p_abuf10 ( right_width_0_height_0__pin_44_lower[0] ) ,
+ .p_abuf11 ( p_abuf11 ) , .p_abuf12 ( p_abuf12 ) ,
+ .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) ,
+ .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) ,
+ .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) ,
+ .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_180 ) , .p1 ( optlc_net_181 ) ,
+ .p2 ( optlc_net_182 ) , .p3 ( optlc_net_183 ) , .p4 ( optlc_net_184 ) ,
+ .p5 ( optlc_net_185 ) ) ;
+sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) ,
+ .X ( Test_en[0] ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) ,
+ .X ( aps_rename_540_ ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) ,
+ .X ( aps_rename_541_ ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
+sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) ,
+ .X ( aps_rename_542_ ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) ,
+ .X ( aps_rename_543_ ) ) ;
+sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
+ .X ( prog_clk_0 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_1186 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_2187 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_3188 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) ,
+ .X ( ctsbuf_net_4189 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_523_ ) ,
+ .X ( top_width_0_height_0__pin_36_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_524_ ) ,
+ .X ( top_width_0_height_0__pin_37_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_525_ ) ,
+ .X ( top_width_0_height_0__pin_38_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_526_ ) ,
+ .X ( top_width_0_height_0__pin_39_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_527_ ) ,
+ .X ( top_width_0_height_0__pin_40_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_528_ ) ,
+ .X ( top_width_0_height_0__pin_41_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_529_ ) ,
+ .X ( top_width_0_height_0__pin_42_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_530_ ) ,
+ .X ( top_width_0_height_0__pin_43_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_531_ ) ,
+ .X ( right_width_0_height_0__pin_44_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_532_ ) ,
+ .X ( right_width_0_height_0__pin_45_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_75__74 ( .A ( p_abuf12 ) ,
+ .X ( right_width_0_height_0__pin_46_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_76__75 ( .A ( p_abuf11 ) ,
+ .X ( right_width_0_height_0__pin_47_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_535_ ) ,
+ .X ( right_width_0_height_0__pin_48_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_536_ ) ,
+ .X ( right_width_0_height_0__pin_49_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( p_abuf16 ) ,
+ .X ( right_width_0_height_0__pin_50_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_538_ ) ,
+ .X ( right_width_0_height_0__pin_51_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_539_ ) ,
+ .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) ,
+ .Y ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) ,
+ .Y ( BUF_net_135 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) ,
+ .Y ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) ,
+ .Y ( BUF_net_137 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( Reset_W_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_542_ ) ,
+ .Y ( BUF_net_139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) ,
+ .HI ( optlc_net_180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( optlc_net_181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( optlc_net_182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( optlc_net_183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( optlc_net_184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .HI ( optlc_net_185 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_543_ ) ,
+ .X ( Reset_E_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3981326 ( .A ( ctsbuf_net_1186 ) ,
+ .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 cts_buf_4031331 ( .A ( ctsbuf_net_2187 ) ,
+ .X ( prog_clk_0_E_out ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_4081336 ( .A ( ctsbuf_net_3188 ) ,
+ .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4131341 ( .A ( ctsbuf_net_4189 ) ,
+ .X ( prog_clk_0_N_out ) ) ;
+endmodule
+
+
+module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , ccff_head , ccff_tail , sc_head ,
+ sc_tail , h_incr0 , p0 , p1 , p2 , p3 , p4 , p5 , p6 , p7 , p8 , p9 ,
+ p10 , p11 , p12 , p13 , p14 , p15 , p16 , p17 , p18 , p19 , p20 , p21 ,
+ p22 , p23 , p24 , p25 , p26 , p27 , p28 , p29 , p30 , p31 , p32 , p33 ,
+ p34 , p35 , p36 , p37 , p38 , p39 , p40 , p41 , p42 , p43 , p44 , p45 ,
+ p46 , p47 , p48 , p49 , p50 , p51 , p52 , p53 , p54 , p55 , p56 , p57 ,
+ p58 , p59 , p60 , p61 , p62 , p63 , p64 , p65 , p66 , p67 , p68 , p69 ,
+ p70 , p71 , p72 , p73 , p74 , p75 , p76 , p77 , p78 , p79 , p80 , p81 ,
+ p82 , p83 , p84 , p85 , p86 , p87 , p88 , p89 , p90 , p91 , p92 , p93 ,
+ p94 , p95 , p96 , p97 , p98 , p99 , p100 , p101 , p102 , p103 , p104 ,
+ p105 , p106 , p107 , p108 , p109 , p110 , p111 , p112 , p113 , p114 ,
+ p115 , p116 , p117 , p118 , p119 , p120 , p121 , p122 , p123 , p124 ,
+ p125 , p126 , p127 , p128 , p129 , p130 , p131 , p132 , p133 , p134 ,
+ p135 , p136 , p137 , p138 , p139 , p140 , p141 , p142 , p143 , p144 ,
+ p145 , p146 , p147 , p148 , p149 , p150 , p151 , p152 , p153 , p154 ,
+ p155 , p156 , p157 , p158 , p159 , p160 , p161 , p162 , p163 , p164 ,
+ p165 , p166 , p167 , p168 , p169 , p170 , p171 , p172 , p173 , p174 ,
+ p175 , p176 , p177 , p178 , p179 , p180 , p181 , p182 , p183 , p184 ,
+ p185 , p186 , p187 , p188 , p189 , p190 , p191 , p192 , p193 , p194 ,
+ p195 , p196 , p197 , p198 , p199 , p200 , p201 , p202 , p203 , p204 ,
+ p205 , p206 , p207 , p208 , p209 , p210 , p211 , p212 , p213 , p214 ,
+ p215 , p216 , p217 , p218 , p219 , p220 , p221 , p222 , p223 , p224 ,
+ p225 , p226 , p227 , p228 , p229 , p230 , p231 , p232 , p233 , p234 ,
+ p235 , p236 , p237 , p238 , p239 , p240 , p241 , p242 , p243 , p244 ,
+ p245 , p246 , p247 , p248 , p249 , p250 , p251 , p252 , p253 , p254 ,
+ p255 , p256 , p257 , p258 , p259 , p260 , p261 , p262 , p263 , p264 ,
+ p265 , p266 , p267 , p268 , p269 , p270 , p271 , p272 , p273 , p274 ,
+ p275 , p276 , p277 , p278 , p279 , p280 , p281 , p282 , p283 , p284 ,
+ p285 , p286 , p287 , p288 , p289 , p290 , p291 , p292 , p293 , p294 ,
+ p295 , p296 , p297 , p298 , p299 , p300 , p301 , p302 , p303 , p304 ,
+ p305 , p306 , p307 , p308 , p309 , p310 , p311 , p312 , p313 , p314 ,
+ p315 , p316 , p317 , p318 , p319 , p320 , p321 , p322 , p323 , p324 ,
+ p325 , p326 , p327 , p328 , p329 , p330 , p331 , p332 , p333 , p334 ,
+ p335 , p336 , p337 , p338 , p339 , p340 , p341 , p342 , p343 , p344 ,
+ p345 , p346 , p347 , p348 , p349 , p350 , p351 , p352 , p353 , p354 ,
+ p355 , p356 , p357 , p358 , p359 , p360 , p361 , p362 , p363 , p364 ,
+ p365 , p366 , p367 , p368 , p369 , p370 , p371 , p372 , p373 , p374 ,
+ p375 , p376 , p377 , p378 , p379 , p380 , p381 , p382 , p383 , p384 ,
+ p385 , p386 , p387 , p388 , p389 , p390 , p391 , p392 , p393 , p394 ,
+ p395 , p396 , p397 , p398 , p399 , p400 , p401 , p402 , p403 , p404 ,
+ p405 , p406 , p407 , p408 , p409 , p410 , p411 , p412 , p413 , p414 ,
+ p415 , p416 , p417 , p418 , p419 , p420 , p421 , p422 , p423 , p424 ,
+ p425 , p426 , p427 , p428 , p429 , p430 , p431 , p432 , p433 , p434 ,
+ p435 , p436 , p437 , p438 , p439 , p440 , p441 , p442 , p443 , p444 ,
+ p445 , p446 , p447 , p448 , p449 , p450 , p451 , p452 , p453 , p454 ,
+ p455 , p456 , p457 , p458 , p459 , p460 , p461 , p462 , p463 , p464 ,
+ p465 , p466 , p467 , p468 , p469 , p470 , p471 , p472 , p473 , p474 ,
+ p475 , p476 , p477 , p478 , p479 , p480 , p481 , p482 , p483 , p484 ,
+ p485 , p486 , p487 , p488 , p489 , p490 , p491 , p492 , p493 , p494 ,
+ p495 , p496 , p497 , p498 , p499 , p500 , p501 , p502 , p503 , p504 ,
+ p505 , p506 , p507 , p508 , p509 , p510 , p511 , p512 , p513 , p514 ,
+ p515 , p516 , p517 , p518 , p519 , p520 , p521 , p522 , p523 , p524 ,
+ p525 , p526 , p527 , p528 , p529 , p530 , p531 , p532 , p533 , p534 ,
+ p535 , p536 , p537 , p538 , p539 , p540 , p541 , p542 , p543 , p544 ,
+ p545 , p546 , p547 , p548 , p549 , p550 , p551 , p552 , p553 , p554 ,
+ p555 , p556 , p557 , p558 , p559 , p560 , p561 , p562 , p563 , p564 ,
+ p565 , p566 , p567 , p568 , p569 , p570 , p571 , p572 , p573 , p574 ,
+ p575 , p576 , p577 , p578 , p579 , p580 , p581 , p582 , p583 , p584 ,
+ p585 , p586 , p587 , p588 , p589 , p590 , p591 , p592 , p593 , p594 ,
+ p595 , p596 , p597 , p598 , p599 , p600 , p601 , p602 , p603 , p604 ,
+ p605 , p606 , p607 , p608 , p609 , p610 , p611 , p612 , p613 , p614 ,
+ p615 , p616 , p617 , p618 , p619 , p620 , p621 , p622 , p623 , p624 ,
+ p625 , p626 , p627 , p628 , p629 , p630 , p631 , p632 , p633 , p634 ,
+ p635 , p636 , p637 , p638 , p639 , p640 , p641 , p642 , p643 , p644 ,
+ p645 , p646 , p647 , p648 , p649 , p650 , p651 , p652 , p653 , p654 ,
+ p655 , p656 , p657 , p658 , p659 , p660 , p661 , p662 , p663 , p664 ,
+ p665 , p666 , p667 , p668 , p669 , p670 , p671 , p672 , p673 , p674 ,
+ p675 , p676 , p677 , p678 , p679 , p680 , p681 , p682 , p683 , p684 ,
+ p685 , p686 , p687 , p688 , p689 , p690 , p691 , p692 , p693 , p694 ,
+ p695 , p696 , p697 , p698 , p699 , p700 , p701 , p702 , p703 , p704 ,
+ p705 , p706 , p707 , p708 , p709 , p710 , p711 , p712 , p713 , p714 ,
+ p715 , p716 , p717 , p718 , p719 , p720 , p721 , p722 , p723 , p724 ,
+ p725 , p726 , p727 , p728 , p729 , p730 , p731 , p732 , p733 , p734 ,
+ p735 , p736 , p737 , p738 , p739 , p740 , p741 , p742 , p743 , p744 ,
+ p745 , p746 , p747 , p748 , p749 , p750 , p751 , p752 , p753 , p754 ,
+ p755 , p756 , p757 , p758 , p759 , p760 , p761 , p762 , p763 , p764 ,
+ p765 , p766 , p767 , p768 , p769 , p770 , p771 , p772 , p773 , p774 ,
+ p775 , p776 , p777 , p778 , p779 , p780 , p781 , p782 , p783 , p784 ,
+ p785 , p786 , p787 , p788 , p789 , p790 , p791 , p792 , p793 , p794 ,
+ p795 , p796 , p797 , p798 , p799 , p800 , p801 , p802 , p803 , p804 ,
+ p805 , p806 , p807 , p808 , p809 , p810 , p811 , p812 , p813 , p814 ,
+ p815 , p816 , p817 , p818 , p819 , p820 , p821 , p822 , p823 , p824 ,
+ p825 , p826 , p827 , p828 , p829 , p830 , p831 , p832 , p833 , p834 ,
+ p835 , p836 , p837 , p838 , p839 , p840 , p841 , p842 , p843 , p844 ,
+ p845 , p846 , p847 , p848 , p849 , p850 , p851 , p852 , p853 , p854 ,
+ p855 , p856 , p857 , p858 , p859 , p860 , p861 , p862 , p863 , p864 ,
+ p865 , p866 , p867 , p868 , p869 , p870 , p871 , p872 , p873 , p874 ,
+ p875 , p876 , p877 , p878 , p879 , p880 , p881 , p882 , p883 , p884 ,
+ p885 , p886 , p887 , p888 , p889 , p890 , p891 , p892 , p893 , p894 ,
+ p895 , p896 , p897 , p898 , p899 , p900 , p901 , p902 , p903 , p904 ,
+ p905 , p906 , p907 , p908 , p909 , p910 , p911 , p912 , p913 , p914 ,
+ p915 , p916 , p917 , p918 , p919 , p920 , p921 , p922 , p923 , p924 ,
+ p925 , p926 , p927 , p928 , p929 , p930 , p931 , p932 , p933 , p934 ,
+ p935 , p936 , p937 , p938 , p939 , p940 , p941 , p942 , p943 , p944 ,
+ p945 , p946 , p947 , p948 , p949 , p950 , p951 , p952 , p953 , p954 ,
+ p955 , p956 , p957 , p958 , p959 , p960 , p961 , p962 , p963 , p964 ,
+ p965 , p966 , p967 , p968 , p969 , p970 , p971 , p972 , p973 , p974 ,
+ p975 , p976 , p977 , p978 , p979 , p980 , p981 , p982 , p983 , p984 ,
+ p985 , p986 , p987 , p988 , p989 , p990 , p991 , p992 , p993 , p994 ,
+ p995 , p996 , p997 , p998 , p999 , p1000 , p1001 , p1002 , p1003 , p1004 ,
+ p1005 , p1006 , p1007 , p1008 , p1009 , p1010 , p1011 , p1012 , p1013 ,
+ p1014 , p1015 , p1016 , p1017 , p1018 , p1019 , p1020 , p1021 , p1022 ,
+ p1023 , p1024 , p1025 , p1026 , p1027 , p1028 , p1029 , p1030 , p1031 ,
+ p1032 , p1033 , p1034 , p1035 , p1036 , p1037 , p1038 , p1039 , p1040 ,
+ p1041 , p1042 , p1043 , p1044 , p1045 , p1046 , p1047 , p1048 , p1049 ,
+ p1050 , p1051 , p1052 , p1053 , p1054 , p1055 , p1056 , p1057 , p1058 ,
+ p1059 , p1060 , p1061 , p1062 , p1063 , p1064 , p1065 , p1066 , p1067 ,
+ p1068 , p1069 , p1070 , p1071 , p1072 , p1073 , p1074 , p1075 , p1076 ,
+ p1077 , p1078 , p1079 , p1080 , p1081 , p1082 , p1083 , p1084 , p1085 ,
+ p1086 , p1087 , p1088 , p1089 , p1090 , p1091 , p1092 , p1093 , p1094 ,
+ p1095 , p1096 , p1097 , p1098 , p1099 , p1100 , p1101 , p1102 , p1103 ,
+ p1104 , p1105 , p1106 , p1107 , p1108 , p1109 , p1110 , p1111 , p1112 ,
+ p1113 , p1114 , p1115 , p1116 , p1117 , p1118 , p1119 , p1120 , p1121 ,
+ p1122 , p1123 , p1124 , p1125 , p1126 , p1127 , p1128 , p1129 , p1130 ,
+ p1131 , p1132 , p1133 , p1134 , p1135 , p1136 , p1137 , p1138 , p1139 ,
+ p1140 , p1141 , p1142 , p1143 , p1144 , p1145 , p1146 , p1147 , p1148 ,
+ p1149 , p1150 , p1151 , p1152 , p1153 , p1154 , p1155 , p1156 , p1157 ,
+ p1158 , p1159 , p1160 , p1161 , p1162 , p1163 , p1164 , p1165 , p1166 ,
+ p1167 , p1168 , p1169 , p1170 , p1171 , p1172 , p1173 , p1174 , p1175 ,
+ p1176 , p1177 , p1178 , p1179 , p1180 , p1181 , p1182 , p1183 , p1184 ,
+ p1185 , p1186 , p1187 , p1188 , p1189 , p1190 , p1191 , p1192 , p1193 ,
+ p1194 , p1195 , p1196 , p1197 , p1198 , p1199 , p1200 , p1201 , p1202 ,
+ p1203 , p1204 , p1205 , p1206 , p1207 , p1208 , p1209 , p1210 , p1211 ,
+ p1212 , p1213 , p1214 , p1215 , p1216 , p1217 , p1218 , p1219 , p1220 ,
+ p1221 , p1222 , p1223 , p1224 , p1225 , p1226 , p1227 , p1228 , p1229 ,
+ p1230 , p1231 , p1232 , p1233 , p1234 , p1235 , p1236 , p1237 , p1238 ,
+ p1239 , p1240 , p1241 , p1242 , p1243 , p1244 , p1245 , p1246 , p1247 ,
+ p1248 , p1249 , p1250 , p1251 , p1252 , p1253 , p1254 , p1255 , p1256 ,
+ p1257 , p1258 , p1259 , p1260 , p1261 , p1262 , p1263 , p1264 , p1265 ,
+ p1266 , p1267 , p1268 , p1269 , p1270 , p1271 , p1272 , p1273 , p1274 ,
+ p1275 , p1276 , p1277 , p1278 , p1279 , p1280 , p1281 , p1282 , p1283 ,
+ p1284 , p1285 , p1286 , p1287 , p1288 , p1289 , p1290 , p1291 , p1292 ,
+ p1293 , p1294 , p1295 , p1296 , p1297 , p1298 , p1299 , p1300 , p1301 ,
+ p1302 , p1303 , p1304 , p1305 , p1306 , p1307 , p1308 , p1309 , p1310 ,
+ p1311 , p1312 , p1313 , p1314 , p1315 , p1316 , p1317 , p1318 , p1319 ,
+ p1320 , p1321 , p1322 , p1323 , p1324 , p1325 , p1326 , p1327 , p1328 ,
+ p1329 , p1330 , p1331 , p1332 , p1333 , p1334 , p1335 , p1336 , p1337 ,
+ p1338 , p1339 , p1340 , p1341 , p1342 , p1343 , p1344 , p1345 , p1346 ,
+ p1347 , p1348 , p1349 , p1350 , p1351 , p1352 , p1353 , p1354 , p1355 ,
+ p1356 , p1357 , p1358 , p1359 , p1360 , p1361 , p1362 , p1363 , p1364 ,
+ p1365 , p1366 , p1367 , p1368 , p1369 , p1370 , p1371 , p1372 , p1373 ,
+ p1374 , p1375 , p1376 , p1377 , p1378 , p1379 , p1380 , p1381 , p1382 ,
+ p1383 , p1384 , p1385 , p1386 , p1387 , p1388 , p1389 , p1390 , p1391 ,
+ p1392 , p1393 , p1394 , p1395 , p1396 , p1397 , p1398 , p1399 , p1400 ,
+ p1401 , p1402 , p1403 , p1404 , p1405 , p1406 , p1407 , p1408 , p1409 ,
+ p1410 , p1411 , p1412 , p1413 , p1414 , p1415 , p1416 , p1417 , p1418 ,
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+ p1806 , p1807 , p1808 , p1809 , p1810 , p1811 , p1812 , p1813 , p1814 ,
+ p1815 , p1816 , p1817 , p1818 , p1819 , p1820 , p1821 , p1822 , p1823 ,
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+ p3291 , p3292 , p3293 , p3294 , p3295 , p3296 , p3297 , p3298 , p3299 ,
+ p3300 , p3301 , p3302 , p3303 , p3304 , p3305 , p3306 , p3307 , p3308 ,
+ p3309 , p3310 , p3311 , p3312 , p3313 , p3314 , p3315 , p3316 , p3317 ,
+ p3318 , p3319 , p3320 , p3321 , p3322 , p3323 , p3324 , p3325 , p3326 ,
+ p3327 , p3328 , p3329 , p3330 , p3331 , p3332 , p3333 , p3334 , p3335 ,
+ p3336 , p3337 , p3338 , p3339 , p3340 , p3341 , p3342 , p3343 , p3344 ,
+ p3345 , p3346 , p3347 , p3348 , p3349 , p3350 , p3351 , p3352 , p3353 ,
+ p3354 , p3355 , p3356 , p3357 , p3358 , p3359 , p3360 , p3361 , p3362 ,
+ p3363 , p3364 , p3365 , p3366 , p3367 , p3368 , p3369 , p3370 , p3371 ,
+ p3372 , p3373 , p3374 , p3375 , p3376 , p3377 , p3378 , p3379 , p3380 ,
+ p3381 , p3382 , p3383 , p3384 , p3385 , p3386 , p3387 , p3388 , p3389 ,
+ p3390 , p3391 , p3392 , p3393 , p3394 , p3395 , p3396 , p3397 , p3398 ,
+ p3399 , p3400 , p3401 , p3402 , p3403 , p3404 , p3405 , p3406 , p3407 ,
+ p3408 , p3409 , p3410 , p3411 , p3412 , p3413 , p3414 , p3415 , p3416 ,
+ p3417 , p3418 , p3419 , p3420 , p3421 , p3422 , p3423 , p3424 , p3425 ,
+ p3426 , p3427 , p3428 , p3429 , p3430 , p3431 , p3432 , p3433 , p3434 ,
+ p3435 , p3436 , p3437 , p3438 , p3439 , p3440 , p3441 , p3442 , p3443 ,
+ p3444 , p3445 , p3446 , p3447 , p3448 , p3449 , p3450 , p3451 , p3452 ,
+ p3453 , p3454 , p3455 , p3456 , p3457 , p3458 , p3459 , p3460 , p3461 ,
+ p3462 , p3463 , p3464 , p3465 , p3466 , p3467 , p3468 , p3469 , p3470 ,
+ p3471 , p3472 , p3473 , p3474 , p3475 , p3476 , p3477 , p3478 , p3479 ,
+ p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , p3487 , p3488 ,
+ p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , p3496 , p3497 ,
+ p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , p3505 , p3506 ,
+ p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , p3514 , p3515 ,
+ p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 , p3523 , p3524 ,
+ p3525 , p3526 , p3527 , p3528 , p3529 , p3530 , p3531 , p3532 , p3533 ,
+ p3534 , p3535 , p3536 , p3537 , p3538 , p3539 , p3540 , p3541 , p3542 ,
+ p3543 , p3544 , p3545 , p3546 , p3547 , p3548 , p3549 , p3550 , p3551 ,
+ p3552 , p3553 , p3554 , p3555 , p3556 , p3557 , p3558 , p3559 , p3560 ,
+ p3561 , p3562 , p3563 , p3564 , p3565 , p3566 , p3567 , p3568 , p3569 ,
+ p3570 , p3571 , p3572 , p3573 , p3574 , p3575 , p3576 , p3577 , p3578 ,
+ p3579 , p3580 , p3581 , p3582 , p3583 , p3584 , p3585 , p3586 , p3587 ,
+ p3588 , p3589 , p3590 , p3591 , p3592 , p3593 , p3594 , p3595 , p3596 ,
+ p3597 , p3598 , p3599 , p3600 , p3601 , p3602 , p3603 , p3604 , p3605 ,
+ p3606 , p3607 , p3608 , p3609 , p3610 , p3611 , p3612 , p3613 , p3614 ,
+ p3615 , p3616 , p3617 , p3618 , p3619 , p3620 , p3621 , p3622 , p3623 ,
+ p3624 , p3625 , p3626 , p3627 , p3628 , p3629 , p3630 , p3631 , p3632 ,
+ p3633 , p3634 , p3635 , p3636 , p3637 , p3638 , p3639 , p3640 , p3641 ,
+ p3642 , p3643 , p3644 , p3645 , p3646 , p3647 , p3648 , p3649 , p3650 ,
+ p3651 , p3652 , p3653 , p3654 , p3655 , p3656 , p3657 , p3658 , p3659 ,
+ p3660 , p3661 , p3662 , p3663 , p3664 , p3665 , p3666 , p3667 , p3668 ,
+ p3669 , p3670 , p3671 , p3672 , p3673 , p3674 , p3675 , p3676 , p3677 ,
+ p3678 ) ;
+input [0:0] pReset ;
+input [0:0] prog_clk ;
+input [0:0] Test_en ;
+input [0:0] IO_ISOL_N ;
+input [0:0] clk ;
+input [0:0] Reset ;
+input [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+input sc_head ;
+output sc_tail ;
+input h_incr0 ;
+input p0 ;
+input p1 ;
+input p2 ;
+input p3 ;
+input p4 ;
+input p5 ;
+input p6 ;
+input p7 ;
+input p8 ;
+input p9 ;
+input p10 ;
+input p11 ;
+input p12 ;
+input p13 ;
+input p14 ;
+input p15 ;
+input p16 ;
+input p17 ;
+input p18 ;
+input p19 ;
+input p20 ;
+input p21 ;
+input p22 ;
+input p23 ;
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+input p25 ;
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+input p30 ;
+input p31 ;
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+
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+wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__0_ccff_tail ;
+wire [0:29] cbx_1__0__0_chanx_left_out ;
+wire [0:29] cbx_1__0__0_chanx_right_out ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__10_ccff_tail ;
+wire [0:29] cbx_1__0__10_chanx_left_out ;
+wire [0:29] cbx_1__0__10_chanx_right_out ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__11_ccff_tail ;
+wire [0:29] cbx_1__0__11_chanx_left_out ;
+wire [0:29] cbx_1__0__11_chanx_right_out ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__1_ccff_tail ;
+wire [0:29] cbx_1__0__1_chanx_left_out ;
+wire [0:29] cbx_1__0__1_chanx_right_out ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__2_ccff_tail ;
+wire [0:29] cbx_1__0__2_chanx_left_out ;
+wire [0:29] cbx_1__0__2_chanx_right_out ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__3_ccff_tail ;
+wire [0:29] cbx_1__0__3_chanx_left_out ;
+wire [0:29] cbx_1__0__3_chanx_right_out ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__4_ccff_tail ;
+wire [0:29] cbx_1__0__4_chanx_left_out ;
+wire [0:29] cbx_1__0__4_chanx_right_out ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__5_ccff_tail ;
+wire [0:29] cbx_1__0__5_chanx_left_out ;
+wire [0:29] cbx_1__0__5_chanx_right_out ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__6_ccff_tail ;
+wire [0:29] cbx_1__0__6_chanx_left_out ;
+wire [0:29] cbx_1__0__6_chanx_right_out ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__7_ccff_tail ;
+wire [0:29] cbx_1__0__7_chanx_left_out ;
+wire [0:29] cbx_1__0__7_chanx_right_out ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__8_ccff_tail ;
+wire [0:29] cbx_1__0__8_chanx_left_out ;
+wire [0:29] cbx_1__0__8_chanx_right_out ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_16_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__0__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__0__9_ccff_tail ;
+wire [0:29] cbx_1__0__9_chanx_left_out ;
+wire [0:29] cbx_1__0__9_chanx_right_out ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__0_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__0_ccff_tail ;
+wire [0:29] cbx_1__12__0_chanx_left_out ;
+wire [0:29] cbx_1__12__0_chanx_right_out ;
+wire [0:0] cbx_1__12__0_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__10_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__10_ccff_tail ;
+wire [0:29] cbx_1__12__10_chanx_left_out ;
+wire [0:29] cbx_1__12__10_chanx_right_out ;
+wire [0:0] cbx_1__12__10_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__11_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__11_ccff_tail ;
+wire [0:29] cbx_1__12__11_chanx_left_out ;
+wire [0:29] cbx_1__12__11_chanx_right_out ;
+wire [0:0] cbx_1__12__11_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__1_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__1_ccff_tail ;
+wire [0:29] cbx_1__12__1_chanx_left_out ;
+wire [0:29] cbx_1__12__1_chanx_right_out ;
+wire [0:0] cbx_1__12__1_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__2_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__2_ccff_tail ;
+wire [0:29] cbx_1__12__2_chanx_left_out ;
+wire [0:29] cbx_1__12__2_chanx_right_out ;
+wire [0:0] cbx_1__12__2_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__3_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__3_ccff_tail ;
+wire [0:29] cbx_1__12__3_chanx_left_out ;
+wire [0:29] cbx_1__12__3_chanx_right_out ;
+wire [0:0] cbx_1__12__3_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__4_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__4_ccff_tail ;
+wire [0:29] cbx_1__12__4_chanx_left_out ;
+wire [0:29] cbx_1__12__4_chanx_right_out ;
+wire [0:0] cbx_1__12__4_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__5_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__5_ccff_tail ;
+wire [0:29] cbx_1__12__5_chanx_left_out ;
+wire [0:29] cbx_1__12__5_chanx_right_out ;
+wire [0:0] cbx_1__12__5_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__6_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__6_ccff_tail ;
+wire [0:29] cbx_1__12__6_chanx_left_out ;
+wire [0:29] cbx_1__12__6_chanx_right_out ;
+wire [0:0] cbx_1__12__6_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__7_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__7_ccff_tail ;
+wire [0:29] cbx_1__12__7_chanx_left_out ;
+wire [0:29] cbx_1__12__7_chanx_right_out ;
+wire [0:0] cbx_1__12__7_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__8_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__8_ccff_tail ;
+wire [0:29] cbx_1__12__8_chanx_left_out ;
+wire [0:29] cbx_1__12__8_chanx_right_out ;
+wire [0:0] cbx_1__12__8_top_grid_pin_0_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__12__9_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__12__9_ccff_tail ;
+wire [0:29] cbx_1__12__9_chanx_left_out ;
+wire [0:29] cbx_1__12__9_chanx_right_out ;
+wire [0:0] cbx_1__12__9_top_grid_pin_0_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__0_ccff_tail ;
+wire [0:29] cbx_1__1__0_chanx_left_out ;
+wire [0:29] cbx_1__1__0_chanx_right_out ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__100_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__100_ccff_tail ;
+wire [0:29] cbx_1__1__100_chanx_left_out ;
+wire [0:29] cbx_1__1__100_chanx_right_out ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__101_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__101_ccff_tail ;
+wire [0:29] cbx_1__1__101_chanx_left_out ;
+wire [0:29] cbx_1__1__101_chanx_right_out ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__102_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__102_ccff_tail ;
+wire [0:29] cbx_1__1__102_chanx_left_out ;
+wire [0:29] cbx_1__1__102_chanx_right_out ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__103_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__103_ccff_tail ;
+wire [0:29] cbx_1__1__103_chanx_left_out ;
+wire [0:29] cbx_1__1__103_chanx_right_out ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__104_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__104_ccff_tail ;
+wire [0:29] cbx_1__1__104_chanx_left_out ;
+wire [0:29] cbx_1__1__104_chanx_right_out ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__105_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__105_ccff_tail ;
+wire [0:29] cbx_1__1__105_chanx_left_out ;
+wire [0:29] cbx_1__1__105_chanx_right_out ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__106_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__106_ccff_tail ;
+wire [0:29] cbx_1__1__106_chanx_left_out ;
+wire [0:29] cbx_1__1__106_chanx_right_out ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__107_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__107_ccff_tail ;
+wire [0:29] cbx_1__1__107_chanx_left_out ;
+wire [0:29] cbx_1__1__107_chanx_right_out ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__108_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__108_ccff_tail ;
+wire [0:29] cbx_1__1__108_chanx_left_out ;
+wire [0:29] cbx_1__1__108_chanx_right_out ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__109_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__109_ccff_tail ;
+wire [0:29] cbx_1__1__109_chanx_left_out ;
+wire [0:29] cbx_1__1__109_chanx_right_out ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__10_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__10_ccff_tail ;
+wire [0:29] cbx_1__1__10_chanx_left_out ;
+wire [0:29] cbx_1__1__10_chanx_right_out ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__110_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__110_ccff_tail ;
+wire [0:29] cbx_1__1__110_chanx_left_out ;
+wire [0:29] cbx_1__1__110_chanx_right_out ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__111_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__111_ccff_tail ;
+wire [0:29] cbx_1__1__111_chanx_left_out ;
+wire [0:29] cbx_1__1__111_chanx_right_out ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__112_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__112_ccff_tail ;
+wire [0:29] cbx_1__1__112_chanx_left_out ;
+wire [0:29] cbx_1__1__112_chanx_right_out ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__113_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__113_ccff_tail ;
+wire [0:29] cbx_1__1__113_chanx_left_out ;
+wire [0:29] cbx_1__1__113_chanx_right_out ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__114_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__114_ccff_tail ;
+wire [0:29] cbx_1__1__114_chanx_left_out ;
+wire [0:29] cbx_1__1__114_chanx_right_out ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__115_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__115_ccff_tail ;
+wire [0:29] cbx_1__1__115_chanx_left_out ;
+wire [0:29] cbx_1__1__115_chanx_right_out ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__116_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__116_ccff_tail ;
+wire [0:29] cbx_1__1__116_chanx_left_out ;
+wire [0:29] cbx_1__1__116_chanx_right_out ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__117_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__117_ccff_tail ;
+wire [0:29] cbx_1__1__117_chanx_left_out ;
+wire [0:29] cbx_1__1__117_chanx_right_out ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__118_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__118_ccff_tail ;
+wire [0:29] cbx_1__1__118_chanx_left_out ;
+wire [0:29] cbx_1__1__118_chanx_right_out ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__119_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__119_ccff_tail ;
+wire [0:29] cbx_1__1__119_chanx_left_out ;
+wire [0:29] cbx_1__1__119_chanx_right_out ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__11_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__11_ccff_tail ;
+wire [0:29] cbx_1__1__11_chanx_left_out ;
+wire [0:29] cbx_1__1__11_chanx_right_out ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__120_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__120_ccff_tail ;
+wire [0:29] cbx_1__1__120_chanx_left_out ;
+wire [0:29] cbx_1__1__120_chanx_right_out ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__121_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__121_ccff_tail ;
+wire [0:29] cbx_1__1__121_chanx_left_out ;
+wire [0:29] cbx_1__1__121_chanx_right_out ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__122_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__122_ccff_tail ;
+wire [0:29] cbx_1__1__122_chanx_left_out ;
+wire [0:29] cbx_1__1__122_chanx_right_out ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__123_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__123_ccff_tail ;
+wire [0:29] cbx_1__1__123_chanx_left_out ;
+wire [0:29] cbx_1__1__123_chanx_right_out ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__124_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__124_ccff_tail ;
+wire [0:29] cbx_1__1__124_chanx_left_out ;
+wire [0:29] cbx_1__1__124_chanx_right_out ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__125_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__125_ccff_tail ;
+wire [0:29] cbx_1__1__125_chanx_left_out ;
+wire [0:29] cbx_1__1__125_chanx_right_out ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__126_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__126_ccff_tail ;
+wire [0:29] cbx_1__1__126_chanx_left_out ;
+wire [0:29] cbx_1__1__126_chanx_right_out ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__127_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__127_ccff_tail ;
+wire [0:29] cbx_1__1__127_chanx_left_out ;
+wire [0:29] cbx_1__1__127_chanx_right_out ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__128_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__128_ccff_tail ;
+wire [0:29] cbx_1__1__128_chanx_left_out ;
+wire [0:29] cbx_1__1__128_chanx_right_out ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__129_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__129_ccff_tail ;
+wire [0:29] cbx_1__1__129_chanx_left_out ;
+wire [0:29] cbx_1__1__129_chanx_right_out ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__12_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__12_ccff_tail ;
+wire [0:29] cbx_1__1__12_chanx_left_out ;
+wire [0:29] cbx_1__1__12_chanx_right_out ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__130_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__130_ccff_tail ;
+wire [0:29] cbx_1__1__130_chanx_left_out ;
+wire [0:29] cbx_1__1__130_chanx_right_out ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__131_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__131_ccff_tail ;
+wire [0:29] cbx_1__1__131_chanx_left_out ;
+wire [0:29] cbx_1__1__131_chanx_right_out ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__13_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__13_ccff_tail ;
+wire [0:29] cbx_1__1__13_chanx_left_out ;
+wire [0:29] cbx_1__1__13_chanx_right_out ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__14_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__14_ccff_tail ;
+wire [0:29] cbx_1__1__14_chanx_left_out ;
+wire [0:29] cbx_1__1__14_chanx_right_out ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__15_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__15_ccff_tail ;
+wire [0:29] cbx_1__1__15_chanx_left_out ;
+wire [0:29] cbx_1__1__15_chanx_right_out ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__16_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__16_ccff_tail ;
+wire [0:29] cbx_1__1__16_chanx_left_out ;
+wire [0:29] cbx_1__1__16_chanx_right_out ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__17_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__17_ccff_tail ;
+wire [0:29] cbx_1__1__17_chanx_left_out ;
+wire [0:29] cbx_1__1__17_chanx_right_out ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__18_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__18_ccff_tail ;
+wire [0:29] cbx_1__1__18_chanx_left_out ;
+wire [0:29] cbx_1__1__18_chanx_right_out ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__19_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__19_ccff_tail ;
+wire [0:29] cbx_1__1__19_chanx_left_out ;
+wire [0:29] cbx_1__1__19_chanx_right_out ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__1_ccff_tail ;
+wire [0:29] cbx_1__1__1_chanx_left_out ;
+wire [0:29] cbx_1__1__1_chanx_right_out ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__20_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__20_ccff_tail ;
+wire [0:29] cbx_1__1__20_chanx_left_out ;
+wire [0:29] cbx_1__1__20_chanx_right_out ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__21_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__21_ccff_tail ;
+wire [0:29] cbx_1__1__21_chanx_left_out ;
+wire [0:29] cbx_1__1__21_chanx_right_out ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__22_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__22_ccff_tail ;
+wire [0:29] cbx_1__1__22_chanx_left_out ;
+wire [0:29] cbx_1__1__22_chanx_right_out ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__23_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__23_ccff_tail ;
+wire [0:29] cbx_1__1__23_chanx_left_out ;
+wire [0:29] cbx_1__1__23_chanx_right_out ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__24_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__24_ccff_tail ;
+wire [0:29] cbx_1__1__24_chanx_left_out ;
+wire [0:29] cbx_1__1__24_chanx_right_out ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__25_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__25_ccff_tail ;
+wire [0:29] cbx_1__1__25_chanx_left_out ;
+wire [0:29] cbx_1__1__25_chanx_right_out ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__26_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__26_ccff_tail ;
+wire [0:29] cbx_1__1__26_chanx_left_out ;
+wire [0:29] cbx_1__1__26_chanx_right_out ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__27_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__27_ccff_tail ;
+wire [0:29] cbx_1__1__27_chanx_left_out ;
+wire [0:29] cbx_1__1__27_chanx_right_out ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__28_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__28_ccff_tail ;
+wire [0:29] cbx_1__1__28_chanx_left_out ;
+wire [0:29] cbx_1__1__28_chanx_right_out ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__29_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__29_ccff_tail ;
+wire [0:29] cbx_1__1__29_chanx_left_out ;
+wire [0:29] cbx_1__1__29_chanx_right_out ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__2_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__2_ccff_tail ;
+wire [0:29] cbx_1__1__2_chanx_left_out ;
+wire [0:29] cbx_1__1__2_chanx_right_out ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__30_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__30_ccff_tail ;
+wire [0:29] cbx_1__1__30_chanx_left_out ;
+wire [0:29] cbx_1__1__30_chanx_right_out ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__31_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__31_ccff_tail ;
+wire [0:29] cbx_1__1__31_chanx_left_out ;
+wire [0:29] cbx_1__1__31_chanx_right_out ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__32_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__32_ccff_tail ;
+wire [0:29] cbx_1__1__32_chanx_left_out ;
+wire [0:29] cbx_1__1__32_chanx_right_out ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__33_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__33_ccff_tail ;
+wire [0:29] cbx_1__1__33_chanx_left_out ;
+wire [0:29] cbx_1__1__33_chanx_right_out ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__34_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__34_ccff_tail ;
+wire [0:29] cbx_1__1__34_chanx_left_out ;
+wire [0:29] cbx_1__1__34_chanx_right_out ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__35_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__35_ccff_tail ;
+wire [0:29] cbx_1__1__35_chanx_left_out ;
+wire [0:29] cbx_1__1__35_chanx_right_out ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__36_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__36_ccff_tail ;
+wire [0:29] cbx_1__1__36_chanx_left_out ;
+wire [0:29] cbx_1__1__36_chanx_right_out ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__37_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__37_ccff_tail ;
+wire [0:29] cbx_1__1__37_chanx_left_out ;
+wire [0:29] cbx_1__1__37_chanx_right_out ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__38_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__38_ccff_tail ;
+wire [0:29] cbx_1__1__38_chanx_left_out ;
+wire [0:29] cbx_1__1__38_chanx_right_out ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__39_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__39_ccff_tail ;
+wire [0:29] cbx_1__1__39_chanx_left_out ;
+wire [0:29] cbx_1__1__39_chanx_right_out ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__3_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__3_ccff_tail ;
+wire [0:29] cbx_1__1__3_chanx_left_out ;
+wire [0:29] cbx_1__1__3_chanx_right_out ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__40_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__40_ccff_tail ;
+wire [0:29] cbx_1__1__40_chanx_left_out ;
+wire [0:29] cbx_1__1__40_chanx_right_out ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__41_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__41_ccff_tail ;
+wire [0:29] cbx_1__1__41_chanx_left_out ;
+wire [0:29] cbx_1__1__41_chanx_right_out ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__42_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__42_ccff_tail ;
+wire [0:29] cbx_1__1__42_chanx_left_out ;
+wire [0:29] cbx_1__1__42_chanx_right_out ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__43_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__43_ccff_tail ;
+wire [0:29] cbx_1__1__43_chanx_left_out ;
+wire [0:29] cbx_1__1__43_chanx_right_out ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__44_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__44_ccff_tail ;
+wire [0:29] cbx_1__1__44_chanx_left_out ;
+wire [0:29] cbx_1__1__44_chanx_right_out ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__45_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__45_ccff_tail ;
+wire [0:29] cbx_1__1__45_chanx_left_out ;
+wire [0:29] cbx_1__1__45_chanx_right_out ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__46_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__46_ccff_tail ;
+wire [0:29] cbx_1__1__46_chanx_left_out ;
+wire [0:29] cbx_1__1__46_chanx_right_out ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__47_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__47_ccff_tail ;
+wire [0:29] cbx_1__1__47_chanx_left_out ;
+wire [0:29] cbx_1__1__47_chanx_right_out ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__48_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__48_ccff_tail ;
+wire [0:29] cbx_1__1__48_chanx_left_out ;
+wire [0:29] cbx_1__1__48_chanx_right_out ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__49_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__49_ccff_tail ;
+wire [0:29] cbx_1__1__49_chanx_left_out ;
+wire [0:29] cbx_1__1__49_chanx_right_out ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__4_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__4_ccff_tail ;
+wire [0:29] cbx_1__1__4_chanx_left_out ;
+wire [0:29] cbx_1__1__4_chanx_right_out ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__50_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__50_ccff_tail ;
+wire [0:29] cbx_1__1__50_chanx_left_out ;
+wire [0:29] cbx_1__1__50_chanx_right_out ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__51_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__51_ccff_tail ;
+wire [0:29] cbx_1__1__51_chanx_left_out ;
+wire [0:29] cbx_1__1__51_chanx_right_out ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__52_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__52_ccff_tail ;
+wire [0:29] cbx_1__1__52_chanx_left_out ;
+wire [0:29] cbx_1__1__52_chanx_right_out ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__53_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__53_ccff_tail ;
+wire [0:29] cbx_1__1__53_chanx_left_out ;
+wire [0:29] cbx_1__1__53_chanx_right_out ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__54_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__54_ccff_tail ;
+wire [0:29] cbx_1__1__54_chanx_left_out ;
+wire [0:29] cbx_1__1__54_chanx_right_out ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__55_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__55_ccff_tail ;
+wire [0:29] cbx_1__1__55_chanx_left_out ;
+wire [0:29] cbx_1__1__55_chanx_right_out ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__56_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__56_ccff_tail ;
+wire [0:29] cbx_1__1__56_chanx_left_out ;
+wire [0:29] cbx_1__1__56_chanx_right_out ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__57_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__57_ccff_tail ;
+wire [0:29] cbx_1__1__57_chanx_left_out ;
+wire [0:29] cbx_1__1__57_chanx_right_out ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__58_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__58_ccff_tail ;
+wire [0:29] cbx_1__1__58_chanx_left_out ;
+wire [0:29] cbx_1__1__58_chanx_right_out ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__59_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__59_ccff_tail ;
+wire [0:29] cbx_1__1__59_chanx_left_out ;
+wire [0:29] cbx_1__1__59_chanx_right_out ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__5_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__5_ccff_tail ;
+wire [0:29] cbx_1__1__5_chanx_left_out ;
+wire [0:29] cbx_1__1__5_chanx_right_out ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__60_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__60_ccff_tail ;
+wire [0:29] cbx_1__1__60_chanx_left_out ;
+wire [0:29] cbx_1__1__60_chanx_right_out ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__61_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__61_ccff_tail ;
+wire [0:29] cbx_1__1__61_chanx_left_out ;
+wire [0:29] cbx_1__1__61_chanx_right_out ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__62_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__62_ccff_tail ;
+wire [0:29] cbx_1__1__62_chanx_left_out ;
+wire [0:29] cbx_1__1__62_chanx_right_out ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__63_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__63_ccff_tail ;
+wire [0:29] cbx_1__1__63_chanx_left_out ;
+wire [0:29] cbx_1__1__63_chanx_right_out ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__64_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__64_ccff_tail ;
+wire [0:29] cbx_1__1__64_chanx_left_out ;
+wire [0:29] cbx_1__1__64_chanx_right_out ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__65_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__65_ccff_tail ;
+wire [0:29] cbx_1__1__65_chanx_left_out ;
+wire [0:29] cbx_1__1__65_chanx_right_out ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__66_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__66_ccff_tail ;
+wire [0:29] cbx_1__1__66_chanx_left_out ;
+wire [0:29] cbx_1__1__66_chanx_right_out ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__67_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__67_ccff_tail ;
+wire [0:29] cbx_1__1__67_chanx_left_out ;
+wire [0:29] cbx_1__1__67_chanx_right_out ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__68_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__68_ccff_tail ;
+wire [0:29] cbx_1__1__68_chanx_left_out ;
+wire [0:29] cbx_1__1__68_chanx_right_out ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__69_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__69_ccff_tail ;
+wire [0:29] cbx_1__1__69_chanx_left_out ;
+wire [0:29] cbx_1__1__69_chanx_right_out ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__6_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__6_ccff_tail ;
+wire [0:29] cbx_1__1__6_chanx_left_out ;
+wire [0:29] cbx_1__1__6_chanx_right_out ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__70_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__70_ccff_tail ;
+wire [0:29] cbx_1__1__70_chanx_left_out ;
+wire [0:29] cbx_1__1__70_chanx_right_out ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__71_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__71_ccff_tail ;
+wire [0:29] cbx_1__1__71_chanx_left_out ;
+wire [0:29] cbx_1__1__71_chanx_right_out ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__72_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__72_ccff_tail ;
+wire [0:29] cbx_1__1__72_chanx_left_out ;
+wire [0:29] cbx_1__1__72_chanx_right_out ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__73_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__73_ccff_tail ;
+wire [0:29] cbx_1__1__73_chanx_left_out ;
+wire [0:29] cbx_1__1__73_chanx_right_out ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__74_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__74_ccff_tail ;
+wire [0:29] cbx_1__1__74_chanx_left_out ;
+wire [0:29] cbx_1__1__74_chanx_right_out ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__75_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__75_ccff_tail ;
+wire [0:29] cbx_1__1__75_chanx_left_out ;
+wire [0:29] cbx_1__1__75_chanx_right_out ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__76_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__76_ccff_tail ;
+wire [0:29] cbx_1__1__76_chanx_left_out ;
+wire [0:29] cbx_1__1__76_chanx_right_out ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__77_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__77_ccff_tail ;
+wire [0:29] cbx_1__1__77_chanx_left_out ;
+wire [0:29] cbx_1__1__77_chanx_right_out ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__78_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__78_ccff_tail ;
+wire [0:29] cbx_1__1__78_chanx_left_out ;
+wire [0:29] cbx_1__1__78_chanx_right_out ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__79_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__79_ccff_tail ;
+wire [0:29] cbx_1__1__79_chanx_left_out ;
+wire [0:29] cbx_1__1__79_chanx_right_out ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__7_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__7_ccff_tail ;
+wire [0:29] cbx_1__1__7_chanx_left_out ;
+wire [0:29] cbx_1__1__7_chanx_right_out ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__80_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__80_ccff_tail ;
+wire [0:29] cbx_1__1__80_chanx_left_out ;
+wire [0:29] cbx_1__1__80_chanx_right_out ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__81_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__81_ccff_tail ;
+wire [0:29] cbx_1__1__81_chanx_left_out ;
+wire [0:29] cbx_1__1__81_chanx_right_out ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__82_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__82_ccff_tail ;
+wire [0:29] cbx_1__1__82_chanx_left_out ;
+wire [0:29] cbx_1__1__82_chanx_right_out ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__83_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__83_ccff_tail ;
+wire [0:29] cbx_1__1__83_chanx_left_out ;
+wire [0:29] cbx_1__1__83_chanx_right_out ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__84_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__84_ccff_tail ;
+wire [0:29] cbx_1__1__84_chanx_left_out ;
+wire [0:29] cbx_1__1__84_chanx_right_out ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__85_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__85_ccff_tail ;
+wire [0:29] cbx_1__1__85_chanx_left_out ;
+wire [0:29] cbx_1__1__85_chanx_right_out ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__86_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__86_ccff_tail ;
+wire [0:29] cbx_1__1__86_chanx_left_out ;
+wire [0:29] cbx_1__1__86_chanx_right_out ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__87_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__87_ccff_tail ;
+wire [0:29] cbx_1__1__87_chanx_left_out ;
+wire [0:29] cbx_1__1__87_chanx_right_out ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__88_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__88_ccff_tail ;
+wire [0:29] cbx_1__1__88_chanx_left_out ;
+wire [0:29] cbx_1__1__88_chanx_right_out ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__89_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__89_ccff_tail ;
+wire [0:29] cbx_1__1__89_chanx_left_out ;
+wire [0:29] cbx_1__1__89_chanx_right_out ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__8_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__8_ccff_tail ;
+wire [0:29] cbx_1__1__8_chanx_left_out ;
+wire [0:29] cbx_1__1__8_chanx_right_out ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__90_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__90_ccff_tail ;
+wire [0:29] cbx_1__1__90_chanx_left_out ;
+wire [0:29] cbx_1__1__90_chanx_right_out ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__91_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__91_ccff_tail ;
+wire [0:29] cbx_1__1__91_chanx_left_out ;
+wire [0:29] cbx_1__1__91_chanx_right_out ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__92_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__92_ccff_tail ;
+wire [0:29] cbx_1__1__92_chanx_left_out ;
+wire [0:29] cbx_1__1__92_chanx_right_out ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__93_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__93_ccff_tail ;
+wire [0:29] cbx_1__1__93_chanx_left_out ;
+wire [0:29] cbx_1__1__93_chanx_right_out ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__94_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__94_ccff_tail ;
+wire [0:29] cbx_1__1__94_chanx_left_out ;
+wire [0:29] cbx_1__1__94_chanx_right_out ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__95_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__95_ccff_tail ;
+wire [0:29] cbx_1__1__95_chanx_left_out ;
+wire [0:29] cbx_1__1__95_chanx_right_out ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__96_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__96_ccff_tail ;
+wire [0:29] cbx_1__1__96_chanx_left_out ;
+wire [0:29] cbx_1__1__96_chanx_right_out ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__97_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__97_ccff_tail ;
+wire [0:29] cbx_1__1__97_chanx_left_out ;
+wire [0:29] cbx_1__1__97_chanx_right_out ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__98_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__98_ccff_tail ;
+wire [0:29] cbx_1__1__98_chanx_left_out ;
+wire [0:29] cbx_1__1__98_chanx_right_out ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__99_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__99_ccff_tail ;
+wire [0:29] cbx_1__1__99_chanx_left_out ;
+wire [0:29] cbx_1__1__99_chanx_right_out ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_0_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_10_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_11_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_12_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_13_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_14_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_15_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_1_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_2_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_3_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_4_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_5_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_6_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_7_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_8_ ;
+wire [0:0] cbx_1__1__9_bottom_grid_pin_9_ ;
+wire [0:0] cbx_1__1__9_ccff_tail ;
+wire [0:29] cbx_1__1__9_chanx_left_out ;
+wire [0:29] cbx_1__1__9_chanx_right_out ;
+wire [0:0] cby_0__1__0_ccff_tail ;
+wire [0:29] cby_0__1__0_chany_bottom_out ;
+wire [0:29] cby_0__1__0_chany_top_out ;
+wire [0:0] cby_0__1__0_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__10_ccff_tail ;
+wire [0:29] cby_0__1__10_chany_bottom_out ;
+wire [0:29] cby_0__1__10_chany_top_out ;
+wire [0:0] cby_0__1__10_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__11_ccff_tail ;
+wire [0:29] cby_0__1__11_chany_bottom_out ;
+wire [0:29] cby_0__1__11_chany_top_out ;
+wire [0:0] cby_0__1__11_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__1_ccff_tail ;
+wire [0:29] cby_0__1__1_chany_bottom_out ;
+wire [0:29] cby_0__1__1_chany_top_out ;
+wire [0:0] cby_0__1__1_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__2_ccff_tail ;
+wire [0:29] cby_0__1__2_chany_bottom_out ;
+wire [0:29] cby_0__1__2_chany_top_out ;
+wire [0:0] cby_0__1__2_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__3_ccff_tail ;
+wire [0:29] cby_0__1__3_chany_bottom_out ;
+wire [0:29] cby_0__1__3_chany_top_out ;
+wire [0:0] cby_0__1__3_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__4_ccff_tail ;
+wire [0:29] cby_0__1__4_chany_bottom_out ;
+wire [0:29] cby_0__1__4_chany_top_out ;
+wire [0:0] cby_0__1__4_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__5_ccff_tail ;
+wire [0:29] cby_0__1__5_chany_bottom_out ;
+wire [0:29] cby_0__1__5_chany_top_out ;
+wire [0:0] cby_0__1__5_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__6_ccff_tail ;
+wire [0:29] cby_0__1__6_chany_bottom_out ;
+wire [0:29] cby_0__1__6_chany_top_out ;
+wire [0:0] cby_0__1__6_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__7_ccff_tail ;
+wire [0:29] cby_0__1__7_chany_bottom_out ;
+wire [0:29] cby_0__1__7_chany_top_out ;
+wire [0:0] cby_0__1__7_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__8_ccff_tail ;
+wire [0:29] cby_0__1__8_chany_bottom_out ;
+wire [0:29] cby_0__1__8_chany_top_out ;
+wire [0:0] cby_0__1__8_left_grid_pin_0_ ;
+wire [0:0] cby_0__1__9_ccff_tail ;
+wire [0:29] cby_0__1__9_chany_bottom_out ;
+wire [0:29] cby_0__1__9_chany_top_out ;
+wire [0:0] cby_0__1__9_left_grid_pin_0_ ;
+wire [0:0] cby_12__1__0_ccff_tail ;
+wire [0:29] cby_12__1__0_chany_bottom_out ;
+wire [0:29] cby_12__1__0_chany_top_out ;
+wire [0:0] cby_12__1__0_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__0_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__0_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__10_ccff_tail ;
+wire [0:29] cby_12__1__10_chany_bottom_out ;
+wire [0:29] cby_12__1__10_chany_top_out ;
+wire [0:0] cby_12__1__10_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__10_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__10_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__11_ccff_tail ;
+wire [0:29] cby_12__1__11_chany_bottom_out ;
+wire [0:29] cby_12__1__11_chany_top_out ;
+wire [0:0] cby_12__1__11_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__11_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__11_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__1_ccff_tail ;
+wire [0:29] cby_12__1__1_chany_bottom_out ;
+wire [0:29] cby_12__1__1_chany_top_out ;
+wire [0:0] cby_12__1__1_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__1_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__1_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__2_ccff_tail ;
+wire [0:29] cby_12__1__2_chany_bottom_out ;
+wire [0:29] cby_12__1__2_chany_top_out ;
+wire [0:0] cby_12__1__2_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__2_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__2_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__3_ccff_tail ;
+wire [0:29] cby_12__1__3_chany_bottom_out ;
+wire [0:29] cby_12__1__3_chany_top_out ;
+wire [0:0] cby_12__1__3_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__3_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__3_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__4_ccff_tail ;
+wire [0:29] cby_12__1__4_chany_bottom_out ;
+wire [0:29] cby_12__1__4_chany_top_out ;
+wire [0:0] cby_12__1__4_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__4_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__4_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__5_ccff_tail ;
+wire [0:29] cby_12__1__5_chany_bottom_out ;
+wire [0:29] cby_12__1__5_chany_top_out ;
+wire [0:0] cby_12__1__5_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__5_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__5_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__6_ccff_tail ;
+wire [0:29] cby_12__1__6_chany_bottom_out ;
+wire [0:29] cby_12__1__6_chany_top_out ;
+wire [0:0] cby_12__1__6_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__6_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__6_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__7_ccff_tail ;
+wire [0:29] cby_12__1__7_chany_bottom_out ;
+wire [0:29] cby_12__1__7_chany_top_out ;
+wire [0:0] cby_12__1__7_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__7_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__7_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__8_ccff_tail ;
+wire [0:29] cby_12__1__8_chany_bottom_out ;
+wire [0:29] cby_12__1__8_chany_top_out ;
+wire [0:0] cby_12__1__8_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__8_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__8_right_grid_pin_0_ ;
+wire [0:0] cby_12__1__9_ccff_tail ;
+wire [0:29] cby_12__1__9_chany_bottom_out ;
+wire [0:29] cby_12__1__9_chany_top_out ;
+wire [0:0] cby_12__1__9_left_grid_pin_16_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_17_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_18_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_19_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_20_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_21_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_22_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_23_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_24_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_25_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_26_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_27_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_28_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_29_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_30_ ;
+wire [0:0] cby_12__1__9_left_grid_pin_31_ ;
+wire [0:0] cby_12__1__9_right_grid_pin_0_ ;
+wire [0:0] cby_1__1__0_ccff_tail ;
+wire [0:29] cby_1__1__0_chany_bottom_out ;
+wire [0:29] cby_1__1__0_chany_top_out ;
+wire [0:0] cby_1__1__0_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__0_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__100_ccff_tail ;
+wire [0:29] cby_1__1__100_chany_bottom_out ;
+wire [0:29] cby_1__1__100_chany_top_out ;
+wire [0:0] cby_1__1__100_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__100_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__101_ccff_tail ;
+wire [0:29] cby_1__1__101_chany_bottom_out ;
+wire [0:29] cby_1__1__101_chany_top_out ;
+wire [0:0] cby_1__1__101_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__101_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__102_ccff_tail ;
+wire [0:29] cby_1__1__102_chany_bottom_out ;
+wire [0:29] cby_1__1__102_chany_top_out ;
+wire [0:0] cby_1__1__102_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__102_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__103_ccff_tail ;
+wire [0:29] cby_1__1__103_chany_bottom_out ;
+wire [0:29] cby_1__1__103_chany_top_out ;
+wire [0:0] cby_1__1__103_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__103_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__104_ccff_tail ;
+wire [0:29] cby_1__1__104_chany_bottom_out ;
+wire [0:29] cby_1__1__104_chany_top_out ;
+wire [0:0] cby_1__1__104_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__104_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__105_ccff_tail ;
+wire [0:29] cby_1__1__105_chany_bottom_out ;
+wire [0:29] cby_1__1__105_chany_top_out ;
+wire [0:0] cby_1__1__105_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__105_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__106_ccff_tail ;
+wire [0:29] cby_1__1__106_chany_bottom_out ;
+wire [0:29] cby_1__1__106_chany_top_out ;
+wire [0:0] cby_1__1__106_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__106_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__107_ccff_tail ;
+wire [0:29] cby_1__1__107_chany_bottom_out ;
+wire [0:29] cby_1__1__107_chany_top_out ;
+wire [0:0] cby_1__1__107_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__107_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__108_ccff_tail ;
+wire [0:29] cby_1__1__108_chany_bottom_out ;
+wire [0:29] cby_1__1__108_chany_top_out ;
+wire [0:0] cby_1__1__108_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__108_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__109_ccff_tail ;
+wire [0:29] cby_1__1__109_chany_bottom_out ;
+wire [0:29] cby_1__1__109_chany_top_out ;
+wire [0:0] cby_1__1__109_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__109_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__10_ccff_tail ;
+wire [0:29] cby_1__1__10_chany_bottom_out ;
+wire [0:29] cby_1__1__10_chany_top_out ;
+wire [0:0] cby_1__1__10_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__10_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__110_ccff_tail ;
+wire [0:29] cby_1__1__110_chany_bottom_out ;
+wire [0:29] cby_1__1__110_chany_top_out ;
+wire [0:0] cby_1__1__110_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__110_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__111_ccff_tail ;
+wire [0:29] cby_1__1__111_chany_bottom_out ;
+wire [0:29] cby_1__1__111_chany_top_out ;
+wire [0:0] cby_1__1__111_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__111_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__112_ccff_tail ;
+wire [0:29] cby_1__1__112_chany_bottom_out ;
+wire [0:29] cby_1__1__112_chany_top_out ;
+wire [0:0] cby_1__1__112_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__112_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__113_ccff_tail ;
+wire [0:29] cby_1__1__113_chany_bottom_out ;
+wire [0:29] cby_1__1__113_chany_top_out ;
+wire [0:0] cby_1__1__113_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__113_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__114_ccff_tail ;
+wire [0:29] cby_1__1__114_chany_bottom_out ;
+wire [0:29] cby_1__1__114_chany_top_out ;
+wire [0:0] cby_1__1__114_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__114_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__115_ccff_tail ;
+wire [0:29] cby_1__1__115_chany_bottom_out ;
+wire [0:29] cby_1__1__115_chany_top_out ;
+wire [0:0] cby_1__1__115_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__115_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__116_ccff_tail ;
+wire [0:29] cby_1__1__116_chany_bottom_out ;
+wire [0:29] cby_1__1__116_chany_top_out ;
+wire [0:0] cby_1__1__116_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__116_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__117_ccff_tail ;
+wire [0:29] cby_1__1__117_chany_bottom_out ;
+wire [0:29] cby_1__1__117_chany_top_out ;
+wire [0:0] cby_1__1__117_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__117_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__118_ccff_tail ;
+wire [0:29] cby_1__1__118_chany_bottom_out ;
+wire [0:29] cby_1__1__118_chany_top_out ;
+wire [0:0] cby_1__1__118_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__118_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__119_ccff_tail ;
+wire [0:29] cby_1__1__119_chany_bottom_out ;
+wire [0:29] cby_1__1__119_chany_top_out ;
+wire [0:0] cby_1__1__119_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__119_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__11_ccff_tail ;
+wire [0:29] cby_1__1__11_chany_bottom_out ;
+wire [0:29] cby_1__1__11_chany_top_out ;
+wire [0:0] cby_1__1__11_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__11_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__120_ccff_tail ;
+wire [0:29] cby_1__1__120_chany_bottom_out ;
+wire [0:29] cby_1__1__120_chany_top_out ;
+wire [0:0] cby_1__1__120_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__120_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__121_ccff_tail ;
+wire [0:29] cby_1__1__121_chany_bottom_out ;
+wire [0:29] cby_1__1__121_chany_top_out ;
+wire [0:0] cby_1__1__121_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__121_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__122_ccff_tail ;
+wire [0:29] cby_1__1__122_chany_bottom_out ;
+wire [0:29] cby_1__1__122_chany_top_out ;
+wire [0:0] cby_1__1__122_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__122_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__123_ccff_tail ;
+wire [0:29] cby_1__1__123_chany_bottom_out ;
+wire [0:29] cby_1__1__123_chany_top_out ;
+wire [0:0] cby_1__1__123_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__123_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__124_ccff_tail ;
+wire [0:29] cby_1__1__124_chany_bottom_out ;
+wire [0:29] cby_1__1__124_chany_top_out ;
+wire [0:0] cby_1__1__124_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__124_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__125_ccff_tail ;
+wire [0:29] cby_1__1__125_chany_bottom_out ;
+wire [0:29] cby_1__1__125_chany_top_out ;
+wire [0:0] cby_1__1__125_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__125_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__126_ccff_tail ;
+wire [0:29] cby_1__1__126_chany_bottom_out ;
+wire [0:29] cby_1__1__126_chany_top_out ;
+wire [0:0] cby_1__1__126_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__126_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__127_ccff_tail ;
+wire [0:29] cby_1__1__127_chany_bottom_out ;
+wire [0:29] cby_1__1__127_chany_top_out ;
+wire [0:0] cby_1__1__127_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__127_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__128_ccff_tail ;
+wire [0:29] cby_1__1__128_chany_bottom_out ;
+wire [0:29] cby_1__1__128_chany_top_out ;
+wire [0:0] cby_1__1__128_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__128_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__129_ccff_tail ;
+wire [0:29] cby_1__1__129_chany_bottom_out ;
+wire [0:29] cby_1__1__129_chany_top_out ;
+wire [0:0] cby_1__1__129_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__129_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__12_ccff_tail ;
+wire [0:29] cby_1__1__12_chany_bottom_out ;
+wire [0:29] cby_1__1__12_chany_top_out ;
+wire [0:0] cby_1__1__12_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__12_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__130_ccff_tail ;
+wire [0:29] cby_1__1__130_chany_bottom_out ;
+wire [0:29] cby_1__1__130_chany_top_out ;
+wire [0:0] cby_1__1__130_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__130_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__131_ccff_tail ;
+wire [0:29] cby_1__1__131_chany_bottom_out ;
+wire [0:29] cby_1__1__131_chany_top_out ;
+wire [0:0] cby_1__1__131_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__131_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__13_ccff_tail ;
+wire [0:29] cby_1__1__13_chany_bottom_out ;
+wire [0:29] cby_1__1__13_chany_top_out ;
+wire [0:0] cby_1__1__13_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__13_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__14_ccff_tail ;
+wire [0:29] cby_1__1__14_chany_bottom_out ;
+wire [0:29] cby_1__1__14_chany_top_out ;
+wire [0:0] cby_1__1__14_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__14_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__15_ccff_tail ;
+wire [0:29] cby_1__1__15_chany_bottom_out ;
+wire [0:29] cby_1__1__15_chany_top_out ;
+wire [0:0] cby_1__1__15_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__15_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__16_ccff_tail ;
+wire [0:29] cby_1__1__16_chany_bottom_out ;
+wire [0:29] cby_1__1__16_chany_top_out ;
+wire [0:0] cby_1__1__16_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__16_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__17_ccff_tail ;
+wire [0:29] cby_1__1__17_chany_bottom_out ;
+wire [0:29] cby_1__1__17_chany_top_out ;
+wire [0:0] cby_1__1__17_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__17_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__18_ccff_tail ;
+wire [0:29] cby_1__1__18_chany_bottom_out ;
+wire [0:29] cby_1__1__18_chany_top_out ;
+wire [0:0] cby_1__1__18_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__18_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__19_ccff_tail ;
+wire [0:29] cby_1__1__19_chany_bottom_out ;
+wire [0:29] cby_1__1__19_chany_top_out ;
+wire [0:0] cby_1__1__19_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__19_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__1_ccff_tail ;
+wire [0:29] cby_1__1__1_chany_bottom_out ;
+wire [0:29] cby_1__1__1_chany_top_out ;
+wire [0:0] cby_1__1__1_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__1_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__20_ccff_tail ;
+wire [0:29] cby_1__1__20_chany_bottom_out ;
+wire [0:29] cby_1__1__20_chany_top_out ;
+wire [0:0] cby_1__1__20_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__20_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__21_ccff_tail ;
+wire [0:29] cby_1__1__21_chany_bottom_out ;
+wire [0:29] cby_1__1__21_chany_top_out ;
+wire [0:0] cby_1__1__21_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__21_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__22_ccff_tail ;
+wire [0:29] cby_1__1__22_chany_bottom_out ;
+wire [0:29] cby_1__1__22_chany_top_out ;
+wire [0:0] cby_1__1__22_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__22_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__23_ccff_tail ;
+wire [0:29] cby_1__1__23_chany_bottom_out ;
+wire [0:29] cby_1__1__23_chany_top_out ;
+wire [0:0] cby_1__1__23_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__23_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__24_ccff_tail ;
+wire [0:29] cby_1__1__24_chany_bottom_out ;
+wire [0:29] cby_1__1__24_chany_top_out ;
+wire [0:0] cby_1__1__24_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__24_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__25_ccff_tail ;
+wire [0:29] cby_1__1__25_chany_bottom_out ;
+wire [0:29] cby_1__1__25_chany_top_out ;
+wire [0:0] cby_1__1__25_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__25_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__26_ccff_tail ;
+wire [0:29] cby_1__1__26_chany_bottom_out ;
+wire [0:29] cby_1__1__26_chany_top_out ;
+wire [0:0] cby_1__1__26_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__26_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__27_ccff_tail ;
+wire [0:29] cby_1__1__27_chany_bottom_out ;
+wire [0:29] cby_1__1__27_chany_top_out ;
+wire [0:0] cby_1__1__27_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__27_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__28_ccff_tail ;
+wire [0:29] cby_1__1__28_chany_bottom_out ;
+wire [0:29] cby_1__1__28_chany_top_out ;
+wire [0:0] cby_1__1__28_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__28_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__29_ccff_tail ;
+wire [0:29] cby_1__1__29_chany_bottom_out ;
+wire [0:29] cby_1__1__29_chany_top_out ;
+wire [0:0] cby_1__1__29_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__29_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__2_ccff_tail ;
+wire [0:29] cby_1__1__2_chany_bottom_out ;
+wire [0:29] cby_1__1__2_chany_top_out ;
+wire [0:0] cby_1__1__2_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__2_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__30_ccff_tail ;
+wire [0:29] cby_1__1__30_chany_bottom_out ;
+wire [0:29] cby_1__1__30_chany_top_out ;
+wire [0:0] cby_1__1__30_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__30_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__31_ccff_tail ;
+wire [0:29] cby_1__1__31_chany_bottom_out ;
+wire [0:29] cby_1__1__31_chany_top_out ;
+wire [0:0] cby_1__1__31_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__31_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__32_ccff_tail ;
+wire [0:29] cby_1__1__32_chany_bottom_out ;
+wire [0:29] cby_1__1__32_chany_top_out ;
+wire [0:0] cby_1__1__32_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__32_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__33_ccff_tail ;
+wire [0:29] cby_1__1__33_chany_bottom_out ;
+wire [0:29] cby_1__1__33_chany_top_out ;
+wire [0:0] cby_1__1__33_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__33_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__34_ccff_tail ;
+wire [0:29] cby_1__1__34_chany_bottom_out ;
+wire [0:29] cby_1__1__34_chany_top_out ;
+wire [0:0] cby_1__1__34_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__34_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__35_ccff_tail ;
+wire [0:29] cby_1__1__35_chany_bottom_out ;
+wire [0:29] cby_1__1__35_chany_top_out ;
+wire [0:0] cby_1__1__35_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__35_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__36_ccff_tail ;
+wire [0:29] cby_1__1__36_chany_bottom_out ;
+wire [0:29] cby_1__1__36_chany_top_out ;
+wire [0:0] cby_1__1__36_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__36_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__37_ccff_tail ;
+wire [0:29] cby_1__1__37_chany_bottom_out ;
+wire [0:29] cby_1__1__37_chany_top_out ;
+wire [0:0] cby_1__1__37_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__37_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__38_ccff_tail ;
+wire [0:29] cby_1__1__38_chany_bottom_out ;
+wire [0:29] cby_1__1__38_chany_top_out ;
+wire [0:0] cby_1__1__38_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__38_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__39_ccff_tail ;
+wire [0:29] cby_1__1__39_chany_bottom_out ;
+wire [0:29] cby_1__1__39_chany_top_out ;
+wire [0:0] cby_1__1__39_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__39_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__3_ccff_tail ;
+wire [0:29] cby_1__1__3_chany_bottom_out ;
+wire [0:29] cby_1__1__3_chany_top_out ;
+wire [0:0] cby_1__1__3_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__3_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__40_ccff_tail ;
+wire [0:29] cby_1__1__40_chany_bottom_out ;
+wire [0:29] cby_1__1__40_chany_top_out ;
+wire [0:0] cby_1__1__40_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__40_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__41_ccff_tail ;
+wire [0:29] cby_1__1__41_chany_bottom_out ;
+wire [0:29] cby_1__1__41_chany_top_out ;
+wire [0:0] cby_1__1__41_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__41_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__42_ccff_tail ;
+wire [0:29] cby_1__1__42_chany_bottom_out ;
+wire [0:29] cby_1__1__42_chany_top_out ;
+wire [0:0] cby_1__1__42_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__42_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__43_ccff_tail ;
+wire [0:29] cby_1__1__43_chany_bottom_out ;
+wire [0:29] cby_1__1__43_chany_top_out ;
+wire [0:0] cby_1__1__43_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__43_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__44_ccff_tail ;
+wire [0:29] cby_1__1__44_chany_bottom_out ;
+wire [0:29] cby_1__1__44_chany_top_out ;
+wire [0:0] cby_1__1__44_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__44_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__45_ccff_tail ;
+wire [0:29] cby_1__1__45_chany_bottom_out ;
+wire [0:29] cby_1__1__45_chany_top_out ;
+wire [0:0] cby_1__1__45_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__45_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__46_ccff_tail ;
+wire [0:29] cby_1__1__46_chany_bottom_out ;
+wire [0:29] cby_1__1__46_chany_top_out ;
+wire [0:0] cby_1__1__46_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__46_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__47_ccff_tail ;
+wire [0:29] cby_1__1__47_chany_bottom_out ;
+wire [0:29] cby_1__1__47_chany_top_out ;
+wire [0:0] cby_1__1__47_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__47_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__48_ccff_tail ;
+wire [0:29] cby_1__1__48_chany_bottom_out ;
+wire [0:29] cby_1__1__48_chany_top_out ;
+wire [0:0] cby_1__1__48_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__48_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__49_ccff_tail ;
+wire [0:29] cby_1__1__49_chany_bottom_out ;
+wire [0:29] cby_1__1__49_chany_top_out ;
+wire [0:0] cby_1__1__49_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__49_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__4_ccff_tail ;
+wire [0:29] cby_1__1__4_chany_bottom_out ;
+wire [0:29] cby_1__1__4_chany_top_out ;
+wire [0:0] cby_1__1__4_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__4_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__50_ccff_tail ;
+wire [0:29] cby_1__1__50_chany_bottom_out ;
+wire [0:29] cby_1__1__50_chany_top_out ;
+wire [0:0] cby_1__1__50_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__50_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__51_ccff_tail ;
+wire [0:29] cby_1__1__51_chany_bottom_out ;
+wire [0:29] cby_1__1__51_chany_top_out ;
+wire [0:0] cby_1__1__51_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__51_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__52_ccff_tail ;
+wire [0:29] cby_1__1__52_chany_bottom_out ;
+wire [0:29] cby_1__1__52_chany_top_out ;
+wire [0:0] cby_1__1__52_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__52_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__53_ccff_tail ;
+wire [0:29] cby_1__1__53_chany_bottom_out ;
+wire [0:29] cby_1__1__53_chany_top_out ;
+wire [0:0] cby_1__1__53_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__53_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__54_ccff_tail ;
+wire [0:29] cby_1__1__54_chany_bottom_out ;
+wire [0:29] cby_1__1__54_chany_top_out ;
+wire [0:0] cby_1__1__54_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__54_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__55_ccff_tail ;
+wire [0:29] cby_1__1__55_chany_bottom_out ;
+wire [0:29] cby_1__1__55_chany_top_out ;
+wire [0:0] cby_1__1__55_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__55_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__56_ccff_tail ;
+wire [0:29] cby_1__1__56_chany_bottom_out ;
+wire [0:29] cby_1__1__56_chany_top_out ;
+wire [0:0] cby_1__1__56_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__56_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__57_ccff_tail ;
+wire [0:29] cby_1__1__57_chany_bottom_out ;
+wire [0:29] cby_1__1__57_chany_top_out ;
+wire [0:0] cby_1__1__57_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__57_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__58_ccff_tail ;
+wire [0:29] cby_1__1__58_chany_bottom_out ;
+wire [0:29] cby_1__1__58_chany_top_out ;
+wire [0:0] cby_1__1__58_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__58_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__59_ccff_tail ;
+wire [0:29] cby_1__1__59_chany_bottom_out ;
+wire [0:29] cby_1__1__59_chany_top_out ;
+wire [0:0] cby_1__1__59_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__59_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__5_ccff_tail ;
+wire [0:29] cby_1__1__5_chany_bottom_out ;
+wire [0:29] cby_1__1__5_chany_top_out ;
+wire [0:0] cby_1__1__5_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__5_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__60_ccff_tail ;
+wire [0:29] cby_1__1__60_chany_bottom_out ;
+wire [0:29] cby_1__1__60_chany_top_out ;
+wire [0:0] cby_1__1__60_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__60_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__61_ccff_tail ;
+wire [0:29] cby_1__1__61_chany_bottom_out ;
+wire [0:29] cby_1__1__61_chany_top_out ;
+wire [0:0] cby_1__1__61_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__61_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__62_ccff_tail ;
+wire [0:29] cby_1__1__62_chany_bottom_out ;
+wire [0:29] cby_1__1__62_chany_top_out ;
+wire [0:0] cby_1__1__62_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__62_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__63_ccff_tail ;
+wire [0:29] cby_1__1__63_chany_bottom_out ;
+wire [0:29] cby_1__1__63_chany_top_out ;
+wire [0:0] cby_1__1__63_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__63_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__64_ccff_tail ;
+wire [0:29] cby_1__1__64_chany_bottom_out ;
+wire [0:29] cby_1__1__64_chany_top_out ;
+wire [0:0] cby_1__1__64_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__64_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__65_ccff_tail ;
+wire [0:29] cby_1__1__65_chany_bottom_out ;
+wire [0:29] cby_1__1__65_chany_top_out ;
+wire [0:0] cby_1__1__65_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__65_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__66_ccff_tail ;
+wire [0:29] cby_1__1__66_chany_bottom_out ;
+wire [0:29] cby_1__1__66_chany_top_out ;
+wire [0:0] cby_1__1__66_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__66_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__67_ccff_tail ;
+wire [0:29] cby_1__1__67_chany_bottom_out ;
+wire [0:29] cby_1__1__67_chany_top_out ;
+wire [0:0] cby_1__1__67_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__67_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__68_ccff_tail ;
+wire [0:29] cby_1__1__68_chany_bottom_out ;
+wire [0:29] cby_1__1__68_chany_top_out ;
+wire [0:0] cby_1__1__68_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__68_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__69_ccff_tail ;
+wire [0:29] cby_1__1__69_chany_bottom_out ;
+wire [0:29] cby_1__1__69_chany_top_out ;
+wire [0:0] cby_1__1__69_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__69_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__6_ccff_tail ;
+wire [0:29] cby_1__1__6_chany_bottom_out ;
+wire [0:29] cby_1__1__6_chany_top_out ;
+wire [0:0] cby_1__1__6_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__6_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__70_ccff_tail ;
+wire [0:29] cby_1__1__70_chany_bottom_out ;
+wire [0:29] cby_1__1__70_chany_top_out ;
+wire [0:0] cby_1__1__70_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__70_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__71_ccff_tail ;
+wire [0:29] cby_1__1__71_chany_bottom_out ;
+wire [0:29] cby_1__1__71_chany_top_out ;
+wire [0:0] cby_1__1__71_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__71_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__72_ccff_tail ;
+wire [0:29] cby_1__1__72_chany_bottom_out ;
+wire [0:29] cby_1__1__72_chany_top_out ;
+wire [0:0] cby_1__1__72_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__72_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__73_ccff_tail ;
+wire [0:29] cby_1__1__73_chany_bottom_out ;
+wire [0:29] cby_1__1__73_chany_top_out ;
+wire [0:0] cby_1__1__73_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__73_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__74_ccff_tail ;
+wire [0:29] cby_1__1__74_chany_bottom_out ;
+wire [0:29] cby_1__1__74_chany_top_out ;
+wire [0:0] cby_1__1__74_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__74_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__75_ccff_tail ;
+wire [0:29] cby_1__1__75_chany_bottom_out ;
+wire [0:29] cby_1__1__75_chany_top_out ;
+wire [0:0] cby_1__1__75_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__75_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__76_ccff_tail ;
+wire [0:29] cby_1__1__76_chany_bottom_out ;
+wire [0:29] cby_1__1__76_chany_top_out ;
+wire [0:0] cby_1__1__76_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__76_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__77_ccff_tail ;
+wire [0:29] cby_1__1__77_chany_bottom_out ;
+wire [0:29] cby_1__1__77_chany_top_out ;
+wire [0:0] cby_1__1__77_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__77_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__78_ccff_tail ;
+wire [0:29] cby_1__1__78_chany_bottom_out ;
+wire [0:29] cby_1__1__78_chany_top_out ;
+wire [0:0] cby_1__1__78_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__78_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__79_ccff_tail ;
+wire [0:29] cby_1__1__79_chany_bottom_out ;
+wire [0:29] cby_1__1__79_chany_top_out ;
+wire [0:0] cby_1__1__79_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__79_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__7_ccff_tail ;
+wire [0:29] cby_1__1__7_chany_bottom_out ;
+wire [0:29] cby_1__1__7_chany_top_out ;
+wire [0:0] cby_1__1__7_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__7_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__80_ccff_tail ;
+wire [0:29] cby_1__1__80_chany_bottom_out ;
+wire [0:29] cby_1__1__80_chany_top_out ;
+wire [0:0] cby_1__1__80_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__80_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__81_ccff_tail ;
+wire [0:29] cby_1__1__81_chany_bottom_out ;
+wire [0:29] cby_1__1__81_chany_top_out ;
+wire [0:0] cby_1__1__81_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__81_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__82_ccff_tail ;
+wire [0:29] cby_1__1__82_chany_bottom_out ;
+wire [0:29] cby_1__1__82_chany_top_out ;
+wire [0:0] cby_1__1__82_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__82_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__83_ccff_tail ;
+wire [0:29] cby_1__1__83_chany_bottom_out ;
+wire [0:29] cby_1__1__83_chany_top_out ;
+wire [0:0] cby_1__1__83_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__83_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__84_ccff_tail ;
+wire [0:29] cby_1__1__84_chany_bottom_out ;
+wire [0:29] cby_1__1__84_chany_top_out ;
+wire [0:0] cby_1__1__84_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__84_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__85_ccff_tail ;
+wire [0:29] cby_1__1__85_chany_bottom_out ;
+wire [0:29] cby_1__1__85_chany_top_out ;
+wire [0:0] cby_1__1__85_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__85_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__86_ccff_tail ;
+wire [0:29] cby_1__1__86_chany_bottom_out ;
+wire [0:29] cby_1__1__86_chany_top_out ;
+wire [0:0] cby_1__1__86_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__86_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__87_ccff_tail ;
+wire [0:29] cby_1__1__87_chany_bottom_out ;
+wire [0:29] cby_1__1__87_chany_top_out ;
+wire [0:0] cby_1__1__87_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__87_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__88_ccff_tail ;
+wire [0:29] cby_1__1__88_chany_bottom_out ;
+wire [0:29] cby_1__1__88_chany_top_out ;
+wire [0:0] cby_1__1__88_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__88_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__89_ccff_tail ;
+wire [0:29] cby_1__1__89_chany_bottom_out ;
+wire [0:29] cby_1__1__89_chany_top_out ;
+wire [0:0] cby_1__1__89_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__89_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__8_ccff_tail ;
+wire [0:29] cby_1__1__8_chany_bottom_out ;
+wire [0:29] cby_1__1__8_chany_top_out ;
+wire [0:0] cby_1__1__8_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__8_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__90_ccff_tail ;
+wire [0:29] cby_1__1__90_chany_bottom_out ;
+wire [0:29] cby_1__1__90_chany_top_out ;
+wire [0:0] cby_1__1__90_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__90_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__91_ccff_tail ;
+wire [0:29] cby_1__1__91_chany_bottom_out ;
+wire [0:29] cby_1__1__91_chany_top_out ;
+wire [0:0] cby_1__1__91_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__91_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__92_ccff_tail ;
+wire [0:29] cby_1__1__92_chany_bottom_out ;
+wire [0:29] cby_1__1__92_chany_top_out ;
+wire [0:0] cby_1__1__92_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__92_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__93_ccff_tail ;
+wire [0:29] cby_1__1__93_chany_bottom_out ;
+wire [0:29] cby_1__1__93_chany_top_out ;
+wire [0:0] cby_1__1__93_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__93_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__94_ccff_tail ;
+wire [0:29] cby_1__1__94_chany_bottom_out ;
+wire [0:29] cby_1__1__94_chany_top_out ;
+wire [0:0] cby_1__1__94_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__94_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__95_ccff_tail ;
+wire [0:29] cby_1__1__95_chany_bottom_out ;
+wire [0:29] cby_1__1__95_chany_top_out ;
+wire [0:0] cby_1__1__95_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__95_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__96_ccff_tail ;
+wire [0:29] cby_1__1__96_chany_bottom_out ;
+wire [0:29] cby_1__1__96_chany_top_out ;
+wire [0:0] cby_1__1__96_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__96_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__97_ccff_tail ;
+wire [0:29] cby_1__1__97_chany_bottom_out ;
+wire [0:29] cby_1__1__97_chany_top_out ;
+wire [0:0] cby_1__1__97_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__97_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__98_ccff_tail ;
+wire [0:29] cby_1__1__98_chany_bottom_out ;
+wire [0:29] cby_1__1__98_chany_top_out ;
+wire [0:0] cby_1__1__98_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__98_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__99_ccff_tail ;
+wire [0:29] cby_1__1__99_chany_bottom_out ;
+wire [0:29] cby_1__1__99_chany_top_out ;
+wire [0:0] cby_1__1__99_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__99_left_grid_pin_31_ ;
+wire [0:0] cby_1__1__9_ccff_tail ;
+wire [0:29] cby_1__1__9_chany_bottom_out ;
+wire [0:29] cby_1__1__9_chany_top_out ;
+wire [0:0] cby_1__1__9_left_grid_pin_16_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_17_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_18_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_19_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_20_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_21_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_22_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_23_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_24_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_25_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_26_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_27_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_28_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_29_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_30_ ;
+wire [0:0] cby_1__1__9_left_grid_pin_31_ ;
+wire [0:0] direct_interc_0_out ;
+wire [0:0] direct_interc_100_out ;
+wire [0:0] direct_interc_101_out ;
+wire [0:0] direct_interc_102_out ;
+wire [0:0] direct_interc_103_out ;
+wire [0:0] direct_interc_104_out ;
+wire [0:0] direct_interc_105_out ;
+wire [0:0] direct_interc_106_out ;
+wire [0:0] direct_interc_107_out ;
+wire [0:0] direct_interc_108_out ;
+wire [0:0] direct_interc_109_out ;
+wire [0:0] direct_interc_10_out ;
+wire [0:0] direct_interc_110_out ;
+wire [0:0] direct_interc_111_out ;
+wire [0:0] direct_interc_112_out ;
+wire [0:0] direct_interc_113_out ;
+wire [0:0] direct_interc_114_out ;
+wire [0:0] direct_interc_115_out ;
+wire [0:0] direct_interc_116_out ;
+wire [0:0] direct_interc_117_out ;
+wire [0:0] direct_interc_118_out ;
+wire [0:0] direct_interc_119_out ;
+wire [0:0] direct_interc_11_out ;
+wire [0:0] direct_interc_120_out ;
+wire [0:0] direct_interc_121_out ;
+wire [0:0] direct_interc_122_out ;
+wire [0:0] direct_interc_123_out ;
+wire [0:0] direct_interc_124_out ;
+wire [0:0] direct_interc_125_out ;
+wire [0:0] direct_interc_126_out ;
+wire [0:0] direct_interc_127_out ;
+wire [0:0] direct_interc_128_out ;
+wire [0:0] direct_interc_129_out ;
+wire [0:0] direct_interc_12_out ;
+wire [0:0] direct_interc_130_out ;
+wire [0:0] direct_interc_131_out ;
+wire [0:0] direct_interc_132_out ;
+wire [0:0] direct_interc_133_out ;
+wire [0:0] direct_interc_134_out ;
+wire [0:0] direct_interc_135_out ;
+wire [0:0] direct_interc_136_out ;
+wire [0:0] direct_interc_137_out ;
+wire [0:0] direct_interc_138_out ;
+wire [0:0] direct_interc_139_out ;
+wire [0:0] direct_interc_13_out ;
+wire [0:0] direct_interc_140_out ;
+wire [0:0] direct_interc_141_out ;
+wire [0:0] direct_interc_142_out ;
+wire [0:0] direct_interc_143_out ;
+wire [0:0] direct_interc_144_out ;
+wire [0:0] direct_interc_145_out ;
+wire [0:0] direct_interc_146_out ;
+wire [0:0] direct_interc_147_out ;
+wire [0:0] direct_interc_148_out ;
+wire [0:0] direct_interc_149_out ;
+wire [0:0] direct_interc_14_out ;
+wire [0:0] direct_interc_150_out ;
+wire [0:0] direct_interc_151_out ;
+wire [0:0] direct_interc_152_out ;
+wire [0:0] direct_interc_153_out ;
+wire [0:0] direct_interc_154_out ;
+wire [0:0] direct_interc_155_out ;
+wire [0:0] direct_interc_156_out ;
+wire [0:0] direct_interc_157_out ;
+wire [0:0] direct_interc_158_out ;
+wire [0:0] direct_interc_159_out ;
+wire [0:0] direct_interc_15_out ;
+wire [0:0] direct_interc_160_out ;
+wire [0:0] direct_interc_161_out ;
+wire [0:0] direct_interc_162_out ;
+wire [0:0] direct_interc_163_out ;
+wire [0:0] direct_interc_164_out ;
+wire [0:0] direct_interc_165_out ;
+wire [0:0] direct_interc_166_out ;
+wire [0:0] direct_interc_167_out ;
+wire [0:0] direct_interc_168_out ;
+wire [0:0] direct_interc_169_out ;
+wire [0:0] direct_interc_16_out ;
+wire [0:0] direct_interc_170_out ;
+wire [0:0] direct_interc_171_out ;
+wire [0:0] direct_interc_172_out ;
+wire [0:0] direct_interc_173_out ;
+wire [0:0] direct_interc_174_out ;
+wire [0:0] direct_interc_175_out ;
+wire [0:0] direct_interc_176_out ;
+wire [0:0] direct_interc_177_out ;
+wire [0:0] direct_interc_178_out ;
+wire [0:0] direct_interc_179_out ;
+wire [0:0] direct_interc_17_out ;
+wire [0:0] direct_interc_180_out ;
+wire [0:0] direct_interc_181_out ;
+wire [0:0] direct_interc_182_out ;
+wire [0:0] direct_interc_183_out ;
+wire [0:0] direct_interc_184_out ;
+wire [0:0] direct_interc_185_out ;
+wire [0:0] direct_interc_186_out ;
+wire [0:0] direct_interc_187_out ;
+wire [0:0] direct_interc_188_out ;
+wire [0:0] direct_interc_189_out ;
+wire [0:0] direct_interc_18_out ;
+wire [0:0] direct_interc_190_out ;
+wire [0:0] direct_interc_191_out ;
+wire [0:0] direct_interc_192_out ;
+wire [0:0] direct_interc_193_out ;
+wire [0:0] direct_interc_194_out ;
+wire [0:0] direct_interc_195_out ;
+wire [0:0] direct_interc_196_out ;
+wire [0:0] direct_interc_197_out ;
+wire [0:0] direct_interc_198_out ;
+wire [0:0] direct_interc_199_out ;
+wire [0:0] direct_interc_19_out ;
+wire [0:0] direct_interc_1_out ;
+wire [0:0] direct_interc_200_out ;
+wire [0:0] direct_interc_201_out ;
+wire [0:0] direct_interc_202_out ;
+wire [0:0] direct_interc_203_out ;
+wire [0:0] direct_interc_204_out ;
+wire [0:0] direct_interc_205_out ;
+wire [0:0] direct_interc_206_out ;
+wire [0:0] direct_interc_207_out ;
+wire [0:0] direct_interc_208_out ;
+wire [0:0] direct_interc_209_out ;
+wire [0:0] direct_interc_20_out ;
+wire [0:0] direct_interc_210_out ;
+wire [0:0] direct_interc_211_out ;
+wire [0:0] direct_interc_212_out ;
+wire [0:0] direct_interc_213_out ;
+wire [0:0] direct_interc_214_out ;
+wire [0:0] direct_interc_215_out ;
+wire [0:0] direct_interc_216_out ;
+wire [0:0] direct_interc_217_out ;
+wire [0:0] direct_interc_218_out ;
+wire [0:0] direct_interc_219_out ;
+wire [0:0] direct_interc_21_out ;
+wire [0:0] direct_interc_220_out ;
+wire [0:0] direct_interc_221_out ;
+wire [0:0] direct_interc_222_out ;
+wire [0:0] direct_interc_223_out ;
+wire [0:0] direct_interc_224_out ;
+wire [0:0] direct_interc_225_out ;
+wire [0:0] direct_interc_226_out ;
+wire [0:0] direct_interc_227_out ;
+wire [0:0] direct_interc_228_out ;
+wire [0:0] direct_interc_229_out ;
+wire [0:0] direct_interc_22_out ;
+wire [0:0] direct_interc_230_out ;
+wire [0:0] direct_interc_231_out ;
+wire [0:0] direct_interc_232_out ;
+wire [0:0] direct_interc_233_out ;
+wire [0:0] direct_interc_234_out ;
+wire [0:0] direct_interc_235_out ;
+wire [0:0] direct_interc_236_out ;
+wire [0:0] direct_interc_237_out ;
+wire [0:0] direct_interc_238_out ;
+wire [0:0] direct_interc_239_out ;
+wire [0:0] direct_interc_23_out ;
+wire [0:0] direct_interc_240_out ;
+wire [0:0] direct_interc_241_out ;
+wire [0:0] direct_interc_242_out ;
+wire [0:0] direct_interc_243_out ;
+wire [0:0] direct_interc_244_out ;
+wire [0:0] direct_interc_245_out ;
+wire [0:0] direct_interc_246_out ;
+wire [0:0] direct_interc_247_out ;
+wire [0:0] direct_interc_248_out ;
+wire [0:0] direct_interc_249_out ;
+wire [0:0] direct_interc_24_out ;
+wire [0:0] direct_interc_250_out ;
+wire [0:0] direct_interc_251_out ;
+wire [0:0] direct_interc_252_out ;
+wire [0:0] direct_interc_253_out ;
+wire [0:0] direct_interc_254_out ;
+wire [0:0] direct_interc_255_out ;
+wire [0:0] direct_interc_256_out ;
+wire [0:0] direct_interc_257_out ;
+wire [0:0] direct_interc_258_out ;
+wire [0:0] direct_interc_259_out ;
+wire [0:0] direct_interc_25_out ;
+wire [0:0] direct_interc_260_out ;
+wire [0:0] direct_interc_261_out ;
+wire [0:0] direct_interc_262_out ;
+wire [0:0] direct_interc_263_out ;
+wire [0:0] direct_interc_264_out ;
+wire [0:0] direct_interc_265_out ;
+wire [0:0] direct_interc_266_out ;
+wire [0:0] direct_interc_267_out ;
+wire [0:0] direct_interc_268_out ;
+wire [0:0] direct_interc_269_out ;
+wire [0:0] direct_interc_26_out ;
+wire [0:0] direct_interc_270_out ;
+wire [0:0] direct_interc_271_out ;
+wire [0:0] direct_interc_272_out ;
+wire [0:0] direct_interc_273_out ;
+wire [0:0] direct_interc_274_out ;
+wire [0:0] direct_interc_275_out ;
+wire [0:0] direct_interc_276_out ;
+wire [0:0] direct_interc_277_out ;
+wire [0:0] direct_interc_278_out ;
+wire [0:0] direct_interc_279_out ;
+wire [0:0] direct_interc_27_out ;
+wire [0:0] direct_interc_280_out ;
+wire [0:0] direct_interc_281_out ;
+wire [0:0] direct_interc_282_out ;
+wire [0:0] direct_interc_283_out ;
+wire [0:0] direct_interc_284_out ;
+wire [0:0] direct_interc_285_out ;
+wire [0:0] direct_interc_286_out ;
+wire [0:0] direct_interc_287_out ;
+wire [0:0] direct_interc_288_out ;
+wire [0:0] direct_interc_289_out ;
+wire [0:0] direct_interc_28_out ;
+wire [0:0] direct_interc_290_out ;
+wire [0:0] direct_interc_291_out ;
+wire [0:0] direct_interc_292_out ;
+wire [0:0] direct_interc_293_out ;
+wire [0:0] direct_interc_294_out ;
+wire [0:0] direct_interc_295_out ;
+wire [0:0] direct_interc_296_out ;
+wire [0:0] direct_interc_297_out ;
+wire [0:0] direct_interc_298_out ;
+wire [0:0] direct_interc_299_out ;
+wire [0:0] direct_interc_29_out ;
+wire [0:0] direct_interc_2_out ;
+wire [0:0] direct_interc_300_out ;
+wire [0:0] direct_interc_301_out ;
+wire [0:0] direct_interc_302_out ;
+wire [0:0] direct_interc_303_out ;
+wire [0:0] direct_interc_304_out ;
+wire [0:0] direct_interc_305_out ;
+wire [0:0] direct_interc_306_out ;
+wire [0:0] direct_interc_307_out ;
+wire [0:0] direct_interc_308_out ;
+wire [0:0] direct_interc_309_out ;
+wire [0:0] direct_interc_30_out ;
+wire [0:0] direct_interc_310_out ;
+wire [0:0] direct_interc_311_out ;
+wire [0:0] direct_interc_312_out ;
+wire [0:0] direct_interc_313_out ;
+wire [0:0] direct_interc_314_out ;
+wire [0:0] direct_interc_315_out ;
+wire [0:0] direct_interc_316_out ;
+wire [0:0] direct_interc_317_out ;
+wire [0:0] direct_interc_318_out ;
+wire [0:0] direct_interc_319_out ;
+wire [0:0] direct_interc_31_out ;
+wire [0:0] direct_interc_320_out ;
+wire [0:0] direct_interc_321_out ;
+wire [0:0] direct_interc_322_out ;
+wire [0:0] direct_interc_323_out ;
+wire [0:0] direct_interc_324_out ;
+wire [0:0] direct_interc_325_out ;
+wire [0:0] direct_interc_326_out ;
+wire [0:0] direct_interc_327_out ;
+wire [0:0] direct_interc_328_out ;
+wire [0:0] direct_interc_329_out ;
+wire [0:0] direct_interc_32_out ;
+wire [0:0] direct_interc_330_out ;
+wire [0:0] direct_interc_331_out ;
+wire [0:0] direct_interc_332_out ;
+wire [0:0] direct_interc_333_out ;
+wire [0:0] direct_interc_334_out ;
+wire [0:0] direct_interc_335_out ;
+wire [0:0] direct_interc_336_out ;
+wire [0:0] direct_interc_337_out ;
+wire [0:0] direct_interc_338_out ;
+wire [0:0] direct_interc_339_out ;
+wire [0:0] direct_interc_33_out ;
+wire [0:0] direct_interc_340_out ;
+wire [0:0] direct_interc_341_out ;
+wire [0:0] direct_interc_342_out ;
+wire [0:0] direct_interc_343_out ;
+wire [0:0] direct_interc_344_out ;
+wire [0:0] direct_interc_345_out ;
+wire [0:0] direct_interc_346_out ;
+wire [0:0] direct_interc_347_out ;
+wire [0:0] direct_interc_348_out ;
+wire [0:0] direct_interc_349_out ;
+wire [0:0] direct_interc_34_out ;
+wire [0:0] direct_interc_350_out ;
+wire [0:0] direct_interc_351_out ;
+wire [0:0] direct_interc_352_out ;
+wire [0:0] direct_interc_353_out ;
+wire [0:0] direct_interc_354_out ;
+wire [0:0] direct_interc_355_out ;
+wire [0:0] direct_interc_356_out ;
+wire [0:0] direct_interc_357_out ;
+wire [0:0] direct_interc_358_out ;
+wire [0:0] direct_interc_359_out ;
+wire [0:0] direct_interc_35_out ;
+wire [0:0] direct_interc_360_out ;
+wire [0:0] direct_interc_361_out ;
+wire [0:0] direct_interc_362_out ;
+wire [0:0] direct_interc_363_out ;
+wire [0:0] direct_interc_364_out ;
+wire [0:0] direct_interc_365_out ;
+wire [0:0] direct_interc_366_out ;
+wire [0:0] direct_interc_367_out ;
+wire [0:0] direct_interc_368_out ;
+wire [0:0] direct_interc_369_out ;
+wire [0:0] direct_interc_36_out ;
+wire [0:0] direct_interc_370_out ;
+wire [0:0] direct_interc_371_out ;
+wire [0:0] direct_interc_372_out ;
+wire [0:0] direct_interc_373_out ;
+wire [0:0] direct_interc_374_out ;
+wire [0:0] direct_interc_375_out ;
+wire [0:0] direct_interc_376_out ;
+wire [0:0] direct_interc_377_out ;
+wire [0:0] direct_interc_378_out ;
+wire [0:0] direct_interc_379_out ;
+wire [0:0] direct_interc_37_out ;
+wire [0:0] direct_interc_380_out ;
+wire [0:0] direct_interc_381_out ;
+wire [0:0] direct_interc_382_out ;
+wire [0:0] direct_interc_383_out ;
+wire [0:0] direct_interc_384_out ;
+wire [0:0] direct_interc_385_out ;
+wire [0:0] direct_interc_386_out ;
+wire [0:0] direct_interc_387_out ;
+wire [0:0] direct_interc_388_out ;
+wire [0:0] direct_interc_389_out ;
+wire [0:0] direct_interc_38_out ;
+wire [0:0] direct_interc_390_out ;
+wire [0:0] direct_interc_391_out ;
+wire [0:0] direct_interc_392_out ;
+wire [0:0] direct_interc_393_out ;
+wire [0:0] direct_interc_394_out ;
+wire [0:0] direct_interc_395_out ;
+wire [0:0] direct_interc_396_out ;
+wire [0:0] direct_interc_397_out ;
+wire [0:0] direct_interc_398_out ;
+wire [0:0] direct_interc_399_out ;
+wire [0:0] direct_interc_39_out ;
+wire [0:0] direct_interc_3_out ;
+wire [0:0] direct_interc_400_out ;
+wire [0:0] direct_interc_401_out ;
+wire [0:0] direct_interc_402_out ;
+wire [0:0] direct_interc_403_out ;
+wire [0:0] direct_interc_404_out ;
+wire [0:0] direct_interc_405_out ;
+wire [0:0] direct_interc_406_out ;
+wire [0:0] direct_interc_40_out ;
+wire [0:0] direct_interc_41_out ;
+wire [0:0] direct_interc_42_out ;
+wire [0:0] direct_interc_43_out ;
+wire [0:0] direct_interc_44_out ;
+wire [0:0] direct_interc_45_out ;
+wire [0:0] direct_interc_46_out ;
+wire [0:0] direct_interc_47_out ;
+wire [0:0] direct_interc_48_out ;
+wire [0:0] direct_interc_49_out ;
+wire [0:0] direct_interc_4_out ;
+wire [0:0] direct_interc_50_out ;
+wire [0:0] direct_interc_51_out ;
+wire [0:0] direct_interc_52_out ;
+wire [0:0] direct_interc_53_out ;
+wire [0:0] direct_interc_54_out ;
+wire [0:0] direct_interc_55_out ;
+wire [0:0] direct_interc_56_out ;
+wire [0:0] direct_interc_57_out ;
+wire [0:0] direct_interc_58_out ;
+wire [0:0] direct_interc_59_out ;
+wire [0:0] direct_interc_5_out ;
+wire [0:0] direct_interc_60_out ;
+wire [0:0] direct_interc_61_out ;
+wire [0:0] direct_interc_62_out ;
+wire [0:0] direct_interc_63_out ;
+wire [0:0] direct_interc_64_out ;
+wire [0:0] direct_interc_65_out ;
+wire [0:0] direct_interc_66_out ;
+wire [0:0] direct_interc_67_out ;
+wire [0:0] direct_interc_68_out ;
+wire [0:0] direct_interc_69_out ;
+wire [0:0] direct_interc_6_out ;
+wire [0:0] direct_interc_70_out ;
+wire [0:0] direct_interc_71_out ;
+wire [0:0] direct_interc_72_out ;
+wire [0:0] direct_interc_73_out ;
+wire [0:0] direct_interc_74_out ;
+wire [0:0] direct_interc_75_out ;
+wire [0:0] direct_interc_76_out ;
+wire [0:0] direct_interc_77_out ;
+wire [0:0] direct_interc_78_out ;
+wire [0:0] direct_interc_79_out ;
+wire [0:0] direct_interc_7_out ;
+wire [0:0] direct_interc_80_out ;
+wire [0:0] direct_interc_81_out ;
+wire [0:0] direct_interc_82_out ;
+wire [0:0] direct_interc_83_out ;
+wire [0:0] direct_interc_84_out ;
+wire [0:0] direct_interc_85_out ;
+wire [0:0] direct_interc_86_out ;
+wire [0:0] direct_interc_87_out ;
+wire [0:0] direct_interc_88_out ;
+wire [0:0] direct_interc_89_out ;
+wire [0:0] direct_interc_8_out ;
+wire [0:0] direct_interc_90_out ;
+wire [0:0] direct_interc_91_out ;
+wire [0:0] direct_interc_92_out ;
+wire [0:0] direct_interc_93_out ;
+wire [0:0] direct_interc_94_out ;
+wire [0:0] direct_interc_95_out ;
+wire [0:0] direct_interc_96_out ;
+wire [0:0] direct_interc_97_out ;
+wire [0:0] direct_interc_98_out ;
+wire [0:0] direct_interc_99_out ;
+wire [0:0] direct_interc_9_out ;
+wire [0:0] grid_clb_0_ccff_tail ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_100_ccff_tail ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_101_ccff_tail ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_102_ccff_tail ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_103_ccff_tail ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_104_ccff_tail ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_105_ccff_tail ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_106_ccff_tail ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_107_ccff_tail ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_108_ccff_tail ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_109_ccff_tail ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_10_ccff_tail ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_110_ccff_tail ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_111_ccff_tail ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_112_ccff_tail ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_113_ccff_tail ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_114_ccff_tail ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_115_ccff_tail ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_116_ccff_tail ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_117_ccff_tail ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_118_ccff_tail ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_119_ccff_tail ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_11_ccff_tail ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_120_ccff_tail ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_121_ccff_tail ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_122_ccff_tail ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_123_ccff_tail ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_124_ccff_tail ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_125_ccff_tail ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_126_ccff_tail ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_127_ccff_tail ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_128_ccff_tail ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_129_ccff_tail ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_53_ ;
+wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_12_ccff_tail ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_130_ccff_tail ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_131_ccff_tail ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_132_ccff_tail ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_133_ccff_tail ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_134_ccff_tail ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_135_ccff_tail ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_136_ccff_tail ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_137_ccff_tail ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_138_ccff_tail ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_139_ccff_tail ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_13_ccff_tail ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_140_ccff_tail ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_141_ccff_tail ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_142_ccff_tail ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_143_ccff_tail ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_14_ccff_tail ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_15_ccff_tail ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_16_ccff_tail ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_17_ccff_tail ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_18_ccff_tail ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_19_ccff_tail ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_33_ ;
+wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_1_ccff_tail ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_20_ccff_tail ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_21_ccff_tail ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_22_ccff_tail ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_23_ccff_tail ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_24_ccff_tail ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_25_ccff_tail ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_26_ccff_tail ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_27_ccff_tail ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_28_ccff_tail ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_29_ccff_tail ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_2_ccff_tail ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_30_ccff_tail ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_31_ccff_tail ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_32_ccff_tail ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_33_ccff_tail ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_34_ccff_tail ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_35_ccff_tail ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_36_ccff_tail ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_37_ccff_tail ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_38_ccff_tail ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_39_ccff_tail ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_3_ccff_tail ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_40_ccff_tail ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_41_ccff_tail ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_42_ccff_tail ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_43_ccff_tail ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_44_ccff_tail ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_45_ccff_tail ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_46_ccff_tail ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_47_ccff_tail ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_48_ccff_tail ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_49_ccff_tail ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_4_ccff_tail ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_50_ccff_tail ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_51_ccff_tail ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_52_ccff_tail ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_53_ccff_tail ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_54_ccff_tail ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_55_ccff_tail ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_56_ccff_tail ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_57_ccff_tail ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_58_ccff_tail ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_59_ccff_tail ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_5_ccff_tail ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_60_ccff_tail ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_61_ccff_tail ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_62_ccff_tail ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_63_ccff_tail ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_64_ccff_tail ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_65_ccff_tail ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_66_ccff_tail ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_67_ccff_tail ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_68_ccff_tail ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_69_ccff_tail ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_6_ccff_tail ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_70_ccff_tail ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_71_ccff_tail ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_72_ccff_tail ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_73_ccff_tail ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_74_ccff_tail ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_75_ccff_tail ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_76_ccff_tail ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_77_ccff_tail ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_78_ccff_tail ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_79_ccff_tail ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_7_ccff_tail ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_80_ccff_tail ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_81_ccff_tail ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_82_ccff_tail ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_83_ccff_tail ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_84_ccff_tail ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_85_ccff_tail ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_86_ccff_tail ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_87_ccff_tail ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_88_ccff_tail ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_89_ccff_tail ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_8_ccff_tail ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_90_ccff_tail ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_91_ccff_tail ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_92_ccff_tail ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_93_ccff_tail ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_94_ccff_tail ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_95_ccff_tail ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_96_ccff_tail ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_97_ccff_tail ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_98_ccff_tail ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_99_ccff_tail ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ;
+wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ;
+wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ;
+wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ;
+wire [0:0] grid_clb_9_ccff_tail ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_upper ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_lower ;
+wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_upper ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_lower ;
+wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_upper ;
+wire [0:0] grid_io_bottom_0_ccff_tail ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_10_ccff_tail ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_11_ccff_tail ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_1_ccff_tail ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_2_ccff_tail ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_3_ccff_tail ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_4_ccff_tail ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_5_ccff_tail ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_6_ccff_tail ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_7_ccff_tail ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_8_ccff_tail ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_bottom_9_ccff_tail ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_upper ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_lower ;
+wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_upper ;
+wire [0:0] grid_io_left_0_ccff_tail ;
+wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_10_ccff_tail ;
+wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_11_ccff_tail ;
+wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_1_ccff_tail ;
+wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_2_ccff_tail ;
+wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_3_ccff_tail ;
+wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_4_ccff_tail ;
+wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_5_ccff_tail ;
+wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_6_ccff_tail ;
+wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_7_ccff_tail ;
+wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_8_ccff_tail ;
+wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_left_9_ccff_tail ;
+wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_0_ccff_tail ;
+wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_10_ccff_tail ;
+wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_11_ccff_tail ;
+wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_1_ccff_tail ;
+wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_2_ccff_tail ;
+wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_3_ccff_tail ;
+wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_4_ccff_tail ;
+wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_5_ccff_tail ;
+wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_6_ccff_tail ;
+wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_7_ccff_tail ;
+wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_8_ccff_tail ;
+wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_right_9_ccff_tail ;
+wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_0_ccff_tail ;
+wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_10_ccff_tail ;
+wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_11_ccff_tail ;
+wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_1_ccff_tail ;
+wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_2_ccff_tail ;
+wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_3_ccff_tail ;
+wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_4_ccff_tail ;
+wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_5_ccff_tail ;
+wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_6_ccff_tail ;
+wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_7_ccff_tail ;
+wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_8_ccff_tail ;
+wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_lower ;
+wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_upper ;
+wire [0:0] grid_io_top_9_ccff_tail ;
+wire [0:29] sb_0__0__0_chanx_right_out ;
+wire [0:29] sb_0__0__0_chany_top_out ;
+wire [0:0] sb_0__12__0_ccff_tail ;
+wire [0:29] sb_0__12__0_chanx_right_out ;
+wire [0:29] sb_0__12__0_chany_bottom_out ;
+wire [0:0] sb_0__1__0_ccff_tail ;
+wire [0:29] sb_0__1__0_chanx_right_out ;
+wire [0:29] sb_0__1__0_chany_bottom_out ;
+wire [0:29] sb_0__1__0_chany_top_out ;
+wire [0:0] sb_0__1__10_ccff_tail ;
+wire [0:29] sb_0__1__10_chanx_right_out ;
+wire [0:29] sb_0__1__10_chany_bottom_out ;
+wire [0:29] sb_0__1__10_chany_top_out ;
+wire [0:0] sb_0__1__1_ccff_tail ;
+wire [0:29] sb_0__1__1_chanx_right_out ;
+wire [0:29] sb_0__1__1_chany_bottom_out ;
+wire [0:29] sb_0__1__1_chany_top_out ;
+wire [0:0] sb_0__1__2_ccff_tail ;
+wire [0:29] sb_0__1__2_chanx_right_out ;
+wire [0:29] sb_0__1__2_chany_bottom_out ;
+wire [0:29] sb_0__1__2_chany_top_out ;
+wire [0:0] sb_0__1__3_ccff_tail ;
+wire [0:29] sb_0__1__3_chanx_right_out ;
+wire [0:29] sb_0__1__3_chany_bottom_out ;
+wire [0:29] sb_0__1__3_chany_top_out ;
+wire [0:0] sb_0__1__4_ccff_tail ;
+wire [0:29] sb_0__1__4_chanx_right_out ;
+wire [0:29] sb_0__1__4_chany_bottom_out ;
+wire [0:29] sb_0__1__4_chany_top_out ;
+wire [0:0] sb_0__1__5_ccff_tail ;
+wire [0:29] sb_0__1__5_chanx_right_out ;
+wire [0:29] sb_0__1__5_chany_bottom_out ;
+wire [0:29] sb_0__1__5_chany_top_out ;
+wire [0:0] sb_0__1__6_ccff_tail ;
+wire [0:29] sb_0__1__6_chanx_right_out ;
+wire [0:29] sb_0__1__6_chany_bottom_out ;
+wire [0:29] sb_0__1__6_chany_top_out ;
+wire [0:0] sb_0__1__7_ccff_tail ;
+wire [0:29] sb_0__1__7_chanx_right_out ;
+wire [0:29] sb_0__1__7_chany_bottom_out ;
+wire [0:29] sb_0__1__7_chany_top_out ;
+wire [0:0] sb_0__1__8_ccff_tail ;
+wire [0:29] sb_0__1__8_chanx_right_out ;
+wire [0:29] sb_0__1__8_chany_bottom_out ;
+wire [0:29] sb_0__1__8_chany_top_out ;
+wire [0:0] sb_0__1__9_ccff_tail ;
+wire [0:29] sb_0__1__9_chanx_right_out ;
+wire [0:29] sb_0__1__9_chany_bottom_out ;
+wire [0:29] sb_0__1__9_chany_top_out ;
+wire [0:0] sb_12__0__0_ccff_tail ;
+wire [0:29] sb_12__0__0_chanx_left_out ;
+wire [0:29] sb_12__0__0_chany_top_out ;
+wire [0:0] sb_12__12__0_ccff_tail ;
+wire [0:29] sb_12__12__0_chanx_left_out ;
+wire [0:29] sb_12__12__0_chany_bottom_out ;
+wire [0:0] sb_12__1__0_ccff_tail ;
+wire [0:29] sb_12__1__0_chanx_left_out ;
+wire [0:29] sb_12__1__0_chany_bottom_out ;
+wire [0:29] sb_12__1__0_chany_top_out ;
+wire [0:0] sb_12__1__10_ccff_tail ;
+wire [0:29] sb_12__1__10_chanx_left_out ;
+wire [0:29] sb_12__1__10_chany_bottom_out ;
+wire [0:29] sb_12__1__10_chany_top_out ;
+wire [0:0] sb_12__1__1_ccff_tail ;
+wire [0:29] sb_12__1__1_chanx_left_out ;
+wire [0:29] sb_12__1__1_chany_bottom_out ;
+wire [0:29] sb_12__1__1_chany_top_out ;
+wire [0:0] sb_12__1__2_ccff_tail ;
+wire [0:29] sb_12__1__2_chanx_left_out ;
+wire [0:29] sb_12__1__2_chany_bottom_out ;
+wire [0:29] sb_12__1__2_chany_top_out ;
+wire [0:0] sb_12__1__3_ccff_tail ;
+wire [0:29] sb_12__1__3_chanx_left_out ;
+wire [0:29] sb_12__1__3_chany_bottom_out ;
+wire [0:29] sb_12__1__3_chany_top_out ;
+wire [0:0] sb_12__1__4_ccff_tail ;
+wire [0:29] sb_12__1__4_chanx_left_out ;
+wire [0:29] sb_12__1__4_chany_bottom_out ;
+wire [0:29] sb_12__1__4_chany_top_out ;
+wire [0:0] sb_12__1__5_ccff_tail ;
+wire [0:29] sb_12__1__5_chanx_left_out ;
+wire [0:29] sb_12__1__5_chany_bottom_out ;
+wire [0:29] sb_12__1__5_chany_top_out ;
+wire [0:0] sb_12__1__6_ccff_tail ;
+wire [0:29] sb_12__1__6_chanx_left_out ;
+wire [0:29] sb_12__1__6_chany_bottom_out ;
+wire [0:29] sb_12__1__6_chany_top_out ;
+wire [0:0] sb_12__1__7_ccff_tail ;
+wire [0:29] sb_12__1__7_chanx_left_out ;
+wire [0:29] sb_12__1__7_chany_bottom_out ;
+wire [0:29] sb_12__1__7_chany_top_out ;
+wire [0:0] sb_12__1__8_ccff_tail ;
+wire [0:29] sb_12__1__8_chanx_left_out ;
+wire [0:29] sb_12__1__8_chany_bottom_out ;
+wire [0:29] sb_12__1__8_chany_top_out ;
+wire [0:0] sb_12__1__9_ccff_tail ;
+wire [0:29] sb_12__1__9_chanx_left_out ;
+wire [0:29] sb_12__1__9_chany_bottom_out ;
+wire [0:29] sb_12__1__9_chany_top_out ;
+wire [0:0] sb_1__0__0_ccff_tail ;
+wire [0:29] sb_1__0__0_chanx_left_out ;
+wire [0:29] sb_1__0__0_chanx_right_out ;
+wire [0:29] sb_1__0__0_chany_top_out ;
+wire [0:0] sb_1__0__10_ccff_tail ;
+wire [0:29] sb_1__0__10_chanx_left_out ;
+wire [0:29] sb_1__0__10_chanx_right_out ;
+wire [0:29] sb_1__0__10_chany_top_out ;
+wire [0:0] sb_1__0__1_ccff_tail ;
+wire [0:29] sb_1__0__1_chanx_left_out ;
+wire [0:29] sb_1__0__1_chanx_right_out ;
+wire [0:29] sb_1__0__1_chany_top_out ;
+wire [0:0] sb_1__0__2_ccff_tail ;
+wire [0:29] sb_1__0__2_chanx_left_out ;
+wire [0:29] sb_1__0__2_chanx_right_out ;
+wire [0:29] sb_1__0__2_chany_top_out ;
+wire [0:0] sb_1__0__3_ccff_tail ;
+wire [0:29] sb_1__0__3_chanx_left_out ;
+wire [0:29] sb_1__0__3_chanx_right_out ;
+wire [0:29] sb_1__0__3_chany_top_out ;
+wire [0:0] sb_1__0__4_ccff_tail ;
+wire [0:29] sb_1__0__4_chanx_left_out ;
+wire [0:29] sb_1__0__4_chanx_right_out ;
+wire [0:29] sb_1__0__4_chany_top_out ;
+wire [0:0] sb_1__0__5_ccff_tail ;
+wire [0:29] sb_1__0__5_chanx_left_out ;
+wire [0:29] sb_1__0__5_chanx_right_out ;
+wire [0:29] sb_1__0__5_chany_top_out ;
+wire [0:0] sb_1__0__6_ccff_tail ;
+wire [0:29] sb_1__0__6_chanx_left_out ;
+wire [0:29] sb_1__0__6_chanx_right_out ;
+wire [0:29] sb_1__0__6_chany_top_out ;
+wire [0:0] sb_1__0__7_ccff_tail ;
+wire [0:29] sb_1__0__7_chanx_left_out ;
+wire [0:29] sb_1__0__7_chanx_right_out ;
+wire [0:29] sb_1__0__7_chany_top_out ;
+wire [0:0] sb_1__0__8_ccff_tail ;
+wire [0:29] sb_1__0__8_chanx_left_out ;
+wire [0:29] sb_1__0__8_chanx_right_out ;
+wire [0:29] sb_1__0__8_chany_top_out ;
+wire [0:0] sb_1__0__9_ccff_tail ;
+wire [0:29] sb_1__0__9_chanx_left_out ;
+wire [0:29] sb_1__0__9_chanx_right_out ;
+wire [0:29] sb_1__0__9_chany_top_out ;
+wire [0:0] sb_1__12__0_ccff_tail ;
+wire [0:29] sb_1__12__0_chanx_left_out ;
+wire [0:29] sb_1__12__0_chanx_right_out ;
+wire [0:29] sb_1__12__0_chany_bottom_out ;
+wire [0:0] sb_1__12__10_ccff_tail ;
+wire [0:29] sb_1__12__10_chanx_left_out ;
+wire [0:29] sb_1__12__10_chanx_right_out ;
+wire [0:29] sb_1__12__10_chany_bottom_out ;
+wire [0:0] sb_1__12__1_ccff_tail ;
+wire [0:29] sb_1__12__1_chanx_left_out ;
+wire [0:29] sb_1__12__1_chanx_right_out ;
+wire [0:29] sb_1__12__1_chany_bottom_out ;
+wire [0:0] sb_1__12__2_ccff_tail ;
+wire [0:29] sb_1__12__2_chanx_left_out ;
+wire [0:29] sb_1__12__2_chanx_right_out ;
+wire [0:29] sb_1__12__2_chany_bottom_out ;
+wire [0:0] sb_1__12__3_ccff_tail ;
+wire [0:29] sb_1__12__3_chanx_left_out ;
+wire [0:29] sb_1__12__3_chanx_right_out ;
+wire [0:29] sb_1__12__3_chany_bottom_out ;
+wire [0:0] sb_1__12__4_ccff_tail ;
+wire [0:29] sb_1__12__4_chanx_left_out ;
+wire [0:29] sb_1__12__4_chanx_right_out ;
+wire [0:29] sb_1__12__4_chany_bottom_out ;
+wire [0:0] sb_1__12__5_ccff_tail ;
+wire [0:29] sb_1__12__5_chanx_left_out ;
+wire [0:29] sb_1__12__5_chanx_right_out ;
+wire [0:29] sb_1__12__5_chany_bottom_out ;
+wire [0:0] sb_1__12__6_ccff_tail ;
+wire [0:29] sb_1__12__6_chanx_left_out ;
+wire [0:29] sb_1__12__6_chanx_right_out ;
+wire [0:29] sb_1__12__6_chany_bottom_out ;
+wire [0:0] sb_1__12__7_ccff_tail ;
+wire [0:29] sb_1__12__7_chanx_left_out ;
+wire [0:29] sb_1__12__7_chanx_right_out ;
+wire [0:29] sb_1__12__7_chany_bottom_out ;
+wire [0:0] sb_1__12__8_ccff_tail ;
+wire [0:29] sb_1__12__8_chanx_left_out ;
+wire [0:29] sb_1__12__8_chanx_right_out ;
+wire [0:29] sb_1__12__8_chany_bottom_out ;
+wire [0:0] sb_1__12__9_ccff_tail ;
+wire [0:29] sb_1__12__9_chanx_left_out ;
+wire [0:29] sb_1__12__9_chanx_right_out ;
+wire [0:29] sb_1__12__9_chany_bottom_out ;
+wire [0:0] sb_1__1__0_ccff_tail ;
+wire [0:29] sb_1__1__0_chanx_left_out ;
+wire [0:29] sb_1__1__0_chanx_right_out ;
+wire [0:29] sb_1__1__0_chany_bottom_out ;
+wire [0:29] sb_1__1__0_chany_top_out ;
+wire [0:0] sb_1__1__100_ccff_tail ;
+wire [0:29] sb_1__1__100_chanx_left_out ;
+wire [0:29] sb_1__1__100_chanx_right_out ;
+wire [0:29] sb_1__1__100_chany_bottom_out ;
+wire [0:29] sb_1__1__100_chany_top_out ;
+wire [0:0] sb_1__1__101_ccff_tail ;
+wire [0:29] sb_1__1__101_chanx_left_out ;
+wire [0:29] sb_1__1__101_chanx_right_out ;
+wire [0:29] sb_1__1__101_chany_bottom_out ;
+wire [0:29] sb_1__1__101_chany_top_out ;
+wire [0:0] sb_1__1__102_ccff_tail ;
+wire [0:29] sb_1__1__102_chanx_left_out ;
+wire [0:29] sb_1__1__102_chanx_right_out ;
+wire [0:29] sb_1__1__102_chany_bottom_out ;
+wire [0:29] sb_1__1__102_chany_top_out ;
+wire [0:0] sb_1__1__103_ccff_tail ;
+wire [0:29] sb_1__1__103_chanx_left_out ;
+wire [0:29] sb_1__1__103_chanx_right_out ;
+wire [0:29] sb_1__1__103_chany_bottom_out ;
+wire [0:29] sb_1__1__103_chany_top_out ;
+wire [0:0] sb_1__1__104_ccff_tail ;
+wire [0:29] sb_1__1__104_chanx_left_out ;
+wire [0:29] sb_1__1__104_chanx_right_out ;
+wire [0:29] sb_1__1__104_chany_bottom_out ;
+wire [0:29] sb_1__1__104_chany_top_out ;
+wire [0:0] sb_1__1__105_ccff_tail ;
+wire [0:29] sb_1__1__105_chanx_left_out ;
+wire [0:29] sb_1__1__105_chanx_right_out ;
+wire [0:29] sb_1__1__105_chany_bottom_out ;
+wire [0:29] sb_1__1__105_chany_top_out ;
+wire [0:0] sb_1__1__106_ccff_tail ;
+wire [0:29] sb_1__1__106_chanx_left_out ;
+wire [0:29] sb_1__1__106_chanx_right_out ;
+wire [0:29] sb_1__1__106_chany_bottom_out ;
+wire [0:29] sb_1__1__106_chany_top_out ;
+wire [0:0] sb_1__1__107_ccff_tail ;
+wire [0:29] sb_1__1__107_chanx_left_out ;
+wire [0:29] sb_1__1__107_chanx_right_out ;
+wire [0:29] sb_1__1__107_chany_bottom_out ;
+wire [0:29] sb_1__1__107_chany_top_out ;
+wire [0:0] sb_1__1__108_ccff_tail ;
+wire [0:29] sb_1__1__108_chanx_left_out ;
+wire [0:29] sb_1__1__108_chanx_right_out ;
+wire [0:29] sb_1__1__108_chany_bottom_out ;
+wire [0:29] sb_1__1__108_chany_top_out ;
+wire [0:0] sb_1__1__109_ccff_tail ;
+wire [0:29] sb_1__1__109_chanx_left_out ;
+wire [0:29] sb_1__1__109_chanx_right_out ;
+wire [0:29] sb_1__1__109_chany_bottom_out ;
+wire [0:29] sb_1__1__109_chany_top_out ;
+wire [0:0] sb_1__1__10_ccff_tail ;
+wire [0:29] sb_1__1__10_chanx_left_out ;
+wire [0:29] sb_1__1__10_chanx_right_out ;
+wire [0:29] sb_1__1__10_chany_bottom_out ;
+wire [0:29] sb_1__1__10_chany_top_out ;
+wire [0:0] sb_1__1__110_ccff_tail ;
+wire [0:29] sb_1__1__110_chanx_left_out ;
+wire [0:29] sb_1__1__110_chanx_right_out ;
+wire [0:29] sb_1__1__110_chany_bottom_out ;
+wire [0:29] sb_1__1__110_chany_top_out ;
+wire [0:0] sb_1__1__111_ccff_tail ;
+wire [0:29] sb_1__1__111_chanx_left_out ;
+wire [0:29] sb_1__1__111_chanx_right_out ;
+wire [0:29] sb_1__1__111_chany_bottom_out ;
+wire [0:29] sb_1__1__111_chany_top_out ;
+wire [0:0] sb_1__1__112_ccff_tail ;
+wire [0:29] sb_1__1__112_chanx_left_out ;
+wire [0:29] sb_1__1__112_chanx_right_out ;
+wire [0:29] sb_1__1__112_chany_bottom_out ;
+wire [0:29] sb_1__1__112_chany_top_out ;
+wire [0:0] sb_1__1__113_ccff_tail ;
+wire [0:29] sb_1__1__113_chanx_left_out ;
+wire [0:29] sb_1__1__113_chanx_right_out ;
+wire [0:29] sb_1__1__113_chany_bottom_out ;
+wire [0:29] sb_1__1__113_chany_top_out ;
+wire [0:0] sb_1__1__114_ccff_tail ;
+wire [0:29] sb_1__1__114_chanx_left_out ;
+wire [0:29] sb_1__1__114_chanx_right_out ;
+wire [0:29] sb_1__1__114_chany_bottom_out ;
+wire [0:29] sb_1__1__114_chany_top_out ;
+wire [0:0] sb_1__1__115_ccff_tail ;
+wire [0:29] sb_1__1__115_chanx_left_out ;
+wire [0:29] sb_1__1__115_chanx_right_out ;
+wire [0:29] sb_1__1__115_chany_bottom_out ;
+wire [0:29] sb_1__1__115_chany_top_out ;
+wire [0:0] sb_1__1__116_ccff_tail ;
+wire [0:29] sb_1__1__116_chanx_left_out ;
+wire [0:29] sb_1__1__116_chanx_right_out ;
+wire [0:29] sb_1__1__116_chany_bottom_out ;
+wire [0:29] sb_1__1__116_chany_top_out ;
+wire [0:0] sb_1__1__117_ccff_tail ;
+wire [0:29] sb_1__1__117_chanx_left_out ;
+wire [0:29] sb_1__1__117_chanx_right_out ;
+wire [0:29] sb_1__1__117_chany_bottom_out ;
+wire [0:29] sb_1__1__117_chany_top_out ;
+wire [0:0] sb_1__1__118_ccff_tail ;
+wire [0:29] sb_1__1__118_chanx_left_out ;
+wire [0:29] sb_1__1__118_chanx_right_out ;
+wire [0:29] sb_1__1__118_chany_bottom_out ;
+wire [0:29] sb_1__1__118_chany_top_out ;
+wire [0:0] sb_1__1__119_ccff_tail ;
+wire [0:29] sb_1__1__119_chanx_left_out ;
+wire [0:29] sb_1__1__119_chanx_right_out ;
+wire [0:29] sb_1__1__119_chany_bottom_out ;
+wire [0:29] sb_1__1__119_chany_top_out ;
+wire [0:0] sb_1__1__11_ccff_tail ;
+wire [0:29] sb_1__1__11_chanx_left_out ;
+wire [0:29] sb_1__1__11_chanx_right_out ;
+wire [0:29] sb_1__1__11_chany_bottom_out ;
+wire [0:29] sb_1__1__11_chany_top_out ;
+wire [0:0] sb_1__1__120_ccff_tail ;
+wire [0:29] sb_1__1__120_chanx_left_out ;
+wire [0:29] sb_1__1__120_chanx_right_out ;
+wire [0:29] sb_1__1__120_chany_bottom_out ;
+wire [0:29] sb_1__1__120_chany_top_out ;
+wire [0:0] sb_1__1__12_ccff_tail ;
+wire [0:29] sb_1__1__12_chanx_left_out ;
+wire [0:29] sb_1__1__12_chanx_right_out ;
+wire [0:29] sb_1__1__12_chany_bottom_out ;
+wire [0:29] sb_1__1__12_chany_top_out ;
+wire [0:0] sb_1__1__13_ccff_tail ;
+wire [0:29] sb_1__1__13_chanx_left_out ;
+wire [0:29] sb_1__1__13_chanx_right_out ;
+wire [0:29] sb_1__1__13_chany_bottom_out ;
+wire [0:29] sb_1__1__13_chany_top_out ;
+wire [0:0] sb_1__1__14_ccff_tail ;
+wire [0:29] sb_1__1__14_chanx_left_out ;
+wire [0:29] sb_1__1__14_chanx_right_out ;
+wire [0:29] sb_1__1__14_chany_bottom_out ;
+wire [0:29] sb_1__1__14_chany_top_out ;
+wire [0:0] sb_1__1__15_ccff_tail ;
+wire [0:29] sb_1__1__15_chanx_left_out ;
+wire [0:29] sb_1__1__15_chanx_right_out ;
+wire [0:29] sb_1__1__15_chany_bottom_out ;
+wire [0:29] sb_1__1__15_chany_top_out ;
+wire [0:0] sb_1__1__16_ccff_tail ;
+wire [0:29] sb_1__1__16_chanx_left_out ;
+wire [0:29] sb_1__1__16_chanx_right_out ;
+wire [0:29] sb_1__1__16_chany_bottom_out ;
+wire [0:29] sb_1__1__16_chany_top_out ;
+wire [0:0] sb_1__1__17_ccff_tail ;
+wire [0:29] sb_1__1__17_chanx_left_out ;
+wire [0:29] sb_1__1__17_chanx_right_out ;
+wire [0:29] sb_1__1__17_chany_bottom_out ;
+wire [0:29] sb_1__1__17_chany_top_out ;
+wire [0:0] sb_1__1__18_ccff_tail ;
+wire [0:29] sb_1__1__18_chanx_left_out ;
+wire [0:29] sb_1__1__18_chanx_right_out ;
+wire [0:29] sb_1__1__18_chany_bottom_out ;
+wire [0:29] sb_1__1__18_chany_top_out ;
+wire [0:0] sb_1__1__19_ccff_tail ;
+wire [0:29] sb_1__1__19_chanx_left_out ;
+wire [0:29] sb_1__1__19_chanx_right_out ;
+wire [0:29] sb_1__1__19_chany_bottom_out ;
+wire [0:29] sb_1__1__19_chany_top_out ;
+wire [0:0] sb_1__1__1_ccff_tail ;
+wire [0:29] sb_1__1__1_chanx_left_out ;
+wire [0:29] sb_1__1__1_chanx_right_out ;
+wire [0:29] sb_1__1__1_chany_bottom_out ;
+wire [0:29] sb_1__1__1_chany_top_out ;
+wire [0:0] sb_1__1__20_ccff_tail ;
+wire [0:29] sb_1__1__20_chanx_left_out ;
+wire [0:29] sb_1__1__20_chanx_right_out ;
+wire [0:29] sb_1__1__20_chany_bottom_out ;
+wire [0:29] sb_1__1__20_chany_top_out ;
+wire [0:0] sb_1__1__21_ccff_tail ;
+wire [0:29] sb_1__1__21_chanx_left_out ;
+wire [0:29] sb_1__1__21_chanx_right_out ;
+wire [0:29] sb_1__1__21_chany_bottom_out ;
+wire [0:29] sb_1__1__21_chany_top_out ;
+wire [0:0] sb_1__1__22_ccff_tail ;
+wire [0:29] sb_1__1__22_chanx_left_out ;
+wire [0:29] sb_1__1__22_chanx_right_out ;
+wire [0:29] sb_1__1__22_chany_bottom_out ;
+wire [0:29] sb_1__1__22_chany_top_out ;
+wire [0:0] sb_1__1__23_ccff_tail ;
+wire [0:29] sb_1__1__23_chanx_left_out ;
+wire [0:29] sb_1__1__23_chanx_right_out ;
+wire [0:29] sb_1__1__23_chany_bottom_out ;
+wire [0:29] sb_1__1__23_chany_top_out ;
+wire [0:0] sb_1__1__24_ccff_tail ;
+wire [0:29] sb_1__1__24_chanx_left_out ;
+wire [0:29] sb_1__1__24_chanx_right_out ;
+wire [0:29] sb_1__1__24_chany_bottom_out ;
+wire [0:29] sb_1__1__24_chany_top_out ;
+wire [0:0] sb_1__1__25_ccff_tail ;
+wire [0:29] sb_1__1__25_chanx_left_out ;
+wire [0:29] sb_1__1__25_chanx_right_out ;
+wire [0:29] sb_1__1__25_chany_bottom_out ;
+wire [0:29] sb_1__1__25_chany_top_out ;
+wire [0:0] sb_1__1__26_ccff_tail ;
+wire [0:29] sb_1__1__26_chanx_left_out ;
+wire [0:29] sb_1__1__26_chanx_right_out ;
+wire [0:29] sb_1__1__26_chany_bottom_out ;
+wire [0:29] sb_1__1__26_chany_top_out ;
+wire [0:0] sb_1__1__27_ccff_tail ;
+wire [0:29] sb_1__1__27_chanx_left_out ;
+wire [0:29] sb_1__1__27_chanx_right_out ;
+wire [0:29] sb_1__1__27_chany_bottom_out ;
+wire [0:29] sb_1__1__27_chany_top_out ;
+wire [0:0] sb_1__1__28_ccff_tail ;
+wire [0:29] sb_1__1__28_chanx_left_out ;
+wire [0:29] sb_1__1__28_chanx_right_out ;
+wire [0:29] sb_1__1__28_chany_bottom_out ;
+wire [0:29] sb_1__1__28_chany_top_out ;
+wire [0:0] sb_1__1__29_ccff_tail ;
+wire [0:29] sb_1__1__29_chanx_left_out ;
+wire [0:29] sb_1__1__29_chanx_right_out ;
+wire [0:29] sb_1__1__29_chany_bottom_out ;
+wire [0:29] sb_1__1__29_chany_top_out ;
+wire [0:0] sb_1__1__2_ccff_tail ;
+wire [0:29] sb_1__1__2_chanx_left_out ;
+wire [0:29] sb_1__1__2_chanx_right_out ;
+wire [0:29] sb_1__1__2_chany_bottom_out ;
+wire [0:29] sb_1__1__2_chany_top_out ;
+wire [0:0] sb_1__1__30_ccff_tail ;
+wire [0:29] sb_1__1__30_chanx_left_out ;
+wire [0:29] sb_1__1__30_chanx_right_out ;
+wire [0:29] sb_1__1__30_chany_bottom_out ;
+wire [0:29] sb_1__1__30_chany_top_out ;
+wire [0:0] sb_1__1__31_ccff_tail ;
+wire [0:29] sb_1__1__31_chanx_left_out ;
+wire [0:29] sb_1__1__31_chanx_right_out ;
+wire [0:29] sb_1__1__31_chany_bottom_out ;
+wire [0:29] sb_1__1__31_chany_top_out ;
+wire [0:0] sb_1__1__32_ccff_tail ;
+wire [0:29] sb_1__1__32_chanx_left_out ;
+wire [0:29] sb_1__1__32_chanx_right_out ;
+wire [0:29] sb_1__1__32_chany_bottom_out ;
+wire [0:29] sb_1__1__32_chany_top_out ;
+wire [0:0] sb_1__1__33_ccff_tail ;
+wire [0:29] sb_1__1__33_chanx_left_out ;
+wire [0:29] sb_1__1__33_chanx_right_out ;
+wire [0:29] sb_1__1__33_chany_bottom_out ;
+wire [0:29] sb_1__1__33_chany_top_out ;
+wire [0:0] sb_1__1__34_ccff_tail ;
+wire [0:29] sb_1__1__34_chanx_left_out ;
+wire [0:29] sb_1__1__34_chanx_right_out ;
+wire [0:29] sb_1__1__34_chany_bottom_out ;
+wire [0:29] sb_1__1__34_chany_top_out ;
+wire [0:0] sb_1__1__35_ccff_tail ;
+wire [0:29] sb_1__1__35_chanx_left_out ;
+wire [0:29] sb_1__1__35_chanx_right_out ;
+wire [0:29] sb_1__1__35_chany_bottom_out ;
+wire [0:29] sb_1__1__35_chany_top_out ;
+wire [0:0] sb_1__1__36_ccff_tail ;
+wire [0:29] sb_1__1__36_chanx_left_out ;
+wire [0:29] sb_1__1__36_chanx_right_out ;
+wire [0:29] sb_1__1__36_chany_bottom_out ;
+wire [0:29] sb_1__1__36_chany_top_out ;
+wire [0:0] sb_1__1__37_ccff_tail ;
+wire [0:29] sb_1__1__37_chanx_left_out ;
+wire [0:29] sb_1__1__37_chanx_right_out ;
+wire [0:29] sb_1__1__37_chany_bottom_out ;
+wire [0:29] sb_1__1__37_chany_top_out ;
+wire [0:0] sb_1__1__38_ccff_tail ;
+wire [0:29] sb_1__1__38_chanx_left_out ;
+wire [0:29] sb_1__1__38_chanx_right_out ;
+wire [0:29] sb_1__1__38_chany_bottom_out ;
+wire [0:29] sb_1__1__38_chany_top_out ;
+wire [0:0] sb_1__1__39_ccff_tail ;
+wire [0:29] sb_1__1__39_chanx_left_out ;
+wire [0:29] sb_1__1__39_chanx_right_out ;
+wire [0:29] sb_1__1__39_chany_bottom_out ;
+wire [0:29] sb_1__1__39_chany_top_out ;
+wire [0:0] sb_1__1__3_ccff_tail ;
+wire [0:29] sb_1__1__3_chanx_left_out ;
+wire [0:29] sb_1__1__3_chanx_right_out ;
+wire [0:29] sb_1__1__3_chany_bottom_out ;
+wire [0:29] sb_1__1__3_chany_top_out ;
+wire [0:0] sb_1__1__40_ccff_tail ;
+wire [0:29] sb_1__1__40_chanx_left_out ;
+wire [0:29] sb_1__1__40_chanx_right_out ;
+wire [0:29] sb_1__1__40_chany_bottom_out ;
+wire [0:29] sb_1__1__40_chany_top_out ;
+wire [0:0] sb_1__1__41_ccff_tail ;
+wire [0:29] sb_1__1__41_chanx_left_out ;
+wire [0:29] sb_1__1__41_chanx_right_out ;
+wire [0:29] sb_1__1__41_chany_bottom_out ;
+wire [0:29] sb_1__1__41_chany_top_out ;
+wire [0:0] sb_1__1__42_ccff_tail ;
+wire [0:29] sb_1__1__42_chanx_left_out ;
+wire [0:29] sb_1__1__42_chanx_right_out ;
+wire [0:29] sb_1__1__42_chany_bottom_out ;
+wire [0:29] sb_1__1__42_chany_top_out ;
+wire [0:0] sb_1__1__43_ccff_tail ;
+wire [0:29] sb_1__1__43_chanx_left_out ;
+wire [0:29] sb_1__1__43_chanx_right_out ;
+wire [0:29] sb_1__1__43_chany_bottom_out ;
+wire [0:29] sb_1__1__43_chany_top_out ;
+wire [0:0] sb_1__1__44_ccff_tail ;
+wire [0:29] sb_1__1__44_chanx_left_out ;
+wire [0:29] sb_1__1__44_chanx_right_out ;
+wire [0:29] sb_1__1__44_chany_bottom_out ;
+wire [0:29] sb_1__1__44_chany_top_out ;
+wire [0:0] sb_1__1__45_ccff_tail ;
+wire [0:29] sb_1__1__45_chanx_left_out ;
+wire [0:29] sb_1__1__45_chanx_right_out ;
+wire [0:29] sb_1__1__45_chany_bottom_out ;
+wire [0:29] sb_1__1__45_chany_top_out ;
+wire [0:0] sb_1__1__46_ccff_tail ;
+wire [0:29] sb_1__1__46_chanx_left_out ;
+wire [0:29] sb_1__1__46_chanx_right_out ;
+wire [0:29] sb_1__1__46_chany_bottom_out ;
+wire [0:29] sb_1__1__46_chany_top_out ;
+wire [0:0] sb_1__1__47_ccff_tail ;
+wire [0:29] sb_1__1__47_chanx_left_out ;
+wire [0:29] sb_1__1__47_chanx_right_out ;
+wire [0:29] sb_1__1__47_chany_bottom_out ;
+wire [0:29] sb_1__1__47_chany_top_out ;
+wire [0:0] sb_1__1__48_ccff_tail ;
+wire [0:29] sb_1__1__48_chanx_left_out ;
+wire [0:29] sb_1__1__48_chanx_right_out ;
+wire [0:29] sb_1__1__48_chany_bottom_out ;
+wire [0:29] sb_1__1__48_chany_top_out ;
+wire [0:0] sb_1__1__49_ccff_tail ;
+wire [0:29] sb_1__1__49_chanx_left_out ;
+wire [0:29] sb_1__1__49_chanx_right_out ;
+wire [0:29] sb_1__1__49_chany_bottom_out ;
+wire [0:29] sb_1__1__49_chany_top_out ;
+wire [0:0] sb_1__1__4_ccff_tail ;
+wire [0:29] sb_1__1__4_chanx_left_out ;
+wire [0:29] sb_1__1__4_chanx_right_out ;
+wire [0:29] sb_1__1__4_chany_bottom_out ;
+wire [0:29] sb_1__1__4_chany_top_out ;
+wire [0:0] sb_1__1__50_ccff_tail ;
+wire [0:29] sb_1__1__50_chanx_left_out ;
+wire [0:29] sb_1__1__50_chanx_right_out ;
+wire [0:29] sb_1__1__50_chany_bottom_out ;
+wire [0:29] sb_1__1__50_chany_top_out ;
+wire [0:0] sb_1__1__51_ccff_tail ;
+wire [0:29] sb_1__1__51_chanx_left_out ;
+wire [0:29] sb_1__1__51_chanx_right_out ;
+wire [0:29] sb_1__1__51_chany_bottom_out ;
+wire [0:29] sb_1__1__51_chany_top_out ;
+wire [0:0] sb_1__1__52_ccff_tail ;
+wire [0:29] sb_1__1__52_chanx_left_out ;
+wire [0:29] sb_1__1__52_chanx_right_out ;
+wire [0:29] sb_1__1__52_chany_bottom_out ;
+wire [0:29] sb_1__1__52_chany_top_out ;
+wire [0:0] sb_1__1__53_ccff_tail ;
+wire [0:29] sb_1__1__53_chanx_left_out ;
+wire [0:29] sb_1__1__53_chanx_right_out ;
+wire [0:29] sb_1__1__53_chany_bottom_out ;
+wire [0:29] sb_1__1__53_chany_top_out ;
+wire [0:0] sb_1__1__54_ccff_tail ;
+wire [0:29] sb_1__1__54_chanx_left_out ;
+wire [0:29] sb_1__1__54_chanx_right_out ;
+wire [0:29] sb_1__1__54_chany_bottom_out ;
+wire [0:29] sb_1__1__54_chany_top_out ;
+wire [0:0] sb_1__1__55_ccff_tail ;
+wire [0:29] sb_1__1__55_chanx_left_out ;
+wire [0:29] sb_1__1__55_chanx_right_out ;
+wire [0:29] sb_1__1__55_chany_bottom_out ;
+wire [0:29] sb_1__1__55_chany_top_out ;
+wire [0:0] sb_1__1__56_ccff_tail ;
+wire [0:29] sb_1__1__56_chanx_left_out ;
+wire [0:29] sb_1__1__56_chanx_right_out ;
+wire [0:29] sb_1__1__56_chany_bottom_out ;
+wire [0:29] sb_1__1__56_chany_top_out ;
+wire [0:0] sb_1__1__57_ccff_tail ;
+wire [0:29] sb_1__1__57_chanx_left_out ;
+wire [0:29] sb_1__1__57_chanx_right_out ;
+wire [0:29] sb_1__1__57_chany_bottom_out ;
+wire [0:29] sb_1__1__57_chany_top_out ;
+wire [0:0] sb_1__1__58_ccff_tail ;
+wire [0:29] sb_1__1__58_chanx_left_out ;
+wire [0:29] sb_1__1__58_chanx_right_out ;
+wire [0:29] sb_1__1__58_chany_bottom_out ;
+wire [0:29] sb_1__1__58_chany_top_out ;
+wire [0:0] sb_1__1__59_ccff_tail ;
+wire [0:29] sb_1__1__59_chanx_left_out ;
+wire [0:29] sb_1__1__59_chanx_right_out ;
+wire [0:29] sb_1__1__59_chany_bottom_out ;
+wire [0:29] sb_1__1__59_chany_top_out ;
+wire [0:0] sb_1__1__5_ccff_tail ;
+wire [0:29] sb_1__1__5_chanx_left_out ;
+wire [0:29] sb_1__1__5_chanx_right_out ;
+wire [0:29] sb_1__1__5_chany_bottom_out ;
+wire [0:29] sb_1__1__5_chany_top_out ;
+wire [0:0] sb_1__1__60_ccff_tail ;
+wire [0:29] sb_1__1__60_chanx_left_out ;
+wire [0:29] sb_1__1__60_chanx_right_out ;
+wire [0:29] sb_1__1__60_chany_bottom_out ;
+wire [0:29] sb_1__1__60_chany_top_out ;
+wire [0:0] sb_1__1__61_ccff_tail ;
+wire [0:29] sb_1__1__61_chanx_left_out ;
+wire [0:29] sb_1__1__61_chanx_right_out ;
+wire [0:29] sb_1__1__61_chany_bottom_out ;
+wire [0:29] sb_1__1__61_chany_top_out ;
+wire [0:0] sb_1__1__62_ccff_tail ;
+wire [0:29] sb_1__1__62_chanx_left_out ;
+wire [0:29] sb_1__1__62_chanx_right_out ;
+wire [0:29] sb_1__1__62_chany_bottom_out ;
+wire [0:29] sb_1__1__62_chany_top_out ;
+wire [0:0] sb_1__1__63_ccff_tail ;
+wire [0:29] sb_1__1__63_chanx_left_out ;
+wire [0:29] sb_1__1__63_chanx_right_out ;
+wire [0:29] sb_1__1__63_chany_bottom_out ;
+wire [0:29] sb_1__1__63_chany_top_out ;
+wire [0:0] sb_1__1__64_ccff_tail ;
+wire [0:29] sb_1__1__64_chanx_left_out ;
+wire [0:29] sb_1__1__64_chanx_right_out ;
+wire [0:29] sb_1__1__64_chany_bottom_out ;
+wire [0:29] sb_1__1__64_chany_top_out ;
+wire [0:0] sb_1__1__65_ccff_tail ;
+wire [0:29] sb_1__1__65_chanx_left_out ;
+wire [0:29] sb_1__1__65_chanx_right_out ;
+wire [0:29] sb_1__1__65_chany_bottom_out ;
+wire [0:29] sb_1__1__65_chany_top_out ;
+wire [0:0] sb_1__1__66_ccff_tail ;
+wire [0:29] sb_1__1__66_chanx_left_out ;
+wire [0:29] sb_1__1__66_chanx_right_out ;
+wire [0:29] sb_1__1__66_chany_bottom_out ;
+wire [0:29] sb_1__1__66_chany_top_out ;
+wire [0:0] sb_1__1__67_ccff_tail ;
+wire [0:29] sb_1__1__67_chanx_left_out ;
+wire [0:29] sb_1__1__67_chanx_right_out ;
+wire [0:29] sb_1__1__67_chany_bottom_out ;
+wire [0:29] sb_1__1__67_chany_top_out ;
+wire [0:0] sb_1__1__68_ccff_tail ;
+wire [0:29] sb_1__1__68_chanx_left_out ;
+wire [0:29] sb_1__1__68_chanx_right_out ;
+wire [0:29] sb_1__1__68_chany_bottom_out ;
+wire [0:29] sb_1__1__68_chany_top_out ;
+wire [0:0] sb_1__1__69_ccff_tail ;
+wire [0:29] sb_1__1__69_chanx_left_out ;
+wire [0:29] sb_1__1__69_chanx_right_out ;
+wire [0:29] sb_1__1__69_chany_bottom_out ;
+wire [0:29] sb_1__1__69_chany_top_out ;
+wire [0:0] sb_1__1__6_ccff_tail ;
+wire [0:29] sb_1__1__6_chanx_left_out ;
+wire [0:29] sb_1__1__6_chanx_right_out ;
+wire [0:29] sb_1__1__6_chany_bottom_out ;
+wire [0:29] sb_1__1__6_chany_top_out ;
+wire [0:0] sb_1__1__70_ccff_tail ;
+wire [0:29] sb_1__1__70_chanx_left_out ;
+wire [0:29] sb_1__1__70_chanx_right_out ;
+wire [0:29] sb_1__1__70_chany_bottom_out ;
+wire [0:29] sb_1__1__70_chany_top_out ;
+wire [0:0] sb_1__1__71_ccff_tail ;
+wire [0:29] sb_1__1__71_chanx_left_out ;
+wire [0:29] sb_1__1__71_chanx_right_out ;
+wire [0:29] sb_1__1__71_chany_bottom_out ;
+wire [0:29] sb_1__1__71_chany_top_out ;
+wire [0:0] sb_1__1__72_ccff_tail ;
+wire [0:29] sb_1__1__72_chanx_left_out ;
+wire [0:29] sb_1__1__72_chanx_right_out ;
+wire [0:29] sb_1__1__72_chany_bottom_out ;
+wire [0:29] sb_1__1__72_chany_top_out ;
+wire [0:0] sb_1__1__73_ccff_tail ;
+wire [0:29] sb_1__1__73_chanx_left_out ;
+wire [0:29] sb_1__1__73_chanx_right_out ;
+wire [0:29] sb_1__1__73_chany_bottom_out ;
+wire [0:29] sb_1__1__73_chany_top_out ;
+wire [0:0] sb_1__1__74_ccff_tail ;
+wire [0:29] sb_1__1__74_chanx_left_out ;
+wire [0:29] sb_1__1__74_chanx_right_out ;
+wire [0:29] sb_1__1__74_chany_bottom_out ;
+wire [0:29] sb_1__1__74_chany_top_out ;
+wire [0:0] sb_1__1__75_ccff_tail ;
+wire [0:29] sb_1__1__75_chanx_left_out ;
+wire [0:29] sb_1__1__75_chanx_right_out ;
+wire [0:29] sb_1__1__75_chany_bottom_out ;
+wire [0:29] sb_1__1__75_chany_top_out ;
+wire [0:0] sb_1__1__76_ccff_tail ;
+wire [0:29] sb_1__1__76_chanx_left_out ;
+wire [0:29] sb_1__1__76_chanx_right_out ;
+wire [0:29] sb_1__1__76_chany_bottom_out ;
+wire [0:29] sb_1__1__76_chany_top_out ;
+wire [0:0] sb_1__1__77_ccff_tail ;
+wire [0:29] sb_1__1__77_chanx_left_out ;
+wire [0:29] sb_1__1__77_chanx_right_out ;
+wire [0:29] sb_1__1__77_chany_bottom_out ;
+wire [0:29] sb_1__1__77_chany_top_out ;
+wire [0:0] sb_1__1__78_ccff_tail ;
+wire [0:29] sb_1__1__78_chanx_left_out ;
+wire [0:29] sb_1__1__78_chanx_right_out ;
+wire [0:29] sb_1__1__78_chany_bottom_out ;
+wire [0:29] sb_1__1__78_chany_top_out ;
+wire [0:0] sb_1__1__79_ccff_tail ;
+wire [0:29] sb_1__1__79_chanx_left_out ;
+wire [0:29] sb_1__1__79_chanx_right_out ;
+wire [0:29] sb_1__1__79_chany_bottom_out ;
+wire [0:29] sb_1__1__79_chany_top_out ;
+wire [0:0] sb_1__1__7_ccff_tail ;
+wire [0:29] sb_1__1__7_chanx_left_out ;
+wire [0:29] sb_1__1__7_chanx_right_out ;
+wire [0:29] sb_1__1__7_chany_bottom_out ;
+wire [0:29] sb_1__1__7_chany_top_out ;
+wire [0:0] sb_1__1__80_ccff_tail ;
+wire [0:29] sb_1__1__80_chanx_left_out ;
+wire [0:29] sb_1__1__80_chanx_right_out ;
+wire [0:29] sb_1__1__80_chany_bottom_out ;
+wire [0:29] sb_1__1__80_chany_top_out ;
+wire [0:0] sb_1__1__81_ccff_tail ;
+wire [0:29] sb_1__1__81_chanx_left_out ;
+wire [0:29] sb_1__1__81_chanx_right_out ;
+wire [0:29] sb_1__1__81_chany_bottom_out ;
+wire [0:29] sb_1__1__81_chany_top_out ;
+wire [0:0] sb_1__1__82_ccff_tail ;
+wire [0:29] sb_1__1__82_chanx_left_out ;
+wire [0:29] sb_1__1__82_chanx_right_out ;
+wire [0:29] sb_1__1__82_chany_bottom_out ;
+wire [0:29] sb_1__1__82_chany_top_out ;
+wire [0:0] sb_1__1__83_ccff_tail ;
+wire [0:29] sb_1__1__83_chanx_left_out ;
+wire [0:29] sb_1__1__83_chanx_right_out ;
+wire [0:29] sb_1__1__83_chany_bottom_out ;
+wire [0:29] sb_1__1__83_chany_top_out ;
+wire [0:0] sb_1__1__84_ccff_tail ;
+wire [0:29] sb_1__1__84_chanx_left_out ;
+wire [0:29] sb_1__1__84_chanx_right_out ;
+wire [0:29] sb_1__1__84_chany_bottom_out ;
+wire [0:29] sb_1__1__84_chany_top_out ;
+wire [0:0] sb_1__1__85_ccff_tail ;
+wire [0:29] sb_1__1__85_chanx_left_out ;
+wire [0:29] sb_1__1__85_chanx_right_out ;
+wire [0:29] sb_1__1__85_chany_bottom_out ;
+wire [0:29] sb_1__1__85_chany_top_out ;
+wire [0:0] sb_1__1__86_ccff_tail ;
+wire [0:29] sb_1__1__86_chanx_left_out ;
+wire [0:29] sb_1__1__86_chanx_right_out ;
+wire [0:29] sb_1__1__86_chany_bottom_out ;
+wire [0:29] sb_1__1__86_chany_top_out ;
+wire [0:0] sb_1__1__87_ccff_tail ;
+wire [0:29] sb_1__1__87_chanx_left_out ;
+wire [0:29] sb_1__1__87_chanx_right_out ;
+wire [0:29] sb_1__1__87_chany_bottom_out ;
+wire [0:29] sb_1__1__87_chany_top_out ;
+wire [0:0] sb_1__1__88_ccff_tail ;
+wire [0:29] sb_1__1__88_chanx_left_out ;
+wire [0:29] sb_1__1__88_chanx_right_out ;
+wire [0:29] sb_1__1__88_chany_bottom_out ;
+wire [0:29] sb_1__1__88_chany_top_out ;
+wire [0:0] sb_1__1__89_ccff_tail ;
+wire [0:29] sb_1__1__89_chanx_left_out ;
+wire [0:29] sb_1__1__89_chanx_right_out ;
+wire [0:29] sb_1__1__89_chany_bottom_out ;
+wire [0:29] sb_1__1__89_chany_top_out ;
+wire [0:0] sb_1__1__8_ccff_tail ;
+wire [0:29] sb_1__1__8_chanx_left_out ;
+wire [0:29] sb_1__1__8_chanx_right_out ;
+wire [0:29] sb_1__1__8_chany_bottom_out ;
+wire [0:29] sb_1__1__8_chany_top_out ;
+wire [0:0] sb_1__1__90_ccff_tail ;
+wire [0:29] sb_1__1__90_chanx_left_out ;
+wire [0:29] sb_1__1__90_chanx_right_out ;
+wire [0:29] sb_1__1__90_chany_bottom_out ;
+wire [0:29] sb_1__1__90_chany_top_out ;
+wire [0:0] sb_1__1__91_ccff_tail ;
+wire [0:29] sb_1__1__91_chanx_left_out ;
+wire [0:29] sb_1__1__91_chanx_right_out ;
+wire [0:29] sb_1__1__91_chany_bottom_out ;
+wire [0:29] sb_1__1__91_chany_top_out ;
+wire [0:0] sb_1__1__92_ccff_tail ;
+wire [0:29] sb_1__1__92_chanx_left_out ;
+wire [0:29] sb_1__1__92_chanx_right_out ;
+wire [0:29] sb_1__1__92_chany_bottom_out ;
+wire [0:29] sb_1__1__92_chany_top_out ;
+wire [0:0] sb_1__1__93_ccff_tail ;
+wire [0:29] sb_1__1__93_chanx_left_out ;
+wire [0:29] sb_1__1__93_chanx_right_out ;
+wire [0:29] sb_1__1__93_chany_bottom_out ;
+wire [0:29] sb_1__1__93_chany_top_out ;
+wire [0:0] sb_1__1__94_ccff_tail ;
+wire [0:29] sb_1__1__94_chanx_left_out ;
+wire [0:29] sb_1__1__94_chanx_right_out ;
+wire [0:29] sb_1__1__94_chany_bottom_out ;
+wire [0:29] sb_1__1__94_chany_top_out ;
+wire [0:0] sb_1__1__95_ccff_tail ;
+wire [0:29] sb_1__1__95_chanx_left_out ;
+wire [0:29] sb_1__1__95_chanx_right_out ;
+wire [0:29] sb_1__1__95_chany_bottom_out ;
+wire [0:29] sb_1__1__95_chany_top_out ;
+wire [0:0] sb_1__1__96_ccff_tail ;
+wire [0:29] sb_1__1__96_chanx_left_out ;
+wire [0:29] sb_1__1__96_chanx_right_out ;
+wire [0:29] sb_1__1__96_chany_bottom_out ;
+wire [0:29] sb_1__1__96_chany_top_out ;
+wire [0:0] sb_1__1__97_ccff_tail ;
+wire [0:29] sb_1__1__97_chanx_left_out ;
+wire [0:29] sb_1__1__97_chanx_right_out ;
+wire [0:29] sb_1__1__97_chany_bottom_out ;
+wire [0:29] sb_1__1__97_chany_top_out ;
+wire [0:0] sb_1__1__98_ccff_tail ;
+wire [0:29] sb_1__1__98_chanx_left_out ;
+wire [0:29] sb_1__1__98_chanx_right_out ;
+wire [0:29] sb_1__1__98_chany_bottom_out ;
+wire [0:29] sb_1__1__98_chany_top_out ;
+wire [0:0] sb_1__1__99_ccff_tail ;
+wire [0:29] sb_1__1__99_chanx_left_out ;
+wire [0:29] sb_1__1__99_chanx_right_out ;
+wire [0:29] sb_1__1__99_chany_bottom_out ;
+wire [0:29] sb_1__1__99_chany_top_out ;
+wire [0:0] sb_1__1__9_ccff_tail ;
+wire [0:29] sb_1__1__9_chanx_left_out ;
+wire [0:29] sb_1__1__9_chanx_right_out ;
+wire [0:29] sb_1__1__9_chany_bottom_out ;
+wire [0:29] sb_1__1__9_chany_top_out ;
+wire [1:0] UNCONN ;
+wire [317:0] scff_Wires ;
+wire [132:0] regin_feedthrough_wires ;
+wire [132:0] regout_feedthrough_wires ;
+wire [132:0] cin_feedthrough_wires ;
+wire [132:0] cout_feedthrough_wires ;
+wire [287:0] Test_enWires ;
+wire [636:0] pResetWires ;
+wire [287:0] ResetWires ;
+wire [624:0] prog_clk_0_wires ;
+wire [251:0] prog_clk_1_wires ;
+wire [135:0] prog_clk_2_wires ;
+wire [100:0] prog_clk_3_wires ;
+wire [251:0] clk_1_wires ;
+wire [135:0] clk_2_wires ;
+wire [100:0] clk_3_wires ;
+
+grid_clb grid_clb_1__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[0] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[0] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_3 } ) ,
+ .ccff_head ( grid_io_left_0_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_0_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_0_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_0_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_0_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_0_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_0_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_0_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_0_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[23] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6 ) , .SC_OUT_BOT ( scff_Wires[25] ) ,
+ .Test_en_E_in ( Test_enWires[24] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9 ) ,
+ .pReset_N_in ( pResetWires[63] ) , .Reset_E_in ( ResetWires[24] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_10 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_11 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_12 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[4] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_13 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[0] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[1] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[3] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_14 ) ,
+ .clk_0_N_in ( clk_1_wires[4] ) , .clk_0_S_in ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+grid_clb grid_clb_1__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_16 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[1] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_17 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[1] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_18 } ) ,
+ .ccff_head ( grid_io_left_1_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_1_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_1_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_1_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_1_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_1_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_1_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_1_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_1_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[0] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_19 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[0] ) ,
+ .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[21] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_20 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_OUT_BOT ( scff_Wires[22] ) ,
+ .Test_en_E_in ( Test_enWires[46] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_22 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_23 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_24 ) ,
+ .pReset_N_in ( pResetWires[112] ) , .Reset_E_in ( ResetWires[46] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_25 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_26 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_27 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_28 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[3] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[6] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[7] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[9] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_29 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_30 ) , .clk_0_S_in ( clk_1_wires[3] ) ) ;
+grid_clb grid_clb_1__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_31 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[2] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_32 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[2] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_33 } ) ,
+ .ccff_head ( grid_io_left_2_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_2_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_2_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_2_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_2_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_2_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_2_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_2_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_2_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[1] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_34 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[1] ) ,
+ .ccff_tail ( grid_clb_2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[19] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , .SC_OUT_BOT ( scff_Wires[20] ) ,
+ .Test_en_E_in ( Test_enWires[68] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_37 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_38 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_39 ) ,
+ .pReset_N_in ( pResetWires[161] ) , .Reset_E_in ( ResetWires[68] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_40 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_41 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_42 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[11] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_43 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[11] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[12] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[14] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_44 ) ,
+ .clk_0_N_in ( clk_1_wires[11] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+grid_clb grid_clb_1__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_46 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[3] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_47 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[3] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_48 } ) ,
+ .ccff_head ( grid_io_left_3_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_3_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_3_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_3_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_3_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_3_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_3_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_3_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_3_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[2] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_49 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[2] ) ,
+ .ccff_tail ( grid_clb_3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[17] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires[18] ) ,
+ .Test_en_E_in ( Test_enWires[90] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_52 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_53 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_54 ) ,
+ .pReset_N_in ( pResetWires[210] ) , .Reset_E_in ( ResetWires[90] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_55 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_56 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_57 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_58 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[10] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[16] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[17] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[19] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_59 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_60 ) ,
+ .clk_0_S_in ( clk_1_wires[10] ) ) ;
+grid_clb grid_clb_1__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_61 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[4] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_62 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[4] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_63 } ) ,
+ .ccff_head ( grid_io_left_4_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_4_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_4_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_4_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_4_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_4_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_4_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_4_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_4_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_4_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_4_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_4_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_4_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_4_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_4_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_4_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_4_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_4_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_4_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_4_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_4_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_4_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_4_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_4_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_4_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_4_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_4_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_4_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_4_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_4_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_4_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_4_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_4_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[3] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_64 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[3] ) ,
+ .ccff_tail ( grid_clb_4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[15] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_65 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_66 ) , .SC_OUT_BOT ( scff_Wires[16] ) ,
+ .Test_en_E_in ( Test_enWires[112] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_67 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_68 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_69 ) ,
+ .pReset_N_in ( pResetWires[259] ) , .Reset_E_in ( ResetWires[112] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_70 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_71 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_72 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[18] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_73 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[21] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[22] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[24] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_74 ) ,
+ .clk_0_N_in ( clk_1_wires[18] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+grid_clb grid_clb_1__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_76 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[5] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_77 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[5] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_78 } ) ,
+ .ccff_head ( grid_io_left_5_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_5_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_5_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_5_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_5_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_5_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_5_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_5_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_5_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_5_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_5_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_5_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_5_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_5_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_5_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_5_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_5_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_5_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_5_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_5_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_5_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_5_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_5_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_5_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_5_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_5_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_5_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_5_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_5_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_5_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_5_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_5_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_5_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[4] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_79 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[4] ) ,
+ .ccff_tail ( grid_clb_5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[13] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_80 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_81 ) , .SC_OUT_BOT ( scff_Wires[14] ) ,
+ .Test_en_E_in ( Test_enWires[134] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_82 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_83 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_84 ) ,
+ .pReset_N_in ( pResetWires[308] ) , .Reset_E_in ( ResetWires[134] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_85 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_86 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_87 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_88 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[17] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[26] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[27] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[29] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_89 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_90 ) ,
+ .clk_0_S_in ( clk_1_wires[17] ) ) ;
+grid_clb grid_clb_1__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_91 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[6] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_92 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[6] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_93 } ) ,
+ .ccff_head ( grid_io_left_6_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_6_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_6_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_6_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_6_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_6_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_6_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_6_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_6_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_6_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_6_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_6_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_6_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_6_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_6_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_6_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_6_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_6_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_6_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_6_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_6_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_6_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_6_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_6_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_6_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_6_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_6_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_6_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_6_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_6_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_6_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_6_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_6_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[5] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_94 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[5] ) ,
+ .ccff_tail ( grid_clb_6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[11] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_95 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_96 ) , .SC_OUT_BOT ( scff_Wires[12] ) ,
+ .Test_en_E_in ( Test_enWires[156] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_97 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_98 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_99 ) ,
+ .pReset_N_in ( pResetWires[357] ) , .Reset_E_in ( ResetWires[156] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_100 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_101 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_102 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[25] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_103 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[31] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[32] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[34] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_104 ) ,
+ .clk_0_N_in ( clk_1_wires[25] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+grid_clb grid_clb_1__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_106 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[7] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_107 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[7] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_108 } ) ,
+ .ccff_head ( grid_io_left_7_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_7_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_7_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_7_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_7_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_7_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_7_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_7_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_7_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_7_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_7_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_7_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_7_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_7_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_7_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_7_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_7_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_7_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_7_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_7_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_7_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_7_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_7_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_7_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_7_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_7_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_7_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_7_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_7_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_7_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_7_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_7_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_7_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[6] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_109 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[6] ) ,
+ .ccff_tail ( grid_clb_7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[9] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_110 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_111 ) ,
+ .SC_OUT_BOT ( scff_Wires[10] ) , .Test_en_E_in ( Test_enWires[178] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_112 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_113 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_114 ) ,
+ .pReset_N_in ( pResetWires[406] ) , .Reset_E_in ( ResetWires[178] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_115 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_116 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_117 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_118 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[24] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[36] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[37] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[39] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_119 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_120 ) ,
+ .clk_0_S_in ( clk_1_wires[24] ) ) ;
+grid_clb grid_clb_1__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_121 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[8] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_122 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[8] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_123 } ) ,
+ .ccff_head ( grid_io_left_8_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_8_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_8_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_8_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_8_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_8_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_8_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_8_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_8_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_8_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_8_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_8_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_8_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_8_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_8_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_8_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_8_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_8_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_8_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_8_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_8_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_8_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_8_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_8_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_8_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_8_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_8_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_8_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_8_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_8_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_8_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_8_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_8_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[7] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_124 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[7] ) ,
+ .ccff_tail ( grid_clb_8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[7] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_125 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_126 ) , .SC_OUT_BOT ( scff_Wires[8] ) ,
+ .Test_en_E_in ( Test_enWires[200] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_127 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_128 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_129 ) ,
+ .pReset_N_in ( pResetWires[455] ) , .Reset_E_in ( ResetWires[200] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_130 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_131 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_132 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[32] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_133 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[41] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[42] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[44] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_134 ) ,
+ .clk_0_N_in ( clk_1_wires[32] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+grid_clb grid_clb_1__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_136 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[9] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_137 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[9] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_138 } ) ,
+ .ccff_head ( grid_io_left_9_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_9_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_9_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_9_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_9_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_9_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_9_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_9_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_9_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_9_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_9_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_9_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_9_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_9_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_9_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_9_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_9_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_9_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_9_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_9_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_9_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_9_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_9_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_9_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_9_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_9_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_9_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_9_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_9_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_9_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_9_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_9_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_9_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[8] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_139 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[8] ) ,
+ .ccff_tail ( grid_clb_9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[5] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_140 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_141 ) , .SC_OUT_BOT ( scff_Wires[6] ) ,
+ .Test_en_E_in ( Test_enWires[222] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_142 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_143 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_144 ) ,
+ .pReset_N_in ( pResetWires[504] ) , .Reset_E_in ( ResetWires[222] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_145 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_146 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_147 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_148 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[31] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[46] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[47] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[49] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_149 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_150 ) ,
+ .clk_0_S_in ( clk_1_wires[31] ) ) ;
+grid_clb grid_clb_1__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_151 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[10] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_152 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[10] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_153 } ) ,
+ .ccff_head ( grid_io_left_10_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_10_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_10_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_10_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_10_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_10_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_10_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_10_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_10_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_10_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_10_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_10_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_10_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_10_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_10_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_10_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_10_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_10_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_10_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_10_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_10_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_10_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_10_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_10_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_10_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_10_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_10_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_10_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_10_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_10_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_10_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_10_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_10_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[9] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_154 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[9] ) ,
+ .ccff_tail ( grid_clb_10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[3] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_155 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_156 ) , .SC_OUT_BOT ( scff_Wires[4] ) ,
+ .Test_en_E_in ( Test_enWires[244] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_157 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_158 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_159 ) ,
+ .pReset_N_in ( pResetWires[553] ) , .Reset_E_in ( ResetWires[244] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_160 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_161 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_162 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[39] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_163 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[51] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[52] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[54] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_164 ) ,
+ .clk_0_N_in ( clk_1_wires[39] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+grid_clb grid_clb_1__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_166 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_167 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_168 } ) ,
+ .ccff_head ( grid_io_left_11_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_11_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_11_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_11_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_11_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_11_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_11_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_11_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_11_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_11_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_11_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_11_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_11_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_11_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_11_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_11_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_11_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_11_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_11_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_11_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_11_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_11_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_11_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_11_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_11_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_11_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_11_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_11_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_11_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_11_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_11_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_11_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_11_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[10] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_169 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[10] ) ,
+ .ccff_tail ( grid_clb_11_ccff_tail ) , .SC_IN_TOP ( scff_Wires[1] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_170 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_171 ) , .SC_OUT_BOT ( scff_Wires[2] ) ,
+ .Test_en_E_in ( Test_enWires[266] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_172 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_173 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_174 ) ,
+ .pReset_N_in ( pResetWires[602] ) , .Reset_E_in ( ResetWires[266] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_175 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_176 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_177 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_178 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[38] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[56] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[57] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[61] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[59] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_179 ) ,
+ .clk_0_S_in ( clk_1_wires[38] ) ) ;
+grid_clb grid_clb_2__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_180 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[11] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_181 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[11] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_182 } ) ,
+ .ccff_head ( cby_1__1__0_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_12_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_12_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_12_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_12_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_12_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_12_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_12_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_12_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_12_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_12_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_12_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_12_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_12_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_12_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_12_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_12_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_12_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_12_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_12_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_12_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_12_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_12_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_12_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_12_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_12_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_12_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_12_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_12_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_12_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_12_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_12_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_12_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_183 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_12_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_184 ) , .SC_IN_BOT ( scff_Wires[28] ) ,
+ .SC_OUT_TOP ( scff_Wires[29] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_185 ) ,
+ .Test_en_E_in ( Test_enWires[25] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_186 ) ,
+ .Test_en_W_out ( Test_enWires[26] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_187 ) ,
+ .pReset_N_in ( pResetWires[68] ) , .Reset_E_in ( ResetWires[25] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_188 ) ,
+ .Reset_W_out ( ResetWires[26] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_189 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[6] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_190 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[63] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[64] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_191 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_192 ) ,
+ .clk_0_N_in ( clk_1_wires[6] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+grid_clb grid_clb_2__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_194 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[12] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_195 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[12] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_196 } ) ,
+ .ccff_head ( cby_1__1__1_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_13_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_13_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_13_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_13_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_13_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_13_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_13_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_13_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_13_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_13_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_13_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_13_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_13_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_13_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_13_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_13_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_13_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_13_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_13_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_13_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_13_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_13_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_13_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_13_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_13_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_13_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_13_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_13_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_13_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_13_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_13_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_13_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[11] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_197 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[11] ) ,
+ .ccff_tail ( grid_clb_13_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_198 ) , .SC_IN_BOT ( scff_Wires[30] ) ,
+ .SC_OUT_TOP ( scff_Wires[31] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_199 ) ,
+ .Test_en_E_in ( Test_enWires[47] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_200 ) ,
+ .Test_en_W_out ( Test_enWires[48] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_201 ) ,
+ .pReset_N_in ( pResetWires[117] ) , .Reset_E_in ( ResetWires[47] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_202 ) ,
+ .Reset_W_out ( ResetWires[48] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_203 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_204 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[5] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[66] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[67] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_205 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_206 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_207 ) ,
+ .clk_0_S_in ( clk_1_wires[5] ) ) ;
+grid_clb grid_clb_2__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_208 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[13] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_209 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[13] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_210 } ) ,
+ .ccff_head ( cby_1__1__2_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_14_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_14_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_14_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_14_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_14_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_14_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_14_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_14_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_14_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_14_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_14_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_14_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_14_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_14_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_14_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_14_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_14_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_14_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_14_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_14_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_14_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_14_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_14_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_14_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_14_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_14_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_14_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_14_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_14_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_14_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_14_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_14_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[12] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_211 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[12] ) ,
+ .ccff_tail ( grid_clb_14_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_212 ) , .SC_IN_BOT ( scff_Wires[32] ) ,
+ .SC_OUT_TOP ( scff_Wires[33] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_213 ) ,
+ .Test_en_E_in ( Test_enWires[69] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_214 ) ,
+ .Test_en_W_out ( Test_enWires[70] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_215 ) ,
+ .pReset_N_in ( pResetWires[166] ) , .Reset_E_in ( ResetWires[69] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_216 ) ,
+ .Reset_W_out ( ResetWires[70] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_217 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[13] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_218 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[69] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[70] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_219 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_220 ) ,
+ .clk_0_N_in ( clk_1_wires[13] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+grid_clb grid_clb_2__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_222 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[14] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_223 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[14] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_224 } ) ,
+ .ccff_head ( cby_1__1__3_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_15_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_15_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_15_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_15_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_15_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_15_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_15_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_15_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_15_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_15_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_15_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_15_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_15_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_15_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_15_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_15_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_15_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_15_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_15_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_15_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_15_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_15_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_15_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_15_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_15_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_15_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_15_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_15_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_15_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_15_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_15_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_15_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[13] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_225 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[13] ) ,
+ .ccff_tail ( grid_clb_15_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_226 ) , .SC_IN_BOT ( scff_Wires[34] ) ,
+ .SC_OUT_TOP ( scff_Wires[35] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_227 ) ,
+ .Test_en_E_in ( Test_enWires[91] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_228 ) ,
+ .Test_en_W_out ( Test_enWires[92] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_229 ) ,
+ .pReset_N_in ( pResetWires[215] ) , .Reset_E_in ( ResetWires[91] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_230 ) ,
+ .Reset_W_out ( ResetWires[92] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_231 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_232 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[12] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[72] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[73] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_233 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_234 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_235 ) ,
+ .clk_0_S_in ( clk_1_wires[12] ) ) ;
+grid_clb grid_clb_2__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_236 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[15] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_237 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[15] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_238 } ) ,
+ .ccff_head ( cby_1__1__4_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_16_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_16_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_16_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_16_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_16_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_16_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_16_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_16_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_16_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_16_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_16_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_16_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_16_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_16_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_16_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_16_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_16_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_16_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_16_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_16_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_16_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_16_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_16_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_16_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_16_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_16_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_16_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_16_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_16_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_16_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_16_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_16_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[14] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_239 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[14] ) ,
+ .ccff_tail ( grid_clb_16_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_240 ) , .SC_IN_BOT ( scff_Wires[36] ) ,
+ .SC_OUT_TOP ( scff_Wires[37] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_241 ) ,
+ .Test_en_E_in ( Test_enWires[113] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_242 ) ,
+ .Test_en_W_out ( Test_enWires[114] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_243 ) ,
+ .pReset_N_in ( pResetWires[264] ) , .Reset_E_in ( ResetWires[113] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_244 ) ,
+ .Reset_W_out ( ResetWires[114] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_245 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[20] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_246 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[75] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[76] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_247 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_248 ) ,
+ .clk_0_N_in ( clk_1_wires[20] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+grid_clb grid_clb_2__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_250 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[16] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_251 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[16] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_252 } ) ,
+ .ccff_head ( cby_1__1__5_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_17_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_17_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_17_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_17_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_17_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_17_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_17_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_17_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_17_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_17_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_17_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_17_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_17_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_17_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_17_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_17_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_17_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_17_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_17_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_17_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_17_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_17_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_17_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_17_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_17_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_17_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_17_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_17_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_17_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_17_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_17_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_17_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[15] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_253 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[15] ) ,
+ .ccff_tail ( grid_clb_17_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_254 ) , .SC_IN_BOT ( scff_Wires[38] ) ,
+ .SC_OUT_TOP ( scff_Wires[39] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_255 ) ,
+ .Test_en_E_in ( Test_enWires[135] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_256 ) ,
+ .Test_en_W_out ( Test_enWires[136] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_257 ) ,
+ .pReset_N_in ( pResetWires[313] ) , .Reset_E_in ( ResetWires[135] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_258 ) ,
+ .Reset_W_out ( ResetWires[136] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_259 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_260 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[19] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[78] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[79] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_261 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_262 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_263 ) ,
+ .clk_0_S_in ( clk_1_wires[19] ) ) ;
+grid_clb grid_clb_2__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_264 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[17] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_265 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[17] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_266 } ) ,
+ .ccff_head ( cby_1__1__6_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_18_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_18_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_18_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_18_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_18_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_18_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_18_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_18_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_18_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_18_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_18_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_18_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_18_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_18_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_18_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_18_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_18_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_18_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_18_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_18_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_18_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_18_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_18_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_18_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_18_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_18_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_18_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_18_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_18_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_18_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_18_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_18_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[16] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_267 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[16] ) ,
+ .ccff_tail ( grid_clb_18_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_268 ) , .SC_IN_BOT ( scff_Wires[40] ) ,
+ .SC_OUT_TOP ( scff_Wires[41] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_269 ) ,
+ .Test_en_E_in ( Test_enWires[157] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_270 ) ,
+ .Test_en_W_out ( Test_enWires[158] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_271 ) ,
+ .pReset_N_in ( pResetWires[362] ) , .Reset_E_in ( ResetWires[157] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_272 ) ,
+ .Reset_W_out ( ResetWires[158] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_273 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[27] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_274 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[81] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[82] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_275 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_276 ) ,
+ .clk_0_N_in ( clk_1_wires[27] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+grid_clb grid_clb_2__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_278 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[18] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_279 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[18] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_280 } ) ,
+ .ccff_head ( cby_1__1__7_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_19_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_19_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_19_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_19_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_19_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_19_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_19_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_19_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_19_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_19_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_19_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_19_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_19_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_19_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_19_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_19_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_19_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_19_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_19_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_19_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_19_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_19_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_19_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_19_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_19_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_19_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_19_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_19_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_19_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_19_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_19_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_19_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[17] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_281 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[17] ) ,
+ .ccff_tail ( grid_clb_19_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_282 ) , .SC_IN_BOT ( scff_Wires[42] ) ,
+ .SC_OUT_TOP ( scff_Wires[43] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_283 ) ,
+ .Test_en_E_in ( Test_enWires[179] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_284 ) ,
+ .Test_en_W_out ( Test_enWires[180] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_285 ) ,
+ .pReset_N_in ( pResetWires[411] ) , .Reset_E_in ( ResetWires[179] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_286 ) ,
+ .Reset_W_out ( ResetWires[180] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_287 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_288 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[26] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[84] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[85] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_289 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_290 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_291 ) ,
+ .clk_0_S_in ( clk_1_wires[26] ) ) ;
+grid_clb grid_clb_2__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_292 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[19] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_293 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[19] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_294 } ) ,
+ .ccff_head ( cby_1__1__8_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_20_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_20_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_20_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_20_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_20_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_20_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_20_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_20_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_20_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_20_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_20_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_20_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_20_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_20_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_20_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_20_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_20_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_20_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_20_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_20_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_20_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_20_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_20_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_20_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_20_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_20_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_20_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_20_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_20_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_20_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_20_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_20_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[18] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_295 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[18] ) ,
+ .ccff_tail ( grid_clb_20_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_296 ) , .SC_IN_BOT ( scff_Wires[44] ) ,
+ .SC_OUT_TOP ( scff_Wires[45] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_297 ) ,
+ .Test_en_E_in ( Test_enWires[201] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_298 ) ,
+ .Test_en_W_out ( Test_enWires[202] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_299 ) ,
+ .pReset_N_in ( pResetWires[460] ) , .Reset_E_in ( ResetWires[201] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_300 ) ,
+ .Reset_W_out ( ResetWires[202] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_301 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[34] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_302 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[87] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[88] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_303 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_304 ) ,
+ .clk_0_N_in ( clk_1_wires[34] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+grid_clb grid_clb_2__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_306 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[20] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_307 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[20] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_308 } ) ,
+ .ccff_head ( cby_1__1__9_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_21_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_21_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_21_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_21_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_21_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_21_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_21_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_21_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_21_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_21_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_21_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_21_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_21_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_21_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_21_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_21_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_21_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_21_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_21_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_21_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_21_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_21_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_21_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_21_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_21_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_21_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_21_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_21_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_21_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_21_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_21_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_21_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[19] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_309 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[19] ) ,
+ .ccff_tail ( grid_clb_21_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_310 ) , .SC_IN_BOT ( scff_Wires[46] ) ,
+ .SC_OUT_TOP ( scff_Wires[47] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_311 ) ,
+ .Test_en_E_in ( Test_enWires[223] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_312 ) ,
+ .Test_en_W_out ( Test_enWires[224] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_313 ) ,
+ .pReset_N_in ( pResetWires[509] ) , .Reset_E_in ( ResetWires[223] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_314 ) ,
+ .Reset_W_out ( ResetWires[224] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_315 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_316 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[33] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[90] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[91] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_317 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_318 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_319 ) ,
+ .clk_0_S_in ( clk_1_wires[33] ) ) ;
+grid_clb grid_clb_2__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_320 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[21] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_321 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[21] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_322 } ) ,
+ .ccff_head ( cby_1__1__10_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_22_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_22_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_22_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_22_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_22_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_22_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_22_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_22_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_22_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_22_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_22_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_22_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_22_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_22_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_22_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_22_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_22_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_22_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_22_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_22_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_22_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_22_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_22_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_22_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_22_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_22_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_22_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_22_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_22_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_22_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_22_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_22_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[20] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_323 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[20] ) ,
+ .ccff_tail ( grid_clb_22_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_324 ) , .SC_IN_BOT ( scff_Wires[48] ) ,
+ .SC_OUT_TOP ( scff_Wires[49] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_325 ) ,
+ .Test_en_E_in ( Test_enWires[245] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_326 ) ,
+ .Test_en_W_out ( Test_enWires[246] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_327 ) ,
+ .pReset_N_in ( pResetWires[558] ) , .Reset_E_in ( ResetWires[245] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_328 ) ,
+ .Reset_W_out ( ResetWires[246] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_329 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[41] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_330 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[93] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[94] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_331 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_332 ) ,
+ .clk_0_N_in ( clk_1_wires[41] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+grid_clb grid_clb_2__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_334 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_335 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_336 } ) ,
+ .ccff_head ( cby_1__1__11_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_23_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_23_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_23_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_23_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_23_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_23_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_23_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_23_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_23_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_23_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_23_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_23_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_23_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_23_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_23_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_23_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_23_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_23_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_23_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_23_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_23_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_23_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_23_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_23_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_23_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_23_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_23_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_23_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_23_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_23_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_23_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_23_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[21] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_337 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[21] ) ,
+ .ccff_tail ( grid_clb_23_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_338 ) , .SC_IN_BOT ( scff_Wires[50] ) ,
+ .SC_OUT_TOP ( scff_Wires[51] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_339 ) ,
+ .Test_en_E_in ( Test_enWires[267] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_340 ) ,
+ .Test_en_W_out ( Test_enWires[268] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_341 ) ,
+ .pReset_N_in ( pResetWires[606] ) , .Reset_E_in ( ResetWires[267] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_342 ) ,
+ .Reset_W_out ( ResetWires[268] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_343 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_344 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[40] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[96] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[97] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_345 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[99] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_346 ) ,
+ .clk_0_S_in ( clk_1_wires[40] ) ) ;
+grid_clb grid_clb_3__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_347 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[22] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_348 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[22] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_349 } ) ,
+ .ccff_head ( cby_1__1__12_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_24_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_24_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_24_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_24_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_24_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_24_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_24_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_24_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_24_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_24_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_24_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_24_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_24_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_24_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_24_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_24_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_24_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_24_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_24_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_24_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_24_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_24_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_24_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_24_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_24_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_24_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_24_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_24_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_24_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_24_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_24_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_24_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_350 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[76] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_351 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_352 ) ,
+ .SC_OUT_BOT ( scff_Wires[78] ) , .Test_en_E_in ( Test_enWires[27] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_353 ) ,
+ .Test_en_W_out ( Test_enWires[28] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_354 ) ,
+ .pReset_N_in ( pResetWires[72] ) , .Reset_E_in ( ResetWires[27] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_355 ) ,
+ .Reset_W_out ( ResetWires[28] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_356 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[46] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_357 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[101] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[102] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_358 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_359 ) ,
+ .clk_0_N_in ( clk_1_wires[46] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+grid_clb grid_clb_3__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_361 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[23] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_362 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[23] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_363 } ) ,
+ .ccff_head ( cby_1__1__13_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_25_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_25_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_25_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_25_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_25_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_25_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_25_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_25_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_25_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_25_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_25_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_25_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_25_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_25_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_25_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_25_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_25_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_25_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_25_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_25_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_25_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_25_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_25_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_25_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_25_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_25_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_25_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_25_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_25_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_25_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_25_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_25_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[22] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_364 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[22] ) ,
+ .ccff_tail ( grid_clb_25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[74] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_365 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_366 ) ,
+ .SC_OUT_BOT ( scff_Wires[75] ) , .Test_en_E_in ( Test_enWires[49] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_367 ) ,
+ .Test_en_W_out ( Test_enWires[50] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_368 ) ,
+ .pReset_N_in ( pResetWires[121] ) , .Reset_E_in ( ResetWires[49] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_369 ) ,
+ .Reset_W_out ( ResetWires[50] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_370 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_371 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[45] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[104] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[105] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_372 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_373 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_374 ) ,
+ .clk_0_S_in ( clk_1_wires[45] ) ) ;
+grid_clb grid_clb_3__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_375 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[24] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_376 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[24] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_377 } ) ,
+ .ccff_head ( cby_1__1__14_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_26_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_26_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_26_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_26_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_26_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_26_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_26_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_26_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_26_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_26_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_26_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_26_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_26_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_26_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_26_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_26_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_26_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_26_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_26_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_26_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_26_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_26_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_26_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_26_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_26_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_26_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_26_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_26_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_26_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_26_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_26_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_26_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[23] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_378 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[23] ) ,
+ .ccff_tail ( grid_clb_26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[72] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_379 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_380 ) ,
+ .SC_OUT_BOT ( scff_Wires[73] ) , .Test_en_E_in ( Test_enWires[71] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_381 ) ,
+ .Test_en_W_out ( Test_enWires[72] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_382 ) ,
+ .pReset_N_in ( pResetWires[170] ) , .Reset_E_in ( ResetWires[71] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_383 ) ,
+ .Reset_W_out ( ResetWires[72] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_384 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[53] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_385 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[107] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[108] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_386 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_387 ) ,
+ .clk_0_N_in ( clk_1_wires[53] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+grid_clb grid_clb_3__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_389 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[25] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_390 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[25] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_391 } ) ,
+ .ccff_head ( cby_1__1__15_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_27_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_27_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_27_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_27_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_27_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_27_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_27_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_27_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_27_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_27_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_27_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_27_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_27_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_27_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_27_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_27_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_27_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_27_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_27_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_27_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_27_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_27_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_27_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_27_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_27_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_27_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_27_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_27_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_27_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_27_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_27_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_27_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[24] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_392 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[24] ) ,
+ .ccff_tail ( grid_clb_27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[70] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_393 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_394 ) ,
+ .SC_OUT_BOT ( scff_Wires[71] ) , .Test_en_E_in ( Test_enWires[93] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_395 ) ,
+ .Test_en_W_out ( Test_enWires[94] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_396 ) ,
+ .pReset_N_in ( pResetWires[219] ) , .Reset_E_in ( ResetWires[93] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_397 ) ,
+ .Reset_W_out ( ResetWires[94] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_398 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_399 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[52] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[110] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[111] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_400 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_401 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_402 ) ,
+ .clk_0_S_in ( clk_1_wires[52] ) ) ;
+grid_clb grid_clb_3__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_403 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[26] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_404 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[26] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_405 } ) ,
+ .ccff_head ( cby_1__1__16_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_28_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_28_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_28_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_28_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_28_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_28_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_28_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_28_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_28_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_28_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_28_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_28_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_28_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_28_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_28_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_28_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_28_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_28_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_28_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_28_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_28_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_28_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_28_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_28_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_28_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_28_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_28_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_28_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_28_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_28_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_28_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_28_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[25] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_406 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[25] ) ,
+ .ccff_tail ( grid_clb_28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[68] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_407 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_408 ) ,
+ .SC_OUT_BOT ( scff_Wires[69] ) , .Test_en_E_in ( Test_enWires[115] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_409 ) ,
+ .Test_en_W_out ( Test_enWires[116] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_410 ) ,
+ .pReset_N_in ( pResetWires[268] ) , .Reset_E_in ( ResetWires[115] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_411 ) ,
+ .Reset_W_out ( ResetWires[116] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_412 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[60] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_413 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[113] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[114] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_414 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_415 ) ,
+ .clk_0_N_in ( clk_1_wires[60] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+grid_clb grid_clb_3__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_417 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[27] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_418 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[27] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_419 } ) ,
+ .ccff_head ( cby_1__1__17_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_29_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_29_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_29_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_29_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_29_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_29_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_29_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_29_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_29_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_29_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_29_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_29_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_29_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_29_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_29_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_29_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_29_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_29_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_29_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_29_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_29_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_29_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_29_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_29_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_29_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_29_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_29_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_29_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_29_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_29_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_29_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_29_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[26] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_420 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[26] ) ,
+ .ccff_tail ( grid_clb_29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[66] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_421 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_422 ) ,
+ .SC_OUT_BOT ( scff_Wires[67] ) , .Test_en_E_in ( Test_enWires[137] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_423 ) ,
+ .Test_en_W_out ( Test_enWires[138] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_424 ) ,
+ .pReset_N_in ( pResetWires[317] ) , .Reset_E_in ( ResetWires[137] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_425 ) ,
+ .Reset_W_out ( ResetWires[138] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_426 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_427 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[59] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[116] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[117] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_428 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_429 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_430 ) ,
+ .clk_0_S_in ( clk_1_wires[59] ) ) ;
+grid_clb grid_clb_3__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_431 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[28] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_432 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[28] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_433 } ) ,
+ .ccff_head ( cby_1__1__18_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_30_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_30_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_30_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_30_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_30_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_30_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_30_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_30_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_30_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_30_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_30_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_30_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_30_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_30_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_30_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_30_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_30_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_30_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_30_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_30_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_30_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_30_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_30_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_30_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_30_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_30_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_30_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_30_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_30_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_30_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_30_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_30_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[27] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_434 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[27] ) ,
+ .ccff_tail ( grid_clb_30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[64] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_435 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_436 ) ,
+ .SC_OUT_BOT ( scff_Wires[65] ) , .Test_en_E_in ( Test_enWires[159] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_437 ) ,
+ .Test_en_W_out ( Test_enWires[160] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_438 ) ,
+ .pReset_N_in ( pResetWires[366] ) , .Reset_E_in ( ResetWires[159] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_439 ) ,
+ .Reset_W_out ( ResetWires[160] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_440 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[67] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_441 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[119] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[120] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_442 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_443 ) ,
+ .clk_0_N_in ( clk_1_wires[67] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+grid_clb grid_clb_3__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_445 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[29] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_446 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[29] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_447 } ) ,
+ .ccff_head ( cby_1__1__19_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_31_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_31_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_31_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_31_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_31_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_31_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_31_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_31_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_31_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_31_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_31_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_31_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_31_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_31_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_31_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_31_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_31_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_31_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_31_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_31_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_31_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_31_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_31_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_31_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_31_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_31_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_31_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_31_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_31_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_31_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_31_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_31_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[28] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_448 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[28] ) ,
+ .ccff_tail ( grid_clb_31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[62] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_449 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_450 ) ,
+ .SC_OUT_BOT ( scff_Wires[63] ) , .Test_en_E_in ( Test_enWires[181] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_451 ) ,
+ .Test_en_W_out ( Test_enWires[182] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_452 ) ,
+ .pReset_N_in ( pResetWires[415] ) , .Reset_E_in ( ResetWires[181] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_453 ) ,
+ .Reset_W_out ( ResetWires[182] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_454 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_455 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[66] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[122] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[123] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_456 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_457 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_458 ) ,
+ .clk_0_S_in ( clk_1_wires[66] ) ) ;
+grid_clb grid_clb_3__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_459 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[30] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_460 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[30] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_461 } ) ,
+ .ccff_head ( cby_1__1__20_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_32_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_32_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_32_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_32_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_32_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_32_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_32_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_32_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_32_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_32_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_32_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_32_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_32_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_32_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_32_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_32_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_32_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_32_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_32_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_32_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_32_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_32_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_32_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_32_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_32_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_32_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_32_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_32_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_32_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_32_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_32_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_32_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[29] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_462 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[29] ) ,
+ .ccff_tail ( grid_clb_32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[60] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_463 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_464 ) ,
+ .SC_OUT_BOT ( scff_Wires[61] ) , .Test_en_E_in ( Test_enWires[203] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_465 ) ,
+ .Test_en_W_out ( Test_enWires[204] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_466 ) ,
+ .pReset_N_in ( pResetWires[464] ) , .Reset_E_in ( ResetWires[203] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_467 ) ,
+ .Reset_W_out ( ResetWires[204] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_468 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[74] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_469 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[125] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[126] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_470 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_471 ) ,
+ .clk_0_N_in ( clk_1_wires[74] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+grid_clb grid_clb_3__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_473 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[31] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_474 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[31] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_475 } ) ,
+ .ccff_head ( cby_1__1__21_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_33_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_33_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_33_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_33_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_33_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_33_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_33_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_33_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_33_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_33_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_33_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_33_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_33_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_33_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_33_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_33_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_33_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_33_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_33_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_33_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_33_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_33_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_33_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_33_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_33_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_33_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_33_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_33_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_33_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_33_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_33_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_33_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[30] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_476 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[30] ) ,
+ .ccff_tail ( grid_clb_33_ccff_tail ) , .SC_IN_TOP ( scff_Wires[58] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_477 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_478 ) ,
+ .SC_OUT_BOT ( scff_Wires[59] ) , .Test_en_E_in ( Test_enWires[225] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_479 ) ,
+ .Test_en_W_out ( Test_enWires[226] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_480 ) ,
+ .pReset_N_in ( pResetWires[513] ) , .Reset_E_in ( ResetWires[225] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_481 ) ,
+ .Reset_W_out ( ResetWires[226] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_482 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_483 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[73] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[128] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[129] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_484 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_485 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_486 ) ,
+ .clk_0_S_in ( clk_1_wires[73] ) ) ;
+grid_clb grid_clb_3__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_487 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[32] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_488 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[32] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_489 } ) ,
+ .ccff_head ( cby_1__1__22_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_34_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_34_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_34_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_34_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_34_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_34_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_34_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_34_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_34_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_34_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_34_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_34_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_34_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_34_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_34_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_34_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_34_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_34_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_34_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_34_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_34_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_34_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_34_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_34_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_34_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_34_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_34_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_34_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_34_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_34_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_34_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_34_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[31] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_490 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[31] ) ,
+ .ccff_tail ( grid_clb_34_ccff_tail ) , .SC_IN_TOP ( scff_Wires[56] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_491 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_492 ) ,
+ .SC_OUT_BOT ( scff_Wires[57] ) , .Test_en_E_in ( Test_enWires[247] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_493 ) ,
+ .Test_en_W_out ( Test_enWires[248] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_494 ) ,
+ .pReset_N_in ( pResetWires[562] ) , .Reset_E_in ( ResetWires[247] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_495 ) ,
+ .Reset_W_out ( ResetWires[248] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_496 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[81] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_497 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[131] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[132] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_498 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_499 ) ,
+ .clk_0_N_in ( clk_1_wires[81] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+grid_clb grid_clb_3__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_501 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_502 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_503 } ) ,
+ .ccff_head ( cby_1__1__23_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_35_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_35_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_35_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_35_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_35_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_35_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_35_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_35_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_35_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_35_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_35_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_35_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_35_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_35_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_35_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_35_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_35_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_35_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_35_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_35_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_35_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_35_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_35_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_35_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_35_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_35_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_35_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_35_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_35_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_35_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_35_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_35_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[32] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_504 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[32] ) ,
+ .ccff_tail ( grid_clb_35_ccff_tail ) , .SC_IN_TOP ( scff_Wires[54] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_505 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_506 ) ,
+ .SC_OUT_BOT ( scff_Wires[55] ) , .Test_en_E_in ( Test_enWires[269] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_507 ) ,
+ .Test_en_W_out ( Test_enWires[270] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_508 ) ,
+ .pReset_N_in ( pResetWires[609] ) , .Reset_E_in ( ResetWires[269] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_509 ) ,
+ .Reset_W_out ( ResetWires[270] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_510 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_511 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[80] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[134] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[135] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_512 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[137] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_513 ) ,
+ .clk_0_S_in ( clk_1_wires[80] ) ) ;
+grid_clb grid_clb_4__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_514 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[33] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_515 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[33] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_516 } ) ,
+ .ccff_head ( cby_1__1__24_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_36_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_36_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_36_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_36_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_36_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_36_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_36_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_36_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_36_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_36_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_36_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_36_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_36_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_36_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_36_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_36_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_36_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_36_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_36_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_36_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_36_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_36_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_36_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_36_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_36_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_36_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_36_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_36_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_36_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_36_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_36_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_36_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_517 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_36_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_518 ) , .SC_IN_BOT ( scff_Wires[81] ) ,
+ .SC_OUT_TOP ( scff_Wires[82] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_519 ) ,
+ .Test_en_E_in ( Test_enWires[29] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_520 ) ,
+ .Test_en_W_out ( Test_enWires[30] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_521 ) ,
+ .pReset_N_in ( pResetWires[76] ) , .Reset_E_in ( ResetWires[29] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_522 ) ,
+ .Reset_W_out ( ResetWires[30] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_523 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[48] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_524 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[139] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[140] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_525 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_526 ) ,
+ .clk_0_N_in ( clk_1_wires[48] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+grid_clb grid_clb_4__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_528 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[34] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_529 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[34] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_530 } ) ,
+ .ccff_head ( cby_1__1__25_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_37_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_37_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_37_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_37_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_37_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_37_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_37_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_37_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_37_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_37_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_37_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_37_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_37_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_37_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_37_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_37_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_37_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_37_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_37_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_37_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_37_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_37_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_37_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_37_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_37_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_37_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_37_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_37_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_37_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_37_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_37_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_37_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[33] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_531 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[33] ) ,
+ .ccff_tail ( grid_clb_37_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_532 ) , .SC_IN_BOT ( scff_Wires[83] ) ,
+ .SC_OUT_TOP ( scff_Wires[84] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_533 ) ,
+ .Test_en_E_in ( Test_enWires[51] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_534 ) ,
+ .Test_en_W_out ( Test_enWires[52] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_535 ) ,
+ .pReset_N_in ( pResetWires[125] ) , .Reset_E_in ( ResetWires[51] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_536 ) ,
+ .Reset_W_out ( ResetWires[52] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_537 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_538 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[47] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[142] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[143] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_539 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_540 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_541 ) ,
+ .clk_0_S_in ( clk_1_wires[47] ) ) ;
+grid_clb grid_clb_4__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_542 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[35] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_543 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[35] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_544 } ) ,
+ .ccff_head ( cby_1__1__26_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_38_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_38_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_38_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_38_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_38_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_38_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_38_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_38_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_38_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_38_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_38_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_38_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_38_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_38_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_38_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_38_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_38_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_38_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_38_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_38_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_38_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_38_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_38_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_38_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_38_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_38_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_38_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_38_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_38_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_38_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_38_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_38_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[34] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_545 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[34] ) ,
+ .ccff_tail ( grid_clb_38_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_546 ) , .SC_IN_BOT ( scff_Wires[85] ) ,
+ .SC_OUT_TOP ( scff_Wires[86] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_547 ) ,
+ .Test_en_E_in ( Test_enWires[73] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_548 ) ,
+ .Test_en_W_out ( Test_enWires[74] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_549 ) ,
+ .pReset_N_in ( pResetWires[174] ) , .Reset_E_in ( ResetWires[73] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_550 ) ,
+ .Reset_W_out ( ResetWires[74] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_551 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[55] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_552 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[145] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[146] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_553 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_554 ) ,
+ .clk_0_N_in ( clk_1_wires[55] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+grid_clb grid_clb_4__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_556 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[36] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_557 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[36] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_558 } ) ,
+ .ccff_head ( cby_1__1__27_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_39_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_39_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_39_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_39_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_39_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_39_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_39_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_39_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_39_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_39_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_39_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_39_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_39_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_39_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_39_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_39_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_39_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_39_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_39_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_39_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_39_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_39_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_39_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_39_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_39_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_39_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_39_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_39_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_39_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_39_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_39_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_39_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[35] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_559 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[35] ) ,
+ .ccff_tail ( grid_clb_39_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_560 ) , .SC_IN_BOT ( scff_Wires[87] ) ,
+ .SC_OUT_TOP ( scff_Wires[88] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_561 ) ,
+ .Test_en_E_in ( Test_enWires[95] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_562 ) ,
+ .Test_en_W_out ( Test_enWires[96] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_563 ) ,
+ .pReset_N_in ( pResetWires[223] ) , .Reset_E_in ( ResetWires[95] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_564 ) ,
+ .Reset_W_out ( ResetWires[96] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_565 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_566 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[54] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[148] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[149] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_567 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_568 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_569 ) ,
+ .clk_0_S_in ( clk_1_wires[54] ) ) ;
+grid_clb grid_clb_4__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_570 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[37] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_571 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[37] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_572 } ) ,
+ .ccff_head ( cby_1__1__28_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_40_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_40_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_40_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_40_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_40_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_40_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_40_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_40_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_40_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_40_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_40_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_40_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_40_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_40_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_40_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_40_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_40_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_40_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_40_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_40_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_40_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_40_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_40_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_40_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_40_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_40_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_40_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_40_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_40_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_40_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_40_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_40_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[36] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_573 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[36] ) ,
+ .ccff_tail ( grid_clb_40_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_574 ) , .SC_IN_BOT ( scff_Wires[89] ) ,
+ .SC_OUT_TOP ( scff_Wires[90] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_575 ) ,
+ .Test_en_E_in ( Test_enWires[117] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_576 ) ,
+ .Test_en_W_out ( Test_enWires[118] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_577 ) ,
+ .pReset_N_in ( pResetWires[272] ) , .Reset_E_in ( ResetWires[117] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_578 ) ,
+ .Reset_W_out ( ResetWires[118] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_579 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[62] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_580 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[151] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[152] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_581 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_582 ) ,
+ .clk_0_N_in ( clk_1_wires[62] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+grid_clb grid_clb_4__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_584 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[38] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_585 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[38] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_586 } ) ,
+ .ccff_head ( cby_1__1__29_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_41_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_41_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_41_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_41_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_41_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_41_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_41_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_41_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_41_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_41_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_41_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_41_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_41_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_41_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_41_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_41_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_41_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_41_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_41_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_41_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_41_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_41_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_41_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_41_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_41_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_41_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_41_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_41_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_41_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_41_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_41_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_41_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[37] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_587 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[37] ) ,
+ .ccff_tail ( grid_clb_41_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_588 ) , .SC_IN_BOT ( scff_Wires[91] ) ,
+ .SC_OUT_TOP ( scff_Wires[92] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_589 ) ,
+ .Test_en_E_in ( Test_enWires[139] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_590 ) ,
+ .Test_en_W_out ( Test_enWires[140] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_591 ) ,
+ .pReset_N_in ( pResetWires[321] ) , .Reset_E_in ( ResetWires[139] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_592 ) ,
+ .Reset_W_out ( ResetWires[140] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_593 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_594 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[61] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[154] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[155] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_595 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_596 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_597 ) ,
+ .clk_0_S_in ( clk_1_wires[61] ) ) ;
+grid_clb grid_clb_4__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_598 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[39] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_599 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[39] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_600 } ) ,
+ .ccff_head ( cby_1__1__30_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_42_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_42_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_42_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_42_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_42_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_42_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_42_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_42_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_42_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_42_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_42_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_42_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_42_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_42_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_42_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_42_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_42_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_42_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_42_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_42_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_42_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_42_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_42_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_42_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_42_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_42_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_42_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_42_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_42_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_42_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_42_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_42_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[38] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_601 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[38] ) ,
+ .ccff_tail ( grid_clb_42_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_602 ) , .SC_IN_BOT ( scff_Wires[93] ) ,
+ .SC_OUT_TOP ( scff_Wires[94] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_603 ) ,
+ .Test_en_E_in ( Test_enWires[161] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_604 ) ,
+ .Test_en_W_out ( Test_enWires[162] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_605 ) ,
+ .pReset_N_in ( pResetWires[370] ) , .Reset_E_in ( ResetWires[161] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_606 ) ,
+ .Reset_W_out ( ResetWires[162] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_607 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[69] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_608 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[157] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[158] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_609 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_610 ) ,
+ .clk_0_N_in ( clk_1_wires[69] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+grid_clb grid_clb_4__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_612 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[40] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_613 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[40] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_614 } ) ,
+ .ccff_head ( cby_1__1__31_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_43_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_43_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_43_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_43_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_43_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_43_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_43_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_43_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_43_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_43_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_43_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_43_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_43_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_43_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_43_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_43_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_43_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_43_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_43_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_43_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_43_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_43_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_43_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_43_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_43_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_43_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_43_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_43_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_43_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_43_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_43_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_43_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[39] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_615 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[39] ) ,
+ .ccff_tail ( grid_clb_43_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_616 ) , .SC_IN_BOT ( scff_Wires[95] ) ,
+ .SC_OUT_TOP ( scff_Wires[96] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_617 ) ,
+ .Test_en_E_in ( Test_enWires[183] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_618 ) ,
+ .Test_en_W_out ( Test_enWires[184] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_619 ) ,
+ .pReset_N_in ( pResetWires[419] ) , .Reset_E_in ( ResetWires[183] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_620 ) ,
+ .Reset_W_out ( ResetWires[184] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_621 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_622 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[68] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[160] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[161] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_623 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_624 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_625 ) ,
+ .clk_0_S_in ( clk_1_wires[68] ) ) ;
+grid_clb grid_clb_4__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_626 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[41] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_627 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[41] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_628 } ) ,
+ .ccff_head ( cby_1__1__32_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_44_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_44_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_44_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_44_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_44_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_44_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_44_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_44_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_44_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_44_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_44_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_44_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_44_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_44_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_44_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_44_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_44_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_44_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_44_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_44_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_44_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_44_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_44_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_44_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_44_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_44_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_44_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_44_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_44_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_44_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_44_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_44_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[40] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_629 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[40] ) ,
+ .ccff_tail ( grid_clb_44_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_630 ) , .SC_IN_BOT ( scff_Wires[97] ) ,
+ .SC_OUT_TOP ( scff_Wires[98] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_631 ) ,
+ .Test_en_E_in ( Test_enWires[205] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_632 ) ,
+ .Test_en_W_out ( Test_enWires[206] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_633 ) ,
+ .pReset_N_in ( pResetWires[468] ) , .Reset_E_in ( ResetWires[205] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_634 ) ,
+ .Reset_W_out ( ResetWires[206] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_635 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[76] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_636 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[163] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[164] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_637 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_638 ) ,
+ .clk_0_N_in ( clk_1_wires[76] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+grid_clb grid_clb_4__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_640 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[42] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_641 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[42] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_642 } ) ,
+ .ccff_head ( cby_1__1__33_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_45_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_45_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_45_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_45_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_45_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_45_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_45_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_45_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_45_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_45_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_45_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_45_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_45_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_45_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_45_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_45_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_45_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_45_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_45_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_45_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_45_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_45_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_45_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_45_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_45_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_45_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_45_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_45_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_45_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_45_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_45_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_45_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[41] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_643 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[41] ) ,
+ .ccff_tail ( grid_clb_45_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_644 ) , .SC_IN_BOT ( scff_Wires[99] ) ,
+ .SC_OUT_TOP ( scff_Wires[100] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_645 ) ,
+ .Test_en_E_in ( Test_enWires[227] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_646 ) ,
+ .Test_en_W_out ( Test_enWires[228] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_647 ) ,
+ .pReset_N_in ( pResetWires[517] ) , .Reset_E_in ( ResetWires[227] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_648 ) ,
+ .Reset_W_out ( ResetWires[228] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_649 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_650 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[75] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[166] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[167] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_651 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_652 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_653 ) ,
+ .clk_0_S_in ( clk_1_wires[75] ) ) ;
+grid_clb grid_clb_4__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_654 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[43] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_655 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[43] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_656 } ) ,
+ .ccff_head ( cby_1__1__34_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_46_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_46_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_46_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_46_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_46_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_46_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_46_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_46_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_46_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_46_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_46_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_46_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_46_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_46_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_46_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_46_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_46_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_46_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_46_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_46_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_46_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_46_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_46_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_46_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_46_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_46_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_46_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_46_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_46_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_46_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_46_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_46_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[42] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_657 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[42] ) ,
+ .ccff_tail ( grid_clb_46_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_658 ) , .SC_IN_BOT ( scff_Wires[101] ) ,
+ .SC_OUT_TOP ( scff_Wires[102] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_659 ) ,
+ .Test_en_E_in ( Test_enWires[249] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_660 ) ,
+ .Test_en_W_out ( Test_enWires[250] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_661 ) ,
+ .pReset_N_in ( pResetWires[566] ) , .Reset_E_in ( ResetWires[249] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_662 ) ,
+ .Reset_W_out ( ResetWires[250] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_663 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[83] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_664 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[169] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[170] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_665 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_666 ) ,
+ .clk_0_N_in ( clk_1_wires[83] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+grid_clb grid_clb_4__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_668 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_669 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_670 } ) ,
+ .ccff_head ( cby_1__1__35_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_47_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_47_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_47_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_47_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_47_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_47_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_47_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_47_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_47_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_47_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_47_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_47_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_47_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_47_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_47_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_47_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_47_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_47_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_47_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_47_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_47_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_47_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_47_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_47_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_47_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_47_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_47_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_47_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_47_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_47_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_47_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_47_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[43] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_671 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[43] ) ,
+ .ccff_tail ( grid_clb_47_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_672 ) , .SC_IN_BOT ( scff_Wires[103] ) ,
+ .SC_OUT_TOP ( scff_Wires[104] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_673 ) ,
+ .Test_en_E_in ( Test_enWires[271] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_674 ) ,
+ .Test_en_W_out ( Test_enWires[272] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_675 ) ,
+ .pReset_N_in ( pResetWires[612] ) , .Reset_E_in ( ResetWires[271] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_676 ) ,
+ .Reset_W_out ( ResetWires[272] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_677 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_678 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[82] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[172] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[173] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_679 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[175] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_680 ) ,
+ .clk_0_S_in ( clk_1_wires[82] ) ) ;
+grid_clb grid_clb_5__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_681 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[44] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_682 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[44] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_683 } ) ,
+ .ccff_head ( cby_1__1__36_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_48_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_48_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_48_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_48_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_48_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_48_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_48_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_48_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_48_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_48_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_48_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_48_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_48_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_48_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_48_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_48_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_48_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_48_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_48_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_48_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_48_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_48_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_48_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_48_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_48_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_48_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_48_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_48_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_48_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_48_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_48_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_48_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_684 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[129] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_685 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_686 ) ,
+ .SC_OUT_BOT ( scff_Wires[131] ) , .Test_en_E_in ( Test_enWires[31] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_687 ) ,
+ .Test_en_W_out ( Test_enWires[32] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_688 ) ,
+ .pReset_N_in ( pResetWires[80] ) , .Reset_E_in ( ResetWires[31] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_689 ) ,
+ .Reset_W_out ( ResetWires[32] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_690 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[88] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_691 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[177] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[178] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_692 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_693 ) ,
+ .clk_0_N_in ( clk_1_wires[88] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+grid_clb grid_clb_5__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_695 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[45] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_696 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[45] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_697 } ) ,
+ .ccff_head ( cby_1__1__37_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_49_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_49_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_49_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_49_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_49_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_49_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_49_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_49_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_49_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_49_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_49_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_49_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_49_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_49_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_49_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_49_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_49_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_49_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_49_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_49_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_49_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_49_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_49_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_49_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_49_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_49_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_49_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_49_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_49_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_49_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_49_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_49_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[44] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_698 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[44] ) ,
+ .ccff_tail ( grid_clb_49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[127] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_699 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_700 ) ,
+ .SC_OUT_BOT ( scff_Wires[128] ) , .Test_en_E_in ( Test_enWires[53] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_701 ) ,
+ .Test_en_W_out ( Test_enWires[54] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_702 ) ,
+ .pReset_N_in ( pResetWires[129] ) , .Reset_E_in ( ResetWires[53] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_703 ) ,
+ .Reset_W_out ( ResetWires[54] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_704 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_705 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[87] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[180] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[181] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_706 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_707 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_708 ) ,
+ .clk_0_S_in ( clk_1_wires[87] ) ) ;
+grid_clb grid_clb_5__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_709 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[46] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_710 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[46] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_711 } ) ,
+ .ccff_head ( cby_1__1__38_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_50_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_50_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_50_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_50_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_50_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_50_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_50_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_50_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_50_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_50_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_50_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_50_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_50_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_50_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_50_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_50_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_50_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_50_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_50_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_50_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_50_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_50_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_50_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_50_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_50_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_50_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_50_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_50_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_50_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_50_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_50_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_50_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[45] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_712 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[45] ) ,
+ .ccff_tail ( grid_clb_50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[125] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_713 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_714 ) ,
+ .SC_OUT_BOT ( scff_Wires[126] ) , .Test_en_E_in ( Test_enWires[75] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_715 ) ,
+ .Test_en_W_out ( Test_enWires[76] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_716 ) ,
+ .pReset_N_in ( pResetWires[178] ) , .Reset_E_in ( ResetWires[75] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_717 ) ,
+ .Reset_W_out ( ResetWires[76] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_718 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[95] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_719 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[183] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[184] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_720 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_721 ) ,
+ .clk_0_N_in ( clk_1_wires[95] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+grid_clb grid_clb_5__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_723 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[47] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_724 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[47] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_725 } ) ,
+ .ccff_head ( cby_1__1__39_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_51_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_51_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_51_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_51_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_51_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_51_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_51_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_51_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_51_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_51_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_51_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_51_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_51_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_51_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_51_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_51_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_51_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_51_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_51_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_51_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_51_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_51_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_51_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_51_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_51_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_51_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_51_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_51_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_51_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_51_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_51_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_51_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[46] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_726 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[46] ) ,
+ .ccff_tail ( grid_clb_51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[123] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_727 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_728 ) ,
+ .SC_OUT_BOT ( scff_Wires[124] ) , .Test_en_E_in ( Test_enWires[97] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_729 ) ,
+ .Test_en_W_out ( Test_enWires[98] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_730 ) ,
+ .pReset_N_in ( pResetWires[227] ) , .Reset_E_in ( ResetWires[97] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_731 ) ,
+ .Reset_W_out ( ResetWires[98] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_732 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_733 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[94] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[186] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[187] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_734 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_735 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_736 ) ,
+ .clk_0_S_in ( clk_1_wires[94] ) ) ;
+grid_clb grid_clb_5__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_737 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[48] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_738 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[48] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_739 } ) ,
+ .ccff_head ( cby_1__1__40_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_52_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_52_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_52_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_52_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_52_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_52_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_52_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_52_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_52_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_52_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_52_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_52_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_52_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_52_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_52_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_52_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_52_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_52_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_52_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_52_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_52_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_52_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_52_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_52_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_52_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_52_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_52_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_52_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_52_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_52_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_52_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_52_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[47] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_740 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[47] ) ,
+ .ccff_tail ( grid_clb_52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[121] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_741 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_742 ) ,
+ .SC_OUT_BOT ( scff_Wires[122] ) , .Test_en_E_in ( Test_enWires[119] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_743 ) ,
+ .Test_en_W_out ( Test_enWires[120] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_744 ) ,
+ .pReset_N_in ( pResetWires[276] ) , .Reset_E_in ( ResetWires[119] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_745 ) ,
+ .Reset_W_out ( ResetWires[120] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_746 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[102] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_747 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[189] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[190] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_748 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_749 ) ,
+ .clk_0_N_in ( clk_1_wires[102] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+grid_clb grid_clb_5__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_751 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[49] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_752 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[49] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_753 } ) ,
+ .ccff_head ( cby_1__1__41_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_53_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_53_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_53_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_53_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_53_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_53_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_53_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_53_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_53_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_53_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_53_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_53_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_53_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_53_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_53_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_53_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_53_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_53_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_53_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_53_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_53_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_53_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_53_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_53_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_53_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_53_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_53_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_53_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_53_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_53_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_53_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_53_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[48] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_754 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[48] ) ,
+ .ccff_tail ( grid_clb_53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[119] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_755 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_756 ) ,
+ .SC_OUT_BOT ( scff_Wires[120] ) , .Test_en_E_in ( Test_enWires[141] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_757 ) ,
+ .Test_en_W_out ( Test_enWires[142] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_758 ) ,
+ .pReset_N_in ( pResetWires[325] ) , .Reset_E_in ( ResetWires[141] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_759 ) ,
+ .Reset_W_out ( ResetWires[142] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_760 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_761 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[101] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[192] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[193] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_762 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_763 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_764 ) ,
+ .clk_0_S_in ( clk_1_wires[101] ) ) ;
+grid_clb grid_clb_5__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_765 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[50] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_766 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[50] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_767 } ) ,
+ .ccff_head ( cby_1__1__42_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_54_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_54_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_54_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_54_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_54_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_54_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_54_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_54_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_54_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_54_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_54_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_54_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_54_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_54_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_54_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_54_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_54_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_54_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_54_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_54_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_54_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_54_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_54_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_54_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_54_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_54_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_54_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_54_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_54_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_54_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_54_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_54_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[49] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_768 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[49] ) ,
+ .ccff_tail ( grid_clb_54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[117] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_769 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_770 ) ,
+ .SC_OUT_BOT ( scff_Wires[118] ) , .Test_en_E_in ( Test_enWires[163] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_771 ) ,
+ .Test_en_W_out ( Test_enWires[164] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_772 ) ,
+ .pReset_N_in ( pResetWires[374] ) , .Reset_E_in ( ResetWires[163] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_773 ) ,
+ .Reset_W_out ( ResetWires[164] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_774 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[109] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_775 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[195] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[196] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_776 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_777 ) ,
+ .clk_0_N_in ( clk_1_wires[109] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+grid_clb grid_clb_5__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_779 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[51] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_780 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[51] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_781 } ) ,
+ .ccff_head ( cby_1__1__43_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_55_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_55_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_55_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_55_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_55_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_55_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_55_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_55_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_55_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_55_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_55_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_55_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_55_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_55_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_55_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_55_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_55_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_55_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_55_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_55_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_55_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_55_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_55_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_55_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_55_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_55_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_55_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_55_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_55_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_55_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_55_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_55_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[50] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_782 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[50] ) ,
+ .ccff_tail ( grid_clb_55_ccff_tail ) , .SC_IN_TOP ( scff_Wires[115] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_783 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_784 ) ,
+ .SC_OUT_BOT ( scff_Wires[116] ) , .Test_en_E_in ( Test_enWires[185] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_785 ) ,
+ .Test_en_W_out ( Test_enWires[186] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_786 ) ,
+ .pReset_N_in ( pResetWires[423] ) , .Reset_E_in ( ResetWires[185] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_787 ) ,
+ .Reset_W_out ( ResetWires[186] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_788 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_789 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[108] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[198] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[199] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_790 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_791 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_792 ) ,
+ .clk_0_S_in ( clk_1_wires[108] ) ) ;
+grid_clb grid_clb_5__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_793 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[52] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_794 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[52] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_795 } ) ,
+ .ccff_head ( cby_1__1__44_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_56_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_56_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_56_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_56_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_56_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_56_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_56_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_56_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_56_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_56_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_56_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_56_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_56_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_56_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_56_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_56_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_56_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_56_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_56_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_56_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_56_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_56_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_56_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_56_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_56_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_56_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_56_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_56_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_56_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_56_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_56_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_56_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[51] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_796 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[51] ) ,
+ .ccff_tail ( grid_clb_56_ccff_tail ) , .SC_IN_TOP ( scff_Wires[113] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_797 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_798 ) ,
+ .SC_OUT_BOT ( scff_Wires[114] ) , .Test_en_E_in ( Test_enWires[207] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_799 ) ,
+ .Test_en_W_out ( Test_enWires[208] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_800 ) ,
+ .pReset_N_in ( pResetWires[472] ) , .Reset_E_in ( ResetWires[207] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_801 ) ,
+ .Reset_W_out ( ResetWires[208] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_802 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[116] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_803 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[201] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[202] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_804 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_805 ) ,
+ .clk_0_N_in ( clk_1_wires[116] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+grid_clb grid_clb_5__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_807 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[53] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_808 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[53] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_809 } ) ,
+ .ccff_head ( cby_1__1__45_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_57_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_57_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_57_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_57_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_57_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_57_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_57_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_57_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_57_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_57_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_57_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_57_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_57_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_57_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_57_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_57_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_57_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_57_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_57_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_57_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_57_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_57_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_57_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_57_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_57_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_57_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_57_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_57_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_57_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_57_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_57_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_57_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[52] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_810 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[52] ) ,
+ .ccff_tail ( grid_clb_57_ccff_tail ) , .SC_IN_TOP ( scff_Wires[111] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_811 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_812 ) ,
+ .SC_OUT_BOT ( scff_Wires[112] ) , .Test_en_E_in ( Test_enWires[229] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_813 ) ,
+ .Test_en_W_out ( Test_enWires[230] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_814 ) ,
+ .pReset_N_in ( pResetWires[521] ) , .Reset_E_in ( ResetWires[229] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_815 ) ,
+ .Reset_W_out ( ResetWires[230] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_816 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_817 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[115] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[204] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[205] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_818 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_819 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_820 ) ,
+ .clk_0_S_in ( clk_1_wires[115] ) ) ;
+grid_clb grid_clb_5__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_821 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[54] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_822 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[54] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_823 } ) ,
+ .ccff_head ( cby_1__1__46_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_58_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_58_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_58_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_58_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_58_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_58_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_58_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_58_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_58_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_58_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_58_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_58_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_58_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_58_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_58_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_58_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_58_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_58_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_58_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_58_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_58_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_58_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_58_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_58_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_58_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_58_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_58_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_58_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_58_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_58_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_58_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_58_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[53] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_824 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[53] ) ,
+ .ccff_tail ( grid_clb_58_ccff_tail ) , .SC_IN_TOP ( scff_Wires[109] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_825 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_826 ) ,
+ .SC_OUT_BOT ( scff_Wires[110] ) , .Test_en_E_in ( Test_enWires[251] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_827 ) ,
+ .Test_en_W_out ( Test_enWires[252] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_828 ) ,
+ .pReset_N_in ( pResetWires[570] ) , .Reset_E_in ( ResetWires[251] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_829 ) ,
+ .Reset_W_out ( ResetWires[252] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_830 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[123] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_831 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[207] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[208] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_832 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_833 ) ,
+ .clk_0_N_in ( clk_1_wires[123] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+grid_clb grid_clb_5__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_835 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_836 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_837 } ) ,
+ .ccff_head ( cby_1__1__47_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_59_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_59_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_59_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_59_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_59_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_59_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_59_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_59_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_59_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_59_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_59_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_59_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_59_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_59_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_59_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_59_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_59_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_59_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_59_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_59_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_59_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_59_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_59_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_59_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_59_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_59_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_59_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_59_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_59_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_59_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_59_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_59_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[54] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_838 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[54] ) ,
+ .ccff_tail ( grid_clb_59_ccff_tail ) , .SC_IN_TOP ( scff_Wires[107] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_839 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_840 ) ,
+ .SC_OUT_BOT ( scff_Wires[108] ) , .Test_en_E_in ( Test_enWires[273] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_841 ) ,
+ .Test_en_W_out ( Test_enWires[274] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_842 ) ,
+ .pReset_N_in ( pResetWires[615] ) , .Reset_E_in ( ResetWires[273] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_843 ) ,
+ .Reset_W_out ( ResetWires[274] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_844 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_845 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[122] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[210] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[211] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_846 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[213] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_847 ) ,
+ .clk_0_S_in ( clk_1_wires[122] ) ) ;
+grid_clb grid_clb_6__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_848 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[55] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_849 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[55] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_850 } ) ,
+ .ccff_head ( cby_1__1__48_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_60_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_60_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_60_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_60_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_60_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_60_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_60_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_60_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_60_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_60_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_60_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_60_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_60_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_60_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_60_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_60_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_60_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_60_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_60_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_60_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_60_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_60_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_60_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_60_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_60_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_60_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_60_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_60_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_60_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_60_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_60_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_60_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_851 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_60_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_852 ) , .SC_IN_BOT ( scff_Wires[134] ) ,
+ .SC_OUT_TOP ( scff_Wires[135] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_853 ) ,
+ .Test_en_E_in ( Test_enWires[33] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_854 ) ,
+ .Test_en_W_out ( Test_enWires[34] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_855 ) ,
+ .pReset_N_in ( pResetWires[84] ) , .Reset_E_in ( ResetWires[33] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_856 ) ,
+ .Reset_W_out ( ResetWires[34] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_857 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[90] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_858 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[215] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[216] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_859 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_860 ) ,
+ .clk_0_N_in ( clk_1_wires[90] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+grid_clb grid_clb_6__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_862 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[56] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_863 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[56] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_864 } ) ,
+ .ccff_head ( cby_1__1__49_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_61_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_61_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_61_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_61_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_61_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_61_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_61_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_61_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_61_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_61_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_61_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_61_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_61_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_61_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_61_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_61_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_61_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_61_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_61_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_61_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_61_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_61_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_61_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_61_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_61_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_61_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_61_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_61_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_61_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_61_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_61_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_61_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[55] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_865 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[55] ) ,
+ .ccff_tail ( grid_clb_61_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_866 ) , .SC_IN_BOT ( scff_Wires[136] ) ,
+ .SC_OUT_TOP ( scff_Wires[137] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_867 ) ,
+ .Test_en_E_in ( Test_enWires[55] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_868 ) ,
+ .Test_en_W_out ( Test_enWires[56] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_869 ) ,
+ .pReset_N_in ( pResetWires[133] ) , .Reset_E_in ( ResetWires[55] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_870 ) ,
+ .Reset_W_out ( ResetWires[56] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_871 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_872 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[89] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[218] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[219] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_873 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_874 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_875 ) ,
+ .clk_0_S_in ( clk_1_wires[89] ) ) ;
+grid_clb grid_clb_6__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_876 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[57] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_877 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[57] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_878 } ) ,
+ .ccff_head ( cby_1__1__50_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_62_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_62_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_62_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_62_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_62_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_62_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_62_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_62_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_62_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_62_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_62_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_62_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_62_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_62_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_62_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_62_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_62_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_62_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_62_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_62_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_62_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_62_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_62_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_62_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_62_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_62_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_62_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_62_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_62_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_62_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_62_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_62_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[56] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_879 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[56] ) ,
+ .ccff_tail ( grid_clb_62_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_880 ) , .SC_IN_BOT ( scff_Wires[138] ) ,
+ .SC_OUT_TOP ( scff_Wires[139] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_881 ) ,
+ .Test_en_E_in ( Test_enWires[77] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_882 ) ,
+ .Test_en_W_out ( Test_enWires[78] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_883 ) ,
+ .pReset_N_in ( pResetWires[182] ) , .Reset_E_in ( ResetWires[77] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_884 ) ,
+ .Reset_W_out ( ResetWires[78] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_885 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[97] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_886 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[221] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[222] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_887 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_888 ) ,
+ .clk_0_N_in ( clk_1_wires[97] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+grid_clb grid_clb_6__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_890 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[58] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_891 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[58] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_892 } ) ,
+ .ccff_head ( cby_1__1__51_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_63_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_63_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_63_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_63_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_63_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_63_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_63_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_63_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_63_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_63_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_63_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_63_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_63_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_63_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_63_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_63_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_63_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_63_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_63_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_63_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_63_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_63_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_63_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_63_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_63_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_63_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_63_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_63_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_63_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_63_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_63_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_63_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[57] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_893 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[57] ) ,
+ .ccff_tail ( grid_clb_63_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_894 ) , .SC_IN_BOT ( scff_Wires[140] ) ,
+ .SC_OUT_TOP ( scff_Wires[141] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_895 ) ,
+ .Test_en_E_in ( Test_enWires[99] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_896 ) ,
+ .Test_en_W_out ( Test_enWires[100] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_897 ) ,
+ .pReset_N_in ( pResetWires[231] ) , .Reset_E_in ( ResetWires[99] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_898 ) ,
+ .Reset_W_out ( ResetWires[100] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_899 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_900 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[96] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[224] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[225] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_901 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_902 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_903 ) ,
+ .clk_0_S_in ( clk_1_wires[96] ) ) ;
+grid_clb grid_clb_6__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_904 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[59] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_905 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[59] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_906 } ) ,
+ .ccff_head ( cby_1__1__52_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_64_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_64_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_64_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_64_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_64_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_64_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_64_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_64_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_64_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_64_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_64_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_64_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_64_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_64_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_64_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_64_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_64_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_64_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_64_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_64_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_64_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_64_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_64_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_64_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_64_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_64_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_64_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_64_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_64_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_64_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_64_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_64_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[58] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_907 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[58] ) ,
+ .ccff_tail ( grid_clb_64_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_908 ) , .SC_IN_BOT ( scff_Wires[142] ) ,
+ .SC_OUT_TOP ( scff_Wires[143] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_909 ) ,
+ .Test_en_E_in ( Test_enWires[121] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_910 ) ,
+ .Test_en_W_out ( Test_enWires[122] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_911 ) ,
+ .pReset_N_in ( pResetWires[280] ) , .Reset_E_in ( ResetWires[121] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_912 ) ,
+ .Reset_W_out ( ResetWires[122] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_913 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[104] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_914 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[227] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[228] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_915 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_916 ) ,
+ .clk_0_N_in ( clk_1_wires[104] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+grid_clb grid_clb_6__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_918 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[60] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_919 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[60] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_920 } ) ,
+ .ccff_head ( cby_1__1__53_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_65_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_65_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_65_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_65_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_65_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_65_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_65_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_65_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_65_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_65_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_65_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_65_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_65_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_65_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_65_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_65_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_65_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_65_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_65_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_65_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_65_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_65_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_65_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_65_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_65_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_65_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_65_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_65_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_65_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_65_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_65_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_65_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[59] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_921 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[59] ) ,
+ .ccff_tail ( grid_clb_65_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_922 ) , .SC_IN_BOT ( scff_Wires[144] ) ,
+ .SC_OUT_TOP ( scff_Wires[145] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_923 ) ,
+ .Test_en_E_in ( Test_enWires[143] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_924 ) ,
+ .Test_en_W_out ( Test_enWires[144] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_925 ) ,
+ .pReset_N_in ( pResetWires[329] ) , .Reset_E_in ( ResetWires[143] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_926 ) ,
+ .Reset_W_out ( ResetWires[144] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_927 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_928 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[103] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[230] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[231] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_929 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_930 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_931 ) ,
+ .clk_0_S_in ( clk_1_wires[103] ) ) ;
+grid_clb grid_clb_6__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_932 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[61] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_933 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[61] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_934 } ) ,
+ .ccff_head ( cby_1__1__54_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_66_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_66_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_66_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_66_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_66_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_66_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_66_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_66_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_66_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_66_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_66_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_66_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_66_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_66_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_66_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_66_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_66_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_66_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_66_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_66_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_66_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_66_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_66_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_66_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_66_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_66_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_66_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_66_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_66_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_66_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_66_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_66_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[60] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_935 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[60] ) ,
+ .ccff_tail ( grid_clb_66_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_936 ) , .SC_IN_BOT ( scff_Wires[146] ) ,
+ .SC_OUT_TOP ( scff_Wires[147] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_937 ) ,
+ .Test_en_E_in ( Test_enWires[165] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_938 ) ,
+ .Test_en_W_out ( Test_enWires[166] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_939 ) ,
+ .pReset_N_in ( pResetWires[378] ) , .Reset_E_in ( ResetWires[165] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_940 ) ,
+ .Reset_W_out ( ResetWires[166] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_941 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[111] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_942 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[233] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[234] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_943 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_944 ) ,
+ .clk_0_N_in ( clk_1_wires[111] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+grid_clb grid_clb_6__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_946 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[62] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_947 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[62] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_948 } ) ,
+ .ccff_head ( cby_1__1__55_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_67_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_67_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_67_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_67_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_67_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_67_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_67_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_67_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_67_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_67_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_67_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_67_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_67_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_67_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_67_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_67_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_67_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_67_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_67_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_67_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_67_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_67_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_67_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_67_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_67_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_67_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_67_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_67_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_67_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_67_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_67_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_67_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[61] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_949 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[61] ) ,
+ .ccff_tail ( grid_clb_67_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_950 ) , .SC_IN_BOT ( scff_Wires[148] ) ,
+ .SC_OUT_TOP ( scff_Wires[149] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_951 ) ,
+ .Test_en_E_in ( Test_enWires[187] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_952 ) ,
+ .Test_en_W_out ( Test_enWires[188] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_953 ) ,
+ .pReset_N_in ( pResetWires[427] ) , .Reset_E_in ( ResetWires[187] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_954 ) ,
+ .Reset_W_out ( ResetWires[188] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_955 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_956 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[110] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[236] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[237] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_957 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_958 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_959 ) ,
+ .clk_0_S_in ( clk_1_wires[110] ) ) ;
+grid_clb grid_clb_6__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_960 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[63] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_961 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[63] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_962 } ) ,
+ .ccff_head ( cby_1__1__56_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_68_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_68_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_68_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_68_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_68_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_68_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_68_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_68_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_68_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_68_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_68_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_68_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_68_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_68_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_68_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_68_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_68_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_68_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_68_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_68_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_68_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_68_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_68_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_68_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_68_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_68_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_68_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_68_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_68_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_68_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_68_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_68_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[62] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_963 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[62] ) ,
+ .ccff_tail ( grid_clb_68_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_964 ) , .SC_IN_BOT ( scff_Wires[150] ) ,
+ .SC_OUT_TOP ( scff_Wires[151] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_965 ) ,
+ .Test_en_E_in ( Test_enWires[209] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_966 ) ,
+ .Test_en_W_out ( Test_enWires[210] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_967 ) ,
+ .pReset_N_in ( pResetWires[476] ) , .Reset_E_in ( ResetWires[209] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_968 ) ,
+ .Reset_W_out ( ResetWires[210] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_969 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[118] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_970 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[239] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[240] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_971 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_972 ) ,
+ .clk_0_N_in ( clk_1_wires[118] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+grid_clb grid_clb_6__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_974 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[64] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_975 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[64] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_976 } ) ,
+ .ccff_head ( cby_1__1__57_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_69_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_69_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_69_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_69_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_69_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_69_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_69_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_69_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_69_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_69_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_69_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_69_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_69_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_69_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_69_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_69_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_69_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_69_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_69_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_69_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_69_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_69_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_69_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_69_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_69_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_69_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_69_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_69_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_69_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_69_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_69_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_69_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[63] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_977 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[63] ) ,
+ .ccff_tail ( grid_clb_69_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_978 ) , .SC_IN_BOT ( scff_Wires[152] ) ,
+ .SC_OUT_TOP ( scff_Wires[153] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_979 ) ,
+ .Test_en_E_in ( Test_enWires[231] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_980 ) ,
+ .Test_en_W_out ( Test_enWires[232] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_981 ) ,
+ .pReset_N_in ( pResetWires[525] ) , .Reset_E_in ( ResetWires[231] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_982 ) ,
+ .Reset_W_out ( ResetWires[232] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_983 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_984 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[117] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[242] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[243] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_985 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_986 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_987 ) ,
+ .clk_0_S_in ( clk_1_wires[117] ) ) ;
+grid_clb grid_clb_6__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_988 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[65] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_989 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[65] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_990 } ) ,
+ .ccff_head ( cby_1__1__58_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_70_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_70_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_70_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_70_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_70_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_70_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_70_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_70_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_70_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_70_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_70_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_70_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_70_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_70_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_70_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_70_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_70_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_70_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_70_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_70_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_70_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_70_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_70_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_70_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_70_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_70_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_70_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_70_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_70_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_70_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_70_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_70_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[64] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_991 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[64] ) ,
+ .ccff_tail ( grid_clb_70_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_992 ) , .SC_IN_BOT ( scff_Wires[154] ) ,
+ .SC_OUT_TOP ( scff_Wires[155] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_993 ) ,
+ .Test_en_E_in ( Test_enWires[253] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_994 ) ,
+ .Test_en_W_out ( Test_enWires[254] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_995 ) ,
+ .pReset_N_in ( pResetWires[574] ) , .Reset_E_in ( ResetWires[253] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_996 ) ,
+ .Reset_W_out ( ResetWires[254] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_997 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[125] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_998 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[245] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[246] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_999 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1000 ) ,
+ .clk_0_N_in ( clk_1_wires[125] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+grid_clb grid_clb_6__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1002 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1003 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1004 } ) ,
+ .ccff_head ( cby_1__1__59_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_71_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_71_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_71_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_71_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_71_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_71_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_71_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_71_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_71_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_71_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_71_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_71_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_71_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_71_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_71_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_71_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_71_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_71_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_71_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_71_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_71_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_71_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_71_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_71_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_71_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_71_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_71_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_71_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_71_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_71_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_71_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_71_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[65] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1005 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[65] ) ,
+ .ccff_tail ( grid_clb_71_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1006 ) ,
+ .SC_IN_BOT ( scff_Wires[156] ) , .SC_OUT_TOP ( scff_Wires[157] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1007 ) ,
+ .Test_en_E_in ( Test_enWires[275] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_1008 ) ,
+ .Test_en_W_out ( Test_enWires[276] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1009 ) ,
+ .pReset_N_in ( pResetWires[618] ) , .Reset_E_in ( ResetWires[275] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_1010 ) ,
+ .Reset_W_out ( ResetWires[276] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1011 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1012 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[124] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[248] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[249] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1013 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[251] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1014 ) ,
+ .clk_0_S_in ( clk_1_wires[124] ) ) ;
+grid_clb grid_clb_7__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1015 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[66] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1016 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[66] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1017 } ) ,
+ .ccff_head ( cby_1__1__60_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_72_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_72_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_72_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_72_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_72_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_72_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_72_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_72_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_72_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_72_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_72_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_72_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_72_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_72_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_72_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_72_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_72_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_72_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_72_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_72_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_72_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_72_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_72_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_72_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_72_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_72_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_72_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_72_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_72_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_72_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_72_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_72_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1018 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[182] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1019 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1020 ) ,
+ .SC_OUT_BOT ( scff_Wires[184] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1021 ) ,
+ .Test_en_W_in ( Test_enWires[35] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1022 ) ,
+ .Test_en_E_out ( Test_enWires[36] ) , .pReset_N_in ( pResetWires[88] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1023 ) ,
+ .Reset_W_in ( ResetWires[35] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1024 ) ,
+ .Reset_E_out ( ResetWires[36] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[130] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1025 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[253] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[254] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1026 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1027 ) ,
+ .clk_0_N_in ( clk_1_wires[130] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+grid_clb grid_clb_7__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1029 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[67] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1030 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[67] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1031 } ) ,
+ .ccff_head ( cby_1__1__61_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_73_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_73_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_73_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_73_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_73_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_73_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_73_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_73_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_73_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_73_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_73_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_73_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_73_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_73_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_73_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_73_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_73_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_73_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_73_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_73_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_73_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_73_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_73_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_73_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_73_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_73_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_73_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_73_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_73_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_73_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_73_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_73_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[66] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1032 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[66] ) ,
+ .ccff_tail ( grid_clb_73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[180] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1033 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1034 ) ,
+ .SC_OUT_BOT ( scff_Wires[181] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1035 ) ,
+ .Test_en_W_in ( Test_enWires[57] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1036 ) ,
+ .Test_en_E_out ( Test_enWires[58] ) , .pReset_N_in ( pResetWires[137] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1037 ) ,
+ .Reset_W_in ( ResetWires[57] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1038 ) ,
+ .Reset_E_out ( ResetWires[58] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1039 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[129] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[256] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[257] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1040 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1041 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1042 ) ,
+ .clk_0_S_in ( clk_1_wires[129] ) ) ;
+grid_clb grid_clb_7__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1043 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[68] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1044 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[68] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1045 } ) ,
+ .ccff_head ( cby_1__1__62_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_74_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_74_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_74_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_74_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_74_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_74_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_74_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_74_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_74_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_74_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_74_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_74_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_74_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_74_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_74_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_74_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_74_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_74_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_74_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_74_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_74_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_74_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_74_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_74_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_74_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_74_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_74_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_74_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_74_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_74_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_74_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_74_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[67] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1046 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[67] ) ,
+ .ccff_tail ( grid_clb_74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[178] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1047 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1048 ) ,
+ .SC_OUT_BOT ( scff_Wires[179] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1049 ) ,
+ .Test_en_W_in ( Test_enWires[79] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1050 ) ,
+ .Test_en_E_out ( Test_enWires[80] ) , .pReset_N_in ( pResetWires[186] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1051 ) ,
+ .Reset_W_in ( ResetWires[79] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1052 ) ,
+ .Reset_E_out ( ResetWires[80] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[137] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1053 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[259] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[260] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1054 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1055 ) ,
+ .clk_0_N_in ( clk_1_wires[137] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+grid_clb grid_clb_7__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1057 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[69] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1058 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[69] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1059 } ) ,
+ .ccff_head ( cby_1__1__63_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_75_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_75_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_75_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_75_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_75_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_75_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_75_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_75_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_75_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_75_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_75_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_75_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_75_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_75_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_75_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_75_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_75_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_75_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_75_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_75_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_75_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_75_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_75_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_75_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_75_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_75_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_75_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_75_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_75_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_75_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_75_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_75_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[68] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1060 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[68] ) ,
+ .ccff_tail ( grid_clb_75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[176] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1061 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1062 ) ,
+ .SC_OUT_BOT ( scff_Wires[177] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1063 ) ,
+ .Test_en_W_in ( Test_enWires[101] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1064 ) ,
+ .Test_en_E_out ( Test_enWires[102] ) , .pReset_N_in ( pResetWires[235] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1065 ) ,
+ .Reset_W_in ( ResetWires[101] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1066 ) ,
+ .Reset_E_out ( ResetWires[102] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1067 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[136] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[262] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[263] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1068 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1069 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1070 ) ,
+ .clk_0_S_in ( clk_1_wires[136] ) ) ;
+grid_clb grid_clb_7__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1071 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[70] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1072 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[70] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1073 } ) ,
+ .ccff_head ( cby_1__1__64_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_76_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_76_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_76_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_76_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_76_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_76_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_76_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_76_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_76_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_76_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_76_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_76_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_76_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_76_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_76_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_76_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_76_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_76_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_76_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_76_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_76_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_76_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_76_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_76_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_76_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_76_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_76_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_76_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_76_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_76_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_76_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_76_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[69] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1074 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[69] ) ,
+ .ccff_tail ( grid_clb_76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[174] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1075 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1076 ) ,
+ .SC_OUT_BOT ( scff_Wires[175] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1077 ) ,
+ .Test_en_W_in ( Test_enWires[123] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1078 ) ,
+ .Test_en_E_out ( Test_enWires[124] ) , .pReset_N_in ( pResetWires[284] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1079 ) ,
+ .Reset_W_in ( ResetWires[123] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1080 ) ,
+ .Reset_E_out ( ResetWires[124] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[144] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1081 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[265] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[266] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1082 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1083 ) ,
+ .clk_0_N_in ( clk_1_wires[144] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+grid_clb grid_clb_7__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1085 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[71] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1086 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[71] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1087 } ) ,
+ .ccff_head ( cby_1__1__65_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_77_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_77_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_77_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_77_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_77_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_77_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_77_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_77_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_77_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_77_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_77_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_77_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_77_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_77_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_77_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_77_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_77_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_77_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_77_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_77_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_77_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_77_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_77_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_77_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_77_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_77_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_77_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_77_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_77_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_77_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_77_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_77_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[70] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1088 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[70] ) ,
+ .ccff_tail ( grid_clb_77_ccff_tail ) , .SC_IN_TOP ( scff_Wires[172] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1089 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1090 ) ,
+ .SC_OUT_BOT ( scff_Wires[173] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1091 ) ,
+ .Test_en_W_in ( Test_enWires[145] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1092 ) ,
+ .Test_en_E_out ( Test_enWires[146] ) , .pReset_N_in ( pResetWires[333] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1093 ) ,
+ .Reset_W_in ( ResetWires[145] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1094 ) ,
+ .Reset_E_out ( ResetWires[146] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1095 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[143] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[268] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[269] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1096 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1097 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1098 ) ,
+ .clk_0_S_in ( clk_1_wires[143] ) ) ;
+grid_clb grid_clb_7__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1099 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[72] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1100 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[72] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1101 } ) ,
+ .ccff_head ( cby_1__1__66_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_78_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_78_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_78_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_78_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_78_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_78_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_78_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_78_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_78_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_78_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_78_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_78_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_78_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_78_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_78_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_78_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_78_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_78_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_78_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_78_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_78_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_78_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_78_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_78_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_78_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_78_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_78_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_78_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_78_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_78_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_78_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_78_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[71] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1102 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[71] ) ,
+ .ccff_tail ( grid_clb_78_ccff_tail ) , .SC_IN_TOP ( scff_Wires[170] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1103 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1104 ) ,
+ .SC_OUT_BOT ( scff_Wires[171] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1105 ) ,
+ .Test_en_W_in ( Test_enWires[167] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1106 ) ,
+ .Test_en_E_out ( Test_enWires[168] ) , .pReset_N_in ( pResetWires[382] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1107 ) ,
+ .Reset_W_in ( ResetWires[167] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1108 ) ,
+ .Reset_E_out ( ResetWires[168] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[151] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1109 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[271] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[272] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1110 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1111 ) ,
+ .clk_0_N_in ( clk_1_wires[151] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+grid_clb grid_clb_7__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1113 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[73] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1114 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[73] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1115 } ) ,
+ .ccff_head ( cby_1__1__67_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_79_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_79_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_79_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_79_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_79_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_79_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_79_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_79_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_79_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_79_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_79_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_79_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_79_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_79_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_79_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_79_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_79_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_79_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_79_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_79_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_79_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_79_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_79_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_79_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_79_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_79_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_79_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_79_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_79_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_79_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_79_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_79_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[72] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1116 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[72] ) ,
+ .ccff_tail ( grid_clb_79_ccff_tail ) , .SC_IN_TOP ( scff_Wires[168] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1117 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1118 ) ,
+ .SC_OUT_BOT ( scff_Wires[169] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1119 ) ,
+ .Test_en_W_in ( Test_enWires[189] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1120 ) ,
+ .Test_en_E_out ( Test_enWires[190] ) , .pReset_N_in ( pResetWires[431] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1121 ) ,
+ .Reset_W_in ( ResetWires[189] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1122 ) ,
+ .Reset_E_out ( ResetWires[190] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1123 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[150] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[274] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[275] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1124 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1125 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1126 ) ,
+ .clk_0_S_in ( clk_1_wires[150] ) ) ;
+grid_clb grid_clb_7__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1127 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[74] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1128 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[74] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1129 } ) ,
+ .ccff_head ( cby_1__1__68_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_80_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_80_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_80_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_80_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_80_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_80_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_80_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_80_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_80_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_80_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_80_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_80_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_80_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_80_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_80_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_80_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_80_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_80_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_80_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_80_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_80_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_80_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_80_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_80_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_80_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_80_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_80_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_80_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_80_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_80_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_80_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_80_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[73] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1130 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[73] ) ,
+ .ccff_tail ( grid_clb_80_ccff_tail ) , .SC_IN_TOP ( scff_Wires[166] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1131 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1132 ) ,
+ .SC_OUT_BOT ( scff_Wires[167] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1133 ) ,
+ .Test_en_W_in ( Test_enWires[211] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1134 ) ,
+ .Test_en_E_out ( Test_enWires[212] ) , .pReset_N_in ( pResetWires[480] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1135 ) ,
+ .Reset_W_in ( ResetWires[211] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1136 ) ,
+ .Reset_E_out ( ResetWires[212] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[158] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1137 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[277] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[278] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1138 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1139 ) ,
+ .clk_0_N_in ( clk_1_wires[158] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+grid_clb grid_clb_7__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1141 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[75] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1142 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[75] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1143 } ) ,
+ .ccff_head ( cby_1__1__69_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_81_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_81_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_81_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_81_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_81_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_81_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_81_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_81_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_81_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_81_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_81_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_81_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_81_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_81_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_81_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_81_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_81_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_81_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_81_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_81_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_81_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_81_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_81_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_81_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_81_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_81_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_81_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_81_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_81_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_81_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_81_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_81_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[74] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1144 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[74] ) ,
+ .ccff_tail ( grid_clb_81_ccff_tail ) , .SC_IN_TOP ( scff_Wires[164] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1145 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1146 ) ,
+ .SC_OUT_BOT ( scff_Wires[165] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1147 ) ,
+ .Test_en_W_in ( Test_enWires[233] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1148 ) ,
+ .Test_en_E_out ( Test_enWires[234] ) , .pReset_N_in ( pResetWires[529] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1149 ) ,
+ .Reset_W_in ( ResetWires[233] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1150 ) ,
+ .Reset_E_out ( ResetWires[234] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1151 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[157] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[280] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[281] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1152 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1153 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1154 ) ,
+ .clk_0_S_in ( clk_1_wires[157] ) ) ;
+grid_clb grid_clb_7__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1155 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[76] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1156 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[76] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1157 } ) ,
+ .ccff_head ( cby_1__1__70_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_82_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_82_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_82_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_82_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_82_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_82_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_82_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_82_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_82_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_82_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_82_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_82_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_82_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_82_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_82_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_82_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_82_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_82_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_82_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_82_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_82_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_82_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_82_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_82_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_82_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_82_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_82_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_82_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_82_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_82_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_82_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_82_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[75] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1158 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[75] ) ,
+ .ccff_tail ( grid_clb_82_ccff_tail ) , .SC_IN_TOP ( scff_Wires[162] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1159 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1160 ) ,
+ .SC_OUT_BOT ( scff_Wires[163] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1161 ) ,
+ .Test_en_W_in ( Test_enWires[255] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1162 ) ,
+ .Test_en_E_out ( Test_enWires[256] ) , .pReset_N_in ( pResetWires[578] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1163 ) ,
+ .Reset_W_in ( ResetWires[255] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1164 ) ,
+ .Reset_E_out ( ResetWires[256] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[165] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1165 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[283] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[284] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1166 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1167 ) ,
+ .clk_0_N_in ( clk_1_wires[165] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+grid_clb grid_clb_7__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1169 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1170 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1171 } ) ,
+ .ccff_head ( cby_1__1__71_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_83_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_83_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_83_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_83_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_83_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_83_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_83_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_83_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_83_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_83_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_83_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_83_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_83_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_83_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_83_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_83_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_83_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_83_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_83_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_83_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_83_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_83_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_83_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_83_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_83_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_83_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_83_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_83_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_83_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_83_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_83_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_83_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[76] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1172 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[76] ) ,
+ .ccff_tail ( grid_clb_83_ccff_tail ) , .SC_IN_TOP ( scff_Wires[160] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1173 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1174 ) ,
+ .SC_OUT_BOT ( scff_Wires[161] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1175 ) ,
+ .Test_en_W_in ( Test_enWires[277] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1176 ) ,
+ .Test_en_E_out ( Test_enWires[278] ) , .pReset_N_in ( pResetWires[621] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1177 ) ,
+ .Reset_W_in ( ResetWires[277] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1178 ) ,
+ .Reset_E_out ( ResetWires[278] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1179 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[164] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[286] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[287] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1180 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[289] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1181 ) ,
+ .clk_0_S_in ( clk_1_wires[164] ) ) ;
+grid_clb grid_clb_8__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1182 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[77] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1183 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[77] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1184 } ) ,
+ .ccff_head ( cby_1__1__72_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_84_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_84_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_84_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_84_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_84_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_84_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_84_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_84_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_84_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_84_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_84_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_84_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_84_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_84_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_84_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_84_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_84_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_84_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_84_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_84_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_84_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_84_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_84_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_84_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_84_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_84_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_84_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_84_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_84_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_84_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_84_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_84_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1185 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_84_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1186 ) ,
+ .SC_IN_BOT ( scff_Wires[187] ) , .SC_OUT_TOP ( scff_Wires[188] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1187 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1188 ) ,
+ .Test_en_W_in ( Test_enWires[37] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1189 ) ,
+ .Test_en_E_out ( Test_enWires[38] ) , .pReset_N_in ( pResetWires[92] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1190 ) ,
+ .Reset_W_in ( ResetWires[37] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1191 ) ,
+ .Reset_E_out ( ResetWires[38] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[132] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1192 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[291] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[292] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1193 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1194 ) ,
+ .clk_0_N_in ( clk_1_wires[132] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+grid_clb grid_clb_8__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1196 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[78] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1197 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[78] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1198 } ) ,
+ .ccff_head ( cby_1__1__73_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_85_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_85_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_85_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_85_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_85_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_85_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_85_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_85_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_85_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_85_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_85_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_85_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_85_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_85_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_85_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_85_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_85_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_85_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_85_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_85_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_85_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_85_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_85_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_85_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_85_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_85_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_85_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_85_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_85_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_85_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_85_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_85_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[77] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1199 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[77] ) ,
+ .ccff_tail ( grid_clb_85_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1200 ) ,
+ .SC_IN_BOT ( scff_Wires[189] ) , .SC_OUT_TOP ( scff_Wires[190] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1201 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1202 ) ,
+ .Test_en_W_in ( Test_enWires[59] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1203 ) ,
+ .Test_en_E_out ( Test_enWires[60] ) , .pReset_N_in ( pResetWires[141] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1204 ) ,
+ .Reset_W_in ( ResetWires[59] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1205 ) ,
+ .Reset_E_out ( ResetWires[60] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1206 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[131] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[294] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[295] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1207 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1208 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1209 ) ,
+ .clk_0_S_in ( clk_1_wires[131] ) ) ;
+grid_clb grid_clb_8__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1210 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[79] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1211 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[79] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1212 } ) ,
+ .ccff_head ( cby_1__1__74_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_86_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_86_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_86_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_86_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_86_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_86_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_86_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_86_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_86_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_86_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_86_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_86_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_86_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_86_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_86_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_86_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_86_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_86_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_86_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_86_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_86_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_86_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_86_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_86_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_86_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_86_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_86_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_86_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_86_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_86_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_86_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_86_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[78] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1213 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[78] ) ,
+ .ccff_tail ( grid_clb_86_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1214 ) ,
+ .SC_IN_BOT ( scff_Wires[191] ) , .SC_OUT_TOP ( scff_Wires[192] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1215 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1216 ) ,
+ .Test_en_W_in ( Test_enWires[81] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1217 ) ,
+ .Test_en_E_out ( Test_enWires[82] ) , .pReset_N_in ( pResetWires[190] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1218 ) ,
+ .Reset_W_in ( ResetWires[81] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1219 ) ,
+ .Reset_E_out ( ResetWires[82] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[139] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1220 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[297] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[298] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1221 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1222 ) ,
+ .clk_0_N_in ( clk_1_wires[139] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+grid_clb grid_clb_8__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1224 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[80] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1225 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[80] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1226 } ) ,
+ .ccff_head ( cby_1__1__75_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_87_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_87_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_87_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_87_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_87_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_87_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_87_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_87_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_87_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_87_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_87_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_87_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_87_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_87_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_87_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_87_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_87_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_87_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_87_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_87_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_87_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_87_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_87_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_87_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_87_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_87_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_87_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_87_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_87_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_87_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_87_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_87_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[79] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1227 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[79] ) ,
+ .ccff_tail ( grid_clb_87_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1228 ) ,
+ .SC_IN_BOT ( scff_Wires[193] ) , .SC_OUT_TOP ( scff_Wires[194] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1229 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1230 ) ,
+ .Test_en_W_in ( Test_enWires[103] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1231 ) ,
+ .Test_en_E_out ( Test_enWires[104] ) , .pReset_N_in ( pResetWires[239] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1232 ) ,
+ .Reset_W_in ( ResetWires[103] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1233 ) ,
+ .Reset_E_out ( ResetWires[104] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1234 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[138] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[300] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[301] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1235 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1236 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1237 ) ,
+ .clk_0_S_in ( clk_1_wires[138] ) ) ;
+grid_clb grid_clb_8__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1238 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[81] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1239 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[81] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1240 } ) ,
+ .ccff_head ( cby_1__1__76_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_88_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_88_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_88_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_88_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_88_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_88_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_88_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_88_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_88_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_88_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_88_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_88_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_88_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_88_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_88_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_88_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_88_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_88_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_88_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_88_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_88_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_88_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_88_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_88_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_88_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_88_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_88_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_88_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_88_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_88_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_88_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_88_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[80] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1241 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[80] ) ,
+ .ccff_tail ( grid_clb_88_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1242 ) ,
+ .SC_IN_BOT ( scff_Wires[195] ) , .SC_OUT_TOP ( scff_Wires[196] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1243 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1244 ) ,
+ .Test_en_W_in ( Test_enWires[125] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1245 ) ,
+ .Test_en_E_out ( Test_enWires[126] ) , .pReset_N_in ( pResetWires[288] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1246 ) ,
+ .Reset_W_in ( ResetWires[125] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1247 ) ,
+ .Reset_E_out ( ResetWires[126] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[146] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1248 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[303] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[304] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1249 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1250 ) ,
+ .clk_0_N_in ( clk_1_wires[146] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+grid_clb grid_clb_8__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1252 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[82] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1253 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[82] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1254 } ) ,
+ .ccff_head ( cby_1__1__77_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_89_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_89_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_89_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_89_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_89_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_89_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_89_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_89_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_89_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_89_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_89_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_89_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_89_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_89_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_89_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_89_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_89_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_89_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_89_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_89_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_89_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_89_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_89_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_89_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_89_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_89_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_89_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_89_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_89_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_89_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_89_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_89_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[81] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1255 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[81] ) ,
+ .ccff_tail ( grid_clb_89_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1256 ) ,
+ .SC_IN_BOT ( scff_Wires[197] ) , .SC_OUT_TOP ( scff_Wires[198] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1257 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1258 ) ,
+ .Test_en_W_in ( Test_enWires[147] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1259 ) ,
+ .Test_en_E_out ( Test_enWires[148] ) , .pReset_N_in ( pResetWires[337] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1260 ) ,
+ .Reset_W_in ( ResetWires[147] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1261 ) ,
+ .Reset_E_out ( ResetWires[148] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1262 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[145] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[306] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[307] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1263 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1264 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1265 ) ,
+ .clk_0_S_in ( clk_1_wires[145] ) ) ;
+grid_clb grid_clb_8__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1266 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[83] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1267 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[83] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1268 } ) ,
+ .ccff_head ( cby_1__1__78_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_90_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_90_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_90_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_90_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_90_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_90_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_90_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_90_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_90_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_90_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_90_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_90_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_90_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_90_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_90_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_90_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_90_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_90_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_90_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_90_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_90_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_90_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_90_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_90_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_90_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_90_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_90_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_90_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_90_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_90_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_90_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_90_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[82] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1269 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[82] ) ,
+ .ccff_tail ( grid_clb_90_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1270 ) ,
+ .SC_IN_BOT ( scff_Wires[199] ) , .SC_OUT_TOP ( scff_Wires[200] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1271 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1272 ) ,
+ .Test_en_W_in ( Test_enWires[169] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1273 ) ,
+ .Test_en_E_out ( Test_enWires[170] ) , .pReset_N_in ( pResetWires[386] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1274 ) ,
+ .Reset_W_in ( ResetWires[169] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1275 ) ,
+ .Reset_E_out ( ResetWires[170] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[153] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1276 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[309] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[310] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1277 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1278 ) ,
+ .clk_0_N_in ( clk_1_wires[153] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+grid_clb grid_clb_8__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1280 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[84] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1281 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[84] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1282 } ) ,
+ .ccff_head ( cby_1__1__79_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_91_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_91_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_91_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_91_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_91_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_91_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_91_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_91_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_91_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_91_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_91_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_91_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_91_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_91_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_91_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_91_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_91_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_91_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_91_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_91_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_91_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_91_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_91_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_91_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_91_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_91_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_91_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_91_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_91_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_91_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_91_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_91_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[83] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1283 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[83] ) ,
+ .ccff_tail ( grid_clb_91_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1284 ) ,
+ .SC_IN_BOT ( scff_Wires[201] ) , .SC_OUT_TOP ( scff_Wires[202] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1285 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1286 ) ,
+ .Test_en_W_in ( Test_enWires[191] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1287 ) ,
+ .Test_en_E_out ( Test_enWires[192] ) , .pReset_N_in ( pResetWires[435] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1288 ) ,
+ .Reset_W_in ( ResetWires[191] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1289 ) ,
+ .Reset_E_out ( ResetWires[192] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1290 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[152] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[312] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[313] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1291 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1292 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1293 ) ,
+ .clk_0_S_in ( clk_1_wires[152] ) ) ;
+grid_clb grid_clb_8__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1294 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[85] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1295 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[85] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1296 } ) ,
+ .ccff_head ( cby_1__1__80_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_92_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_92_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_92_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_92_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_92_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_92_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_92_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_92_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_92_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_92_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_92_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_92_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_92_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_92_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_92_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_92_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_92_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_92_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_92_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_92_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_92_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_92_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_92_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_92_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_92_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_92_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_92_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_92_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_92_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_92_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_92_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_92_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[84] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1297 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[84] ) ,
+ .ccff_tail ( grid_clb_92_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1298 ) ,
+ .SC_IN_BOT ( scff_Wires[203] ) , .SC_OUT_TOP ( scff_Wires[204] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1299 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1300 ) ,
+ .Test_en_W_in ( Test_enWires[213] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1301 ) ,
+ .Test_en_E_out ( Test_enWires[214] ) , .pReset_N_in ( pResetWires[484] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1302 ) ,
+ .Reset_W_in ( ResetWires[213] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1303 ) ,
+ .Reset_E_out ( ResetWires[214] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[160] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1304 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[315] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[316] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1305 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1306 ) ,
+ .clk_0_N_in ( clk_1_wires[160] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+grid_clb grid_clb_8__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1308 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[86] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1309 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[86] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1310 } ) ,
+ .ccff_head ( cby_1__1__81_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_93_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_93_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_93_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_93_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_93_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_93_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_93_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_93_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_93_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_93_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_93_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_93_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_93_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_93_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_93_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_93_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_93_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_93_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_93_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_93_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_93_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_93_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_93_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_93_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_93_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_93_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_93_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_93_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_93_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_93_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_93_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_93_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[85] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1311 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[85] ) ,
+ .ccff_tail ( grid_clb_93_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1312 ) ,
+ .SC_IN_BOT ( scff_Wires[205] ) , .SC_OUT_TOP ( scff_Wires[206] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1313 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1314 ) ,
+ .Test_en_W_in ( Test_enWires[235] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1315 ) ,
+ .Test_en_E_out ( Test_enWires[236] ) , .pReset_N_in ( pResetWires[533] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1316 ) ,
+ .Reset_W_in ( ResetWires[235] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1317 ) ,
+ .Reset_E_out ( ResetWires[236] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1318 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[159] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[318] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[319] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1319 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1320 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1321 ) ,
+ .clk_0_S_in ( clk_1_wires[159] ) ) ;
+grid_clb grid_clb_8__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1322 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[87] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1323 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[87] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1324 } ) ,
+ .ccff_head ( cby_1__1__82_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_94_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_94_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_94_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_94_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_94_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_94_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_94_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_94_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_94_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_94_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_94_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_94_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_94_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_94_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_94_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_94_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_94_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_94_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_94_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_94_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_94_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_94_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_94_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_94_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_94_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_94_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_94_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_94_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_94_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_94_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_94_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_94_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[86] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1325 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[86] ) ,
+ .ccff_tail ( grid_clb_94_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1326 ) ,
+ .SC_IN_BOT ( scff_Wires[207] ) , .SC_OUT_TOP ( scff_Wires[208] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1327 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1328 ) ,
+ .Test_en_W_in ( Test_enWires[257] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1329 ) ,
+ .Test_en_E_out ( Test_enWires[258] ) , .pReset_N_in ( pResetWires[582] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1330 ) ,
+ .Reset_W_in ( ResetWires[257] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1331 ) ,
+ .Reset_E_out ( ResetWires[258] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[167] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1332 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[321] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[322] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1333 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1334 ) ,
+ .clk_0_N_in ( clk_1_wires[167] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+grid_clb grid_clb_8__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1336 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1337 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1338 } ) ,
+ .ccff_head ( cby_1__1__83_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_95_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_95_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_95_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_95_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_95_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_95_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_95_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_95_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_95_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_95_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_95_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_95_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_95_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_95_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_95_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_95_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_95_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_95_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_95_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_95_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_95_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_95_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_95_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_95_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_95_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_95_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_95_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_95_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_95_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_95_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_95_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_95_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[87] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1339 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[87] ) ,
+ .ccff_tail ( grid_clb_95_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1340 ) ,
+ .SC_IN_BOT ( scff_Wires[209] ) , .SC_OUT_TOP ( scff_Wires[210] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1341 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1342 ) ,
+ .Test_en_W_in ( Test_enWires[279] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1343 ) ,
+ .Test_en_E_out ( Test_enWires[280] ) , .pReset_N_in ( pResetWires[624] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1344 ) ,
+ .Reset_W_in ( ResetWires[279] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1345 ) ,
+ .Reset_E_out ( ResetWires[280] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1346 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[166] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[324] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[325] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1347 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[327] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1348 ) ,
+ .clk_0_S_in ( clk_1_wires[166] ) ) ;
+grid_clb grid_clb_9__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1349 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[88] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1350 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[88] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1351 } ) ,
+ .ccff_head ( cby_1__1__84_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_96_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_96_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_96_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_96_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_96_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_96_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_96_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_96_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_96_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_96_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_96_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_96_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_96_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_96_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_96_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_96_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_96_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_96_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_96_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_96_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_96_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_96_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_96_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_96_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_96_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_96_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_96_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_96_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_96_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_96_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_96_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_96_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1352 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[235] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1353 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1354 ) ,
+ .SC_OUT_BOT ( scff_Wires[237] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1355 ) ,
+ .Test_en_W_in ( Test_enWires[39] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1356 ) ,
+ .Test_en_E_out ( Test_enWires[40] ) , .pReset_N_in ( pResetWires[96] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1357 ) ,
+ .Reset_W_in ( ResetWires[39] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1358 ) ,
+ .Reset_E_out ( ResetWires[40] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[172] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1359 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[329] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[330] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1360 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1361 ) ,
+ .clk_0_N_in ( clk_1_wires[172] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+grid_clb grid_clb_9__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1363 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[89] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1364 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[89] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1365 } ) ,
+ .ccff_head ( cby_1__1__85_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_97_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_97_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_97_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_97_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_97_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_97_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_97_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_97_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_97_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_97_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_97_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_97_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_97_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_97_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_97_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_97_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_97_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_97_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_97_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_97_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_97_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_97_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_97_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_97_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_97_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_97_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_97_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_97_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_97_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_97_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_97_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_97_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[88] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1366 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[88] ) ,
+ .ccff_tail ( grid_clb_97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[233] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1367 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1368 ) ,
+ .SC_OUT_BOT ( scff_Wires[234] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1369 ) ,
+ .Test_en_W_in ( Test_enWires[61] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1370 ) ,
+ .Test_en_E_out ( Test_enWires[62] ) , .pReset_N_in ( pResetWires[145] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1371 ) ,
+ .Reset_W_in ( ResetWires[61] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1372 ) ,
+ .Reset_E_out ( ResetWires[62] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1373 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[171] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[332] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[333] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1374 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1375 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1376 ) ,
+ .clk_0_S_in ( clk_1_wires[171] ) ) ;
+grid_clb grid_clb_9__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1377 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[90] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1378 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[90] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1379 } ) ,
+ .ccff_head ( cby_1__1__86_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_98_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_98_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_98_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_98_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_98_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_98_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_98_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_98_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_98_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_98_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_98_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_98_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_98_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_98_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_98_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_98_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_98_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_98_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_98_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_98_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_98_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_98_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_98_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_98_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_98_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_98_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_98_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_98_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_98_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_98_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_98_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_98_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[89] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1380 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[89] ) ,
+ .ccff_tail ( grid_clb_98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[231] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1381 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1382 ) ,
+ .SC_OUT_BOT ( scff_Wires[232] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1383 ) ,
+ .Test_en_W_in ( Test_enWires[83] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1384 ) ,
+ .Test_en_E_out ( Test_enWires[84] ) , .pReset_N_in ( pResetWires[194] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1385 ) ,
+ .Reset_W_in ( ResetWires[83] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1386 ) ,
+ .Reset_E_out ( ResetWires[84] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[179] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1387 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[335] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[336] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1388 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1389 ) ,
+ .clk_0_N_in ( clk_1_wires[179] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+grid_clb grid_clb_9__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1391 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[91] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1392 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[91] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1393 } ) ,
+ .ccff_head ( cby_1__1__87_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_99_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_99_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_99_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_99_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_99_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_99_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_99_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_99_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_99_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_99_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_99_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_99_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_99_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_99_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_99_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_99_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_99_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_99_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_99_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_99_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_99_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_99_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_99_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_99_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_99_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_99_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_99_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_99_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_99_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_99_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_99_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_99_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[90] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1394 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[90] ) ,
+ .ccff_tail ( grid_clb_99_ccff_tail ) , .SC_IN_TOP ( scff_Wires[229] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1395 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1396 ) ,
+ .SC_OUT_BOT ( scff_Wires[230] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1397 ) ,
+ .Test_en_W_in ( Test_enWires[105] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1398 ) ,
+ .Test_en_E_out ( Test_enWires[106] ) , .pReset_N_in ( pResetWires[243] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1399 ) ,
+ .Reset_W_in ( ResetWires[105] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1400 ) ,
+ .Reset_E_out ( ResetWires[106] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1401 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[178] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[338] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[339] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1402 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1403 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1404 ) ,
+ .clk_0_S_in ( clk_1_wires[178] ) ) ;
+grid_clb grid_clb_9__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1405 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[92] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1406 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[92] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1407 } ) ,
+ .ccff_head ( cby_1__1__88_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_100_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_100_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_100_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_100_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_100_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_100_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_100_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_100_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_100_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_100_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_100_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_100_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_100_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_100_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_100_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_100_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_100_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_100_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_100_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_100_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_100_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_100_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_100_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_100_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_100_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_100_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_100_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_100_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_100_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_100_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_100_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_100_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[91] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1408 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[91] ) ,
+ .ccff_tail ( grid_clb_100_ccff_tail ) , .SC_IN_TOP ( scff_Wires[227] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1409 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1410 ) ,
+ .SC_OUT_BOT ( scff_Wires[228] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1411 ) ,
+ .Test_en_W_in ( Test_enWires[127] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1412 ) ,
+ .Test_en_E_out ( Test_enWires[128] ) , .pReset_N_in ( pResetWires[292] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1413 ) ,
+ .Reset_W_in ( ResetWires[127] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1414 ) ,
+ .Reset_E_out ( ResetWires[128] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[186] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1415 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[341] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[342] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1416 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1417 ) ,
+ .clk_0_N_in ( clk_1_wires[186] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+grid_clb grid_clb_9__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1419 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[93] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1420 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[93] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1421 } ) ,
+ .ccff_head ( cby_1__1__89_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_101_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_101_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_101_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_101_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_101_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_101_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_101_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_101_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_101_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_101_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_101_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_101_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_101_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_101_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_101_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_101_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_101_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_101_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_101_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_101_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_101_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_101_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_101_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_101_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_101_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_101_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_101_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_101_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_101_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_101_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_101_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_101_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[92] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1422 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[92] ) ,
+ .ccff_tail ( grid_clb_101_ccff_tail ) , .SC_IN_TOP ( scff_Wires[225] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1423 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1424 ) ,
+ .SC_OUT_BOT ( scff_Wires[226] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1425 ) ,
+ .Test_en_W_in ( Test_enWires[149] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1426 ) ,
+ .Test_en_E_out ( Test_enWires[150] ) , .pReset_N_in ( pResetWires[341] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1427 ) ,
+ .Reset_W_in ( ResetWires[149] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1428 ) ,
+ .Reset_E_out ( ResetWires[150] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1429 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[185] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[344] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[345] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1430 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1431 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1432 ) ,
+ .clk_0_S_in ( clk_1_wires[185] ) ) ;
+grid_clb grid_clb_9__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1433 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[94] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1434 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[94] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1435 } ) ,
+ .ccff_head ( cby_1__1__90_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_102_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_102_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_102_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_102_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_102_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_102_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_102_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_102_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_102_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_102_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_102_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_102_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_102_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_102_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_102_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_102_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_102_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_102_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_102_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_102_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_102_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_102_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_102_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_102_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_102_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_102_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_102_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_102_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_102_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_102_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_102_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_102_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[93] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1436 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[93] ) ,
+ .ccff_tail ( grid_clb_102_ccff_tail ) , .SC_IN_TOP ( scff_Wires[223] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1437 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1438 ) ,
+ .SC_OUT_BOT ( scff_Wires[224] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1439 ) ,
+ .Test_en_W_in ( Test_enWires[171] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1440 ) ,
+ .Test_en_E_out ( Test_enWires[172] ) , .pReset_N_in ( pResetWires[390] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1441 ) ,
+ .Reset_W_in ( ResetWires[171] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1442 ) ,
+ .Reset_E_out ( ResetWires[172] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[193] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1443 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[347] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[348] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1444 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1445 ) ,
+ .clk_0_N_in ( clk_1_wires[193] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+grid_clb grid_clb_9__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1447 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[95] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1448 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[95] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1449 } ) ,
+ .ccff_head ( cby_1__1__91_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_103_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_103_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_103_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_103_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_103_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_103_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_103_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_103_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_103_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_103_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_103_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_103_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_103_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_103_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_103_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_103_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_103_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_103_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_103_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_103_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_103_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_103_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_103_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_103_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_103_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_103_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_103_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_103_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_103_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_103_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_103_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_103_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[94] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1450 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[94] ) ,
+ .ccff_tail ( grid_clb_103_ccff_tail ) , .SC_IN_TOP ( scff_Wires[221] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1451 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1452 ) ,
+ .SC_OUT_BOT ( scff_Wires[222] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1453 ) ,
+ .Test_en_W_in ( Test_enWires[193] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1454 ) ,
+ .Test_en_E_out ( Test_enWires[194] ) , .pReset_N_in ( pResetWires[439] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1455 ) ,
+ .Reset_W_in ( ResetWires[193] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1456 ) ,
+ .Reset_E_out ( ResetWires[194] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1457 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[192] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[350] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[351] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1458 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1459 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1460 ) ,
+ .clk_0_S_in ( clk_1_wires[192] ) ) ;
+grid_clb grid_clb_9__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1461 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[96] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1462 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[96] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1463 } ) ,
+ .ccff_head ( cby_1__1__92_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_104_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_104_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_104_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_104_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_104_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_104_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_104_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_104_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_104_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_104_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_104_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_104_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_104_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_104_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_104_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_104_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_104_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_104_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_104_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_104_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_104_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_104_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_104_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_104_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_104_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_104_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_104_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_104_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_104_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_104_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_104_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_104_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[95] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1464 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[95] ) ,
+ .ccff_tail ( grid_clb_104_ccff_tail ) , .SC_IN_TOP ( scff_Wires[219] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1465 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1466 ) ,
+ .SC_OUT_BOT ( scff_Wires[220] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1467 ) ,
+ .Test_en_W_in ( Test_enWires[215] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1468 ) ,
+ .Test_en_E_out ( Test_enWires[216] ) , .pReset_N_in ( pResetWires[488] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1469 ) ,
+ .Reset_W_in ( ResetWires[215] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1470 ) ,
+ .Reset_E_out ( ResetWires[216] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[200] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1471 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[353] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[354] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1472 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1473 ) ,
+ .clk_0_N_in ( clk_1_wires[200] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+grid_clb grid_clb_9__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1475 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[97] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1476 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[97] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1477 } ) ,
+ .ccff_head ( cby_1__1__93_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_105_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_105_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_105_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_105_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_105_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_105_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_105_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_105_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_105_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_105_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_105_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_105_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_105_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_105_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_105_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_105_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_105_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_105_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_105_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_105_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_105_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_105_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_105_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_105_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_105_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_105_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_105_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_105_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_105_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_105_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_105_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_105_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[96] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1478 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[96] ) ,
+ .ccff_tail ( grid_clb_105_ccff_tail ) , .SC_IN_TOP ( scff_Wires[217] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1479 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1480 ) ,
+ .SC_OUT_BOT ( scff_Wires[218] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1481 ) ,
+ .Test_en_W_in ( Test_enWires[237] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1482 ) ,
+ .Test_en_E_out ( Test_enWires[238] ) , .pReset_N_in ( pResetWires[537] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1483 ) ,
+ .Reset_W_in ( ResetWires[237] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1484 ) ,
+ .Reset_E_out ( ResetWires[238] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1485 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[199] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[356] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[357] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1486 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1487 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1488 ) ,
+ .clk_0_S_in ( clk_1_wires[199] ) ) ;
+grid_clb grid_clb_9__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1489 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[98] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1490 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[98] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1491 } ) ,
+ .ccff_head ( cby_1__1__94_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_106_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_106_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_106_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_106_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_106_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_106_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_106_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_106_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_106_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_106_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_106_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_106_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_106_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_106_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_106_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_106_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_106_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_106_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_106_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_106_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_106_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_106_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_106_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_106_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_106_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_106_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_106_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_106_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_106_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_106_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_106_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_106_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[97] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1492 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[97] ) ,
+ .ccff_tail ( grid_clb_106_ccff_tail ) , .SC_IN_TOP ( scff_Wires[215] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1493 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1494 ) ,
+ .SC_OUT_BOT ( scff_Wires[216] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1495 ) ,
+ .Test_en_W_in ( Test_enWires[259] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1496 ) ,
+ .Test_en_E_out ( Test_enWires[260] ) , .pReset_N_in ( pResetWires[586] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1497 ) ,
+ .Reset_W_in ( ResetWires[259] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1498 ) ,
+ .Reset_E_out ( ResetWires[260] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[207] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1499 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[359] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[360] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1500 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1501 ) ,
+ .clk_0_N_in ( clk_1_wires[207] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+grid_clb grid_clb_9__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1503 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1504 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1505 } ) ,
+ .ccff_head ( cby_1__1__95_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_107_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_107_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_107_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_107_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_107_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_107_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_107_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_107_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_107_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_107_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_107_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_107_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_107_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_107_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_107_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_107_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_107_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_107_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_107_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_107_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_107_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_107_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_107_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_107_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_107_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_107_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_107_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_107_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_107_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_107_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_107_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_107_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[98] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1506 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[98] ) ,
+ .ccff_tail ( grid_clb_107_ccff_tail ) , .SC_IN_TOP ( scff_Wires[213] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1507 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1508 ) ,
+ .SC_OUT_BOT ( scff_Wires[214] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1509 ) ,
+ .Test_en_W_in ( Test_enWires[281] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1510 ) ,
+ .Test_en_E_out ( Test_enWires[282] ) , .pReset_N_in ( pResetWires[627] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1511 ) ,
+ .Reset_W_in ( ResetWires[281] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1512 ) ,
+ .Reset_E_out ( ResetWires[282] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1513 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[206] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[362] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[363] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1514 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[365] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1515 ) ,
+ .clk_0_S_in ( clk_1_wires[206] ) ) ;
+grid_clb grid_clb_10__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1516 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[99] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1517 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[99] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1518 } ) ,
+ .ccff_head ( cby_1__1__96_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_108_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_108_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_108_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_108_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_108_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_108_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_108_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_108_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_108_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_108_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_108_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_108_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_108_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_108_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_108_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_108_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_108_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_108_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_108_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_108_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_108_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_108_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_108_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_108_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_108_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_108_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_108_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_108_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_108_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_108_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_108_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_108_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1519 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_108_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1520 ) ,
+ .SC_IN_BOT ( scff_Wires[240] ) , .SC_OUT_TOP ( scff_Wires[241] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1521 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1522 ) ,
+ .Test_en_W_in ( Test_enWires[41] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1523 ) ,
+ .Test_en_E_out ( Test_enWires[42] ) , .pReset_N_in ( pResetWires[100] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1524 ) ,
+ .Reset_W_in ( ResetWires[41] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1525 ) ,
+ .Reset_E_out ( ResetWires[42] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[174] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1526 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[367] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[368] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1527 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1528 ) ,
+ .clk_0_N_in ( clk_1_wires[174] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+grid_clb grid_clb_10__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1530 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[100] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1531 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[100] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1532 } ) ,
+ .ccff_head ( cby_1__1__97_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_109_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_109_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_109_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_109_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_109_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_109_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_109_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_109_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_109_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_109_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_109_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_109_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_109_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_109_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_109_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_109_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_109_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_109_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_109_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_109_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_109_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_109_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_109_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_109_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_109_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_109_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_109_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_109_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_109_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_109_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_109_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_109_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[99] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1533 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[99] ) ,
+ .ccff_tail ( grid_clb_109_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1534 ) ,
+ .SC_IN_BOT ( scff_Wires[242] ) , .SC_OUT_TOP ( scff_Wires[243] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1535 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1536 ) ,
+ .Test_en_W_in ( Test_enWires[63] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1537 ) ,
+ .Test_en_E_out ( Test_enWires[64] ) , .pReset_N_in ( pResetWires[149] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1538 ) ,
+ .Reset_W_in ( ResetWires[63] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1539 ) ,
+ .Reset_E_out ( ResetWires[64] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1540 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[173] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[370] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[371] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1541 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1542 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1543 ) ,
+ .clk_0_S_in ( clk_1_wires[173] ) ) ;
+grid_clb grid_clb_10__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1544 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[101] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1545 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[101] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1546 } ) ,
+ .ccff_head ( cby_1__1__98_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_110_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_110_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_110_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_110_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_110_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_110_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_110_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_110_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_110_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_110_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_110_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_110_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_110_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_110_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_110_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_110_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_110_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_110_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_110_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_110_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_110_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_110_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_110_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_110_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_110_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_110_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_110_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_110_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_110_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_110_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_110_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_110_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[100] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1547 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[100] ) ,
+ .ccff_tail ( grid_clb_110_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1548 ) ,
+ .SC_IN_BOT ( scff_Wires[244] ) , .SC_OUT_TOP ( scff_Wires[245] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1549 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1550 ) ,
+ .Test_en_W_in ( Test_enWires[85] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1551 ) ,
+ .Test_en_E_out ( Test_enWires[86] ) , .pReset_N_in ( pResetWires[198] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1552 ) ,
+ .Reset_W_in ( ResetWires[85] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1553 ) ,
+ .Reset_E_out ( ResetWires[86] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[181] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1554 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[373] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[374] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1555 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1556 ) ,
+ .clk_0_N_in ( clk_1_wires[181] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+grid_clb grid_clb_10__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1558 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[102] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1559 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[102] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1560 } ) ,
+ .ccff_head ( cby_1__1__99_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_111_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_111_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_111_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_111_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_111_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_111_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_111_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_111_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_111_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_111_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_111_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_111_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_111_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_111_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_111_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_111_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_111_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_111_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_111_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_111_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_111_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_111_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_111_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_111_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_111_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_111_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_111_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_111_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_111_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_111_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_111_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_111_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[101] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1561 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[101] ) ,
+ .ccff_tail ( grid_clb_111_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1562 ) ,
+ .SC_IN_BOT ( scff_Wires[246] ) , .SC_OUT_TOP ( scff_Wires[247] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1563 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1564 ) ,
+ .Test_en_W_in ( Test_enWires[107] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1565 ) ,
+ .Test_en_E_out ( Test_enWires[108] ) , .pReset_N_in ( pResetWires[247] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1566 ) ,
+ .Reset_W_in ( ResetWires[107] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1567 ) ,
+ .Reset_E_out ( ResetWires[108] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1568 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[180] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[376] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[377] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1569 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1570 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1571 ) ,
+ .clk_0_S_in ( clk_1_wires[180] ) ) ;
+grid_clb grid_clb_10__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1572 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[103] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1573 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[103] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1574 } ) ,
+ .ccff_head ( cby_1__1__100_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_112_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_112_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_112_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_112_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_112_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_112_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_112_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_112_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_112_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_112_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_112_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_112_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_112_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_112_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_112_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_112_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_112_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_112_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_112_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_112_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_112_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_112_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_112_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_112_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_112_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_112_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_112_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_112_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_112_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_112_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_112_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_112_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[102] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1575 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[102] ) ,
+ .ccff_tail ( grid_clb_112_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1576 ) ,
+ .SC_IN_BOT ( scff_Wires[248] ) , .SC_OUT_TOP ( scff_Wires[249] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1577 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1578 ) ,
+ .Test_en_W_in ( Test_enWires[129] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1579 ) ,
+ .Test_en_E_out ( Test_enWires[130] ) , .pReset_N_in ( pResetWires[296] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1580 ) ,
+ .Reset_W_in ( ResetWires[129] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1581 ) ,
+ .Reset_E_out ( ResetWires[130] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[188] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1582 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[379] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[380] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1583 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1584 ) ,
+ .clk_0_N_in ( clk_1_wires[188] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+grid_clb grid_clb_10__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1586 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[104] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1587 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[104] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1588 } ) ,
+ .ccff_head ( cby_1__1__101_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_113_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_113_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_113_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_113_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_113_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_113_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_113_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_113_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_113_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_113_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_113_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_113_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_113_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_113_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_113_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_113_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_113_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_113_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_113_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_113_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_113_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_113_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_113_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_113_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_113_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_113_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_113_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_113_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_113_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_113_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_113_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_113_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[103] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1589 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[103] ) ,
+ .ccff_tail ( grid_clb_113_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1590 ) ,
+ .SC_IN_BOT ( scff_Wires[250] ) , .SC_OUT_TOP ( scff_Wires[251] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1591 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1592 ) ,
+ .Test_en_W_in ( Test_enWires[151] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1593 ) ,
+ .Test_en_E_out ( Test_enWires[152] ) , .pReset_N_in ( pResetWires[345] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1594 ) ,
+ .Reset_W_in ( ResetWires[151] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1595 ) ,
+ .Reset_E_out ( ResetWires[152] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1596 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[187] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[382] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[383] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1597 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1598 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1599 ) ,
+ .clk_0_S_in ( clk_1_wires[187] ) ) ;
+grid_clb grid_clb_10__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1600 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[105] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1601 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[105] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1602 } ) ,
+ .ccff_head ( cby_1__1__102_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_114_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_114_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_114_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_114_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_114_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_114_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_114_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_114_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_114_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_114_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_114_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_114_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_114_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_114_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_114_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_114_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_114_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_114_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_114_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_114_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_114_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_114_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_114_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_114_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_114_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_114_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_114_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_114_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_114_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_114_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_114_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_114_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[104] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1603 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[104] ) ,
+ .ccff_tail ( grid_clb_114_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1604 ) ,
+ .SC_IN_BOT ( scff_Wires[252] ) , .SC_OUT_TOP ( scff_Wires[253] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1605 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1606 ) ,
+ .Test_en_W_in ( Test_enWires[173] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1607 ) ,
+ .Test_en_E_out ( Test_enWires[174] ) , .pReset_N_in ( pResetWires[394] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1608 ) ,
+ .Reset_W_in ( ResetWires[173] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1609 ) ,
+ .Reset_E_out ( ResetWires[174] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[195] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1610 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[385] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[386] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1611 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1612 ) ,
+ .clk_0_N_in ( clk_1_wires[195] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+grid_clb grid_clb_10__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1614 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[106] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1615 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[106] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1616 } ) ,
+ .ccff_head ( cby_1__1__103_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_115_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_115_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_115_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_115_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_115_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_115_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_115_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_115_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_115_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_115_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_115_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_115_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_115_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_115_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_115_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_115_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_115_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_115_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_115_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_115_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_115_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_115_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_115_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_115_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_115_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_115_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_115_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_115_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_115_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_115_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_115_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_115_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[105] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1617 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[105] ) ,
+ .ccff_tail ( grid_clb_115_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1618 ) ,
+ .SC_IN_BOT ( scff_Wires[254] ) , .SC_OUT_TOP ( scff_Wires[255] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1619 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1620 ) ,
+ .Test_en_W_in ( Test_enWires[195] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1621 ) ,
+ .Test_en_E_out ( Test_enWires[196] ) , .pReset_N_in ( pResetWires[443] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1622 ) ,
+ .Reset_W_in ( ResetWires[195] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1623 ) ,
+ .Reset_E_out ( ResetWires[196] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1624 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[194] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[388] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[389] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1625 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1626 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1627 ) ,
+ .clk_0_S_in ( clk_1_wires[194] ) ) ;
+grid_clb grid_clb_10__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1628 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[107] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1629 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[107] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1630 } ) ,
+ .ccff_head ( cby_1__1__104_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_116_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_116_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_116_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_116_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_116_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_116_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_116_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_116_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_116_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_116_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_116_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_116_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_116_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_116_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_116_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_116_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_116_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_116_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_116_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_116_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_116_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_116_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_116_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_116_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_116_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_116_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_116_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_116_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_116_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_116_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_116_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_116_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[106] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1631 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[106] ) ,
+ .ccff_tail ( grid_clb_116_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1632 ) ,
+ .SC_IN_BOT ( scff_Wires[256] ) , .SC_OUT_TOP ( scff_Wires[257] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1633 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1634 ) ,
+ .Test_en_W_in ( Test_enWires[217] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1635 ) ,
+ .Test_en_E_out ( Test_enWires[218] ) , .pReset_N_in ( pResetWires[492] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1636 ) ,
+ .Reset_W_in ( ResetWires[217] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1637 ) ,
+ .Reset_E_out ( ResetWires[218] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[202] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1638 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[391] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[392] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1639 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1640 ) ,
+ .clk_0_N_in ( clk_1_wires[202] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+grid_clb grid_clb_10__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1642 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[108] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1643 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[108] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1644 } ) ,
+ .ccff_head ( cby_1__1__105_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_117_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_117_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_117_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_117_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_117_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_117_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_117_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_117_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_117_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_117_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_117_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_117_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_117_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_117_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_117_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_117_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_117_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_117_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_117_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_117_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_117_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_117_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_117_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_117_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_117_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_117_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_117_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_117_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_117_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_117_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_117_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_117_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[107] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1645 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[107] ) ,
+ .ccff_tail ( grid_clb_117_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1646 ) ,
+ .SC_IN_BOT ( scff_Wires[258] ) , .SC_OUT_TOP ( scff_Wires[259] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1647 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1648 ) ,
+ .Test_en_W_in ( Test_enWires[239] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1649 ) ,
+ .Test_en_E_out ( Test_enWires[240] ) , .pReset_N_in ( pResetWires[541] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1650 ) ,
+ .Reset_W_in ( ResetWires[239] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1651 ) ,
+ .Reset_E_out ( ResetWires[240] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1652 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[201] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[394] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[395] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1653 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1654 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1655 ) ,
+ .clk_0_S_in ( clk_1_wires[201] ) ) ;
+grid_clb grid_clb_10__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1656 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[109] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1657 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[109] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1658 } ) ,
+ .ccff_head ( cby_1__1__106_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_118_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_118_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_118_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_118_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_118_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_118_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_118_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_118_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_118_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_118_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_118_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_118_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_118_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_118_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_118_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_118_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_118_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_118_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_118_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_118_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_118_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_118_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_118_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_118_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_118_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_118_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_118_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_118_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_118_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_118_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_118_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_118_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[108] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1659 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[108] ) ,
+ .ccff_tail ( grid_clb_118_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1660 ) ,
+ .SC_IN_BOT ( scff_Wires[260] ) , .SC_OUT_TOP ( scff_Wires[261] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1661 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1662 ) ,
+ .Test_en_W_in ( Test_enWires[261] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1663 ) ,
+ .Test_en_E_out ( Test_enWires[262] ) , .pReset_N_in ( pResetWires[590] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1664 ) ,
+ .Reset_W_in ( ResetWires[261] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1665 ) ,
+ .Reset_E_out ( ResetWires[262] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[209] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1666 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[397] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[398] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1667 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1668 ) ,
+ .clk_0_N_in ( clk_1_wires[209] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+grid_clb grid_clb_10__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1670 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1671 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1672 } ) ,
+ .ccff_head ( cby_1__1__107_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_119_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_119_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_119_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_119_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_119_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_119_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_119_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_119_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_119_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_119_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_119_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_119_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_119_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_119_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_119_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_119_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_119_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_119_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_119_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_119_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_119_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_119_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_119_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_119_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_119_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_119_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_119_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_119_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_119_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_119_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_119_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_119_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[109] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1673 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[109] ) ,
+ .ccff_tail ( grid_clb_119_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1674 ) ,
+ .SC_IN_BOT ( scff_Wires[262] ) , .SC_OUT_TOP ( scff_Wires[263] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1675 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1676 ) ,
+ .Test_en_W_in ( Test_enWires[283] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1677 ) ,
+ .Test_en_E_out ( Test_enWires[284] ) , .pReset_N_in ( pResetWires[630] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1678 ) ,
+ .Reset_W_in ( ResetWires[283] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1679 ) ,
+ .Reset_E_out ( ResetWires[284] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1680 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[208] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[400] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[401] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1681 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[403] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1682 ) ,
+ .clk_0_S_in ( clk_1_wires[208] ) ) ;
+grid_clb grid_clb_11__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1683 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[110] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1684 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[110] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1685 } ) ,
+ .ccff_head ( cby_1__1__108_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_120_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_120_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_120_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_120_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_120_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_120_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_120_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_120_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_120_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_120_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_120_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_120_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_120_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_120_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_120_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_120_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_120_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_120_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_120_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_120_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_120_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_120_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_120_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_120_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_120_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_120_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_120_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_120_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_120_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_120_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_120_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_120_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1686 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[288] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1687 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1688 ) ,
+ .SC_OUT_BOT ( scff_Wires[290] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1689 ) ,
+ .Test_en_W_in ( Test_enWires[43] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1690 ) ,
+ .Test_en_E_out ( Test_enWires[44] ) , .pReset_N_in ( pResetWires[104] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1691 ) ,
+ .Reset_W_in ( ResetWires[43] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1692 ) ,
+ .Reset_E_out ( ResetWires[44] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[214] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1693 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[405] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[406] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1694 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1695 ) ,
+ .clk_0_N_in ( clk_1_wires[214] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+grid_clb grid_clb_11__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1697 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[111] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1698 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[111] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1699 } ) ,
+ .ccff_head ( cby_1__1__109_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_121_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_121_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_121_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_121_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_121_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_121_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_121_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_121_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_121_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_121_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_121_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_121_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_121_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_121_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_121_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_121_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_121_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_121_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_121_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_121_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_121_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_121_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_121_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_121_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_121_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_121_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_121_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_121_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_121_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_121_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_121_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_121_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[110] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1700 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[110] ) ,
+ .ccff_tail ( grid_clb_121_ccff_tail ) , .SC_IN_TOP ( scff_Wires[286] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1701 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1702 ) ,
+ .SC_OUT_BOT ( scff_Wires[287] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1703 ) ,
+ .Test_en_W_in ( Test_enWires[65] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1704 ) ,
+ .Test_en_E_out ( Test_enWires[66] ) , .pReset_N_in ( pResetWires[153] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1705 ) ,
+ .Reset_W_in ( ResetWires[65] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1706 ) ,
+ .Reset_E_out ( ResetWires[66] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1707 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[213] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[408] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[409] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1708 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1709 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1710 ) ,
+ .clk_0_S_in ( clk_1_wires[213] ) ) ;
+grid_clb grid_clb_11__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1711 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[112] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1712 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[112] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1713 } ) ,
+ .ccff_head ( cby_1__1__110_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_122_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_122_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_122_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_122_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_122_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_122_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_122_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_122_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_122_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_122_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_122_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_122_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_122_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_122_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_122_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_122_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_122_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_122_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_122_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_122_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_122_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_122_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_122_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_122_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_122_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_122_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_122_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_122_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_122_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_122_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_122_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_122_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[111] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1714 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[111] ) ,
+ .ccff_tail ( grid_clb_122_ccff_tail ) , .SC_IN_TOP ( scff_Wires[284] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1715 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1716 ) ,
+ .SC_OUT_BOT ( scff_Wires[285] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1717 ) ,
+ .Test_en_W_in ( Test_enWires[87] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1718 ) ,
+ .Test_en_E_out ( Test_enWires[88] ) , .pReset_N_in ( pResetWires[202] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1719 ) ,
+ .Reset_W_in ( ResetWires[87] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1720 ) ,
+ .Reset_E_out ( ResetWires[88] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[221] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1721 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[411] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[412] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1722 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1723 ) ,
+ .clk_0_N_in ( clk_1_wires[221] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+grid_clb grid_clb_11__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1725 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[113] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1726 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[113] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1727 } ) ,
+ .ccff_head ( cby_1__1__111_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_123_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_123_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_123_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_123_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_123_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_123_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_123_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_123_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_123_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_123_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_123_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_123_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_123_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_123_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_123_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_123_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_123_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_123_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_123_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_123_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_123_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_123_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_123_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_123_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_123_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_123_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_123_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_123_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_123_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_123_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_123_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_123_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[112] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1728 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[112] ) ,
+ .ccff_tail ( grid_clb_123_ccff_tail ) , .SC_IN_TOP ( scff_Wires[282] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1729 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1730 ) ,
+ .SC_OUT_BOT ( scff_Wires[283] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1731 ) ,
+ .Test_en_W_in ( Test_enWires[109] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1732 ) ,
+ .Test_en_E_out ( Test_enWires[110] ) , .pReset_N_in ( pResetWires[251] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1733 ) ,
+ .Reset_W_in ( ResetWires[109] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1734 ) ,
+ .Reset_E_out ( ResetWires[110] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1735 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[220] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[414] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[415] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1736 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1737 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1738 ) ,
+ .clk_0_S_in ( clk_1_wires[220] ) ) ;
+grid_clb grid_clb_11__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1739 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[114] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1740 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[114] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1741 } ) ,
+ .ccff_head ( cby_1__1__112_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_124_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_124_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_124_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_124_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_124_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_124_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_124_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_124_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_124_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_124_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_124_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_124_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_124_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_124_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_124_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_124_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_124_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_124_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_124_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_124_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_124_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_124_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_124_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_124_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_124_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_124_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_124_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_124_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_124_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_124_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_124_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_124_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[113] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1742 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[113] ) ,
+ .ccff_tail ( grid_clb_124_ccff_tail ) , .SC_IN_TOP ( scff_Wires[280] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1743 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1744 ) ,
+ .SC_OUT_BOT ( scff_Wires[281] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1745 ) ,
+ .Test_en_W_in ( Test_enWires[131] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1746 ) ,
+ .Test_en_E_out ( Test_enWires[132] ) , .pReset_N_in ( pResetWires[300] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1747 ) ,
+ .Reset_W_in ( ResetWires[131] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1748 ) ,
+ .Reset_E_out ( ResetWires[132] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[228] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1749 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[417] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[418] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1750 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1751 ) ,
+ .clk_0_N_in ( clk_1_wires[228] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+grid_clb grid_clb_11__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1753 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[115] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1754 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[115] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1755 } ) ,
+ .ccff_head ( cby_1__1__113_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_125_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_125_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_125_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_125_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_125_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_125_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_125_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_125_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_125_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_125_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_125_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_125_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_125_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_125_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_125_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_125_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_125_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_125_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_125_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_125_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_125_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_125_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_125_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_125_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_125_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_125_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_125_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_125_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_125_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_125_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_125_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_125_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[114] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1756 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[114] ) ,
+ .ccff_tail ( grid_clb_125_ccff_tail ) , .SC_IN_TOP ( scff_Wires[278] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1757 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1758 ) ,
+ .SC_OUT_BOT ( scff_Wires[279] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1759 ) ,
+ .Test_en_W_in ( Test_enWires[153] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1760 ) ,
+ .Test_en_E_out ( Test_enWires[154] ) , .pReset_N_in ( pResetWires[349] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1761 ) ,
+ .Reset_W_in ( ResetWires[153] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1762 ) ,
+ .Reset_E_out ( ResetWires[154] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1763 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[227] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[420] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[421] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1764 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1765 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1766 ) ,
+ .clk_0_S_in ( clk_1_wires[227] ) ) ;
+grid_clb grid_clb_11__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1767 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[116] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1768 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[116] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1769 } ) ,
+ .ccff_head ( cby_1__1__114_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_126_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_126_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_126_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_126_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_126_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_126_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_126_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_126_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_126_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_126_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_126_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_126_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_126_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_126_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_126_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_126_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_126_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_126_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_126_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_126_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_126_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_126_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_126_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_126_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_126_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_126_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_126_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_126_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_126_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_126_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_126_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_126_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[115] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1770 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[115] ) ,
+ .ccff_tail ( grid_clb_126_ccff_tail ) , .SC_IN_TOP ( scff_Wires[276] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1771 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1772 ) ,
+ .SC_OUT_BOT ( scff_Wires[277] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1773 ) ,
+ .Test_en_W_in ( Test_enWires[175] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1774 ) ,
+ .Test_en_E_out ( Test_enWires[176] ) , .pReset_N_in ( pResetWires[398] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1775 ) ,
+ .Reset_W_in ( ResetWires[175] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1776 ) ,
+ .Reset_E_out ( ResetWires[176] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[235] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1777 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[423] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[424] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1778 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1779 ) ,
+ .clk_0_N_in ( clk_1_wires[235] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+grid_clb grid_clb_11__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1781 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[117] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1782 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[117] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1783 } ) ,
+ .ccff_head ( cby_1__1__115_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_127_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_127_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_127_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_127_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_127_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_127_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_127_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_127_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_127_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_127_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_127_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_127_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_127_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_127_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_127_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_127_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_127_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_127_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_127_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_127_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_127_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_127_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_127_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_127_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_127_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_127_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_127_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_127_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_127_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_127_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_127_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_127_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[116] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1784 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[116] ) ,
+ .ccff_tail ( grid_clb_127_ccff_tail ) , .SC_IN_TOP ( scff_Wires[274] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1785 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1786 ) ,
+ .SC_OUT_BOT ( scff_Wires[275] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1787 ) ,
+ .Test_en_W_in ( Test_enWires[197] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1788 ) ,
+ .Test_en_E_out ( Test_enWires[198] ) , .pReset_N_in ( pResetWires[447] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1789 ) ,
+ .Reset_W_in ( ResetWires[197] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1790 ) ,
+ .Reset_E_out ( ResetWires[198] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1791 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[234] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[426] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[427] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1792 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1793 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1794 ) ,
+ .clk_0_S_in ( clk_1_wires[234] ) ) ;
+grid_clb grid_clb_11__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1795 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[118] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1796 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[118] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1797 } ) ,
+ .ccff_head ( cby_1__1__116_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_128_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_128_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_128_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_128_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_128_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_128_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_128_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_128_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_128_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_128_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_128_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_128_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_128_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_128_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_128_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_128_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_128_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_128_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_128_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_128_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_128_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_128_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_128_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_128_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_128_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_128_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_128_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_128_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_128_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_128_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_128_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_128_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[117] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1798 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[117] ) ,
+ .ccff_tail ( grid_clb_128_ccff_tail ) , .SC_IN_TOP ( scff_Wires[272] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1799 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1800 ) ,
+ .SC_OUT_BOT ( scff_Wires[273] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1801 ) ,
+ .Test_en_W_in ( Test_enWires[219] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1802 ) ,
+ .Test_en_E_out ( Test_enWires[220] ) , .pReset_N_in ( pResetWires[496] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1803 ) ,
+ .Reset_W_in ( ResetWires[219] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1804 ) ,
+ .Reset_E_out ( ResetWires[220] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[242] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1805 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[429] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[430] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1806 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1807 ) ,
+ .clk_0_N_in ( clk_1_wires[242] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+grid_clb grid_clb_11__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1809 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[119] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1810 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[119] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1811 } ) ,
+ .ccff_head ( cby_1__1__117_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_129_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_129_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_129_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_129_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_129_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_129_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_129_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_129_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_129_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_129_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_129_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_129_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_129_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_129_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_129_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_129_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_129_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_129_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_129_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_129_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_129_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_129_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_129_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_129_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_129_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_129_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_129_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_129_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_129_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_129_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_129_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_129_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[118] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1812 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[118] ) ,
+ .ccff_tail ( grid_clb_129_ccff_tail ) , .SC_IN_TOP ( scff_Wires[270] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1813 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1814 ) ,
+ .SC_OUT_BOT ( scff_Wires[271] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1815 ) ,
+ .Test_en_W_in ( Test_enWires[241] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1816 ) ,
+ .Test_en_E_out ( Test_enWires[242] ) , .pReset_N_in ( pResetWires[545] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1817 ) ,
+ .Reset_W_in ( ResetWires[241] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1818 ) ,
+ .Reset_E_out ( ResetWires[242] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1819 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[241] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[432] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[433] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1820 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1821 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1822 ) ,
+ .clk_0_S_in ( clk_1_wires[241] ) ) ;
+grid_clb grid_clb_11__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1823 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[120] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1824 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[120] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1825 } ) ,
+ .ccff_head ( cby_1__1__118_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_130_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_130_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_130_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_130_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_130_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_130_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_130_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_130_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_130_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_130_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_130_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_130_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_130_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_130_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_130_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_130_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_130_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_130_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_130_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_130_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_130_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_130_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_130_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_130_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_130_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_130_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_130_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_130_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_130_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_130_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_130_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_130_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[119] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1826 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[119] ) ,
+ .ccff_tail ( grid_clb_130_ccff_tail ) , .SC_IN_TOP ( scff_Wires[268] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1827 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1828 ) ,
+ .SC_OUT_BOT ( scff_Wires[269] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1829 ) ,
+ .Test_en_W_in ( Test_enWires[263] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1830 ) ,
+ .Test_en_E_out ( Test_enWires[264] ) , .pReset_N_in ( pResetWires[594] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1831 ) ,
+ .Reset_W_in ( ResetWires[263] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1832 ) ,
+ .Reset_E_out ( ResetWires[264] ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[249] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1833 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[435] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[436] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1834 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1835 ) ,
+ .clk_0_N_in ( clk_1_wires[249] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+grid_clb grid_clb_11__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1837 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1838 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1839 } ) ,
+ .ccff_head ( cby_1__1__119_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_131_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_131_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_131_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_131_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_131_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_131_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_131_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_131_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_131_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_131_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_131_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_131_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_131_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_131_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_131_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_131_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_131_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_131_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_131_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_131_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_131_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_131_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_131_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_131_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_131_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_131_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_131_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_131_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_131_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_131_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_131_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_131_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[120] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1840 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[120] ) ,
+ .ccff_tail ( grid_clb_131_ccff_tail ) , .SC_IN_TOP ( scff_Wires[266] ) ,
+ .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1841 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1842 ) ,
+ .SC_OUT_BOT ( scff_Wires[267] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1843 ) ,
+ .Test_en_W_in ( Test_enWires[285] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1844 ) ,
+ .Test_en_E_out ( Test_enWires[286] ) , .pReset_N_in ( pResetWires[633] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1845 ) ,
+ .Reset_W_in ( ResetWires[285] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1846 ) ,
+ .Reset_E_out ( ResetWires[286] ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1847 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[248] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[438] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[439] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1848 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[441] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1849 ) ,
+ .clk_0_S_in ( clk_1_wires[248] ) ) ;
+grid_clb grid_clb_12__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1850 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[121] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1851 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[121] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1852 } ) ,
+ .ccff_head ( cby_1__1__120_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_132_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_132_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_132_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_132_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_132_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_132_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_132_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_132_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_132_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_132_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_132_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_132_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_132_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_132_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_132_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_132_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_132_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_132_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_132_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_132_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_132_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_132_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_132_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_132_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_132_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_132_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_132_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_132_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_132_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_132_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_132_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_132_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1853 } ) ,
+
+ .bottom_width_0_height_0__pin_54_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ) ,
+ .ccff_tail ( grid_clb_132_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1854 ) ,
+ .SC_IN_BOT ( scff_Wires[293] ) , .SC_OUT_TOP ( scff_Wires[294] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1855 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1856 ) ,
+ .Test_en_W_in ( Test_enWires[45] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1857 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1858 ) ,
+ .pReset_N_in ( pResetWires[108] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1859 ) ,
+ .Reset_W_in ( ResetWires[45] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1860 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1861 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[216] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1862 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[443] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[444] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1863 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1864 ) ,
+ .clk_0_N_in ( clk_1_wires[216] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+grid_clb grid_clb_12__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1866 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[122] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1867 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[122] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1868 } ) ,
+ .ccff_head ( cby_1__1__121_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_133_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_133_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_133_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_133_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_133_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_133_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_133_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_133_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_133_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_133_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_133_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_133_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_133_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_133_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_133_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_133_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_133_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_133_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_133_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_133_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_133_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_133_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_133_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_133_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_133_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_133_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_133_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_133_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_133_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_133_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_133_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_133_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[121] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1869 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[121] ) ,
+ .ccff_tail ( grid_clb_133_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1870 ) ,
+ .SC_IN_BOT ( scff_Wires[295] ) , .SC_OUT_TOP ( scff_Wires[296] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1871 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1872 ) ,
+ .Test_en_W_in ( Test_enWires[67] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1873 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1874 ) ,
+ .pReset_N_in ( pResetWires[157] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1875 ) ,
+ .Reset_W_in ( ResetWires[67] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1876 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1877 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1878 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[215] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[446] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[447] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1879 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1880 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1881 ) ,
+ .clk_0_S_in ( clk_1_wires[215] ) ) ;
+grid_clb grid_clb_12__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1882 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[123] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1883 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[123] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1884 } ) ,
+ .ccff_head ( cby_1__1__122_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_134_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_134_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_134_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_134_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_134_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_134_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_134_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_134_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_134_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_134_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_134_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_134_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_134_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_134_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_134_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_134_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_134_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_134_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_134_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_134_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_134_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_134_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_134_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_134_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_134_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_134_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_134_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_134_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_134_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_134_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_134_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_134_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[122] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1885 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[122] ) ,
+ .ccff_tail ( grid_clb_134_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1886 ) ,
+ .SC_IN_BOT ( scff_Wires[297] ) , .SC_OUT_TOP ( scff_Wires[298] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1887 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1888 ) ,
+ .Test_en_W_in ( Test_enWires[89] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1889 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1890 ) ,
+ .pReset_N_in ( pResetWires[206] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1891 ) ,
+ .Reset_W_in ( ResetWires[89] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1892 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1893 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[223] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1894 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[449] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[450] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1895 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1896 ) ,
+ .clk_0_N_in ( clk_1_wires[223] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+grid_clb grid_clb_12__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1898 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[124] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1899 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[124] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1900 } ) ,
+ .ccff_head ( cby_1__1__123_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_135_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_135_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_135_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_135_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_135_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_135_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_135_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_135_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_135_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_135_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_135_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_135_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_135_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_135_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_135_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_135_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_135_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_135_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_135_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_135_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_135_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_135_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_135_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_135_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_135_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_135_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_135_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_135_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_135_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_135_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_135_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_135_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[123] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1901 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[123] ) ,
+ .ccff_tail ( grid_clb_135_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1902 ) ,
+ .SC_IN_BOT ( scff_Wires[299] ) , .SC_OUT_TOP ( scff_Wires[300] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1903 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1904 ) ,
+ .Test_en_W_in ( Test_enWires[111] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1905 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1906 ) ,
+ .pReset_N_in ( pResetWires[255] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1907 ) ,
+ .Reset_W_in ( ResetWires[111] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1908 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1909 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1910 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[222] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[452] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[453] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1911 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1912 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1913 ) ,
+ .clk_0_S_in ( clk_1_wires[222] ) ) ;
+grid_clb grid_clb_12__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1914 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[125] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1915 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[125] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1916 } ) ,
+ .ccff_head ( cby_1__1__124_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_136_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_136_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_136_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_136_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_136_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_136_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_136_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_136_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_136_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_136_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_136_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_136_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_136_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_136_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_136_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_136_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_136_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_136_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_136_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_136_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_136_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_136_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_136_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_136_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_136_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_136_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_136_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_136_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_136_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_136_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_136_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_136_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[124] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1917 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[124] ) ,
+ .ccff_tail ( grid_clb_136_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1918 ) ,
+ .SC_IN_BOT ( scff_Wires[301] ) , .SC_OUT_TOP ( scff_Wires[302] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1919 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1920 ) ,
+ .Test_en_W_in ( Test_enWires[133] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1921 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1922 ) ,
+ .pReset_N_in ( pResetWires[304] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1923 ) ,
+ .Reset_W_in ( ResetWires[133] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1924 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1925 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[230] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1926 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[455] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[456] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1927 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1928 ) ,
+ .clk_0_N_in ( clk_1_wires[230] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+grid_clb grid_clb_12__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1930 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[126] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1931 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[126] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1932 } ) ,
+ .ccff_head ( cby_1__1__125_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_137_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_137_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_137_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_137_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_137_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_137_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_137_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_137_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_137_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_137_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_137_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_137_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_137_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_137_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_137_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_137_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_137_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_137_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_137_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_137_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_137_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_137_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_137_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_137_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_137_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_137_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_137_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_137_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_137_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_137_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_137_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_137_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[125] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1933 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[125] ) ,
+ .ccff_tail ( grid_clb_137_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1934 ) ,
+ .SC_IN_BOT ( scff_Wires[303] ) , .SC_OUT_TOP ( scff_Wires[304] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1935 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1936 ) ,
+ .Test_en_W_in ( Test_enWires[155] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1937 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1938 ) ,
+ .pReset_N_in ( pResetWires[353] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1939 ) ,
+ .Reset_W_in ( ResetWires[155] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1940 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1941 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1942 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[229] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[458] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[459] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1943 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1944 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1945 ) ,
+ .clk_0_S_in ( clk_1_wires[229] ) ) ;
+grid_clb grid_clb_12__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1946 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[127] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1947 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[127] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1948 } ) ,
+ .ccff_head ( cby_1__1__126_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_138_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_138_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_138_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_138_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_138_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_138_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_138_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_138_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_138_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_138_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_138_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_138_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_138_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_138_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_138_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_138_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_138_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_138_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_138_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_138_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_138_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_138_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_138_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_138_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_138_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_138_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_138_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_138_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_138_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_138_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_138_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_138_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[126] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1949 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[126] ) ,
+ .ccff_tail ( grid_clb_138_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1950 ) ,
+ .SC_IN_BOT ( scff_Wires[305] ) , .SC_OUT_TOP ( scff_Wires[306] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1951 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1952 ) ,
+ .Test_en_W_in ( Test_enWires[177] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1953 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1954 ) ,
+ .pReset_N_in ( pResetWires[402] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1955 ) ,
+ .Reset_W_in ( ResetWires[177] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1956 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1957 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[237] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1958 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[461] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[462] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1959 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1960 ) ,
+ .clk_0_N_in ( clk_1_wires[237] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+grid_clb grid_clb_12__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1962 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[128] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1963 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[128] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1964 } ) ,
+ .ccff_head ( cby_1__1__127_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_139_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_139_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_139_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_139_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_139_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_139_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_139_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_139_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_139_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_139_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_139_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_139_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_139_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_139_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_139_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_139_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_139_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_139_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_139_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_139_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_139_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_139_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_139_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_139_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_139_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_139_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_139_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_139_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_139_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_139_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_139_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_139_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[127] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1965 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[127] ) ,
+ .ccff_tail ( grid_clb_139_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1966 ) ,
+ .SC_IN_BOT ( scff_Wires[307] ) , .SC_OUT_TOP ( scff_Wires[308] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1967 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1968 ) ,
+ .Test_en_W_in ( Test_enWires[199] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1969 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1970 ) ,
+ .pReset_N_in ( pResetWires[451] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1971 ) ,
+ .Reset_W_in ( ResetWires[199] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1972 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1973 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1974 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[236] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[464] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[465] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1975 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1976 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1977 ) ,
+ .clk_0_S_in ( clk_1_wires[236] ) ) ;
+grid_clb grid_clb_12__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1978 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[129] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1979 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[129] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1980 } ) ,
+ .ccff_head ( cby_1__1__128_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_140_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_140_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_140_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_140_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_140_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_140_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_140_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_140_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_140_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_140_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_140_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_140_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_140_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_140_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_140_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_140_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_140_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_140_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_140_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_140_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_140_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_140_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_140_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_140_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_140_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_140_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_140_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_140_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_140_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_140_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_140_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_140_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[128] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1981 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[128] ) ,
+ .ccff_tail ( grid_clb_140_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1982 ) ,
+ .SC_IN_BOT ( scff_Wires[309] ) , .SC_OUT_TOP ( scff_Wires[310] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1983 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1984 ) ,
+ .Test_en_W_in ( Test_enWires[221] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1985 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1986 ) ,
+ .pReset_N_in ( pResetWires[500] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_1987 ) ,
+ .Reset_W_in ( ResetWires[221] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_1988 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_1989 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[244] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1990 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[467] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[468] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1991 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1992 ) ,
+ .clk_0_N_in ( clk_1_wires[244] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+grid_clb grid_clb_12__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_1994 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[130] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1995 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[130] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_1996 } ) ,
+ .ccff_head ( cby_1__1__129_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_141_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_141_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_141_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_141_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_141_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_141_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_141_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_141_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_141_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_141_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_141_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_141_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_141_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_141_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_141_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_141_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_141_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_141_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_141_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_141_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_141_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_141_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_141_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_141_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_141_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_141_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_141_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_141_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_141_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_141_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_141_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_141_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[129] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1997 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[129] ) ,
+ .ccff_tail ( grid_clb_141_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1998 ) ,
+ .SC_IN_BOT ( scff_Wires[311] ) , .SC_OUT_TOP ( scff_Wires[312] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1999 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2000 ) ,
+ .Test_en_W_in ( Test_enWires[243] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2001 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2002 ) ,
+ .pReset_N_in ( pResetWires[549] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_2003 ) ,
+ .Reset_W_in ( ResetWires[243] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_2004 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_2005 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2006 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[243] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[470] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[471] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2007 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2008 ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2009 ) ,
+ .clk_0_S_in ( clk_1_wires[243] ) ) ;
+grid_clb grid_clb_12__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2010 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[131] ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2011 } ) ,
+ .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[131] ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_2012 } ) ,
+ .ccff_head ( cby_1__1__130_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_142_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_142_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_142_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_142_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_142_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_142_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_142_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_142_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_142_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_142_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_142_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_142_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_142_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_142_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_142_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_142_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_142_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_142_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_142_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_142_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_142_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_142_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_142_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_142_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_142_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_142_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_142_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_142_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_142_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_142_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_142_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_142_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[130] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2013 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[130] ) ,
+ .ccff_tail ( grid_clb_142_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2014 ) ,
+ .SC_IN_BOT ( scff_Wires[313] ) , .SC_OUT_TOP ( scff_Wires[314] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2015 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2016 ) ,
+ .Test_en_W_in ( Test_enWires[265] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2017 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2018 ) ,
+ .pReset_N_in ( pResetWires[598] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_2019 ) ,
+ .Reset_W_in ( ResetWires[265] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_2020 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_2021 ) ,
+ .prog_clk_0_N_in ( prog_clk_1_wires[251] ) ,
+ .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_2022 ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[473] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[474] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2023 ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2024 ) ,
+ .clk_0_N_in ( clk_1_wires[251] ) ,
+ .clk_0_S_in ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+grid_clb grid_clb_12__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2026 } ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) ,
+ .top_width_0_height_0__pin_32_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ) ,
+ .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2027 } ) ,
+
+ .top_width_0_height_0__pin_34_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ) ,
+ .right_width_0_height_0__pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) ,
+ .right_width_0_height_0__pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) ,
+ .right_width_0_height_0__pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) ,
+ .right_width_0_height_0__pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) ,
+ .right_width_0_height_0__pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) ,
+ .right_width_0_height_0__pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) ,
+ .right_width_0_height_0__pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) ,
+ .right_width_0_height_0__pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) ,
+ .right_width_0_height_0__pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) ,
+ .right_width_0_height_0__pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) ,
+ .right_width_0_height_0__pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) ,
+ .right_width_0_height_0__pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) ,
+ .right_width_0_height_0__pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) ,
+ .right_width_0_height_0__pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) ,
+ .right_width_0_height_0__pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) ,
+ .right_width_0_height_0__pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) ,
+ .Reset ( { SYNOPSYS_UNCONNECTED_2028 } ) ,
+ .ccff_head ( cby_1__1__131_ccff_tail ) ,
+ .top_width_0_height_0__pin_36_upper ( grid_clb_143_top_width_0_height_0__pin_36_upper ) ,
+ .top_width_0_height_0__pin_36_lower ( grid_clb_143_top_width_0_height_0__pin_36_lower ) ,
+ .top_width_0_height_0__pin_37_upper ( grid_clb_143_top_width_0_height_0__pin_37_upper ) ,
+ .top_width_0_height_0__pin_37_lower ( grid_clb_143_top_width_0_height_0__pin_37_lower ) ,
+ .top_width_0_height_0__pin_38_upper ( grid_clb_143_top_width_0_height_0__pin_38_upper ) ,
+ .top_width_0_height_0__pin_38_lower ( grid_clb_143_top_width_0_height_0__pin_38_lower ) ,
+ .top_width_0_height_0__pin_39_upper ( grid_clb_143_top_width_0_height_0__pin_39_upper ) ,
+ .top_width_0_height_0__pin_39_lower ( grid_clb_143_top_width_0_height_0__pin_39_lower ) ,
+ .top_width_0_height_0__pin_40_upper ( grid_clb_143_top_width_0_height_0__pin_40_upper ) ,
+ .top_width_0_height_0__pin_40_lower ( grid_clb_143_top_width_0_height_0__pin_40_lower ) ,
+ .top_width_0_height_0__pin_41_upper ( grid_clb_143_top_width_0_height_0__pin_41_upper ) ,
+ .top_width_0_height_0__pin_41_lower ( grid_clb_143_top_width_0_height_0__pin_41_lower ) ,
+ .top_width_0_height_0__pin_42_upper ( grid_clb_143_top_width_0_height_0__pin_42_upper ) ,
+ .top_width_0_height_0__pin_42_lower ( grid_clb_143_top_width_0_height_0__pin_42_lower ) ,
+ .top_width_0_height_0__pin_43_upper ( grid_clb_143_top_width_0_height_0__pin_43_upper ) ,
+ .top_width_0_height_0__pin_43_lower ( grid_clb_143_top_width_0_height_0__pin_43_lower ) ,
+ .right_width_0_height_0__pin_44_upper ( grid_clb_143_right_width_0_height_0__pin_44_upper ) ,
+ .right_width_0_height_0__pin_44_lower ( grid_clb_143_right_width_0_height_0__pin_44_lower ) ,
+ .right_width_0_height_0__pin_45_upper ( grid_clb_143_right_width_0_height_0__pin_45_upper ) ,
+ .right_width_0_height_0__pin_45_lower ( grid_clb_143_right_width_0_height_0__pin_45_lower ) ,
+ .right_width_0_height_0__pin_46_upper ( grid_clb_143_right_width_0_height_0__pin_46_upper ) ,
+ .right_width_0_height_0__pin_46_lower ( grid_clb_143_right_width_0_height_0__pin_46_lower ) ,
+ .right_width_0_height_0__pin_47_upper ( grid_clb_143_right_width_0_height_0__pin_47_upper ) ,
+ .right_width_0_height_0__pin_47_lower ( grid_clb_143_right_width_0_height_0__pin_47_lower ) ,
+ .right_width_0_height_0__pin_48_upper ( grid_clb_143_right_width_0_height_0__pin_48_upper ) ,
+ .right_width_0_height_0__pin_48_lower ( grid_clb_143_right_width_0_height_0__pin_48_lower ) ,
+ .right_width_0_height_0__pin_49_upper ( grid_clb_143_right_width_0_height_0__pin_49_upper ) ,
+ .right_width_0_height_0__pin_49_lower ( grid_clb_143_right_width_0_height_0__pin_49_lower ) ,
+ .right_width_0_height_0__pin_50_upper ( grid_clb_143_right_width_0_height_0__pin_50_upper ) ,
+ .right_width_0_height_0__pin_50_lower ( grid_clb_143_right_width_0_height_0__pin_50_lower ) ,
+ .right_width_0_height_0__pin_51_upper ( grid_clb_143_right_width_0_height_0__pin_51_upper ) ,
+ .right_width_0_height_0__pin_51_lower ( grid_clb_143_right_width_0_height_0__pin_51_lower ) ,
+ .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[131] ) ,
+ .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2029 } ) ,
+ .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[131] ) ,
+ .ccff_tail ( grid_clb_143_ccff_tail ) ,
+ .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2030 ) ,
+ .SC_IN_BOT ( scff_Wires[315] ) , .SC_OUT_TOP ( scff_Wires[316] ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2031 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2032 ) ,
+ .Test_en_W_in ( Test_enWires[287] ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2033 ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2034 ) ,
+ .pReset_N_in ( pResetWires[636] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_2035 ) ,
+ .Reset_W_in ( ResetWires[287] ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_2036 ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_2037 ) ,
+ .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2038 ) ,
+ .prog_clk_0_S_in ( prog_clk_1_wires[250] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[476] ) ,
+ .prog_clk_0_E_out ( prog_clk_0_wires[477] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2039 ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[479] ) ,
+ .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2040 ) ,
+ .clk_0_S_in ( clk_1_wires[250] ) ) ;
+sb_0__0_ sb_0__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2041 } ) ,
+ .chany_top_in ( cby_0__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__0__0_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) ,
+ .ccff_head ( grid_io_bottom_11_ccff_tail ) ,
+ .chany_top_out ( sb_0__0__0_chany_top_out ) ,
+ .chanx_right_out ( sb_0__0__0_chanx_right_out ) ,
+ .ccff_tail ( ccff_tail ) , .pReset_E_in ( pResetWires[25] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[5] ) ) ;
+sb_0__1_ sb_0__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2042 } ) ,
+ .chany_top_in ( cby_0__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__0_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__0_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__0_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__0_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__0_ccff_tail ) , .pReset_E_in ( pResetWires[61] ) ,
+ .pReset_S_out ( pResetWires[64] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[4] ) ) ;
+sb_0__1_ sb_0__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2043 } ) ,
+ .chany_top_in ( cby_0__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__1_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__1_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__1_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__1_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__1_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__1_ccff_tail ) , .pReset_E_in ( pResetWires[110] ) ,
+ .pReset_S_out ( pResetWires[113] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[10] ) ) ;
+sb_0__1_ sb_0__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2044 } ) ,
+ .chany_top_in ( cby_0__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__2_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__2_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__2_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__2_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__2_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__2_ccff_tail ) , .pReset_E_in ( pResetWires[159] ) ,
+ .pReset_S_out ( pResetWires[162] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[15] ) ) ;
+sb_0__1_ sb_0__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2045 } ) ,
+ .chany_top_in ( cby_0__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__3_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__3_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__3_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__3_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__3_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__3_ccff_tail ) , .pReset_E_in ( pResetWires[208] ) ,
+ .pReset_S_out ( pResetWires[211] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[20] ) ) ;
+sb_0__1_ sb_0__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2046 } ) ,
+ .chany_top_in ( cby_0__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__4_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__4_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__4_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__4_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__4_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__4_ccff_tail ) , .pReset_E_in ( pResetWires[257] ) ,
+ .pReset_S_out ( pResetWires[260] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[25] ) ) ;
+sb_0__1_ sb_0__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2047 } ) ,
+ .chany_top_in ( cby_0__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__5_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__5_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__5_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__5_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__5_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__5_ccff_tail ) , .pReset_E_in ( pResetWires[306] ) ,
+ .pReset_S_out ( pResetWires[309] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[30] ) ) ;
+sb_0__1_ sb_0__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2048 } ) ,
+ .chany_top_in ( cby_0__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__6_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__6_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__6_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__6_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__6_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__6_ccff_tail ) , .pReset_E_in ( pResetWires[355] ) ,
+ .pReset_S_out ( pResetWires[358] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[35] ) ) ;
+sb_0__1_ sb_0__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2049 } ) ,
+ .chany_top_in ( cby_0__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__7_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__7_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__7_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__7_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__7_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__7_ccff_tail ) , .pReset_E_in ( pResetWires[404] ) ,
+ .pReset_S_out ( pResetWires[407] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[40] ) ) ;
+sb_0__1_ sb_0__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2050 } ) ,
+ .chany_top_in ( cby_0__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__8_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__8_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__8_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__8_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__8_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__8_ccff_tail ) , .pReset_E_in ( pResetWires[453] ) ,
+ .pReset_S_out ( pResetWires[456] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[45] ) ) ;
+sb_0__1_ sb_0__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2051 } ) ,
+ .chany_top_in ( cby_0__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__9_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__9_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__9_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__9_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__9_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__9_ccff_tail ) , .pReset_E_in ( pResetWires[502] ) ,
+ .pReset_S_out ( pResetWires[505] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[50] ) ) ;
+sb_0__1_ sb_0__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2052 } ) ,
+ .chany_top_in ( cby_0__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) ,
+ .chanx_right_in ( cbx_1__1__10_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__10_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( cbx_1__1__10_ccff_tail ) ,
+ .chany_top_out ( sb_0__1__10_chany_top_out ) ,
+ .chanx_right_out ( sb_0__1__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__1__10_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__1__10_ccff_tail ) , .pReset_E_in ( pResetWires[551] ) ,
+ .pReset_S_out ( pResetWires[554] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[55] ) ) ;
+sb_0__2_ sb_0__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2053 } ) ,
+ .chanx_right_in ( cbx_1__12__0_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_0__1__11_chany_top_out ) ,
+ .bottom_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) ,
+ .ccff_head ( grid_io_top_0_ccff_tail ) ,
+ .chanx_right_out ( sb_0__12__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_0__12__0_chany_bottom_out ) ,
+ .ccff_tail ( sb_0__12__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) ,
+ .SC_OUT_BOT ( scff_Wires[0] ) , .pReset_E_in ( pResetWires[600] ) ,
+ .pReset_S_out ( pResetWires[603] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[62] ) ) ;
+sb_1__0_ sb_1__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2054 } ) ,
+ .chany_top_in ( cby_1__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__1_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__0_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_10_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__0_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__0_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) ,
+ .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p862 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2055 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2056 ) ,
+ .pReset_E_in ( pResetWires[28] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2057 ) ,
+ .pReset_N_out ( pResetWires[27] ) , .pReset_W_out ( pResetWires[26] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( p862 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p862 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p862 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+sb_1__0_ sb_2__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) ,
+ .chany_top_in ( cby_1__1__12_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__2_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__1_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_9_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__1_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__1_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1149 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( p1285 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2064 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2065 ) ,
+ .pReset_E_in ( pResetWires[31] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2066 ) ,
+ .pReset_N_out ( pResetWires[30] ) , .pReset_W_out ( pResetWires[29] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( p1285 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p1285 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p1285 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+sb_1__0_ sb_3__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) ,
+ .chany_top_in ( cby_1__1__24_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__3_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__2_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_8_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__2_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__2_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) ,
+ .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1198 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2072 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2073 ) ,
+ .pReset_E_in ( pResetWires[34] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2074 ) ,
+ .pReset_N_out ( pResetWires[33] ) , .pReset_W_out ( pResetWires[32] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( p1198 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1198 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1198 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+sb_1__0_ sb_4__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) ,
+ .chany_top_in ( cby_1__1__36_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__4_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__3_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_7_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__3_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__3_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1282 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( p1191 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2081 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2082 ) ,
+ .pReset_E_in ( pResetWires[37] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2083 ) ,
+ .pReset_N_out ( pResetWires[36] ) , .pReset_W_out ( pResetWires[35] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( p1191 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1191 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1191 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+sb_1__0_ sb_5__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) ,
+ .chany_top_in ( cby_1__1__48_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__5_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__4_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_6_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__4_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__4_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) ,
+ .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1008 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2089 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2090 ) ,
+ .pReset_E_in ( pResetWires[40] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2091 ) ,
+ .pReset_N_out ( pResetWires[39] ) , .pReset_W_out ( pResetWires[38] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( p1008 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1008 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1008 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+sb_1__0_ sb_6__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) ,
+ .chany_top_in ( cby_1__1__60_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__6_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__5_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_5_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__5_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__5_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1212 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2097 ) , .Test_en_S_in ( Test_en[0] ) ,
+ .Test_en_N_out ( Test_enWires[1] ) , .pReset_S_in ( pReset[0] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2098 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2099 ) ,
+ .pReset_N_out ( pResetWires[42] ) , .pReset_W_out ( pResetWires[41] ) ,
+ .pReset_E_out ( pResetWires[43] ) , .Reset_S_in ( Reset[0] ) ,
+ .Reset_N_out ( ResetWires[1] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[217] ) ,
+ .prog_clk_3_S_in ( prog_clk[0] ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[90] ) , .clk_3_S_in ( clk[0] ) ,
+ .clk_3_N_out ( clk_3_wires[90] ) ) ;
+sb_1__0_ sb_7__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2100 } ) ,
+ .chany_top_in ( cby_1__1__72_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__7_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__6_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_4_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__6_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__6_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) ,
+ .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p611 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2101 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2102 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2103 ) ,
+ .pReset_W_in ( pResetWires[44] ) , .pReset_N_out ( pResetWires[45] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2104 ) ,
+ .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( p611 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2105 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p611 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p611 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+sb_1__0_ sb_8__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2108 } ) ,
+ .chany_top_in ( cby_1__1__84_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__8_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__7_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_3_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__7_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__7_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p613 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2109 ) , .Test_en_S_in ( p1324 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2110 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2111 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2112 ) ,
+ .pReset_W_in ( pResetWires[47] ) , .pReset_N_out ( pResetWires[48] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2113 ) ,
+ .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( p1324 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2114 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p1324 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p1324 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+sb_1__0_ sb_9__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2117 } ) ,
+ .chany_top_in ( cby_1__1__96_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__9_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__8_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_2_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__8_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__8_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) ,
+ .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p1074 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2118 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2119 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2120 ) ,
+ .pReset_W_in ( pResetWires[50] ) , .pReset_N_out ( pResetWires[51] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2121 ) ,
+ .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( p1074 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2122 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1074 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p1074 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+sb_1__0_ sb_10__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2125 } ) ,
+ .chany_top_in ( cby_1__1__108_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__10_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__9_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_1_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__9_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__9_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1213 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2126 ) , .Test_en_S_in ( p1091 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2127 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2128 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2129 ) ,
+ .pReset_W_in ( pResetWires[53] ) , .pReset_N_out ( pResetWires[54] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2130 ) ,
+ .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( p1091 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2131 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1091 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p1091 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+sb_1__0_ sb_11__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2134 } ) ,
+ .chany_top_in ( cby_1__1__120_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__0__11_chanx_left_out ) ,
+ .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) ,
+ .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) ,
+ .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) ,
+ .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) ,
+ .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) ,
+ .right_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) ,
+ .right_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) ,
+ .right_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) ,
+ .chanx_left_in ( cbx_1__0__10_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_bottom_0_ccff_tail ) ,
+ .chany_top_out ( sb_1__0__10_chany_top_out ) ,
+ .chanx_right_out ( sb_1__0__10_chanx_right_out ) ,
+ .chanx_left_out ( sb_1__0__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) ,
+ .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1031 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2135 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2136 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_2137 ) ,
+ .pReset_W_in ( pResetWires[56] ) , .pReset_N_out ( pResetWires[57] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_2138 ) ,
+ .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( p1031 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2139 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1031 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1031 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+sb_1__1_ sb_1__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2142 } ) ,
+ .chany_top_in ( cby_1__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__11_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__0_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__0_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__11_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__0_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p3105 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2143 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2144 ) ,
+ .pReset_E_in ( pResetWires[66] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2145 ) ,
+ .pReset_N_out ( pResetWires[65] ) , .pReset_W_out ( pResetWires[62] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2146 ) , .Reset_S_in ( p3280 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2147 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[8] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[4] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2148 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[1] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3125 ) ,
+ .prog_clk_2_E_in ( p255 ) , .prog_clk_2_S_in ( p1158 ) ,
+ .prog_clk_2_W_in ( p2616 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2149 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2150 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2151 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2152 ) ,
+ .prog_clk_3_W_in ( p2725 ) , .prog_clk_3_E_in ( p801 ) ,
+ .prog_clk_3_S_in ( p6 ) , .prog_clk_3_N_in ( p3014 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2153 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2154 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2155 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2156 ) ,
+ .clk_1_N_in ( clk_2_wires[4] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2157 ) ,
+ .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) ,
+ .clk_2_N_in ( p2501 ) , .clk_2_E_in ( p847 ) , .clk_2_S_in ( p3204 ) ,
+ .clk_2_W_in ( p2272 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2158 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2159 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2160 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2161 ) , .clk_3_W_in ( p2503 ) ,
+ .clk_3_E_in ( p745 ) , .clk_3_S_in ( p123 ) , .clk_3_N_in ( p2370 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2162 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2163 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2164 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+sb_1__1_ sb_1__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2166 } ) ,
+ .chany_top_in ( cby_1__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__12_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__1_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__1_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__12_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__1_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2394 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2167 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2168 ) ,
+ .pReset_E_in ( pResetWires[115] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2169 ) ,
+ .pReset_N_out ( pResetWires[114] ) , .pReset_W_out ( pResetWires[111] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , .Reset_S_in ( p2549 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2171 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p2160 ) ,
+ .prog_clk_1_S_in ( p654 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2172 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2173 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2174 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[1] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2175 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2176 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2177 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[3] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2178 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2179 ) ,
+ .prog_clk_3_W_in ( p2537 ) , .prog_clk_3_E_in ( p858 ) ,
+ .prog_clk_3_S_in ( p644 ) , .prog_clk_3_N_in ( p199 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2180 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2181 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2182 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p2938 ) ,
+ .clk_1_S_in ( p88 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2185 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2186 ) ,
+ .clk_2_E_in ( clk_2_wires[1] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2187 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2188 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2189 ) ,
+ .clk_2_S_out ( clk_2_wires[3] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2190 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p2393 ) ,
+ .clk_3_E_in ( p332 ) , .clk_3_S_in ( p2294 ) , .clk_3_N_in ( p2876 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2192 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2193 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2194 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sb_1__1_ sb_1__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2196 } ) ,
+ .chany_top_in ( cby_1__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__13_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__2_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__2_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__13_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__2_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p2536 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2197 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2198 ) ,
+ .pReset_E_in ( pResetWires[164] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2199 ) ,
+ .pReset_N_out ( pResetWires[163] ) , .pReset_W_out ( pResetWires[160] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2200 ) , .Reset_S_in ( p3353 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2201 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[18] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[11] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2202 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[8] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3597 ) ,
+ .prog_clk_2_E_in ( p152 ) , .prog_clk_2_S_in ( p950 ) ,
+ .prog_clk_2_W_in ( p3462 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2203 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2204 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2205 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2206 ) ,
+ .prog_clk_3_W_in ( p3483 ) , .prog_clk_3_E_in ( p957 ) ,
+ .prog_clk_3_S_in ( p71 ) , .prog_clk_3_N_in ( p3585 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2207 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2208 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2209 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2210 ) ,
+ .clk_1_N_in ( clk_2_wires[11] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2211 ) ,
+ .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) ,
+ .clk_2_N_in ( p1871 ) , .clk_2_E_in ( p664 ) , .clk_2_S_in ( p3289 ) ,
+ .clk_2_W_in ( p3043 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2212 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2213 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2214 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2215 ) , .clk_3_W_in ( p3132 ) ,
+ .clk_3_E_in ( p440 ) , .clk_3_S_in ( p293 ) , .clk_3_N_in ( p1967 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2216 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2217 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2218 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+sb_1__1_ sb_1__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2220 } ) ,
+ .chany_top_in ( cby_1__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__14_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__3_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__3_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__14_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__3_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p2512 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2221 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2222 ) ,
+ .pReset_E_in ( pResetWires[213] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2223 ) ,
+ .pReset_N_out ( pResetWires[212] ) , .pReset_W_out ( pResetWires[209] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , .Reset_S_in ( p2512 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2225 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p1402 ) ,
+ .prog_clk_1_S_in ( p949 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2226 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2227 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2228 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[6] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2229 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2230 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2231 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[10] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[8] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2232 ) ,
+ .prog_clk_3_W_in ( p599 ) , .prog_clk_3_E_in ( p1632 ) ,
+ .prog_clk_3_S_in ( p259 ) , .prog_clk_3_N_in ( p110 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2233 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2234 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2235 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2236 ) , .clk_1_N_in ( p2455 ) ,
+ .clk_1_S_in ( p98 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2238 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2239 ) ,
+ .clk_2_E_in ( clk_2_wires[6] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2240 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2241 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2242 ) ,
+ .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2243 ) , .clk_3_W_in ( p599 ) ,
+ .clk_3_E_in ( p1519 ) , .clk_3_S_in ( p2300 ) , .clk_3_N_in ( p2273 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2244 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2245 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2246 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+sb_1__1_ sb_1__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2248 } ) ,
+ .chany_top_in ( cby_1__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__15_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__4_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__4_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__15_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__4_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p3505 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2249 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2250 ) ,
+ .pReset_E_in ( pResetWires[262] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2251 ) ,
+ .pReset_N_out ( pResetWires[261] ) , .pReset_W_out ( pResetWires[258] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2252 ) , .Reset_S_in ( p3624 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2253 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[28] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2254 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[9] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[15] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3497 ) ,
+ .prog_clk_2_E_in ( p467 ) , .prog_clk_2_S_in ( p388 ) ,
+ .prog_clk_2_W_in ( p3019 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2255 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2256 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2257 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2258 ) ,
+ .prog_clk_3_W_in ( p3095 ) , .prog_clk_3_E_in ( p1004 ) ,
+ .prog_clk_3_S_in ( p980 ) , .prog_clk_3_N_in ( p3480 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2259 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2260 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2261 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2262 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2263 ) ,
+ .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) ,
+ .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3583 ) ,
+ .clk_2_E_in ( p686 ) , .clk_2_S_in ( p3609 ) , .clk_2_W_in ( p2806 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2264 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2265 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2266 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2267 ) , .clk_3_W_in ( p2961 ) ,
+ .clk_3_E_in ( p522 ) , .clk_3_S_in ( p1039 ) , .clk_3_N_in ( p3558 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2268 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2269 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2270 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+sb_1__1_ sb_1__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2272 } ) ,
+ .chany_top_in ( cby_1__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__16_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__5_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__5_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__16_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__5_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p1102 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2273 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2274 ) ,
+ .pReset_E_in ( pResetWires[311] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2275 ) ,
+ .pReset_N_out ( pResetWires[310] ) , .pReset_W_out ( pResetWires[307] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , .Reset_S_in ( p1102 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2277 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p1296 ) ,
+ .prog_clk_1_S_in ( p679 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2278 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2279 ) ,
+ .prog_clk_2_N_in ( p3540 ) , .prog_clk_2_E_in ( p678 ) ,
+ .prog_clk_2_S_in ( p217 ) , .prog_clk_2_W_in ( p2641 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2280 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2281 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2282 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2283 ) ,
+ .prog_clk_3_W_in ( p2786 ) , .prog_clk_3_E_in ( p498 ) ,
+ .prog_clk_3_S_in ( p1157 ) , .prog_clk_3_N_in ( p3522 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2284 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2285 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2286 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_1_N_in ( p2737 ) ,
+ .clk_1_S_in ( p67 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2288 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2289 ) , .clk_2_N_in ( p3344 ) ,
+ .clk_2_E_in ( p878 ) , .clk_2_S_in ( p416 ) , .clk_2_W_in ( p3181 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2290 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2291 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2292 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2293 ) , .clk_3_W_in ( p3270 ) ,
+ .clk_3_E_in ( p24 ) , .clk_3_S_in ( p1165 ) , .clk_3_N_in ( p3304 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2294 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2295 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2296 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+sb_1__1_ sb_1__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2298 } ) ,
+ .chany_top_in ( cby_1__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__17_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__6_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__6_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__17_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__6_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2135 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2299 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2300 ) ,
+ .pReset_E_in ( pResetWires[360] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2301 ) ,
+ .pReset_N_out ( pResetWires[359] ) , .pReset_W_out ( pResetWires[356] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2302 ) , .Reset_S_in ( p3606 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2303 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[38] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[18] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2304 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[22] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3537 ) ,
+ .prog_clk_2_E_in ( p159 ) , .prog_clk_2_S_in ( p1053 ) ,
+ .prog_clk_2_W_in ( p3613 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2305 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2306 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2307 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2308 ) ,
+ .prog_clk_3_W_in ( p3618 ) , .prog_clk_3_E_in ( p524 ) ,
+ .prog_clk_3_S_in ( p58 ) , .prog_clk_3_N_in ( p3528 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2309 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2310 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2311 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2312 ) ,
+ .clk_1_N_in ( clk_2_wires[18] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2313 ) ,
+ .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) ,
+ .clk_2_N_in ( p2775 ) , .clk_2_E_in ( p872 ) , .clk_2_S_in ( p3593 ) ,
+ .clk_2_W_in ( p2629 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2315 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2316 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , .clk_3_W_in ( p2793 ) ,
+ .clk_3_E_in ( p723 ) , .clk_3_S_in ( p1144 ) , .clk_3_N_in ( p2613 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2318 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2319 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2320 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+sb_1__1_ sb_1__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2322 } ) ,
+ .chany_top_in ( cby_1__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__18_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__7_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__7_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__18_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__7_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p1761 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2323 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2324 ) ,
+ .pReset_E_in ( pResetWires[409] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2325 ) ,
+ .pReset_N_out ( pResetWires[408] ) , .pReset_W_out ( pResetWires[405] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , .Reset_S_in ( p1761 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2327 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p1706 ) ,
+ .prog_clk_1_S_in ( p1077 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2328 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2329 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2330 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[13] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2331 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2332 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2333 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[17] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[15] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2334 ) ,
+ .prog_clk_3_W_in ( p1747 ) , .prog_clk_3_E_in ( p1500 ) ,
+ .prog_clk_3_S_in ( p48 ) , .prog_clk_3_N_in ( p413 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2335 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2336 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2337 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2338 ) , .clk_1_N_in ( p1800 ) ,
+ .clk_1_S_in ( p196 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2339 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2340 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2341 ) ,
+ .clk_2_E_in ( clk_2_wires[13] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2342 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2343 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2344 ) ,
+ .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2345 ) , .clk_3_W_in ( p1747 ) ,
+ .clk_3_E_in ( p1549 ) , .clk_3_S_in ( p1471 ) , .clk_3_N_in ( p1485 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2346 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2347 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2348 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+sb_1__1_ sb_1__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2350 } ) ,
+ .chany_top_in ( cby_1__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__19_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__8_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__8_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__19_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__8_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p3538 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2351 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2352 ) ,
+ .pReset_E_in ( pResetWires[458] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2353 ) ,
+ .pReset_N_out ( pResetWires[457] ) , .pReset_W_out ( pResetWires[454] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2354 ) , .Reset_S_in ( p3650 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2355 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[48] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2356 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[16] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[29] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3539 ) ,
+ .prog_clk_2_E_in ( p588 ) , .prog_clk_2_S_in ( p165 ) ,
+ .prog_clk_2_W_in ( p2000 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2357 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2358 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2359 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2360 ) ,
+ .prog_clk_3_W_in ( p2069 ) , .prog_clk_3_E_in ( p17 ) ,
+ .prog_clk_3_S_in ( p1086 ) , .prog_clk_3_N_in ( p3524 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2361 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2362 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2363 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2364 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2365 ) ,
+ .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) ,
+ .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p2996 ) ,
+ .clk_2_E_in ( p966 ) , .clk_2_S_in ( p3641 ) , .clk_2_W_in ( p2360 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2366 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2367 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2368 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_3_W_in ( p2389 ) ,
+ .clk_3_E_in ( p554 ) , .clk_3_S_in ( p547 ) , .clk_3_N_in ( p2810 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2370 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2371 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2372 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+sb_1__1_ sb_1__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2374 } ) ,
+ .chany_top_in ( cby_1__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__20_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__9_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__9_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__20_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__9_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2906 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2375 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2376 ) ,
+ .pReset_E_in ( pResetWires[507] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2377 ) ,
+ .pReset_N_out ( pResetWires[506] ) , .pReset_W_out ( pResetWires[503] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , .Reset_S_in ( p2906 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2379 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p1778 ) ,
+ .prog_clk_1_S_in ( p61 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2380 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2381 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2382 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[20] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2383 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2384 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2385 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2386 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[22] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2387 ) ,
+ .prog_clk_3_W_in ( p1841 ) , .prog_clk_3_E_in ( p265 ) ,
+ .prog_clk_3_S_in ( p578 ) , .prog_clk_3_N_in ( p203 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2388 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2389 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2390 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2391 ) , .clk_1_N_in ( p3104 ) ,
+ .clk_1_S_in ( p968 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2392 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2393 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2394 ) ,
+ .clk_2_E_in ( clk_2_wires[20] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2395 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2396 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2397 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2398 ) ,
+ .clk_2_N_out ( clk_2_wires[22] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_3_W_in ( p1841 ) ,
+ .clk_3_E_in ( p148 ) , .clk_3_S_in ( p2871 ) , .clk_3_N_in ( p3038 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2400 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2401 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2402 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+sb_1__1_ sb_1__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2404 } ) ,
+ .chany_top_in ( cby_1__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__21_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__10_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__10_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__21_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__10_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p2723 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2405 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2406 ) ,
+ .pReset_E_in ( pResetWires[556] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2407 ) ,
+ .pReset_N_out ( pResetWires[555] ) , .pReset_W_out ( pResetWires[552] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2408 ) , .Reset_S_in ( p2723 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2409 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[58] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2410 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[23] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[36] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p2979 ) ,
+ .prog_clk_2_E_in ( p656 ) , .prog_clk_2_S_in ( p765 ) ,
+ .prog_clk_2_W_in ( p3588 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2411 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2412 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2413 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2414 ) ,
+ .prog_clk_3_W_in ( p3598 ) , .prog_clk_3_E_in ( p1052 ) ,
+ .prog_clk_3_S_in ( p538 ) , .prog_clk_3_N_in ( p2818 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2415 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2416 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2417 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2418 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2419 ) ,
+ .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) ,
+ .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p3277 ) ,
+ .clk_2_E_in ( p9 ) , .clk_2_S_in ( p2595 ) , .clk_2_W_in ( p2630 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2420 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2421 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2422 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_3_W_in ( p2715 ) ,
+ .clk_3_E_in ( p788 ) , .clk_3_S_in ( p91 ) , .clk_3_N_in ( p3183 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2424 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2425 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2426 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+sb_1__1_ sb_2__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2428 } ) ,
+ .chany_top_in ( cby_1__1__13_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__22_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__12_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__11_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__22_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__11_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__11_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__11_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p2072 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2429 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2430 ) ,
+ .pReset_E_in ( pResetWires[70] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2431 ) ,
+ .pReset_N_out ( pResetWires[69] ) , .pReset_W_out ( pResetWires[67] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , .Reset_S_in ( p2072 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2433 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p1199 ) ,
+ .prog_clk_1_S_in ( p468 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2434 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2435 ) ,
+ .prog_clk_2_N_in ( p2922 ) , .prog_clk_2_E_in ( p454 ) ,
+ .prog_clk_2_S_in ( p1152 ) , .prog_clk_2_W_in ( p3653 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2436 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2437 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2438 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2439 ) ,
+ .prog_clk_3_W_in ( p3656 ) , .prog_clk_3_E_in ( p84 ) ,
+ .prog_clk_3_S_in ( p337 ) , .prog_clk_3_N_in ( p2836 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2440 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2441 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2442 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_1_N_in ( p3234 ) ,
+ .clk_1_S_in ( p339 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2444 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_2_N_in ( p3433 ) ,
+ .clk_2_E_in ( p736 ) , .clk_2_S_in ( p1930 ) , .clk_2_W_in ( p2031 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2446 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2447 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2448 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_3_W_in ( p2234 ) ,
+ .clk_3_E_in ( p770 ) , .clk_3_S_in ( p615 ) , .clk_3_N_in ( p3400 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2450 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2451 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2452 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+sb_1__1_ sb_2__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2454 } ) ,
+ .chany_top_in ( cby_1__1__14_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__23_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__13_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__12_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__23_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__12_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__12_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__12_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p2695 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2455 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2456 ) ,
+ .pReset_E_in ( pResetWires[119] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2457 ) ,
+ .pReset_N_out ( pResetWires[118] ) , .pReset_W_out ( pResetWires[116] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , .Reset_S_in ( p2695 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2459 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p1682 ) ,
+ .prog_clk_1_S_in ( p234 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2460 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2461 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[69] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2462 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2463 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2464 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[2] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2465 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2466 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2467 ) ,
+ .prog_clk_3_W_in ( p1767 ) , .prog_clk_3_E_in ( p501 ) ,
+ .prog_clk_3_S_in ( p636 ) , .prog_clk_3_N_in ( p229 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2468 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2469 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2470 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , .clk_1_N_in ( p3082 ) ,
+ .clk_1_S_in ( p1006 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2472 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2473 ) ,
+ .clk_2_N_in ( clk_3_wires[69] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2474 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2475 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2476 ) ,
+ .clk_2_W_out ( clk_2_wires[2] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2477 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2478 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2479 ) , .clk_3_W_in ( p1767 ) ,
+ .clk_3_E_in ( p266 ) , .clk_3_S_in ( p2634 ) , .clk_3_N_in ( p3036 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2480 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2481 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2482 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+sb_1__1_ sb_2__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2484 } ) ,
+ .chany_top_in ( cby_1__1__15_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__24_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__14_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__13_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__24_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__13_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__13_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__13_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p3446 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2485 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2486 ) ,
+ .pReset_E_in ( pResetWires[168] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2487 ) ,
+ .pReset_N_out ( pResetWires[167] ) , .pReset_W_out ( pResetWires[165] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , .Reset_S_in ( p3536 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2489 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p2223 ) ,
+ .prog_clk_1_S_in ( p767 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2490 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2491 ) ,
+ .prog_clk_2_N_in ( p2050 ) , .prog_clk_2_E_in ( p49 ) ,
+ .prog_clk_2_S_in ( p1561 ) , .prog_clk_2_W_in ( p364 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2492 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2493 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2494 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2495 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2496 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2497 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2498 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[65] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2499 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2500 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2501 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p2050 ) ,
+ .clk_1_S_in ( p102 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2502 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .clk_2_N_in ( p2050 ) ,
+ .clk_2_E_in ( p738 ) , .clk_2_S_in ( p3516 ) , .clk_2_W_in ( p396 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2504 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2505 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2506 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2507 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2508 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2509 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2510 ) ,
+ .clk_3_N_in ( clk_3_wires[65] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2511 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2512 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2513 ) ,
+ .clk_3_S_out ( clk_3_wires[68] ) ) ;
+sb_1__1_ sb_2__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2514 } ) ,
+ .chany_top_in ( cby_1__1__16_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__25_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__15_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__14_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__25_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__14_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__14_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__14_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p2388 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2515 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2516 ) ,
+ .pReset_E_in ( pResetWires[217] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2517 ) ,
+ .pReset_N_out ( pResetWires[216] ) , .pReset_W_out ( pResetWires[214] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , .Reset_S_in ( p2388 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2519 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1366 ) ,
+ .prog_clk_1_S_in ( p2333 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2520 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2521 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[59] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2522 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2523 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2524 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[7] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2525 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2526 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2527 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2528 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2529 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2530 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[59] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2531 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2532 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2533 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p2210 ) ,
+ .clk_1_S_in ( p30 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2534 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2535 ) ,
+ .clk_2_N_in ( clk_3_wires[59] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2536 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2537 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2538 ) ,
+ .clk_2_W_out ( clk_2_wires[7] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2539 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2540 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2541 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2542 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2543 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2544 ) ,
+ .clk_3_N_in ( clk_3_wires[59] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2545 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2546 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2547 ) ,
+ .clk_3_S_out ( clk_3_wires[64] ) ) ;
+sb_1__1_ sb_2__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2548 } ) ,
+ .chany_top_in ( cby_1__1__17_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__26_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__16_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__15_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__26_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__15_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__15_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__15_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p1822 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2549 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2550 ) ,
+ .pReset_E_in ( pResetWires[266] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2551 ) ,
+ .pReset_N_out ( pResetWires[265] ) , .pReset_W_out ( pResetWires[263] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , .Reset_S_in ( p2125 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2553 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1377 ) ,
+ .prog_clk_1_S_in ( p475 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2554 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2555 ) ,
+ .prog_clk_2_N_in ( p2165 ) , .prog_clk_2_E_in ( p57 ) ,
+ .prog_clk_2_S_in ( p2013 ) , .prog_clk_2_W_in ( p709 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2556 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2557 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2558 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2559 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2560 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2561 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2562 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[55] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2563 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2564 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2565 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1409 ) ,
+ .clk_1_S_in ( p771 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2566 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2567 ) , .clk_2_N_in ( p1409 ) ,
+ .clk_2_E_in ( p632 ) , .clk_2_S_in ( p1913 ) , .clk_2_W_in ( p264 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2568 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2569 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2570 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2571 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2572 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2573 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2574 ) ,
+ .clk_3_N_in ( clk_3_wires[55] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2575 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2576 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2577 ) ,
+ .clk_3_S_out ( clk_3_wires[58] ) ) ;
+sb_1__1_ sb_2__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2578 } ) ,
+ .chany_top_in ( cby_1__1__18_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__27_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__17_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__16_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__27_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__16_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__16_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__16_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p2691 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2579 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2580 ) ,
+ .pReset_E_in ( pResetWires[315] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2581 ) ,
+ .pReset_N_out ( pResetWires[314] ) , .pReset_W_out ( pResetWires[312] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , .Reset_S_in ( p2955 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2583 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1453 ) ,
+ .prog_clk_1_S_in ( p50 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2584 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2585 ) ,
+ .prog_clk_2_N_in ( p2484 ) , .prog_clk_2_E_in ( p237 ) ,
+ .prog_clk_2_S_in ( p1584 ) , .prog_clk_2_W_in ( p586 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2586 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2587 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2588 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2589 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2590 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[51] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2591 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2592 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2593 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2594 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[52] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1453 ) ,
+ .clk_1_S_in ( p747 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2595 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2596 ) , .clk_2_N_in ( p1453 ) ,
+ .clk_2_E_in ( p529 ) , .clk_2_S_in ( p2826 ) , .clk_2_W_in ( p270 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2597 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2598 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2599 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2600 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2601 ) ,
+ .clk_3_E_in ( clk_3_wires[51] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2602 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2603 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2604 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2605 ) ,
+ .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) ) ;
+sb_1__1_ sb_2__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2606 } ) ,
+ .chany_top_in ( cby_1__1__19_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__28_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__18_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__17_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__28_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__17_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__17_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__17_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p2901 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2607 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2608 ) ,
+ .pReset_E_in ( pResetWires[364] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2609 ) ,
+ .pReset_N_out ( pResetWires[363] ) , .pReset_W_out ( pResetWires[361] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , .Reset_S_in ( p3352 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2611 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1390 ) ,
+ .prog_clk_1_S_in ( p696 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2612 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2613 ) ,
+ .prog_clk_2_N_in ( p2431 ) , .prog_clk_2_E_in ( p731 ) ,
+ .prog_clk_2_S_in ( p359 ) , .prog_clk_2_W_in ( p119 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2614 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2615 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2616 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2617 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2618 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2619 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[53] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2620 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2621 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2622 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[56] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_1_N_in ( p1211 ) ,
+ .clk_1_S_in ( p204 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2624 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2625 ) , .clk_2_N_in ( p1211 ) ,
+ .clk_2_E_in ( p380 ) , .clk_2_S_in ( p3296 ) , .clk_2_W_in ( p566 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2626 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2627 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2628 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2629 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2630 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2631 ) ,
+ .clk_3_S_in ( clk_3_wires[53] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2632 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2633 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2634 ) ,
+ .clk_3_N_out ( clk_3_wires[56] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+sb_1__1_ sb_2__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2636 } ) ,
+ .chany_top_in ( cby_1__1__20_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__29_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__19_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__18_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__29_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__18_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__18_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__18_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p2174 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2637 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2638 ) ,
+ .pReset_E_in ( pResetWires[413] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2639 ) ,
+ .pReset_N_out ( pResetWires[412] ) , .pReset_W_out ( pResetWires[410] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , .Reset_S_in ( p2174 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2641 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1755 ) ,
+ .prog_clk_1_S_in ( p1909 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2642 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2643 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2644 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2645 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[57] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2646 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[14] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2647 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2648 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2649 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2650 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2651 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[57] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2652 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2653 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2654 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[62] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2655 ) , .clk_1_N_in ( p2088 ) ,
+ .clk_1_S_in ( p705 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2656 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2657 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2658 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2659 ) ,
+ .clk_2_S_in ( clk_3_wires[57] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2660 ) ,
+ .clk_2_W_out ( clk_2_wires[14] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2661 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2662 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2663 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2664 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2665 ) ,
+ .clk_3_S_in ( clk_3_wires[57] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2666 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2667 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2668 ) ,
+ .clk_3_N_out ( clk_3_wires[62] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+sb_1__1_ sb_2__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2670 } ) ,
+ .chany_top_in ( cby_1__1__21_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__30_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__20_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__19_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__30_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__19_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__19_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__19_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p1279 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2671 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2672 ) ,
+ .pReset_E_in ( pResetWires[462] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2673 ) ,
+ .pReset_N_out ( pResetWires[461] ) , .pReset_W_out ( pResetWires[459] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , .Reset_S_in ( p2245 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2675 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1341 ) ,
+ .prog_clk_1_S_in ( p43 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2676 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2677 ) ,
+ .prog_clk_2_N_in ( p2236 ) , .prog_clk_2_E_in ( p124 ) ,
+ .prog_clk_2_S_in ( p464 ) , .prog_clk_2_W_in ( p184 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2678 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2679 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2680 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2681 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2682 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2683 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[63] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2684 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2685 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2686 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[66] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_1_N_in ( p1341 ) ,
+ .clk_1_S_in ( p918 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2688 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_2_N_in ( p1341 ) ,
+ .clk_2_E_in ( p563 ) , .clk_2_S_in ( p1950 ) , .clk_2_W_in ( p539 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2690 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2691 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2692 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2693 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2694 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2695 ) ,
+ .clk_3_S_in ( clk_3_wires[63] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2696 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2697 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2698 ) ,
+ .clk_3_N_out ( clk_3_wires[66] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+sb_1__1_ sb_2__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2700 } ) ,
+ .chany_top_in ( cby_1__1__22_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__31_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__21_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__20_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__31_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__20_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__20_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__20_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2480 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2701 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2702 ) ,
+ .pReset_E_in ( pResetWires[511] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2703 ) ,
+ .pReset_N_out ( pResetWires[510] ) , .pReset_W_out ( pResetWires[508] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , .Reset_S_in ( p2480 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2705 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p1825 ) ,
+ .prog_clk_1_S_in ( p665 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2706 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2707 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2708 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2709 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[67] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2710 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[21] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2711 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2712 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2713 ) ,
+ .prog_clk_3_W_in ( p1695 ) , .prog_clk_3_E_in ( p246 ) ,
+ .prog_clk_3_S_in ( p1498 ) , .prog_clk_3_N_in ( p502 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2714 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2715 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2716 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , .clk_1_N_in ( p1775 ) ,
+ .clk_1_S_in ( p200 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2718 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2719 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2720 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2721 ) ,
+ .clk_2_S_in ( clk_3_wires[67] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2722 ) ,
+ .clk_2_W_out ( clk_2_wires[21] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2723 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2724 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , .clk_3_W_in ( p1695 ) ,
+ .clk_3_E_in ( p727 ) , .clk_3_S_in ( p2284 ) , .clk_3_N_in ( p1548 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2726 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2727 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2728 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+sb_1__1_ sb_2__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2730 } ) ,
+ .chany_top_in ( cby_1__1__23_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__32_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__22_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__21_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__32_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__21_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__21_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__21_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p1809 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2731 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2732 ) ,
+ .pReset_E_in ( pResetWires[560] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2733 ) ,
+ .pReset_N_out ( pResetWires[559] ) , .pReset_W_out ( pResetWires[557] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , .Reset_S_in ( p2535 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2735 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p2244 ) ,
+ .prog_clk_1_S_in ( p903 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2736 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2737 ) ,
+ .prog_clk_2_N_in ( p3454 ) , .prog_clk_2_E_in ( p576 ) ,
+ .prog_clk_2_S_in ( p1062 ) , .prog_clk_2_W_in ( p3644 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2738 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2739 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2740 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2741 ) ,
+ .prog_clk_3_W_in ( p3648 ) , .prog_clk_3_E_in ( p934 ) ,
+ .prog_clk_3_S_in ( p341 ) , .prog_clk_3_N_in ( p3406 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2742 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2743 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2744 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_1_N_in ( p2953 ) ,
+ .clk_1_S_in ( p556 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2746 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .clk_2_N_in ( p2928 ) ,
+ .clk_2_E_in ( p660 ) , .clk_2_S_in ( p2315 ) , .clk_2_W_in ( p2866 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2748 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2749 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2750 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2751 ) , .clk_3_W_in ( p2948 ) ,
+ .clk_3_E_in ( p198 ) , .clk_3_S_in ( p227 ) , .clk_3_N_in ( p2861 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2752 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2753 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2754 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+sb_1__1_ sb_3__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2756 } ) ,
+ .chany_top_in ( cby_1__1__25_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__33_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__24_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__22_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__33_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__22_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__22_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__22_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2707 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2757 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2758 ) ,
+ .pReset_E_in ( pResetWires[74] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2759 ) ,
+ .pReset_N_out ( pResetWires[73] ) , .pReset_W_out ( pResetWires[71] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2760 ) , .Reset_S_in ( p3502 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2761 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[106] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[30] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2762 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[43] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p3274 ) ,
+ .prog_clk_2_E_in ( p1063 ) , .prog_clk_2_S_in ( p1021 ) ,
+ .prog_clk_2_W_in ( p2326 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2763 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2764 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2765 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2766 ) ,
+ .prog_clk_3_W_in ( p2504 ) , .prog_clk_3_E_in ( p549 ) ,
+ .prog_clk_3_S_in ( p526 ) , .prog_clk_3_N_in ( p3209 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2767 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2768 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2769 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2770 ) ,
+ .clk_1_N_in ( clk_2_wires[30] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2771 ) ,
+ .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) ,
+ .clk_2_N_in ( p3500 ) , .clk_2_E_in ( p138 ) , .clk_2_S_in ( p3458 ) ,
+ .clk_2_W_in ( p1499 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2772 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2773 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2774 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2775 ) , .clk_3_W_in ( p1779 ) ,
+ .clk_3_E_in ( p1010 ) , .clk_3_S_in ( p69 ) , .clk_3_N_in ( p3475 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2776 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2777 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2778 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+sb_1__1_ sb_3__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2780 } ) ,
+ .chany_top_in ( cby_1__1__26_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__34_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__25_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__23_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__34_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__23_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__23_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__23_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2419 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2781 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2782 ) ,
+ .pReset_E_in ( pResetWires[123] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2783 ) ,
+ .pReset_N_out ( pResetWires[122] ) , .pReset_W_out ( pResetWires[120] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , .Reset_S_in ( p2478 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2785 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1699 ) ,
+ .prog_clk_1_S_in ( p861 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2786 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2787 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2788 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[28] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2789 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2790 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2791 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[29] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2792 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2793 ) ,
+ .prog_clk_3_W_in ( p1076 ) , .prog_clk_3_E_in ( p306 ) ,
+ .prog_clk_3_S_in ( p744 ) , .prog_clk_3_N_in ( p692 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2794 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2795 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2796 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2797 ) , .clk_1_N_in ( p2708 ) ,
+ .clk_1_S_in ( p348 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2799 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2800 ) ,
+ .clk_2_E_in ( clk_2_wires[28] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2801 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2802 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2803 ) ,
+ .clk_2_S_out ( clk_2_wires[29] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2804 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2805 ) , .clk_3_W_in ( p1076 ) ,
+ .clk_3_E_in ( p792 ) , .clk_3_S_in ( p2286 ) , .clk_3_N_in ( p2639 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2806 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2807 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2808 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+sb_1__1_ sb_3__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2810 } ) ,
+ .chany_top_in ( cby_1__1__27_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__35_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__26_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__24_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__35_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__24_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__24_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__24_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p2149 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2811 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2812 ) ,
+ .pReset_E_in ( pResetWires[172] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2813 ) ,
+ .pReset_N_out ( pResetWires[171] ) , .pReset_W_out ( pResetWires[169] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , .Reset_S_in ( p3263 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2815 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[112] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[41] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2816 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[50] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p2934 ) ,
+ .prog_clk_2_E_in ( p32 ) , .prog_clk_2_S_in ( p1081 ) ,
+ .prog_clk_2_W_in ( p3614 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2817 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2818 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2819 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2820 ) ,
+ .prog_clk_3_W_in ( p3623 ) , .prog_clk_3_E_in ( p1168 ) ,
+ .prog_clk_3_S_in ( p271 ) , .prog_clk_3_N_in ( p2839 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2821 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2822 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2823 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2824 ) ,
+ .clk_1_N_in ( clk_2_wires[41] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2825 ) ,
+ .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) ,
+ .clk_2_N_in ( p3657 ) , .clk_2_E_in ( p694 ) , .clk_2_S_in ( p3200 ) ,
+ .clk_2_W_in ( p2606 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2826 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2827 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2828 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2829 ) , .clk_3_W_in ( p2741 ) ,
+ .clk_3_E_in ( p713 ) , .clk_3_S_in ( p506 ) , .clk_3_N_in ( p3652 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2832 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+sb_1__1_ sb_3__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2834 } ) ,
+ .chany_top_in ( cby_1__1__28_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__36_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__27_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__25_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__36_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__25_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__25_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__25_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p1462 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2835 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2836 ) ,
+ .pReset_E_in ( pResetWires[221] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2837 ) ,
+ .pReset_N_out ( pResetWires[220] ) , .pReset_W_out ( pResetWires[218] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , .Reset_S_in ( p1462 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2839 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p2418 ) ,
+ .prog_clk_1_S_in ( p404 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2840 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2841 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2842 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[37] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2843 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2844 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2845 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[40] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[38] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2846 ) ,
+ .prog_clk_3_W_in ( p1864 ) , .prog_clk_3_E_in ( p1947 ) ,
+ .prog_clk_3_S_in ( p171 ) , .prog_clk_3_N_in ( p68 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2847 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2848 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2849 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2850 ) , .clk_1_N_in ( p2898 ) ,
+ .clk_1_S_in ( p973 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2851 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2852 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2853 ) ,
+ .clk_2_E_in ( clk_2_wires[37] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2854 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2855 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2856 ) ,
+ .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2857 ) , .clk_3_W_in ( p2969 ) ,
+ .clk_3_E_in ( p1925 ) , .clk_3_S_in ( p531 ) , .clk_3_N_in ( p2809 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2858 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2859 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2860 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+sb_1__1_ sb_3__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2862 } ) ,
+ .chany_top_in ( cby_1__1__29_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__37_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__28_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__26_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__37_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__26_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__26_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__26_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p2084 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2863 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2864 ) ,
+ .pReset_E_in ( pResetWires[270] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2865 ) ,
+ .pReset_N_out ( pResetWires[269] ) , .pReset_W_out ( pResetWires[267] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2866 ) , .Reset_S_in ( p2719 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2867 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[118] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2868 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[39] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[57] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p2965 ) ,
+ .prog_clk_2_E_in ( p386 ) , .prog_clk_2_S_in ( p923 ) ,
+ .prog_clk_2_W_in ( p3651 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2869 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2870 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2871 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2872 ) ,
+ .prog_clk_3_W_in ( p3658 ) , .prog_clk_3_E_in ( p718 ) ,
+ .prog_clk_3_S_in ( p310 ) , .prog_clk_3_N_in ( p2800 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2873 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2874 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2875 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2876 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2877 ) ,
+ .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) ,
+ .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p3257 ) ,
+ .clk_2_E_in ( p969 ) , .clk_2_S_in ( p2618 ) , .clk_2_W_in ( p3044 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2878 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2879 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2880 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , .clk_3_W_in ( p3153 ) ,
+ .clk_3_E_in ( p800 ) , .clk_3_S_in ( p1155 ) , .clk_3_N_in ( p3186 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2882 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2883 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2884 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+sb_1__1_ sb_3__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2886 } ) ,
+ .chany_top_in ( cby_1__1__30_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__38_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__29_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__27_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__38_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__27_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__27_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__27_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p2089 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2887 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2888 ) ,
+ .pReset_E_in ( pResetWires[319] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2889 ) ,
+ .pReset_N_out ( pResetWires[318] ) , .pReset_W_out ( pResetWires[316] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .Reset_S_in ( p3581 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2891 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1388 ) ,
+ .prog_clk_1_S_in ( p357 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2892 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2893 ) ,
+ .prog_clk_2_N_in ( p2122 ) , .prog_clk_2_E_in ( p478 ) ,
+ .prog_clk_2_S_in ( p134 ) , .prog_clk_2_W_in ( p573 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2894 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2895 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2896 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2897 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2898 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[47] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2899 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2900 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2901 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[50] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2902 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_1_N_in ( p1423 ) ,
+ .clk_1_S_in ( p916 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2904 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2905 ) , .clk_2_N_in ( p1423 ) ,
+ .clk_2_E_in ( p543 ) , .clk_2_S_in ( p3560 ) , .clk_2_W_in ( p95 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2906 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2907 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2908 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2909 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2910 ) ,
+ .clk_3_E_in ( clk_3_wires[47] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2911 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2912 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2913 ) ,
+ .clk_3_W_out ( clk_3_wires[50] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2914 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+sb_1__1_ sb_3__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2916 } ) ,
+ .chany_top_in ( cby_1__1__31_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__39_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__30_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__28_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__39_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__28_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__28_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__28_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p2547 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2917 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2918 ) ,
+ .pReset_E_in ( pResetWires[368] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2919 ) ,
+ .pReset_N_out ( pResetWires[367] ) , .pReset_W_out ( pResetWires[365] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , .Reset_S_in ( p2547 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2921 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[124] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[54] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2922 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[64] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p3671 ) ,
+ .prog_clk_2_E_in ( p605 ) , .prog_clk_2_S_in ( p1083 ) ,
+ .prog_clk_2_W_in ( p1496 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2923 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2924 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2925 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2926 ) ,
+ .prog_clk_3_W_in ( p1789 ) , .prog_clk_3_E_in ( p998 ) ,
+ .prog_clk_3_S_in ( p428 ) , .prog_clk_3_N_in ( p3669 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2927 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2928 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2929 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2930 ) ,
+ .clk_1_N_in ( clk_2_wires[54] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2931 ) ,
+ .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) ,
+ .clk_2_N_in ( p3487 ) , .clk_2_E_in ( p410 ) , .clk_2_S_in ( p2343 ) ,
+ .clk_2_W_in ( p3561 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2932 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2933 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2934 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , .clk_3_W_in ( p3584 ) ,
+ .clk_3_E_in ( p919 ) , .clk_3_S_in ( p256 ) , .clk_3_N_in ( p3465 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2936 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2937 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2938 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+sb_1__1_ sb_3__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2940 } ) ,
+ .chany_top_in ( cby_1__1__32_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__40_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__31_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__29_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__40_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__29_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__29_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__29_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p2150 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2941 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2942 ) ,
+ .pReset_E_in ( pResetWires[417] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2943 ) ,
+ .pReset_N_out ( pResetWires[416] ) , .pReset_W_out ( pResetWires[414] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , .Reset_S_in ( p2150 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2945 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p2457 ) ,
+ .prog_clk_1_S_in ( p1048 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2946 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2947 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2948 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[50] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2949 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2950 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2951 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[53] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[51] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2952 ) ,
+ .prog_clk_3_W_in ( p1297 ) , .prog_clk_3_E_in ( p1563 ) ,
+ .prog_clk_3_S_in ( p205 ) , .prog_clk_3_N_in ( p1481 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2953 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2954 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2955 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2956 ) , .clk_1_N_in ( p2183 ) ,
+ .clk_1_S_in ( p321 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2957 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2958 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2959 ) ,
+ .clk_2_E_in ( clk_2_wires[50] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2960 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2961 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2962 ) ,
+ .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2963 ) , .clk_3_W_in ( p1297 ) ,
+ .clk_3_E_in ( p1523 ) , .clk_3_S_in ( p1932 ) , .clk_3_N_in ( p2265 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2964 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2965 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2966 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+sb_1__1_ sb_3__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2968 } ) ,
+ .chany_top_in ( cby_1__1__33_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__41_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__32_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__30_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__41_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__30_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__30_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__30_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p2406 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2969 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2970 ) ,
+ .pReset_E_in ( pResetWires[466] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2971 ) ,
+ .pReset_N_out ( pResetWires[465] ) , .pReset_W_out ( pResetWires[463] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , .Reset_S_in ( p3603 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2973 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[130] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2974 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[52] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[71] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3427 ) ,
+ .prog_clk_2_E_in ( p31 ) , .prog_clk_2_S_in ( p739 ) ,
+ .prog_clk_2_W_in ( p3418 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2975 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2976 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2977 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2978 ) ,
+ .prog_clk_3_W_in ( p3443 ) , .prog_clk_3_E_in ( p789 ) ,
+ .prog_clk_3_S_in ( p101 ) , .prog_clk_3_N_in ( p3402 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2979 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2980 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2981 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2982 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2983 ) ,
+ .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) ,
+ .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3364 ) ,
+ .clk_2_E_in ( p825 ) , .clk_2_S_in ( p3592 ) , .clk_2_W_in ( p3059 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2984 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2985 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2986 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , .clk_3_W_in ( p3108 ) ,
+ .clk_3_E_in ( p753 ) , .clk_3_S_in ( p652 ) , .clk_3_N_in ( p3299 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2988 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2989 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2990 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+sb_1__1_ sb_3__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_2992 } ) ,
+ .chany_top_in ( cby_1__1__34_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__42_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__33_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__31_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__42_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__31_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__31_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__31_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p1725 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2993 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_2994 ) ,
+ .pReset_E_in ( pResetWires[515] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_2995 ) ,
+ .pReset_N_out ( pResetWires[514] ) , .pReset_W_out ( pResetWires[512] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , .Reset_S_in ( p1725 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_2997 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p1783 ) ,
+ .prog_clk_1_S_in ( p127 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2998 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2999 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3000 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[63] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3001 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3002 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3003 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3004 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[64] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3005 ) ,
+ .prog_clk_3_W_in ( p1173 ) , .prog_clk_3_E_in ( p109 ) ,
+ .prog_clk_3_S_in ( p20 ) , .prog_clk_3_N_in ( p1573 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3006 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3007 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3008 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_N_in ( p2972 ) ,
+ .clk_1_S_in ( p1085 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3010 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3011 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3012 ) ,
+ .clk_2_E_in ( clk_2_wires[63] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3013 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3014 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3015 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3016 ) ,
+ .clk_2_N_out ( clk_2_wires[64] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3017 ) , .clk_3_W_in ( p1173 ) ,
+ .clk_3_E_in ( p407 ) , .clk_3_S_in ( p1558 ) , .clk_3_N_in ( p2830 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3018 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3019 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3020 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+sb_1__1_ sb_3__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3022 } ) ,
+ .chany_top_in ( cby_1__1__35_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__43_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__34_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__32_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__43_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__32_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__32_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__32_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2759 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3023 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3024 ) ,
+ .pReset_E_in ( pResetWires[564] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3025 ) ,
+ .pReset_N_out ( pResetWires[563] ) , .pReset_W_out ( pResetWires[561] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , .Reset_S_in ( p2962 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3027 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[136] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3028 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[65] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[78] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p3231 ) ,
+ .prog_clk_2_E_in ( p1070 ) , .prog_clk_2_S_in ( p290 ) ,
+ .prog_clk_2_W_in ( p3392 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3029 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3030 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3031 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3032 ) ,
+ .prog_clk_3_W_in ( p3449 ) , .prog_clk_3_E_in ( p645 ) ,
+ .prog_clk_3_S_in ( p1023 ) , .prog_clk_3_N_in ( p3163 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3033 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3034 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3035 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3036 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3037 ) ,
+ .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) ,
+ .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p3260 ) ,
+ .clk_2_E_in ( p849 ) , .clk_2_S_in ( p2804 ) , .clk_2_W_in ( p2831 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3038 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3039 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3040 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3041 ) , .clk_3_W_in ( p2902 ) ,
+ .clk_3_E_in ( p782 ) , .clk_3_S_in ( p1162 ) , .clk_3_N_in ( p3205 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3042 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3043 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3044 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+sb_1__1_ sb_4__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3046 } ) ,
+ .chany_top_in ( cby_1__1__37_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__44_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__36_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__33_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__44_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__33_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__33_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__33_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2684 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3047 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3048 ) ,
+ .pReset_E_in ( pResetWires[78] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3049 ) ,
+ .pReset_N_out ( pResetWires[77] ) , .pReset_W_out ( pResetWires[75] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , .Reset_S_in ( p2949 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3051 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p1221 ) ,
+ .prog_clk_1_S_in ( p366 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3052 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3053 ) ,
+ .prog_clk_2_N_in ( p3605 ) , .prog_clk_2_E_in ( p848 ) ,
+ .prog_clk_2_S_in ( p182 ) , .prog_clk_2_W_in ( p1944 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3054 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3055 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3056 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3057 ) ,
+ .prog_clk_3_W_in ( p2109 ) , .prog_clk_3_E_in ( p4 ) ,
+ .prog_clk_3_S_in ( p1067 ) , .prog_clk_3_N_in ( p3589 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3058 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3059 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3060 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_1_N_in ( p2243 ) ,
+ .clk_1_S_in ( p824 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3062 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , .clk_2_N_in ( p2771 ) ,
+ .clk_2_E_in ( p837 ) , .clk_2_S_in ( p2848 ) , .clk_2_W_in ( p1954 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3064 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3065 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3066 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , .clk_3_W_in ( p2233 ) ,
+ .clk_3_E_in ( p836 ) , .clk_3_S_in ( p1071 ) , .clk_3_N_in ( p2605 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3068 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3069 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3070 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+sb_1__1_ sb_4__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3072 } ) ,
+ .chany_top_in ( cby_1__1__38_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__45_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__37_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__34_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__45_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__34_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__34_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__34_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p2472 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3073 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3074 ) ,
+ .pReset_E_in ( pResetWires[127] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3075 ) ,
+ .pReset_N_out ( pResetWires[126] ) , .pReset_W_out ( pResetWires[124] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , .Reset_S_in ( p2472 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3077 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p2459 ) ,
+ .prog_clk_1_S_in ( p981 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3078 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3079 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[25] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3080 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3081 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3082 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[27] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3083 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3084 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p1319 ) ,
+ .prog_clk_3_E_in ( p748 ) , .prog_clk_3_S_in ( p167 ) ,
+ .prog_clk_3_N_in ( p26 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3085 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3086 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3087 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , .clk_1_N_in ( p2140 ) ,
+ .clk_1_S_in ( p129 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3089 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3090 ) ,
+ .clk_2_N_in ( clk_3_wires[25] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3091 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3092 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3093 ) ,
+ .clk_2_W_out ( clk_2_wires[27] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3094 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3095 ) ,
+ .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p1319 ) ,
+ .clk_3_E_in ( p193 ) , .clk_3_S_in ( p2338 ) , .clk_3_N_in ( p2259 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3096 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3097 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3098 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+sb_1__1_ sb_4__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3100 } ) ,
+ .chany_top_in ( cby_1__1__39_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__46_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__38_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__35_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__46_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__35_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__35_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__35_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p1853 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3101 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3102 ) ,
+ .pReset_E_in ( pResetWires[176] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3103 ) ,
+ .pReset_N_out ( pResetWires[175] ) , .pReset_W_out ( pResetWires[173] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , .Reset_S_in ( p1853 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3105 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1437 ) ,
+ .prog_clk_1_S_in ( p734 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3106 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3107 ) ,
+ .prog_clk_2_N_in ( p1709 ) , .prog_clk_2_E_in ( p469 ) ,
+ .prog_clk_2_S_in ( p80 ) , .prog_clk_2_W_in ( p288 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3108 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3109 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3110 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3111 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3112 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3113 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3114 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[21] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3115 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3116 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3117 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1709 ) ,
+ .clk_1_S_in ( p269 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3118 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3119 ) , .clk_2_N_in ( p1709 ) ,
+ .clk_2_E_in ( p365 ) , .clk_2_S_in ( p1544 ) , .clk_2_W_in ( p759 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3120 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3121 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3122 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3123 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3124 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3125 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3126 ) ,
+ .clk_3_N_in ( clk_3_wires[21] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3127 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3128 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3129 ) ,
+ .clk_3_S_out ( clk_3_wires[24] ) ) ;
+sb_1__1_ sb_4__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3130 } ) ,
+ .chany_top_in ( cby_1__1__40_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__47_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__39_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__36_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__47_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__36_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__36_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__36_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p1694 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3131 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3132 ) ,
+ .pReset_E_in ( pResetWires[225] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3133 ) ,
+ .pReset_N_out ( pResetWires[224] ) , .pReset_W_out ( pResetWires[222] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , .Reset_S_in ( p1694 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3135 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p851 ) ,
+ .prog_clk_1_S_in ( p1522 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3136 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3137 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[15] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3138 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3139 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3140 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[36] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3141 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3142 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[34] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3143 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3144 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3145 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[15] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3146 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3147 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3148 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p2912 ) ,
+ .clk_1_S_in ( p351 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3149 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3150 ) ,
+ .clk_2_N_in ( clk_3_wires[15] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3151 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3152 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3153 ) ,
+ .clk_2_W_out ( clk_2_wires[36] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3154 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3155 ) ,
+ .clk_2_E_out ( clk_2_wires[34] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3156 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3157 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3158 ) ,
+ .clk_3_N_in ( clk_3_wires[15] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3159 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3160 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3161 ) ,
+ .clk_3_S_out ( clk_3_wires[20] ) ) ;
+sb_1__1_ sb_4__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3162 } ) ,
+ .chany_top_in ( cby_1__1__41_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__48_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__40_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__37_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__48_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__37_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__37_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__37_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p2177 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3163 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3164 ) ,
+ .pReset_E_in ( pResetWires[274] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3165 ) ,
+ .pReset_N_out ( pResetWires[273] ) , .pReset_W_out ( pResetWires[271] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .Reset_S_in ( p2783 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3167 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1733 ) ,
+ .prog_clk_1_S_in ( p427 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3168 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3169 ) ,
+ .prog_clk_2_N_in ( p2766 ) , .prog_clk_2_E_in ( p154 ) ,
+ .prog_clk_2_S_in ( p1569 ) , .prog_clk_2_W_in ( p806 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3170 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3171 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3172 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3173 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3174 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3175 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3176 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[11] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3177 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3178 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3179 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p2102 ) ,
+ .clk_1_S_in ( p617 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3180 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_2_N_in ( p2102 ) ,
+ .clk_2_E_in ( p922 ) , .clk_2_S_in ( p2619 ) , .clk_2_W_in ( p689 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3182 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3183 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3184 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3185 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3186 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3187 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3188 ) ,
+ .clk_3_N_in ( clk_3_wires[11] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3189 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3190 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3191 ) ,
+ .clk_3_S_out ( clk_3_wires[14] ) ) ;
+sb_1__1_ sb_4__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3192 } ) ,
+ .chany_top_in ( cby_1__1__42_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__49_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__41_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__38_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__49_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__38_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__38_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__38_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p2971 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3193 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3194 ) ,
+ .pReset_E_in ( pResetWires[323] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3195 ) ,
+ .pReset_N_out ( pResetWires[322] ) , .pReset_W_out ( pResetWires[320] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , .Reset_S_in ( p2900 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3197 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1394 ) ,
+ .prog_clk_1_S_in ( p282 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3198 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3199 ) ,
+ .prog_clk_2_N_in ( p1867 ) , .prog_clk_2_E_in ( p7 ) ,
+ .prog_clk_2_S_in ( p97 ) , .prog_clk_2_W_in ( p752 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3200 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3201 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3202 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3203 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3204 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[7] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3205 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3206 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3207 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[46] ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[8] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1867 ) ,
+ .clk_1_S_in ( p486 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3208 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3209 ) , .clk_2_N_in ( p1879 ) ,
+ .clk_2_E_in ( p455 ) , .clk_2_S_in ( p2852 ) , .clk_2_W_in ( p99 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3210 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3211 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3212 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3213 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3214 ) ,
+ .clk_3_E_in ( clk_3_wires[7] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3215 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3216 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3217 ) ,
+ .clk_3_W_out ( clk_3_wires[46] ) , .clk_3_N_out ( clk_3_wires[8] ) ,
+ .clk_3_S_out ( clk_3_wires[10] ) ) ;
+sb_1__1_ sb_4__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3218 } ) ,
+ .chany_top_in ( cby_1__1__43_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__50_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__42_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__39_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__50_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__39_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__39_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__39_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2706 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3219 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3220 ) ,
+ .pReset_E_in ( pResetWires[372] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3221 ) ,
+ .pReset_N_out ( pResetWires[371] ) , .pReset_W_out ( pResetWires[369] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , .Reset_S_in ( p3340 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3223 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1380 ) ,
+ .prog_clk_1_S_in ( p871 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3224 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3225 ) ,
+ .prog_clk_2_N_in ( p2425 ) , .prog_clk_2_E_in ( p244 ) ,
+ .prog_clk_2_S_in ( p1585 ) , .prog_clk_2_W_in ( p133 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3226 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3227 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3228 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3229 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3230 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3231 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[9] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3232 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3233 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3234 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[12] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_1_N_in ( p1452 ) ,
+ .clk_1_S_in ( p183 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3236 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , .clk_2_N_in ( p1452 ) ,
+ .clk_2_E_in ( p743 ) , .clk_2_S_in ( p3300 ) , .clk_2_W_in ( p445 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3238 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3239 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3240 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3241 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3242 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3243 ) ,
+ .clk_3_S_in ( clk_3_wires[9] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3244 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3245 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3246 ) ,
+ .clk_3_N_out ( clk_3_wires[12] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+sb_1__1_ sb_4__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3248 } ) ,
+ .chany_top_in ( cby_1__1__44_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__51_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__43_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__40_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__51_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__40_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__40_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__40_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1797 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3249 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3250 ) ,
+ .pReset_E_in ( pResetWires[421] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3251 ) ,
+ .pReset_N_out ( pResetWires[420] ) , .pReset_W_out ( pResetWires[418] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , .Reset_S_in ( p1797 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3253 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1424 ) ,
+ .prog_clk_1_S_in ( p1540 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3254 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3255 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3256 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3257 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[13] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3258 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[49] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3259 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3260 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[47] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3261 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3262 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[13] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3263 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3264 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3265 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[18] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3266 ) , .clk_1_N_in ( p1672 ) ,
+ .clk_1_S_in ( p1089 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3267 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3268 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3269 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3270 ) ,
+ .clk_2_S_in ( clk_3_wires[13] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3271 ) ,
+ .clk_2_W_out ( clk_2_wires[49] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3272 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3273 ) ,
+ .clk_2_E_out ( clk_2_wires[47] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3274 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3275 ) ,
+ .clk_3_S_in ( clk_3_wires[13] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3276 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3277 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3278 ) ,
+ .clk_3_N_out ( clk_3_wires[18] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+sb_1__1_ sb_4__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3280 } ) ,
+ .chany_top_in ( cby_1__1__45_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__52_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__44_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__41_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__52_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__41_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__41_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__41_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2396 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3281 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3282 ) ,
+ .pReset_E_in ( pResetWires[470] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3283 ) ,
+ .pReset_N_out ( pResetWires[469] ) , .pReset_W_out ( pResetWires[467] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , .Reset_S_in ( p2396 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3285 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1337 ) ,
+ .prog_clk_1_S_in ( p228 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3286 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3287 ) ,
+ .prog_clk_2_N_in ( p1337 ) , .prog_clk_2_E_in ( p984 ) ,
+ .prog_clk_2_S_in ( p1916 ) , .prog_clk_2_W_in ( p299 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3288 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3289 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3290 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3291 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3292 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3293 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[19] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3294 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3295 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3296 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[22] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_1_N_in ( p1337 ) ,
+ .clk_1_S_in ( p943 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3298 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3299 ) , .clk_2_N_in ( p1337 ) ,
+ .clk_2_E_in ( p188 ) , .clk_2_S_in ( p2277 ) , .clk_2_W_in ( p479 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3300 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3301 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3302 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3303 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3304 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3305 ) ,
+ .clk_3_S_in ( clk_3_wires[19] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3306 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3307 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3308 ) ,
+ .clk_3_N_out ( clk_3_wires[22] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+sb_1__1_ sb_4__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3310 } ) ,
+ .chany_top_in ( cby_1__1__46_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__53_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__45_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__42_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__53_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__42_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__42_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__42_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2896 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3311 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3312 ) ,
+ .pReset_E_in ( pResetWires[519] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3313 ) ,
+ .pReset_N_out ( pResetWires[518] ) , .pReset_W_out ( pResetWires[516] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , .Reset_S_in ( p2896 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3315 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p2068 ) ,
+ .prog_clk_1_S_in ( p911 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3316 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3317 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3318 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3319 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[23] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3320 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[62] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3321 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3322 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p1718 ) ,
+ .prog_clk_3_E_in ( p1596 ) , .prog_clk_3_S_in ( p414 ) ,
+ .prog_clk_3_N_in ( p280 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3323 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3324 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3325 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3326 ) , .clk_1_N_in ( p2240 ) ,
+ .clk_1_S_in ( p89 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3328 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3329 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3330 ) ,
+ .clk_2_S_in ( clk_3_wires[23] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3331 ) ,
+ .clk_2_W_out ( clk_2_wires[62] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3332 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3333 ) ,
+ .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p1718 ) ,
+ .clk_3_E_in ( p1479 ) , .clk_3_S_in ( p2822 ) , .clk_3_N_in ( p1993 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3334 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3335 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3336 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+sb_1__1_ sb_4__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3338 } ) ,
+ .chany_top_in ( cby_1__1__47_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__54_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__46_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__43_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__54_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__43_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__43_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__43_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p2471 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3339 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3340 ) ,
+ .pReset_E_in ( pResetWires[568] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3341 ) ,
+ .pReset_N_out ( pResetWires[567] ) , .pReset_W_out ( pResetWires[565] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , .Reset_S_in ( p3668 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3343 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p1751 ) ,
+ .prog_clk_1_S_in ( p1025 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3344 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3345 ) ,
+ .prog_clk_2_N_in ( p3622 ) , .prog_clk_2_E_in ( p1163 ) ,
+ .prog_clk_2_S_in ( p1109 ) , .prog_clk_2_W_in ( p2625 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3346 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3347 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3348 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3349 ) ,
+ .prog_clk_3_W_in ( p2745 ) , .prog_clk_3_E_in ( p820 ) ,
+ .prog_clk_3_S_in ( p103 ) , .prog_clk_3_N_in ( p3616 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3350 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3351 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3352 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_1_N_in ( p2168 ) ,
+ .clk_1_S_in ( p369 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3354 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_2_N_in ( p3599 ) ,
+ .clk_2_E_in ( p92 ) , .clk_2_S_in ( p3665 ) , .clk_2_W_in ( p3009 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3356 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3357 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3358 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3359 ) , .clk_3_W_in ( p3112 ) ,
+ .clk_3_E_in ( p592 ) , .clk_3_S_in ( p548 ) , .clk_3_N_in ( p3596 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3360 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3361 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3362 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+sb_1__1_ sb_5__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3364 } ) ,
+ .chany_top_in ( cby_1__1__49_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__55_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__48_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__44_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__55_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__44_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__44_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__44_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p1887 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3365 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3366 ) ,
+ .pReset_E_in ( pResetWires[82] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3367 ) ,
+ .pReset_N_out ( pResetWires[81] ) , .pReset_W_out ( pResetWires[79] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , .Reset_S_in ( p3250 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3369 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[182] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[32] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3370 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[85] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p2117 ) ,
+ .prog_clk_2_E_in ( p411 ) , .prog_clk_2_S_in ( p163 ) ,
+ .prog_clk_2_W_in ( p3594 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3371 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3372 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3373 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3374 ) ,
+ .prog_clk_3_W_in ( p3604 ) , .prog_clk_3_E_in ( p909 ) ,
+ .prog_clk_3_S_in ( p279 ) , .prog_clk_3_N_in ( p1979 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3375 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3376 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3377 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3378 ) ,
+ .clk_1_N_in ( clk_2_wires[32] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3379 ) ,
+ .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) ,
+ .clk_2_N_in ( p3261 ) , .clk_2_E_in ( p305 ) , .clk_2_S_in ( p3193 ) ,
+ .clk_2_W_in ( p2553 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3380 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3381 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3382 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3383 ) , .clk_3_W_in ( p2794 ) ,
+ .clk_3_E_in ( p558 ) , .clk_3_S_in ( p446 ) , .clk_3_N_in ( p3192 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3384 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3385 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3386 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+sb_1__1_ sb_5__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3388 } ) ,
+ .chany_top_in ( cby_1__1__50_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__56_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__49_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__45_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__56_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__45_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__45_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__45_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p1936 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3389 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3390 ) ,
+ .pReset_E_in ( pResetWires[131] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3391 ) ,
+ .pReset_N_out ( pResetWires[130] ) , .pReset_W_out ( pResetWires[128] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , .Reset_S_in ( p1936 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3393 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p1830 ) ,
+ .prog_clk_1_S_in ( p220 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3394 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3395 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3396 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3397 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3398 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[26] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3399 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[31] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3400 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3401 ) ,
+ .prog_clk_3_W_in ( p2154 ) , .prog_clk_3_E_in ( p333 ) ,
+ .prog_clk_3_S_in ( p484 ) , .prog_clk_3_N_in ( p935 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3402 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3403 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3404 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3405 ) , .clk_1_N_in ( p2933 ) ,
+ .clk_1_S_in ( p841 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3406 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3407 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3408 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3409 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3410 ) ,
+ .clk_2_W_in ( clk_2_wires[26] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3411 ) ,
+ .clk_2_S_out ( clk_2_wires[31] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3412 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3413 ) , .clk_3_W_in ( p2154 ) ,
+ .clk_3_E_in ( p173 ) , .clk_3_S_in ( p2039 ) , .clk_3_N_in ( p2828 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3414 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3415 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3416 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+sb_1__1_ sb_5__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3418 } ) ,
+ .chany_top_in ( cby_1__1__51_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__57_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__50_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__46_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__57_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__46_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__46_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__46_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p1451 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3419 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3420 ) ,
+ .pReset_E_in ( pResetWires[180] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3421 ) ,
+ .pReset_N_out ( pResetWires[179] ) , .pReset_W_out ( pResetWires[177] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3422 ) , .Reset_S_in ( p1451 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3423 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[188] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[45] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3424 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[92] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p2923 ) ,
+ .prog_clk_2_E_in ( p726 ) , .prog_clk_2_S_in ( p1129 ) ,
+ .prog_clk_2_W_in ( p2645 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3425 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3426 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3427 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3428 ) ,
+ .prog_clk_3_W_in ( p2716 ) , .prog_clk_3_E_in ( p1047 ) ,
+ .prog_clk_3_S_in ( p248 ) , .prog_clk_3_N_in ( p2864 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3429 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3430 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3431 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3432 ) ,
+ .clk_1_N_in ( clk_2_wires[45] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3433 ) ,
+ .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) ,
+ .clk_2_N_in ( p3640 ) , .clk_2_E_in ( p185 ) , .clk_2_S_in ( p986 ) ,
+ .clk_2_W_in ( p3473 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3434 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3435 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3436 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3437 ) , .clk_3_W_in ( p3495 ) ,
+ .clk_3_E_in ( p322 ) , .clk_3_S_in ( p457 ) , .clk_3_N_in ( p3632 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3438 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3439 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3440 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+sb_1__1_ sb_5__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3442 } ) ,
+ .chany_top_in ( cby_1__1__52_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__58_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__51_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__47_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__58_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__47_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__47_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__47_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2173 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3443 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3444 ) ,
+ .pReset_E_in ( pResetWires[229] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3445 ) ,
+ .pReset_N_out ( pResetWires[228] ) , .pReset_W_out ( pResetWires[226] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , .Reset_S_in ( p2173 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3447 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p1448 ) ,
+ .prog_clk_1_S_in ( p908 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3448 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3449 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3450 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3451 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3452 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[35] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3453 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[44] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[42] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3454 ) ,
+ .prog_clk_3_W_in ( p1193 ) , .prog_clk_3_E_in ( p18 ) ,
+ .prog_clk_3_S_in ( p78 ) , .prog_clk_3_N_in ( p2024 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3455 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3456 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3457 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , .clk_1_N_in ( p2446 ) ,
+ .clk_1_S_in ( p144 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3459 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3460 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3461 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3462 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3463 ) ,
+ .clk_2_W_in ( clk_2_wires[35] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3464 ) ,
+ .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , .clk_3_W_in ( p1193 ) ,
+ .clk_3_E_in ( p393 ) , .clk_3_S_in ( p1923 ) , .clk_3_N_in ( p2283 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3466 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3467 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3468 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+sb_1__1_ sb_5__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3470 } ) ,
+ .chany_top_in ( cby_1__1__53_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__59_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__52_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__48_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__59_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__48_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__48_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__48_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p1357 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3471 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3472 ) ,
+ .pReset_E_in ( pResetWires[278] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3473 ) ,
+ .pReset_N_out ( pResetWires[277] ) , .pReset_W_out ( pResetWires[275] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3474 ) , .Reset_S_in ( p2462 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3475 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[194] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3476 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[43] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[99] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p3425 ) ,
+ .prog_clk_2_E_in ( p708 ) , .prog_clk_2_S_in ( p1269 ) ,
+ .prog_clk_2_W_in ( p3559 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3477 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3478 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3479 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3480 ) ,
+ .prog_clk_3_W_in ( p3568 ) , .prog_clk_3_E_in ( p993 ) ,
+ .prog_clk_3_S_in ( p2 ) , .prog_clk_3_N_in ( p3396 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3481 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3482 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3483 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3484 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3485 ) ,
+ .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) ,
+ .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p1455 ) ,
+ .clk_2_E_in ( p240 ) , .clk_2_S_in ( p2311 ) , .clk_2_W_in ( p2829 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3486 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3487 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3488 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_3_W_in ( p2899 ) ,
+ .clk_3_E_in ( p663 ) , .clk_3_S_in ( p394 ) , .clk_3_N_in ( p732 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3490 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3491 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3492 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+sb_1__1_ sb_5__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3494 } ) ,
+ .chany_top_in ( cby_1__1__54_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__60_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__53_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__49_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__60_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__49_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__49_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__49_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p2250 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3495 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3496 ) ,
+ .pReset_E_in ( pResetWires[327] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3497 ) ,
+ .pReset_N_out ( pResetWires[326] ) , .pReset_W_out ( pResetWires[324] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , .Reset_S_in ( p2250 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3499 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p1375 ) ,
+ .prog_clk_1_S_in ( p1043 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3500 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3501 ) ,
+ .prog_clk_2_N_in ( p2744 ) , .prog_clk_2_E_in ( p472 ) ,
+ .prog_clk_2_S_in ( p639 ) , .prog_clk_2_W_in ( p1546 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3502 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3503 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3504 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3505 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3506 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[3] ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3507 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3508 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3509 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[6] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3510 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_1_N_in ( p1375 ) ,
+ .clk_1_S_in ( p546 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3512 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , .clk_2_N_in ( p1375 ) ,
+ .clk_2_E_in ( p253 ) , .clk_2_S_in ( p1989 ) , .clk_2_W_in ( p1588 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3514 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3515 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3516 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3517 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3518 ) ,
+ .clk_3_E_in ( clk_3_wires[3] ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3519 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3520 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3521 ) ,
+ .clk_3_W_out ( clk_3_wires[6] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3522 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+sb_1__1_ sb_5__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3524 } ) ,
+ .chany_top_in ( cby_1__1__55_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__61_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__54_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__50_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__61_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__50_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__50_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__50_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2516 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3525 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3526 ) ,
+ .pReset_E_in ( pResetWires[376] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3527 ) ,
+ .pReset_N_out ( pResetWires[375] ) , .pReset_W_out ( pResetWires[373] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , .Reset_S_in ( p2516 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3529 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[200] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[58] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3530 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[106] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p2390 ) ,
+ .prog_clk_2_E_in ( p649 ) , .prog_clk_2_S_in ( p482 ) ,
+ .prog_clk_2_W_in ( p2883 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3531 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3532 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3533 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3534 ) ,
+ .prog_clk_3_W_in ( p2977 ) , .prog_clk_3_E_in ( p666 ) ,
+ .prog_clk_3_S_in ( p1111 ) , .prog_clk_3_N_in ( p2318 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3535 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3536 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3537 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3538 ) ,
+ .clk_1_N_in ( clk_2_wires[58] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3539 ) ,
+ .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) ,
+ .clk_2_N_in ( p2105 ) , .clk_2_E_in ( p236 ) , .clk_2_S_in ( p2297 ) ,
+ .clk_2_W_in ( p3329 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3540 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3541 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3542 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3543 ) , .clk_3_W_in ( p3348 ) ,
+ .clk_3_E_in ( p983 ) , .clk_3_S_in ( p367 ) , .clk_3_N_in ( p1986 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3544 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3545 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3546 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
+sb_1__1_ sb_5__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3548 } ) ,
+ .chany_top_in ( cby_1__1__56_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__62_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__55_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__51_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__62_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__51_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__51_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__51_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2751 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3549 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3550 ) ,
+ .pReset_E_in ( pResetWires[425] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3551 ) ,
+ .pReset_N_out ( pResetWires[424] ) , .pReset_W_out ( pResetWires[422] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , .Reset_S_in ( p2751 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3553 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p1748 ) ,
+ .prog_clk_1_S_in ( p904 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3554 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3555 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3556 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3557 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3558 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[48] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3559 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[57] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[55] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3560 ) ,
+ .prog_clk_3_W_in ( p1407 ) , .prog_clk_3_E_in ( p842 ) ,
+ .prog_clk_3_S_in ( p463 ) , .prog_clk_3_N_in ( p572 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3561 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3562 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3563 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3564 ) , .clk_1_N_in ( p3229 ) ,
+ .clk_1_S_in ( p263 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3565 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3566 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3567 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3568 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3569 ) ,
+ .clk_2_W_in ( clk_2_wires[48] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3570 ) ,
+ .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , .clk_3_W_in ( p1407 ) ,
+ .clk_3_E_in ( p258 ) , .clk_3_S_in ( p2555 ) , .clk_3_N_in ( p3199 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3572 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3573 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3574 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
+sb_1__1_ sb_5__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3576 } ) ,
+ .chany_top_in ( cby_1__1__57_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__63_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__56_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__52_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__63_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__52_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__52_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__52_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p2226 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3577 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3578 ) ,
+ .pReset_E_in ( pResetWires[474] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3579 ) ,
+ .pReset_N_out ( pResetWires[473] ) , .pReset_W_out ( pResetWires[471] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3580 ) , .Reset_S_in ( p3284 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3581 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[206] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3582 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[56] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[113] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3655 ) ,
+ .prog_clk_2_E_in ( p1075 ) , .prog_clk_2_S_in ( p1093 ) ,
+ .prog_clk_2_W_in ( p1983 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3583 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3584 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3585 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3586 ) ,
+ .prog_clk_3_W_in ( p2132 ) , .prog_clk_3_E_in ( p181 ) ,
+ .prog_clk_3_S_in ( p550 ) , .prog_clk_3_N_in ( p3654 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3587 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3588 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3589 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3590 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3591 ) ,
+ .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) ,
+ .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p3547 ) ,
+ .clk_2_E_in ( p618 ) , .clk_2_S_in ( p3184 ) , .clk_2_W_in ( p1942 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3592 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3593 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3594 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3595 ) , .clk_3_W_in ( p2205 ) ,
+ .clk_3_E_in ( p877 ) , .clk_3_S_in ( p135 ) , .clk_3_N_in ( p3515 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3596 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3597 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3598 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3599 ) ) ;
+sb_1__1_ sb_5__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3600 } ) ,
+ .chany_top_in ( cby_1__1__58_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__64_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__57_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__53_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__64_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__53_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__53_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__53_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p2493 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3601 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3602 ) ,
+ .pReset_E_in ( pResetWires[523] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3603 ) ,
+ .pReset_N_out ( pResetWires[522] ) , .pReset_W_out ( pResetWires[520] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , .Reset_S_in ( p2493 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3605 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p1796 ) ,
+ .prog_clk_1_S_in ( p700 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3606 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3607 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3608 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3609 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3610 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[61] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3611 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3612 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[66] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3613 ) ,
+ .prog_clk_3_W_in ( p1397 ) , .prog_clk_3_E_in ( p114 ) ,
+ .prog_clk_3_S_in ( p296 ) , .prog_clk_3_N_in ( p2001 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3614 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3615 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3616 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3617 ) , .clk_1_N_in ( p3092 ) ,
+ .clk_1_S_in ( p189 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3618 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3619 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3620 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3621 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3622 ) ,
+ .clk_2_W_in ( clk_2_wires[61] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3623 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3624 ) ,
+ .clk_2_N_out ( clk_2_wires[66] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3625 ) , .clk_3_W_in ( p1466 ) ,
+ .clk_3_E_in ( p598 ) , .clk_3_S_in ( p2285 ) , .clk_3_N_in ( p3029 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3626 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3627 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3628 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3629 ) ) ;
+sb_1__1_ sb_5__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3630 } ) ,
+ .chany_top_in ( cby_1__1__59_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__65_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__58_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__54_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__65_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__54_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__54_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__54_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p2209 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3631 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3632 ) ,
+ .pReset_E_in ( pResetWires[572] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3633 ) ,
+ .pReset_N_out ( pResetWires[571] ) , .pReset_W_out ( pResetWires[569] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_3634 ) , .Reset_S_in ( p3578 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3635 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[212] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3636 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[67] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[120] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p3634 ) ,
+ .prog_clk_2_E_in ( p106 ) , .prog_clk_2_S_in ( p933 ) ,
+ .prog_clk_2_W_in ( p2015 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3637 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3638 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3639 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3640 ) ,
+ .prog_clk_3_W_in ( p2055 ) , .prog_clk_3_E_in ( p735 ) ,
+ .prog_clk_3_S_in ( p509 ) , .prog_clk_3_N_in ( p3629 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3641 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3642 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3643 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3644 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3645 ) ,
+ .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) ,
+ .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3147 ) ,
+ .clk_2_E_in ( p929 ) , .clk_2_S_in ( p3562 ) , .clk_2_W_in ( p2579 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3646 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3647 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3648 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3649 ) , .clk_3_W_in ( p2795 ) ,
+ .clk_3_E_in ( p609 ) , .clk_3_S_in ( p441 ) , .clk_3_N_in ( p3061 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3650 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3651 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3652 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3653 ) ) ;
+sb_1__1_ sb_6__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3654 } ) ,
+ .chany_top_in ( cby_1__1__61_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__66_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__60_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__55_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__66_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__55_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__55_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__55_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__55_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__55_ccff_tail ) , .Test_en_S_in ( Test_enWires[2] ) ,
+ .Test_en_N_out ( Test_enWires[3] ) , .pReset_S_in ( pResetWires[2] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3655 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3656 ) ,
+ .pReset_N_out ( pResetWires[85] ) , .pReset_W_out ( pResetWires[83] ) ,
+ .pReset_E_out ( pResetWires[86] ) , .Reset_S_in ( ResetWires[2] ) ,
+ .Reset_N_out ( ResetWires[3] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1166 ) ,
+ .prog_clk_1_S_in ( p76 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3657 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3658 ) ,
+ .prog_clk_2_N_in ( p1656 ) , .prog_clk_2_E_in ( p671 ) ,
+ .prog_clk_2_S_in ( p387 ) , .prog_clk_2_W_in ( p113 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3659 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3660 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3661 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3662 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3663 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3664 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[89] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3665 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3666 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3667 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[92] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_1_N_in ( p1656 ) ,
+ .clk_1_S_in ( p889 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3669 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3670 ) , .clk_2_N_in ( p1656 ) ,
+ .clk_2_E_in ( p175 ) , .clk_2_S_in ( p476 ) , .clk_2_W_in ( p662 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3671 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3672 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3673 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3674 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3675 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3676 ) ,
+ .clk_3_S_in ( clk_3_wires[89] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3677 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3678 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3679 ) ,
+ .clk_3_N_out ( clk_3_wires[92] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3680 ) ) ;
+sb_1__1_ sb_6__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3681 } ) ,
+ .chany_top_in ( cby_1__1__62_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__67_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__61_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__56_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__67_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__56_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__56_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__56_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__56_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__56_ccff_tail ) , .Test_en_S_in ( Test_enWires[4] ) ,
+ .Test_en_N_out ( Test_enWires[5] ) , .pReset_S_in ( pResetWires[4] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3682 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3683 ) ,
+ .pReset_N_out ( pResetWires[134] ) , .pReset_W_out ( pResetWires[132] ) ,
+ .pReset_E_out ( pResetWires[135] ) , .Reset_S_in ( ResetWires[4] ) ,
+ .Reset_N_out ( ResetWires[5] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1459 ) ,
+ .prog_clk_1_S_in ( p471 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3684 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3685 ) ,
+ .prog_clk_2_N_in ( p1080 ) , .prog_clk_2_E_in ( p226 ) ,
+ .prog_clk_2_S_in ( p500 ) , .prog_clk_2_W_in ( p495 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3686 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3687 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3688 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3689 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3690 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3691 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[91] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3692 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3693 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3694 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[94] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_1_N_in ( p1080 ) ,
+ .clk_1_S_in ( p1014 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3696 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3697 ) , .clk_2_N_in ( p1080 ) ,
+ .clk_2_E_in ( p626 ) , .clk_2_S_in ( p79 ) , .clk_2_W_in ( p528 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3698 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3699 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3700 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3701 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3702 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3703 ) ,
+ .clk_3_S_in ( clk_3_wires[91] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3704 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3705 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3706 ) ,
+ .clk_3_N_out ( clk_3_wires[94] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3707 ) ) ;
+sb_1__1_ sb_6__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3708 } ) ,
+ .chany_top_in ( cby_1__1__63_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__68_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__62_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__57_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__68_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__57_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__57_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__57_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__57_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__57_ccff_tail ) , .Test_en_S_in ( Test_enWires[6] ) ,
+ .Test_en_N_out ( Test_enWires[7] ) , .pReset_S_in ( pResetWires[6] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3709 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3710 ) ,
+ .pReset_N_out ( pResetWires[183] ) , .pReset_W_out ( pResetWires[181] ) ,
+ .pReset_E_out ( pResetWires[184] ) , .Reset_S_in ( ResetWires[6] ) ,
+ .Reset_N_out ( ResetWires[7] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1333 ) ,
+ .prog_clk_1_S_in ( p356 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3711 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3712 ) ,
+ .prog_clk_2_N_in ( p2162 ) , .prog_clk_2_E_in ( p570 ) ,
+ .prog_clk_2_S_in ( p214 ) , .prog_clk_2_W_in ( p807 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3713 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3714 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3715 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3716 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3717 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3718 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[93] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3719 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3720 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3721 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[96] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_1_N_in ( p1307 ) ,
+ .clk_1_S_in ( p73 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3723 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3724 ) , .clk_2_N_in ( p1307 ) ,
+ .clk_2_E_in ( p724 ) , .clk_2_S_in ( p603 ) , .clk_2_W_in ( p304 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3725 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3726 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3727 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3728 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3729 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3730 ) ,
+ .clk_3_S_in ( clk_3_wires[93] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3731 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3732 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3733 ) ,
+ .clk_3_N_out ( clk_3_wires[96] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3734 ) ) ;
+sb_1__1_ sb_6__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3735 } ) ,
+ .chany_top_in ( cby_1__1__64_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__69_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__63_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__58_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__69_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__58_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__58_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__58_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__58_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__58_ccff_tail ) , .Test_en_S_in ( Test_enWires[8] ) ,
+ .Test_en_N_out ( Test_enWires[9] ) , .pReset_S_in ( pResetWires[8] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3736 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3737 ) ,
+ .pReset_N_out ( pResetWires[232] ) , .pReset_W_out ( pResetWires[230] ) ,
+ .pReset_E_out ( pResetWires[233] ) , .Reset_S_in ( ResetWires[8] ) ,
+ .Reset_N_out ( ResetWires[9] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1348 ) ,
+ .prog_clk_1_S_in ( p224 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3738 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3739 ) ,
+ .prog_clk_2_N_in ( p1322 ) , .prog_clk_2_E_in ( p172 ) ,
+ .prog_clk_2_S_in ( p222 ) , .prog_clk_2_W_in ( p560 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3740 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3741 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3742 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3743 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3744 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3745 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[95] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3746 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3747 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3748 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[98] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_1_N_in ( p1322 ) ,
+ .clk_1_S_in ( p868 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3750 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3751 ) , .clk_2_N_in ( p1439 ) ,
+ .clk_2_E_in ( p740 ) , .clk_2_S_in ( p516 ) , .clk_2_W_in ( p64 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3752 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3753 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3754 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3755 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3756 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3757 ) ,
+ .clk_3_S_in ( clk_3_wires[95] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3758 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3759 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3760 ) ,
+ .clk_3_N_out ( clk_3_wires[98] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3761 ) ) ;
+sb_1__1_ sb_6__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3762 } ) ,
+ .chany_top_in ( cby_1__1__65_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__70_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__64_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__59_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__70_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__59_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__59_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__59_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__59_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__59_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[10] ) , .Test_en_N_out ( Test_enWires[11] ) ,
+ .pReset_S_in ( pResetWires[10] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3763 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3764 ) ,
+ .pReset_N_out ( pResetWires[281] ) , .pReset_W_out ( pResetWires[279] ) ,
+ .pReset_E_out ( pResetWires[282] ) , .Reset_S_in ( ResetWires[10] ) ,
+ .Reset_N_out ( ResetWires[11] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p1325 ) ,
+ .prog_clk_1_S_in ( p260 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3765 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3766 ) ,
+ .prog_clk_2_N_in ( p1414 ) , .prog_clk_2_E_in ( p355 ) ,
+ .prog_clk_2_S_in ( p2312 ) , .prog_clk_2_W_in ( p122 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3767 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3768 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3769 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3770 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3771 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3772 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[97] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3773 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3774 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3775 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[100] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_1_N_in ( p1414 ) ,
+ .clk_1_S_in ( p596 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3777 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3778 ) , .clk_2_N_in ( p1414 ) ,
+ .clk_2_E_in ( p338 ) , .clk_2_S_in ( p415 ) , .clk_2_W_in ( p480 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3779 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3780 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3781 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3782 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3783 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3784 ) ,
+ .clk_3_S_in ( clk_3_wires[97] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3785 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3786 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3787 ) ,
+ .clk_3_N_out ( clk_3_wires[100] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3788 ) ) ;
+sb_1__1_ sb_6__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3789 } ) ,
+ .chany_top_in ( cby_1__1__66_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__71_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__65_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__60_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__71_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__60_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__60_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__60_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__60_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__60_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[12] ) , .Test_en_N_out ( Test_enWires[13] ) ,
+ .pReset_S_in ( pResetWires[12] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3790 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3791 ) ,
+ .pReset_N_out ( pResetWires[330] ) , .pReset_W_out ( pResetWires[328] ) ,
+ .pReset_E_out ( pResetWires[331] ) , .Reset_S_in ( ResetWires[12] ) ,
+ .Reset_N_out ( ResetWires[13] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1314 ) ,
+ .prog_clk_1_S_in ( p354 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3792 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3793 ) ,
+ .prog_clk_2_N_in ( p1896 ) , .prog_clk_2_E_in ( p514 ) ,
+ .prog_clk_2_S_in ( p1503 ) , .prog_clk_2_W_in ( p1501 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3794 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3795 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3796 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3797 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3798 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3799 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[99] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3800 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[0] ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[2] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3801 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_1_N_in ( p1314 ) ,
+ .clk_1_S_in ( p814 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3803 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3804 ) , .clk_2_N_in ( p1314 ) ,
+ .clk_2_E_in ( p485 ) , .clk_2_S_in ( p585 ) , .clk_2_W_in ( p1518 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3805 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3806 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3807 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3808 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3809 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3810 ) ,
+ .clk_3_S_in ( clk_3_wires[99] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3811 ) ,
+ .clk_3_E_out ( clk_3_wires[0] ) , .clk_3_W_out ( clk_3_wires[2] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3812 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3813 ) ) ;
+sb_1__1_ sb_6__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3814 } ) ,
+ .chany_top_in ( cby_1__1__67_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__72_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__66_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__61_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__72_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__61_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__61_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__61_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__61_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__61_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[14] ) , .Test_en_N_out ( Test_enWires[15] ) ,
+ .pReset_S_in ( pResetWires[14] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3815 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3816 ) ,
+ .pReset_N_out ( pResetWires[379] ) , .pReset_W_out ( pResetWires[377] ) ,
+ .pReset_E_out ( pResetWires[380] ) , .Reset_S_in ( ResetWires[14] ) ,
+ .Reset_N_out ( ResetWires[15] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p2152 ) ,
+ .prog_clk_1_S_in ( p965 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3817 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3818 ) ,
+ .prog_clk_2_N_in ( p3510 ) , .prog_clk_2_E_in ( p677 ) ,
+ .prog_clk_2_S_in ( p963 ) , .prog_clk_2_W_in ( p3615 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3819 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3820 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3821 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3822 ) ,
+ .prog_clk_3_W_in ( p3626 ) , .prog_clk_3_E_in ( p746 ) ,
+ .prog_clk_3_S_in ( p218 ) , .prog_clk_3_N_in ( p3469 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3823 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3824 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3825 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_1_N_in ( p2514 ) ,
+ .clk_1_S_in ( p47 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3827 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3828 ) , .clk_2_N_in ( p3243 ) ,
+ .clk_2_E_in ( p155 ) , .clk_2_S_in ( p336 ) , .clk_2_W_in ( p2650 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3829 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3830 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3831 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3832 ) , .clk_3_W_in ( p2667 ) ,
+ .clk_3_E_in ( p822 ) , .clk_3_S_in ( p1159 ) , .clk_3_N_in ( p3212 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3833 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3834 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3835 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3836 ) ) ;
+sb_1__1_ sb_6__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3837 } ) ,
+ .chany_top_in ( cby_1__1__68_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__73_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__67_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__62_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__73_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__62_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__62_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__62_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__62_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__62_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[16] ) , .Test_en_N_out ( Test_enWires[17] ) ,
+ .pReset_S_in ( pResetWires[16] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3838 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3839 ) ,
+ .pReset_N_out ( pResetWires[428] ) , .pReset_W_out ( pResetWires[426] ) ,
+ .pReset_E_out ( pResetWires[429] ) , .Reset_S_in ( ResetWires[16] ) ,
+ .Reset_N_out ( ResetWires[17] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p2429 ) ,
+ .prog_clk_1_S_in ( p900 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3840 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3841 ) ,
+ .prog_clk_2_N_in ( p3663 ) , .prog_clk_2_E_in ( p191 ) ,
+ .prog_clk_2_S_in ( p1001 ) , .prog_clk_2_W_in ( p2808 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3842 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3843 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3844 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3845 ) ,
+ .prog_clk_3_W_in ( p2925 ) , .prog_clk_3_E_in ( p1068 ) ,
+ .prog_clk_3_S_in ( p385 ) , .prog_clk_3_N_in ( p3660 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3846 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3847 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3848 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_1_N_in ( p2454 ) ,
+ .clk_1_S_in ( p249 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3850 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , .clk_2_N_in ( p3530 ) ,
+ .clk_2_E_in ( p211 ) , .clk_2_S_in ( p978 ) , .clk_2_W_in ( p3314 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3852 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3853 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3854 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3855 ) , .clk_3_W_in ( p3368 ) ,
+ .clk_3_E_in ( p601 ) , .clk_3_S_in ( p559 ) , .clk_3_N_in ( p3514 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3856 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3857 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3858 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3859 ) ) ;
+sb_1__1_ sb_6__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3860 } ) ,
+ .chany_top_in ( cby_1__1__69_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__74_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__68_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__63_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__74_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__63_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__63_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__63_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__63_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__63_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[18] ) , .Test_en_N_out ( Test_enWires[19] ) ,
+ .pReset_S_in ( pResetWires[18] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3861 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3862 ) ,
+ .pReset_N_out ( pResetWires[477] ) , .pReset_W_out ( pResetWires[475] ) ,
+ .pReset_E_out ( pResetWires[478] ) , .Reset_S_in ( ResetWires[18] ) ,
+ .Reset_N_out ( ResetWires[19] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p1141 ) ,
+ .prog_clk_1_S_in ( p311 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3863 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3864 ) ,
+ .prog_clk_2_N_in ( p3535 ) , .prog_clk_2_E_in ( p945 ) ,
+ .prog_clk_2_S_in ( p607 ) , .prog_clk_2_W_in ( p3037 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3865 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3866 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3867 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3868 ) ,
+ .prog_clk_3_W_in ( p3145 ) , .prog_clk_3_E_in ( p158 ) ,
+ .prog_clk_3_S_in ( p1003 ) , .prog_clk_3_N_in ( p3526 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3869 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3870 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3871 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_1_N_in ( p2430 ) ,
+ .clk_1_S_in ( p712 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3873 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .clk_2_N_in ( p3233 ) ,
+ .clk_2_E_in ( p821 ) , .clk_2_S_in ( p854 ) , .clk_2_W_in ( p2281 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3875 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3876 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3877 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3878 ) , .clk_3_W_in ( p2405 ) ,
+ .clk_3_E_in ( p443 ) , .clk_3_S_in ( p368 ) , .clk_3_N_in ( p3191 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3879 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3880 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3881 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3882 ) ) ;
+sb_1__1_ sb_6__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3883 } ) ,
+ .chany_top_in ( cby_1__1__70_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__75_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__69_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__64_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__75_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__64_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__64_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__64_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__64_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__64_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[20] ) , .Test_en_N_out ( Test_enWires[21] ) ,
+ .pReset_S_in ( pResetWires[20] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3884 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3885 ) ,
+ .pReset_N_out ( pResetWires[526] ) , .pReset_W_out ( pResetWires[524] ) ,
+ .pReset_E_out ( pResetWires[527] ) , .Reset_S_in ( ResetWires[20] ) ,
+ .Reset_N_out ( ResetWires[21] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p2461 ) ,
+ .prog_clk_1_S_in ( p891 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3886 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3887 ) ,
+ .prog_clk_2_N_in ( p3672 ) , .prog_clk_2_E_in ( p1115 ) ,
+ .prog_clk_2_S_in ( p405 ) , .prog_clk_2_W_in ( p3464 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3888 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3889 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3890 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3891 ) ,
+ .prog_clk_3_W_in ( p3491 ) , .prog_clk_3_E_in ( p35 ) ,
+ .prog_clk_3_S_in ( p819 ) , .prog_clk_3_N_in ( p3670 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3892 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3893 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3894 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_1_N_in ( p1265 ) ,
+ .clk_1_S_in ( p160 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3896 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3897 ) , .clk_2_N_in ( p3097 ) ,
+ .clk_2_E_in ( p574 ) , .clk_2_S_in ( p1059 ) , .clk_2_W_in ( p2017 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3898 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3899 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3900 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3901 ) , .clk_3_W_in ( p2126 ) ,
+ .clk_3_E_in ( p672 ) , .clk_3_S_in ( p225 ) , .clk_3_N_in ( p3012 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3902 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3903 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3904 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3905 ) ) ;
+sb_1__1_ sb_6__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3906 } ) ,
+ .chany_top_in ( cby_1__1__71_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__76_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__70_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__65_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__76_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__65_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__65_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__65_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__65_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__65_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[22] ) , .Test_en_N_out ( Test_enWires[23] ) ,
+ .pReset_S_in ( pResetWires[22] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3907 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_3908 ) ,
+ .pReset_N_out ( pResetWires[575] ) , .pReset_W_out ( pResetWires[573] ) ,
+ .pReset_E_out ( pResetWires[576] ) , .Reset_S_in ( ResetWires[22] ) ,
+ .Reset_N_out ( ResetWires[23] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p907 ) ,
+ .prog_clk_1_S_in ( p777 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3909 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3910 ) ,
+ .prog_clk_2_N_in ( p3674 ) , .prog_clk_2_E_in ( p856 ) ,
+ .prog_clk_2_S_in ( p262 ) , .prog_clk_2_W_in ( p2034 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3911 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3912 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3913 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3914 ) ,
+ .prog_clk_3_W_in ( p2119 ) , .prog_clk_3_E_in ( p8 ) ,
+ .prog_clk_3_S_in ( p913 ) , .prog_clk_3_N_in ( p3673 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3915 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3916 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3917 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_1_N_in ( p2764 ) ,
+ .clk_1_S_in ( p83 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , .clk_2_N_in ( p3450 ) ,
+ .clk_2_E_in ( p818 ) , .clk_2_S_in ( p324 ) , .clk_2_W_in ( p2838 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3921 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3922 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3923 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , .clk_3_W_in ( p2983 ) ,
+ .clk_3_E_in ( p519 ) , .clk_3_S_in ( p1103 ) , .clk_3_N_in ( p3417 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3925 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3926 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3927 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3928 ) ) ;
+sb_1__1_ sb_7__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3929 } ) ,
+ .chany_top_in ( cby_1__1__73_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__77_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__72_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__66_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__77_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__66_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__66_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__66_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p2936 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3930 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3931 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3932 ) ,
+ .pReset_W_in ( pResetWires[87] ) , .pReset_N_out ( pResetWires[89] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_3933 ) ,
+ .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( p3637 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3934 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[258] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[74] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3935 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[127] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p2920 ) ,
+ .prog_clk_2_E_in ( p648 ) , .prog_clk_2_S_in ( p33 ) ,
+ .prog_clk_2_W_in ( p1477 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3936 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3937 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3938 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3939 ) ,
+ .prog_clk_3_W_in ( p1861 ) , .prog_clk_3_E_in ( p169 ) ,
+ .prog_clk_3_S_in ( p760 ) , .prog_clk_3_N_in ( p2872 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3940 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3941 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3942 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3943 ) ,
+ .clk_1_N_in ( clk_2_wires[74] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3944 ) ,
+ .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) ,
+ .clk_2_N_in ( p3133 ) , .clk_2_E_in ( p243 ) , .clk_2_S_in ( p3630 ) ,
+ .clk_2_W_in ( p2815 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3946 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3947 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , .clk_3_W_in ( p2891 ) ,
+ .clk_3_E_in ( p610 ) , .clk_3_S_in ( p328 ) , .clk_3_N_in ( p3042 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3949 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3950 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3951 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3952 ) ) ;
+sb_1__1_ sb_7__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3953 } ) ,
+ .chany_top_in ( cby_1__1__74_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__78_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__73_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__67_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__78_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__67_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__67_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__67_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p2796 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3954 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3955 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3956 ) ,
+ .pReset_W_in ( pResetWires[136] ) , .pReset_N_out ( pResetWires[138] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_3957 ) ,
+ .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( p2796 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3958 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p1839 ) ,
+ .prog_clk_1_S_in ( p982 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3959 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3960 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3961 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[72] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3962 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3963 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3964 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[73] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3965 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3966 ) ,
+ .prog_clk_3_W_in ( p1372 ) , .prog_clk_3_E_in ( p373 ) ,
+ .prog_clk_3_S_in ( p602 ) , .prog_clk_3_N_in ( p638 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3967 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3968 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3969 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( p2676 ) ,
+ .clk_1_S_in ( p231 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3971 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3972 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3973 ) ,
+ .clk_2_E_in ( clk_2_wires[72] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3974 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3975 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3976 ) ,
+ .clk_2_S_out ( clk_2_wires[73] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3977 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3978 ) , .clk_3_W_in ( p1372 ) ,
+ .clk_3_E_in ( p377 ) , .clk_3_S_in ( p2578 ) , .clk_3_N_in ( p2587 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3979 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3980 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3981 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3982 ) ) ;
+sb_1__1_ sb_7__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_3983 } ) ,
+ .chany_top_in ( cby_1__1__75_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__79_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__74_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__68_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__79_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__68_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__68_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__68_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2945 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3984 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_3985 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_3986 ) ,
+ .pReset_W_in ( pResetWires[185] ) , .pReset_N_out ( pResetWires[187] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_3987 ) ,
+ .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( p3283 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_3988 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[264] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[85] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3989 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[134] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3664 ) ,
+ .prog_clk_2_E_in ( p268 ) , .prog_clk_2_S_in ( p149 ) ,
+ .prog_clk_2_W_in ( p3666 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3990 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3991 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3992 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3993 ) ,
+ .prog_clk_3_W_in ( p3667 ) , .prog_clk_3_E_in ( p776 ) ,
+ .prog_clk_3_S_in ( p992 ) , .prog_clk_3_N_in ( p3661 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3994 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3995 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3996 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3997 ) ,
+ .clk_1_N_in ( clk_2_wires[85] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3998 ) ,
+ .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) ,
+ .clk_2_N_in ( p3608 ) , .clk_2_E_in ( p597 ) , .clk_2_S_in ( p3190 ) ,
+ .clk_2_W_in ( p3456 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3999 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4000 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4001 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4002 ) , .clk_3_W_in ( p3509 ) ,
+ .clk_3_E_in ( p583 ) , .clk_3_S_in ( p1175 ) , .clk_3_N_in ( p3595 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4003 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4004 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4005 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4006 ) ) ;
+sb_1__1_ sb_7__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4007 } ) ,
+ .chany_top_in ( cby_1__1__76_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__80_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__75_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__69_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__80_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__69_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__69_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__69_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p2157 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4008 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4009 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4010 ) ,
+ .pReset_W_in ( pResetWires[234] ) , .pReset_N_out ( pResetWires[236] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4011 ) ,
+ .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( p2157 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4012 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p2736 ) ,
+ .prog_clk_1_S_in ( p830 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4013 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4014 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4015 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[81] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4016 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4017 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4018 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[84] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[82] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4019 ) ,
+ .prog_clk_3_W_in ( p1650 ) , .prog_clk_3_E_in ( p725 ) ,
+ .prog_clk_3_S_in ( p675 ) , .prog_clk_3_N_in ( p1912 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4020 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4021 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4022 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) , .clk_1_N_in ( p2441 ) ,
+ .clk_1_S_in ( p19 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4024 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4025 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4026 ) ,
+ .clk_2_E_in ( clk_2_wires[81] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4027 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4028 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4029 ) ,
+ .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4030 ) , .clk_3_W_in ( p1650 ) ,
+ .clk_3_E_in ( p187 ) , .clk_3_S_in ( p1959 ) , .clk_3_N_in ( p2592 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4031 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4032 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4033 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4034 ) ) ;
+sb_1__1_ sb_7__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4035 } ) ,
+ .chany_top_in ( cby_1__1__77_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__81_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__76_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__70_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__81_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__70_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__70_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__70_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p2413 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4036 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4037 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4038 ) ,
+ .pReset_W_in ( pResetWires[283] ) , .pReset_N_out ( pResetWires[285] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4039 ) ,
+ .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( p2413 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4040 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[270] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4041 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[83] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[141] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3607 ) ,
+ .prog_clk_2_E_in ( p143 ) , .prog_clk_2_S_in ( p449 ) ,
+ .prog_clk_2_W_in ( p3166 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4042 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4043 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4044 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4045 ) ,
+ .prog_clk_3_W_in ( p3222 ) , .prog_clk_3_E_in ( p924 ) ,
+ .prog_clk_3_S_in ( p864 ) , .prog_clk_3_N_in ( p3586 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4046 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4047 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4048 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4049 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4050 ) ,
+ .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) ,
+ .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3380 ) ,
+ .clk_2_E_in ( p845 ) , .clk_2_S_in ( p2290 ) , .clk_2_W_in ( p2879 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4051 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4052 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4053 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4054 ) , .clk_3_W_in ( p2957 ) ,
+ .clk_3_E_in ( p710 ) , .clk_3_S_in ( p111 ) , .clk_3_N_in ( p3324 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4055 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4056 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4057 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4058 ) ) ;
+sb_1__1_ sb_7__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4059 } ) ,
+ .chany_top_in ( cby_1__1__78_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__82_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__77_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__71_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__82_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__71_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__71_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__71_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2907 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4060 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4061 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4062 ) ,
+ .pReset_W_in ( pResetWires[332] ) , .pReset_N_out ( pResetWires[334] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4063 ) ,
+ .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( p3506 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4064 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1344 ) ,
+ .prog_clk_1_S_in ( p363 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4065 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4066 ) ,
+ .prog_clk_2_N_in ( p1240 ) , .prog_clk_2_E_in ( p683 ) ,
+ .prog_clk_2_S_in ( p156 ) , .prog_clk_2_W_in ( p497 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4067 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4068 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4069 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4070 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[1] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4071 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4072 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4073 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[4] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4074 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4075 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p1240 ) ,
+ .clk_1_S_in ( p852 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p1240 ) ,
+ .clk_2_E_in ( p12 ) , .clk_2_S_in ( p3466 ) , .clk_2_W_in ( p176 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4079 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4080 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4081 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4082 ) ,
+ .clk_3_W_in ( clk_3_wires[1] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4083 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4084 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4085 ) ,
+ .clk_3_E_out ( clk_3_wires[4] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4086 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4087 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4088 ) ) ;
+sb_1__1_ sb_7__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4089 } ) ,
+ .chany_top_in ( cby_1__1__79_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__83_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__78_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__72_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__83_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__72_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__72_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__72_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p2762 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4090 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4091 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4092 ) ,
+ .pReset_W_in ( pResetWires[381] ) , .pReset_N_out ( pResetWires[383] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4093 ) ,
+ .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( p2762 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4094 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[276] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[98] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4095 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[148] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p3571 ) ,
+ .prog_clk_2_E_in ( p527 ) , .prog_clk_2_S_in ( p107 ) ,
+ .prog_clk_2_W_in ( p3000 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4096 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4097 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4098 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4099 ) ,
+ .prog_clk_3_W_in ( p3120 ) , .prog_clk_3_E_in ( p668 ) ,
+ .prog_clk_3_S_in ( p816 ) , .prog_clk_3_N_in ( p3563 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4100 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4101 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4102 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4103 ) ,
+ .clk_1_N_in ( clk_2_wires[98] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4104 ) ,
+ .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) ,
+ .clk_2_N_in ( p3507 ) , .clk_2_E_in ( p741 ) , .clk_2_S_in ( p2566 ) ,
+ .clk_2_W_in ( p1935 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4105 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4106 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4107 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4108 ) , .clk_3_W_in ( p2059 ) ,
+ .clk_3_E_in ( p370 ) , .clk_3_S_in ( p272 ) , .clk_3_N_in ( p3477 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4109 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4110 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4111 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4112 ) ) ;
+sb_1__1_ sb_7__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4113 } ) ,
+ .chany_top_in ( cby_1__1__80_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__84_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__79_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__73_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__84_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__73_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__73_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__73_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p2994 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4114 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4115 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4116 ) ,
+ .pReset_W_in ( pResetWires[430] ) , .pReset_N_out ( pResetWires[432] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4117 ) ,
+ .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( p2994 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4118 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p1742 ) ,
+ .prog_clk_1_S_in ( p5 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4119 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4120 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4121 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[94] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4122 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4123 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4124 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[97] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[95] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4125 ) ,
+ .prog_clk_3_W_in ( p1889 ) , .prog_clk_3_E_in ( p145 ) ,
+ .prog_clk_3_S_in ( p209 ) , .prog_clk_3_N_in ( p1579 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4126 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4127 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4128 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4129 ) , .clk_1_N_in ( p1769 ) ,
+ .clk_1_S_in ( p893 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4130 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4131 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4132 ) ,
+ .clk_2_E_in ( clk_2_wires[94] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4133 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4134 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4135 ) ,
+ .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4136 ) , .clk_3_W_in ( p1889 ) ,
+ .clk_3_E_in ( p827 ) , .clk_3_S_in ( p2811 ) , .clk_3_N_in ( p1511 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4137 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4138 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4139 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4140 ) ) ;
+sb_1__1_ sb_7__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4141 } ) ,
+ .chany_top_in ( cby_1__1__81_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__85_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__80_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__74_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__85_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__74_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__74_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__74_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p2086 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4142 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4143 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4144 ) ,
+ .pReset_W_in ( pResetWires[479] ) , .pReset_N_out ( pResetWires[481] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4145 ) ,
+ .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( p2468 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4146 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[282] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4147 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[96] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[155] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p2432 ) ,
+ .prog_clk_2_E_in ( p1143 ) , .prog_clk_2_S_in ( p828 ) ,
+ .prog_clk_2_W_in ( p2588 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4148 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4149 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4150 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4151 ) ,
+ .prog_clk_3_W_in ( p2765 ) , .prog_clk_3_E_in ( p521 ) ,
+ .prog_clk_3_S_in ( p72 ) , .prog_clk_3_N_in ( p2345 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4152 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4153 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4154 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4155 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4156 ) ,
+ .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) ,
+ .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3232 ) ,
+ .clk_2_E_in ( p838 ) , .clk_2_S_in ( p2302 ) , .clk_2_W_in ( p2305 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4157 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4158 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4159 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_3_W_in ( p2496 ) ,
+ .clk_3_E_in ( p141 ) , .clk_3_S_in ( p437 ) , .clk_3_N_in ( p3170 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4161 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4162 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4163 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4164 ) ) ;
+sb_1__1_ sb_7__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4165 } ) ,
+ .chany_top_in ( cby_1__1__82_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__86_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__81_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__75_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__86_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__75_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__75_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__75_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p3235 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4166 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4167 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4168 ) ,
+ .pReset_W_in ( pResetWires[528] ) , .pReset_N_out ( pResetWires[530] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4169 ) ,
+ .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( p3235 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4170 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p2436 ) ,
+ .prog_clk_1_S_in ( p917 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4171 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4172 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4173 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[107] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4174 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4175 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4176 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4177 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[108] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4178 ) ,
+ .prog_clk_3_W_in ( p1882 ) , .prog_clk_3_E_in ( p1492 ) ,
+ .prog_clk_3_S_in ( p688 ) , .prog_clk_3_N_in ( p762 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4179 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4180 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4181 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , .clk_1_N_in ( p2181 ) ,
+ .clk_1_S_in ( p81 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4183 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4184 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4185 ) ,
+ .clk_2_E_in ( clk_2_wires[107] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4186 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4187 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4188 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4189 ) ,
+ .clk_2_N_out ( clk_2_wires[108] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4190 ) , .clk_3_W_in ( p1882 ) ,
+ .clk_3_E_in ( p1612 ) , .clk_3_S_in ( p3203 ) , .clk_3_N_in ( p2266 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4191 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4192 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4193 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4194 ) ) ;
+sb_1__1_ sb_7__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4195 } ) ,
+ .chany_top_in ( cby_1__1__83_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__87_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__82_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__76_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__87_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__76_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__76_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__76_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p2169 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4196 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4197 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4198 ) ,
+ .pReset_W_in ( pResetWires[577] ) , .pReset_N_out ( pResetWires[579] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4199 ) ,
+ .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( p3228 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4200 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[288] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4201 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[109] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[162] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3252 ) ,
+ .prog_clk_2_E_in ( p906 ) , .prog_clk_2_S_in ( p1204 ) ,
+ .prog_clk_2_W_in ( p3675 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4202 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4203 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4204 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4205 ) ,
+ .prog_clk_3_W_in ( p3676 ) , .prog_clk_3_E_in ( p223 ) ,
+ .prog_clk_3_S_in ( p477 ) , .prog_clk_3_N_in ( p3218 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4206 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4207 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4208 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4209 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4210 ) ,
+ .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) ,
+ .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p3349 ) ,
+ .clk_2_E_in ( p805 ) , .clk_2_S_in ( p3189 ) , .clk_2_W_in ( p3180 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4211 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4212 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4213 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4214 ) , .clk_3_W_in ( p3259 ) ,
+ .clk_3_E_in ( p352 ) , .clk_3_S_in ( p990 ) , .clk_3_N_in ( p3315 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4215 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4216 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4217 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4218 ) ) ;
+sb_1__1_ sb_8__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4219 } ) ,
+ .chany_top_in ( cby_1__1__85_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__88_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__84_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__77_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__88_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__77_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__77_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__77_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p3238 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4220 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4221 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4222 ) ,
+ .pReset_W_in ( pResetWires[91] ) , .pReset_N_out ( pResetWires[93] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4223 ) ,
+ .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( p3238 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4224 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p1642 ) ,
+ .prog_clk_1_S_in ( p797 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4225 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4226 ) ,
+ .prog_clk_2_N_in ( p2726 ) , .prog_clk_2_E_in ( p751 ) ,
+ .prog_clk_2_S_in ( p571 ) , .prog_clk_2_W_in ( p2021 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4227 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4228 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4229 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4230 ) ,
+ .prog_clk_3_W_in ( p2247 ) , .prog_clk_3_E_in ( p56 ) ,
+ .prog_clk_3_S_in ( p719 ) , .prog_clk_3_N_in ( p2556 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4231 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4232 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4233 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_1_N_in ( p2214 ) ,
+ .clk_1_S_in ( p202 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4235 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4236 ) , .clk_2_N_in ( p3255 ) ,
+ .clk_2_E_in ( p703 ) , .clk_2_S_in ( p3160 ) , .clk_2_W_in ( p1906 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4237 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4238 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4239 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_3_W_in ( p2163 ) ,
+ .clk_3_E_in ( p0 ) , .clk_3_S_in ( p1116 ) , .clk_3_N_in ( p3164 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4241 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4242 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4243 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4244 ) ) ;
+sb_1__1_ sb_8__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4245 } ) ,
+ .chany_top_in ( cby_1__1__86_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__89_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__85_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__78_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__89_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__78_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__78_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__78_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p2520 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4246 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4247 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4248 ) ,
+ .pReset_W_in ( pResetWires[140] ) , .pReset_N_out ( pResetWires[142] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4249 ) ,
+ .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( p2520 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4250 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p2683 ) ,
+ .prog_clk_1_S_in ( p768 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4251 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4252 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[43] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4253 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4254 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4255 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[71] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4256 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4257 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p2211 ) ,
+ .prog_clk_3_E_in ( p487 ) , .prog_clk_3_S_in ( p533 ) ,
+ .prog_clk_3_N_in ( p667 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4258 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4259 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4260 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4261 ) , .clk_1_N_in ( p2481 ) ,
+ .clk_1_S_in ( p397 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4262 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4263 ) ,
+ .clk_2_N_in ( clk_3_wires[43] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4264 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4265 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4266 ) ,
+ .clk_2_W_out ( clk_2_wires[71] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4267 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4268 ) ,
+ .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p2211 ) ,
+ .clk_3_E_in ( p254 ) , .clk_3_S_in ( p2258 ) , .clk_3_N_in ( p2581 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4269 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4270 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4271 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4272 ) ) ;
+sb_1__1_ sb_8__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4273 } ) ,
+ .chany_top_in ( cby_1__1__87_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__90_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__86_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__79_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__90_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__79_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__79_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__79_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p3376 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4274 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4275 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4276 ) ,
+ .pReset_W_in ( pResetWires[189] ) , .pReset_N_out ( pResetWires[191] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4277 ) ,
+ .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( p3638 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4278 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p1396 ) ,
+ .prog_clk_1_S_in ( p235 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4279 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4280 ) ,
+ .prog_clk_2_N_in ( p1444 ) , .prog_clk_2_E_in ( p174 ) ,
+ .prog_clk_2_S_in ( p283 ) , .prog_clk_2_W_in ( p855 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4281 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4282 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4283 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4284 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4285 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4286 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4287 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[39] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4288 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4289 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4290 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p1444 ) ,
+ .clk_1_S_in ( p711 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4291 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4292 ) , .clk_2_N_in ( p1444 ) ,
+ .clk_2_E_in ( p691 ) , .clk_2_S_in ( p3628 ) , .clk_2_W_in ( p128 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4293 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4294 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4295 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4296 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4297 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4298 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4299 ) ,
+ .clk_3_N_in ( clk_3_wires[39] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4300 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4301 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4302 ) ,
+ .clk_3_S_out ( clk_3_wires[42] ) ) ;
+sb_1__1_ sb_8__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4303 } ) ,
+ .chany_top_in ( cby_1__1__88_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__91_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__87_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__80_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__91_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__80_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__80_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__80_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p2093 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4304 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4305 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4306 ) ,
+ .pReset_W_in ( pResetWires[238] ) , .pReset_N_out ( pResetWires[240] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4307 ) ,
+ .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( p2093 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4308 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p1883 ) ,
+ .prog_clk_1_S_in ( p1948 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4309 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4310 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[33] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4311 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4312 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4313 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[80] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4314 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4315 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[78] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4316 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4317 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4318 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[33] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4319 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4320 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4321 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p2212 ) ,
+ .clk_1_S_in ( p625 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4322 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4323 ) ,
+ .clk_2_N_in ( clk_3_wires[33] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4324 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4325 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4326 ) ,
+ .clk_2_W_out ( clk_2_wires[80] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4327 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4328 ) ,
+ .clk_2_E_out ( clk_2_wires[78] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4329 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4330 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4331 ) ,
+ .clk_3_N_in ( clk_3_wires[33] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4332 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4333 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4334 ) ,
+ .clk_3_S_out ( clk_3_wires[38] ) ) ;
+sb_1__1_ sb_8__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4335 } ) ,
+ .chany_top_in ( cby_1__1__89_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__92_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__88_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__81_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__92_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__81_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__81_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__81_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2443 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4336 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4337 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4338 ) ,
+ .pReset_W_in ( pResetWires[287] ) , .pReset_N_out ( pResetWires[289] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4339 ) ,
+ .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( p3434 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4340 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1227 ) ,
+ .prog_clk_1_S_in ( p142 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4341 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4342 ) ,
+ .prog_clk_2_N_in ( p1745 ) , .prog_clk_2_E_in ( p772 ) ,
+ .prog_clk_2_S_in ( p2296 ) , .prog_clk_2_W_in ( p505 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4343 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4344 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4345 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4346 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4347 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4348 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4349 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[29] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4350 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4351 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4352 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1446 ) ,
+ .clk_1_S_in ( p786 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4353 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4354 ) , .clk_2_N_in ( p1446 ) ,
+ .clk_2_E_in ( p591 ) , .clk_2_S_in ( p3390 ) , .clk_2_W_in ( p278 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4355 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4356 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4357 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4358 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4359 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4360 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4361 ) ,
+ .clk_3_N_in ( clk_3_wires[29] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4362 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4363 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4364 ) ,
+ .clk_3_S_out ( clk_3_wires[32] ) ) ;
+sb_1__1_ sb_8__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4365 } ) ,
+ .chany_top_in ( cby_1__1__90_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__93_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__89_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__82_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__93_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__82_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__82_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__82_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p2534 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4366 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4367 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4368 ) ,
+ .pReset_W_in ( pResetWires[336] ) , .pReset_N_out ( pResetWires[338] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4369 ) ,
+ .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( p2534 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4370 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1361 ) ,
+ .prog_clk_1_S_in ( p319 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4371 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4372 ) ,
+ .prog_clk_2_N_in ( p1385 ) , .prog_clk_2_E_in ( p335 ) ,
+ .prog_clk_2_S_in ( p38 ) , .prog_clk_2_W_in ( p132 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4373 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4374 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4375 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4376 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[5] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4377 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4378 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4379 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[44] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4380 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[26] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1361 ) ,
+ .clk_1_S_in ( p754 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4381 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4382 ) , .clk_2_N_in ( p1361 ) ,
+ .clk_2_E_in ( p706 ) , .clk_2_S_in ( p2307 ) , .clk_2_W_in ( p499 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4383 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4384 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4385 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4386 ) ,
+ .clk_3_W_in ( clk_3_wires[5] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4387 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4388 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4389 ) ,
+ .clk_3_E_out ( clk_3_wires[44] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4390 ) ,
+ .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) ) ;
+sb_1__1_ sb_8__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4391 } ) ,
+ .chany_top_in ( cby_1__1__91_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__94_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__90_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__83_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__94_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__83_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__83_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__83_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p2774 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4392 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4393 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4394 ) ,
+ .pReset_W_in ( pResetWires[385] ) , .pReset_N_out ( pResetWires[387] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4395 ) ,
+ .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( p3453 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4396 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1332 ) ,
+ .prog_clk_1_S_in ( p195 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4397 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4398 ) ,
+ .prog_clk_2_N_in ( p1795 ) , .prog_clk_2_E_in ( p426 ) ,
+ .prog_clk_2_S_in ( p1515 ) , .prog_clk_2_W_in ( p442 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4399 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4400 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4401 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4402 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4403 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4404 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[27] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4405 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4406 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4407 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[30] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_1_N_in ( p1795 ) ,
+ .clk_1_S_in ( p561 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4409 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_2_N_in ( p1795 ) ,
+ .clk_2_E_in ( p146 ) , .clk_2_S_in ( p3401 ) , .clk_2_W_in ( p157 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4411 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4412 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4413 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4414 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4415 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4416 ) ,
+ .clk_3_S_in ( clk_3_wires[27] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4417 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4418 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4419 ) ,
+ .clk_3_N_out ( clk_3_wires[30] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4420 ) ) ;
+sb_1__1_ sb_8__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4421 } ) ,
+ .chany_top_in ( cby_1__1__92_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__95_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__91_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__84_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__95_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__84_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__84_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__84_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p1752 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4422 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4423 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4424 ) ,
+ .pReset_W_in ( pResetWires[434] ) , .pReset_N_out ( pResetWires[436] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4425 ) ,
+ .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( p1752 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4426 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1235 ) ,
+ .prog_clk_1_S_in ( p1529 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4427 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4428 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4429 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4430 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[31] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4431 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[93] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4432 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4433 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[91] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4434 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4435 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[31] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4436 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4437 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4438 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[36] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_1_N_in ( p2529 ) ,
+ .clk_1_S_in ( p938 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4440 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4441 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4442 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4443 ) ,
+ .clk_2_S_in ( clk_3_wires[31] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4444 ) ,
+ .clk_2_W_out ( clk_2_wires[93] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4445 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4446 ) ,
+ .clk_2_E_out ( clk_2_wires[91] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4447 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4448 ) ,
+ .clk_3_S_in ( clk_3_wires[31] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4449 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4450 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4451 ) ,
+ .clk_3_N_out ( clk_3_wires[36] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4452 ) ) ;
+sb_1__1_ sb_8__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4453 } ) ,
+ .chany_top_in ( cby_1__1__93_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__96_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__92_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__85_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__96_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__85_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__85_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__85_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p3085 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4454 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4455 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4456 ) ,
+ .pReset_W_in ( pResetWires[483] ) , .pReset_N_out ( pResetWires[485] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4457 ) ,
+ .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( p3662 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4458 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1803 ) ,
+ .prog_clk_1_S_in ( p1078 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4459 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4460 ) ,
+ .prog_clk_2_N_in ( p3080 ) , .prog_clk_2_E_in ( p728 ) ,
+ .prog_clk_2_S_in ( p1527 ) , .prog_clk_2_W_in ( p646 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4461 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4462 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4463 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4464 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4465 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4466 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[37] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4467 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4468 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4469 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[40] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_1_N_in ( p1791 ) ,
+ .clk_1_S_in ( p120 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4471 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4472 ) , .clk_2_N_in ( p1791 ) ,
+ .clk_2_E_in ( p316 ) , .clk_2_S_in ( p3659 ) , .clk_2_W_in ( p94 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4473 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4474 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4475 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4476 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4477 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4478 ) ,
+ .clk_3_S_in ( clk_3_wires[37] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4479 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4480 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4481 ) ,
+ .clk_3_N_out ( clk_3_wires[40] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4482 ) ) ;
+sb_1__1_ sb_8__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4483 } ) ,
+ .chany_top_in ( cby_1__1__94_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__97_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__93_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__86_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__97_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__86_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__86_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__86_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p2732 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4484 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4485 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4486 ) ,
+ .pReset_W_in ( pResetWires[532] ) , .pReset_N_out ( pResetWires[534] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4487 ) ,
+ .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( p2732 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4488 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p1203 ) ,
+ .prog_clk_1_S_in ( p281 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4489 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4490 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4491 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4492 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[41] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4493 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[106] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4494 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4495 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p1739 ) ,
+ .prog_clk_3_E_in ( p815 ) , .prog_clk_3_S_in ( p21 ) ,
+ .prog_clk_3_N_in ( p595 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4496 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4497 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4498 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , .clk_1_N_in ( p2421 ) ,
+ .clk_1_S_in ( p839 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4500 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4501 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4502 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4503 ) ,
+ .clk_2_S_in ( clk_3_wires[41] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4504 ) ,
+ .clk_2_W_out ( clk_2_wires[106] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4505 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4506 ) ,
+ .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p1739 ) ,
+ .clk_3_E_in ( p320 ) , .clk_3_S_in ( p2596 ) , .clk_3_N_in ( p2323 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4507 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4508 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4509 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4510 ) ) ;
+sb_1__1_ sb_8__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4511 } ) ,
+ .chany_top_in ( cby_1__1__95_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__98_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__94_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__87_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__98_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__87_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__87_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__87_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p2946 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4512 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4513 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4514 ) ,
+ .pReset_W_in ( pResetWires[581] ) , .pReset_N_out ( pResetWires[583] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4515 ) ,
+ .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( p2946 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4516 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p1346 ) ,
+ .prog_clk_1_S_in ( p447 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4517 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4518 ) ,
+ .prog_clk_2_N_in ( p3577 ) , .prog_clk_2_E_in ( p899 ) ,
+ .prog_clk_2_S_in ( p353 ) , .prog_clk_2_W_in ( p3645 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4519 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4520 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4521 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4522 ) ,
+ .prog_clk_3_W_in ( p3647 ) , .prog_clk_3_E_in ( p238 ) ,
+ .prog_clk_3_S_in ( p769 ) , .prog_clk_3_N_in ( p3556 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4523 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4524 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4525 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_1_N_in ( p2739 ) ,
+ .clk_1_S_in ( p378 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4527 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , .clk_2_N_in ( p3362 ) ,
+ .clk_2_E_in ( p417 ) , .clk_2_S_in ( p2870 ) , .clk_2_W_in ( p3567 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4529 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4530 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4531 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4532 ) , .clk_3_W_in ( p3572 ) ,
+ .clk_3_E_in ( p894 ) , .clk_3_S_in ( p16 ) , .clk_3_N_in ( p3318 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4533 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4534 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4535 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4536 ) ) ;
+sb_1__1_ sb_9__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4537 } ) ,
+ .chany_top_in ( cby_1__1__97_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__99_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__96_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__88_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__99_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__88_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__88_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__88_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p2686 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4538 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4539 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4540 ) ,
+ .pReset_W_in ( pResetWires[95] ) , .pReset_N_out ( pResetWires[97] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4541 ) ,
+ .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( p2686 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4542 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[334] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[76] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4543 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[169] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3570 ) ,
+ .prog_clk_2_E_in ( p96 ) , .prog_clk_2_S_in ( p1105 ) ,
+ .prog_clk_2_W_in ( p3404 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4544 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4545 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4546 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4547 ) ,
+ .prog_clk_3_W_in ( p3420 ) , .prog_clk_3_E_in ( p988 ) ,
+ .prog_clk_3_S_in ( p360 ) , .prog_clk_3_N_in ( p3557 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4548 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4549 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4550 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4551 ) ,
+ .clk_1_N_in ( clk_2_wires[76] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4552 ) ,
+ .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) ,
+ .clk_2_N_in ( p2439 ) , .clk_2_E_in ( p886 ) , .clk_2_S_in ( p2624 ) ,
+ .clk_2_W_in ( p3169 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4553 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4554 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4555 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , .clk_3_W_in ( p3258 ) ,
+ .clk_3_E_in ( p604 ) , .clk_3_S_in ( p44 ) , .clk_3_N_in ( p2364 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4557 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4558 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4559 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4560 ) ) ;
+sb_1__1_ sb_9__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4561 } ) ,
+ .chany_top_in ( cby_1__1__98_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__100_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__97_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__89_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__100_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__89_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__89_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__89_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p2712 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4562 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4563 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4564 ) ,
+ .pReset_W_in ( pResetWires[144] ) , .pReset_N_out ( pResetWires[146] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4565 ) ,
+ .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( p2712 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4566 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p2096 ) ,
+ .prog_clk_1_S_in ( p136 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4567 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4568 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4569 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4570 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4571 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[70] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4572 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[75] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4573 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4574 ) ,
+ .prog_clk_3_W_in ( p1680 ) , .prog_clk_3_E_in ( p537 ) ,
+ .prog_clk_3_S_in ( p733 ) , .prog_clk_3_N_in ( p633 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4575 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4576 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4577 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4578 ) , .clk_1_N_in ( p2986 ) ,
+ .clk_1_S_in ( p866 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4579 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4580 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4581 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4582 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4583 ) ,
+ .clk_2_W_in ( clk_2_wires[70] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4584 ) ,
+ .clk_2_S_out ( clk_2_wires[75] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4585 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4586 ) , .clk_3_W_in ( p1680 ) ,
+ .clk_3_E_in ( p37 ) , .clk_3_S_in ( p2570 ) , .clk_3_N_in ( p2816 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4587 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4588 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4589 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4590 ) ) ;
+sb_1__1_ sb_9__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4591 } ) ,
+ .chany_top_in ( cby_1__1__99_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__101_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__98_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__90_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__101_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__90_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__90_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__90_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p2952 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4592 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4593 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4594 ) ,
+ .pReset_W_in ( pResetWires[193] ) , .pReset_N_out ( pResetWires[195] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4595 ) ,
+ .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( p2952 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4596 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[340] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[89] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4597 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[176] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p3336 ) ,
+ .prog_clk_2_E_in ( p974 ) , .prog_clk_2_S_in ( p955 ) ,
+ .prog_clk_2_W_in ( p3397 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4598 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4599 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4600 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4601 ) ,
+ .prog_clk_3_W_in ( p3455 ) , .prog_clk_3_E_in ( p1011 ) ,
+ .prog_clk_3_S_in ( p614 ) , .prog_clk_3_N_in ( p3303 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4602 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4603 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4604 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4605 ) ,
+ .clk_1_N_in ( clk_2_wires[89] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4606 ) ,
+ .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) ,
+ .clk_2_N_in ( p2232 ) , .clk_2_E_in ( p643 ) , .clk_2_S_in ( p2817 ) ,
+ .clk_2_W_in ( p3168 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4608 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4609 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , .clk_3_W_in ( p3282 ) ,
+ .clk_3_E_in ( p241 ) , .clk_3_S_in ( p1200 ) , .clk_3_N_in ( p1991 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4611 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4612 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4613 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4614 ) ) ;
+sb_1__1_ sb_9__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4615 } ) ,
+ .chany_top_in ( cby_1__1__100_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__102_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__99_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__91_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__102_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__91_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__91_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__91_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p1844 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4616 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4617 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4618 ) ,
+ .pReset_W_in ( pResetWires[242] ) , .pReset_N_out ( pResetWires[244] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4619 ) ,
+ .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( p1844 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4620 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p1438 ) ,
+ .prog_clk_1_S_in ( p921 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4621 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4622 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4623 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4624 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4625 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[79] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4626 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[88] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[86] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4627 ) ,
+ .prog_clk_3_W_in ( p1687 ) , .prog_clk_3_E_in ( p168 ) ,
+ .prog_clk_3_S_in ( p308 ) , .prog_clk_3_N_in ( p424 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4628 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4629 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4630 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_N_in ( p1837 ) ,
+ .clk_1_S_in ( p46 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4632 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4633 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4634 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4635 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4636 ) ,
+ .clk_2_W_in ( clk_2_wires[79] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4637 ) ,
+ .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4638 ) , .clk_3_W_in ( p1684 ) ,
+ .clk_3_E_in ( p690 ) , .clk_3_S_in ( p1530 ) , .clk_3_N_in ( p1484 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4639 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4640 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4641 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4642 ) ) ;
+sb_1__1_ sb_9__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4643 } ) ,
+ .chany_top_in ( cby_1__1__101_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__103_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__100_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__92_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__103_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__92_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__92_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__92_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p1146 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4644 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4645 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4646 ) ,
+ .pReset_W_in ( pResetWires[291] ) , .pReset_N_out ( pResetWires[293] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4647 ) ,
+ .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( p1146 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4648 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[346] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4649 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[87] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[183] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p2532 ) ,
+ .prog_clk_2_E_in ( p1044 ) , .prog_clk_2_S_in ( p879 ) ,
+ .prog_clk_2_W_in ( p1483 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4650 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4651 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4652 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4653 ) ,
+ .prog_clk_3_W_in ( p1855 ) , .prog_clk_3_E_in ( p41 ) ,
+ .prog_clk_3_S_in ( p494 ) , .prog_clk_3_N_in ( p2361 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4654 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4655 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4656 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4657 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4658 ) ,
+ .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) ,
+ .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p2672 ) ,
+ .clk_2_E_in ( p1027 ) , .clk_2_S_in ( p274 ) , .clk_2_W_in ( p2325 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4659 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4660 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4661 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , .clk_3_W_in ( p2352 ) ,
+ .clk_3_E_in ( p555 ) , .clk_3_S_in ( p997 ) , .clk_3_N_in ( p2642 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4663 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4664 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4665 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4666 ) ) ;
+sb_1__1_ sb_9__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4667 } ) ,
+ .chany_top_in ( cby_1__1__102_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__104_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__101_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__93_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__104_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__93_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__93_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__93_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p3532 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4668 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4669 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4670 ) ,
+ .pReset_W_in ( pResetWires[340] ) , .pReset_N_out ( pResetWires[342] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4671 ) ,
+ .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( p3625 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4672 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p896 ) ,
+ .prog_clk_1_S_in ( p252 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4673 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4674 ) ,
+ .prog_clk_2_N_in ( p1187 ) , .prog_clk_2_E_in ( p763 ) ,
+ .prog_clk_2_S_in ( p681 ) , .prog_clk_2_W_in ( p1566 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4675 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4676 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4677 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4678 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[45] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4679 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4680 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4681 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[48] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4682 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4683 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_1_N_in ( p1187 ) ,
+ .clk_1_S_in ( p701 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4685 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4686 ) , .clk_2_N_in ( p1187 ) ,
+ .clk_2_E_in ( p221 ) , .clk_2_S_in ( p3610 ) , .clk_2_W_in ( p1478 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4687 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4688 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4689 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4690 ) ,
+ .clk_3_W_in ( clk_3_wires[45] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4691 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4692 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4693 ) ,
+ .clk_3_E_out ( clk_3_wires[48] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4694 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4695 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4696 ) ) ;
+sb_1__1_ sb_9__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4697 } ) ,
+ .chany_top_in ( cby_1__1__103_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__105_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__102_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__94_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__105_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__94_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__94_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__94_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p2790 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4698 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4699 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4700 ) ,
+ .pReset_W_in ( pResetWires[389] ) , .pReset_N_out ( pResetWires[391] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4701 ) ,
+ .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( p2790 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4702 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[352] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[102] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4703 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[190] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p3534 ) ,
+ .prog_clk_2_E_in ( p699 ) , .prog_clk_2_S_in ( p349 ) ,
+ .prog_clk_2_W_in ( p3564 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4704 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4705 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4706 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4707 ) ,
+ .prog_clk_3_W_in ( p3582 ) , .prog_clk_3_E_in ( p65 ) ,
+ .prog_clk_3_S_in ( p631 ) , .prog_clk_3_N_in ( p3525 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4708 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4709 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4710 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4711 ) ,
+ .clk_1_N_in ( clk_2_wires[102] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4712 ) ,
+ .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) ,
+ .clk_2_N_in ( p3155 ) , .clk_2_E_in ( p964 ) , .clk_2_S_in ( p2608 ) ,
+ .clk_2_W_in ( p2856 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4713 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4714 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4715 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4716 ) , .clk_3_W_in ( p2991 ) ,
+ .clk_3_E_in ( p910 ) , .clk_3_S_in ( p937 ) , .clk_3_N_in ( p3065 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4717 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4718 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4719 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4720 ) ) ;
+sb_1__1_ sb_9__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4721 } ) ,
+ .chany_top_in ( cby_1__1__104_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__106_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__103_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__95_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__106_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__95_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__95_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__95_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p3088 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4722 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4723 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4724 ) ,
+ .pReset_W_in ( pResetWires[438] ) , .pReset_N_out ( pResetWires[440] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4725 ) ,
+ .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( p3088 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4726 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p1659 ) ,
+ .prog_clk_1_S_in ( p504 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4727 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4728 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4729 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4730 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4731 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[92] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4732 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[101] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[99] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4733 ) ,
+ .prog_clk_3_W_in ( p1386 ) , .prog_clk_3_E_in ( p104 ) ,
+ .prog_clk_3_S_in ( p758 ) , .prog_clk_3_N_in ( p1583 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4734 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4735 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4736 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_1_N_in ( p2508 ) ,
+ .clk_1_S_in ( p784 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4738 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4739 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4740 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4741 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4742 ) ,
+ .clk_2_W_in ( clk_2_wires[92] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4743 ) ,
+ .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , .clk_3_W_in ( p1386 ) ,
+ .clk_3_E_in ( p568 ) , .clk_3_S_in ( p3027 ) , .clk_3_N_in ( p2309 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4745 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4746 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4747 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4748 ) ) ;
+sb_1__1_ sb_9__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4749 } ) ,
+ .chany_top_in ( cby_1__1__105_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__107_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__104_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__96_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__107_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__96_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__96_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__96_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p3242 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4750 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4751 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4752 ) ,
+ .pReset_W_in ( pResetWires[487] ) , .pReset_N_out ( pResetWires[489] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4753 ) ,
+ .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( p3242 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4754 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[358] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4755 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[100] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[197] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3492 ) ,
+ .prog_clk_2_E_in ( p379 ) , .prog_clk_2_S_in ( p1122 ) ,
+ .prog_clk_2_W_in ( p3633 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4756 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4757 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4758 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4759 ) ,
+ .prog_clk_3_W_in ( p3639 ) , .prog_clk_3_E_in ( p1028 ) ,
+ .prog_clk_3_S_in ( p462 ) , .prog_clk_3_N_in ( p3481 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4760 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4761 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4762 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4763 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4764 ) ,
+ .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) ,
+ .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p3550 ) ,
+ .clk_2_E_in ( p846 ) , .clk_2_S_in ( p3178 ) , .clk_2_W_in ( p1470 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4765 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4766 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4767 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4768 ) , .clk_3_W_in ( p1820 ) ,
+ .clk_3_E_in ( p285 ) , .clk_3_S_in ( p1112 ) , .clk_3_N_in ( p3521 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4769 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4770 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4771 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4772 ) ) ;
+sb_1__1_ sb_9__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4773 } ) ,
+ .chany_top_in ( cby_1__1__106_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__108_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__105_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__97_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__108_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__97_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__97_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__97_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p2730 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4774 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4775 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4776 ) ,
+ .pReset_W_in ( pResetWires[536] ) , .pReset_N_out ( pResetWires[538] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4777 ) ,
+ .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( p2730 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4778 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p1578 ) ,
+ .prog_clk_1_S_in ( p523 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4779 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4780 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4781 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4782 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4783 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[105] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4784 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4785 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[110] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4786 ) ,
+ .prog_clk_3_W_in ( p1702 ) , .prog_clk_3_E_in ( p375 ) ,
+ .prog_clk_3_S_in ( p669 ) , .prog_clk_3_N_in ( p1941 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4787 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4788 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4789 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , .clk_1_N_in ( p3090 ) ,
+ .clk_1_S_in ( p340 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4791 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4792 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4793 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4794 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4795 ) ,
+ .clk_2_W_in ( clk_2_wires[105] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4796 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4797 ) ,
+ .clk_2_N_out ( clk_2_wires[110] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4798 ) , .clk_3_W_in ( p1702 ) ,
+ .clk_3_E_in ( p680 ) , .clk_3_S_in ( p2600 ) , .clk_3_N_in ( p3033 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4799 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4800 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4801 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4802 ) ) ;
+sb_1__1_ sb_9__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4803 } ) ,
+ .chany_top_in ( cby_1__1__107_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__109_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__106_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__98_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__109_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__98_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__98_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__98_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2509 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4804 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4805 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4806 ) ,
+ .pReset_W_in ( pResetWires[585] ) , .pReset_N_out ( pResetWires[587] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4807 ) ,
+ .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( p2509 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4808 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[364] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4809 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[111] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[204] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p3678 ) ,
+ .prog_clk_2_E_in ( p180 ) , .prog_clk_2_S_in ( p125 ) ,
+ .prog_clk_2_W_in ( p3210 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4810 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4811 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4812 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4813 ) ,
+ .prog_clk_3_W_in ( p3267 ) , .prog_clk_3_E_in ( p1140 ) ,
+ .prog_clk_3_S_in ( p674 ) , .prog_clk_3_N_in ( p3677 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4814 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4815 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4816 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4817 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4818 ) ,
+ .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) ,
+ .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p2929 ) ,
+ .clk_2_E_in ( p813 ) , .clk_2_S_in ( p2270 ) , .clk_2_W_in ( p3175 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4819 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4820 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4821 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , .clk_3_W_in ( p3272 ) ,
+ .clk_3_E_in ( p412 ) , .clk_3_S_in ( p317 ) , .clk_3_N_in ( p2874 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4823 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4824 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4825 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4826 ) ) ;
+sb_1__1_ sb_10__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4827 } ) ,
+ .chany_top_in ( cby_1__1__109_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__110_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__108_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__99_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__110_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__99_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__99_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__99_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p3451 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4828 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4829 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4830 ) ,
+ .pReset_W_in ( pResetWires[99] ) , .pReset_N_out ( pResetWires[101] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4831 ) ,
+ .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( p3451 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4832 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p2108 ) ,
+ .prog_clk_1_S_in ( p326 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4833 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4834 ) ,
+ .prog_clk_2_N_in ( p3360 ) , .prog_clk_2_E_in ( p230 ) ,
+ .prog_clk_2_S_in ( p27 ) , .prog_clk_2_W_in ( p3383 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4835 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4836 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4837 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4838 ) ,
+ .prog_clk_3_W_in ( p3439 ) , .prog_clk_3_E_in ( p1126 ) ,
+ .prog_clk_3_S_in ( p1007 ) , .prog_clk_3_N_in ( p3327 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4839 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4840 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4841 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_1_N_in ( p2215 ) ,
+ .clk_1_S_in ( p905 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4843 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4844 ) , .clk_2_N_in ( p3371 ) ,
+ .clk_2_E_in ( p870 ) , .clk_2_S_in ( p3389 ) , .clk_2_W_in ( p3003 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4845 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4846 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4847 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4848 ) , .clk_3_W_in ( p3084 ) ,
+ .clk_3_E_in ( p804 ) , .clk_3_S_in ( p946 ) , .clk_3_N_in ( p3292 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4849 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4850 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4851 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4852 ) ) ;
+sb_1__1_ sb_10__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4853 } ) ,
+ .chany_top_in ( cby_1__1__110_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__111_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__109_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__100_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__111_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__100_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__100_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__100_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p1878 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4854 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4855 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4856 ) ,
+ .pReset_W_in ( pResetWires[148] ) , .pReset_N_out ( pResetWires[150] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4857 ) ,
+ .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( p1878 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4858 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p2142 ) ,
+ .prog_clk_1_S_in ( p400 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4859 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4860 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[87] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4861 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4862 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4863 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4864 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4865 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4866 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p1597 ) ,
+ .prog_clk_3_E_in ( p1601 ) , .prog_clk_3_S_in ( p737 ) ,
+ .prog_clk_3_N_in ( p481 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4867 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4868 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4869 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4870 ) , .clk_1_N_in ( p2982 ) ,
+ .clk_1_S_in ( p798 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4871 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4872 ) ,
+ .clk_2_N_in ( clk_3_wires[87] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4873 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4874 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4875 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4876 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4877 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4878 ) ,
+ .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p1597 ) ,
+ .clk_3_E_in ( p1528 ) , .clk_3_S_in ( p1580 ) , .clk_3_N_in ( p2807 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4879 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4880 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4881 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4882 ) ) ;
+sb_1__1_ sb_10__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4883 } ) ,
+ .chany_top_in ( cby_1__1__111_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__112_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__110_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__101_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__112_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__101_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__101_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__101_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p2408 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4884 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4885 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4886 ) ,
+ .pReset_W_in ( pResetWires[197] ) , .pReset_N_out ( pResetWires[199] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4887 ) ,
+ .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( p2497 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4888 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1291 ) ,
+ .prog_clk_1_S_in ( p383 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4889 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4890 ) ,
+ .prog_clk_2_N_in ( p1812 ) , .prog_clk_2_E_in ( p242 ) ,
+ .prog_clk_2_S_in ( p1581 ) , .prog_clk_2_W_in ( p25 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4891 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4892 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4893 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4894 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4895 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4896 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4897 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[83] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4898 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4899 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4900 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1812 ) ,
+ .clk_1_S_in ( p697 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4901 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4902 ) , .clk_2_N_in ( p1812 ) ,
+ .clk_2_E_in ( p796 ) , .clk_2_S_in ( p2314 ) , .clk_2_W_in ( p491 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4903 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4904 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4905 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4906 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4907 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4908 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4909 ) ,
+ .clk_3_N_in ( clk_3_wires[83] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4910 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4911 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4912 ) ,
+ .clk_3_S_out ( clk_3_wires[86] ) ) ;
+sb_1__1_ sb_10__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4913 } ) ,
+ .chany_top_in ( cby_1__1__112_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__113_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__111_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__102_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__113_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__102_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__102_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__102_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1846 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4914 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4915 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4916 ) ,
+ .pReset_W_in ( pResetWires[246] ) , .pReset_N_out ( pResetWires[248] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4917 ) ,
+ .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( p1760 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4918 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1370 ) ,
+ .prog_clk_1_S_in ( p1468 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4919 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4920 ) ,
+ .prog_clk_2_N_in ( prog_clk_3_wires[77] ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4921 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4922 ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4923 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4924 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4925 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4926 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[119] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4927 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4928 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4929 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[77] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4930 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4931 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4932 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p2474 ) ,
+ .clk_1_S_in ( p961 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4933 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4934 ) ,
+ .clk_2_N_in ( clk_3_wires[77] ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4935 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4936 ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4937 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4938 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4939 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4940 ) ,
+ .clk_2_E_out ( clk_2_wires[119] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4941 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4942 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4943 ) ,
+ .clk_3_N_in ( clk_3_wires[77] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4944 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4945 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4946 ) ,
+ .clk_3_S_out ( clk_3_wires[82] ) ) ;
+sb_1__1_ sb_10__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4947 } ) ,
+ .chany_top_in ( cby_1__1__113_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__114_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__112_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__103_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__114_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__103_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__103_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__103_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p2145 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4948 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4949 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4950 ) ,
+ .pReset_W_in ( pResetWires[295] ) , .pReset_N_out ( pResetWires[297] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4951 ) ,
+ .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( p2145 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4952 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p1842 ) ,
+ .prog_clk_1_S_in ( p137 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4953 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4954 ) ,
+ .prog_clk_2_N_in ( p1774 ) , .prog_clk_2_E_in ( p915 ) ,
+ .prog_clk_2_S_in ( p1550 ) , .prog_clk_2_W_in ( p54 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4955 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4956 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4957 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4958 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4959 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4960 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4961 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[73] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4962 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4963 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4964 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p1774 ) ,
+ .clk_1_S_in ( p1101 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4965 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4966 ) , .clk_2_N_in ( p1663 ) ,
+ .clk_2_E_in ( p115 ) , .clk_2_S_in ( p1933 ) , .clk_2_W_in ( p755 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4967 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4968 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4969 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4970 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4971 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4972 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4973 ) ,
+ .clk_3_N_in ( clk_3_wires[73] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4974 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4975 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4976 ) ,
+ .clk_3_S_out ( clk_3_wires[76] ) ) ;
+sb_1__1_ sb_10__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_4977 } ) ,
+ .chany_top_in ( cby_1__1__114_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__115_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__113_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__104_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__115_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__104_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__104_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__104_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p3157 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4978 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_4979 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_4980 ) ,
+ .pReset_W_in ( pResetWires[344] ) , .pReset_N_out ( pResetWires[346] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_4981 ) ,
+ .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( p3157 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_4982 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1251 ) ,
+ .prog_clk_1_S_in ( p194 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4983 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4984 ) ,
+ .prog_clk_2_N_in ( p1358 ) , .prog_clk_2_E_in ( p811 ) ,
+ .prog_clk_2_S_in ( p1506 ) , .prog_clk_2_W_in ( p1497 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4985 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4986 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4987 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4988 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[49] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4989 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4990 ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4991 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4992 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4993 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[70] ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1358 ) ,
+ .clk_1_S_in ( p1054 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4994 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4995 ) , .clk_2_N_in ( p1358 ) ,
+ .clk_2_E_in ( p239 ) , .clk_2_S_in ( p3001 ) , .clk_2_W_in ( p1644 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4996 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4997 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4998 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4999 ) ,
+ .clk_3_W_in ( clk_3_wires[49] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5000 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5001 ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5002 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5003 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5004 ) ,
+ .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) ) ;
+sb_1__1_ sb_10__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5005 } ) ,
+ .chany_top_in ( cby_1__1__115_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__116_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__114_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__105_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__116_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__105_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__105_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__105_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p2798 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5006 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5007 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5008 ) ,
+ .pReset_W_in ( pResetWires[393] ) , .pReset_N_out ( pResetWires[395] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5009 ) ,
+ .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( p3115 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5010 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1215 ) ,
+ .prog_clk_1_S_in ( p1113 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5011 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5012 ) ,
+ .prog_clk_2_N_in ( p1343 ) , .prog_clk_2_E_in ( p257 ) ,
+ .prog_clk_2_S_in ( p1508 ) , .prog_clk_2_W_in ( p346 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5013 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5014 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5015 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5016 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5017 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5018 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[71] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5019 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5020 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5021 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[74] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_1_N_in ( p1343 ) ,
+ .clk_1_S_in ( p434 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5023 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5024 ) , .clk_2_N_in ( p1343 ) ,
+ .clk_2_E_in ( p444 ) , .clk_2_S_in ( p3004 ) , .clk_2_W_in ( p425 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5025 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5026 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5027 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5028 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5029 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5030 ) ,
+ .clk_3_S_in ( clk_3_wires[71] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5031 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5032 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5033 ) ,
+ .clk_3_N_out ( clk_3_wires[74] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5034 ) ) ;
+sb_1__1_ sb_10__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5035 } ) ,
+ .chany_top_in ( cby_1__1__116_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__117_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__115_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__106_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__117_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__106_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__106_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__106_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p2141 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5036 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5037 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5038 ) ,
+ .pReset_W_in ( pResetWires[442] ) , .pReset_N_out ( pResetWires[444] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5039 ) ,
+ .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( p2141 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5040 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p1147 ) ,
+ .prog_clk_1_S_in ( p1955 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5041 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5042 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5043 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5044 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[75] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5045 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5046 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5047 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5048 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[126] ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5049 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5050 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[75] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5051 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5052 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5053 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[80] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5054 ) , .clk_1_N_in ( p2414 ) ,
+ .clk_1_S_in ( p659 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5055 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5056 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5057 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5058 ) ,
+ .clk_2_S_in ( clk_3_wires[75] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5059 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5060 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5061 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5062 ) ,
+ .clk_2_E_out ( clk_2_wires[126] ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5063 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5064 ) ,
+ .clk_3_S_in ( clk_3_wires[75] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5065 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5066 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5067 ) ,
+ .clk_3_N_out ( clk_3_wires[80] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5068 ) ) ;
+sb_1__1_ sb_10__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5069 } ) ,
+ .chany_top_in ( cby_1__1__117_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__118_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__116_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__107_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__118_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__107_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__107_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__107_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p2917 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5070 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5071 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5072 ) ,
+ .pReset_W_in ( pResetWires[491] ) , .pReset_N_out ( pResetWires[493] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5073 ) ,
+ .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( p2917 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5074 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p1441 ) ,
+ .prog_clk_1_S_in ( p616 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5075 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5076 ) ,
+ .prog_clk_2_N_in ( p1723 ) , .prog_clk_2_E_in ( p704 ) ,
+ .prog_clk_2_S_in ( p232 ) , .prog_clk_2_W_in ( p147 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5077 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5078 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5079 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5080 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5081 ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5082 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[81] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5083 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5084 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5085 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[84] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_1_N_in ( p1723 ) ,
+ .clk_1_S_in ( p314 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5087 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5088 ) , .clk_2_N_in ( p1723 ) ,
+ .clk_2_E_in ( p216 ) , .clk_2_S_in ( p2847 ) , .clk_2_W_in ( p793 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5089 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5090 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5091 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5092 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5093 ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5094 ) ,
+ .clk_3_S_in ( clk_3_wires[81] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5095 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5096 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5097 ) ,
+ .clk_3_N_out ( clk_3_wires[84] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5098 ) ) ;
+sb_1__1_ sb_10__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5099 } ) ,
+ .chany_top_in ( cby_1__1__118_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__119_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__117_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__108_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__119_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__108_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__108_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__108_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p2217 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5100 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5101 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5102 ) ,
+ .pReset_W_in ( pResetWires[540] ) , .pReset_N_out ( pResetWires[542] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5103 ) ,
+ .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( p2217 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5104 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p835 ) ,
+ .prog_clk_1_S_in ( p640 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5105 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5106 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5107 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5108 ) ,
+ .prog_clk_2_S_in ( prog_clk_3_wires[85] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5109 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5110 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5111 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5112 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p873 ) ,
+ .prog_clk_3_E_in ( p1969 ) , .prog_clk_3_S_in ( p362 ) ,
+ .prog_clk_3_N_in ( p53 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5113 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5114 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5115 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5116 ) , .clk_1_N_in ( p1731 ) ,
+ .clk_1_S_in ( p150 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5117 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5118 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5119 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5120 ) ,
+ .clk_2_S_in ( clk_3_wires[85] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5121 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5122 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5123 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5124 ) ,
+ .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1406 ) ,
+ .clk_3_E_in ( p2025 ) , .clk_3_S_in ( p1918 ) , .clk_3_N_in ( p1587 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5125 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5126 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5127 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5128 ) ) ;
+sb_1__1_ sb_10__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5129 } ) ,
+ .chany_top_in ( cby_1__1__119_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__120_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__118_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__109_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__120_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__109_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__109_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__109_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p3101 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5130 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5131 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5132 ) ,
+ .pReset_W_in ( pResetWires[589] ) , .pReset_N_out ( pResetWires[591] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5133 ) ,
+ .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( p3381 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5134 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p2161 ) ,
+ .prog_clk_1_S_in ( p580 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5135 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5136 ) ,
+ .prog_clk_2_N_in ( p2519 ) , .prog_clk_2_E_in ( p1174 ) ,
+ .prog_clk_2_S_in ( p1000 ) , .prog_clk_2_W_in ( p3472 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5137 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5138 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5139 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5140 ) ,
+ .prog_clk_3_W_in ( p3489 ) , .prog_clk_3_E_in ( p207 ) ,
+ .prog_clk_3_S_in ( p131 ) , .prog_clk_3_N_in ( p2324 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5141 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5142 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5143 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_1_N_in ( p3114 ) ,
+ .clk_1_S_in ( p685 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5145 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , .clk_2_N_in ( p2153 ) ,
+ .clk_2_E_in ( p994 ) , .clk_2_S_in ( p3325 ) , .clk_2_W_in ( p3030 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5147 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5148 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5149 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , .clk_3_W_in ( p3135 ) ,
+ .clk_3_E_in ( p551 ) , .clk_3_S_in ( p525 ) , .clk_3_N_in ( p3016 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5151 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5152 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5153 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5154 ) ) ;
+sb_1__1_ sb_11__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5155 } ) ,
+ .chany_top_in ( cby_1__1__121_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__121_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__120_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__110_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__121_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__110_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__110_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__110_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p2959 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5156 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5157 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5158 ) ,
+ .pReset_W_in ( pResetWires[103] ) , .pReset_N_out ( pResetWires[105] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5159 ) ,
+ .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( p2959 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5160 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[410] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[116] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5161 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[211] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3548 ) ,
+ .prog_clk_2_E_in ( p956 ) , .prog_clk_2_S_in ( p829 ) ,
+ .prog_clk_2_W_in ( p3467 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5162 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5163 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5164 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5165 ) ,
+ .prog_clk_3_W_in ( p3486 ) , .prog_clk_3_E_in ( p261 ) ,
+ .prog_clk_3_S_in ( p384 ) , .prog_clk_3_N_in ( p3511 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5166 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5167 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5168 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5169 ) ,
+ .clk_1_N_in ( clk_2_wires[116] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5170 ) ,
+ .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) ,
+ .clk_2_N_in ( p3600 ) , .clk_2_E_in ( p579 ) , .clk_2_S_in ( p2840 ) ,
+ .clk_2_W_in ( p3410 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5171 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5172 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5173 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5174 ) , .clk_3_W_in ( p3448 ) ,
+ .clk_3_E_in ( p720 ) , .clk_3_S_in ( p1042 ) , .clk_3_N_in ( p3590 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5175 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5176 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5177 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5178 ) ) ;
+sb_1__1_ sb_11__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5179 } ) ,
+ .chany_top_in ( cby_1__1__122_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__122_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__121_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__111_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__122_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__111_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__111_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__111_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p1401 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5180 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5181 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5182 ) ,
+ .pReset_W_in ( pResetWires[152] ) , .pReset_N_out ( pResetWires[154] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5183 ) ,
+ .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( p1401 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5184 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p1697 ) ,
+ .prog_clk_1_S_in ( p1087 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5185 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5186 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5187 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5188 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5189 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[113] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5190 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[115] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5191 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5192 ) ,
+ .prog_clk_3_W_in ( p2146 ) , .prog_clk_3_E_in ( p623 ) ,
+ .prog_clk_3_S_in ( p112 ) , .prog_clk_3_N_in ( p536 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5193 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5194 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5195 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5196 ) , .clk_1_N_in ( p2789 ) ,
+ .clk_1_S_in ( p295 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5197 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5198 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5199 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5200 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5201 ) ,
+ .clk_2_W_in ( clk_2_wires[113] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5202 ) ,
+ .clk_2_S_out ( clk_2_wires[115] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5203 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5204 ) , .clk_3_W_in ( p2146 ) ,
+ .clk_3_E_in ( p309 ) , .clk_3_S_in ( p517 ) , .clk_3_N_in ( p2609 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5205 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5206 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5207 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5208 ) ) ;
+sb_1__1_ sb_11__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5209 } ) ,
+ .chany_top_in ( cby_1__1__123_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__123_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__122_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__112_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__123_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__112_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__112_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__112_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p3139 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5210 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5211 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5212 ) ,
+ .pReset_W_in ( pResetWires[201] ) , .pReset_N_out ( pResetWires[203] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5213 ) ,
+ .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( p3254 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5214 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[416] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[123] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5215 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[218] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3635 ) ,
+ .prog_clk_2_E_in ( p3 ) , .prog_clk_2_S_in ( p1061 ) ,
+ .prog_clk_2_W_in ( p3288 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5216 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5217 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5218 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5219 ) ,
+ .prog_clk_3_W_in ( p3375 ) , .prog_clk_3_E_in ( p914 ) ,
+ .prog_clk_3_S_in ( p390 ) , .prog_clk_3_N_in ( p3627 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5220 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5221 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5222 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5223 ) ,
+ .clk_1_N_in ( clk_2_wires[123] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5224 ) ,
+ .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) ,
+ .clk_2_N_in ( p3087 ) , .clk_2_E_in ( p912 ) , .clk_2_S_in ( p3179 ) ,
+ .clk_2_W_in ( p3328 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5225 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5226 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5227 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , .clk_3_W_in ( p3378 ) ,
+ .clk_3_E_in ( p887 ) , .clk_3_S_in ( p928 ) , .clk_3_N_in ( p3018 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5229 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5230 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5231 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5232 ) ) ;
+sb_1__1_ sb_11__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5233 } ) ,
+ .chany_top_in ( cby_1__1__124_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__124_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__123_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__113_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__124_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__113_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__113_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__113_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p1875 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5234 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5235 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5236 ) ,
+ .pReset_W_in ( pResetWires[250] ) , .pReset_N_out ( pResetWires[252] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5237 ) ,
+ .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( p1875 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5238 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p2193 ) ,
+ .prog_clk_1_S_in ( p208 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5239 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5240 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5241 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5242 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5243 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[118] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5244 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[122] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[120] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5245 ) ,
+ .prog_clk_3_W_in ( p1665 ) , .prog_clk_3_E_in ( p178 ) ,
+ .prog_clk_3_S_in ( p535 ) , .prog_clk_3_N_in ( p1562 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5246 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5247 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5248 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_N_in ( p2709 ) ,
+ .clk_1_S_in ( p1005 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5250 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5251 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5252 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5253 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5254 ) ,
+ .clk_2_W_in ( clk_2_wires[118] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5255 ) ,
+ .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5256 ) , .clk_3_W_in ( p1665 ) ,
+ .clk_3_E_in ( p717 ) , .clk_3_S_in ( p1509 ) , .clk_3_N_in ( p2602 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5257 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5258 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5259 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5260 ) ) ;
+sb_1__1_ sb_11__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5261 } ) ,
+ .chany_top_in ( cby_1__1__125_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__125_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__124_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__114_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__125_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__114_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__114_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__114_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p2227 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5262 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5263 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5264 ) ,
+ .pReset_W_in ( pResetWires[299] ) , .pReset_N_out ( pResetWires[301] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5265 ) ,
+ .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( p2997 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5266 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[422] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5267 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[121] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[225] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p3111 ) ,
+ .prog_clk_2_E_in ( p750 ) , .prog_clk_2_S_in ( p562 ) ,
+ .prog_clk_2_W_in ( p2594 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5268 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5269 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5270 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5271 ) ,
+ .prog_clk_3_W_in ( p2680 ) , .prog_clk_3_E_in ( p286 ) ,
+ .prog_clk_3_S_in ( p951 ) , .prog_clk_3_N_in ( p3054 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5272 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5273 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5274 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5275 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5276 ) ,
+ .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) ,
+ .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p2666 ) ,
+ .clk_2_E_in ( p859 ) , .clk_2_S_in ( p2850 ) , .clk_2_W_in ( p2353 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5277 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5278 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5279 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_W_in ( p2448 ) ,
+ .clk_3_E_in ( p87 ) , .clk_3_S_in ( p1033 ) , .clk_3_N_in ( p2610 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5281 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5282 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5283 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5284 ) ) ;
+sb_1__1_ sb_11__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5285 } ) ,
+ .chany_top_in ( cby_1__1__126_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__126_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__125_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__115_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__126_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__115_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__115_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__115_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2397 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5286 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5287 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5288 ) ,
+ .pReset_W_in ( pResetWires[348] ) , .pReset_N_out ( pResetWires[350] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5289 ) ,
+ .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( p2397 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5290 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p1843 ) ,
+ .prog_clk_1_S_in ( p553 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5291 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5292 ) ,
+ .prog_clk_2_N_in ( p3281 ) , .prog_clk_2_E_in ( p693 ) ,
+ .prog_clk_2_S_in ( p1196 ) , .prog_clk_2_W_in ( p3527 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5293 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5294 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5295 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5296 ) ,
+ .prog_clk_3_W_in ( p3549 ) , .prog_clk_3_E_in ( p395 ) ,
+ .prog_clk_3_S_in ( p212 ) , .prog_clk_3_N_in ( p3208 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5297 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5298 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5299 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_1_N_in ( p2401 ) ,
+ .clk_1_S_in ( p823 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5301 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5302 ) , .clk_2_N_in ( p3601 ) ,
+ .clk_2_E_in ( p600 ) , .clk_2_S_in ( p2288 ) , .clk_2_W_in ( p3035 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5303 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5304 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5305 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , .clk_3_W_in ( p3150 ) ,
+ .clk_3_E_in ( p219 ) , .clk_3_S_in ( p780 ) , .clk_3_N_in ( p3587 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5307 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5308 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5309 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5310 ) ) ;
+sb_1__1_ sb_11__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5311 } ) ,
+ .chany_top_in ( cby_1__1__127_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__127_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__126_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__116_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__127_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__116_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__116_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__116_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p1036 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5312 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5313 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5314 ) ,
+ .pReset_W_in ( pResetWires[397] ) , .pReset_N_out ( pResetWires[399] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5315 ) ,
+ .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( p2937 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5316 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[428] ) ,
+ .prog_clk_1_N_in ( prog_clk_2_wires[130] ) ,
+ .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5317 ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[232] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3431 ) ,
+ .prog_clk_2_E_in ( p86 ) , .prog_clk_2_S_in ( p1057 ) ,
+ .prog_clk_2_W_in ( p3591 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5318 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5319 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5320 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5321 ) ,
+ .prog_clk_3_W_in ( p3602 ) , .prog_clk_3_E_in ( p960 ) ,
+ .prog_clk_3_S_in ( p297 ) , .prog_clk_3_N_in ( p3415 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5322 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5323 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5324 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5325 ) ,
+ .clk_1_N_in ( clk_2_wires[130] ) ,
+ .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5326 ) ,
+ .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) ,
+ .clk_2_N_in ( p3576 ) , .clk_2_E_in ( p635 ) , .clk_2_S_in ( p2843 ) ,
+ .clk_2_W_in ( p2008 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5327 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5328 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5329 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_3_W_in ( p2106 ) ,
+ .clk_3_E_in ( p730 ) , .clk_3_S_in ( p985 ) , .clk_3_N_in ( p3555 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5331 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5332 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5333 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5334 ) ) ;
+sb_1__1_ sb_11__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5335 } ) ,
+ .chany_top_in ( cby_1__1__128_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__128_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__127_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__117_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__128_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__117_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__117_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__117_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p2492 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5336 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5337 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5338 ) ,
+ .pReset_W_in ( pResetWires[446] ) , .pReset_N_out ( pResetWires[448] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5339 ) ,
+ .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( p2492 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5340 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p1117 ) ,
+ .prog_clk_1_S_in ( p857 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5341 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5342 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5343 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5344 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5345 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[125] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5346 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[129] ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[127] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5347 ) ,
+ .prog_clk_3_W_in ( p1811 ) , .prog_clk_3_E_in ( p474 ) ,
+ .prog_clk_3_S_in ( p315 ) , .prog_clk_3_N_in ( p511 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5348 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5349 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5350 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5351 ) , .clk_1_N_in ( p1403 ) ,
+ .clk_1_S_in ( p70 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5352 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5353 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5354 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5355 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5356 ) ,
+ .clk_2_W_in ( clk_2_wires[125] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5357 ) ,
+ .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5358 ) , .clk_3_W_in ( p1811 ) ,
+ .clk_3_E_in ( p100 ) , .clk_3_S_in ( p2317 ) , .clk_3_N_in ( p166 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5359 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5360 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5361 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5362 ) ) ;
+sb_1__1_ sb_11__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5363 } ) ,
+ .chany_top_in ( cby_1__1__129_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__129_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__128_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__118_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__129_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__118_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__118_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__118_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2940 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5364 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5365 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5366 ) ,
+ .pReset_W_in ( pResetWires[495] ) , .pReset_N_out ( pResetWires[497] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5367 ) ,
+ .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( p3452 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5368 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[434] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5369 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[128] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[239] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3636 ) ,
+ .prog_clk_2_E_in ( p62 ) , .prog_clk_2_S_in ( p1090 ) ,
+ .prog_clk_2_W_in ( p3471 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5370 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5371 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5372 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5373 ) ,
+ .prog_clk_3_W_in ( p3504 ) , .prog_clk_3_E_in ( p1026 ) ,
+ .prog_clk_3_S_in ( p420 ) , .prog_clk_3_N_in ( p3631 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5374 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5375 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5376 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5377 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5378 ) ,
+ .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) ,
+ .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p3249 ) ,
+ .clk_2_E_in ( p382 ) , .clk_2_S_in ( p3394 ) , .clk_2_W_in ( p2037 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5379 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5380 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5381 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , .clk_3_W_in ( p2143 ) ,
+ .clk_3_E_in ( p781 ) , .clk_3_S_in ( p93 ) , .clk_3_N_in ( p3188 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5383 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5384 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5385 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5386 ) ) ;
+sb_1__1_ sb_11__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5387 } ) ,
+ .chany_top_in ( cby_1__1__130_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__130_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__129_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__119_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__130_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__119_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__119_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__119_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p2128 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5388 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5389 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5390 ) ,
+ .pReset_W_in ( pResetWires[544] ) , .pReset_N_out ( pResetWires[546] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5391 ) ,
+ .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( p2228 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5392 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p1692 ) ,
+ .prog_clk_1_S_in ( p1119 ) ,
+ .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5393 ) ,
+ .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5394 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5395 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5396 ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5397 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[132] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5398 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5399 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[134] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5400 ) ,
+ .prog_clk_3_W_in ( p1328 ) , .prog_clk_3_E_in ( p42 ) ,
+ .prog_clk_3_S_in ( p515 ) , .prog_clk_3_N_in ( p450 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5401 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5402 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5403 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , .clk_1_N_in ( p2460 ) ,
+ .clk_1_S_in ( p303 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5405 ) ,
+ .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5406 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5407 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5408 ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5409 ) ,
+ .clk_2_W_in ( clk_2_wires[132] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5410 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5411 ) ,
+ .clk_2_N_out ( clk_2_wires[134] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5412 ) , .clk_3_W_in ( p1328 ) ,
+ .clk_3_E_in ( p594 ) , .clk_3_S_in ( p1921 ) , .clk_3_N_in ( p2328 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5413 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5414 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5415 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5416 ) ) ;
+sb_1__1_ sb_11__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5417 } ) ,
+ .chany_top_in ( cby_1__1__131_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_lower ) ,
+ .chanx_right_in ( cbx_1__1__131_chanx_left_out ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__130_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__120_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( cbx_1__1__131_ccff_tail ) ,
+ .chany_top_out ( sb_1__1__120_chany_top_out ) ,
+ .chanx_right_out ( sb_1__1__120_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__1__120_chanx_left_out ) ,
+ .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p1290 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5418 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5419 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5420 ) ,
+ .pReset_W_in ( pResetWires[593] ) , .pReset_N_out ( pResetWires[595] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5421 ) ,
+ .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( p3253 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_5422 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[440] ) ,
+ .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5423 ) ,
+ .prog_clk_1_S_in ( prog_clk_2_wires[135] ) ,
+ .prog_clk_1_E_out ( prog_clk_1_wires[246] ) ,
+ .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p2674 ) ,
+ .prog_clk_2_E_in ( p153 ) , .prog_clk_2_S_in ( p684 ) ,
+ .prog_clk_2_W_in ( p2552 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5424 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5425 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5426 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5427 ) ,
+ .prog_clk_3_W_in ( p2679 ) , .prog_clk_3_E_in ( p834 ) ,
+ .prog_clk_3_S_in ( p55 ) , .prog_clk_3_N_in ( p2658 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5428 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5429 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5430 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5431 ) ,
+ .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5432 ) ,
+ .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) ,
+ .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p3338 ) ,
+ .clk_2_E_in ( p831 ) , .clk_2_S_in ( p3172 ) , .clk_2_W_in ( p3011 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5433 ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5434 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5435 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5436 ) , .clk_3_W_in ( p3144 ) ,
+ .clk_3_E_in ( p593 ) , .clk_3_S_in ( p432 ) , .clk_3_N_in ( p3298 ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5437 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5438 ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5439 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5440 ) ) ;
+sb_1__2_ sb_1__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5441 } ) ,
+ .chanx_right_in ( cbx_1__12__1_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__11_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__0_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_1_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__0_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__0_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1416 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5442 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5443 ) ,
+ .pReset_E_in ( pResetWires[604] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5444 ) ,
+ .pReset_W_out ( pResetWires[601] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5445 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[60] ) ) ;
+sb_1__2_ sb_2__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5446 } ) ,
+ .chanx_right_in ( cbx_1__12__2_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__23_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__1_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_2_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__1_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__1_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__1_ccff_tail ) , .SC_IN_BOT ( scff_Wires[52] ) ,
+ .SC_OUT_BOT ( scff_Wires[53] ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5447 ) ,
+ .pReset_E_in ( pResetWires[607] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5448 ) ,
+ .pReset_W_out ( pResetWires[605] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5449 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[100] ) ) ;
+sb_1__2_ sb_3__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5450 } ) ,
+ .chanx_right_in ( cbx_1__12__3_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__35_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__2_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_3_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__2_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__2_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1038 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5451 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5452 ) ,
+ .pReset_E_in ( pResetWires[610] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5453 ) ,
+ .pReset_W_out ( pResetWires[608] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5454 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[138] ) ) ;
+sb_1__2_ sb_4__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5455 } ) ,
+ .chanx_right_in ( cbx_1__12__4_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__47_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__3_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_4_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__3_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__3_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__3_ccff_tail ) , .SC_IN_BOT ( scff_Wires[105] ) ,
+ .SC_OUT_BOT ( scff_Wires[106] ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5456 ) ,
+ .pReset_E_in ( pResetWires[613] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5457 ) ,
+ .pReset_W_out ( pResetWires[611] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5458 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[176] ) ) ;
+sb_1__2_ sb_5__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5459 } ) ,
+ .chanx_right_in ( cbx_1__12__5_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__59_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__4_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_5_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__4_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__4_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1245 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5460 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5461 ) ,
+ .pReset_E_in ( pResetWires[616] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5462 ) ,
+ .pReset_W_out ( pResetWires[614] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5463 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[214] ) ) ;
+sb_1__2_ sb_6__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5464 } ) ,
+ .chanx_right_in ( cbx_1__12__6_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__71_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__5_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_6_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__5_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__5_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__5_ccff_tail ) , .SC_IN_BOT ( scff_Wires[158] ) ,
+ .SC_OUT_BOT ( scff_Wires[159] ) , .pReset_S_in ( pResetWires[24] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5465 ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5466 ) ,
+ .pReset_W_out ( pResetWires[617] ) , .pReset_E_out ( pResetWires[619] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[252] ) ) ;
+sb_1__2_ sb_7__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5467 } ) ,
+ .chanx_right_in ( cbx_1__12__7_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__83_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__6_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_7_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__6_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__6_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1347 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5468 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5469 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5470 ) ,
+ .pReset_W_in ( pResetWires[620] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5471 ) ,
+ .pReset_E_out ( pResetWires[622] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[290] ) ) ;
+sb_1__2_ sb_8__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5472 } ) ,
+ .chanx_right_in ( cbx_1__12__8_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__95_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__7_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_8_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__7_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__7_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__7_ccff_tail ) , .SC_IN_BOT ( scff_Wires[211] ) ,
+ .SC_OUT_BOT ( scff_Wires[212] ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5473 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5474 ) ,
+ .pReset_W_in ( pResetWires[623] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5475 ) ,
+ .pReset_E_out ( pResetWires[625] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[328] ) ) ;
+sb_1__2_ sb_9__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5476 } ) ,
+ .chanx_right_in ( cbx_1__12__9_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__107_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__8_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_9_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__8_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__8_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1219 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5477 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5478 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5479 ) ,
+ .pReset_W_in ( pResetWires[626] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5480 ) ,
+ .pReset_E_out ( pResetWires[628] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[366] ) ) ;
+sb_1__2_ sb_10__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5481 } ) ,
+ .chanx_right_in ( cbx_1__12__10_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__119_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__9_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_10_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__9_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__9_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__9_ccff_tail ) , .SC_IN_BOT ( scff_Wires[264] ) ,
+ .SC_OUT_BOT ( scff_Wires[265] ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5482 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5483 ) ,
+ .pReset_W_in ( pResetWires[629] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5484 ) ,
+ .pReset_E_out ( pResetWires[631] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[404] ) ) ;
+sb_1__2_ sb_11__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5485 } ) ,
+ .chanx_right_in ( cbx_1__12__11_chanx_left_out ) ,
+ .right_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) ,
+ .right_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_upper ) ,
+ .right_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_upper ) ,
+ .right_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_upper ) ,
+ .right_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_upper ) ,
+ .right_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_upper ) ,
+ .right_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_upper ) ,
+ .right_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_upper ) ,
+ .right_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_upper ) ,
+ .chany_bottom_in ( cby_1__1__131_chany_top_out ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__10_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_top_11_ccff_tail ) ,
+ .chanx_right_out ( sb_1__12__10_chanx_right_out ) ,
+ .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_1__12__10_chanx_left_out ) ,
+ .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1254 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5486 ) ,
+ .pReset_S_in ( SYNOPSYS_UNCONNECTED_5487 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5488 ) ,
+ .pReset_W_in ( pResetWires[632] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5489 ) ,
+ .pReset_E_out ( pResetWires[634] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[442] ) ) ;
+sb_2__0_ sb_12__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5490 } ) ,
+ .chany_top_in ( cby_12__1__0_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) ,
+ .chanx_left_in ( cbx_1__0__11_chanx_right_out ) ,
+ .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) ,
+ .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) ,
+ .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) ,
+ .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) ,
+ .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) ,
+ .left_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) ,
+ .left_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) ,
+ .left_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) ,
+ .ccff_head ( grid_io_right_11_ccff_tail ) ,
+ .chany_top_out ( sb_12__0__0_chany_top_out ) ,
+ .chanx_left_out ( sb_12__0__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__0__0_ccff_tail ) , .pReset_W_in ( pResetWires[59] ) ,
+ .pReset_N_out ( pResetWires[60] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[445] ) ) ;
+sb_2__1_ sb_12__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5491 } ) ,
+ .chany_top_in ( cby_12__1__1_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__0_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__121_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_10_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__0_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__0_ccff_tail ) , .pReset_W_in ( pResetWires[107] ) ,
+ .pReset_N_out ( pResetWires[109] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[448] ) ) ;
+sb_2__1_ sb_12__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5492 } ) ,
+ .chany_top_in ( cby_12__1__2_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__1_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__122_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_9_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__1_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__1_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__1_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__1_ccff_tail ) , .pReset_W_in ( pResetWires[156] ) ,
+ .pReset_N_out ( pResetWires[158] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[451] ) ) ;
+sb_2__1_ sb_12__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5493 } ) ,
+ .chany_top_in ( cby_12__1__3_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__2_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__123_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_8_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__2_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__2_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__2_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__2_ccff_tail ) , .pReset_W_in ( pResetWires[205] ) ,
+ .pReset_N_out ( pResetWires[207] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[454] ) ) ;
+sb_2__1_ sb_12__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5494 } ) ,
+ .chany_top_in ( cby_12__1__4_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__3_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__124_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_7_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__3_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__3_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__3_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__3_ccff_tail ) , .pReset_W_in ( pResetWires[254] ) ,
+ .pReset_N_out ( pResetWires[256] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[457] ) ) ;
+sb_2__1_ sb_12__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5495 } ) ,
+ .chany_top_in ( cby_12__1__5_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__4_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__125_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_6_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__4_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__4_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__4_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__4_ccff_tail ) , .pReset_W_in ( pResetWires[303] ) ,
+ .pReset_N_out ( pResetWires[305] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[460] ) ) ;
+sb_2__1_ sb_12__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5496 } ) ,
+ .chany_top_in ( cby_12__1__6_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__5_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__126_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_5_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__5_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__5_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__5_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__5_ccff_tail ) , .pReset_W_in ( pResetWires[352] ) ,
+ .pReset_N_out ( pResetWires[354] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[463] ) ) ;
+sb_2__1_ sb_12__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5497 } ) ,
+ .chany_top_in ( cby_12__1__7_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__6_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__127_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_4_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__6_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__6_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__6_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__6_ccff_tail ) , .pReset_W_in ( pResetWires[401] ) ,
+ .pReset_N_out ( pResetWires[403] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[466] ) ) ;
+sb_2__1_ sb_12__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5498 } ) ,
+ .chany_top_in ( cby_12__1__8_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__7_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__128_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_3_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__7_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__7_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__7_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__7_ccff_tail ) , .pReset_W_in ( pResetWires[450] ) ,
+ .pReset_N_out ( pResetWires[452] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[469] ) ) ;
+sb_2__1_ sb_12__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5499 } ) ,
+ .chany_top_in ( cby_12__1__9_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__8_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__129_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_2_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__8_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__8_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__8_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__8_ccff_tail ) , .pReset_W_in ( pResetWires[499] ) ,
+ .pReset_N_out ( pResetWires[501] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[472] ) ) ;
+sb_2__1_ sb_12__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5500 } ) ,
+ .chany_top_in ( cby_12__1__10_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__9_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__130_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_1_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__9_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__9_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__9_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__9_ccff_tail ) , .pReset_W_in ( pResetWires[548] ) ,
+ .pReset_N_out ( pResetWires[550] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[475] ) ) ;
+sb_2__1_ sb_12__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5501 } ) ,
+ .chany_top_in ( cby_12__1__11_chany_bottom_out ) ,
+ .top_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_lower ) ,
+ .top_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_lower ) ,
+ .top_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_lower ) ,
+ .top_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_lower ) ,
+ .top_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_lower ) ,
+ .top_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_lower ) ,
+ .top_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_lower ) ,
+ .top_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_lower ) ,
+ .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ,
+ .chany_bottom_in ( cby_12__1__10_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__1__131_chanx_right_out ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( grid_io_right_0_ccff_tail ) ,
+ .chany_top_out ( sb_12__1__10_chany_top_out ) ,
+ .chany_bottom_out ( sb_12__1__10_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__1__10_chanx_left_out ) ,
+ .ccff_tail ( sb_12__1__10_ccff_tail ) ,
+ .pReset_W_in ( pResetWires[597] ) , .pReset_N_out ( pResetWires[599] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[478] ) ) ;
+sb_2__2_ sb_12__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5502 } ) ,
+ .chany_bottom_in ( cby_12__1__11_chany_top_out ) ,
+ .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) ,
+ .bottom_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_upper ) ,
+ .bottom_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_upper ) ,
+ .bottom_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_upper ) ,
+ .bottom_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_upper ) ,
+ .bottom_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_upper ) ,
+ .bottom_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_upper ) ,
+ .bottom_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_upper ) ,
+ .bottom_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_upper ) ,
+ .chanx_left_in ( cbx_1__12__11_chanx_right_out ) ,
+ .left_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) ,
+ .left_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_lower ) ,
+ .left_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_lower ) ,
+ .left_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_lower ) ,
+ .left_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_lower ) ,
+ .left_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_lower ) ,
+ .left_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_lower ) ,
+ .left_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_lower ) ,
+ .left_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_lower ) ,
+ .ccff_head ( ccff_head ) ,
+ .chany_bottom_out ( sb_12__12__0_chany_bottom_out ) ,
+ .chanx_left_out ( sb_12__12__0_chanx_left_out ) ,
+ .ccff_tail ( sb_12__12__0_ccff_tail ) , .SC_IN_BOT ( scff_Wires[317] ) ,
+ .SC_OUT_BOT ( sc_tail ) , .pReset_W_in ( pResetWires[635] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[480] ) ) ;
+cbx_1__0_ cbx_1__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5503 } ) ,
+ .chanx_left_in ( sb_0__0__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__0_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123:131] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123:131] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123:131] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) ,
+ .SC_IN_BOT ( p895 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5504 ) ,
+ .pReset_E_in ( pResetWires[26] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5505 ) ,
+ .pReset_W_out ( pResetWires[25] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5506 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[0] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[5] ) ) ;
+cbx_1__0_ cbx_2__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5507 } ) ,
+ .chanx_left_in ( sb_1__0__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__1_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114:122] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114:122] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114:122] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1149 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5508 ) ,
+ .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) ,
+ .pReset_E_in ( pResetWires[29] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5509 ) ,
+ .pReset_W_out ( pResetWires[28] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5510 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[63] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5511 ) ) ;
+cbx_1__0_ cbx_3__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5512 } ) ,
+ .chanx_left_in ( sb_1__0__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__2_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105:113] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105:113] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105:113] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) ,
+ .SC_IN_BOT ( p1691 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5513 ) ,
+ .pReset_E_in ( pResetWires[32] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5514 ) ,
+ .pReset_W_out ( pResetWires[31] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5515 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[101] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5516 ) ) ;
+cbx_1__0_ cbx_4__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5517 } ) ,
+ .chanx_left_in ( sb_1__0__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__3_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:104] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:104] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:104] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1442 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5518 ) ,
+ .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) ,
+ .pReset_E_in ( pResetWires[35] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5519 ) ,
+ .pReset_W_out ( pResetWires[34] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5520 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[139] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5521 ) ) ;
+cbx_1__0_ cbx_5__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5522 } ) ,
+ .chanx_left_in ( sb_1__0__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__4_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87:95] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87:95] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87:95] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) ,
+ .SC_IN_BOT ( p1055 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5523 ) ,
+ .pReset_E_in ( pResetWires[38] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5524 ) ,
+ .pReset_W_out ( pResetWires[37] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5525 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[177] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5526 ) ) ;
+cbx_1__0_ cbx_6__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5527 } ) ,
+ .chanx_left_in ( sb_1__0__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__5_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78:86] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78:86] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78:86] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1458 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5528 ) ,
+ .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) ,
+ .pReset_E_in ( pResetWires[41] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5529 ) ,
+ .pReset_W_out ( pResetWires[40] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5530 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[215] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5531 ) ) ;
+cbx_1__0_ cbx_7__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5532 } ) ,
+ .chanx_left_in ( sb_1__0__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__6_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69:77] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69:77] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69:77] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) ,
+ .SC_IN_BOT ( p1432 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5533 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5534 ) ,
+ .pReset_W_in ( pResetWires[43] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5535 ) ,
+ .pReset_E_out ( pResetWires[44] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[253] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5536 ) ) ;
+cbx_1__0_ cbx_8__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5537 } ) ,
+ .chanx_left_in ( sb_1__0__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__7_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:68] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:68] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:68] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p613 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5538 ) ,
+ .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5539 ) ,
+ .pReset_W_in ( pResetWires[46] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5540 ) ,
+ .pReset_E_out ( pResetWires[47] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[291] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5541 ) ) ;
+cbx_1__0_ cbx_9__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5542 } ) ,
+ .chanx_left_in ( sb_1__0__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__8_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51:59] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51:59] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51:59] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) ,
+ .SC_IN_BOT ( p1373 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5543 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5544 ) ,
+ .pReset_W_in ( pResetWires[49] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5545 ) ,
+ .pReset_E_out ( pResetWires[50] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[329] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5546 ) ) ;
+cbx_1__0_ cbx_10__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5547 } ) ,
+ .chanx_left_in ( sb_1__0__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__9_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42:50] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42:50] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42:50] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1213 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5548 ) ,
+ .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5549 ) ,
+ .pReset_W_in ( pResetWires[52] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5550 ) ,
+ .pReset_E_out ( pResetWires[53] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[367] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5551 ) ) ;
+cbx_1__0_ cbx_11__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5552 } ) ,
+ .chanx_left_in ( sb_1__0__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__0__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__0__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__10_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33:41] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33:41] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33:41] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) ,
+ .SC_IN_BOT ( p1271 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5553 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5554 ) ,
+ .pReset_W_in ( pResetWires[55] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5555 ) ,
+ .pReset_E_out ( pResetWires[56] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[405] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5556 ) ) ;
+cbx_1__0_ cbx_12__0_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5557 } ) ,
+ .chanx_left_in ( sb_1__0__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__0__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__0__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__0__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__0__11_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) ,
+ .ccff_tail ( grid_io_bottom_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:32] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:32] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:32] ) ,
+ .top_width_0_height_0__pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) ,
+ .top_width_0_height_0__pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) ,
+ .top_width_0_height_0__pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) ,
+ .top_width_0_height_0__pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) ,
+ .top_width_0_height_0__pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) ,
+ .top_width_0_height_0__pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) ,
+ .top_width_0_height_0__pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) ,
+ .top_width_0_height_0__pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) ,
+ .top_width_0_height_0__pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) ,
+ .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) ,
+ .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) ,
+ .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) ,
+ .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) ,
+ .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) ,
+ .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) ,
+ .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) ,
+ .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) ,
+ .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) ,
+ .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) ,
+ .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) ,
+ .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) ,
+ .top_width_0_height_0__pin_13_upper ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) ,
+ .top_width_0_height_0__pin_13_lower ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) ,
+ .top_width_0_height_0__pin_15_upper ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) ,
+ .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) ,
+ .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) ,
+ .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) ,
+ .SC_IN_TOP ( p1237 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5558 ) ,
+ .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_5559 ) ,
+ .pReset_W_in ( pResetWires[58] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_5560 ) ,
+ .pReset_E_out ( pResetWires[59] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[443] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5561 ) ) ;
+cbx_1__1_ cbx_1__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5562 } ) ,
+ .chanx_left_in ( sb_0__1__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__0_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) ,
+ .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p1127 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5563 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[0] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[0] ) ,
+ .pReset_E_in ( pResetWires[62] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5564 ) ,
+ .pReset_W_out ( pResetWires[61] ) , .pReset_S_out ( pResetWires[63] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5565 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[6] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[4] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5566 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[2] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[3] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p2700 ) ,
+ .prog_clk_2_W_in ( p2889 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5567 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5568 ) ,
+ .prog_clk_3_W_in ( p2987 ) , .prog_clk_3_E_in ( p2659 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5569 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5570 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5571 ) ,
+ .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) ,
+ .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p2190 ) ,
+ .clk_2_W_in ( p2851 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2895 ) ,
+ .clk_3_E_in ( p926 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5575 ) ) ;
+cbx_1__1_ cbx_1__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5576 } ) ,
+ .chanx_left_in ( sb_0__1__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__1_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) ,
+ .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p2475 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5577 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[1] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[1] ) ,
+ .pReset_E_in ( pResetWires[111] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5578 ) ,
+ .pReset_W_out ( pResetWires[110] ) , .pReset_S_out ( pResetWires[112] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5579 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[11] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p1214 ) ,
+ .prog_clk_1_E_in ( p518 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5580 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5581 ) ,
+ .prog_clk_2_E_in ( p3498 ) , .prog_clk_2_W_in ( p3219 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5582 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5583 ) ,
+ .prog_clk_3_W_in ( p3279 ) , .prog_clk_3_E_in ( p3459 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5584 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p1214 ) ,
+ .clk_1_E_in ( p2289 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p1678 ) ,
+ .clk_2_W_in ( p3206 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p3278 ) ,
+ .clk_3_E_in ( p2369 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) ) ;
+cbx_1__1_ cbx_1__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5592 } ) ,
+ .chanx_left_in ( sb_0__1__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__2_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) ,
+ .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1374 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5593 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[2] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[2] ) ,
+ .pReset_E_in ( pResetWires[160] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5594 ) ,
+ .pReset_W_out ( pResetWires[159] ) , .pReset_S_out ( pResetWires[161] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5595 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[16] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[15] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5596 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[9] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[10] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p2381 ) ,
+ .prog_clk_2_W_in ( p3308 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5597 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5598 ) ,
+ .prog_clk_3_W_in ( p3363 ) , .prog_clk_3_E_in ( p2391 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5599 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5600 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5601 ) ,
+ .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) ,
+ .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p1856 ) ,
+ .clk_2_W_in ( p3020 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p3154 ) ,
+ .clk_3_E_in ( p790 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5605 ) ) ;
+cbx_1__1_ cbx_1__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5606 } ) ,
+ .chanx_left_in ( sb_0__1__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__3_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) ,
+ .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1353 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5607 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[3] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[3] ) ,
+ .pReset_E_in ( pResetWires[209] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5608 ) ,
+ .pReset_W_out ( pResetWires[208] ) , .pReset_S_out ( pResetWires[210] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5609 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[21] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p1169 ) ,
+ .prog_clk_1_E_in ( p999 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5610 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5611 ) ,
+ .prog_clk_2_E_in ( p2500 ) , .prog_clk_2_W_in ( p2615 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5612 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5613 ) ,
+ .prog_clk_3_W_in ( p2731 ) , .prog_clk_3_E_in ( p2341 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5614 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_1_W_in ( p1169 ) ,
+ .clk_1_E_in ( p161 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5616 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_2_E_in ( p2467 ) ,
+ .clk_2_W_in ( p3055 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p3137 ) ,
+ .clk_3_E_in ( p493 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5621 ) ) ;
+cbx_1__1_ cbx_1__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5622 } ) ,
+ .chanx_left_in ( sb_0__1__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__4_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) ,
+ .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1082 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5623 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[4] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[4] ) ,
+ .pReset_E_in ( pResetWires[258] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5624 ) ,
+ .pReset_W_out ( pResetWires[257] ) , .pReset_S_out ( pResetWires[259] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5625 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[26] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[25] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5626 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[16] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[17] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p2116 ) ,
+ .prog_clk_2_W_in ( p3319 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5627 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5628 ) ,
+ .prog_clk_3_W_in ( p3366 ) , .prog_clk_3_E_in ( p2356 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5629 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5630 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5631 ) ,
+ .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) ,
+ .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p2442 ) ,
+ .clk_2_W_in ( p1949 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p2194 ) ,
+ .clk_3_E_in ( p1020 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5635 ) ) ;
+cbx_1__1_ cbx_1__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5636 } ) ,
+ .chanx_left_in ( sb_0__1__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__5_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) ,
+ .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1224 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5637 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[5] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[5] ) ,
+ .pReset_E_in ( pResetWires[307] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5638 ) ,
+ .pReset_W_out ( pResetWires[306] ) , .pReset_S_out ( pResetWires[308] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5639 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[31] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p1630 ) ,
+ .prog_clk_1_E_in ( p676 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5640 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5641 ) ,
+ .prog_clk_2_E_in ( p3544 ) , .prog_clk_2_W_in ( p3423 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5642 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5643 ) ,
+ .prog_clk_3_W_in ( p3411 ) , .prog_clk_3_E_in ( p3529 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5644 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_1_W_in ( p1630 ) ,
+ .clk_1_E_in ( p1098 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5646 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_2_E_in ( p2433 ) ,
+ .clk_2_W_in ( p1621 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p1805 ) ,
+ .clk_3_E_in ( p1035 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5651 ) ) ;
+cbx_1__1_ cbx_1__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5652 } ) ,
+ .chanx_left_in ( sb_0__1__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__6_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) ,
+ .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1012 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5653 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[6] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[6] ) ,
+ .pReset_E_in ( pResetWires[356] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5654 ) ,
+ .pReset_W_out ( pResetWires[355] ) , .pReset_S_out ( pResetWires[357] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5655 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[36] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[35] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5656 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[23] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[24] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p3441 ) ,
+ .prog_clk_2_W_in ( p2577 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5657 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5658 ) ,
+ .prog_clk_3_W_in ( p2777 ) , .prog_clk_3_E_in ( p3413 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5659 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5660 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5661 ) ,
+ .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) ,
+ .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p3237 ) ,
+ .clk_2_W_in ( p2043 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p2071 ) ,
+ .clk_3_E_in ( p510 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5665 ) ) ;
+cbx_1__1_ cbx_1__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5666 } ) ,
+ .chanx_left_in ( sb_0__1__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__7_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) ,
+ .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1836 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5667 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[7] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[7] ) ,
+ .pReset_E_in ( pResetWires[405] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5668 ) ,
+ .pReset_W_out ( pResetWires[404] ) , .pReset_S_out ( pResetWires[406] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5669 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[41] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1017 ) ,
+ .prog_clk_1_E_in ( p953 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5670 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5671 ) ,
+ .prog_clk_2_E_in ( p3424 ) , .prog_clk_2_W_in ( p3643 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5672 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5673 ) ,
+ .prog_clk_3_W_in ( p3646 ) , .prog_clk_3_E_in ( p3387 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5674 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p1017 ) ,
+ .clk_1_E_in ( p1602 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_2_E_in ( p2399 ) ,
+ .clk_2_W_in ( p3217 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p3245 ) ,
+ .clk_3_E_in ( p1543 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) ) ;
+cbx_1__1_ cbx_1__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5682 } ) ,
+ .chanx_left_in ( sb_0__1__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__8_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) ,
+ .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1712 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5683 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[8] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[8] ) ,
+ .pReset_E_in ( pResetWires[454] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5684 ) ,
+ .pReset_W_out ( pResetWires[453] ) , .pReset_S_out ( pResetWires[455] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5685 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[46] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[45] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5686 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[30] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[31] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p3501 ) ,
+ .prog_clk_2_W_in ( p3293 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5687 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5688 ) ,
+ .prog_clk_3_W_in ( p3345 ) , .prog_clk_3_E_in ( p3463 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5689 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5690 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5691 ) ,
+ .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) ,
+ .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p2935 ) ,
+ .clk_2_W_in ( p2999 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p3117 ) ,
+ .clk_3_E_in ( p629 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5695 ) ) ;
+cbx_1__1_ cbx_1__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5696 } ) ,
+ .chanx_left_in ( sb_0__1__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__9_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) ,
+ .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p1316 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5697 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[9] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[9] ) ,
+ .pReset_E_in ( pResetWires[503] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5698 ) ,
+ .pReset_W_out ( pResetWires[502] ) , .pReset_S_out ( pResetWires[504] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5699 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[51] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p1460 ) ,
+ .prog_clk_1_E_in ( p1135 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5700 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5701 ) ,
+ .prog_clk_2_E_in ( p3269 ) , .prog_clk_2_W_in ( p3213 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5702 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5703 ) ,
+ .prog_clk_3_W_in ( p3227 ) , .prog_clk_3_E_in ( p3195 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5704 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_1_W_in ( p1460 ) ,
+ .clk_1_E_in ( p453 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5706 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_2_E_in ( p3091 ) ,
+ .clk_2_W_in ( p2867 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p2988 ) ,
+ .clk_3_E_in ( p1524 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5711 ) ) ;
+cbx_1__1_ cbx_1__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5712 } ) ,
+ .chanx_left_in ( sb_0__1__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__10_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) ,
+ .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1338 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5713 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[10] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[10] ) ,
+ .pReset_E_in ( pResetWires[552] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5714 ) ,
+ .pReset_W_out ( pResetWires[551] ) , .pReset_S_out ( pResetWires[553] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5715 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[56] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[55] ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5716 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[37] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[38] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p2175 ) ,
+ .prog_clk_2_W_in ( p1981 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5717 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5718 ) ,
+ .prog_clk_3_W_in ( p2120 ) , .prog_clk_3_E_in ( p2004 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5719 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5720 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5721 ) ,
+ .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) ,
+ .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2137 ) ,
+ .clk_2_W_in ( p2042 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2067 ) ,
+ .clk_3_E_in ( p545 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5725 ) ) ;
+cbx_1__1_ cbx_2__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5726 } ) ,
+ .chanx_left_in ( sb_1__1__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__11_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__11_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__11_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p1334 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5727 ) ,
+ .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[11] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[11] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[11] ) ,
+ .pReset_E_in ( pResetWires[67] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5728 ) ,
+ .pReset_W_out ( pResetWires[66] ) , .pReset_S_out ( pResetWires[68] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5729 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[66] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5730 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[1] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5731 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[5] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p1784 ) ,
+ .prog_clk_2_W_in ( p3053 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5732 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5733 ) ,
+ .prog_clk_3_W_in ( p3109 ) , .prog_clk_3_E_in ( p2261 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5734 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5735 ) ,
+ .clk_1_W_in ( clk_1_wires[1] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5736 ) ,
+ .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) ,
+ .clk_2_E_in ( p2456 ) , .clk_2_W_in ( p3064 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5737 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p3086 ) ,
+ .clk_3_E_in ( p488 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) ) ;
+cbx_1__1_ cbx_2__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5741 } ) ,
+ .chanx_left_in ( sb_1__1__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__12_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__12_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__12_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__12_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p1900 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5742 ) ,
+ .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[12] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[12] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[12] ) ,
+ .pReset_E_in ( pResetWires[116] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5743 ) ,
+ .pReset_W_out ( pResetWires[115] ) , .pReset_S_out ( pResetWires[117] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5744 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[69] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5745 ) ,
+ .prog_clk_1_W_in ( p931 ) , .prog_clk_1_E_in ( p530 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5746 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5747 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[2] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5748 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[1] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5749 ) ,
+ .prog_clk_3_W_in ( p1456 ) , .prog_clk_3_E_in ( p1624 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5750 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , .clk_1_W_in ( p931 ) ,
+ .clk_1_E_in ( p1230 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5752 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5753 ) ,
+ .clk_2_E_in ( clk_2_wires[2] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5754 ) ,
+ .clk_2_W_out ( clk_2_wires[1] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1456 ) ,
+ .clk_3_E_in ( p1491 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5757 ) ) ;
+cbx_1__1_ cbx_2__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5758 } ) ,
+ .chanx_left_in ( sb_1__1__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__13_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__13_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__13_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__13_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1746 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5759 ) ,
+ .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[13] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[13] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[13] ) ,
+ .pReset_E_in ( pResetWires[165] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5760 ) ,
+ .pReset_W_out ( pResetWires[164] ) , .pReset_S_out ( pResetWires[166] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5761 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[72] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5762 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[8] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5763 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[12] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p2499 ) ,
+ .prog_clk_2_W_in ( p2660 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5764 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5765 ) ,
+ .prog_clk_3_W_in ( p2702 ) , .prog_clk_3_E_in ( p2351 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5766 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5767 ) ,
+ .clk_1_W_in ( clk_1_wires[8] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5768 ) ,
+ .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) ,
+ .clk_2_E_in ( p2241 ) , .clk_2_W_in ( p2585 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5769 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p2760 ) ,
+ .clk_3_E_in ( p1643 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5772 ) ) ;
+cbx_1__1_ cbx_2__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5773 } ) ,
+ .chanx_left_in ( sb_1__1__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__14_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__14_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__14_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__14_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p2385 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5774 ) ,
+ .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[14] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[14] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[14] ) ,
+ .pReset_E_in ( pResetWires[214] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5775 ) ,
+ .pReset_W_out ( pResetWires[213] ) , .pReset_S_out ( pResetWires[215] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5776 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[75] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5777 ) ,
+ .prog_clk_1_W_in ( p1364 ) , .prog_clk_1_E_in ( p1160 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5778 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5779 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[7] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5780 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[6] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5781 ) ,
+ .prog_clk_3_W_in ( p1886 ) , .prog_clk_3_E_in ( p575 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5782 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) , .clk_1_W_in ( p1364 ) ,
+ .clk_1_E_in ( p458 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5784 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5785 ) ,
+ .clk_2_E_in ( clk_2_wires[7] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5786 ) ,
+ .clk_2_W_out ( clk_2_wires[6] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1886 ) ,
+ .clk_3_E_in ( p2260 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5789 ) ) ;
+cbx_1__1_ cbx_2__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5790 } ) ,
+ .chanx_left_in ( sb_1__1__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__15_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__15_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__15_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__15_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p1792 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5791 ) ,
+ .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[15] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[15] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[15] ) ,
+ .pReset_E_in ( pResetWires[263] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5792 ) ,
+ .pReset_W_out ( pResetWires[262] ) , .pReset_S_out ( pResetWires[264] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5793 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[78] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5794 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[15] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5795 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[19] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p1649 ) ,
+ .prog_clk_2_W_in ( p3565 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5796 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5797 ) ,
+ .prog_clk_3_W_in ( p3569 ) , .prog_clk_3_E_in ( p2635 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5798 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5799 ) ,
+ .clk_1_W_in ( clk_1_wires[15] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5800 ) ,
+ .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) ,
+ .clk_2_E_in ( p2787 ) , .clk_2_W_in ( p483 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5801 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p1405 ) ,
+ .clk_3_E_in ( p1617 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) ) ;
+cbx_1__1_ cbx_2__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5805 } ) ,
+ .chanx_left_in ( sb_1__1__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__16_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__16_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__16_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__16_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p1295 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5806 ) ,
+ .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[16] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[16] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[16] ) ,
+ .pReset_E_in ( pResetWires[312] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5807 ) ,
+ .pReset_W_out ( pResetWires[311] ) , .pReset_S_out ( pResetWires[313] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5808 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[81] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5809 ) ,
+ .prog_clk_1_W_in ( p1099 ) , .prog_clk_1_E_in ( p300 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5810 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5811 ) ,
+ .prog_clk_2_E_in ( p2738 ) , .prog_clk_2_W_in ( p2631 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5812 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5813 ) ,
+ .prog_clk_3_W_in ( p2740 ) , .prog_clk_3_E_in ( p2612 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5814 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_1_W_in ( p1099 ) ,
+ .clk_1_E_in ( p749 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5816 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_2_E_in ( p2791 ) ,
+ .clk_2_W_in ( p2372 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p2544 ) ,
+ .clk_3_E_in ( p490 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5821 ) ) ;
+cbx_1__1_ cbx_2__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5822 } ) ,
+ .chanx_left_in ( sb_1__1__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__17_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__17_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__17_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__17_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p1097 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5823 ) ,
+ .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[17] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[17] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[17] ) ,
+ .pReset_E_in ( pResetWires[361] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5824 ) ,
+ .pReset_W_out ( pResetWires[360] ) , .pReset_S_out ( pResetWires[362] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5825 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[84] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5826 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[22] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5827 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[26] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p3146 ) ,
+ .prog_clk_2_W_in ( p3174 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5828 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5829 ) ,
+ .prog_clk_3_W_in ( p3264 ) , .prog_clk_3_E_in ( p3045 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5830 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5831 ) ,
+ .clk_1_W_in ( clk_1_wires[22] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5832 ) ,
+ .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) ,
+ .clk_2_E_in ( p2486 ) , .clk_2_W_in ( p1984 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5833 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p2242 ) ,
+ .clk_3_E_in ( p213 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5836 ) ) ;
+cbx_1__1_ cbx_2__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5837 } ) ,
+ .chanx_left_in ( sb_1__1__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__18_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__18_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__18_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__18_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p1851 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5838 ) ,
+ .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[18] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[18] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[18] ) ,
+ .pReset_E_in ( pResetWires[410] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5839 ) ,
+ .pReset_W_out ( pResetWires[409] ) , .pReset_S_out ( pResetWires[411] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5840 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[87] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5841 ) ,
+ .prog_clk_1_W_in ( p1228 ) , .prog_clk_1_E_in ( p1234 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5842 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5843 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[14] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5844 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[13] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5845 ) ,
+ .prog_clk_3_W_in ( p1777 ) , .prog_clk_3_E_in ( p406 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5846 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_1_W_in ( p1228 ) ,
+ .clk_1_E_in ( p358 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5848 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5849 ) ,
+ .clk_2_E_in ( clk_2_wires[14] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5850 ) ,
+ .clk_2_W_out ( clk_2_wires[13] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p1777 ) ,
+ .clk_3_E_in ( p1531 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5853 ) ) ;
+cbx_1__1_ cbx_2__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5854 } ) ,
+ .chanx_left_in ( sb_1__1__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__19_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__19_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__19_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__19_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p2085 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5855 ) ,
+ .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[19] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[19] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[19] ) ,
+ .pReset_E_in ( pResetWires[459] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5856 ) ,
+ .pReset_W_out ( pResetWires[458] ) , .pReset_S_out ( pResetWires[460] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5857 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[90] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5858 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[29] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5859 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[33] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p3268 ) ,
+ .prog_clk_2_W_in ( p408 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5860 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5861 ) ,
+ .prog_clk_3_W_in ( p1323 ) , .prog_clk_3_E_in ( p3194 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5862 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5863 ) ,
+ .clk_1_W_in ( clk_1_wires[29] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5864 ) ,
+ .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) ,
+ .clk_2_E_in ( p2950 ) , .clk_2_W_in ( p2611 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5865 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p2772 ) ,
+ .clk_3_E_in ( p2038 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5868 ) ) ;
+cbx_1__1_ cbx_2__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5869 } ) ,
+ .chanx_left_in ( sb_1__1__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__20_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__20_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__20_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__20_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p2077 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5870 ) ,
+ .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[20] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[20] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[20] ) ,
+ .pReset_E_in ( pResetWires[508] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5871 ) ,
+ .pReset_W_out ( pResetWires[507] ) , .pReset_S_out ( pResetWires[509] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5872 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[93] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5873 ) ,
+ .prog_clk_1_W_in ( p1185 ) , .prog_clk_1_E_in ( p1132 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5874 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5875 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[21] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5876 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[20] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5877 ) ,
+ .prog_clk_3_W_in ( p1368 ) , .prog_clk_3_E_in ( p1616 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5878 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , .clk_1_W_in ( p1185 ) ,
+ .clk_1_E_in ( p276 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5880 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5881 ) ,
+ .clk_2_E_in ( clk_2_wires[21] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5882 ) ,
+ .clk_2_W_out ( clk_2_wires[20] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1368 ) ,
+ .clk_3_E_in ( p1974 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5885 ) ) ;
+cbx_1__1_ cbx_2__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5886 } ) ,
+ .chanx_left_in ( sb_1__1__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__21_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__21_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__21_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__21_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1450 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5887 ) ,
+ .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[21] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[21] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[21] ) ,
+ .pReset_E_in ( pResetWires[557] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5888 ) ,
+ .pReset_W_out ( pResetWires[556] ) , .pReset_S_out ( pResetWires[558] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5889 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[96] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5890 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[36] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5891 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[40] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p3138 ) ,
+ .prog_clk_2_W_in ( p1683 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5892 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5893 ) ,
+ .prog_clk_3_W_in ( p1646 ) , .prog_clk_3_E_in ( p3073 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5894 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5895 ) ,
+ .clk_1_W_in ( clk_1_wires[36] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5896 ) ,
+ .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) ,
+ .clk_2_E_in ( p2182 ) , .clk_2_W_in ( p2617 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5897 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p2770 ) ,
+ .clk_3_E_in ( p757 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5900 ) ) ;
+cbx_1__1_ cbx_3__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5901 } ) ,
+ .chanx_left_in ( sb_1__1__11_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__22_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__22_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__22_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__22_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) ,
+ .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1013 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5902 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[22] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[22] ) ,
+ .pReset_E_in ( pResetWires[71] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5903 ) ,
+ .pReset_W_out ( pResetWires[70] ) , .pReset_S_out ( pResetWires[72] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5904 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[104] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5905 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5906 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[44] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[45] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p1350 ) ,
+ .prog_clk_2_W_in ( p2998 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5907 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5908 ) ,
+ .prog_clk_3_W_in ( p3093 ) , .prog_clk_3_E_in ( p1611 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5909 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5910 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5911 ) ,
+ .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) ,
+ .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p1726 ) ,
+ .clk_2_W_in ( p3072 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p3140 ) ,
+ .clk_3_E_in ( p1 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5915 ) ) ;
+cbx_1__1_ cbx_3__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5916 } ) ,
+ .chanx_left_in ( sb_1__1__12_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__23_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__23_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__23_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__23_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) ,
+ .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1689 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5917 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[23] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[23] ) ,
+ .pReset_E_in ( pResetWires[120] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5918 ) ,
+ .pReset_W_out ( pResetWires[119] ) , .pReset_S_out ( pResetWires[121] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5919 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[107] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5920 ) ,
+ .prog_clk_1_W_in ( p1084 ) , .prog_clk_1_E_in ( p1242 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5921 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5922 ) ,
+ .prog_clk_2_E_in ( p3488 ) , .prog_clk_2_W_in ( p2885 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5923 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5924 ) ,
+ .prog_clk_3_W_in ( p2992 ) , .prog_clk_3_E_in ( p3479 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5925 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_1_W_in ( p1084 ) ,
+ .clk_1_E_in ( p1521 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5927 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_2_E_in ( p2229 ) ,
+ .clk_2_W_in ( p2814 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p2943 ) ,
+ .clk_3_E_in ( p975 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5932 ) ) ;
+cbx_1__1_ cbx_3__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5933 } ) ,
+ .chanx_left_in ( sb_1__1__13_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__24_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__24_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__24_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__24_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) ,
+ .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1273 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5934 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[24] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[24] ) ,
+ .pReset_E_in ( pResetWires[169] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5935 ) ,
+ .pReset_W_out ( pResetWires[168] ) , .pReset_S_out ( pResetWires[170] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5936 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[110] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5937 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5938 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[51] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[52] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p3620 ) ,
+ .prog_clk_2_W_in ( p3162 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5939 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5940 ) ,
+ .prog_clk_3_W_in ( p3236 ) , .prog_clk_3_E_in ( p3617 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5941 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5942 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5943 ) ,
+ .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) ,
+ .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p2427 ) ,
+ .clk_2_W_in ( p3068 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p3118 ) ,
+ .clk_3_E_in ( p177 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5947 ) ) ;
+cbx_1__1_ cbx_3__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5948 } ) ,
+ .chanx_left_in ( sb_1__1__14_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__25_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__25_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__25_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__25_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) ,
+ .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1310 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5949 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[25] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[25] ) ,
+ .pReset_E_in ( pResetWires[218] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5950 ) ,
+ .pReset_W_out ( pResetWires[217] ) , .pReset_S_out ( pResetWires[219] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5951 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[113] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5952 ) ,
+ .prog_clk_1_W_in ( p1264 ) , .prog_clk_1_E_in ( p1178 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5953 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5954 ) ,
+ .prog_clk_2_E_in ( p1864 ) , .prog_clk_2_W_in ( p2857 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5955 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5956 ) ,
+ .prog_clk_3_W_in ( p2985 ) , .prog_clk_3_E_in ( p1952 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5957 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_1_W_in ( p1264 ) ,
+ .clk_1_E_in ( p14 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5959 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_2_E_in ( p2231 ) ,
+ .clk_2_W_in ( p334 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p1317 ) ,
+ .clk_3_E_in ( p2834 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5964 ) ) ;
+cbx_1__1_ cbx_3__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5965 } ) ,
+ .chanx_left_in ( sb_1__1__15_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__26_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__26_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__26_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__26_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) ,
+ .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1349 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5966 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[26] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[26] ) ,
+ .pReset_E_in ( pResetWires[267] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5967 ) ,
+ .pReset_W_out ( pResetWires[266] ) , .pReset_S_out ( pResetWires[268] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5968 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[116] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5969 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5970 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[58] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[59] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p3370 ) ,
+ .prog_clk_2_W_in ( p1567 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5971 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5972 ) ,
+ .prog_clk_3_W_in ( p1721 ) , .prog_clk_3_E_in ( p3331 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5973 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5974 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5975 ) ,
+ .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) ,
+ .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p3124 ) ,
+ .clk_2_W_in ( p874 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p1286 ) ,
+ .clk_3_E_in ( p627 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5979 ) ) ;
+cbx_1__1_ cbx_3__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5980 } ) ,
+ .chanx_left_in ( sb_1__1__16_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__27_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__27_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__27_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__27_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) ,
+ .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p1276 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5981 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[27] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[27] ) ,
+ .pReset_E_in ( pResetWires[316] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5982 ) ,
+ .pReset_W_out ( pResetWires[315] ) , .pReset_S_out ( pResetWires[317] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_5983 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[119] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5984 ) ,
+ .prog_clk_1_W_in ( p1065 ) , .prog_clk_1_E_in ( p661 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5985 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5986 ) ,
+ .prog_clk_2_E_in ( p1133 ) , .prog_clk_2_W_in ( p976 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5987 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5988 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5989 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[50] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5990 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p1065 ) ,
+ .clk_1_E_in ( p448 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5991 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5992 ) , .clk_2_E_in ( p1133 ) ,
+ .clk_2_W_in ( p812 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5993 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5994 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5995 ) ,
+ .clk_3_E_in ( clk_3_wires[50] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5996 ) ,
+ .clk_3_W_out ( clk_3_wires[51] ) ) ;
+cbx_1__1_ cbx_3__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_5997 } ) ,
+ .chanx_left_in ( sb_1__1__17_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__28_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__28_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__28_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__28_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) ,
+ .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1131 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5998 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[28] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[28] ) ,
+ .pReset_E_in ( pResetWires[365] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_5999 ) ,
+ .pReset_W_out ( pResetWires[364] ) , .pReset_S_out ( pResetWires[366] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6000 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[122] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6001 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6002 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[65] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[66] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p3619 ) ,
+ .prog_clk_2_W_in ( p3409 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6003 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6004 ) ,
+ .prog_clk_3_W_in ( p3426 ) , .prog_clk_3_E_in ( p3611 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6005 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6006 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6007 ) ,
+ .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) ,
+ .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p1431 ) ,
+ .clk_2_W_in ( p2888 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p2951 ) ,
+ .clk_3_E_in ( p888 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6011 ) ) ;
+cbx_1__1_ cbx_3__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6012 } ) ,
+ .chanx_left_in ( sb_1__1__18_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__29_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__29_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__29_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__29_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) ,
+ .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p1340 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6013 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[29] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[29] ) ,
+ .pReset_E_in ( pResetWires[414] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6014 ) ,
+ .pReset_W_out ( pResetWires[413] ) , .pReset_S_out ( pResetWires[415] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6015 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[125] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6016 ) ,
+ .prog_clk_1_W_in ( p1217 ) , .prog_clk_1_E_in ( p11 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6017 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6018 ) ,
+ .prog_clk_2_E_in ( p2995 ) , .prog_clk_2_W_in ( p3386 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6019 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6020 ) ,
+ .prog_clk_3_W_in ( p3419 ) , .prog_clk_3_E_in ( p2862 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6021 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_1_W_in ( p1217 ) ,
+ .clk_1_E_in ( p1289 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6023 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_2_E_in ( p2668 ) ,
+ .clk_2_W_in ( p2599 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p2688 ) ,
+ .clk_3_E_in ( p564 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6028 ) ) ;
+cbx_1__1_ cbx_3__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6029 } ) ,
+ .chanx_left_in ( sb_1__1__19_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__30_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__30_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__30_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__30_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) ,
+ .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1311 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6030 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[30] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[30] ) ,
+ .pReset_E_in ( pResetWires[463] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6031 ) ,
+ .pReset_W_out ( pResetWires[462] ) , .pReset_S_out ( pResetWires[464] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6032 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[128] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6033 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6034 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[72] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[73] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p3575 ) ,
+ .prog_clk_2_W_in ( p2374 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6035 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6036 ) ,
+ .prog_clk_3_W_in ( p2521 ) , .prog_clk_3_E_in ( p3554 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6037 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6038 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6039 ) ,
+ .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) ,
+ .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p2123 ) ,
+ .clk_2_W_in ( p3028 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p3106 ) ,
+ .clk_3_E_in ( p721 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6043 ) ) ;
+cbx_1__1_ cbx_3__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6044 } ) ,
+ .chanx_left_in ( sb_1__1__20_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__31_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__31_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__31_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__31_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) ,
+ .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1202 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6045 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[31] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[31] ) ,
+ .pReset_E_in ( pResetWires[512] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6046 ) ,
+ .pReset_W_out ( pResetWires[511] ) , .pReset_S_out ( pResetWires[513] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6047 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[131] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6048 ) ,
+ .prog_clk_1_W_in ( p1239 ) , .prog_clk_1_E_in ( p1208 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6049 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6050 ) ,
+ .prog_clk_2_E_in ( p3377 ) , .prog_clk_2_W_in ( p2568 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6051 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6052 ) ,
+ .prog_clk_3_W_in ( p2754 ) , .prog_clk_3_E_in ( p3291 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6053 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_1_W_in ( p1239 ) ,
+ .clk_1_E_in ( p401 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6055 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_2_E_in ( p2931 ) ,
+ .clk_2_W_in ( p2377 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p2502 ) ,
+ .clk_3_E_in ( p465 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6060 ) ) ;
+cbx_1__1_ cbx_3__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6061 } ) ,
+ .chanx_left_in ( sb_1__1__21_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__32_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__32_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__32_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__32_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) ,
+ .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1142 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6062 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[32] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[32] ) ,
+ .pReset_E_in ( pResetWires[561] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6063 ) ,
+ .pReset_W_out ( pResetWires[560] ) , .pReset_S_out ( pResetWires[562] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6064 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[134] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6065 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6066 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[79] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[80] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p1780 ) ,
+ .prog_clk_2_W_in ( p2875 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6067 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6068 ) ,
+ .prog_clk_3_W_in ( p2903 ) , .prog_clk_3_E_in ( p1953 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6069 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6070 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6071 ) ,
+ .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) ,
+ .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p2178 ) ,
+ .clk_2_W_in ( p1904 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p2248 ) ,
+ .clk_3_E_in ( p343 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6075 ) ) ;
+cbx_1__1_ cbx_4__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6076 } ) ,
+ .chanx_left_in ( sb_1__1__22_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__33_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__33_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__33_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__33_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p1393 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6077 ) ,
+ .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[33] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[33] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[33] ) ,
+ .pReset_E_in ( pResetWires[75] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6078 ) ,
+ .pReset_W_out ( pResetWires[74] ) , .pReset_S_out ( pResetWires[76] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6079 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[142] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6080 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[43] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6081 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[47] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p1750 ) ,
+ .prog_clk_2_W_in ( p2036 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6082 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6083 ) ,
+ .prog_clk_3_W_in ( p1990 ) , .prog_clk_3_E_in ( p1603 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6084 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6085 ) ,
+ .clk_1_W_in ( clk_1_wires[43] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6086 ) ,
+ .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) ,
+ .clk_2_E_in ( p1170 ) , .clk_2_W_in ( p1469 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6087 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p1870 ) ,
+ .clk_3_E_in ( p581 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6090 ) ) ;
+cbx_1__1_ cbx_4__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6091 } ) ,
+ .chanx_left_in ( sb_1__1__23_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__34_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__34_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__34_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__34_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p1834 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6092 ) ,
+ .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[34] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[34] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[34] ) ,
+ .pReset_E_in ( pResetWires[124] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6093 ) ,
+ .pReset_W_out ( pResetWires[123] ) , .pReset_S_out ( pResetWires[125] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6094 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[145] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6095 ) ,
+ .prog_clk_1_W_in ( p1248 ) , .prog_clk_1_E_in ( p391 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6096 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6097 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[27] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6098 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[28] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6099 ) ,
+ .prog_clk_3_W_in ( p1130 ) , .prog_clk_3_E_in ( p817 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6100 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) , .clk_1_W_in ( p1248 ) ,
+ .clk_1_E_in ( p1206 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6102 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6103 ) ,
+ .clk_2_E_in ( clk_2_wires[27] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6104 ) ,
+ .clk_2_W_out ( clk_2_wires[28] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1130 ) ,
+ .clk_3_E_in ( p1507 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6107 ) ) ;
+cbx_1__1_ cbx_4__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6108 } ) ,
+ .chanx_left_in ( sb_1__1__24_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__35_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__35_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__35_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__35_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p2438 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6109 ) ,
+ .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[35] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[35] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[35] ) ,
+ .pReset_E_in ( pResetWires[173] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6110 ) ,
+ .pReset_W_out ( pResetWires[172] ) , .pReset_S_out ( pResetWires[174] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6111 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[148] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6112 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[50] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6113 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[54] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p2491 ) ,
+ .prog_clk_2_W_in ( p3461 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6114 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6115 ) ,
+ .prog_clk_3_W_in ( p3494 ) , .prog_clk_3_E_in ( p2262 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6116 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6117 ) ,
+ .clk_1_W_in ( clk_1_wires[50] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6118 ) ,
+ .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) ,
+ .clk_2_E_in ( p1807 ) , .clk_2_W_in ( p2331 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6119 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p2384 ) ,
+ .clk_3_E_in ( p2379 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6122 ) ) ;
+cbx_1__1_ cbx_4__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6123 } ) ,
+ .chanx_left_in ( sb_1__1__25_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__36_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__36_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__36_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__36_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p1829 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6124 ) ,
+ .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[36] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[36] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[36] ) ,
+ .pReset_E_in ( pResetWires[222] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6125 ) ,
+ .pReset_W_out ( pResetWires[221] ) , .pReset_S_out ( pResetWires[223] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6126 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[151] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6127 ) ,
+ .prog_clk_1_W_in ( p1110 ) , .prog_clk_1_E_in ( p371 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6128 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6129 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[36] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6130 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[37] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6131 ) ,
+ .prog_clk_3_W_in ( p2081 ) , .prog_clk_3_E_in ( p853 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6132 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , .clk_1_W_in ( p1110 ) ,
+ .clk_1_E_in ( p833 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6134 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6135 ) ,
+ .clk_2_E_in ( clk_2_wires[36] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6136 ) ,
+ .clk_2_W_out ( clk_2_wires[37] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p2081 ) ,
+ .clk_3_E_in ( p1552 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6139 ) ) ;
+cbx_1__1_ cbx_4__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6140 } ) ,
+ .chanx_left_in ( sb_1__1__26_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__37_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__37_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__37_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__37_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p2115 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6141 ) ,
+ .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[37] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[37] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[37] ) ,
+ .pReset_E_in ( pResetWires[271] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6142 ) ,
+ .pReset_W_out ( pResetWires[270] ) , .pReset_S_out ( pResetWires[272] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6143 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[154] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6144 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[57] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6145 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[61] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p3342 ) ,
+ .prog_clk_2_W_in ( p2628 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6146 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6147 ) ,
+ .prog_clk_3_W_in ( p2721 ) , .prog_clk_3_E_in ( p3311 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6148 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6149 ) ,
+ .clk_1_W_in ( clk_1_wires[57] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6150 ) ,
+ .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) ,
+ .clk_2_E_in ( p1398 ) , .clk_2_W_in ( p2365 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6151 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2511 ) ,
+ .clk_3_E_in ( p1937 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6154 ) ) ;
+cbx_1__1_ cbx_4__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6155 } ) ,
+ .chanx_left_in ( sb_1__1__27_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__38_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__38_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__38_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__38_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1207 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6156 ) ,
+ .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[38] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[38] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[38] ) ,
+ .pReset_E_in ( pResetWires[320] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6157 ) ,
+ .pReset_W_out ( pResetWires[319] ) , .pReset_S_out ( pResetWires[321] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6158 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[157] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6159 ) ,
+ .prog_clk_1_W_in ( p1114 ) , .prog_clk_1_E_in ( p1241 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6160 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6161 ) ,
+ .prog_clk_2_E_in ( p1225 ) , .prog_clk_2_W_in ( p164 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6162 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6163 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6164 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[46] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6165 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p1114 ) ,
+ .clk_1_E_in ( p289 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6166 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6167 ) , .clk_2_E_in ( p1225 ) ,
+ .clk_2_W_in ( p876 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6169 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6170 ) ,
+ .clk_3_E_in ( clk_3_wires[46] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6171 ) ,
+ .clk_3_W_out ( clk_3_wires[47] ) ) ;
+cbx_1__1_ cbx_4__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6172 } ) ,
+ .chanx_left_in ( sb_1__1__28_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__39_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__39_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__39_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__39_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p1628 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6173 ) ,
+ .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[39] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[39] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[39] ) ,
+ .pReset_E_in ( pResetWires[369] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6174 ) ,
+ .pReset_W_out ( pResetWires[368] ) , .pReset_S_out ( pResetWires[370] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6175 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[160] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6176 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[64] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6177 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[68] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p3285 ) ,
+ .prog_clk_2_W_in ( p3201 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6178 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6179 ) ,
+ .prog_clk_3_W_in ( p3256 ) , .prog_clk_3_E_in ( p3187 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6180 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6181 ) ,
+ .clk_1_W_in ( clk_1_wires[64] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6182 ) ,
+ .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) ,
+ .clk_2_E_in ( p2915 ) , .clk_2_W_in ( p2803 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6183 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p2956 ) ,
+ .clk_3_E_in ( p1636 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6186 ) ) ;
+cbx_1__1_ cbx_4__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6187 } ) ,
+ .chanx_left_in ( sb_1__1__29_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__40_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__40_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__40_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__40_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p2204 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6188 ) ,
+ .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[40] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[40] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[40] ) ,
+ .pReset_E_in ( pResetWires[418] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6189 ) ,
+ .pReset_W_out ( pResetWires[417] ) , .pReset_S_out ( pResetWires[419] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6190 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[163] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6191 ) ,
+ .prog_clk_1_W_in ( p1197 ) , .prog_clk_1_E_in ( p277 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6192 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6193 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[49] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6194 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[50] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6195 ) ,
+ .prog_clk_3_W_in ( p1705 ) , .prog_clk_3_E_in ( p947 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6196 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6197 ) , .clk_1_W_in ( p1197 ) ,
+ .clk_1_E_in ( p832 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6199 ) ,
+ .clk_2_E_in ( clk_2_wires[49] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6200 ) ,
+ .clk_2_W_out ( clk_2_wires[50] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1705 ) ,
+ .clk_3_E_in ( p1928 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6203 ) ) ;
+cbx_1__1_ cbx_4__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6204 } ) ,
+ .chanx_left_in ( sb_1__1__30_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__41_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__41_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__41_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__41_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p1257 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6205 ) ,
+ .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[41] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[41] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[41] ) ,
+ .pReset_E_in ( pResetWires[467] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6206 ) ,
+ .pReset_W_out ( pResetWires[466] ) , .pReset_S_out ( pResetWires[468] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6207 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[166] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6208 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[71] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6209 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[75] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p1714 ) ,
+ .prog_clk_2_W_in ( p3070 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6210 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6211 ) ,
+ .prog_clk_3_W_in ( p3096 ) , .prog_clk_3_E_in ( p1555 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6212 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6213 ) ,
+ .clk_1_W_in ( clk_1_wires[71] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6214 ) ,
+ .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) ,
+ .clk_2_E_in ( p1808 ) , .clk_2_W_in ( p3385 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6215 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p3435 ) ,
+ .clk_3_E_in ( p840 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6218 ) ) ;
+cbx_1__1_ cbx_4__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6219 } ) ,
+ .chanx_left_in ( sb_1__1__31_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__42_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__42_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__42_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__42_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p2083 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6220 ) ,
+ .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[42] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[42] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[42] ) ,
+ .pReset_E_in ( pResetWires[516] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6221 ) ,
+ .pReset_W_out ( pResetWires[515] ) , .pReset_S_out ( pResetWires[517] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6222 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[169] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6223 ) ,
+ .prog_clk_1_W_in ( p1383 ) , .prog_clk_1_E_in ( p1060 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6224 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6225 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[62] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6226 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[63] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6227 ) ,
+ .prog_clk_3_W_in ( p1429 ) , .prog_clk_3_E_in ( p1618 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6228 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6229 ) , .clk_1_W_in ( p1188 ) ,
+ .clk_1_E_in ( p298 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6230 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6231 ) ,
+ .clk_2_E_in ( clk_2_wires[62] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6232 ) ,
+ .clk_2_W_out ( clk_2_wires[63] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1429 ) ,
+ .clk_3_E_in ( p1920 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6235 ) ) ;
+cbx_1__1_ cbx_4__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6236 } ) ,
+ .chanx_left_in ( sb_1__1__32_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__43_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__43_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__43_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__43_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p1454 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6237 ) ,
+ .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[43] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[43] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[43] ) ,
+ .pReset_E_in ( pResetWires[565] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6238 ) ,
+ .pReset_W_out ( pResetWires[564] ) , .pReset_S_out ( pResetWires[566] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6239 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[172] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6240 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[78] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6241 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[82] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p3079 ) ,
+ .prog_clk_2_W_in ( p1482 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6242 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6243 ) ,
+ .prog_clk_3_W_in ( p1814 ) , .prog_clk_3_E_in ( p3067 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6244 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6245 ) ,
+ .clk_1_W_in ( clk_1_wires[78] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6246 ) ,
+ .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) ,
+ .clk_2_E_in ( p3131 ) , .clk_2_W_in ( p60 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6247 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p1266 ) ,
+ .clk_3_E_in ( p682 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6250 ) ) ;
+cbx_1__1_ cbx_5__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6251 } ) ,
+ .chanx_left_in ( sb_1__1__33_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__44_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__44_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__44_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__44_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) ,
+ .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1249 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6252 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[44] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[44] ) ,
+ .pReset_E_in ( pResetWires[79] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6253 ) ,
+ .pReset_W_out ( pResetWires[78] ) , .pReset_S_out ( pResetWires[80] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6254 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[180] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6255 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6256 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[86] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[87] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p2932 ) ,
+ .prog_clk_2_W_in ( p2593 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6257 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6258 ) ,
+ .prog_clk_3_W_in ( p2742 ) , .prog_clk_3_E_in ( p2877 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6259 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6260 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6261 ) ,
+ .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) ,
+ .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p1121 ) ,
+ .clk_2_W_in ( p787 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p1263 ) ,
+ .clk_3_E_in ( p883 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6265 ) ) ;
+cbx_1__1_ cbx_5__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6266 } ) ,
+ .chanx_left_in ( sb_1__1__34_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__45_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__45_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__45_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__45_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) ,
+ .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p1648 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6267 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[45] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[45] ) ,
+ .pReset_E_in ( pResetWires[128] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6268 ) ,
+ .pReset_W_out ( pResetWires[127] ) , .pReset_S_out ( pResetWires[129] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6269 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[183] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6270 ) ,
+ .prog_clk_1_W_in ( p1181 ) , .prog_clk_1_E_in ( p206 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6271 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6272 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6273 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[25] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6274 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p940 ) ,
+ .prog_clk_3_E_in ( p2014 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6275 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , .clk_1_W_in ( p1181 ) ,
+ .clk_1_E_in ( p1600 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6277 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6278 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6279 ) ,
+ .clk_2_W_in ( clk_2_wires[25] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6280 ) ,
+ .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p940 ) ,
+ .clk_3_E_in ( p1962 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6282 ) ) ;
+cbx_1__1_ cbx_5__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6283 } ) ,
+ .chanx_left_in ( sb_1__1__35_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__46_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__46_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__46_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__46_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) ,
+ .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1277 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6284 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[46] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[46] ) ,
+ .pReset_E_in ( pResetWires[177] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6285 ) ,
+ .pReset_W_out ( pResetWires[176] ) , .pReset_S_out ( pResetWires[178] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6286 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[186] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6287 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6288 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[93] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[94] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p2525 ) ,
+ .prog_clk_2_W_in ( p3196 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6289 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6290 ) ,
+ .prog_clk_3_W_in ( p3226 ) , .prog_clk_3_E_in ( p2275 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6291 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6292 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6293 ) ,
+ .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) ,
+ .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p1890 ) ,
+ .clk_2_W_in ( p1538 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p1716 ) ,
+ .clk_3_E_in ( p637 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6297 ) ) ;
+cbx_1__1_ cbx_5__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6298 } ) ,
+ .chanx_left_in ( sb_1__1__36_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__47_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__47_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__47_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__47_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) ,
+ .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p2670 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6299 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[47] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[47] ) ,
+ .pReset_E_in ( pResetWires[226] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6300 ) ,
+ .pReset_W_out ( pResetWires[225] ) , .pReset_S_out ( pResetWires[227] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6301 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[189] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6302 ) ,
+ .prog_clk_1_W_in ( p1210 ) , .prog_clk_1_E_in ( p991 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6303 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6304 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6305 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[34] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6306 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1391 ) ,
+ .prog_clk_3_E_in ( p882 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6307 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_1_W_in ( p1210 ) ,
+ .clk_1_E_in ( p2622 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6309 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6310 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6311 ) ,
+ .clk_2_W_in ( clk_2_wires[34] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6312 ) ,
+ .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1391 ) ,
+ .clk_3_E_in ( p233 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6314 ) ) ;
+cbx_1__1_ cbx_5__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6315 } ) ,
+ .chanx_left_in ( sb_1__1__37_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__48_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__48_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__48_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__48_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) ,
+ .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1715 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6316 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[48] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[48] ) ,
+ .pReset_E_in ( pResetWires[275] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6317 ) ,
+ .pReset_W_out ( pResetWires[274] ) , .pReset_S_out ( pResetWires[276] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6318 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[192] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6319 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6320 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[100] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[101] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p2477 ) ,
+ .prog_clk_2_W_in ( p2878 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6321 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6322 ) ,
+ .prog_clk_3_W_in ( p2921 ) , .prog_clk_3_E_in ( p2560 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6323 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6324 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6325 ) ,
+ .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) ,
+ .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p2767 ) ,
+ .clk_2_W_in ( p3320 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p3358 ) ,
+ .clk_3_E_in ( p619 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6329 ) ) ;
+cbx_1__1_ cbx_5__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6330 } ) ,
+ .chanx_left_in ( sb_1__1__38_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__49_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__49_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__49_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__49_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) ,
+ .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p2110 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6331 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[49] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[49] ) ,
+ .pReset_E_in ( pResetWires[324] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6332 ) ,
+ .pReset_W_out ( pResetWires[323] ) , .pReset_S_out ( pResetWires[325] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6333 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[195] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6334 ) ,
+ .prog_clk_1_W_in ( p1176 ) , .prog_clk_1_E_in ( p197 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6335 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6336 ) ,
+ .prog_clk_2_E_in ( p1688 ) , .prog_clk_2_W_in ( p799 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6337 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6338 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6339 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[6] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6340 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p1176 ) ,
+ .clk_1_E_in ( p1964 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6341 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6342 ) , .clk_2_E_in ( p1688 ) ,
+ .clk_2_W_in ( p508 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6343 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6344 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6345 ) ,
+ .clk_3_E_in ( clk_3_wires[6] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6346 ) ,
+ .clk_3_W_out ( clk_3_wires[7] ) ) ;
+cbx_1__1_ cbx_5__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6347 } ) ,
+ .chanx_left_in ( sb_1__1__39_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__50_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__50_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__50_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__50_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) ,
+ .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p1037 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6348 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[50] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[50] ) ,
+ .pReset_E_in ( pResetWires[373] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6349 ) ,
+ .pReset_W_out ( pResetWires[372] ) , .pReset_S_out ( pResetWires[374] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6350 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[198] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6351 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6352 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[107] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[108] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p3490 ) ,
+ .prog_clk_2_W_in ( p3476 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6353 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6354 ) ,
+ .prog_clk_3_W_in ( p3484 ) , .prog_clk_3_E_in ( p3468 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6355 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6356 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6357 ) ,
+ .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) ,
+ .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p2545 ) ,
+ .clk_2_W_in ( p1985 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p2073 ) ,
+ .clk_3_E_in ( p939 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6361 ) ) ;
+cbx_1__1_ cbx_5__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6362 } ) ,
+ .chanx_left_in ( sb_1__1__40_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__51_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__51_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__51_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__51_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) ,
+ .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1139 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6363 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[51] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[51] ) ,
+ .pReset_E_in ( pResetWires[422] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6364 ) ,
+ .pReset_W_out ( pResetWires[421] ) , .pReset_S_out ( pResetWires[423] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6365 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[201] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6366 ) ,
+ .prog_clk_1_W_in ( p1356 ) , .prog_clk_1_E_in ( p15 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6367 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6368 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6369 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[47] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6370 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1088 ) ,
+ .prog_clk_3_E_in ( p409 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6371 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_1_W_in ( p1356 ) ,
+ .clk_1_E_in ( p1123 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6373 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6374 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6375 ) ,
+ .clk_2_W_in ( clk_2_wires[47] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6376 ) ,
+ .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1088 ) ,
+ .clk_3_E_in ( p695 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6378 ) ) ;
+cbx_1__1_ cbx_5__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6379 } ) ,
+ .chanx_left_in ( sb_1__1__41_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__52_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__52_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__52_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__52_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) ,
+ .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1342 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6380 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[52] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[52] ) ,
+ .pReset_E_in ( pResetWires[471] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6381 ) ,
+ .pReset_W_out ( pResetWires[470] ) , .pReset_S_out ( pResetWires[472] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6382 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[204] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6383 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6384 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[114] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[115] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p2075 ) ,
+ .prog_clk_2_W_in ( p2601 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6385 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6386 ) ,
+ .prog_clk_3_W_in ( p2720 ) , .prog_clk_3_E_in ( p2035 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6387 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6388 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6389 ) ,
+ .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) ,
+ .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p2176 ) ,
+ .clk_2_W_in ( p3310 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p3357 ) ,
+ .clk_3_E_in ( p318 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6393 ) ) ;
+cbx_1__1_ cbx_5__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6394 } ) ,
+ .chanx_left_in ( sb_1__1__42_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__53_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__53_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__53_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__53_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) ,
+ .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1400 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6395 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[53] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[53] ) ,
+ .pReset_E_in ( pResetWires[520] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6396 ) ,
+ .pReset_W_out ( pResetWires[519] ) , .pReset_S_out ( pResetWires[521] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6397 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[207] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6398 ) ,
+ .prog_clk_1_W_in ( p1164 ) , .prog_clk_1_E_in ( p307 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6399 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6400 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6401 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[60] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6402 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p1724 ) ,
+ .prog_clk_3_E_in ( p23 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6403 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , .clk_1_W_in ( p1164 ) ,
+ .clk_1_E_in ( p1015 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6405 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6406 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6407 ) ,
+ .clk_2_W_in ( clk_2_wires[60] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6408 ) ,
+ .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p1852 ) ,
+ .clk_3_E_in ( p865 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6410 ) ) ;
+cbx_1__1_ cbx_5__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6411 } ) ,
+ .chanx_left_in ( sb_1__1__43_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__54_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__54_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__54_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__54_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) ,
+ .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1186 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6412 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[54] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[54] ) ,
+ .pReset_E_in ( pResetWires[569] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6413 ) ,
+ .pReset_W_out ( pResetWires[568] ) , .pReset_S_out ( pResetWires[570] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6414 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[210] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6415 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6416 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[121] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[122] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p3103 ) ,
+ .prog_clk_2_W_in ( p3460 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6417 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6418 ) ,
+ .prog_clk_3_W_in ( p3496 ) , .prog_clk_3_E_in ( p3062 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6419 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6420 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6421 ) ,
+ .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) ,
+ .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p2681 ) ,
+ .clk_2_W_in ( p1571 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p1701 ) ,
+ .clk_3_E_in ( p642 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6425 ) ) ;
+cbx_1__1_ cbx_6__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6426 } ) ,
+ .chanx_left_in ( sb_1__1__44_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__55_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__55_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__55_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__55_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p1167 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6427 ) ,
+ .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[55] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[55] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[55] ) ,
+ .pReset_E_in ( pResetWires[83] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6428 ) ,
+ .pReset_W_out ( pResetWires[82] ) , .pReset_S_out ( pResetWires[84] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6429 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[218] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6430 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[85] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6431 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[89] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p3542 ) ,
+ .prog_clk_2_W_in ( p2371 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6432 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6433 ) ,
+ .prog_clk_3_W_in ( p2465 ) , .prog_clk_3_E_in ( p3512 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6434 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6435 ) ,
+ .clk_1_W_in ( clk_1_wires[85] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6436 ) ,
+ .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) ,
+ .clk_2_E_in ( p2978 ) , .clk_2_W_in ( p2858 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6437 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2919 ) ,
+ .clk_3_E_in ( p534 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6440 ) ) ;
+cbx_1__1_ cbx_6__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6441 } ) ,
+ .chanx_left_in ( sb_1__1__45_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__56_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__56_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__56_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__56_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1772 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6442 ) ,
+ .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[56] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[56] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[56] ) ,
+ .pReset_E_in ( pResetWires[132] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6443 ) ,
+ .pReset_W_out ( pResetWires[131] ) , .pReset_S_out ( pResetWires[133] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6444 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[221] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6445 ) ,
+ .prog_clk_1_W_in ( p1252 ) , .prog_clk_1_E_in ( p503 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6446 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6447 ) ,
+ .prog_clk_2_E_in ( p1654 ) , .prog_clk_2_W_in ( p3407 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6448 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6449 ) ,
+ .prog_clk_3_W_in ( p3436 ) , .prog_clk_3_E_in ( p3321 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6450 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_1_W_in ( p1252 ) ,
+ .clk_1_E_in ( p925 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6452 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_2_E_in ( p3356 ) ,
+ .clk_2_W_in ( p3034 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p3119 ) ,
+ .clk_3_E_in ( p1623 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6457 ) ) ;
+cbx_1__1_ cbx_6__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6458 } ) ,
+ .chanx_left_in ( sb_1__1__46_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__57_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__57_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__57_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__57_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p1728 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6459 ) ,
+ .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[57] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[57] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[57] ) ,
+ .pReset_E_in ( pResetWires[181] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6460 ) ,
+ .pReset_W_out ( pResetWires[180] ) , .pReset_S_out ( pResetWires[182] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6461 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[224] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6462 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[92] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6463 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[96] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p2221 ) ,
+ .prog_clk_2_W_in ( p1651 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6464 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6465 ) ,
+ .prog_clk_3_W_in ( p1859 ) , .prog_clk_3_E_in ( p1940 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6466 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6467 ) ,
+ .clk_1_W_in ( clk_1_wires[92] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6468 ) ,
+ .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) ,
+ .clk_2_E_in ( p2056 ) , .clk_2_W_in ( p1903 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6469 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p2202 ) ,
+ .clk_3_E_in ( p1606 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6472 ) ) ;
+cbx_1__1_ cbx_6__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6473 } ) ,
+ .chanx_left_in ( sb_1__1__47_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__58_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__58_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__58_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__58_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p2230 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6474 ) ,
+ .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[58] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[58] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[58] ) ,
+ .pReset_E_in ( pResetWires[230] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6475 ) ,
+ .pReset_W_out ( pResetWires[229] ) , .pReset_S_out ( pResetWires[231] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6476 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[227] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6477 ) ,
+ .prog_clk_1_W_in ( p1320 ) , .prog_clk_1_E_in ( p987 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6478 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6479 ) ,
+ .prog_clk_2_E_in ( p3361 ) , .prog_clk_2_W_in ( p2319 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6480 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6481 ) ,
+ .prog_clk_3_W_in ( p2437 ) , .prog_clk_3_E_in ( p3307 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6482 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_1_W_in ( p1320 ) ,
+ .clk_1_E_in ( p399 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6484 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_2_E_in ( p3244 ) ,
+ .clk_2_W_in ( p2322 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p2528 ) ,
+ .clk_3_E_in ( p1968 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6489 ) ) ;
+cbx_1__1_ cbx_6__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6490 } ) ,
+ .chanx_left_in ( sb_1__1__48_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__59_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__59_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__59_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__59_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p1382 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6491 ) ,
+ .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[59] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[59] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[59] ) ,
+ .pReset_E_in ( pResetWires[279] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6492 ) ,
+ .pReset_W_out ( pResetWires[278] ) , .pReset_S_out ( pResetWires[280] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6493 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[230] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6494 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[99] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6495 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[103] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p3533 ) ,
+ .prog_clk_2_W_in ( p2603 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6496 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6497 ) ,
+ .prog_clk_3_W_in ( p2728 ) , .prog_clk_3_E_in ( p3519 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6498 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6499 ) ,
+ .clk_1_W_in ( clk_1_wires[99] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6500 ) ,
+ .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) ,
+ .clk_2_E_in ( p2423 ) , .clk_2_W_in ( p2349 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6501 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p2469 ) ,
+ .clk_3_E_in ( p979 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6504 ) ) ;
+cbx_1__1_ cbx_6__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6505 } ) ,
+ .chanx_left_in ( sb_1__1__49_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__60_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__60_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__60_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__60_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p1773 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6506 ) ,
+ .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[60] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[60] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[60] ) ,
+ .pReset_E_in ( pResetWires[328] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6507 ) ,
+ .pReset_W_out ( pResetWires[327] ) , .pReset_S_out ( pResetWires[329] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6508 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[233] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6509 ) ,
+ .prog_clk_1_W_in ( p1034 ) , .prog_clk_1_E_in ( p589 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6510 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6511 ) ,
+ .prog_clk_2_E_in ( p1773 ) , .prog_clk_2_W_in ( p783 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6512 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6513 ) ,
+ .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6514 ) ,
+ .prog_clk_3_E_in ( prog_clk_3_wires[2] ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6515 ) ,
+ .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p1034 ) ,
+ .clk_1_E_in ( p1189 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6516 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_2_E_in ( p1773 ) ,
+ .clk_2_W_in ( p567 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6518 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6519 ) ,
+ .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6520 ) ,
+ .clk_3_E_in ( clk_3_wires[2] ) ,
+ .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6521 ) ,
+ .clk_3_W_out ( clk_3_wires[3] ) ) ;
+cbx_1__1_ cbx_6__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6522 } ) ,
+ .chanx_left_in ( sb_1__1__50_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__61_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__61_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__61_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__61_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p1850 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6523 ) ,
+ .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[61] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[61] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[61] ) ,
+ .pReset_E_in ( pResetWires[377] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6524 ) ,
+ .pReset_W_out ( pResetWires[376] ) , .pReset_S_out ( pResetWires[378] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6525 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[236] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6526 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[106] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6527 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[110] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p3546 ) ,
+ .prog_clk_2_W_in ( p2298 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6528 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6529 ) ,
+ .prog_clk_3_W_in ( p2526 ) , .prog_clk_3_E_in ( p3517 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6530 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6531 ) ,
+ .clk_1_W_in ( clk_1_wires[106] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6532 ) ,
+ .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) ,
+ .clk_2_E_in ( p2939 ) , .clk_2_W_in ( p1592 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6533 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p1676 ) ,
+ .clk_3_E_in ( p1582 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6536 ) ) ;
+cbx_1__1_ cbx_6__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6537 } ) ,
+ .chanx_left_in ( sb_1__1__51_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__62_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__62_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__62_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__62_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p1693 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6538 ) ,
+ .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[62] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[62] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[62] ) ,
+ .pReset_E_in ( pResetWires[426] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6539 ) ,
+ .pReset_W_out ( pResetWires[425] ) , .pReset_S_out ( pResetWires[427] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6540 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[239] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6541 ) ,
+ .prog_clk_1_W_in ( p1306 ) , .prog_clk_1_E_in ( p826 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6542 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6543 ) ,
+ .prog_clk_2_E_in ( p1148 ) , .prog_clk_2_W_in ( p1605 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6544 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6545 ) ,
+ .prog_clk_3_W_in ( p1802 ) , .prog_clk_3_E_in ( p1490 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6546 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_1_W_in ( p1306 ) ,
+ .clk_1_E_in ( p473 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6548 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_2_E_in ( p1815 ) ,
+ .clk_2_W_in ( p3051 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p3094 ) ,
+ .clk_3_E_in ( p1653 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6553 ) ) ;
+cbx_1__1_ cbx_6__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6554 } ) ,
+ .chanx_left_in ( sb_1__1__52_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__63_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__63_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__63_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__63_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p2200 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6555 ) ,
+ .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[63] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[63] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[63] ) ,
+ .pReset_E_in ( pResetWires[475] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6556 ) ,
+ .pReset_W_out ( pResetWires[474] ) , .pReset_S_out ( pResetWires[476] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6557 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[242] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6558 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[113] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6559 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[117] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2124 ) ,
+ .prog_clk_2_W_in ( p722 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6560 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6561 ) ,
+ .prog_clk_3_W_in ( p1428 ) , .prog_clk_3_E_in ( p1987 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6562 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6563 ) ,
+ .clk_1_W_in ( clk_1_wires[113] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6564 ) ,
+ .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) ,
+ .clk_2_E_in ( p2151 ) , .clk_2_W_in ( p1980 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6565 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p2246 ) ,
+ .clk_3_E_in ( p2040 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6568 ) ) ;
+cbx_1__1_ cbx_6__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6569 } ) ,
+ .chanx_left_in ( sb_1__1__53_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__64_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__64_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__64_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__64_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p1145 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6570 ) ,
+ .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[64] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[64] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[64] ) ,
+ .pReset_E_in ( pResetWires[524] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6571 ) ,
+ .pReset_W_out ( pResetWires[523] ) , .pReset_S_out ( pResetWires[525] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6572 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[245] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6573 ) ,
+ .prog_clk_1_W_in ( p1223 ) , .prog_clk_1_E_in ( p1171 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6574 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6575 ) ,
+ .prog_clk_2_E_in ( p2743 ) , .prog_clk_2_W_in ( p3388 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6576 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6577 ) ,
+ .prog_clk_3_W_in ( p3430 ) , .prog_clk_3_E_in ( p2652 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6578 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_1_W_in ( p1223 ) ,
+ .clk_1_E_in ( p275 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6580 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_2_E_in ( p2490 ) ,
+ .clk_2_W_in ( p1945 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p2156 ) ,
+ .clk_3_E_in ( p342 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6585 ) ) ;
+cbx_1__1_ cbx_6__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6586 } ) ,
+ .chanx_left_in ( sb_1__1__54_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__65_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__65_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__65_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__65_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p2155 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6587 ) ,
+ .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[65] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[65] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[65] ) ,
+ .pReset_E_in ( pResetWires[573] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_6588 ) ,
+ .pReset_W_out ( pResetWires[572] ) , .pReset_S_out ( pResetWires[574] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_6589 ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[248] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6590 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[120] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6591 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[124] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p3110 ) ,
+ .prog_clk_2_W_in ( p2375 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6592 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6593 ) ,
+ .prog_clk_3_W_in ( p2546 ) , .prog_clk_3_E_in ( p3056 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6594 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6595 ) ,
+ .clk_1_W_in ( clk_1_wires[120] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6596 ) ,
+ .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) ,
+ .clk_2_E_in ( p2682 ) , .clk_2_W_in ( p2598 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6597 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2689 ) ,
+ .clk_3_E_in ( p2005 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6600 ) ) ;
+cbx_1__1_ cbx_7__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6601 } ) ,
+ .chanx_left_in ( sb_1__1__55_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__66_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__66_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__66_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__66_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) ,
+ .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p1869 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6602 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[66] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[66] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6603 ) ,
+ .pReset_W_in ( pResetWires[86] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6604 ) ,
+ .pReset_S_out ( pResetWires[88] ) , .pReset_E_out ( pResetWires[87] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[256] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6605 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6606 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[128] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[129] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p3098 ) ,
+ .prog_clk_2_W_in ( p2018 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6607 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6608 ) ,
+ .prog_clk_3_W_in ( p2179 ) , .prog_clk_3_E_in ( p3057 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6609 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6610 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6611 ) ,
+ .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) ,
+ .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p2127 ) ,
+ .clk_2_W_in ( p2799 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p2981 ) ,
+ .clk_3_E_in ( p948 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6615 ) ) ;
+cbx_1__1_ cbx_7__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6616 } ) ,
+ .chanx_left_in ( sb_1__1__56_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__67_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__67_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__67_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__67_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) ,
+ .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2180 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6617 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[67] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[67] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6618 ) ,
+ .pReset_W_in ( pResetWires[135] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6619 ) ,
+ .pReset_S_out ( pResetWires[137] ) , .pReset_E_out ( pResetWires[136] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[259] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6620 ) ,
+ .prog_clk_1_W_in ( p863 ) , .prog_clk_1_E_in ( p350 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6621 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6622 ) ,
+ .prog_clk_2_E_in ( p2057 ) , .prog_clk_2_W_in ( p2832 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6623 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6624 ) ,
+ .prog_clk_3_W_in ( p2911 ) , .prog_clk_3_E_in ( p1975 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6625 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_1_W_in ( p863 ) ,
+ .clk_1_E_in ( p1958 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6627 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_2_E_in ( p1826 ) ,
+ .clk_2_W_in ( p2591 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2752 ) ,
+ .clk_3_E_in ( p764 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6632 ) ) ;
+cbx_1__1_ cbx_7__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6633 } ) ,
+ .chanx_left_in ( sb_1__1__57_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__68_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__68_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__68_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__68_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) ,
+ .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1720 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6634 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[68] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[68] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6635 ) ,
+ .pReset_W_in ( pResetWires[184] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6636 ) ,
+ .pReset_S_out ( pResetWires[186] ) , .pReset_E_out ( pResetWires[185] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[262] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6637 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6638 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[135] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[136] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p1679 ) ,
+ .prog_clk_2_W_in ( p3301 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6639 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6640 ) ,
+ .prog_clk_3_W_in ( p3354 ) , .prog_clk_3_E_in ( p1595 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6641 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6642 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6643 ) ,
+ .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) ,
+ .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p1399 ) ,
+ .clk_2_W_in ( p140 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p1449 ) ,
+ .clk_3_E_in ( p460 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6647 ) ) ;
+cbx_1__1_ cbx_7__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6648 } ) ,
+ .chanx_left_in ( sb_1__1__58_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__69_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__69_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__69_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__69_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) ,
+ .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1741 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6649 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[69] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[69] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6650 ) ,
+ .pReset_W_in ( pResetWires[233] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6651 ) ,
+ .pReset_S_out ( pResetWires[235] ) , .pReset_E_out ( pResetWires[234] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[265] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6652 ) ,
+ .prog_clk_1_W_in ( p1246 ) , .prog_clk_1_E_in ( p162 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6653 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6654 ) ,
+ .prog_clk_2_E_in ( p3445 ) , .prog_clk_2_W_in ( p3391 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6655 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6656 ) ,
+ .prog_clk_3_W_in ( p3447 ) , .prog_clk_3_E_in ( p3405 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6657 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_1_W_in ( p1246 ) ,
+ .clk_1_E_in ( p1489 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6659 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_2_E_in ( p2540 ) ,
+ .clk_2_W_in ( p1598 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p1880 ) ,
+ .clk_3_E_in ( p1634 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6664 ) ) ;
+cbx_1__1_ cbx_7__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6665 } ) ,
+ .chanx_left_in ( sb_1__1__59_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__70_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__70_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__70_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__70_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) ,
+ .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1094 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6666 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[70] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[70] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6667 ) ,
+ .pReset_W_in ( pResetWires[282] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6668 ) ,
+ .pReset_S_out ( pResetWires[284] ) , .pReset_E_out ( pResetWires[283] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[268] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6669 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6670 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[142] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[143] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p2881 ) ,
+ .prog_clk_2_W_in ( p2849 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6671 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6672 ) ,
+ .prog_clk_3_W_in ( p2976 ) , .prog_clk_3_E_in ( p2892 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6673 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6674 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6675 ) ,
+ .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) ,
+ .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p2172 ) ,
+ .clk_2_W_in ( p1577 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p1893 ) ,
+ .clk_3_E_in ( p470 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6679 ) ) ;
+cbx_1__1_ cbx_7__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6680 } ) ,
+ .chanx_left_in ( sb_1__1__60_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__71_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__71_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__71_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__71_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) ,
+ .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p1625 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6681 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[71] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[71] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6682 ) ,
+ .pReset_W_in ( pResetWires[331] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6683 ) ,
+ .pReset_S_out ( pResetWires[333] ) , .pReset_E_out ( pResetWires[332] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[271] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6684 ) ,
+ .prog_clk_1_W_in ( p1229 ) , .prog_clk_1_E_in ( p51 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6685 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6686 ) ,
+ .prog_clk_2_E_in ( p1339 ) , .prog_clk_2_W_in ( p121 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6687 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6688 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[0] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6689 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[1] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_1_W_in ( p1229 ) ,
+ .clk_1_E_in ( p1512 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6691 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6692 ) , .clk_2_E_in ( p1339 ) ,
+ .clk_2_W_in ( p439 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6693 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6694 ) ,
+ .clk_3_W_in ( clk_3_wires[0] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6695 ) ,
+ .clk_3_E_out ( clk_3_wires[1] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6696 ) ) ;
+cbx_1__1_ cbx_7__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6697 } ) ,
+ .chanx_left_in ( sb_1__1__61_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__72_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__72_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__72_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__72_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) ,
+ .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p803 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6698 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[72] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[72] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6699 ) ,
+ .pReset_W_in ( pResetWires[380] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6700 ) ,
+ .pReset_S_out ( pResetWires[382] ) , .pReset_E_out ( pResetWires[381] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[274] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6701 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6702 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[149] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[150] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p2753 ) ,
+ .prog_clk_2_W_in ( p3047 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6703 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6704 ) ,
+ .prog_clk_3_W_in ( p3116 ) , .prog_clk_3_E_in ( p3026 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6705 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6706 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6707 ) ,
+ .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) ,
+ .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p3107 ) ,
+ .clk_2_W_in ( p3207 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p3224 ) ,
+ .clk_3_E_in ( p590 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6711 ) ) ;
+cbx_1__1_ cbx_7__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6712 } ) ,
+ .chanx_left_in ( sb_1__1__62_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__73_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__73_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__73_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__73_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) ,
+ .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p1658 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6713 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[73] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[73] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6714 ) ,
+ .pReset_W_in ( pResetWires[429] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6715 ) ,
+ .pReset_S_out ( pResetWires[431] ) , .pReset_E_out ( pResetWires[430] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[277] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6716 ) ,
+ .prog_clk_1_W_in ( p1268 ) , .prog_clk_1_E_in ( p215 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6717 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6718 ) ,
+ .prog_clk_2_E_in ( p2784 ) , .prog_clk_2_W_in ( p1514 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6719 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6720 ) ,
+ .prog_clk_3_W_in ( p1785 ) , .prog_clk_3_E_in ( p2565 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6721 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_1_W_in ( p1268 ) ,
+ .clk_1_E_in ( p1526 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6723 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_2_E_in ( p2398 ) ,
+ .clk_2_W_in ( p2623 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p2698 ) ,
+ .clk_3_E_in ( p1565 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6728 ) ) ;
+cbx_1__1_ cbx_7__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6729 } ) ,
+ .chanx_left_in ( sb_1__1__63_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__74_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__74_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__74_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__74_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) ,
+ .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p1827 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6730 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[74] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[74] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6731 ) ,
+ .pReset_W_in ( pResetWires[478] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6732 ) ,
+ .pReset_S_out ( pResetWires[480] ) , .pReset_E_out ( pResetWires[479] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[280] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6733 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6734 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[156] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[157] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p2420 ) ,
+ .prog_clk_2_W_in ( p3412 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6735 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6736 ) ,
+ .prog_clk_3_W_in ( p3440 ) , .prog_clk_3_E_in ( p2373 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6737 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6738 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6739 ) ,
+ .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) ,
+ .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p2426 ) ,
+ .clk_2_W_in ( p1533 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p1754 ) ,
+ .clk_3_E_in ( p565 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6743 ) ) ;
+cbx_1__1_ cbx_7__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6744 } ) ,
+ .chanx_left_in ( sb_1__1__64_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__75_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__75_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__75_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__75_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) ,
+ .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p1360 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6745 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[75] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[75] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6746 ) ,
+ .pReset_W_in ( pResetWires[527] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6747 ) ,
+ .pReset_S_out ( pResetWires[529] ) , .pReset_E_out ( pResetWires[528] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[283] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6748 ) ,
+ .prog_clk_1_W_in ( p1092 ) , .prog_clk_1_E_in ( p347 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6749 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6750 ) ,
+ .prog_clk_2_E_in ( p3077 ) , .prog_clk_2_W_in ( p2306 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6751 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6752 ) ,
+ .prog_clk_3_W_in ( p2404 ) , .prog_clk_3_E_in ( p3024 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6753 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_1_W_in ( p1092 ) ,
+ .clk_1_E_in ( p1079 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6755 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_2_E_in ( p2746 ) ,
+ .clk_2_W_in ( p2551 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p2735 ) ,
+ .clk_3_E_in ( p1591 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6760 ) ) ;
+cbx_1__1_ cbx_7__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6761 } ) ,
+ .chanx_left_in ( sb_1__1__65_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__76_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__76_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__76_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__76_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) ,
+ .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1069 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6762 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[76] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[76] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6763 ) ,
+ .pReset_W_in ( pResetWires[576] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6764 ) ,
+ .pReset_S_out ( pResetWires[578] ) , .pReset_E_out ( pResetWires[577] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[286] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6765 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6766 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[163] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[164] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2909 ) ,
+ .prog_clk_2_W_in ( p2002 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6767 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6768 ) ,
+ .prog_clk_3_W_in ( p2147 ) , .prog_clk_3_E_in ( p2873 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6769 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6770 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6771 ) ,
+ .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) ,
+ .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p1862 ) ,
+ .clk_2_W_in ( p2586 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2782 ) ,
+ .clk_3_E_in ( p621 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6775 ) ) ;
+cbx_1__1_ cbx_8__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6776 } ) ,
+ .chanx_left_in ( sb_1__1__66_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__77_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__77_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__77_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__77_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p1730 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6777 ) ,
+ .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[77] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[77] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[77] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6778 ) ,
+ .pReset_W_in ( pResetWires[90] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6779 ) ,
+ .pReset_S_out ( pResetWires[92] ) , .pReset_E_out ( pResetWires[91] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[294] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6780 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[127] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6781 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[131] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p3493 ) ,
+ .prog_clk_2_W_in ( p2590 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6782 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6783 ) ,
+ .prog_clk_3_W_in ( p2671 ) , .prog_clk_3_E_in ( p3470 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6784 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6785 ) ,
+ .clk_1_W_in ( clk_1_wires[127] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6786 ) ,
+ .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) ,
+ .clk_2_E_in ( p2254 ) , .clk_2_W_in ( p628 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6787 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p1292 ) ,
+ .clk_3_E_in ( p1614 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6790 ) ) ;
+cbx_1__1_ cbx_8__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6791 } ) ,
+ .chanx_left_in ( sb_1__1__67_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__78_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__78_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__78_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__78_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p1857 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6792 ) ,
+ .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[78] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[78] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[78] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6793 ) ,
+ .pReset_W_in ( pResetWires[139] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6794 ) ,
+ .pReset_S_out ( pResetWires[141] ) , .pReset_E_out ( pResetWires[140] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[297] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6795 ) ,
+ .prog_clk_1_W_in ( p1351 ) , .prog_clk_1_E_in ( p452 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6796 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6797 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[71] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6798 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[72] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6799 ) ,
+ .prog_clk_3_W_in ( p1321 ) , .prog_clk_3_E_in ( p1970 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6800 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6801 ) , .clk_1_W_in ( p1351 ) ,
+ .clk_1_E_in ( p1179 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6802 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6803 ) ,
+ .clk_2_E_in ( clk_2_wires[71] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6804 ) ,
+ .clk_2_W_out ( clk_2_wires[72] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p1321 ) ,
+ .clk_3_E_in ( p1995 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6807 ) ) ;
+cbx_1__1_ cbx_8__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6808 } ) ,
+ .chanx_left_in ( sb_1__1__68_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__79_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__79_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__79_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__79_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p1877 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6809 ) ,
+ .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[79] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[79] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[79] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6810 ) ,
+ .pReset_W_in ( pResetWires[188] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6811 ) ,
+ .pReset_S_out ( pResetWires[190] ) , .pReset_E_out ( pResetWires[189] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[300] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6812 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[134] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6813 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[138] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p3531 ) ,
+ .prog_clk_2_W_in ( p2032 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6814 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6815 ) ,
+ .prog_clk_3_W_in ( p2171 ) , .prog_clk_3_E_in ( p3518 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6816 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6817 ) ,
+ .clk_1_W_in ( clk_1_wires[134] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6818 ) ,
+ .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) ,
+ .clk_2_E_in ( p2530 ) , .clk_2_W_in ( p2329 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6819 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2539 ) ,
+ .clk_3_E_in ( p1547 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6822 ) ) ;
+cbx_1__1_ cbx_8__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6823 } ) ,
+ .chanx_left_in ( sb_1__1__69_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__80_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__80_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__80_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__80_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p2144 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6824 ) ,
+ .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[80] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[80] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[80] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6825 ) ,
+ .pReset_W_in ( pResetWires[237] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6826 ) ,
+ .pReset_S_out ( pResetWires[239] ) , .pReset_E_out ( pResetWires[238] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[303] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6827 ) ,
+ .prog_clk_1_W_in ( p1260 ) , .prog_clk_1_E_in ( p301 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6828 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6829 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[80] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6830 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[81] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6831 ) ,
+ .prog_clk_3_W_in ( p1194 ) , .prog_clk_3_E_in ( p885 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6832 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6833 ) , .clk_1_W_in ( p1260 ) ,
+ .clk_1_E_in ( p520 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6834 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6835 ) ,
+ .clk_2_E_in ( clk_2_wires[80] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6836 ) ,
+ .clk_2_W_out ( clk_2_wires[81] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1194 ) ,
+ .clk_3_E_in ( p1924 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6839 ) ) ;
+cbx_1__1_ cbx_8__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6840 } ) ,
+ .chanx_left_in ( sb_1__1__70_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__81_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__81_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__81_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__81_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p2139 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6841 ) ,
+ .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[81] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[81] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[81] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6842 ) ,
+ .pReset_W_in ( pResetWires[286] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6843 ) ,
+ .pReset_S_out ( pResetWires[288] ) , .pReset_E_out ( pResetWires[287] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[306] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6844 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[141] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6845 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[145] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p2392 ) ,
+ .prog_clk_2_W_in ( p2575 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6846 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6847 ) ,
+ .prog_clk_3_W_in ( p2701 ) , .prog_clk_3_E_in ( p2346 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6848 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6849 ) ,
+ .clk_1_W_in ( clk_1_wires[141] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6850 ) ,
+ .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) ,
+ .clk_2_E_in ( p2527 ) , .clk_2_W_in ( p403 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6851 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p1408 ) ,
+ .clk_3_E_in ( p1965 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6854 ) ) ;
+cbx_1__1_ cbx_8__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6855 } ) ,
+ .chanx_left_in ( sb_1__1__71_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__82_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__82_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__82_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__82_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1236 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6856 ) ,
+ .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[82] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[82] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[82] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6857 ) ,
+ .pReset_W_in ( pResetWires[335] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6858 ) ,
+ .pReset_S_out ( pResetWires[337] ) , .pReset_E_out ( pResetWires[336] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[309] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6859 ) ,
+ .prog_clk_1_W_in ( p1244 ) , .prog_clk_1_E_in ( p435 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6860 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6861 ) ,
+ .prog_clk_2_E_in ( p1236 ) , .prog_clk_2_W_in ( p658 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6862 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6863 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[4] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6864 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[5] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_1_W_in ( p1244 ) ,
+ .clk_1_E_in ( p1018 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6866 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_2_E_in ( p1236 ) ,
+ .clk_2_W_in ( p569 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6868 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6869 ) ,
+ .clk_3_W_in ( clk_3_wires[4] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6870 ) ,
+ .clk_3_E_out ( clk_3_wires[5] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6871 ) ) ;
+cbx_1__1_ cbx_8__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6872 } ) ,
+ .chanx_left_in ( sb_1__1__72_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__83_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__83_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__83_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__83_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p1415 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6873 ) ,
+ .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[83] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[83] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[83] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6874 ) ,
+ .pReset_W_in ( pResetWires[384] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6875 ) ,
+ .pReset_S_out ( pResetWires[386] ) , .pReset_E_out ( pResetWires[385] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[312] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6876 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[148] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6877 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[152] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p2930 ) ,
+ .prog_clk_2_W_in ( p2620 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6878 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6879 ) ,
+ .prog_clk_3_W_in ( p2769 ) , .prog_clk_3_E_in ( p2824 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6880 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6881 ) ,
+ .clk_1_W_in ( clk_1_wires[148] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6882 ) ,
+ .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) ,
+ .clk_2_E_in ( p2531 ) , .clk_2_W_in ( p1939 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6883 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p2222 ) ,
+ .clk_3_E_in ( p421 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6886 ) ) ;
+cbx_1__1_ cbx_8__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6887 } ) ,
+ .chanx_left_in ( sb_1__1__73_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__84_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__84_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__84_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__84_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p1259 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6888 ) ,
+ .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[84] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[84] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[84] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6889 ) ,
+ .pReset_W_in ( pResetWires[433] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6890 ) ,
+ .pReset_S_out ( pResetWires[435] ) , .pReset_E_out ( pResetWires[434] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[315] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6891 ) ,
+ .prog_clk_1_W_in ( p1104 ) , .prog_clk_1_E_in ( p22 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6892 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6893 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[93] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6894 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[94] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6895 ) ,
+ .prog_clk_3_W_in ( p1313 ) , .prog_clk_3_E_in ( p513 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6896 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6897 ) , .clk_1_W_in ( p1104 ) ,
+ .clk_1_E_in ( p867 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6898 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6899 ) ,
+ .clk_2_E_in ( clk_2_wires[93] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6900 ) ,
+ .clk_2_W_out ( clk_2_wires[94] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p1313 ) ,
+ .clk_3_E_in ( p794 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6903 ) ) ;
+cbx_1__1_ cbx_8__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6904 } ) ,
+ .chanx_left_in ( sb_1__1__74_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__85_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__85_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__85_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__85_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p1763 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6905 ) ,
+ .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[85] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[85] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[85] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6906 ) ,
+ .pReset_W_in ( pResetWires[482] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6907 ) ,
+ .pReset_S_out ( pResetWires[484] ) , .pReset_E_out ( pResetWires[483] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[318] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6908 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[155] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6909 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[159] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p2781 ) ,
+ .prog_clk_2_W_in ( p2327 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6910 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6911 ) ,
+ .prog_clk_3_W_in ( p2444 ) , .prog_clk_3_E_in ( p2580 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6912 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6913 ) ,
+ .clk_1_W_in ( clk_1_wires[155] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6914 ) ,
+ .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) ,
+ .clk_2_E_in ( p1873 ) , .clk_2_W_in ( p1541 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6915 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p1793 ) ,
+ .clk_3_E_in ( p1622 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6918 ) ) ;
+cbx_1__1_ cbx_8__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6919 } ) ,
+ .chanx_left_in ( sb_1__1__75_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__86_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__86_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__86_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__86_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p2445 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6920 ) ,
+ .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[86] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[86] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[86] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6921 ) ,
+ .pReset_W_in ( pResetWires[531] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6922 ) ,
+ .pReset_S_out ( pResetWires[533] ) , .pReset_E_out ( pResetWires[532] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[321] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6923 ) ,
+ .prog_clk_1_W_in ( p1138 ) , .prog_clk_1_E_in ( p331 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6924 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6925 ) ,
+ .prog_clk_2_E_in ( prog_clk_2_wires[106] ) ,
+ .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6926 ) ,
+ .prog_clk_2_W_out ( prog_clk_2_wires[107] ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6927 ) ,
+ .prog_clk_3_W_in ( p1707 ) , .prog_clk_3_E_in ( p1534 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6928 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6929 ) , .clk_1_W_in ( p1138 ) ,
+ .clk_1_E_in ( p1056 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6930 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6931 ) ,
+ .clk_2_E_in ( clk_2_wires[106] ) ,
+ .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6932 ) ,
+ .clk_2_W_out ( clk_2_wires[107] ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1711 ) ,
+ .clk_3_E_in ( p2291 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6935 ) ) ;
+cbx_1__1_ cbx_8__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6936 } ) ,
+ .chanx_left_in ( sb_1__1__76_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__87_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__87_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__87_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__87_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p1464 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6937 ) ,
+ .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[87] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[87] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[87] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6938 ) ,
+ .pReset_W_in ( pResetWires[580] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6939 ) ,
+ .pReset_S_out ( pResetWires[582] ) , .pReset_E_out ( pResetWires[581] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[324] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6940 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[162] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6941 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[166] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p2505 ) ,
+ .prog_clk_2_W_in ( p3022 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6942 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6943 ) ,
+ .prog_clk_3_W_in ( p3142 ) , .prog_clk_3_E_in ( p2336 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6944 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6945 ) ,
+ .clk_1_W_in ( clk_1_wires[162] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6946 ) ,
+ .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) ,
+ .clk_2_E_in ( p2479 ) , .clk_2_W_in ( p2648 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6947 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2696 ) ,
+ .clk_3_E_in ( p418 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6950 ) ) ;
+cbx_1__1_ cbx_9__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6951 } ) ,
+ .chanx_left_in ( sb_1__1__77_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__88_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__88_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__88_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__88_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) ,
+ .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p1352 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6952 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[88] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[88] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6953 ) ,
+ .pReset_W_in ( pResetWires[94] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6954 ) ,
+ .pReset_S_out ( pResetWires[96] ) , .pReset_E_out ( pResetWires[95] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[332] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6955 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6956 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[170] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[171] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p1352 ) ,
+ .prog_clk_2_W_in ( p2863 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6957 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6958 ) ,
+ .prog_clk_3_W_in ( p2967 ) , .prog_clk_3_E_in ( p2573 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6959 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6960 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6961 ) ,
+ .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) ,
+ .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p2713 ) ,
+ .clk_2_W_in ( p2023 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p2207 ) ,
+ .clk_3_E_in ( p1030 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6965 ) ) ;
+cbx_1__1_ cbx_9__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6966 } ) ,
+ .chanx_left_in ( sb_1__1__78_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__89_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__89_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__89_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__89_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) ,
+ .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1868 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6967 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[89] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[89] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6968 ) ,
+ .pReset_W_in ( pResetWires[143] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6969 ) ,
+ .pReset_S_out ( pResetWires[145] ) , .pReset_E_out ( pResetWires[144] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[335] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6970 ) ,
+ .prog_clk_1_W_in ( p954 ) , .prog_clk_1_E_in ( p959 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6971 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6972 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6973 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[69] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6974 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1461 ) ,
+ .prog_clk_3_E_in ( p1560 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6975 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6976 ) , .clk_1_W_in ( p954 ) ,
+ .clk_1_E_in ( p1574 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6977 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6978 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6979 ) ,
+ .clk_2_W_in ( clk_2_wires[69] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6980 ) ,
+ .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1461 ) ,
+ .clk_3_E_in ( p1513 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6982 ) ) ;
+cbx_1__1_ cbx_9__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6983 } ) ,
+ .chanx_left_in ( sb_1__1__79_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__90_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__90_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__90_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__90_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) ,
+ .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1128 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6984 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[90] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[90] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_6985 ) ,
+ .pReset_W_in ( pResetWires[192] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_6986 ) ,
+ .pReset_S_out ( pResetWires[194] ) , .pReset_E_out ( pResetWires[193] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[338] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6987 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6988 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[177] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[178] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p2458 ) ,
+ .prog_clk_2_W_in ( p2833 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6989 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6990 ) ,
+ .prog_clk_3_W_in ( p2926 ) , .prog_clk_3_E_in ( p2348 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6991 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6992 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6993 ) ,
+ .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) ,
+ .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p2166 ) ,
+ .clk_2_W_in ( p2355 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p2422 ) ,
+ .clk_3_E_in ( p433 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6997 ) ) ;
+cbx_1__1_ cbx_9__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_6998 } ) ,
+ .chanx_left_in ( sb_1__1__80_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__91_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__91_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__91_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__91_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) ,
+ .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1355 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6999 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[91] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[91] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7000 ) ,
+ .pReset_W_in ( pResetWires[241] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7001 ) ,
+ .pReset_S_out ( pResetWires[243] ) , .pReset_E_out ( pResetWires[242] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[341] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7002 ) ,
+ .prog_clk_1_W_in ( p1029 ) , .prog_clk_1_E_in ( p1161 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7003 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7004 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7005 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[78] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7006 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p1183 ) ,
+ .prog_clk_3_E_in ( p1494 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7007 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7008 ) , .clk_1_W_in ( p1029 ) ,
+ .clk_1_E_in ( p374 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7009 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7010 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7011 ) ,
+ .clk_2_W_in ( clk_2_wires[78] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7012 ) ,
+ .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p1183 ) ,
+ .clk_3_E_in ( p1607 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7014 ) ) ;
+cbx_1__1_ cbx_9__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7015 } ) ,
+ .chanx_left_in ( sb_1__1__81_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__92_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__92_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__92_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__92_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) ,
+ .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1435 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7016 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[92] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[92] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7017 ) ,
+ .pReset_W_in ( pResetWires[290] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7018 ) ,
+ .pReset_S_out ( pResetWires[292] ) , .pReset_E_out ( pResetWires[291] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[344] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7019 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7020 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[184] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[185] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p3158 ) ,
+ .prog_clk_2_W_in ( p2805 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7021 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7022 ) ,
+ .prog_clk_3_W_in ( p2913 ) , .prog_clk_3_E_in ( p3031 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7023 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7024 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7025 ) ,
+ .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) ,
+ .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p1284 ) ,
+ .clk_2_W_in ( p3312 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p3347 ) ,
+ .clk_3_E_in ( p620 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7029 ) ) ;
+cbx_1__1_ cbx_9__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7030 } ) ,
+ .chanx_left_in ( sb_1__1__82_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__93_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__93_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__93_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__93_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) ,
+ .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1430 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7031 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[93] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[93] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7032 ) ,
+ .pReset_W_in ( pResetWires[339] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7033 ) ,
+ .pReset_S_out ( pResetWires[341] ) , .pReset_E_out ( pResetWires[340] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[347] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7034 ) ,
+ .prog_clk_1_W_in ( p1303 ) , .prog_clk_1_E_in ( p1120 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7035 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7036 ) ,
+ .prog_clk_2_E_in ( p1776 ) , .prog_clk_2_W_in ( p541 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7037 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7038 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[44] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7039 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[45] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_1_W_in ( p1303 ) ,
+ .clk_1_E_in ( p361 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7041 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7042 ) , .clk_2_E_in ( p1776 ) ,
+ .clk_2_W_in ( p130 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7043 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7044 ) ,
+ .clk_3_W_in ( clk_3_wires[44] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7045 ) ,
+ .clk_3_E_out ( clk_3_wires[45] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7046 ) ) ;
+cbx_1__1_ cbx_9__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7047 } ) ,
+ .chanx_left_in ( sb_1__1__83_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__94_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__94_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__94_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__94_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) ,
+ .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1270 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7048 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[94] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[94] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7049 ) ,
+ .pReset_W_in ( pResetWires[388] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7050 ) ,
+ .pReset_S_out ( pResetWires[390] ) , .pReset_E_out ( pResetWires[389] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[350] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7051 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7052 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[191] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[192] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p2428 ) ,
+ .prog_clk_2_W_in ( p3551 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7053 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7054 ) ,
+ .prog_clk_3_W_in ( p3574 ) , .prog_clk_3_E_in ( p2339 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7055 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7056 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7057 ) ,
+ .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) ,
+ .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p2482 ) ,
+ .clk_2_W_in ( p1919 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p2159 ) ,
+ .clk_3_E_in ( p389 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7061 ) ) ;
+cbx_1__1_ cbx_9__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7062 } ) ,
+ .chanx_left_in ( sb_1__1__84_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__95_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__95_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__95_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__95_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) ,
+ .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p1410 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7063 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[95] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[95] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7064 ) ,
+ .pReset_W_in ( pResetWires[437] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7065 ) ,
+ .pReset_S_out ( pResetWires[439] ) , .pReset_E_out ( pResetWires[438] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[353] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7066 ) ,
+ .prog_clk_1_W_in ( p1049 ) , .prog_clk_1_E_in ( p402 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7067 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7068 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7069 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[91] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7070 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1233 ) ,
+ .prog_clk_3_E_in ( p250 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7071 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) , .clk_1_W_in ( p1049 ) ,
+ .clk_1_E_in ( p898 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7073 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7074 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7075 ) ,
+ .clk_2_W_in ( clk_2_wires[91] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7076 ) ,
+ .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1233 ) ,
+ .clk_3_E_in ( p287 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7078 ) ) ;
+cbx_1__1_ cbx_9__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7079 } ) ,
+ .chanx_left_in ( sb_1__1__85_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__96_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__96_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__96_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__96_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) ,
+ .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1786 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7080 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[96] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[96] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7081 ) ,
+ .pReset_W_in ( pResetWires[486] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7082 ) ,
+ .pReset_S_out ( pResetWires[488] ) , .pReset_E_out ( pResetWires[487] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[356] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7083 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7084 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[198] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[199] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p3247 ) ,
+ .prog_clk_2_W_in ( p3403 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7085 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7086 ) ,
+ .prog_clk_3_W_in ( p3442 ) , .prog_clk_3_E_in ( p3182 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7087 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7088 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7089 ) ,
+ .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) ,
+ .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p2993 ) ,
+ .clk_2_W_in ( p2820 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p2960 ) ,
+ .clk_3_E_in ( p881 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7093 ) ) ;
+cbx_1__1_ cbx_9__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7094 } ) ,
+ .chanx_left_in ( sb_1__1__86_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__97_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__97_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__97_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__97_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) ,
+ .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p2131 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7095 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[97] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[97] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7096 ) ,
+ .pReset_W_in ( pResetWires[535] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7097 ) ,
+ .pReset_S_out ( pResetWires[537] ) , .pReset_E_out ( pResetWires[536] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[359] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7098 ) ,
+ .prog_clk_1_W_in ( p1172 ) , .prog_clk_1_E_in ( p1182 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7099 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7100 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7101 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[104] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7102 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p1404 ) ,
+ .prog_clk_3_E_in ( p1535 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7103 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7104 ) , .clk_1_W_in ( p1172 ) ,
+ .clk_1_E_in ( p1957 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7105 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7106 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7107 ) ,
+ .clk_2_W_in ( clk_2_wires[104] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7108 ) ,
+ .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p1404 ) ,
+ .clk_3_E_in ( p1586 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7110 ) ) ;
+cbx_1__1_ cbx_9__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7111 } ) ,
+ .chanx_left_in ( sb_1__1__87_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__98_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__98_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__98_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__98_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) ,
+ .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1413 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7112 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[98] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[98] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7113 ) ,
+ .pReset_W_in ( pResetWires[584] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7114 ) ,
+ .pReset_S_out ( pResetWires[586] ) , .pReset_E_out ( pResetWires[585] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[362] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7115 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7116 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[205] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[206] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p3508 ) ,
+ .prog_clk_2_W_in ( p2293 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7117 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7118 ) ,
+ .prog_clk_3_W_in ( p2435 ) , .prog_clk_3_E_in ( p3478 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7119 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7120 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7121 ) ,
+ .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) ,
+ .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p2100 ) ,
+ .clk_2_W_in ( p3161 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p3240 ) ,
+ .clk_3_E_in ( p715 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7125 ) ) ;
+cbx_1__1_ cbx_10__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7126 } ) ,
+ .chanx_left_in ( sb_1__1__88_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__99_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__99_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__99_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__99_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1847 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7127 ) ,
+ .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[99] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[99] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[99] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7128 ) ,
+ .pReset_W_in ( pResetWires[98] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7129 ) ,
+ .pReset_S_out ( pResetWires[100] ) , .pReset_E_out ( pResetWires[99] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[370] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7130 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[169] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7131 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[173] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p3374 ) ,
+ .prog_clk_2_W_in ( p2386 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7132 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7133 ) ,
+ .prog_clk_3_W_in ( p2434 ) , .prog_clk_3_E_in ( p3337 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7134 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7135 ) ,
+ .clk_1_W_in ( clk_1_wires[169] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7136 ) ,
+ .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) ,
+ .clk_2_E_in ( p2485 ) , .clk_2_W_in ( p2886 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7137 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p2947 ) ,
+ .clk_3_E_in ( p1671 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7140 ) ) ;
+cbx_1__1_ cbx_10__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7141 } ) ,
+ .chanx_left_in ( sb_1__1__89_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__100_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__100_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__100_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__100_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p1771 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7142 ) ,
+ .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[100] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[100] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[100] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7143 ) ,
+ .pReset_W_in ( pResetWires[147] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7144 ) ,
+ .pReset_S_out ( pResetWires[149] ) , .pReset_E_out ( pResetWires[148] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[373] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7145 ) ,
+ .prog_clk_1_W_in ( p1329 ) , .prog_clk_1_E_in ( p1673 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7146 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7147 ) ,
+ .prog_clk_2_E_in ( p3334 ) , .prog_clk_2_W_in ( p2382 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7148 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7149 ) ,
+ .prog_clk_3_W_in ( p2541 ) , .prog_clk_3_E_in ( p3330 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7150 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_1_W_in ( p1329 ) ,
+ .clk_1_E_in ( p1608 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7152 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_2_E_in ( p1708 ) ,
+ .clk_2_W_in ( p2026 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2238 ) ,
+ .clk_3_E_in ( p1645 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7157 ) ) ;
+cbx_1__1_ cbx_10__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7158 } ) ,
+ .chanx_left_in ( sb_1__1__90_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__101_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__101_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__101_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__101_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p2185 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7159 ) ,
+ .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[101] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[101] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[101] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7160 ) ,
+ .pReset_W_in ( pResetWires[196] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7161 ) ,
+ .pReset_S_out ( pResetWires[198] ) , .pReset_E_out ( pResetWires[197] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[376] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7162 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[176] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7163 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[180] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p3151 ) ,
+ .prog_clk_2_W_in ( p2718 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7164 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7165 ) ,
+ .prog_clk_3_W_in ( p2669 ) , .prog_clk_3_E_in ( p3050 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7166 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7167 ) ,
+ .clk_1_W_in ( clk_1_wires[176] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7168 ) ,
+ .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) ,
+ .clk_2_E_in ( p1821 ) , .clk_2_W_in ( p2649 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7169 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p2717 ) ,
+ .clk_3_E_in ( p2098 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7172 ) ) ;
+cbx_1__1_ cbx_10__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7173 } ) ,
+ .chanx_left_in ( sb_1__1__91_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__102_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__102_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__102_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__102_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p1379 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7174 ) ,
+ .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[102] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[102] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[102] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7175 ) ,
+ .pReset_W_in ( pResetWires[245] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7176 ) ,
+ .pReset_S_out ( pResetWires[247] ) , .pReset_E_out ( pResetWires[246] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[379] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7177 ) ,
+ .prog_clk_1_W_in ( p1209 ) , .prog_clk_1_E_in ( p1554 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7178 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7179 ) ,
+ .prog_clk_2_E_in ( p2673 ) , .prog_clk_2_W_in ( p3341 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7180 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7181 ) ,
+ .prog_clk_3_W_in ( p3316 ) , .prog_clk_3_E_in ( p2654 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7182 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_1_W_in ( p1209 ) ,
+ .clk_1_E_in ( p1810 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7184 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_2_E_in ( p2792 ) ,
+ .clk_2_W_in ( p1309 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p967 ) ,
+ .clk_3_E_in ( p1156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7189 ) ) ;
+cbx_1__1_ cbx_10__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7190 } ) ,
+ .chanx_left_in ( sb_1__1__92_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__103_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__103_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__103_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__103_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p2095 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7191 ) ,
+ .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[103] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[103] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[103] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7192 ) ,
+ .pReset_W_in ( pResetWires[294] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7193 ) ,
+ .pReset_S_out ( pResetWires[296] ) , .pReset_E_out ( pResetWires[295] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[382] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7194 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[183] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7195 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[187] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p2984 ) ,
+ .prog_clk_2_W_in ( p3216 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7196 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7197 ) ,
+ .prog_clk_3_W_in ( p3266 ) , .prog_clk_3_E_in ( p2868 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7198 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7199 ) ,
+ .clk_1_W_in ( clk_1_wires[183] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7200 ) ,
+ .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) ,
+ .clk_2_E_in ( p2416 ) , .clk_2_W_in ( p1559 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7201 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p1664 ) ,
+ .clk_3_E_in ( p1977 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7204 ) ) ;
+cbx_1__1_ cbx_10__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7205 } ) ,
+ .chanx_left_in ( sb_1__1__93_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__104_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__104_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__104_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__104_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1722 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7206 ) ,
+ .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[104] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[104] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[104] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7207 ) ,
+ .pReset_W_in ( pResetWires[343] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7208 ) ,
+ .pReset_S_out ( pResetWires[345] ) , .pReset_E_out ( pResetWires[344] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[385] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7209 ) ,
+ .prog_clk_1_W_in ( p1220 ) , .prog_clk_1_E_in ( p880 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7210 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7211 ) ,
+ .prog_clk_2_E_in ( p1722 ) , .prog_clk_2_W_in ( p1150 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7212 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7213 ) ,
+ .prog_clk_3_W_in ( prog_clk_3_wires[48] ) ,
+ .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7214 ) ,
+ .prog_clk_3_E_out ( prog_clk_3_wires[49] ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_1_W_in ( p1220 ) ,
+ .clk_1_E_in ( p1243 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7216 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7217 ) , .clk_2_E_in ( p1722 ) ,
+ .clk_2_W_in ( p1040 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7218 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7219 ) ,
+ .clk_3_W_in ( clk_3_wires[48] ) ,
+ .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7220 ) ,
+ .clk_3_E_out ( clk_3_wires[49] ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7221 ) ) ;
+cbx_1__1_ cbx_10__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7222 } ) ,
+ .chanx_left_in ( sb_1__1__94_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__105_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__105_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__105_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__105_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1863 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7223 ) ,
+ .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[105] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[105] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[105] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7224 ) ,
+ .pReset_W_in ( pResetWires[392] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7225 ) ,
+ .pReset_S_out ( pResetWires[394] ) , .pReset_E_out ( pResetWires[393] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[388] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7226 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[190] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7227 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[194] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p2488 ) ,
+ .prog_clk_2_W_in ( p1670 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7228 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7229 ) ,
+ .prog_clk_3_W_in ( p1874 ) , .prog_clk_3_E_in ( p2344 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7230 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7231 ) ,
+ .clk_1_W_in ( clk_1_wires[190] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7232 ) ,
+ .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) ,
+ .clk_2_E_in ( p1766 ) , .clk_2_W_in ( p2368 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7233 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p2452 ) ,
+ .clk_3_E_in ( p1686 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7236 ) ) ;
+cbx_1__1_ cbx_10__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7237 } ) ,
+ .chanx_left_in ( sb_1__1__95_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__106_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__106_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__106_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__106_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p2058 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7238 ) ,
+ .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[106] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[106] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[106] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7239 ) ,
+ .pReset_W_in ( pResetWires[441] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7240 ) ,
+ .pReset_S_out ( pResetWires[443] ) , .pReset_E_out ( pResetWires[442] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[391] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7241 ) ,
+ .prog_clk_1_W_in ( p1192 ) , .prog_clk_1_E_in ( p398 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7242 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7243 ) ,
+ .prog_clk_2_E_in ( p3230 ) , .prog_clk_2_W_in ( p1539 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7244 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7245 ) ,
+ .prog_clk_3_W_in ( p1866 ) , .prog_clk_3_E_in ( p3202 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7246 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_1_W_in ( p1192 ) ,
+ .clk_1_E_in ( p1299 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7248 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_2_E_in ( p2136 ) ,
+ .clk_2_W_in ( p2860 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p2916 ) ,
+ .clk_3_E_in ( p2030 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7253 ) ) ;
+cbx_1__1_ cbx_10__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7254 } ) ,
+ .chanx_left_in ( sb_1__1__96_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__107_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__107_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__107_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__107_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p1770 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7255 ) ,
+ .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[107] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[107] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[107] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7256 ) ,
+ .pReset_W_in ( pResetWires[490] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7257 ) ,
+ .pReset_S_out ( pResetWires[492] ) , .pReset_E_out ( pResetWires[491] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[394] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7258 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[197] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7259 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[201] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p2192 ) ,
+ .prog_clk_2_W_in ( p657 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7260 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7261 ) ,
+ .prog_clk_3_W_in ( p1095 ) , .prog_clk_3_E_in ( p2354 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7262 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7263 ) ,
+ .clk_1_W_in ( clk_1_wires[197] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7264 ) ,
+ .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) ,
+ .clk_2_E_in ( p2523 ) , .clk_2_W_in ( p3323 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7265 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p3359 ) ,
+ .clk_3_E_in ( p1647 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7268 ) ) ;
+cbx_1__1_ cbx_10__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7269 } ) ,
+ .chanx_left_in ( sb_1__1__97_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__108_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__108_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__108_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__108_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1378 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7270 ) ,
+ .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[108] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[108] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[108] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7271 ) ,
+ .pReset_W_in ( pResetWires[539] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7272 ) ,
+ .pReset_S_out ( pResetWires[541] ) , .pReset_E_out ( pResetWires[540] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[397] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7273 ) ,
+ .prog_clk_1_W_in ( p1041 ) , .prog_clk_1_E_in ( p716 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7274 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7275 ) ,
+ .prog_clk_2_E_in ( p873 ) , .prog_clk_2_W_in ( p1287 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7276 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7277 ) ,
+ .prog_clk_3_W_in ( p1287 ) , .prog_clk_3_E_in ( p873 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7278 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_1_W_in ( p1041 ) ,
+ .clk_1_E_in ( p716 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7280 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_2_E_in ( p873 ) ,
+ .clk_2_W_in ( p1190 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1190 ) ,
+ .clk_3_E_in ( p1406 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7285 ) ) ;
+cbx_1__1_ cbx_10__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7286 } ) ,
+ .chanx_left_in ( sb_1__1__98_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__109_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__109_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__109_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__109_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p1865 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7287 ) ,
+ .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[109] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[109] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[109] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7288 ) ,
+ .pReset_W_in ( pResetWires[588] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7289 ) ,
+ .pReset_S_out ( pResetWires[590] ) , .pReset_E_out ( pResetWires[589] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[400] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7290 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[204] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7291 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[208] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p1046 ) ,
+ .prog_clk_2_W_in ( p1384 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7292 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7293 ) ,
+ .prog_clk_3_W_in ( p1384 ) , .prog_clk_3_E_in ( p1046 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7294 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7295 ) ,
+ .clk_1_W_in ( clk_1_wires[204] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7296 ) ,
+ .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) ,
+ .clk_2_E_in ( p1046 ) , .clk_2_W_in ( p1137 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7297 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p1137 ) ,
+ .clk_3_E_in ( p1662 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7300 ) ) ;
+cbx_1__1_ cbx_11__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7301 } ) ,
+ .chanx_left_in ( sb_1__1__99_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__110_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__110_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__110_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__110_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) ,
+ .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1363 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7302 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[110] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[110] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7303 ) ,
+ .pReset_W_in ( pResetWires[102] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7304 ) ,
+ .pReset_S_out ( pResetWires[104] ) , .pReset_E_out ( pResetWires[103] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[408] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7305 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7306 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[212] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[213] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p3573 ) ,
+ .prog_clk_2_W_in ( p3416 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7307 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7308 ) ,
+ .prog_clk_3_W_in ( p3432 ) , .prog_clk_3_E_in ( p3566 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7309 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7310 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7311 ) ,
+ .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) ,
+ .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p1419 ) ,
+ .clk_2_W_in ( p2894 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p2963 ) ,
+ .clk_3_E_in ( p995 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7315 ) ) ;
+cbx_1__1_ cbx_11__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7316 } ) ,
+ .chanx_left_in ( sb_1__1__100_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__111_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__111_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__111_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__111_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) ,
+ .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p1427 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7317 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[111] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[111] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7318 ) ,
+ .pReset_W_in ( pResetWires[151] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7319 ) ,
+ .pReset_S_out ( pResetWires[153] ) , .pReset_E_out ( pResetWires[152] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[411] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7320 ) ,
+ .prog_clk_1_W_in ( p1073 ) , .prog_clk_1_E_in ( p612 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7321 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7322 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7323 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[114] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7324 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p1801 ) ,
+ .prog_clk_3_E_in ( p2033 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7325 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7326 ) , .clk_1_W_in ( p1073 ) ,
+ .clk_1_E_in ( p1232 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7327 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7328 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7329 ) ,
+ .clk_2_W_in ( clk_2_wires[114] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7330 ) ,
+ .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1801 ) ,
+ .clk_3_E_in ( p1994 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7332 ) ) ;
+cbx_1__1_ cbx_11__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7333 } ) ,
+ .chanx_left_in ( sb_1__1__101_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__112_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__112_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__112_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__112_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) ,
+ .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p1253 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7334 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[112] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[112] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7335 ) ,
+ .pReset_W_in ( pResetWires[200] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7336 ) ,
+ .pReset_S_out ( pResetWires[202] ) , .pReset_E_out ( pResetWires[201] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[414] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7337 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7338 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[219] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[220] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p3333 ) ,
+ .prog_clk_2_W_in ( p3612 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7339 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7340 ) ,
+ .prog_clk_3_W_in ( p3621 ) , .prog_clk_3_E_in ( p3332 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7341 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7342 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7343 ) ,
+ .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) ,
+ .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2252 ) ,
+ .clk_2_W_in ( p532 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p1411 ) ,
+ .clk_3_E_in ( p971 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7347 ) ) ;
+cbx_1__1_ cbx_11__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7348 } ) ,
+ .chanx_left_in ( sb_1__1__102_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__113_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__113_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__113_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__113_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) ,
+ .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1710 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7349 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[113] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[113] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7350 ) ,
+ .pReset_W_in ( pResetWires[249] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7351 ) ,
+ .pReset_S_out ( pResetWires[251] ) , .pReset_E_out ( pResetWires[250] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[417] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7352 ) ,
+ .prog_clk_1_W_in ( p892 ) , .prog_clk_1_E_in ( p512 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7353 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7354 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7355 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[119] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7356 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1064 ) ,
+ .prog_clk_3_E_in ( p1557 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7357 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7358 ) , .clk_1_W_in ( p892 ) ,
+ .clk_1_E_in ( p1640 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7359 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7360 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7361 ) ,
+ .clk_2_W_in ( clk_2_wires[119] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7362 ) ,
+ .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1064 ) ,
+ .clk_3_E_in ( p1668 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7364 ) ) ;
+cbx_1__1_ cbx_11__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7365 } ) ,
+ .chanx_left_in ( sb_1__1__103_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__114_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__114_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__114_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__114_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) ,
+ .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p1848 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7366 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[114] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[114] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7367 ) ,
+ .pReset_W_in ( pResetWires[298] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7368 ) ,
+ .pReset_S_out ( pResetWires[300] ) , .pReset_E_out ( pResetWires[299] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[420] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7369 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7370 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[226] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[227] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p3149 ) ,
+ .prog_clk_2_W_in ( p2636 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7371 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7372 ) ,
+ .prog_clk_3_W_in ( p2697 ) , .prog_clk_3_E_in ( p3052 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7373 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7374 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7375 ) ,
+ .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) ,
+ .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p2966 ) ,
+ .clk_2_W_in ( p1999 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p2103 ) ,
+ .clk_3_E_in ( p247 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7379 ) ) ;
+cbx_1__1_ cbx_11__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7380 } ) ,
+ .chanx_left_in ( sb_1__1__104_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__115_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__115_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__115_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__115_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) ,
+ .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p1806 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7381 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[115] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[115] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7382 ) ,
+ .pReset_W_in ( pResetWires[347] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7383 ) ,
+ .pReset_S_out ( pResetWires[349] ) , .pReset_E_out ( pResetWires[348] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[423] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7384 ) ,
+ .prog_clk_1_W_in ( p1205 ) , .prog_clk_1_E_in ( p1136 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7385 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7386 ) ,
+ .prog_clk_2_E_in ( p3271 ) , .prog_clk_2_W_in ( p3421 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7387 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7388 ) ,
+ .prog_clk_3_W_in ( p3398 ) , .prog_clk_3_E_in ( p3220 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7389 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_1_W_in ( p1205 ) ,
+ .clk_1_E_in ( p1620 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7391 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_2_E_in ( p2727 ) ,
+ .clk_2_W_in ( p2801 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2989 ) ,
+ .clk_3_E_in ( p1153 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7396 ) ) ;
+cbx_1__1_ cbx_11__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7397 } ) ,
+ .chanx_left_in ( sb_1__1__105_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__116_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__116_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__116_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__116_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) ,
+ .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1425 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7398 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[116] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[116] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7399 ) ,
+ .pReset_W_in ( pResetWires[396] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7400 ) ,
+ .pReset_S_out ( pResetWires[398] ) , .pReset_E_out ( pResetWires[397] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[426] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7401 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7402 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[233] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[234] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p1740 ) ,
+ .prog_clk_2_W_in ( p3066 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7403 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7404 ) ,
+ .prog_clk_3_W_in ( p3076 ) , .prog_clk_3_E_in ( p3025 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7405 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7406 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7407 ) ,
+ .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) ,
+ .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p3075 ) ,
+ .clk_2_W_in ( p1019 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p1412 ) ,
+ .clk_3_E_in ( p1151 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7411 ) ) ;
+cbx_1__1_ cbx_11__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7412 } ) ,
+ .chanx_left_in ( sb_1__1__106_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__117_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__117_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__117_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__117_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) ,
+ .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p2074 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7413 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[117] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[117] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7414 ) ,
+ .pReset_W_in ( pResetWires[445] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7415 ) ,
+ .pReset_S_out ( pResetWires[447] ) , .pReset_E_out ( pResetWires[446] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[429] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7416 ) ,
+ .prog_clk_1_W_in ( p1072 ) , .prog_clk_1_E_in ( p1238 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7417 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7418 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7419 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[126] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7420 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1195 ) ,
+ .prog_clk_3_E_in ( p1675 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7421 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7422 ) , .clk_1_W_in ( p1072 ) ,
+ .clk_1_E_in ( p2007 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7423 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7424 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7425 ) ,
+ .clk_2_W_in ( clk_2_wires[126] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7426 ) ,
+ .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1195 ) ,
+ .clk_3_E_in ( p1615 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7428 ) ) ;
+cbx_1__1_ cbx_11__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7429 } ) ,
+ .chanx_left_in ( sb_1__1__107_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__118_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__118_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__118_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__118_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) ,
+ .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p1247 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7430 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[118] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[118] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7431 ) ,
+ .pReset_W_in ( pResetWires[494] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7432 ) ,
+ .pReset_S_out ( pResetWires[496] ) , .pReset_E_out ( pResetWires[495] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[432] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7433 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7434 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[240] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[241] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p3382 ) ,
+ .prog_clk_2_W_in ( p3290 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7435 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7436 ) ,
+ .prog_clk_3_W_in ( p3335 ) , .prog_clk_3_E_in ( p3326 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7437 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7438 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7439 ) ,
+ .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) ,
+ .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p2749 ) ,
+ .clk_2_W_in ( p2357 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p2403 ) ,
+ .clk_3_E_in ( p1032 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7443 ) ) ;
+cbx_1__1_ cbx_11__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7444 } ) ,
+ .chanx_left_in ( sb_1__1__108_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__119_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__119_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__119_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__119_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) ,
+ .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p1669 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7445 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[119] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[119] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7446 ) ,
+ .pReset_W_in ( pResetWires[543] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7447 ) ,
+ .pReset_S_out ( pResetWires[545] ) , .pReset_E_out ( pResetWires[544] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[435] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7448 ) ,
+ .prog_clk_1_W_in ( p1301 ) , .prog_clk_1_E_in ( p431 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7449 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7450 ) ,
+ .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7451 ) ,
+ .prog_clk_2_W_in ( prog_clk_2_wires[133] ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7452 ) ,
+ .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p2216 ) ,
+ .prog_clk_3_E_in ( p577 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7453 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7454 ) , .clk_1_W_in ( p1301 ) ,
+ .clk_1_E_in ( p1609 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7455 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7456 ) ,
+ .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7457 ) ,
+ .clk_2_W_in ( clk_2_wires[133] ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7458 ) ,
+ .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p2148 ) ,
+ .clk_3_E_in ( p1058 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7460 ) ) ;
+cbx_1__1_ cbx_11__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7461 } ) ,
+ .chanx_left_in ( sb_1__1__109_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__1__120_chanx_left_out ) ,
+ .ccff_head ( sb_1__1__120_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__120_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__120_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) ,
+ .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1274 ) ,
+ .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7462 ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[120] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[120] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7463 ) ,
+ .pReset_W_in ( pResetWires[592] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7464 ) ,
+ .pReset_S_out ( pResetWires[594] ) , .pReset_E_out ( pResetWires[593] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[438] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7465 ) ,
+ .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7466 ) ,
+ .prog_clk_1_E_in ( prog_clk_1_wires[247] ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[248] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p1434 ) ,
+ .prog_clk_2_W_in ( p2358 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7467 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7468 ) ,
+ .prog_clk_3_W_in ( p2407 ) , .prog_clk_3_E_in ( p2663 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7469 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7470 ) ,
+ .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7471 ) ,
+ .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) ,
+ .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p2750 ) ,
+ .clk_2_W_in ( p2380 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p2548 ) ,
+ .clk_3_E_in ( p1096 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7475 ) ) ;
+cbx_1__1_ cbx_12__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7476 } ) ,
+ .chanx_left_in ( sb_1__1__110_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__121_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__121_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p1764 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7477 ) ,
+ .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[121] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[121] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[121] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7478 ) ,
+ .pReset_W_in ( pResetWires[106] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7479 ) ,
+ .pReset_S_out ( pResetWires[108] ) , .pReset_E_out ( pResetWires[107] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[446] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7480 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[211] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7481 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[215] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2954 ) ,
+ .prog_clk_2_W_in ( p3474 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7482 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7483 ) ,
+ .prog_clk_3_W_in ( p3503 ) , .prog_clk_3_E_in ( p2827 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7484 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7485 ) ,
+ .clk_1_W_in ( clk_1_wires[211] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7486 ) ,
+ .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) ,
+ .clk_2_E_in ( p2099 ) , .clk_2_W_in ( p3058 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7487 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p3122 ) ,
+ .clk_3_E_in ( p1556 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7490 ) ) ;
+cbx_1__1_ cbx_12__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7491 } ) ,
+ .chanx_left_in ( sb_1__1__111_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__1_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__122_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__122_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1735 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7492 ) ,
+ .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[122] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[122] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[122] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7493 ) ,
+ .pReset_W_in ( pResetWires[155] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7494 ) ,
+ .pReset_S_out ( pResetWires[157] ) , .pReset_E_out ( pResetWires[156] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[449] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7495 ) ,
+ .prog_clk_1_W_in ( p1218 ) , .prog_clk_1_E_in ( p273 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7496 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7497 ) ,
+ .prog_clk_2_E_in ( p1794 ) , .prog_clk_2_W_in ( p2006 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7498 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7499 ) ,
+ .prog_clk_3_W_in ( p2078 ) , .prog_clk_3_E_in ( p2020 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7500 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_1_W_in ( p1218 ) ,
+ .clk_1_E_in ( p869 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7502 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_2_E_in ( p2249 ) ,
+ .clk_2_W_in ( p2063 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p1943 ) ,
+ .clk_3_E_in ( p1655 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7507 ) ) ;
+cbx_1__1_ cbx_12__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7508 } ) ,
+ .chanx_left_in ( sb_1__1__112_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__2_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__123_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__123_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1267 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7509 ) ,
+ .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[123] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[123] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[123] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7510 ) ,
+ .pReset_W_in ( pResetWires[204] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7511 ) ,
+ .pReset_S_out ( pResetWires[206] ) , .pReset_E_out ( pResetWires[205] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[452] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7512 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[218] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7513 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[222] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p1326 ) ,
+ .prog_clk_2_W_in ( p1661 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7514 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7515 ) ,
+ .prog_clk_3_W_in ( p1881 ) , .prog_clk_3_E_in ( p2869 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7516 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7517 ) ,
+ .clk_1_W_in ( clk_1_wires[218] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7518 ) ,
+ .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) ,
+ .clk_2_E_in ( p2908 ) , .clk_2_W_in ( p3223 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7519 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p3211 ) ,
+ .clk_3_E_in ( p451 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7522 ) ) ;
+cbx_1__1_ cbx_12__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7523 } ) ,
+ .chanx_left_in ( sb_1__1__113_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__3_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__124_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__124_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p2186 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7524 ) ,
+ .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[124] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[124] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[124] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7525 ) ,
+ .pReset_W_in ( pResetWires[253] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7526 ) ,
+ .pReset_S_out ( pResetWires[255] ) , .pReset_E_out ( pResetWires[254] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[455] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7527 ) ,
+ .prog_clk_1_W_in ( p1280 ) , .prog_clk_1_E_in ( p1124 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7528 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7529 ) ,
+ .prog_clk_2_E_in ( p2882 ) , .prog_clk_2_W_in ( p1641 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7530 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7531 ) ,
+ .prog_clk_3_W_in ( p1690 ) , .prog_clk_3_E_in ( p2855 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7532 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_1_W_in ( p1280 ) ,
+ .clk_1_E_in ( p742 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7534 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_2_E_in ( p2710 ) ,
+ .clk_2_W_in ( p2003 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2118 ) ,
+ .clk_3_E_in ( p2054 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7539 ) ) ;
+cbx_1__1_ cbx_12__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7540 } ) ,
+ .chanx_left_in ( sb_1__1__114_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__4_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__125_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__125_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p1817 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7541 ) ,
+ .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[125] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[125] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[125] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7542 ) ,
+ .pReset_W_in ( pResetWires[302] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7543 ) ,
+ .pReset_S_out ( pResetWires[304] ) , .pReset_E_out ( pResetWires[303] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[458] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7544 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[225] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7545 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[229] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p3141 ) ,
+ .prog_clk_2_W_in ( p2046 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7546 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7547 ) ,
+ .prog_clk_3_W_in ( p2198 ) , .prog_clk_3_E_in ( p3041 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7548 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7549 ) ,
+ .clk_1_W_in ( clk_1_wires[225] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7550 ) ,
+ .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) ,
+ .clk_2_E_in ( p2678 ) , .clk_2_W_in ( p2621 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7551 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2675 ) ,
+ .clk_3_E_in ( p1568 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7554 ) ) ;
+cbx_1__1_ cbx_12__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7555 } ) ,
+ .chanx_left_in ( sb_1__1__115_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__5_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__126_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__126_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p2224 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7556 ) ,
+ .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[126] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[126] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[126] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7557 ) ,
+ .pReset_W_in ( pResetWires[351] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7558 ) ,
+ .pReset_S_out ( pResetWires[353] ) , .pReset_E_out ( pResetWires[352] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[461] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7559 ) ,
+ .prog_clk_1_W_in ( p1744 ) , .prog_clk_1_E_in ( p312 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7560 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7561 ) ,
+ .prog_clk_2_E_in ( p3428 ) , .prog_clk_2_W_in ( p3482 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7562 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7563 ) ,
+ .prog_clk_3_W_in ( p3485 ) , .prog_clk_3_E_in ( p3414 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7564 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_1_W_in ( p1744 ) ,
+ .clk_1_E_in ( p1125 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7566 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_2_E_in ( p2779 ) ,
+ .clk_2_W_in ( p2335 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p2495 ) ,
+ .clk_3_E_in ( p2051 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7571 ) ) ;
+cbx_1__1_ cbx_12__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7572 } ) ,
+ .chanx_left_in ( sb_1__1__116_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__6_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__127_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__127_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p2082 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7573 ) ,
+ .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[127] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[127] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[127] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7574 ) ,
+ .pReset_W_in ( pResetWires[400] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7575 ) ,
+ .pReset_S_out ( pResetWires[402] ) , .pReset_E_out ( pResetWires[401] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[464] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7576 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[232] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7577 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[236] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p1696 ) ,
+ .prog_clk_2_W_in ( p2330 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7578 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7579 ) ,
+ .prog_clk_3_W_in ( p2400 ) , .prog_clk_3_E_in ( p2321 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7580 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7581 ) ,
+ .clk_1_W_in ( clk_1_wires[232] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7582 ) ,
+ .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) ,
+ .clk_2_E_in ( p2498 ) , .clk_2_W_in ( p1938 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7583 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p2188 ) ,
+ .clk_3_E_in ( p2044 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7586 ) ) ;
+cbx_1__1_ cbx_12__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7587 } ) ,
+ .chanx_left_in ( sb_1__1__117_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__7_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__128_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__128_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p2402 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7588 ) ,
+ .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[128] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[128] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[128] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7589 ) ,
+ .pReset_W_in ( pResetWires[449] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7590 ) ,
+ .pReset_S_out ( pResetWires[451] ) , .pReset_E_out ( pResetWires[450] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[467] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7591 ) ,
+ .prog_clk_1_W_in ( p1278 ) , .prog_clk_1_E_in ( p327 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7592 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7593 ) ,
+ .prog_clk_2_E_in ( p3580 ) , .prog_clk_2_W_in ( p3048 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7594 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7595 ) ,
+ .prog_clk_3_W_in ( p3127 ) , .prog_clk_3_E_in ( p3552 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7596 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_1_W_in ( p1278 ) ,
+ .clk_1_E_in ( p1100 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7598 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_2_E_in ( p2066 ) ,
+ .clk_2_W_in ( p2597 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p2763 ) ,
+ .clk_3_E_in ( p2383 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7603 ) ) ;
+cbx_1__1_ cbx_12__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7604 } ) ,
+ .chanx_left_in ( sb_1__1__118_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__8_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__129_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__129_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1885 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7605 ) ,
+ .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[129] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[129] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[129] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7606 ) ,
+ .pReset_W_in ( pResetWires[498] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7607 ) ,
+ .pReset_S_out ( pResetWires[500] ) , .pReset_E_out ( pResetWires[499] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[470] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7608 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[239] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7609 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[243] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p2489 ) ,
+ .prog_clk_2_W_in ( p2841 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7610 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7611 ) ,
+ .prog_clk_3_W_in ( p2914 ) , .prog_clk_3_E_in ( p2359 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7612 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7613 ) ,
+ .clk_1_W_in ( clk_1_wires[239] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7614 ) ,
+ .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) ,
+ .clk_2_E_in ( p1639 ) , .clk_2_W_in ( p2890 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7615 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p2990 ) ,
+ .clk_3_E_in ( p1633 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7618 ) ) ;
+cbx_1__1_ cbx_12__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7619 } ) ,
+ .chanx_left_in ( sb_1__1__119_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__9_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__130_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__130_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p1838 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7620 ) ,
+ .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[130] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[130] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[130] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7621 ) ,
+ .pReset_W_in ( pResetWires[547] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7622 ) ,
+ .pReset_S_out ( pResetWires[549] ) , .pReset_E_out ( pResetWires[548] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[473] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7623 ) ,
+ .prog_clk_1_W_in ( p1255 ) , .prog_clk_1_E_in ( p10 ) ,
+ .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7624 ) ,
+ .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7625 ) ,
+ .prog_clk_2_E_in ( p2196 ) , .prog_clk_2_W_in ( p3032 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7626 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7627 ) ,
+ .prog_clk_3_W_in ( p3152 ) , .prog_clk_3_E_in ( p1992 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7628 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_1_W_in ( p1255 ) ,
+ .clk_1_E_in ( p1293 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7630 ) ,
+ .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_2_E_in ( p1016 ) ,
+ .clk_2_W_in ( p2661 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p2733 ) ,
+ .clk_3_E_in ( p1480 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7635 ) ) ;
+cbx_1__1_ cbx_12__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7636 } ) ,
+ .chanx_left_in ( sb_1__1__120_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__1__10_chanx_left_out ) ,
+ .ccff_head ( sb_12__1__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__1__131_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__1__131_chanx_right_out ) ,
+ .bottom_grid_pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p1818 ) ,
+ .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7637 ) ,
+ .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) ,
+ .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) ,
+ .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[131] ) ,
+ .CIN_FEEDTHROUGH ( cin_feedthrough_wires[131] ) ,
+ .COUT_FEEDTHROUGH ( cout_feedthrough_wires[131] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7638 ) ,
+ .pReset_W_in ( pResetWires[596] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7639 ) ,
+ .pReset_S_out ( pResetWires[598] ) , .pReset_E_out ( pResetWires[597] ) ,
+ .prog_clk_0_N_in ( prog_clk_0_wires[476] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7640 ) ,
+ .prog_clk_1_W_in ( prog_clk_1_wires[246] ) ,
+ .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7641 ) ,
+ .prog_clk_1_N_out ( prog_clk_1_wires[250] ) ,
+ .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p2694 ) ,
+ .prog_clk_2_W_in ( p2362 ) ,
+ .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7642 ) ,
+ .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7643 ) ,
+ .prog_clk_3_W_in ( p2412 ) , .prog_clk_3_E_in ( p2604 ) ,
+ .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7644 ) ,
+ .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7645 ) ,
+ .clk_1_W_in ( clk_1_wires[246] ) ,
+ .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7646 ) ,
+ .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) ,
+ .clk_2_E_in ( p1758 ) , .clk_2_W_in ( p1976 ) ,
+ .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7647 ) ,
+ .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p2203 ) ,
+ .clk_3_E_in ( p1619 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) ,
+ .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7650 ) ) ;
+cbx_1__2_ cbx_1__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7651 } ) ,
+ .chanx_left_in ( sb_0__12__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__0_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__0_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__0_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) ,
+ .SC_IN_BOT ( p1416 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7652 ) ,
+ .pReset_E_in ( pResetWires[601] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7653 ) ,
+ .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7654 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[59] ) ,
+ .prog_clk_0_W_out ( prog_clk_0_wires[62] ) ) ;
+cbx_1__2_ cbx_2__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7655 } ) ,
+ .chanx_left_in ( sb_1__12__0_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__1_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__1_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__1_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__1_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1700 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7656 ) ,
+ .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) ,
+ .pReset_E_in ( pResetWires[605] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7657 ) ,
+ .pReset_W_out ( pResetWires[604] ) , .pReset_S_out ( pResetWires[606] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7658 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[99] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7659 ) ) ;
+cbx_1__2_ cbx_3__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7660 } ) ,
+ .chanx_left_in ( sb_1__12__1_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__2_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__2_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__2_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__2_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) ,
+ .SC_IN_BOT ( p1447 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7661 ) ,
+ .pReset_E_in ( pResetWires[608] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7662 ) ,
+ .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7663 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[137] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7664 ) ) ;
+cbx_1__2_ cbx_4__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7665 } ) ,
+ .chanx_left_in ( sb_1__12__2_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__3_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__3_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__3_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__3_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1389 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7666 ) ,
+ .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) ,
+ .pReset_E_in ( pResetWires[611] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7667 ) ,
+ .pReset_W_out ( pResetWires[610] ) , .pReset_S_out ( pResetWires[612] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7668 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[175] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7669 ) ) ;
+cbx_1__2_ cbx_5__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7670 } ) ,
+ .chanx_left_in ( sb_1__12__3_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__4_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__4_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__4_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__4_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) ,
+ .SC_IN_BOT ( p1245 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7671 ) ,
+ .pReset_E_in ( pResetWires[614] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7672 ) ,
+ .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7673 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[213] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7674 ) ) ;
+cbx_1__2_ cbx_6__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7675 } ) ,
+ .chanx_left_in ( sb_1__12__4_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__5_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__5_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__5_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__5_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1222 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7676 ) ,
+ .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) ,
+ .pReset_E_in ( pResetWires[617] ) ,
+ .pReset_W_in ( SYNOPSYS_UNCONNECTED_7677 ) ,
+ .pReset_W_out ( pResetWires[616] ) , .pReset_S_out ( pResetWires[618] ) ,
+ .pReset_E_out ( SYNOPSYS_UNCONNECTED_7678 ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[251] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7679 ) ) ;
+cbx_1__2_ cbx_7__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7680 } ) ,
+ .chanx_left_in ( sb_1__12__5_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__6_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__6_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__6_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__6_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) ,
+ .SC_IN_BOT ( p1118 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7681 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7682 ) ,
+ .pReset_W_in ( pResetWires[619] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7683 ) ,
+ .pReset_S_out ( pResetWires[621] ) , .pReset_E_out ( pResetWires[620] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[289] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7684 ) ) ;
+cbx_1__2_ cbx_8__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7685 } ) ,
+ .chanx_left_in ( sb_1__12__6_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__7_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__7_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__7_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__7_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1281 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7686 ) ,
+ .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7687 ) ,
+ .pReset_W_in ( pResetWires[622] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7688 ) ,
+ .pReset_S_out ( pResetWires[624] ) , .pReset_E_out ( pResetWires[623] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[327] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7689 ) ) ;
+cbx_1__2_ cbx_9__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7690 } ) ,
+ .chanx_left_in ( sb_1__12__7_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__8_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__8_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__8_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__8_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) ,
+ .SC_IN_BOT ( p1219 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7691 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7692 ) ,
+ .pReset_W_in ( pResetWires[625] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7693 ) ,
+ .pReset_S_out ( pResetWires[627] ) , .pReset_E_out ( pResetWires[626] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[365] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7694 ) ) ;
+cbx_1__2_ cbx_10__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7695 } ) ,
+ .chanx_left_in ( sb_1__12__8_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__9_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__9_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__9_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__9_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p1216 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7696 ) ,
+ .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7697 ) ,
+ .pReset_W_in ( pResetWires[628] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7698 ) ,
+ .pReset_S_out ( pResetWires[630] ) , .pReset_E_out ( pResetWires[629] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[403] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7699 ) ) ;
+cbx_1__2_ cbx_11__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7700 } ) ,
+ .chanx_left_in ( sb_1__12__9_chanx_right_out ) ,
+ .chanx_right_in ( sb_1__12__10_chanx_left_out ) ,
+ .ccff_head ( sb_1__12__10_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__10_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__10_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) ,
+ .SC_IN_BOT ( p1254 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7701 ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7702 ) ,
+ .pReset_W_in ( pResetWires[631] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7703 ) ,
+ .pReset_S_out ( pResetWires[633] ) , .pReset_E_out ( pResetWires[632] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[441] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7704 ) ) ;
+cbx_1__2_ cbx_12__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7705 } ) ,
+ .chanx_left_in ( sb_1__12__10_chanx_right_out ) ,
+ .chanx_right_in ( sb_12__12__0_chanx_left_out ) ,
+ .ccff_head ( sb_12__12__0_ccff_tail ) ,
+ .chanx_left_out ( cbx_1__12__11_chanx_left_out ) ,
+ .chanx_right_out ( cbx_1__12__11_chanx_right_out ) ,
+ .top_grid_pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) ,
+ .bottom_grid_pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) ,
+ .bottom_grid_pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) ,
+ .bottom_grid_pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) ,
+ .bottom_grid_pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) ,
+ .bottom_grid_pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) ,
+ .bottom_grid_pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) ,
+ .bottom_grid_pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) ,
+ .bottom_grid_pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) ,
+ .bottom_grid_pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) ,
+ .bottom_grid_pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) ,
+ .bottom_grid_pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) ,
+ .bottom_grid_pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) ,
+ .bottom_grid_pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) ,
+ .bottom_grid_pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) ,
+ .bottom_grid_pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) ,
+ .bottom_grid_pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) ,
+ .ccff_tail ( grid_io_top_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] ) ,
+ .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) ,
+ .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) ,
+ .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) ,
+ .SC_IN_TOP ( p844 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7706 ) ,
+ .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) ,
+ .pReset_E_in ( SYNOPSYS_UNCONNECTED_7707 ) ,
+ .pReset_W_in ( pResetWires[634] ) ,
+ .pReset_W_out ( SYNOPSYS_UNCONNECTED_7708 ) ,
+ .pReset_S_out ( pResetWires[636] ) , .pReset_E_out ( pResetWires[635] ) ,
+ .prog_clk_0_S_in ( prog_clk_0_wires[479] ) ,
+ .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7709 ) ) ;
+cby_0__1_ cby_0__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7710 } ) ,
+ .chany_bottom_in ( sb_0__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__0_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__0_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__0_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[64] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[3] ) ) ;
+cby_0__1_ cby_0__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7711 } ) ,
+ .chany_bottom_in ( sb_0__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__1_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__1_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__1_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[113] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[9] ) ) ;
+cby_0__1_ cby_0__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7712 } ) ,
+ .chany_bottom_in ( sb_0__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__2_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__2_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__2_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[162] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[14] ) ) ;
+cby_0__1_ cby_0__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7713 } ) ,
+ .chany_bottom_in ( sb_0__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__3_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__3_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__3_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[211] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[19] ) ) ;
+cby_0__1_ cby_0__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7714 } ) ,
+ .chany_bottom_in ( sb_0__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__4_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__4_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__4_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[260] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[24] ) ) ;
+cby_0__1_ cby_0__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7715 } ) ,
+ .chany_bottom_in ( sb_0__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__5_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__5_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__5_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[309] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[29] ) ) ;
+cby_0__1_ cby_0__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7716 } ) ,
+ .chany_bottom_in ( sb_0__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__6_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__6_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__6_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[358] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[34] ) ) ;
+cby_0__1_ cby_0__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7717 } ) ,
+ .chany_bottom_in ( sb_0__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__7_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__7_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__7_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[407] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[39] ) ) ;
+cby_0__1_ cby_0__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7718 } ) ,
+ .chany_bottom_in ( sb_0__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__8_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__8_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__8_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[456] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[44] ) ) ;
+cby_0__1_ cby_0__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7719 } ) ,
+ .chany_bottom_in ( sb_0__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__9_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__9_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__9_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[505] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[49] ) ) ;
+cby_0__1_ cby_0__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7720 } ) ,
+ .chany_bottom_in ( sb_0__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_0__1__10_chany_bottom_out ) ,
+ .ccff_head ( sb_0__1__10_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__10_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[554] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[54] ) ) ;
+cby_0__1_ cby_0__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7721 } ) ,
+ .chany_bottom_in ( sb_0__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_0__12__0_chany_bottom_out ) ,
+ .ccff_head ( sb_0__12__0_ccff_tail ) ,
+ .chany_bottom_out ( cby_0__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_0__1__11_chany_top_out ) ,
+ .left_grid_pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) ,
+ .ccff_tail ( grid_io_left_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] ) ,
+ .right_width_0_height_0__pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) ,
+ .right_width_0_height_0__pin_1_upper ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) ,
+ .right_width_0_height_0__pin_1_lower ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) ,
+ .pReset_N_in ( pResetWires[603] ) ,
+ .prog_clk_0_E_in ( prog_clk_0_wires[61] ) ) ;
+cby_1__1_ cby_1__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7722 } ) ,
+ .chany_bottom_in ( sb_1__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_0_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__0_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__0_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7723 ) ,
+ .Test_en_E_in ( Test_enWires[26] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7724 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7725 ) ,
+ .Test_en_W_out ( Test_enWires[24] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7726 ) ,
+ .pReset_S_in ( pResetWires[27] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7727 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7728 ) ,
+ .Reset_E_in ( ResetWires[26] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7729 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7730 ) ,
+ .Reset_W_out ( ResetWires[24] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7731 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[1] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[2] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7732 ) ,
+ .prog_clk_2_N_in ( p2970 ) , .prog_clk_2_S_in ( p698 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7733 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7734 ) ,
+ .prog_clk_3_S_in ( p1433 ) , .prog_clk_3_N_in ( p2837 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7735 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_2_N_in ( p3241 ) ,
+ .clk_2_S_in ( p3023 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p3136 ) ,
+ .clk_3_N_in ( p3198 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7740 ) ) ;
+cby_1__1_ cby_1__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7741 } ) ,
+ .chany_bottom_in ( sb_1__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_1_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__1_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__1_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7742 ) ,
+ .Test_en_E_in ( Test_enWires[48] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7743 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7744 ) ,
+ .Test_en_W_out ( Test_enWires[46] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7745 ) ,
+ .pReset_S_in ( pResetWires[65] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7746 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7747 ) ,
+ .Reset_E_in ( ResetWires[48] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7748 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7749 ) ,
+ .Reset_W_out ( ResetWires[46] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7750 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[7] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[8] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7751 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[3] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7752 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[4] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7753 ) ,
+ .prog_clk_3_S_in ( p1445 ) , .prog_clk_3_N_in ( p942 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7754 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7755 ) ,
+ .clk_2_N_in ( clk_2_wires[3] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7756 ) ,
+ .clk_2_S_out ( clk_2_wires[4] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p1835 ) ,
+ .clk_3_N_in ( p313 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7759 ) ) ;
+cby_1__1_ cby_1__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7760 } ) ,
+ .chany_bottom_in ( sb_1__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_2_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__2_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__2_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7761 ) ,
+ .Test_en_E_in ( Test_enWires[70] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7762 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7763 ) ,
+ .Test_en_W_out ( Test_enWires[68] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7764 ) ,
+ .pReset_S_in ( pResetWires[114] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7765 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7766 ) ,
+ .Reset_E_in ( ResetWires[70] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7767 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7768 ) ,
+ .Reset_W_out ( ResetWires[68] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7769 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[12] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[13] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7770 ) ,
+ .prog_clk_2_N_in ( p2251 ) , .prog_clk_2_S_in ( p2048 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7771 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7772 ) ,
+ .prog_clk_3_S_in ( p2113 ) , .prog_clk_3_N_in ( p1926 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7773 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_2_N_in ( p3355 ) ,
+ .clk_2_S_in ( p3021 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p3134 ) ,
+ .clk_3_N_in ( p3322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7778 ) ) ;
+cby_1__1_ cby_1__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7779 } ) ,
+ .chany_bottom_in ( sb_1__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_3_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__3_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__3_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7780 ) ,
+ .Test_en_E_in ( Test_enWires[92] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7781 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7782 ) ,
+ .Test_en_W_out ( Test_enWires[90] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7783 ) ,
+ .pReset_S_in ( pResetWires[163] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7784 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7785 ) ,
+ .Reset_E_in ( ResetWires[92] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7786 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7787 ) ,
+ .Reset_W_out ( ResetWires[90] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7788 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[17] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[18] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7789 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[10] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7790 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[11] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7791 ) ,
+ .prog_clk_3_S_in ( p2208 ) , .prog_clk_3_N_in ( p436 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7792 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7793 ) ,
+ .clk_2_N_in ( clk_2_wires[10] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7794 ) ,
+ .clk_2_S_out ( clk_2_wires[11] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p2197 ) ,
+ .clk_3_N_in ( p251 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7797 ) ) ;
+cby_1__1_ cby_1__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7798 } ) ,
+ .chany_bottom_in ( sb_1__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_4_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__4_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__4_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7799 ) ,
+ .Test_en_E_in ( Test_enWires[114] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7800 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7801 ) ,
+ .Test_en_W_out ( Test_enWires[112] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7802 ) ,
+ .pReset_S_in ( pResetWires[212] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7803 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7804 ) ,
+ .Reset_E_in ( ResetWires[114] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7805 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7806 ) ,
+ .Reset_W_out ( ResetWires[112] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7807 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[22] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[23] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7808 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7809 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[8] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7810 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p1050 ) ,
+ .prog_clk_3_N_in ( p687 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7811 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7812 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7813 ) ,
+ .clk_2_S_in ( clk_2_wires[8] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7814 ) ,
+ .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p1262 ) ,
+ .clk_3_N_in ( p75 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7816 ) ) ;
+cby_1__1_ cby_1__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7817 } ) ,
+ .chany_bottom_in ( sb_1__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_5_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__5_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__5_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7818 ) ,
+ .Test_en_E_in ( Test_enWires[136] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7819 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7820 ) ,
+ .Test_en_W_out ( Test_enWires[134] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7821 ) ,
+ .pReset_S_in ( pResetWires[261] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7822 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7823 ) ,
+ .Reset_E_in ( ResetWires[136] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7824 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7825 ) ,
+ .Reset_W_out ( ResetWires[134] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7826 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[27] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[28] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7827 ) ,
+ .prog_clk_2_N_in ( p2944 ) , .prog_clk_2_S_in ( p1905 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7828 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7829 ) ,
+ .prog_clk_3_S_in ( p2195 ) , .prog_clk_3_N_in ( p2865 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7830 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_2_N_in ( p2665 ) ,
+ .clk_2_S_in ( p3287 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p3346 ) ,
+ .clk_3_N_in ( p2607 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7835 ) ) ;
+cby_1__1_ cby_1__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7836 } ) ,
+ .chany_bottom_in ( sb_1__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_6_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__6_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__6_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7837 ) ,
+ .Test_en_E_in ( Test_enWires[158] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7838 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7839 ) ,
+ .Test_en_W_out ( Test_enWires[156] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7840 ) ,
+ .pReset_S_in ( pResetWires[310] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7841 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7842 ) ,
+ .Reset_E_in ( ResetWires[158] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7843 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7844 ) ,
+ .Reset_W_out ( ResetWires[156] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7845 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[32] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[33] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7846 ) ,
+ .prog_clk_2_N_in ( p3099 ) , .prog_clk_2_S_in ( p766 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7847 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7848 ) ,
+ .prog_clk_3_S_in ( p1365 ) , .prog_clk_3_N_in ( p3063 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7849 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_2_N_in ( p3649 ) ,
+ .clk_2_S_in ( p3317 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p3367 ) ,
+ .clk_3_N_in ( p3642 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7854 ) ) ;
+cby_1__1_ cby_1__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7855 } ) ,
+ .chany_bottom_in ( sb_1__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_7_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__7_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__7_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7856 ) ,
+ .Test_en_E_in ( Test_enWires[180] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7857 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7858 ) ,
+ .Test_en_W_out ( Test_enWires[178] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7859 ) ,
+ .pReset_S_in ( pResetWires[359] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7860 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7861 ) ,
+ .Reset_E_in ( ResetWires[180] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7862 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7863 ) ,
+ .Reset_W_out ( ResetWires[178] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7864 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[37] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[38] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7865 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[17] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7866 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[18] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7867 ) ,
+ .prog_clk_3_S_in ( p2129 ) , .prog_clk_3_N_in ( p489 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7868 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7869 ) ,
+ .clk_2_N_in ( clk_2_wires[17] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7870 ) ,
+ .clk_2_S_out ( clk_2_wires[18] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p2107 ) ,
+ .clk_3_N_in ( p791 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7873 ) ) ;
+cby_1__1_ cby_1__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7874 } ) ,
+ .chany_bottom_in ( sb_1__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_8_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__8_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__8_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7875 ) ,
+ .Test_en_E_in ( Test_enWires[202] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7876 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7877 ) ,
+ .Test_en_W_out ( Test_enWires[200] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7878 ) ,
+ .pReset_S_in ( pResetWires[408] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7879 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7880 ) ,
+ .Reset_E_in ( ResetWires[202] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7881 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7882 ) ,
+ .Reset_W_out ( ResetWires[200] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7883 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[42] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[43] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7884 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7885 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[15] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7886 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1362 ) ,
+ .prog_clk_3_N_in ( p890 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7887 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7888 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7889 ) ,
+ .clk_2_S_in ( clk_2_wires[15] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7890 ) ,
+ .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1362 ) ,
+ .clk_3_N_in ( p647 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7892 ) ) ;
+cby_1__1_ cby_1__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7893 } ) ,
+ .chany_bottom_in ( sb_1__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_9_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__9_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__9_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7894 ) ,
+ .Test_en_E_in ( Test_enWires[224] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7895 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7896 ) ,
+ .Test_en_W_out ( Test_enWires[222] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7897 ) ,
+ .pReset_S_in ( pResetWires[457] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7898 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7899 ) ,
+ .Reset_E_in ( ResetWires[224] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7900 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7901 ) ,
+ .Reset_W_out ( ResetWires[222] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7902 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[47] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[48] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7903 ) ,
+ .prog_clk_2_N_in ( p1753 ) , .prog_clk_2_S_in ( p1553 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7904 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7905 ) ,
+ .prog_clk_3_S_in ( p1824 ) , .prog_clk_3_N_in ( p1590 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7906 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_2_N_in ( p3143 ) ,
+ .clk_2_S_in ( p2027 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p2061 ) ,
+ .clk_3_N_in ( p3008 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7911 ) ) ;
+cby_1__1_ cby_1__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7912 } ) ,
+ .chany_bottom_in ( sb_1__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_10_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__10_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__10_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7913 ) ,
+ .Test_en_E_in ( Test_enWires[246] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7914 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7915 ) ,
+ .Test_en_W_out ( Test_enWires[244] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7916 ) ,
+ .pReset_S_in ( pResetWires[506] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7917 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7918 ) ,
+ .Reset_E_in ( ResetWires[246] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7919 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7920 ) ,
+ .Reset_W_out ( ResetWires[244] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7921 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[52] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[53] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7922 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7923 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[22] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7924 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1381 ) ,
+ .prog_clk_3_N_in ( p82 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7925 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7926 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7927 ) ,
+ .clk_2_S_in ( clk_2_wires[22] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7928 ) ,
+ .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1381 ) ,
+ .clk_3_N_in ( p802 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7930 ) ) ;
+cby_1__1_ cby_1__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7931 } ) ,
+ .chany_bottom_in ( sb_1__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_11_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__11_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__11_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7932 ) ,
+ .Test_en_E_in ( Test_enWires[268] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7933 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7934 ) ,
+ .Test_en_W_out ( Test_enWires[266] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7935 ) ,
+ .pReset_S_in ( pResetWires[555] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7936 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7937 ) ,
+ .Reset_E_in ( ResetWires[268] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7938 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7939 ) ,
+ .Reset_W_out ( ResetWires[266] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7940 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[57] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[58] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p3499 ) ,
+ .prog_clk_2_S_in ( p2047 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7941 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7942 ) ,
+ .prog_clk_3_S_in ( p1966 ) , .prog_clk_3_N_in ( p3457 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7943 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_2_N_in ( p2065 ) ,
+ .clk_2_S_in ( p3049 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p3148 ) ,
+ .clk_3_N_in ( p1946 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7948 ) ) ;
+cby_1__1_ cby_2__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7949 } ) ,
+ .chany_bottom_in ( sb_1__0__1_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__11_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_12_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__12_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__12_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__12_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7950 ) ,
+ .Test_en_E_in ( Test_enWires[28] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7951 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7952 ) ,
+ .Test_en_W_out ( Test_enWires[25] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7953 ) ,
+ .pReset_S_in ( pResetWires[30] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7954 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7955 ) ,
+ .Reset_E_in ( ResetWires[28] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7956 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7957 ) ,
+ .Reset_W_out ( ResetWires[25] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7958 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[64] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[65] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7959 ) ,
+ .prog_clk_2_N_in ( p2958 ) , .prog_clk_2_S_in ( p1613 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7960 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7961 ) ,
+ .prog_clk_3_S_in ( p1713 ) , .prog_clk_3_N_in ( p2813 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7962 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_2_N_in ( p2729 ) ,
+ .clk_2_S_in ( p3002 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p3126 ) ,
+ .clk_3_N_in ( p2569 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7967 ) ) ;
+cby_1__1_ cby_2__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7968 } ) ,
+ .chany_bottom_in ( sb_1__1__11_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__12_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_13_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__13_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__13_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__13_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7969 ) ,
+ .Test_en_E_in ( Test_enWires[50] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7970 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7971 ) ,
+ .Test_en_W_out ( Test_enWires[47] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7972 ) ,
+ .pReset_S_in ( pResetWires[69] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7973 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7974 ) ,
+ .Reset_E_in ( ResetWires[50] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7975 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7976 ) ,
+ .Reset_W_out ( ResetWires[47] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7977 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[67] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[68] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7978 ) ,
+ .prog_clk_2_N_in ( p3246 ) , .prog_clk_2_S_in ( p2045 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7979 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7980 ) ,
+ .prog_clk_3_S_in ( p2201 ) , .prog_clk_3_N_in ( p3167 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7981 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_2_N_in ( p2748 ) ,
+ .clk_2_S_in ( p2655 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p2785 ) ,
+ .clk_3_N_in ( p2582 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7986 ) ) ;
+cby_1__1_ cby_2__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_7987 } ) ,
+ .chany_bottom_in ( sb_1__1__12_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__13_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_14_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__14_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__14_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__14_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7988 ) ,
+ .Test_en_E_in ( Test_enWires[72] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7989 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7990 ) ,
+ .Test_en_W_out ( Test_enWires[69] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7991 ) ,
+ .pReset_S_in ( pResetWires[118] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_7992 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_7993 ) ,
+ .Reset_E_in ( ResetWires[72] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_7994 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_7995 ) ,
+ .Reset_W_out ( ResetWires[69] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_7996 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[70] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[71] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7997 ) ,
+ .prog_clk_2_N_in ( p1703 ) , .prog_clk_2_S_in ( p456 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7998 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7999 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8000 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[68] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8001 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1703 ) ,
+ .clk_2_S_in ( p1107 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8002 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8003 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8004 ) ,
+ .clk_3_N_in ( clk_3_wires[68] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8005 ) ,
+ .clk_3_S_out ( clk_3_wires[69] ) ) ;
+cby_1__1_ cby_2__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8006 } ) ,
+ .chany_bottom_in ( sb_1__1__13_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__14_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_15_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__15_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__15_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__15_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8007 ) ,
+ .Test_en_E_in ( Test_enWires[94] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8008 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8009 ) ,
+ .Test_en_W_out ( Test_enWires[91] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8010 ) ,
+ .pReset_S_in ( pResetWires[167] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8011 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8012 ) ,
+ .Reset_E_in ( ResetWires[94] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8013 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8014 ) ,
+ .Reset_W_out ( ResetWires[91] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8015 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[73] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[74] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8016 ) ,
+ .prog_clk_2_N_in ( p1302 ) , .prog_clk_2_S_in ( p1922 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8017 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8018 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8019 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[64] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8020 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1302 ) ,
+ .clk_2_S_in ( p372 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8021 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8022 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8023 ) ,
+ .clk_3_N_in ( clk_3_wires[64] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8024 ) ,
+ .clk_3_S_out ( clk_3_wires[65] ) ) ;
+cby_1__1_ cby_2__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8025 } ) ,
+ .chany_bottom_in ( sb_1__1__14_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__15_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_16_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__16_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__16_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__16_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8026 ) ,
+ .Test_en_E_in ( Test_enWires[116] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8027 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8028 ) ,
+ .Test_en_W_out ( Test_enWires[113] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8029 ) ,
+ .pReset_S_in ( pResetWires[216] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8030 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8031 ) ,
+ .Reset_E_in ( ResetWires[116] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8032 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8033 ) ,
+ .Reset_W_out ( ResetWires[113] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8034 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[76] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[77] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8035 ) ,
+ .prog_clk_2_N_in ( p2138 ) , .prog_clk_2_S_in ( p1972 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8036 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8037 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8038 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[58] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8039 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p2138 ) ,
+ .clk_2_S_in ( p291 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8040 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8041 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8042 ) ,
+ .clk_3_N_in ( clk_3_wires[58] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8043 ) ,
+ .clk_3_S_out ( clk_3_wires[59] ) ) ;
+cby_1__1_ cby_2__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8044 } ) ,
+ .chany_bottom_in ( sb_1__1__15_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__16_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_17_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__17_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__17_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__17_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8045 ) ,
+ .Test_en_E_in ( Test_enWires[138] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8046 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8047 ) ,
+ .Test_en_W_out ( Test_enWires[135] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8048 ) ,
+ .pReset_S_in ( pResetWires[265] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8049 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8050 ) ,
+ .Reset_E_in ( ResetWires[138] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8051 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8052 ) ,
+ .Reset_W_out ( ResetWires[135] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8053 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[79] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[80] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8054 ) ,
+ .prog_clk_2_N_in ( p1788 ) , .prog_clk_2_S_in ( p1929 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8055 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8056 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8057 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[54] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8058 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p1788 ) ,
+ .clk_2_S_in ( p461 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8059 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8060 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8061 ) ,
+ .clk_3_N_in ( clk_3_wires[54] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8062 ) ,
+ .clk_3_S_out ( clk_3_wires[55] ) ) ;
+cby_1__1_ cby_2__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8063 } ) ,
+ .chany_bottom_in ( sb_1__1__16_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__17_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_18_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__18_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__18_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__18_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8064 ) ,
+ .Test_en_E_in ( Test_enWires[160] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8065 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8066 ) ,
+ .Test_en_W_out ( Test_enWires[157] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8067 ) ,
+ .pReset_S_in ( pResetWires[314] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8068 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8069 ) ,
+ .Reset_E_in ( ResetWires[160] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8070 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8071 ) ,
+ .Reset_W_out ( ResetWires[157] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8072 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[82] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[83] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8073 ) ,
+ .prog_clk_2_N_in ( p1421 ) , .prog_clk_2_S_in ( p651 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8074 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8075 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[52] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8076 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[53] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8077 ) , .clk_2_N_in ( p1421 ) ,
+ .clk_2_S_in ( p2269 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8078 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8079 ) ,
+ .clk_3_S_in ( clk_3_wires[52] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8080 ) ,
+ .clk_3_N_out ( clk_3_wires[53] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8081 ) ) ;
+cby_1__1_ cby_2__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8082 } ) ,
+ .chany_bottom_in ( sb_1__1__17_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__18_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_19_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__19_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__19_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__19_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8083 ) ,
+ .Test_en_E_in ( Test_enWires[182] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8084 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8085 ) ,
+ .Test_en_W_out ( Test_enWires[179] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8086 ) ,
+ .pReset_S_in ( pResetWires[363] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8087 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8088 ) ,
+ .Reset_E_in ( ResetWires[182] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8089 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8090 ) ,
+ .Reset_W_out ( ResetWires[179] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8091 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[85] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[86] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8092 ) ,
+ .prog_clk_2_N_in ( p1002 ) , .prog_clk_2_S_in ( p2263 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8093 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8094 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[56] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8095 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[57] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , .clk_2_N_in ( p1002 ) ,
+ .clk_2_S_in ( p66 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8097 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8098 ) ,
+ .clk_3_S_in ( clk_3_wires[56] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8099 ) ,
+ .clk_3_N_out ( clk_3_wires[57] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8100 ) ) ;
+cby_1__1_ cby_2__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8101 } ) ,
+ .chany_bottom_in ( sb_1__1__18_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__19_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_20_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__20_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__20_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__20_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8102 ) ,
+ .Test_en_E_in ( Test_enWires[204] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8103 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8104 ) ,
+ .Test_en_W_out ( Test_enWires[201] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8105 ) ,
+ .pReset_S_in ( pResetWires[412] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8106 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8107 ) ,
+ .Reset_E_in ( ResetWires[204] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8108 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8109 ) ,
+ .Reset_W_out ( ResetWires[201] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8110 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[88] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[89] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8111 ) ,
+ .prog_clk_2_N_in ( p1315 ) , .prog_clk_2_S_in ( p1978 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8112 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8113 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[62] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8114 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[63] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8115 ) , .clk_2_N_in ( p1315 ) ,
+ .clk_2_S_in ( p920 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8116 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8117 ) ,
+ .clk_3_S_in ( clk_3_wires[62] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8118 ) ,
+ .clk_3_N_out ( clk_3_wires[63] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8119 ) ) ;
+cby_1__1_ cby_2__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8120 } ) ,
+ .chany_bottom_in ( sb_1__1__19_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__20_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_21_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__21_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__21_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__21_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8121 ) ,
+ .Test_en_E_in ( Test_enWires[226] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8122 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8123 ) ,
+ .Test_en_W_out ( Test_enWires[223] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8124 ) ,
+ .pReset_S_in ( pResetWires[461] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8125 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8126 ) ,
+ .Reset_E_in ( ResetWires[226] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8127 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8128 ) ,
+ .Reset_W_out ( ResetWires[223] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8129 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[91] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[92] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8130 ) ,
+ .prog_clk_2_N_in ( p1759 ) , .prog_clk_2_S_in ( p1988 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8131 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8132 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[66] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8133 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[67] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8134 ) , .clk_2_N_in ( p1759 ) ,
+ .clk_2_S_in ( p927 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8135 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8136 ) ,
+ .clk_3_S_in ( clk_3_wires[66] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8137 ) ,
+ .clk_3_N_out ( clk_3_wires[67] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8138 ) ) ;
+cby_1__1_ cby_2__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8139 } ) ,
+ .chany_bottom_in ( sb_1__1__20_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__21_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_22_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__22_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__22_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__22_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8140 ) ,
+ .Test_en_E_in ( Test_enWires[248] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8141 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8142 ) ,
+ .Test_en_W_out ( Test_enWires[245] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8143 ) ,
+ .pReset_S_in ( pResetWires[510] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8144 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8145 ) ,
+ .Reset_E_in ( ResetWires[248] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8146 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8147 ) ,
+ .Reset_W_out ( ResetWires[245] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8148 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[94] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[95] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8149 ) ,
+ .prog_clk_2_N_in ( p2111 ) , .prog_clk_2_S_in ( p1961 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8150 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8151 ) ,
+ .prog_clk_3_S_in ( p2121 ) , .prog_clk_3_N_in ( p2049 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8152 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_2_N_in ( p2778 ) ,
+ .clk_2_S_in ( p2060 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p2255 ) ,
+ .clk_3_N_in ( p2574 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8157 ) ) ;
+cby_1__1_ cby_2__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8158 } ) ,
+ .chany_bottom_in ( sb_1__1__21_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_23_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__23_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__23_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__23_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8159 ) ,
+ .Test_en_E_in ( Test_enWires[270] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8160 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8161 ) ,
+ .Test_en_W_out ( Test_enWires[267] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8162 ) ,
+ .pReset_S_in ( pResetWires[559] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8163 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8164 ) ,
+ .Reset_E_in ( ResetWires[270] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8165 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8166 ) ,
+ .Reset_W_out ( ResetWires[267] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8167 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[97] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[98] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p1858 ) ,
+ .prog_clk_2_S_in ( p952 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8168 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8169 ) ,
+ .prog_clk_3_S_in ( p1275 ) , .prog_clk_3_N_in ( p1493 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8170 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_2_N_in ( p2974 ) ,
+ .clk_2_S_in ( p3071 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p3129 ) ,
+ .clk_3_N_in ( p2823 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8175 ) ) ;
+cby_1__1_ cby_3__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8176 } ) ,
+ .chany_bottom_in ( sb_1__0__2_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__22_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_24_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__24_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__24_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__24_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8177 ) ,
+ .Test_en_E_in ( Test_enWires[30] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8178 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8179 ) ,
+ .Test_en_W_out ( Test_enWires[27] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8180 ) ,
+ .pReset_S_in ( pResetWires[33] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8181 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8182 ) ,
+ .Reset_E_in ( ResetWires[30] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8183 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8184 ) ,
+ .Reset_W_out ( ResetWires[27] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8185 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[102] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[103] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8186 ) ,
+ .prog_clk_2_N_in ( p1898 ) , .prog_clk_2_S_in ( p2303 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8187 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8188 ) ,
+ .prog_clk_3_S_in ( p2538 ) , .prog_clk_3_N_in ( p1637 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8189 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_2_N_in ( p2235 ) ,
+ .clk_2_S_in ( p1931 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p2092 ) ,
+ .clk_3_N_in ( p1908 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8194 ) ) ;
+cby_1__1_ cby_3__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8195 } ) ,
+ .chany_bottom_in ( sb_1__1__22_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__23_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_25_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__25_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__25_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__25_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8196 ) ,
+ .Test_en_E_in ( Test_enWires[52] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8197 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8198 ) ,
+ .Test_en_W_out ( Test_enWires[49] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8199 ) ,
+ .pReset_S_in ( pResetWires[73] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8200 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8201 ) ,
+ .Reset_E_in ( ResetWires[52] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8202 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8203 ) ,
+ .Reset_W_out ( ResetWires[49] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8204 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[105] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[106] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8205 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[29] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8206 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[30] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8207 ) ,
+ .prog_clk_3_S_in ( p1677 ) , .prog_clk_3_N_in ( p977 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8208 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8209 ) ,
+ .clk_2_N_in ( clk_2_wires[29] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8210 ) ,
+ .clk_2_S_out ( clk_2_wires[30] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p1681 ) ,
+ .clk_3_N_in ( p77 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8213 ) ) ;
+cby_1__1_ cby_3__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8214 } ) ,
+ .chany_bottom_in ( sb_1__1__23_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__24_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_26_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__26_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__26_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__26_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8215 ) ,
+ .Test_en_E_in ( Test_enWires[74] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8216 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8217 ) ,
+ .Test_en_W_out ( Test_enWires[71] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8218 ) ,
+ .pReset_S_in ( pResetWires[122] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8219 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8220 ) ,
+ .Reset_E_in ( ResetWires[74] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8221 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8222 ) ,
+ .Reset_W_out ( ResetWires[71] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8223 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[108] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[109] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8224 ) ,
+ .prog_clk_2_N_in ( p2533 ) , .prog_clk_2_S_in ( p1564 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8225 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8226 ) ,
+ .prog_clk_3_S_in ( p1727 ) , .prog_clk_3_N_in ( p2276 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8227 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_2_N_in ( p2101 ) ,
+ .clk_2_S_in ( p3173 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p3262 ) ,
+ .clk_3_N_in ( p1971 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8232 ) ) ;
+cby_1__1_ cby_3__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8233 } ) ,
+ .chany_bottom_in ( sb_1__1__24_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__25_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_27_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__27_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__27_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__27_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8234 ) ,
+ .Test_en_E_in ( Test_enWires[96] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8235 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8236 ) ,
+ .Test_en_W_out ( Test_enWires[93] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8237 ) ,
+ .pReset_S_in ( pResetWires[171] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8238 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8239 ) ,
+ .Reset_E_in ( ResetWires[96] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8240 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8241 ) ,
+ .Reset_W_out ( ResetWires[93] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8242 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[111] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[112] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8243 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[40] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8244 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[41] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8245 ) ,
+ .prog_clk_3_S_in ( p1051 ) , .prog_clk_3_N_in ( p808 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8246 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8247 ) ,
+ .clk_2_N_in ( clk_2_wires[40] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8248 ) ,
+ .clk_2_S_out ( clk_2_wires[41] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p1051 ) ,
+ .clk_3_N_in ( p201 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8251 ) ) ;
+cby_1__1_ cby_3__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8252 } ) ,
+ .chany_bottom_in ( sb_1__1__25_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__26_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_28_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__28_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__28_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__28_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8253 ) ,
+ .Test_en_E_in ( Test_enWires[118] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8254 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8255 ) ,
+ .Test_en_W_out ( Test_enWires[115] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8256 ) ,
+ .pReset_S_in ( pResetWires[220] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8257 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8258 ) ,
+ .Reset_E_in ( ResetWires[118] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8259 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8260 ) ,
+ .Reset_W_out ( ResetWires[115] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8261 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[114] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[115] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8262 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8263 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[38] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8264 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p1422 ) ,
+ .prog_clk_3_N_in ( p775 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8265 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8266 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8267 ) ,
+ .clk_2_S_in ( clk_2_wires[38] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8268 ) ,
+ .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p1422 ) ,
+ .clk_3_N_in ( p344 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8270 ) ) ;
+cby_1__1_ cby_3__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8271 } ) ,
+ .chany_bottom_in ( sb_1__1__26_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__27_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_29_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__29_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__29_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__29_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8272 ) ,
+ .Test_en_E_in ( Test_enWires[140] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8273 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8274 ) ,
+ .Test_en_W_out ( Test_enWires[137] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8275 ) ,
+ .pReset_S_in ( pResetWires[269] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8276 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8277 ) ,
+ .Reset_E_in ( ResetWires[140] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8278 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8279 ) ,
+ .Reset_W_out ( ResetWires[137] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8280 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[117] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[118] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8281 ) ,
+ .prog_clk_2_N_in ( p2734 ) , .prog_clk_2_S_in ( p459 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8282 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8283 ) ,
+ .prog_clk_3_S_in ( p39 ) , .prog_clk_3_N_in ( p2559 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8284 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_2_N_in ( p2087 ) ,
+ .clk_2_S_in ( p2376 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p2550 ) ,
+ .clk_3_N_in ( p2009 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8289 ) ) ;
+cby_1__1_ cby_3__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8290 } ) ,
+ .chany_bottom_in ( sb_1__1__27_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__28_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_30_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__30_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__30_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__30_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8291 ) ,
+ .Test_en_E_in ( Test_enWires[162] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8292 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8293 ) ,
+ .Test_en_W_out ( Test_enWires[159] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8294 ) ,
+ .pReset_S_in ( pResetWires[318] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8295 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8296 ) ,
+ .Reset_E_in ( ResetWires[162] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8297 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8298 ) ,
+ .Reset_W_out ( ResetWires[159] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8299 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[120] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[121] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8300 ) ,
+ .prog_clk_2_N_in ( p3251 ) , .prog_clk_2_S_in ( p1476 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8301 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8302 ) ,
+ .prog_clk_3_S_in ( p1423 ) , .prog_clk_3_N_in ( p3197 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8303 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_2_N_in ( p1201 ) ,
+ .clk_2_S_in ( p2304 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p2440 ) ,
+ .clk_3_N_in ( p63 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8308 ) ) ;
+cby_1__1_ cby_3__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8309 } ) ,
+ .chany_bottom_in ( sb_1__1__28_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__29_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_31_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__31_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__31_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__31_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8310 ) ,
+ .Test_en_E_in ( Test_enWires[184] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8311 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8312 ) ,
+ .Test_en_W_out ( Test_enWires[181] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8313 ) ,
+ .pReset_S_in ( pResetWires[367] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8314 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8315 ) ,
+ .Reset_E_in ( ResetWires[184] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8316 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8317 ) ,
+ .Reset_W_out ( ResetWires[181] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8318 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[123] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[124] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8319 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[53] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8320 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[54] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8321 ) ,
+ .prog_clk_3_S_in ( p1359 ) , .prog_clk_3_N_in ( p74 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8322 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8323 ) ,
+ .clk_2_N_in ( clk_2_wires[53] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8324 ) ,
+ .clk_2_S_out ( clk_2_wires[54] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p1359 ) ,
+ .clk_3_N_in ( p540 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8327 ) ) ;
+cby_1__1_ cby_3__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8328 } ) ,
+ .chany_bottom_in ( sb_1__1__29_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__30_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_32_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__32_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__32_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__32_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8329 ) ,
+ .Test_en_E_in ( Test_enWires[206] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8330 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8331 ) ,
+ .Test_en_W_out ( Test_enWires[203] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8332 ) ,
+ .pReset_S_in ( pResetWires[416] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8333 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8334 ) ,
+ .Reset_E_in ( ResetWires[206] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8335 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8336 ) ,
+ .Reset_W_out ( ResetWires[203] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8337 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[126] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[127] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8338 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8339 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[51] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8340 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p1463 ) ,
+ .prog_clk_3_N_in ( p795 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8341 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8342 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8343 ) ,
+ .clk_2_S_in ( clk_2_wires[51] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8344 ) ,
+ .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p1674 ) ,
+ .clk_3_N_in ( p641 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8346 ) ) ;
+cby_1__1_ cby_3__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8347 } ) ,
+ .chany_bottom_in ( sb_1__1__30_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__31_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_33_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__33_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__33_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__33_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8348 ) ,
+ .Test_en_E_in ( Test_enWires[228] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8349 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8350 ) ,
+ .Test_en_W_out ( Test_enWires[225] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8351 ) ,
+ .pReset_S_in ( pResetWires[465] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8352 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8353 ) ,
+ .Reset_E_in ( ResetWires[228] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8354 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8355 ) ,
+ .Reset_W_out ( ResetWires[225] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8356 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[129] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[130] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8357 ) ,
+ .prog_clk_2_N_in ( p2705 ) , .prog_clk_2_S_in ( p2637 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8358 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8359 ) ,
+ .prog_clk_3_S_in ( p2685 ) , .prog_clk_3_N_in ( p2647 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8360 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_2_N_in ( p3373 ) ,
+ .clk_2_S_in ( p1475 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p1749 ) ,
+ .clk_3_N_in ( p3305 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8365 ) ) ;
+cby_1__1_ cby_3__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8366 } ) ,
+ .chany_bottom_in ( sb_1__1__31_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__32_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_34_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__34_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__34_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__34_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8367 ) ,
+ .Test_en_E_in ( Test_enWires[250] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8368 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8369 ) ,
+ .Test_en_W_out ( Test_enWires[247] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8370 ) ,
+ .pReset_S_in ( pResetWires[514] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8371 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8372 ) ,
+ .Reset_E_in ( ResetWires[250] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8373 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8374 ) ,
+ .Reset_W_out ( ResetWires[247] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8375 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[132] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[133] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8376 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8377 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[64] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8378 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p1440 ) ,
+ .prog_clk_3_N_in ( p932 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8379 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8380 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8381 ) ,
+ .clk_2_S_in ( clk_2_wires[64] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8382 ) ,
+ .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p1757 ) ,
+ .clk_3_N_in ( p430 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8384 ) ) ;
+cby_1__1_ cby_3__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8385 } ) ,
+ .chany_bottom_in ( sb_1__1__32_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_35_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__35_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__35_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__35_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8386 ) ,
+ .Test_en_E_in ( Test_enWires[272] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8387 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8388 ) ,
+ .Test_en_W_out ( Test_enWires[269] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8389 ) ,
+ .pReset_S_in ( pResetWires[563] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8390 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8391 ) ,
+ .Reset_E_in ( ResetWires[272] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8392 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8393 ) ,
+ .Reset_W_out ( ResetWires[269] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8394 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[135] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[136] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p2411 ) ,
+ .prog_clk_2_S_in ( p2367 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8395 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8396 ) ,
+ .prog_clk_3_S_in ( p2487 ) , .prog_clk_3_N_in ( p2332 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8397 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_2_N_in ( p1134 ) ,
+ .clk_2_S_in ( p1505 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p1799 ) ,
+ .clk_3_N_in ( p170 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8402 ) ) ;
+cby_1__1_ cby_4__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8403 } ) ,
+ .chany_bottom_in ( sb_1__0__3_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__33_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_36_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__36_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__36_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__36_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8404 ) ,
+ .Test_en_E_in ( Test_enWires[32] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8405 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8406 ) ,
+ .Test_en_W_out ( Test_enWires[29] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8407 ) ,
+ .pReset_S_in ( pResetWires[36] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8408 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8409 ) ,
+ .Reset_E_in ( ResetWires[32] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8410 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8411 ) ,
+ .Reset_W_out ( ResetWires[29] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8412 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[140] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[141] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8413 ) ,
+ .prog_clk_2_N_in ( p3123 ) , .prog_clk_2_S_in ( p1545 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8414 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8415 ) ,
+ .prog_clk_3_S_in ( p1738 ) , .prog_clk_3_N_in ( p3010 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8416 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_2_N_in ( p2690 ) ,
+ .clk_2_S_in ( p292 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p1335 ) ,
+ .clk_3_N_in ( p2633 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8421 ) ) ;
+cby_1__1_ cby_4__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8422 } ) ,
+ .chany_bottom_in ( sb_1__1__33_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__34_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_37_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__37_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__37_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__37_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8423 ) ,
+ .Test_en_E_in ( Test_enWires[54] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8424 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8425 ) ,
+ .Test_en_W_out ( Test_enWires[51] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8426 ) ,
+ .pReset_S_in ( pResetWires[77] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8427 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8428 ) ,
+ .Reset_E_in ( ResetWires[54] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8429 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8430 ) ,
+ .Reset_W_out ( ResetWires[51] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8431 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[143] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[144] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8432 ) ,
+ .prog_clk_2_N_in ( p3100 ) , .prog_clk_2_S_in ( p1631 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8433 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8434 ) ,
+ .prog_clk_3_S_in ( p1845 ) , .prog_clk_3_N_in ( p3046 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8435 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_2_N_in ( p2543 ) ,
+ .clk_2_S_in ( p2626 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p2761 ) ,
+ .clk_3_N_in ( p2320 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8440 ) ) ;
+cby_1__1_ cby_4__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8441 } ) ,
+ .chany_bottom_in ( sb_1__1__34_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__35_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_38_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__38_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__38_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__38_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8442 ) ,
+ .Test_en_E_in ( Test_enWires[76] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8443 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8444 ) ,
+ .Test_en_W_out ( Test_enWires[73] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8445 ) ,
+ .pReset_S_in ( pResetWires[126] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8446 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8447 ) ,
+ .Reset_E_in ( ResetWires[76] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8448 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8449 ) ,
+ .Reset_W_out ( ResetWires[73] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8450 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[146] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[147] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8451 ) ,
+ .prog_clk_2_N_in ( p1371 ) , .prog_clk_2_S_in ( p778 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8452 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8453 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8454 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[24] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8455 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p1371 ) ,
+ .clk_2_S_in ( p325 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8456 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8457 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8458 ) ,
+ .clk_3_N_in ( clk_3_wires[24] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8459 ) ,
+ .clk_3_S_out ( clk_3_wires[25] ) ) ;
+cby_1__1_ cby_4__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8460 } ) ,
+ .chany_bottom_in ( sb_1__1__35_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__36_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_39_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__39_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__39_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__39_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8461 ) ,
+ .Test_en_E_in ( Test_enWires[98] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8462 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8463 ) ,
+ .Test_en_W_out ( Test_enWires[95] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8464 ) ,
+ .pReset_S_in ( pResetWires[175] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8465 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8466 ) ,
+ .Reset_E_in ( ResetWires[98] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8467 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8468 ) ,
+ .Reset_W_out ( ResetWires[95] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8469 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[149] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[150] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8470 ) ,
+ .prog_clk_2_N_in ( p1108 ) , .prog_clk_2_S_in ( p1542 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8471 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8472 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8473 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[20] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8474 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1108 ) ,
+ .clk_2_S_in ( p989 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8475 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8476 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8477 ) ,
+ .clk_3_N_in ( clk_3_wires[20] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8478 ) ,
+ .clk_3_S_out ( clk_3_wires[21] ) ) ;
+cby_1__1_ cby_4__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8479 } ) ,
+ .chany_bottom_in ( sb_1__1__36_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__37_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_40_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__40_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__40_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__40_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8480 ) ,
+ .Test_en_E_in ( Test_enWires[120] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8481 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8482 ) ,
+ .Test_en_W_out ( Test_enWires[117] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8483 ) ,
+ .pReset_S_in ( pResetWires[224] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8484 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8485 ) ,
+ .Reset_E_in ( ResetWires[120] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8486 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8487 ) ,
+ .Reset_W_out ( ResetWires[117] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8488 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[152] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[153] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8489 ) ,
+ .prog_clk_2_N_in ( p1762 ) , .prog_clk_2_S_in ( p2845 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8490 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8491 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8492 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[14] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8493 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1762 ) ,
+ .clk_2_S_in ( p85 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8494 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8495 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8496 ) ,
+ .clk_3_N_in ( clk_3_wires[14] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8497 ) ,
+ .clk_3_S_out ( clk_3_wires[15] ) ) ;
+cby_1__1_ cby_4__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8498 } ) ,
+ .chany_bottom_in ( sb_1__1__37_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__38_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_41_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__41_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__41_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__41_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8499 ) ,
+ .Test_en_E_in ( Test_enWires[142] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8500 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8501 ) ,
+ .Test_en_W_out ( Test_enWires[139] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8502 ) ,
+ .pReset_S_in ( pResetWires[273] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8503 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8504 ) ,
+ .Reset_E_in ( ResetWires[142] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8505 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8506 ) ,
+ .Reset_W_out ( ResetWires[139] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8507 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[155] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[156] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8508 ) ,
+ .prog_clk_2_N_in ( p1436 ) , .prog_clk_2_S_in ( p2583 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8509 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8510 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8511 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[10] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8512 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p1436 ) ,
+ .clk_2_S_in ( p329 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8513 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8514 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8515 ) ,
+ .clk_3_N_in ( clk_3_wires[10] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8516 ) ,
+ .clk_3_S_out ( clk_3_wires[11] ) ) ;
+cby_1__1_ cby_4__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8517 } ) ,
+ .chany_bottom_in ( sb_1__1__38_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__39_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_42_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__42_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__42_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__42_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8518 ) ,
+ .Test_en_E_in ( Test_enWires[164] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8519 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8520 ) ,
+ .Test_en_W_out ( Test_enWires[161] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8521 ) ,
+ .pReset_S_in ( pResetWires[322] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8522 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8523 ) ,
+ .Reset_E_in ( ResetWires[164] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8524 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8525 ) ,
+ .Reset_W_out ( ResetWires[161] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8526 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[158] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[159] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8527 ) ,
+ .prog_clk_2_N_in ( p1798 ) , .prog_clk_2_S_in ( p1517 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8528 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8529 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[8] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8530 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[9] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8531 ) , .clk_2_N_in ( p1798 ) ,
+ .clk_2_S_in ( p875 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8532 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8533 ) ,
+ .clk_3_S_in ( clk_3_wires[8] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8534 ) ,
+ .clk_3_N_out ( clk_3_wires[9] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8535 ) ) ;
+cby_1__1_ cby_4__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8536 } ) ,
+ .chany_bottom_in ( sb_1__1__39_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__40_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_43_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__43_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__43_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__43_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8537 ) ,
+ .Test_en_E_in ( Test_enWires[186] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8538 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8539 ) ,
+ .Test_en_W_out ( Test_enWires[183] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8540 ) ,
+ .pReset_S_in ( pResetWires[371] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8541 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8542 ) ,
+ .Reset_E_in ( ResetWires[186] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8543 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8544 ) ,
+ .Reset_W_out ( ResetWires[183] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8545 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[161] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[162] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8546 ) ,
+ .prog_clk_2_N_in ( p1154 ) , .prog_clk_2_S_in ( p45 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8547 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8548 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[12] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8549 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[13] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , .clk_2_N_in ( p1154 ) ,
+ .clk_2_S_in ( p2280 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8551 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8552 ) ,
+ .clk_3_S_in ( clk_3_wires[12] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8553 ) ,
+ .clk_3_N_out ( clk_3_wires[13] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8554 ) ) ;
+cby_1__1_ cby_4__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8555 } ) ,
+ .chany_bottom_in ( sb_1__1__40_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__41_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_44_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__44_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__44_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__44_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8556 ) ,
+ .Test_en_E_in ( Test_enWires[208] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8557 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8558 ) ,
+ .Test_en_W_out ( Test_enWires[205] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8559 ) ,
+ .pReset_S_in ( pResetWires[420] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8560 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8561 ) ,
+ .Reset_E_in ( ResetWires[208] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8562 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8563 ) ,
+ .Reset_W_out ( ResetWires[205] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8564 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[164] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[165] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8565 ) ,
+ .prog_clk_2_N_in ( p2167 ) , .prog_clk_2_S_in ( p1487 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8566 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8567 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[18] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8568 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[19] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8569 ) , .clk_2_N_in ( p2167 ) ,
+ .clk_2_S_in ( p179 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8570 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8571 ) ,
+ .clk_3_S_in ( clk_3_wires[18] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8572 ) ,
+ .clk_3_N_out ( clk_3_wires[19] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8573 ) ) ;
+cby_1__1_ cby_4__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8574 } ) ,
+ .chany_bottom_in ( sb_1__1__41_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__42_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_45_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__45_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__45_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__45_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8575 ) ,
+ .Test_en_E_in ( Test_enWires[230] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8576 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8577 ) ,
+ .Test_en_W_out ( Test_enWires[227] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8578 ) ,
+ .pReset_S_in ( pResetWires[469] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8579 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8580 ) ,
+ .Reset_E_in ( ResetWires[230] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8581 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8582 ) ,
+ .Reset_W_out ( ResetWires[227] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8583 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[167] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[168] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8584 ) ,
+ .prog_clk_2_N_in ( p1418 ) , .prog_clk_2_S_in ( p52 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8585 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8586 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[22] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8587 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[23] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8588 ) , .clk_2_N_in ( p1418 ) ,
+ .clk_2_S_in ( p850 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8589 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8590 ) ,
+ .clk_3_S_in ( clk_3_wires[22] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8591 ) ,
+ .clk_3_N_out ( clk_3_wires[23] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8592 ) ) ;
+cby_1__1_ cby_4__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8593 } ) ,
+ .chany_bottom_in ( sb_1__1__42_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__43_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_46_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__46_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__46_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__46_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8594 ) ,
+ .Test_en_E_in ( Test_enWires[252] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8595 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8596 ) ,
+ .Test_en_W_out ( Test_enWires[249] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8597 ) ,
+ .pReset_S_in ( pResetWires[518] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8598 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8599 ) ,
+ .Reset_E_in ( ResetWires[252] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8600 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8601 ) ,
+ .Reset_W_out ( ResetWires[249] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8602 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[170] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[171] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8603 ) ,
+ .prog_clk_2_N_in ( p2213 ) , .prog_clk_2_S_in ( p1066 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8604 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8605 ) ,
+ .prog_clk_3_S_in ( p1354 ) , .prog_clk_3_N_in ( p2041 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8606 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_2_N_in ( p3372 ) ,
+ .clk_2_S_in ( p2554 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p2711 ) ,
+ .clk_3_N_in ( p3295 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8611 ) ) ;
+cby_1__1_ cby_4__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8612 } ) ,
+ .chany_bottom_in ( sb_1__1__43_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_47_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__47_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__47_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__47_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8613 ) ,
+ .Test_en_E_in ( Test_enWires[274] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8614 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8615 ) ,
+ .Test_en_W_out ( Test_enWires[271] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8616 ) ,
+ .pReset_S_in ( pResetWires[567] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8617 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8618 ) ,
+ .Reset_E_in ( ResetWires[274] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8619 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8620 ) ,
+ .Reset_W_out ( ResetWires[271] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8621 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[173] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[174] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p2656 ) ,
+ .prog_clk_2_S_in ( p1973 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8622 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8623 ) ,
+ .prog_clk_3_S_in ( p2070 ) , .prog_clk_3_N_in ( p2557 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8624 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_2_N_in ( p1305 ) ,
+ .clk_2_S_in ( p1593 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p1840 ) ,
+ .clk_3_N_in ( p108 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8629 ) ) ;
+cby_1__1_ cby_5__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8630 } ) ,
+ .chany_bottom_in ( sb_1__0__4_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__44_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_48_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__48_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__48_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__48_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8631 ) ,
+ .Test_en_E_in ( Test_enWires[34] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8632 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8633 ) ,
+ .Test_en_W_out ( Test_enWires[31] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8634 ) ,
+ .pReset_S_in ( pResetWires[39] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8635 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8636 ) ,
+ .Reset_E_in ( ResetWires[34] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8637 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8638 ) ,
+ .Reset_W_out ( ResetWires[31] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8639 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[178] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[179] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8640 ) ,
+ .prog_clk_2_N_in ( p2703 ) , .prog_clk_2_S_in ( p2378 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8641 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8642 ) ,
+ .prog_clk_3_S_in ( p2387 ) , .prog_clk_3_N_in ( p2614 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8643 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_2_N_in ( p2184 ) ,
+ .clk_2_S_in ( p2854 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2964 ) ,
+ .clk_3_N_in ( p2010 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8648 ) ) ;
+cby_1__1_ cby_5__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8649 } ) ,
+ .chany_bottom_in ( sb_1__1__44_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__45_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_49_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__49_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__49_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__49_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8650 ) ,
+ .Test_en_E_in ( Test_enWires[56] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8651 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8652 ) ,
+ .Test_en_W_out ( Test_enWires[53] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8653 ) ,
+ .pReset_S_in ( pResetWires[81] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8654 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8655 ) ,
+ .Reset_E_in ( ResetWires[56] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8656 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8657 ) ,
+ .Reset_W_out ( ResetWires[53] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8658 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[181] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[182] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8659 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[31] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8660 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[32] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8661 ) ,
+ .prog_clk_3_S_in ( p1184 ) , .prog_clk_3_N_in ( p34 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8662 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8663 ) ,
+ .clk_2_N_in ( clk_2_wires[31] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8664 ) ,
+ .clk_2_S_out ( clk_2_wires[32] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p2133 ) ,
+ .clk_3_N_in ( p774 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8667 ) ) ;
+cby_1__1_ cby_5__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8668 } ) ,
+ .chany_bottom_in ( sb_1__1__45_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__46_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_50_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__50_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__50_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__50_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8669 ) ,
+ .Test_en_E_in ( Test_enWires[78] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8670 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8671 ) ,
+ .Test_en_W_out ( Test_enWires[75] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8672 ) ,
+ .pReset_S_in ( pResetWires[130] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8673 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8674 ) ,
+ .Reset_E_in ( ResetWires[78] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8675 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8676 ) ,
+ .Reset_W_out ( ResetWires[75] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8677 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[184] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[185] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8678 ) ,
+ .prog_clk_2_N_in ( p2206 ) , .prog_clk_2_S_in ( p1572 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8679 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8680 ) ,
+ .prog_clk_3_S_in ( p1782 ) , .prog_clk_3_N_in ( p2019 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8681 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_2_N_in ( p2451 ) ,
+ .clk_2_S_in ( p3513 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p3541 ) ,
+ .clk_3_N_in ( p2301 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8686 ) ) ;
+cby_1__1_ cby_5__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8687 } ) ,
+ .chany_bottom_in ( sb_1__1__46_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__47_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_51_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__51_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__51_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__51_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8688 ) ,
+ .Test_en_E_in ( Test_enWires[100] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8689 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8690 ) ,
+ .Test_en_W_out ( Test_enWires[97] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8691 ) ,
+ .pReset_S_in ( pResetWires[179] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8692 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8693 ) ,
+ .Reset_E_in ( ResetWires[100] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8694 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8695 ) ,
+ .Reset_W_out ( ResetWires[97] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8696 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[187] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[188] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8697 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[44] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8698 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[45] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8699 ) ,
+ .prog_clk_3_S_in ( p1768 ) , .prog_clk_3_N_in ( p466 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8700 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8701 ) ,
+ .clk_2_N_in ( clk_2_wires[44] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8702 ) ,
+ .clk_2_S_out ( clk_2_wires[45] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1768 ) ,
+ .clk_3_N_in ( p587 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8705 ) ) ;
+cby_1__1_ cby_5__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8706 } ) ,
+ .chany_bottom_in ( sb_1__1__47_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__48_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_52_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__52_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__52_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__52_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8707 ) ,
+ .Test_en_E_in ( Test_enWires[122] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8708 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8709 ) ,
+ .Test_en_W_out ( Test_enWires[119] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8710 ) ,
+ .pReset_S_in ( pResetWires[228] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8711 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8712 ) ,
+ .Reset_E_in ( ResetWires[122] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8713 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8714 ) ,
+ .Reset_W_out ( ResetWires[119] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8715 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[190] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[191] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8716 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8717 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[42] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8718 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p1304 ) ,
+ .prog_clk_3_N_in ( p584 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8719 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8720 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8721 ) ,
+ .clk_2_S_in ( clk_2_wires[42] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8722 ) ,
+ .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p2237 ) ,
+ .clk_3_N_in ( p429 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8724 ) ) ;
+cby_1__1_ cby_5__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8725 } ) ,
+ .chany_bottom_in ( sb_1__1__48_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__49_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_53_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__53_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__53_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__53_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8726 ) ,
+ .Test_en_E_in ( Test_enWires[144] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8727 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8728 ) ,
+ .Test_en_W_out ( Test_enWires[141] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8729 ) ,
+ .pReset_S_in ( pResetWires[277] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8730 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8731 ) ,
+ .Reset_E_in ( ResetWires[144] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8732 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8733 ) ,
+ .Reset_W_out ( ResetWires[141] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8734 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[193] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[194] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8735 ) ,
+ .prog_clk_2_N_in ( p2722 ) , .prog_clk_2_S_in ( p1956 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8736 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8737 ) ,
+ .prog_clk_3_S_in ( p2187 ) , .prog_clk_3_N_in ( p2563 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8738 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_2_N_in ( p2692 ) ,
+ .clk_2_S_in ( p1537 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p1872 ) ,
+ .clk_3_N_in ( p2640 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8743 ) ) ;
+cby_1__1_ cby_5__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8744 } ) ,
+ .chany_bottom_in ( sb_1__1__49_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__50_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_54_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__54_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__54_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__54_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8745 ) ,
+ .Test_en_E_in ( Test_enWires[166] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8746 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8747 ) ,
+ .Test_en_W_out ( Test_enWires[163] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8748 ) ,
+ .pReset_S_in ( pResetWires[326] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8749 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8750 ) ,
+ .Reset_E_in ( ResetWires[166] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8751 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8752 ) ,
+ .Reset_W_out ( ResetWires[163] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8753 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[196] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[197] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8754 ) ,
+ .prog_clk_2_N_in ( p3438 ) , .prog_clk_2_S_in ( p2278 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8755 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8756 ) ,
+ .prog_clk_3_S_in ( p1685 ) , .prog_clk_3_N_in ( p3384 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8757 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_2_N_in ( p2409 ) ,
+ .clk_2_S_in ( p2576 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2395 ) ,
+ .clk_3_N_in ( p2340 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8762 ) ) ;
+cby_1__1_ cby_5__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8763 } ) ,
+ .chany_bottom_in ( sb_1__1__50_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__51_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_55_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__55_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__55_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__55_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8764 ) ,
+ .Test_en_E_in ( Test_enWires[188] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8765 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8766 ) ,
+ .Test_en_W_out ( Test_enWires[185] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8767 ) ,
+ .pReset_S_in ( pResetWires[375] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8768 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8769 ) ,
+ .Reset_E_in ( ResetWires[188] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8770 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8771 ) ,
+ .Reset_W_out ( ResetWires[185] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8772 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[199] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[200] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8773 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[57] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8774 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[58] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8775 ) ,
+ .prog_clk_3_S_in ( p1736 ) , .prog_clk_3_N_in ( p557 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8776 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8777 ) ,
+ .clk_2_N_in ( clk_2_wires[57] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8778 ) ,
+ .clk_2_S_out ( clk_2_wires[58] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1736 ) ,
+ .clk_3_N_in ( p330 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8781 ) ) ;
+cby_1__1_ cby_5__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8782 } ) ,
+ .chany_bottom_in ( sb_1__1__51_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__52_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_56_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__56_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__56_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__56_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8783 ) ,
+ .Test_en_E_in ( Test_enWires[210] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8784 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8785 ) ,
+ .Test_en_W_out ( Test_enWires[207] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8786 ) ,
+ .pReset_S_in ( pResetWires[424] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8787 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8788 ) ,
+ .Reset_E_in ( ResetWires[210] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8789 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8790 ) ,
+ .Reset_W_out ( ResetWires[207] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8791 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[202] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[203] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8792 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8793 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[55] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8794 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1318 ) ,
+ .prog_clk_3_N_in ( p1024 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8795 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8796 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8797 ) ,
+ .clk_2_S_in ( clk_2_wires[55] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8798 ) ,
+ .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1318 ) ,
+ .clk_3_N_in ( p423 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8800 ) ) ;
+cby_1__1_ cby_5__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8801 } ) ,
+ .chany_bottom_in ( sb_1__1__52_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__53_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_57_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__57_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__57_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__57_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8802 ) ,
+ .Test_en_E_in ( Test_enWires[232] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8803 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8804 ) ,
+ .Test_en_W_out ( Test_enWires[229] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8805 ) ,
+ .pReset_S_in ( pResetWires[473] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8806 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8807 ) ,
+ .Reset_E_in ( ResetWires[232] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8808 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8809 ) ,
+ .Reset_W_out ( ResetWires[229] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8810 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[205] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[206] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8811 ) ,
+ .prog_clk_2_N_in ( p2797 ) , .prog_clk_2_S_in ( p1652 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8812 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8813 ) ,
+ .prog_clk_3_S_in ( p1666 ) , .prog_clk_3_N_in ( p2638 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8814 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_2_N_in ( p2905 ) ,
+ .clk_2_S_in ( p3215 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p3273 ) ,
+ .clk_3_N_in ( p2846 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8819 ) ) ;
+cby_1__1_ cby_5__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8820 } ) ,
+ .chany_bottom_in ( sb_1__1__53_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__54_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_58_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__58_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__58_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__58_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8821 ) ,
+ .Test_en_E_in ( Test_enWires[254] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8822 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8823 ) ,
+ .Test_en_W_out ( Test_enWires[251] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8824 ) ,
+ .pReset_S_in ( pResetWires[522] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8825 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8826 ) ,
+ .Reset_E_in ( ResetWires[254] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8827 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8828 ) ,
+ .Reset_W_out ( ResetWires[251] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8829 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[208] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[209] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8830 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8831 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[66] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8832 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p1765 ) ,
+ .prog_clk_3_N_in ( p996 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8833 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8834 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8835 ) ,
+ .clk_2_S_in ( clk_2_wires[66] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8836 ) ,
+ .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p2112 ) ,
+ .clk_3_N_in ( p190 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8838 ) ) ;
+cby_1__1_ cby_5__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8839 } ) ,
+ .chany_bottom_in ( sb_1__1__54_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_59_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__59_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__59_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__59_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8840 ) ,
+ .Test_en_E_in ( Test_enWires[276] ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8841 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8842 ) ,
+ .Test_en_W_out ( Test_enWires[273] ) ,
+ .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8843 ) ,
+ .pReset_S_in ( pResetWires[571] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_8844 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_8845 ) ,
+ .Reset_E_in ( ResetWires[276] ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8846 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_8847 ) ,
+ .Reset_W_out ( ResetWires[273] ) ,
+ .Reset_E_out ( SYNOPSYS_UNCONNECTED_8848 ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[211] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[212] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p2415 ) ,
+ .prog_clk_2_S_in ( p1626 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8849 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8850 ) ,
+ .prog_clk_3_S_in ( p1902 ) , .prog_clk_3_N_in ( p2264 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8851 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_2_N_in ( p2714 ) ,
+ .clk_2_S_in ( p3159 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p3275 ) ,
+ .clk_3_N_in ( p2562 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8856 ) ) ;
+cby_1__1_ cby_6__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8857 } ) ,
+ .chany_bottom_in ( sb_1__0__5_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__55_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_60_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__60_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__60_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__60_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[1] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8858 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8859 ) ,
+ .Test_en_N_out ( Test_enWires[2] ) , .Test_en_W_out ( Test_enWires[33] ) ,
+ .Test_en_E_out ( Test_enWires[35] ) , .pReset_S_in ( pResetWires[42] ) ,
+ .pReset_N_out ( pResetWires[2] ) , .Reset_S_in ( ResetWires[1] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8860 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8861 ) ,
+ .Reset_N_out ( ResetWires[2] ) , .Reset_W_out ( ResetWires[33] ) ,
+ .Reset_E_out ( ResetWires[35] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[216] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[217] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8862 ) ,
+ .prog_clk_2_N_in ( p1367 ) , .prog_clk_2_S_in ( p59 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8863 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8864 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[90] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8865 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[89] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8866 ) , .clk_2_N_in ( p1367 ) ,
+ .clk_2_S_in ( p673 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8867 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8868 ) ,
+ .clk_3_S_in ( clk_3_wires[90] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8869 ) ,
+ .clk_3_N_out ( clk_3_wires[89] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8870 ) ) ;
+cby_1__1_ cby_6__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8871 } ) ,
+ .chany_bottom_in ( sb_1__1__55_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__56_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_61_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__61_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__61_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__61_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[3] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8872 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8873 ) ,
+ .Test_en_N_out ( Test_enWires[4] ) , .Test_en_W_out ( Test_enWires[55] ) ,
+ .Test_en_E_out ( Test_enWires[57] ) , .pReset_S_in ( pResetWires[85] ) ,
+ .pReset_N_out ( pResetWires[4] ) , .Reset_S_in ( ResetWires[3] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8874 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8875 ) ,
+ .Reset_N_out ( ResetWires[4] ) , .Reset_W_out ( ResetWires[55] ) ,
+ .Reset_E_out ( ResetWires[57] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[219] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[220] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8876 ) ,
+ .prog_clk_2_N_in ( p1426 ) , .prog_clk_2_S_in ( p1520 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8877 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8878 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[92] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8879 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[91] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8880 ) , .clk_2_N_in ( p1426 ) ,
+ .clk_2_S_in ( p139 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8881 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8882 ) ,
+ .clk_3_S_in ( clk_3_wires[92] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8883 ) ,
+ .clk_3_N_out ( clk_3_wires[91] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8884 ) ) ;
+cby_1__1_ cby_6__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8885 } ) ,
+ .chany_bottom_in ( sb_1__1__56_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__57_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_62_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__62_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__62_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__62_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[5] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8886 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8887 ) ,
+ .Test_en_N_out ( Test_enWires[6] ) , .Test_en_W_out ( Test_enWires[77] ) ,
+ .Test_en_E_out ( Test_enWires[79] ) , .pReset_S_in ( pResetWires[134] ) ,
+ .pReset_N_out ( pResetWires[6] ) , .Reset_S_in ( ResetWires[5] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8888 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8889 ) ,
+ .Reset_N_out ( ResetWires[6] ) , .Reset_W_out ( ResetWires[77] ) ,
+ .Reset_E_out ( ResetWires[79] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[222] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[223] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8890 ) ,
+ .prog_clk_2_N_in ( p1294 ) , .prog_clk_2_S_in ( p345 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8891 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8892 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[94] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8893 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[93] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8894 ) , .clk_2_N_in ( p1294 ) ,
+ .clk_2_S_in ( p381 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8895 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8896 ) ,
+ .clk_3_S_in ( clk_3_wires[94] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8897 ) ,
+ .clk_3_N_out ( clk_3_wires[93] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8898 ) ) ;
+cby_1__1_ cby_6__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8899 } ) ,
+ .chany_bottom_in ( sb_1__1__57_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__58_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_63_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__63_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__63_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__63_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[7] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8900 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8901 ) ,
+ .Test_en_N_out ( Test_enWires[8] ) , .Test_en_W_out ( Test_enWires[99] ) ,
+ .Test_en_E_out ( Test_enWires[101] ) , .pReset_S_in ( pResetWires[183] ) ,
+ .pReset_N_out ( pResetWires[8] ) , .Reset_S_in ( ResetWires[7] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8902 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8903 ) ,
+ .Reset_N_out ( ResetWires[8] ) , .Reset_W_out ( ResetWires[99] ) ,
+ .Reset_E_out ( ResetWires[101] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[225] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[226] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8904 ) ,
+ .prog_clk_2_N_in ( p1300 ) , .prog_clk_2_S_in ( p1951 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8905 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8906 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[96] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8907 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[95] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8908 ) , .clk_2_N_in ( p1300 ) ,
+ .clk_2_S_in ( p729 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8909 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8910 ) ,
+ .clk_3_S_in ( clk_3_wires[96] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8911 ) ,
+ .clk_3_N_out ( clk_3_wires[95] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8912 ) ) ;
+cby_1__1_ cby_6__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8913 } ) ,
+ .chany_bottom_in ( sb_1__1__58_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__59_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_64_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__64_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__64_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__64_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[9] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8914 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8915 ) ,
+ .Test_en_N_out ( Test_enWires[10] ) ,
+ .Test_en_W_out ( Test_enWires[121] ) ,
+ .Test_en_E_out ( Test_enWires[123] ) , .pReset_S_in ( pResetWires[232] ) ,
+ .pReset_N_out ( pResetWires[10] ) , .Reset_S_in ( ResetWires[9] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8916 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8917 ) ,
+ .Reset_N_out ( ResetWires[10] ) , .Reset_W_out ( ResetWires[121] ) ,
+ .Reset_E_out ( ResetWires[123] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[228] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[229] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8918 ) ,
+ .prog_clk_2_N_in ( p2410 ) , .prog_clk_2_S_in ( p186 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8919 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8920 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[98] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8921 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[97] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8922 ) , .clk_2_N_in ( p2513 ) ,
+ .clk_2_S_in ( p972 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8923 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8924 ) ,
+ .clk_3_S_in ( clk_3_wires[98] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8925 ) ,
+ .clk_3_N_out ( clk_3_wires[97] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8926 ) ) ;
+cby_1__1_ cby_6__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8927 } ) ,
+ .chany_bottom_in ( sb_1__1__59_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__60_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_65_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__65_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__65_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__65_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[11] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8928 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8929 ) ,
+ .Test_en_N_out ( Test_enWires[12] ) ,
+ .Test_en_W_out ( Test_enWires[143] ) ,
+ .Test_en_E_out ( Test_enWires[145] ) , .pReset_S_in ( pResetWires[281] ) ,
+ .pReset_N_out ( pResetWires[12] ) , .Reset_S_in ( ResetWires[11] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8930 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8931 ) ,
+ .Reset_N_out ( ResetWires[12] ) , .Reset_W_out ( ResetWires[143] ) ,
+ .Reset_E_out ( ResetWires[145] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[231] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[232] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8932 ) ,
+ .prog_clk_2_N_in ( p1899 ) , .prog_clk_2_S_in ( p702 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8933 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8934 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[100] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8935 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[99] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8936 ) , .clk_2_N_in ( p1899 ) ,
+ .clk_2_S_in ( p284 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8937 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8938 ) ,
+ .clk_3_S_in ( clk_3_wires[100] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8939 ) ,
+ .clk_3_N_out ( clk_3_wires[99] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8940 ) ) ;
+cby_1__1_ cby_6__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8941 } ) ,
+ .chany_bottom_in ( sb_1__1__60_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__61_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_66_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__66_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__66_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__66_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[13] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8942 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8943 ) ,
+ .Test_en_N_out ( Test_enWires[14] ) ,
+ .Test_en_W_out ( Test_enWires[165] ) ,
+ .Test_en_E_out ( Test_enWires[167] ) , .pReset_S_in ( pResetWires[330] ) ,
+ .pReset_N_out ( pResetWires[14] ) , .Reset_S_in ( ResetWires[13] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8944 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8945 ) ,
+ .Reset_N_out ( ResetWires[14] ) , .Reset_W_out ( ResetWires[165] ) ,
+ .Reset_E_out ( ResetWires[167] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[234] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[235] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8946 ) ,
+ .prog_clk_2_N_in ( p2699 ) , .prog_clk_2_S_in ( p1516 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8947 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8948 ) ,
+ .prog_clk_3_S_in ( p1894 ) , .prog_clk_3_N_in ( p2589 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8949 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_2_N_in ( p2515 ) ,
+ .clk_2_S_in ( p1551 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p1895 ) ,
+ .clk_3_N_in ( p2313 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8954 ) ) ;
+cby_1__1_ cby_6__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8955 } ) ,
+ .chany_bottom_in ( sb_1__1__61_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__62_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_67_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__67_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__67_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__67_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[15] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8956 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8957 ) ,
+ .Test_en_N_out ( Test_enWires[16] ) ,
+ .Test_en_W_out ( Test_enWires[187] ) ,
+ .Test_en_E_out ( Test_enWires[189] ) , .pReset_S_in ( pResetWires[379] ) ,
+ .pReset_N_out ( pResetWires[16] ) , .Reset_S_in ( ResetWires[15] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8958 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8959 ) ,
+ .Reset_N_out ( ResetWires[16] ) , .Reset_W_out ( ResetWires[187] ) ,
+ .Reset_E_out ( ResetWires[189] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[237] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[238] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8960 ) ,
+ .prog_clk_2_N_in ( p3128 ) , .prog_clk_2_S_in ( p1575 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8961 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8962 ) ,
+ .prog_clk_3_S_in ( p1698 ) , .prog_clk_3_N_in ( p3005 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8963 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_2_N_in ( p2918 ) ,
+ .clk_2_S_in ( p2316 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p2424 ) ,
+ .clk_3_N_in ( p2880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8968 ) ) ;
+cby_1__1_ cby_6__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8969 } ) ,
+ .chany_bottom_in ( sb_1__1__62_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__63_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_68_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__68_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__68_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__68_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[17] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8970 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8971 ) ,
+ .Test_en_N_out ( Test_enWires[18] ) ,
+ .Test_en_W_out ( Test_enWires[209] ) ,
+ .Test_en_E_out ( Test_enWires[211] ) , .pReset_S_in ( pResetWires[428] ) ,
+ .pReset_N_out ( pResetWires[18] ) , .Reset_S_in ( ResetWires[17] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8972 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8973 ) ,
+ .Reset_N_out ( ResetWires[18] ) , .Reset_W_out ( ResetWires[209] ) ,
+ .Reset_E_out ( ResetWires[211] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[240] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[241] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8974 ) ,
+ .prog_clk_2_N_in ( p3437 ) , .prog_clk_2_S_in ( p2011 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8975 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8976 ) ,
+ .prog_clk_3_S_in ( p2191 ) , .prog_clk_3_N_in ( p3395 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8977 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_2_N_in ( p1417 ) ,
+ .clk_2_S_in ( p2279 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p2483 ) ,
+ .clk_3_N_in ( p40 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8982 ) ) ;
+cby_1__1_ cby_6__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8983 } ) ,
+ .chany_bottom_in ( sb_1__1__63_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__64_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_69_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__69_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__69_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__69_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[19] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8984 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8985 ) ,
+ .Test_en_N_out ( Test_enWires[20] ) ,
+ .Test_en_W_out ( Test_enWires[231] ) ,
+ .Test_en_E_out ( Test_enWires[233] ) , .pReset_S_in ( pResetWires[477] ) ,
+ .pReset_N_out ( pResetWires[20] ) , .Reset_S_in ( ResetWires[19] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_8986 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_8987 ) ,
+ .Reset_N_out ( ResetWires[20] ) , .Reset_W_out ( ResetWires[231] ) ,
+ .Reset_E_out ( ResetWires[233] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[243] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[244] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8988 ) ,
+ .prog_clk_2_N_in ( p1457 ) , .prog_clk_2_S_in ( p2268 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8989 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8990 ) ,
+ .prog_clk_3_S_in ( p2417 ) , .prog_clk_3_N_in ( p492 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8991 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_2_N_in ( p2927 ) ,
+ .clk_2_S_in ( p1576 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p1732 ) ,
+ .clk_3_N_in ( p2835 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8996 ) ) ;
+cby_1__1_ cby_6__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_8997 } ) ,
+ .chany_bottom_in ( sb_1__1__64_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__65_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_70_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__70_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__70_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__70_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[21] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8998 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8999 ) ,
+ .Test_en_N_out ( Test_enWires[22] ) ,
+ .Test_en_W_out ( Test_enWires[253] ) ,
+ .Test_en_E_out ( Test_enWires[255] ) , .pReset_S_in ( pResetWires[526] ) ,
+ .pReset_N_out ( pResetWires[22] ) , .Reset_S_in ( ResetWires[21] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9000 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_9001 ) ,
+ .Reset_N_out ( ResetWires[22] ) , .Reset_W_out ( ResetWires[253] ) ,
+ .Reset_E_out ( ResetWires[255] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[246] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[247] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9002 ) ,
+ .prog_clk_2_N_in ( p3130 ) , .prog_clk_2_S_in ( p810 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9003 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9004 ) ,
+ .prog_clk_3_S_in ( p1256 ) , .prog_clk_3_N_in ( p3040 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9005 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_2_N_in ( p2664 ) ,
+ .clk_2_S_in ( p1982 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p2091 ) ,
+ .clk_3_N_in ( p2572 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9010 ) ) ;
+cby_1__1_ cby_6__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9011 } ) ,
+ .chany_bottom_in ( sb_1__1__65_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_71_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__71_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__71_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__71_ccff_tail ) ,
+ .Test_en_S_in ( Test_enWires[23] ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9012 ) ,
+ .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9013 ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9014 ) ,
+ .Test_en_W_out ( Test_enWires[275] ) ,
+ .Test_en_E_out ( Test_enWires[277] ) , .pReset_S_in ( pResetWires[575] ) ,
+ .pReset_N_out ( pResetWires[24] ) , .Reset_S_in ( ResetWires[23] ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9015 ) ,
+ .Reset_W_in ( SYNOPSYS_UNCONNECTED_9016 ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9017 ) ,
+ .Reset_W_out ( ResetWires[275] ) , .Reset_E_out ( ResetWires[277] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[249] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[250] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p1819 ) ,
+ .prog_clk_2_S_in ( p1502 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9018 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9019 ) ,
+ .prog_clk_3_S_in ( p1823 ) , .prog_clk_3_N_in ( p1474 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9020 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_2_N_in ( p3351 ) ,
+ .clk_2_S_in ( p3060 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p3081 ) ,
+ .clk_3_N_in ( p3286 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9025 ) ) ;
+cby_1__1_ cby_7__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9026 } ) ,
+ .chany_bottom_in ( sb_1__0__6_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__66_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_72_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__72_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__72_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__72_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9027 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9028 ) ,
+ .Test_en_W_in ( Test_enWires[36] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9029 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9030 ) ,
+ .Test_en_E_out ( Test_enWires[37] ) , .pReset_S_in ( pResetWires[45] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9031 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9032 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9033 ) ,
+ .Reset_W_in ( ResetWires[36] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9034 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9035 ) ,
+ .Reset_E_out ( ResetWires[37] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[254] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[255] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9036 ) ,
+ .prog_clk_2_N_in ( p2473 ) , .prog_clk_2_S_in ( p1914 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9037 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9038 ) ,
+ .prog_clk_3_S_in ( p2097 ) , .prog_clk_3_N_in ( p2363 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9039 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_2_N_in ( p2170 ) ,
+ .clk_2_S_in ( p2022 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p2094 ) ,
+ .clk_3_N_in ( p1917 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9044 ) ) ;
+cby_1__1_ cby_7__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9045 } ) ,
+ .chany_bottom_in ( sb_1__1__66_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__67_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_73_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__73_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__73_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__73_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9046 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9047 ) ,
+ .Test_en_W_in ( Test_enWires[58] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9048 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9049 ) ,
+ .Test_en_E_out ( Test_enWires[59] ) , .pReset_S_in ( pResetWires[89] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9050 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9051 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9052 ) ,
+ .Reset_W_in ( ResetWires[58] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9053 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9054 ) ,
+ .Reset_E_out ( ResetWires[59] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[257] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[258] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9055 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[73] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9056 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[74] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9057 ) ,
+ .prog_clk_3_S_in ( p1261 ) , .prog_clk_3_N_in ( p773 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9058 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9059 ) ,
+ .clk_2_N_in ( clk_2_wires[73] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9060 ) ,
+ .clk_2_S_out ( clk_2_wires[74] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1860 ) ,
+ .clk_3_N_in ( p438 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9063 ) ) ;
+cby_1__1_ cby_7__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9064 } ) ,
+ .chany_bottom_in ( sb_1__1__67_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__68_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_74_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__74_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__74_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__74_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9065 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9066 ) ,
+ .Test_en_W_in ( Test_enWires[80] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9067 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9068 ) ,
+ .Test_en_E_out ( Test_enWires[81] ) , .pReset_S_in ( pResetWires[138] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9069 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9070 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9071 ) ,
+ .Reset_W_in ( ResetWires[80] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9072 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9073 ) ,
+ .Reset_E_out ( ResetWires[81] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[260] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[261] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9074 ) ,
+ .prog_clk_2_N_in ( p1737 ) , .prog_clk_2_S_in ( p1934 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9075 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9076 ) ,
+ .prog_clk_3_S_in ( p2218 ) , .prog_clk_3_N_in ( p1472 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9077 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_2_N_in ( p1330 ) ,
+ .clk_2_S_in ( p2342 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2524 ) ,
+ .clk_3_N_in ( p90 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9082 ) ) ;
+cby_1__1_ cby_7__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9083 } ) ,
+ .chany_bottom_in ( sb_1__1__68_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__69_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_75_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__75_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__75_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__75_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9084 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9085 ) ,
+ .Test_en_W_in ( Test_enWires[102] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9086 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9087 ) ,
+ .Test_en_E_out ( Test_enWires[103] ) , .pReset_S_in ( pResetWires[187] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9088 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9089 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9090 ) ,
+ .Reset_W_in ( ResetWires[102] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9091 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9092 ) ,
+ .Reset_E_out ( ResetWires[103] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[263] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[264] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9093 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[84] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9094 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[85] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9095 ) ,
+ .prog_clk_3_S_in ( p1901 ) , .prog_clk_3_N_in ( p634 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9096 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9097 ) ,
+ .clk_2_N_in ( clk_2_wires[84] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9098 ) ,
+ .clk_2_S_out ( clk_2_wires[85] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p2453 ) ,
+ .clk_3_N_in ( p419 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9101 ) ) ;
+cby_1__1_ cby_7__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9102 } ) ,
+ .chany_bottom_in ( sb_1__1__69_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__70_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_76_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__76_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__76_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__76_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9103 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9104 ) ,
+ .Test_en_W_in ( Test_enWires[124] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9105 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9106 ) ,
+ .Test_en_E_out ( Test_enWires[125] ) , .pReset_S_in ( pResetWires[236] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9107 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9108 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9109 ) ,
+ .Reset_W_in ( ResetWires[124] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9110 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9111 ) ,
+ .Reset_E_out ( ResetWires[125] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[266] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[267] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9112 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9113 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[82] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9114 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p2064 ) ,
+ .prog_clk_3_N_in ( p901 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9115 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9116 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9117 ) ,
+ .clk_2_S_in ( clk_2_wires[82] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9118 ) ,
+ .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p2079 ) ,
+ .clk_3_N_in ( p624 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9120 ) ) ;
+cby_1__1_ cby_7__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9121 } ) ,
+ .chany_bottom_in ( sb_1__1__70_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__71_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_77_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__77_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__77_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__77_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9122 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9123 ) ,
+ .Test_en_W_in ( Test_enWires[146] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9124 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9125 ) ,
+ .Test_en_E_out ( Test_enWires[147] ) , .pReset_S_in ( pResetWires[285] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9126 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9127 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9128 ) ,
+ .Reset_W_in ( ResetWires[146] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9129 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9130 ) ,
+ .Reset_E_out ( ResetWires[147] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[269] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[270] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9131 ) ,
+ .prog_clk_2_N_in ( p3369 ) , .prog_clk_2_S_in ( p1570 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9132 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9133 ) ,
+ .prog_clk_3_S_in ( p1790 ) , .prog_clk_3_N_in ( p3297 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9134 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_2_N_in ( p2904 ) ,
+ .clk_2_S_in ( p2632 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p2724 ) ,
+ .clk_3_N_in ( p2812 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9139 ) ) ;
+cby_1__1_ cby_7__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9140 } ) ,
+ .chany_bottom_in ( sb_1__1__71_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__72_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_78_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__78_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__78_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__78_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9141 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9142 ) ,
+ .Test_en_W_in ( Test_enWires[168] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9143 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9144 ) ,
+ .Test_en_E_out ( Test_enWires[169] ) , .pReset_S_in ( pResetWires[334] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9145 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9146 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9147 ) ,
+ .Reset_W_in ( ResetWires[168] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9148 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9149 ) ,
+ .Reset_E_out ( ResetWires[169] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[272] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[273] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9150 ) ,
+ .prog_clk_2_N_in ( p2897 ) , .prog_clk_2_S_in ( p2802 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9151 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9152 ) ,
+ .prog_clk_3_S_in ( p2910 ) , .prog_clk_3_N_in ( p2821 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9153 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_2_N_in ( p2756 ) ,
+ .clk_2_S_in ( p2884 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p2942 ) ,
+ .clk_3_N_in ( p2627 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9158 ) ) ;
+cby_1__1_ cby_7__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9159 } ) ,
+ .chany_bottom_in ( sb_1__1__72_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__73_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_79_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__79_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__79_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__79_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9160 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9161 ) ,
+ .Test_en_W_in ( Test_enWires[190] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9162 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9163 ) ,
+ .Test_en_E_out ( Test_enWires[191] ) , .pReset_S_in ( pResetWires[383] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9164 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9165 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9166 ) ,
+ .Reset_W_in ( ResetWires[190] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9167 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9168 ) ,
+ .Reset_E_out ( ResetWires[191] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[275] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[276] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9169 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[97] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9170 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[98] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9171 ) ,
+ .prog_clk_3_S_in ( p1667 ) , .prog_clk_3_N_in ( p761 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9172 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9173 ) ,
+ .clk_2_N_in ( clk_2_wires[97] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9174 ) ,
+ .clk_2_S_out ( clk_2_wires[98] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p1816 ) ,
+ .clk_3_N_in ( p544 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9177 ) ) ;
+cby_1__1_ cby_7__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9178 } ) ,
+ .chany_bottom_in ( sb_1__1__73_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__74_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_80_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__80_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__80_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__80_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9179 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9180 ) ,
+ .Test_en_W_in ( Test_enWires[212] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9181 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9182 ) ,
+ .Test_en_E_out ( Test_enWires[213] ) , .pReset_S_in ( pResetWires[432] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9183 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9184 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9185 ) ,
+ .Reset_W_in ( ResetWires[212] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9186 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9187 ) ,
+ .Reset_E_out ( ResetWires[213] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[278] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[279] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9188 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9189 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[95] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9190 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p1420 ) ,
+ .prog_clk_3_N_in ( p507 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9191 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9192 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9193 ) ,
+ .clk_2_S_in ( clk_2_wires[95] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9194 ) ,
+ .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p1854 ) ,
+ .clk_3_N_in ( p630 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9196 ) ) ;
+cby_1__1_ cby_7__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9197 } ) ,
+ .chany_bottom_in ( sb_1__1__74_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__75_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_81_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__81_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__81_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__81_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9198 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9199 ) ,
+ .Test_en_W_in ( Test_enWires[234] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9200 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9201 ) ,
+ .Test_en_E_out ( Test_enWires[235] ) , .pReset_S_in ( pResetWires[481] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9202 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9203 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9204 ) ,
+ .Reset_W_in ( ResetWires[234] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9205 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9206 ) ,
+ .Reset_E_out ( ResetWires[235] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[281] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[282] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9207 ) ,
+ .prog_clk_2_N_in ( p2466 ) , .prog_clk_2_S_in ( p1635 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9208 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9209 ) ,
+ .prog_clk_3_S_in ( p1888 ) , .prog_clk_3_N_in ( p2308 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9210 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_2_N_in ( p3365 ) ,
+ .clk_2_S_in ( p3294 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p3339 ) ,
+ .clk_3_N_in ( p3313 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9215 ) ) ;
+cby_1__1_ cby_7__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9216 } ) ,
+ .chany_bottom_in ( sb_1__1__75_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__76_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_82_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__82_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__82_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__82_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9217 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9218 ) ,
+ .Test_en_W_in ( Test_enWires[256] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9219 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9220 ) ,
+ .Test_en_E_out ( Test_enWires[257] ) , .pReset_S_in ( pResetWires[530] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9221 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9222 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9223 ) ,
+ .Reset_W_in ( ResetWires[256] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9224 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9225 ) ,
+ .Reset_E_out ( ResetWires[257] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[284] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[285] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9226 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9227 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[108] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9228 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1226 ) ,
+ .prog_clk_3_N_in ( p118 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9229 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9230 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9231 ) ,
+ .clk_2_S_in ( clk_2_wires[108] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9232 ) ,
+ .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1177 ) ,
+ .clk_3_N_in ( p958 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9234 ) ) ;
+cby_1__1_ cby_7__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9235 } ) ,
+ .chany_bottom_in ( sb_1__1__76_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_83_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__83_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__83_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__83_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9236 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9237 ) ,
+ .Test_en_W_in ( Test_enWires[278] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9238 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9239 ) ,
+ .Test_en_E_out ( Test_enWires[279] ) , .pReset_S_in ( pResetWires[579] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9240 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9241 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9242 ) ,
+ .Reset_W_in ( ResetWires[278] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9243 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9244 ) ,
+ .Reset_E_out ( ResetWires[279] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[287] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[288] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p2893 ) ,
+ .prog_clk_2_S_in ( p2016 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9245 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9246 ) ,
+ .prog_clk_3_S_in ( p2239 ) , .prog_clk_3_N_in ( p2825 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9247 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_2_N_in ( p2755 ) ,
+ .clk_2_S_in ( p2028 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p2164 ) ,
+ .clk_3_N_in ( p2567 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9252 ) ) ;
+cby_1__1_ cby_8__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9253 } ) ,
+ .chany_bottom_in ( sb_1__0__7_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__77_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_84_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__84_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__84_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__84_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9254 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9255 ) ,
+ .Test_en_W_in ( Test_enWires[38] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9256 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9257 ) ,
+ .Test_en_E_out ( Test_enWires[39] ) , .pReset_S_in ( pResetWires[48] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9258 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9259 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9260 ) ,
+ .Reset_W_in ( ResetWires[38] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9261 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9262 ) ,
+ .Reset_E_out ( ResetWires[39] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[292] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[293] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9263 ) ,
+ .prog_clk_2_N_in ( p2975 ) , .prog_clk_2_S_in ( p245 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9264 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9265 ) ,
+ .prog_clk_3_S_in ( p1395 ) , .prog_clk_3_N_in ( p2842 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9266 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_2_N_in ( p2747 ) ,
+ .clk_2_S_in ( p2299 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p2450 ) ,
+ .clk_3_N_in ( p2657 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9271 ) ) ;
+cby_1__1_ cby_8__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9272 } ) ,
+ .chany_bottom_in ( sb_1__1__77_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__78_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_85_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__85_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__85_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__85_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9273 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9274 ) ,
+ .Test_en_W_in ( Test_enWires[60] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9275 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9276 ) ,
+ .Test_en_E_out ( Test_enWires[61] ) , .pReset_S_in ( pResetWires[93] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9277 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9278 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9279 ) ,
+ .Reset_W_in ( ResetWires[60] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9280 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9281 ) ,
+ .Reset_E_out ( ResetWires[61] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[295] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[296] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9282 ) ,
+ .prog_clk_2_N_in ( p2090 ) , .prog_clk_2_S_in ( p2653 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9283 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9284 ) ,
+ .prog_clk_3_S_in ( p2780 ) , .prog_clk_3_N_in ( p1907 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9285 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_2_N_in ( p3248 ) ,
+ .clk_2_S_in ( p3185 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p3225 ) ,
+ .clk_3_N_in ( p3177 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9290 ) ) ;
+cby_1__1_ cby_8__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9291 } ) ,
+ .chany_bottom_in ( sb_1__1__78_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__79_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_86_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__86_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__86_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__86_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9292 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9293 ) ,
+ .Test_en_W_in ( Test_enWires[82] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9294 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9295 ) ,
+ .Test_en_E_out ( Test_enWires[83] ) , .pReset_S_in ( pResetWires[142] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9296 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9297 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9298 ) ,
+ .Reset_W_in ( ResetWires[82] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9299 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9300 ) ,
+ .Reset_E_out ( ResetWires[83] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[298] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[299] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9301 ) ,
+ .prog_clk_2_N_in ( p1327 ) , .prog_clk_2_S_in ( p192 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9302 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9303 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9304 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[42] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9305 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p1327 ) ,
+ .clk_2_S_in ( p608 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9307 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9308 ) ,
+ .clk_3_N_in ( clk_3_wires[42] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9309 ) ,
+ .clk_3_S_out ( clk_3_wires[43] ) ) ;
+cby_1__1_ cby_8__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9310 } ) ,
+ .chany_bottom_in ( sb_1__1__79_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__80_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_87_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__87_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__87_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__87_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9311 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9312 ) ,
+ .Test_en_W_in ( Test_enWires[104] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9313 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9314 ) ,
+ .Test_en_E_out ( Test_enWires[105] ) , .pReset_S_in ( pResetWires[191] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9315 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9316 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9317 ) ,
+ .Reset_W_in ( ResetWires[104] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9318 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9319 ) ,
+ .Reset_E_out ( ResetWires[105] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[301] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[302] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9320 ) ,
+ .prog_clk_2_N_in ( p1331 ) , .prog_clk_2_S_in ( p962 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9321 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9322 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9323 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[38] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9324 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1331 ) ,
+ .clk_2_S_in ( p29 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9325 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9326 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9327 ) ,
+ .clk_3_N_in ( clk_3_wires[38] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9328 ) ,
+ .clk_3_S_out ( clk_3_wires[39] ) ) ;
+cby_1__1_ cby_8__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9329 } ) ,
+ .chany_bottom_in ( sb_1__1__80_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__81_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_88_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__88_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__88_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__88_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9330 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9331 ) ,
+ .Test_en_W_in ( Test_enWires[126] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9332 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9333 ) ,
+ .Test_en_E_out ( Test_enWires[127] ) , .pReset_S_in ( pResetWires[240] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9334 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9335 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9336 ) ,
+ .Reset_W_in ( ResetWires[126] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9337 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9338 ) ,
+ .Reset_E_out ( ResetWires[127] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[304] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[305] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9339 ) ,
+ .prog_clk_2_N_in ( p2447 ) , .prog_clk_2_S_in ( p1960 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9340 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9341 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9342 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[32] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9343 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p2517 ) ,
+ .clk_2_S_in ( p105 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9344 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9345 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9346 ) ,
+ .clk_3_N_in ( clk_3_wires[32] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9347 ) ,
+ .clk_3_S_out ( clk_3_wires[33] ) ) ;
+cby_1__1_ cby_8__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9348 } ) ,
+ .chany_bottom_in ( sb_1__1__81_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__82_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_89_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__89_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__89_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__89_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9349 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9350 ) ,
+ .Test_en_W_in ( Test_enWires[148] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9351 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9352 ) ,
+ .Test_en_E_out ( Test_enWires[149] ) , .pReset_S_in ( pResetWires[289] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9353 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9354 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9355 ) ,
+ .Reset_W_in ( ResetWires[148] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9356 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9357 ) ,
+ .Reset_E_out ( ResetWires[149] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[307] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[308] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9358 ) ,
+ .prog_clk_2_N_in ( p1298 ) , .prog_clk_2_S_in ( p1467 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9359 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9360 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9361 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[28] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9362 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p1298 ) ,
+ .clk_2_S_in ( p28 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9364 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9365 ) ,
+ .clk_3_N_in ( clk_3_wires[28] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9366 ) ,
+ .clk_3_S_out ( clk_3_wires[29] ) ) ;
+cby_1__1_ cby_8__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9367 } ) ,
+ .chany_bottom_in ( sb_1__1__82_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__83_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_90_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__90_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__90_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__90_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9368 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9369 ) ,
+ .Test_en_W_in ( Test_enWires[170] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9370 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9371 ) ,
+ .Test_en_E_out ( Test_enWires[171] ) , .pReset_S_in ( pResetWires[338] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9372 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9373 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9374 ) ,
+ .Reset_W_in ( ResetWires[170] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9375 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9376 ) ,
+ .Reset_E_out ( ResetWires[171] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[310] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[311] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9377 ) ,
+ .prog_clk_2_N_in ( p1756 ) , .prog_clk_2_S_in ( p267 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9378 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9379 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[26] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9380 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[27] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9381 ) , .clk_2_N_in ( p1756 ) ,
+ .clk_2_S_in ( p1022 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9382 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9383 ) ,
+ .clk_3_S_in ( clk_3_wires[26] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9384 ) ,
+ .clk_3_N_out ( clk_3_wires[27] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9385 ) ) ;
+cby_1__1_ cby_8__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9386 } ) ,
+ .chany_bottom_in ( sb_1__1__83_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__84_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_91_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__91_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__91_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__91_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9387 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9388 ) ,
+ .Test_en_W_in ( Test_enWires[192] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9389 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9390 ) ,
+ .Test_en_E_out ( Test_enWires[193] ) , .pReset_S_in ( pResetWires[387] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9391 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9392 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9393 ) ,
+ .Reset_W_in ( ResetWires[192] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9394 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9395 ) ,
+ .Reset_E_out ( ResetWires[193] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[313] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[314] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9396 ) ,
+ .prog_clk_2_N_in ( p1312 ) , .prog_clk_2_S_in ( p1510 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9397 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9398 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[30] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9399 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[31] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9400 ) , .clk_2_N_in ( p1312 ) ,
+ .clk_2_S_in ( p1638 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9401 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9402 ) ,
+ .clk_3_S_in ( clk_3_wires[30] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9403 ) ,
+ .clk_3_N_out ( clk_3_wires[31] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9404 ) ) ;
+cby_1__1_ cby_8__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9405 } ) ,
+ .chany_bottom_in ( sb_1__1__84_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__85_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_92_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__92_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__92_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__92_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9406 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9407 ) ,
+ .Test_en_W_in ( Test_enWires[214] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9408 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9409 ) ,
+ .Test_en_E_out ( Test_enWires[215] ) , .pReset_S_in ( pResetWires[436] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9410 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9411 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9412 ) ,
+ .Reset_W_in ( ResetWires[214] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9413 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9414 ) ,
+ .Reset_E_out ( ResetWires[215] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[316] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[317] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9415 ) ,
+ .prog_clk_2_N_in ( p1876 ) , .prog_clk_2_S_in ( p2282 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9416 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9417 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[36] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9418 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[37] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9419 ) , .clk_2_N_in ( p1876 ) ,
+ .clk_2_S_in ( p117 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9420 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9421 ) ,
+ .clk_3_S_in ( clk_3_wires[36] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9422 ) ,
+ .clk_3_N_out ( clk_3_wires[37] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9423 ) ) ;
+cby_1__1_ cby_8__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9424 } ) ,
+ .chany_bottom_in ( sb_1__1__85_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__86_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_93_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__93_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__93_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__93_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9425 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9426 ) ,
+ .Test_en_W_in ( Test_enWires[236] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9427 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9428 ) ,
+ .Test_en_E_out ( Test_enWires[237] ) , .pReset_S_in ( pResetWires[485] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9429 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9430 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9431 ) ,
+ .Reset_W_in ( ResetWires[236] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9432 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9433 ) ,
+ .Reset_E_out ( ResetWires[237] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[319] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[320] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9434 ) ,
+ .prog_clk_2_N_in ( p936 ) , .prog_clk_2_S_in ( p3006 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9435 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9436 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[40] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9437 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[41] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9438 ) , .clk_2_N_in ( p936 ) ,
+ .clk_2_S_in ( p622 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9439 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9440 ) ,
+ .clk_3_S_in ( clk_3_wires[40] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9441 ) ,
+ .clk_3_N_out ( clk_3_wires[41] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9442 ) ) ;
+cby_1__1_ cby_8__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9443 } ) ,
+ .chany_bottom_in ( sb_1__1__86_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__87_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_94_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__94_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__94_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__94_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9444 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9445 ) ,
+ .Test_en_W_in ( Test_enWires[258] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9446 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9447 ) ,
+ .Test_en_E_out ( Test_enWires[259] ) , .pReset_S_in ( pResetWires[534] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9448 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9449 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9450 ) ,
+ .Reset_W_in ( ResetWires[258] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9451 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9452 ) ,
+ .Reset_E_out ( ResetWires[259] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[322] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[323] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9453 ) ,
+ .prog_clk_2_N_in ( p3089 ) , .prog_clk_2_S_in ( p2561 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9454 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9455 ) ,
+ .prog_clk_3_S_in ( p2788 ) , .prog_clk_3_N_in ( p3017 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9456 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_2_N_in ( p2687 ) ,
+ .clk_2_S_in ( p2844 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2941 ) ,
+ .clk_3_N_in ( p2662 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9461 ) ) ;
+cby_1__1_ cby_8__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9462 } ) ,
+ .chany_bottom_in ( sb_1__1__87_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_95_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__95_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__95_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__95_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9463 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9464 ) ,
+ .Test_en_W_in ( Test_enWires[280] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9465 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9466 ) ,
+ .Test_en_E_out ( Test_enWires[281] ) , .pReset_S_in ( pResetWires[583] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9467 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9468 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9469 ) ,
+ .Reset_W_in ( ResetWires[280] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9470 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9471 ) ,
+ .Reset_E_out ( ResetWires[281] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[325] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[326] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p2757 ) ,
+ .prog_clk_2_S_in ( p542 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9472 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9473 ) ,
+ .prog_clk_3_S_in ( p1369 ) , .prog_clk_3_N_in ( p2651 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9474 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_2_N_in ( p3343 ) ,
+ .clk_2_S_in ( p2646 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p2758 ) ,
+ .clk_3_N_in ( p3309 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9479 ) ) ;
+cby_1__1_ cby_9__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9480 } ) ,
+ .chany_bottom_in ( sb_1__0__8_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__88_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_96_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__96_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__96_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__96_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9481 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9482 ) ,
+ .Test_en_W_in ( Test_enWires[40] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9483 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9484 ) ,
+ .Test_en_E_out ( Test_enWires[41] ) , .pReset_S_in ( pResetWires[51] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9485 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9486 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9487 ) ,
+ .Reset_W_in ( ResetWires[40] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9488 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9489 ) ,
+ .Reset_E_out ( ResetWires[41] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[330] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[331] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9490 ) ,
+ .prog_clk_2_N_in ( p2776 ) , .prog_clk_2_S_in ( p714 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9491 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9492 ) ,
+ .prog_clk_3_S_in ( p1272 ) , .prog_clk_3_N_in ( p2643 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9493 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_2_N_in ( p3579 ) ,
+ .clk_2_S_in ( p1963 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p2080 ) ,
+ .clk_3_N_in ( p3553 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9498 ) ) ;
+cby_1__1_ cby_9__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9499 } ) ,
+ .chany_bottom_in ( sb_1__1__88_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__89_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_97_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__97_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__97_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__97_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9500 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9501 ) ,
+ .Test_en_W_in ( Test_enWires[62] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9502 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9503 ) ,
+ .Test_en_E_out ( Test_enWires[63] ) , .pReset_S_in ( pResetWires[97] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9504 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9505 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9506 ) ,
+ .Reset_W_in ( ResetWires[62] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9507 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9508 ) ,
+ .Reset_E_out ( ResetWires[63] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[333] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[334] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9509 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[75] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9510 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[76] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9511 ) ,
+ .prog_clk_3_S_in ( p1376 ) , .prog_clk_3_N_in ( p653 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9512 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9513 ) ,
+ .clk_2_N_in ( clk_2_wires[75] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9514 ) ,
+ .clk_2_S_out ( clk_2_wires[76] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p2158 ) ,
+ .clk_3_N_in ( p376 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9517 ) ) ;
+cby_1__1_ cby_9__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9518 } ) ,
+ .chany_bottom_in ( sb_1__1__89_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__90_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_98_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__98_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__98_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__98_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9519 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9520 ) ,
+ .Test_en_W_in ( Test_enWires[84] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9521 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9522 ) ,
+ .Test_en_E_out ( Test_enWires[85] ) , .pReset_S_in ( pResetWires[146] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9523 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9524 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9525 ) ,
+ .Reset_W_in ( ResetWires[84] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9526 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9527 ) ,
+ .Reset_E_out ( ResetWires[85] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[336] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[337] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9528 ) ,
+ .prog_clk_2_N_in ( p2773 ) , .prog_clk_2_S_in ( p2644 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9529 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9530 ) ,
+ .prog_clk_3_S_in ( p2768 ) , .prog_clk_3_N_in ( p2564 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9531 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_2_N_in ( p1832 ) ,
+ .clk_2_S_in ( p1594 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p1884 ) ,
+ .clk_3_N_in ( p1504 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9536 ) ) ;
+cby_1__1_ cby_9__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9537 } ) ,
+ .chany_bottom_in ( sb_1__1__90_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__91_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_99_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__99_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__99_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__99_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9538 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9539 ) ,
+ .Test_en_W_in ( Test_enWires[106] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9540 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9541 ) ,
+ .Test_en_E_out ( Test_enWires[107] ) , .pReset_S_in ( pResetWires[195] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9542 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9543 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9544 ) ,
+ .Reset_W_in ( ResetWires[106] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9545 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9546 ) ,
+ .Reset_E_out ( ResetWires[107] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[339] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[340] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9547 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[88] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9548 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[89] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9549 ) ,
+ .prog_clk_3_S_in ( p1231 ) , .prog_clk_3_N_in ( p655 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9550 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9551 ) ,
+ .clk_2_N_in ( clk_2_wires[88] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9552 ) ,
+ .clk_2_S_out ( clk_2_wires[89] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p1704 ) ,
+ .clk_3_N_in ( p606 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9555 ) ) ;
+cby_1__1_ cby_9__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9556 } ) ,
+ .chany_bottom_in ( sb_1__1__91_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__92_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_100_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__100_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__100_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__100_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9557 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9558 ) ,
+ .Test_en_W_in ( Test_enWires[128] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9559 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9560 ) ,
+ .Test_en_E_out ( Test_enWires[129] ) , .pReset_S_in ( pResetWires[244] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9561 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9562 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9563 ) ,
+ .Reset_W_in ( ResetWires[128] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9564 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9565 ) ,
+ .Reset_E_out ( ResetWires[129] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[342] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[343] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9566 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9567 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[86] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9568 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p1283 ) ,
+ .prog_clk_3_N_in ( p785 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9569 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9570 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9571 ) ,
+ .clk_2_S_in ( clk_2_wires[86] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9572 ) ,
+ .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p1283 ) ,
+ .clk_3_N_in ( p13 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9574 ) ) ;
+cby_1__1_ cby_9__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9575 } ) ,
+ .chany_bottom_in ( sb_1__1__92_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__93_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_101_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__101_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__101_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__101_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9576 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9577 ) ,
+ .Test_en_W_in ( Test_enWires[150] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9578 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9579 ) ,
+ .Test_en_E_out ( Test_enWires[151] ) , .pReset_S_in ( pResetWires[293] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9580 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9581 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9582 ) ,
+ .Reset_W_in ( ResetWires[150] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9583 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9584 ) ,
+ .Reset_E_out ( ResetWires[151] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[345] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[346] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9585 ) ,
+ .prog_clk_2_N_in ( p3113 ) , .prog_clk_2_S_in ( p1604 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9586 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9587 ) ,
+ .prog_clk_3_S_in ( p1719 ) , .prog_clk_3_N_in ( p3007 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9588 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_2_N_in ( p2542 ) ,
+ .clk_2_S_in ( p2558 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2677 ) ,
+ .clk_3_N_in ( p2257 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9593 ) ) ;
+cby_1__1_ cby_9__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9594 } ) ,
+ .chany_bottom_in ( sb_1__1__93_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__94_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_102_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__102_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__102_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__102_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9595 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9596 ) ,
+ .Test_en_W_in ( Test_enWires[172] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9597 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9598 ) ,
+ .Test_en_E_out ( Test_enWires[173] ) , .pReset_S_in ( pResetWires[342] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9599 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9600 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9601 ) ,
+ .Reset_W_in ( ResetWires[172] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9602 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9603 ) ,
+ .Reset_E_out ( ResetWires[173] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[348] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[349] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9604 ) ,
+ .prog_clk_2_N_in ( p3265 ) , .prog_clk_2_S_in ( p1927 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9605 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9606 ) ,
+ .prog_clk_3_S_in ( p2114 ) , .prog_clk_3_N_in ( p3165 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9607 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_2_N_in ( p2980 ) ,
+ .clk_2_S_in ( p3039 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p3121 ) ,
+ .clk_3_N_in ( p2819 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9612 ) ) ;
+cby_1__1_ cby_9__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9613 } ) ,
+ .chany_bottom_in ( sb_1__1__94_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__95_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_103_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__103_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__103_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__103_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9614 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9615 ) ,
+ .Test_en_W_in ( Test_enWires[194] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9616 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9617 ) ,
+ .Test_en_E_out ( Test_enWires[195] ) , .pReset_S_in ( pResetWires[391] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9618 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9619 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9620 ) ,
+ .Reset_W_in ( ResetWires[194] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9621 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9622 ) ,
+ .Reset_E_out ( ResetWires[195] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[351] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[352] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9623 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[101] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9624 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[102] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9625 ) ,
+ .prog_clk_3_S_in ( p1831 ) , .prog_clk_3_N_in ( p897 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9626 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9627 ) ,
+ .clk_2_N_in ( clk_2_wires[101] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9628 ) ,
+ .clk_2_S_out ( clk_2_wires[102] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1717 ) ,
+ .clk_3_N_in ( p116 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9631 ) ) ;
+cby_1__1_ cby_9__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9632 } ) ,
+ .chany_bottom_in ( sb_1__1__95_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__96_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_104_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__104_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__104_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__104_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9633 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9634 ) ,
+ .Test_en_W_in ( Test_enWires[216] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9635 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9636 ) ,
+ .Test_en_E_out ( Test_enWires[217] ) , .pReset_S_in ( pResetWires[440] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9637 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9638 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9639 ) ,
+ .Reset_W_in ( ResetWires[216] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9640 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9641 ) ,
+ .Reset_E_out ( ResetWires[217] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[354] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[355] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9642 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9643 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[99] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9644 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1465 ) ,
+ .prog_clk_3_N_in ( p843 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9645 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9646 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9647 ) ,
+ .clk_2_S_in ( clk_2_wires[99] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9648 ) ,
+ .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1897 ) ,
+ .clk_3_N_in ( p302 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9650 ) ) ;
+cby_1__1_ cby_9__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9651 } ) ,
+ .chany_bottom_in ( sb_1__1__96_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__97_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_105_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__105_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__105_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__105_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9652 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9653 ) ,
+ .Test_en_W_in ( Test_enWires[238] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9654 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9655 ) ,
+ .Test_en_E_out ( Test_enWires[239] ) , .pReset_S_in ( pResetWires[489] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9656 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9657 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9658 ) ,
+ .Reset_W_in ( ResetWires[238] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9659 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9660 ) ,
+ .Reset_E_out ( ResetWires[239] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[357] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[358] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9661 ) ,
+ .prog_clk_2_N_in ( p1813 ) , .prog_clk_2_S_in ( p2334 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9662 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9663 ) ,
+ .prog_clk_3_S_in ( p2464 ) , .prog_clk_3_N_in ( p1599 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9664 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_2_N_in ( p2253 ) ,
+ .clk_2_S_in ( p2350 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2510 ) ,
+ .clk_3_N_in ( p1998 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9669 ) ) ;
+cby_1__1_ cby_9__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9670 } ) ,
+ .chany_bottom_in ( sb_1__1__97_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__98_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_106_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__106_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__106_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__106_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9671 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9672 ) ,
+ .Test_en_W_in ( Test_enWires[260] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9673 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9674 ) ,
+ .Test_en_E_out ( Test_enWires[261] ) , .pReset_S_in ( pResetWires[538] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9675 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9676 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9677 ) ,
+ .Reset_W_in ( ResetWires[260] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9678 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9679 ) ,
+ .Reset_E_out ( ResetWires[261] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[360] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[361] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9680 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9681 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[110] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9682 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1849 ) ,
+ .prog_clk_3_N_in ( p756 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9683 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9684 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9685 ) ,
+ .clk_2_S_in ( clk_2_wires[110] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9686 ) ,
+ .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p2130 ) ,
+ .clk_3_N_in ( p582 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9688 ) ) ;
+cby_1__1_ cby_9__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9689 } ) ,
+ .chany_bottom_in ( sb_1__1__98_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_107_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__107_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__107_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__107_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9690 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9691 ) ,
+ .Test_en_W_in ( Test_enWires[282] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9692 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9693 ) ,
+ .Test_en_E_out ( Test_enWires[283] ) , .pReset_S_in ( pResetWires[587] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9694 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9695 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9696 ) ,
+ .Reset_W_in ( ResetWires[282] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9697 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9698 ) ,
+ .Reset_E_out ( ResetWires[283] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[363] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[364] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p2924 ) ,
+ .prog_clk_2_S_in ( p2347 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9699 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9700 ) ,
+ .prog_clk_3_S_in ( p2518 ) , .prog_clk_3_N_in ( p2859 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9701 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_2_N_in ( p2693 ) ,
+ .clk_2_S_in ( p2853 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p2973 ) ,
+ .clk_3_N_in ( p2571 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9706 ) ) ;
+cby_1__1_ cby_10__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9707 } ) ,
+ .chany_bottom_in ( sb_1__0__9_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__99_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_108_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__108_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__108_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__108_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9708 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9709 ) ,
+ .Test_en_W_in ( Test_enWires[42] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9710 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9711 ) ,
+ .Test_en_E_out ( Test_enWires[43] ) , .pReset_S_in ( pResetWires[54] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9712 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9713 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9714 ) ,
+ .Reset_W_in ( ResetWires[42] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9715 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9716 ) ,
+ .Reset_E_out ( ResetWires[43] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[368] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[369] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9717 ) ,
+ .prog_clk_2_N_in ( p3078 ) , .prog_clk_2_S_in ( p1627 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9718 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9719 ) ,
+ .prog_clk_3_S_in ( p1833 ) , .prog_clk_3_N_in ( p3074 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9720 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_2_N_in ( p3379 ) ,
+ .clk_2_S_in ( p1488 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p1660 ) ,
+ .clk_3_N_in ( p3306 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9725 ) ) ;
+cby_1__1_ cby_10__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9726 } ) ,
+ .chany_bottom_in ( sb_1__1__99_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__100_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_109_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__109_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__109_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__109_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9727 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9728 ) ,
+ .Test_en_W_in ( Test_enWires[64] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9729 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9730 ) ,
+ .Test_en_E_out ( Test_enWires[65] ) , .pReset_S_in ( pResetWires[101] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9731 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9732 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9733 ) ,
+ .Reset_W_in ( ResetWires[64] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9734 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9735 ) ,
+ .Reset_E_out ( ResetWires[65] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[371] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[372] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9736 ) ,
+ .prog_clk_2_N_in ( p3221 ) , .prog_clk_2_S_in ( p1911 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9737 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9738 ) ,
+ .prog_clk_3_S_in ( p2076 ) , .prog_clk_3_N_in ( p3214 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9739 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_2_N_in ( p3239 ) ,
+ .clk_2_S_in ( p3069 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p3083 ) ,
+ .clk_3_N_in ( p3176 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9744 ) ) ;
+cby_1__1_ cby_10__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9745 } ) ,
+ .chany_bottom_in ( sb_1__1__100_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__101_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_110_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__110_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__110_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__110_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9746 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9747 ) ,
+ .Test_en_W_in ( Test_enWires[86] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9748 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9749 ) ,
+ .Test_en_E_out ( Test_enWires[87] ) , .pReset_S_in ( pResetWires[150] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9750 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9751 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9752 ) ,
+ .Reset_W_in ( ResetWires[86] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9753 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9754 ) ,
+ .Reset_E_out ( ResetWires[87] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[374] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[375] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9755 ) ,
+ .prog_clk_2_N_in ( p1891 ) , .prog_clk_2_S_in ( p941 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9756 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9757 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9758 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[86] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9759 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p1891 ) ,
+ .clk_2_S_in ( p126 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9760 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9761 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9762 ) ,
+ .clk_3_N_in ( clk_3_wires[86] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9763 ) ,
+ .clk_3_S_out ( clk_3_wires[87] ) ) ;
+cby_1__1_ cby_10__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9764 } ) ,
+ .chany_bottom_in ( sb_1__1__101_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__102_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_111_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__111_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__111_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__111_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9765 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9766 ) ,
+ .Test_en_W_in ( Test_enWires[108] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9767 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9768 ) ,
+ .Test_en_E_out ( Test_enWires[109] ) , .pReset_S_in ( pResetWires[199] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9769 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9770 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9771 ) ,
+ .Reset_W_in ( ResetWires[108] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9772 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9773 ) ,
+ .Reset_E_out ( ResetWires[109] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[377] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[378] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9774 ) ,
+ .prog_clk_2_N_in ( p1250 ) , .prog_clk_2_S_in ( p1657 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9775 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9776 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9777 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[82] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9778 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( p1250 ) ,
+ .clk_2_S_in ( p1495 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9779 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9780 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9781 ) ,
+ .clk_3_N_in ( clk_3_wires[82] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9782 ) ,
+ .clk_3_S_out ( clk_3_wires[83] ) ) ;
+cby_1__1_ cby_10__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9783 } ) ,
+ .chany_bottom_in ( sb_1__1__102_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__103_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_112_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__112_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__112_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__112_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9784 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9785 ) ,
+ .Test_en_W_in ( Test_enWires[130] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9786 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9787 ) ,
+ .Test_en_E_out ( Test_enWires[131] ) , .pReset_S_in ( pResetWires[248] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9788 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9789 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9790 ) ,
+ .Reset_W_in ( ResetWires[130] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9791 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9792 ) ,
+ .Reset_E_out ( ResetWires[131] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[380] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[381] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9793 ) ,
+ .prog_clk_2_N_in ( p1743 ) , .prog_clk_2_S_in ( p2310 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9794 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9795 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9796 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[76] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9797 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1743 ) ,
+ .clk_2_S_in ( p151 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9798 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9799 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9800 ) ,
+ .clk_3_N_in ( clk_3_wires[76] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9801 ) ,
+ .clk_3_S_out ( clk_3_wires[77] ) ) ;
+cby_1__1_ cby_10__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9802 } ) ,
+ .chany_bottom_in ( sb_1__1__103_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__104_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_113_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__113_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__113_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__113_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9803 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9804 ) ,
+ .Test_en_W_in ( Test_enWires[152] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9805 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9806 ) ,
+ .Test_en_E_out ( Test_enWires[153] ) , .pReset_S_in ( pResetWires[297] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9807 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9808 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9809 ) ,
+ .Reset_W_in ( ResetWires[152] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9810 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9811 ) ,
+ .Reset_E_out ( ResetWires[153] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[383] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[384] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9812 ) ,
+ .prog_clk_2_N_in ( p1781 ) , .prog_clk_2_S_in ( p1536 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9813 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9814 ) ,
+ .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9815 ) ,
+ .prog_clk_3_N_in ( prog_clk_3_wires[72] ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9816 ) ,
+ .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p1781 ) ,
+ .clk_2_S_in ( p902 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9817 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9818 ) ,
+ .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9819 ) ,
+ .clk_3_N_in ( clk_3_wires[72] ) ,
+ .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9820 ) ,
+ .clk_3_S_out ( clk_3_wires[73] ) ) ;
+cby_1__1_ cby_10__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9821 } ) ,
+ .chany_bottom_in ( sb_1__1__104_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__105_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_114_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__114_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__114_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__114_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9822 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9823 ) ,
+ .Test_en_W_in ( Test_enWires[174] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9824 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9825 ) ,
+ .Test_en_E_out ( Test_enWires[175] ) , .pReset_S_in ( pResetWires[346] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9826 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9827 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9828 ) ,
+ .Reset_W_in ( ResetWires[174] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9829 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9830 ) ,
+ .Reset_E_out ( ResetWires[175] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[386] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[387] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9831 ) ,
+ .prog_clk_2_N_in ( p1804 ) , .prog_clk_2_S_in ( p210 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9832 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9833 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[70] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9834 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[71] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9835 ) , .clk_2_N_in ( p1804 ) ,
+ .clk_2_S_in ( p970 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9836 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9837 ) ,
+ .clk_3_S_in ( clk_3_wires[70] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9838 ) ,
+ .clk_3_N_out ( clk_3_wires[71] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9839 ) ) ;
+cby_1__1_ cby_10__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9840 } ) ,
+ .chany_bottom_in ( sb_1__1__105_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__106_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_115_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__115_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__115_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__115_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9841 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9842 ) ,
+ .Test_en_W_in ( Test_enWires[196] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9843 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9844 ) ,
+ .Test_en_E_out ( Test_enWires[197] ) , .pReset_S_in ( pResetWires[395] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9845 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9846 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9847 ) ,
+ .Reset_W_in ( ResetWires[196] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9848 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9849 ) ,
+ .Reset_E_out ( ResetWires[197] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[389] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[390] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9850 ) ,
+ .prog_clk_2_N_in ( p1336 ) , .prog_clk_2_S_in ( p650 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9851 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9852 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[74] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9853 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[75] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , .clk_2_N_in ( p1336 ) ,
+ .clk_2_S_in ( p392 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9855 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9856 ) ,
+ .clk_3_S_in ( clk_3_wires[74] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9857 ) ,
+ .clk_3_N_out ( clk_3_wires[75] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9858 ) ) ;
+cby_1__1_ cby_10__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9859 } ) ,
+ .chany_bottom_in ( sb_1__1__106_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__107_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_116_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__116_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__116_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__116_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9860 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9861 ) ,
+ .Test_en_W_in ( Test_enWires[218] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9862 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9863 ) ,
+ .Test_en_E_out ( Test_enWires[219] ) , .pReset_S_in ( pResetWires[444] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9864 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9865 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9866 ) ,
+ .Reset_W_in ( ResetWires[218] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9867 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9868 ) ,
+ .Reset_E_out ( ResetWires[219] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[392] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[393] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9869 ) ,
+ .prog_clk_2_N_in ( p1045 ) , .prog_clk_2_S_in ( p2267 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9870 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9871 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[80] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9872 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[81] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9873 ) , .clk_2_N_in ( p1045 ) ,
+ .clk_2_S_in ( p779 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9874 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9875 ) ,
+ .clk_3_S_in ( clk_3_wires[80] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9876 ) ,
+ .clk_3_N_out ( clk_3_wires[81] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9877 ) ) ;
+cby_1__1_ cby_10__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9878 } ) ,
+ .chany_bottom_in ( sb_1__1__107_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__108_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_117_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__117_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__117_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__117_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9879 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9880 ) ,
+ .Test_en_W_in ( Test_enWires[240] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9881 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9882 ) ,
+ .Test_en_E_out ( Test_enWires[241] ) , .pReset_S_in ( pResetWires[493] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9883 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9884 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9885 ) ,
+ .Reset_W_in ( ResetWires[240] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9886 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9887 ) ,
+ .Reset_E_out ( ResetWires[241] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[395] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[396] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9888 ) ,
+ .prog_clk_2_N_in ( p1180 ) , .prog_clk_2_S_in ( p1473 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9889 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9890 ) ,
+ .prog_clk_3_S_in ( prog_clk_3_wires[84] ) ,
+ .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9891 ) ,
+ .prog_clk_3_N_out ( prog_clk_3_wires[85] ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9892 ) , .clk_2_N_in ( p1180 ) ,
+ .clk_2_S_in ( p1610 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9893 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9894 ) ,
+ .clk_3_S_in ( clk_3_wires[84] ) ,
+ .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9895 ) ,
+ .clk_3_N_out ( clk_3_wires[85] ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9896 ) ) ;
+cby_1__1_ cby_10__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9897 } ) ,
+ .chany_bottom_in ( sb_1__1__108_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__109_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_118_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__118_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__118_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__118_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9898 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9899 ) ,
+ .Test_en_W_in ( Test_enWires[262] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9900 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9901 ) ,
+ .Test_en_E_out ( Test_enWires[263] ) , .pReset_S_in ( pResetWires[542] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9902 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9903 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9904 ) ,
+ .Reset_W_in ( ResetWires[262] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9905 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9906 ) ,
+ .Reset_E_out ( ResetWires[263] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[398] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[399] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9907 ) ,
+ .prog_clk_2_N_in ( p3350 ) , .prog_clk_2_S_in ( p1532 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9908 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9909 ) ,
+ .prog_clk_3_S_in ( p1828 ) , .prog_clk_3_N_in ( p3302 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9910 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_2_N_in ( p2449 ) ,
+ .clk_2_S_in ( p2337 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p2522 ) ,
+ .clk_3_N_in ( p2287 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9915 ) ) ;
+cby_1__1_ cby_10__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9916 } ) ,
+ .chany_bottom_in ( sb_1__1__109_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_119_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__119_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__119_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__119_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9917 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9918 ) ,
+ .Test_en_W_in ( Test_enWires[284] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9919 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9920 ) ,
+ .Test_en_E_out ( Test_enWires[285] ) , .pReset_S_in ( pResetWires[591] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9921 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9922 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9923 ) ,
+ .Reset_W_in ( ResetWires[284] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9924 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9925 ) ,
+ .Reset_E_out ( ResetWires[285] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[401] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[402] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p2704 ) ,
+ .prog_clk_2_S_in ( p1996 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9926 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9927 ) ,
+ .prog_clk_3_S_in ( p2053 ) , .prog_clk_3_N_in ( p2584 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9928 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_2_N_in ( p3545 ) ,
+ .clk_2_S_in ( p3408 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p3444 ) ,
+ .clk_3_N_in ( p3523 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9933 ) ) ;
+cby_1__1_ cby_11__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9934 } ) ,
+ .chany_bottom_in ( sb_1__0__10_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__110_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_120_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__120_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__120_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__120_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9935 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9936 ) ,
+ .Test_en_W_in ( Test_enWires[44] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9937 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9938 ) ,
+ .Test_en_E_out ( Test_enWires[45] ) , .pReset_S_in ( pResetWires[57] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9939 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9940 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9941 ) ,
+ .Reset_W_in ( ResetWires[44] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9942 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9943 ) ,
+ .Reset_E_out ( ResetWires[45] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[406] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[407] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9944 ) ,
+ .prog_clk_2_N_in ( p2494 ) , .prog_clk_2_S_in ( p1915 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9945 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9946 ) ,
+ .prog_clk_3_S_in ( p2104 ) , .prog_clk_3_N_in ( p2292 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9947 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_2_N_in ( p2225 ) ,
+ .clk_2_S_in ( p1486 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p1729 ) ,
+ .clk_3_N_in ( p2029 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9952 ) ) ;
+cby_1__1_ cby_11__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9953 } ) ,
+ .chany_bottom_in ( sb_1__1__110_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__111_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_121_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__121_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__121_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__121_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9954 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9955 ) ,
+ .Test_en_W_in ( Test_enWires[66] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9956 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9957 ) ,
+ .Test_en_E_out ( Test_enWires[67] ) , .pReset_S_in ( pResetWires[105] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9958 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9959 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9960 ) ,
+ .Reset_W_in ( ResetWires[66] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9961 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9962 ) ,
+ .Reset_E_out ( ResetWires[67] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[409] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[410] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9963 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[115] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9964 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[116] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9965 ) ,
+ .prog_clk_3_S_in ( p1734 ) , .prog_clk_3_N_in ( p860 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9966 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9967 ) ,
+ .clk_2_N_in ( clk_2_wires[115] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9968 ) ,
+ .clk_2_S_out ( clk_2_wires[116] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p1734 ) ,
+ .clk_3_N_in ( p707 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9971 ) ) ;
+cby_1__1_ cby_11__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9972 } ) ,
+ .chany_bottom_in ( sb_1__1__111_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__112_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_122_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__122_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__122_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__122_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9973 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9974 ) ,
+ .Test_en_W_in ( Test_enWires[88] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9975 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9976 ) ,
+ .Test_en_E_out ( Test_enWires[89] ) , .pReset_S_in ( pResetWires[154] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9977 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9978 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9979 ) ,
+ .Reset_W_in ( ResetWires[88] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9980 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_9981 ) ,
+ .Reset_E_out ( ResetWires[89] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[412] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[413] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9982 ) ,
+ .prog_clk_2_N_in ( p2968 ) , .prog_clk_2_S_in ( p1009 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9983 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9984 ) ,
+ .prog_clk_3_S_in ( p1106 ) , .prog_clk_3_N_in ( p2887 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9985 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_2_N_in ( p3422 ) ,
+ .clk_2_S_in ( p2271 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p2470 ) ,
+ .clk_3_N_in ( p3393 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9990 ) ) ;
+cby_1__1_ cby_11__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_9991 } ) ,
+ .chany_bottom_in ( sb_1__1__112_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__113_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_123_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__123_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__123_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__123_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9992 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9993 ) ,
+ .Test_en_W_in ( Test_enWires[110] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9994 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9995 ) ,
+ .Test_en_E_out ( Test_enWires[111] ) , .pReset_S_in ( pResetWires[203] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_9996 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_9997 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_9998 ) ,
+ .Reset_W_in ( ResetWires[110] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_9999 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10000 ) ,
+ .Reset_E_out ( ResetWires[111] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[415] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[416] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10001 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[122] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10002 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[123] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10003 ) ,
+ .prog_clk_3_S_in ( p1258 ) , .prog_clk_3_N_in ( p294 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10004 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10005 ) ,
+ .clk_2_N_in ( clk_2_wires[122] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10006 ) ,
+ .clk_2_S_out ( clk_2_wires[123] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1258 ) ,
+ .clk_3_N_in ( p944 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10009 ) ) ;
+cby_1__1_ cby_11__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10010 } ) ,
+ .chany_bottom_in ( sb_1__1__113_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__114_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_124_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__124_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__124_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__124_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10011 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10012 ) ,
+ .Test_en_W_in ( Test_enWires[132] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10013 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10014 ) ,
+ .Test_en_E_out ( Test_enWires[133] ) , .pReset_S_in ( pResetWires[252] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10015 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10016 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10017 ) ,
+ .Reset_W_in ( ResetWires[132] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10018 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10019 ) ,
+ .Reset_E_out ( ResetWires[133] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[418] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[419] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10020 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10021 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[120] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10022 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1443 ) ,
+ .prog_clk_3_N_in ( p36 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10023 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10024 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10025 ) ,
+ .clk_2_S_in ( clk_2_wires[120] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10026 ) ,
+ .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1629 ) ,
+ .clk_3_N_in ( p930 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10028 ) ) ;
+cby_1__1_ cby_11__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10029 } ) ,
+ .chany_bottom_in ( sb_1__1__114_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__115_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_125_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__125_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__125_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__125_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10030 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10031 ) ,
+ .Test_en_W_in ( Test_enWires[154] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10032 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10033 ) ,
+ .Test_en_E_out ( Test_enWires[155] ) , .pReset_S_in ( pResetWires[301] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10034 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10035 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10036 ) ,
+ .Reset_W_in ( ResetWires[154] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10037 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10038 ) ,
+ .Reset_E_out ( ResetWires[155] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[421] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[422] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10039 ) ,
+ .prog_clk_2_N_in ( p3156 ) , .prog_clk_2_S_in ( p1525 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10040 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10041 ) ,
+ .prog_clk_3_S_in ( p1892 ) , .prog_clk_3_N_in ( p3013 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10042 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_2_N_in ( p2189 ) ,
+ .clk_2_S_in ( p552 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p1387 ) ,
+ .clk_3_N_in ( p2012 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10047 ) ) ;
+cby_1__1_ cby_11__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10048 } ) ,
+ .chany_bottom_in ( sb_1__1__115_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__116_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_126_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__126_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__126_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__126_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10049 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10050 ) ,
+ .Test_en_W_in ( Test_enWires[176] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10051 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10052 ) ,
+ .Test_en_E_out ( Test_enWires[177] ) , .pReset_S_in ( pResetWires[350] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10053 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10054 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10055 ) ,
+ .Reset_W_in ( ResetWires[176] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10056 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10057 ) ,
+ .Reset_E_out ( ResetWires[177] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[424] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[425] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10058 ) ,
+ .prog_clk_2_N_in ( p2199 ) , .prog_clk_2_S_in ( p1910 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10059 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10060 ) ,
+ .prog_clk_3_S_in ( p2062 ) , .prog_clk_3_N_in ( p1997 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10061 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_2_N_in ( p3276 ) ,
+ .clk_2_S_in ( p2256 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p2507 ) ,
+ .clk_3_N_in ( p3171 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10066 ) ) ;
+cby_1__1_ cby_11__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10067 } ) ,
+ .chany_bottom_in ( sb_1__1__116_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__117_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_127_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__127_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__127_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__127_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10068 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10069 ) ,
+ .Test_en_W_in ( Test_enWires[198] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10070 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10071 ) ,
+ .Test_en_E_out ( Test_enWires[199] ) , .pReset_S_in ( pResetWires[399] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10072 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10073 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10074 ) ,
+ .Reset_W_in ( ResetWires[198] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10075 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10076 ) ,
+ .Reset_E_out ( ResetWires[199] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[427] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[428] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10077 ) ,
+ .prog_clk_2_N_in ( prog_clk_2_wires[129] ) ,
+ .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10078 ) ,
+ .prog_clk_2_S_out ( prog_clk_2_wires[130] ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10079 ) ,
+ .prog_clk_3_S_in ( p2219 ) , .prog_clk_3_N_in ( p670 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10080 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10081 ) ,
+ .clk_2_N_in ( clk_2_wires[129] ) ,
+ .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10082 ) ,
+ .clk_2_S_out ( clk_2_wires[130] ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p2220 ) ,
+ .clk_3_N_in ( p496 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10085 ) ) ;
+cby_1__1_ cby_11__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10086 } ) ,
+ .chany_bottom_in ( sb_1__1__117_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__118_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_128_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__128_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__128_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__128_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10087 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10088 ) ,
+ .Test_en_W_in ( Test_enWires[220] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10089 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10090 ) ,
+ .Test_en_E_out ( Test_enWires[221] ) , .pReset_S_in ( pResetWires[448] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10091 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10092 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10093 ) ,
+ .Reset_W_in ( ResetWires[220] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10094 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10095 ) ,
+ .Reset_E_out ( ResetWires[221] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[430] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[431] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10096 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10097 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[127] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10098 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1308 ) ,
+ .prog_clk_3_N_in ( p884 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10099 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10100 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10101 ) ,
+ .clk_2_S_in ( clk_2_wires[127] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10102 ) ,
+ .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1392 ) ,
+ .clk_3_N_in ( p809 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10104 ) ) ;
+cby_1__1_ cby_11__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10105 } ) ,
+ .chany_bottom_in ( sb_1__1__118_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__119_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_129_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__129_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__129_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__129_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10106 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10107 ) ,
+ .Test_en_W_in ( Test_enWires[242] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10108 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10109 ) ,
+ .Test_en_E_out ( Test_enWires[243] ) , .pReset_S_in ( pResetWires[497] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10110 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10111 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10112 ) ,
+ .Reset_W_in ( ResetWires[242] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10113 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10114 ) ,
+ .Reset_E_out ( ResetWires[243] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[433] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[434] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10115 ) ,
+ .prog_clk_2_N_in ( p3102 ) , .prog_clk_2_S_in ( p2366 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10116 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10117 ) ,
+ .prog_clk_3_S_in ( p2506 ) , .prog_clk_3_N_in ( p3015 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10118 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_2_N_in ( p3543 ) ,
+ .clk_2_S_in ( p2052 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p2134 ) ,
+ .clk_3_N_in ( p3520 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10123 ) ) ;
+cby_1__1_ cby_11__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10124 } ) ,
+ .chany_bottom_in ( sb_1__1__119_chany_top_out ) ,
+ .chany_top_in ( sb_1__1__120_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_130_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__130_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__130_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__130_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10125 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10126 ) ,
+ .Test_en_W_in ( Test_enWires[264] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10127 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10128 ) ,
+ .Test_en_E_out ( Test_enWires[265] ) , .pReset_S_in ( pResetWires[546] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10129 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10130 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10131 ) ,
+ .Reset_W_in ( ResetWires[264] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10132 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10133 ) ,
+ .Reset_E_out ( ResetWires[265] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[436] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[437] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10134 ) ,
+ .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10135 ) ,
+ .prog_clk_2_S_in ( prog_clk_2_wires[134] ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10136 ) ,
+ .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1345 ) ,
+ .prog_clk_3_N_in ( p422 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10137 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10138 ) ,
+ .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10139 ) ,
+ .clk_2_S_in ( clk_2_wires[134] ) ,
+ .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10140 ) ,
+ .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1288 ) ,
+ .clk_3_N_in ( p323 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10142 ) ) ;
+cby_1__1_ cby_11__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10143 } ) ,
+ .chany_bottom_in ( sb_1__1__120_chany_top_out ) ,
+ .chany_top_in ( sb_1__12__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_131_ccff_tail ) ,
+ .chany_bottom_out ( cby_1__1__131_chany_bottom_out ) ,
+ .chany_top_out ( cby_1__1__131_chany_top_out ) ,
+ .left_grid_pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) ,
+ .ccff_tail ( cby_1__1__131_ccff_tail ) ,
+ .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10144 ) ,
+ .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10145 ) ,
+ .Test_en_W_in ( Test_enWires[286] ) ,
+ .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10146 ) ,
+ .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10147 ) ,
+ .Test_en_E_out ( Test_enWires[287] ) , .pReset_S_in ( pResetWires[595] ) ,
+ .pReset_N_out ( SYNOPSYS_UNCONNECTED_10148 ) ,
+ .Reset_S_in ( SYNOPSYS_UNCONNECTED_10149 ) ,
+ .Reset_E_in ( SYNOPSYS_UNCONNECTED_10150 ) ,
+ .Reset_W_in ( ResetWires[286] ) ,
+ .Reset_N_out ( SYNOPSYS_UNCONNECTED_10151 ) ,
+ .Reset_W_out ( SYNOPSYS_UNCONNECTED_10152 ) ,
+ .Reset_E_out ( ResetWires[287] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[439] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[440] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p3429 ) ,
+ .prog_clk_2_S_in ( p1589 ) ,
+ .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10153 ) ,
+ .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10154 ) ,
+ .prog_clk_3_S_in ( p1787 ) , .prog_clk_3_N_in ( p3399 ) ,
+ .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10155 ) ,
+ .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_2_N_in ( p2463 ) ,
+ .clk_2_S_in ( p2274 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) ,
+ .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p2476 ) ,
+ .clk_3_N_in ( p2295 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) ,
+ .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10160 ) ) ;
+cby_2__1_ cby_12__1_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10161 } ) ,
+ .chany_bottom_in ( sb_12__0__0_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_132_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__0_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__0_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[60] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[444] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[445] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10162 ) ) ;
+cby_2__1_ cby_12__2_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10163 } ) ,
+ .chany_bottom_in ( sb_12__1__0_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__1_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_133_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__1_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__1_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[109] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[447] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[448] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10164 ) ) ;
+cby_2__1_ cby_12__3_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10165 } ) ,
+ .chany_bottom_in ( sb_12__1__1_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__2_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_134_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__2_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__2_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[158] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[450] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[451] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10166 ) ) ;
+cby_2__1_ cby_12__4_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10167 } ) ,
+ .chany_bottom_in ( sb_12__1__2_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__3_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_135_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__3_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__3_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[207] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[453] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[454] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10168 ) ) ;
+cby_2__1_ cby_12__5_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10169 } ) ,
+ .chany_bottom_in ( sb_12__1__3_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__4_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_136_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__4_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__4_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[256] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[456] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[457] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10170 ) ) ;
+cby_2__1_ cby_12__6_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10171 } ) ,
+ .chany_bottom_in ( sb_12__1__4_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__5_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_137_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__5_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__5_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[305] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[459] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[460] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10172 ) ) ;
+cby_2__1_ cby_12__7_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10173 } ) ,
+ .chany_bottom_in ( sb_12__1__5_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__6_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_138_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__6_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__6_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[354] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[462] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[463] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10174 ) ) ;
+cby_2__1_ cby_12__8_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10175 } ) ,
+ .chany_bottom_in ( sb_12__1__6_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__7_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_139_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__7_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__7_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[403] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[465] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[466] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10176 ) ) ;
+cby_2__1_ cby_12__9_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10177 } ) ,
+ .chany_bottom_in ( sb_12__1__7_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__8_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_140_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__8_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__8_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[452] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[468] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[469] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10178 ) ) ;
+cby_2__1_ cby_12__10_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10179 } ) ,
+ .chany_bottom_in ( sb_12__1__8_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__9_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_141_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__9_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__9_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[501] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[471] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[472] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10180 ) ) ;
+cby_2__1_ cby_12__11_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10181 } ) ,
+ .chany_bottom_in ( sb_12__1__9_chany_top_out ) ,
+ .chany_top_in ( sb_12__1__10_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_142_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__10_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__10_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[550] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[474] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[475] ) ,
+ .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10182 ) ) ;
+cby_2__1_ cby_12__12_ (
+ .pReset ( { SYNOPSYS_UNCONNECTED_10183 } ) ,
+ .chany_bottom_in ( sb_12__1__10_chany_top_out ) ,
+ .chany_top_in ( sb_12__12__0_chany_bottom_out ) ,
+ .ccff_head ( grid_clb_143_ccff_tail ) ,
+ .chany_bottom_out ( cby_12__1__11_chany_bottom_out ) ,
+ .chany_top_out ( cby_12__1__11_chany_top_out ) ,
+ .right_grid_pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) ,
+ .left_grid_pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) ,
+ .left_grid_pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) ,
+ .left_grid_pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) ,
+ .left_grid_pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) ,
+ .left_grid_pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) ,
+ .left_grid_pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) ,
+ .left_grid_pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) ,
+ .left_grid_pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) ,
+ .left_grid_pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) ,
+ .left_grid_pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) ,
+ .left_grid_pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) ,
+ .left_grid_pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) ,
+ .left_grid_pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) ,
+ .left_grid_pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) ,
+ .left_grid_pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) ,
+ .left_grid_pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) ,
+ .ccff_tail ( grid_io_right_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] ) ,
+ .left_width_0_height_0__pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) ,
+ .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) ,
+ .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ,
+ .pReset_S_in ( pResetWires[599] ) ,
+ .prog_clk_0_W_in ( prog_clk_0_wires[477] ) ,
+ .prog_clk_0_S_out ( prog_clk_0_wires[478] ) ,
+ .prog_clk_0_N_out ( prog_clk_0_wires[480] ) ) ;
+endmodule
+
+
+module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 ,
+ vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i ,
+ wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in ,
+ la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ ,
+ analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ ,
+ analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ ,
+ analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ ,
+ analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ ,
+ analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ ,
+ analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ ,
+ analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ ,
+ analog_io_9_ , user_clock2 ) ;
+inout vdda1 ;
+inout vdda2 ;
+inout vssa1 ;
+inout vssa2 ;
+inout vccd1 ;
+inout vccd2 ;
+inout vssd1 ;
+inout vssd2 ;
+input wb_clk_i ;
+input wb_rst_i ;
+input wbs_stb_i ;
+input wbs_cyc_i ;
+input wbs_we_i ;
+input [3:0] wbs_sel_i ;
+input [31:0] wbs_dat_i ;
+input [31:0] wbs_adr_i ;
+output wbs_ack_o ;
+output [31:0] wbs_dat_o ;
+input [127:0] la_data_in ;
+output [127:0] la_data_out ;
+input [127:0] la_oen ;
+input [37:0] io_in ;
+output [37:0] io_out ;
+output [37:0] io_oeb ;
+inout analog_io_0_ ;
+inout analog_io_10_ ;
+inout analog_io_11_ ;
+inout analog_io_12_ ;
+inout analog_io_13_ ;
+inout analog_io_14_ ;
+inout analog_io_15_ ;
+inout analog_io_16_ ;
+inout analog_io_17_ ;
+inout analog_io_18_ ;
+inout analog_io_19_ ;
+inout analog_io_1_ ;
+inout analog_io_20_ ;
+inout analog_io_21_ ;
+inout analog_io_22_ ;
+inout analog_io_23_ ;
+inout analog_io_24_ ;
+inout analog_io_25_ ;
+inout analog_io_26_ ;
+inout analog_io_27_ ;
+inout analog_io_28_ ;
+inout analog_io_29_ ;
+inout analog_io_2_ ;
+inout analog_io_30_ ;
+inout analog_io_3_ ;
+inout analog_io_4_ ;
+inout analog_io_5_ ;
+inout analog_io_6_ ;
+inout analog_io_7_ ;
+inout analog_io_8_ ;
+inout analog_io_9_ ;
+input user_clock2 ;
+
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+wire ccff_head ;
+wire sc_tail ;
+wire pReset ;
+wire Reset ;
+wire IO_ISOL_N ;
+wire Test_en ;
+wire prog_clk ;
+wire clk ;
+wire ccff_tail ;
+wire sc_head ;
+wire wb_la_switch ;
+
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ;
+assign ccff_head = io_in[12] ;
+assign sc_tail = io_out[11] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ;
+assign pReset = io_in[3] ;
+assign Reset = io_in[2] ;
+assign IO_ISOL_N = io_in[1] ;
+assign Test_en = io_in[0] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = la_data_out[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = la_data_out[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[84] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[83] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[82] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[81] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[80] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[79] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[78] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[77] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[76] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[75] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[74] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[73] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[72] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[71] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[70] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[69] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[68] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[67] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[66] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[65] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[64] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[63] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[62] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[61] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[60] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[59] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[58] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[57] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[56] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[55] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[54] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[53] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[52] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[51] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[50] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[49] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[48] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[47] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[46] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[45] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[44] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[43] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[42] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[41] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[40] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[39] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[38] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[37] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[36] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[26] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[25] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[12] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[11] ;
+assign prog_clk = io_in[37] ;
+assign clk = io_in[36] ;
+assign ccff_tail = io_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ;
+assign sc_head = io_in[26] ;
+assign wb_la_switch = io_in[25] ;
+
+sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) ,
+ .Y ( wb_la_switch_b ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[0] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[116] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[1] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[115] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[2] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[114] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[3] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[113] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[4] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[112] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[5] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[111] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[6] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[110] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[7] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[109] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[8] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[108] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[9] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[107] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[10] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[106] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[11] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[105] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[12] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[104] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[13] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[103] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[14] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[102] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[15] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[101] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[16] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[100] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[17] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[99] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[18] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[98] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[19] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[97] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[20] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[96] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[21] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[95] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[22] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[94] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[23] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[93] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[24] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[92] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[25] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[91] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[26] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[90] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[27] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[89] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[28] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[88] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[29] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[87] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[30] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[86] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[31] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) ,
+ .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) ,
+ .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) ,
+ .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) ,
+ .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) ,
+ .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) ,
+ .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) ,
+ .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) ,
+ .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) ,
+ .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) ,
+ .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) ,
+ .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) ,
+ .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) ,
+ .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) ,
+ .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) ,
+ .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) ,
+ .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) ,
+ .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) ,
+ .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) ,
+ .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) ,
+ .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) ,
+ .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) ,
+ .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) ,
+ .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) ,
+ .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) ,
+ .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) ,
+ .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) ,
+ .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) ,
+ .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) ,
+ .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) ,
+ .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) ,
+ .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) ,
+ .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) ,
+ .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) ,
+ .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) ,
+ .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) ,
+ .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) ,
+ .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) ,
+ .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) ,
+ .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) ,
+ .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) ,
+ .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) ,
+ .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) ,
+ .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) ,
+ .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) ,
+ .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) ,
+ .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) ,
+ .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) ,
+ .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) ,
+ .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) ,
+ .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) ,
+ .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) ,
+ .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) ,
+ .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) ,
+ .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) ,
+ .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) ,
+ .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) ,
+ .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) ,
+ .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) ,
+ .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) ,
+ .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) ,
+ .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) ,
+ .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) ,
+ .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) ,
+ .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) ,
+ .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) ,
+ .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) ,
+ .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) ,
+ .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) ,
+ .A1 ( wbs_we_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) ,
+ .A1 ( wbs_stb_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) ,
+ .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_ack_o ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[13] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) ,
+ .A1 ( wb_rst_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) ,
+ .A1 ( wb_clk_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ;
+fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) ,
+ .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) ,
+ .Reset ( io_in[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] ,
+ io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] ,
+ io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] ,
+ io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] ,
+ la_data_in[127] , la_data_in[126] , la_data_in[125] ,
+ la_data_in[124] , la_data_in[123] , la_data_in[122] ,
+ la_data_in[121] , la_data_in[120] , la_data_in[119] ,
+ la_data_in[118] , la_data_in[117] , la_data_in[116] ,
+ la_data_in[115] , la_data_in[114] , la_data_in[113] ,
+ la_data_in[112] , la_data_in[111] , la_data_in[110] ,
+ la_data_in[109] , la_data_in[108] , la_data_in[107] ,
+ la_data_in[106] , la_data_in[105] , la_data_in[104] ,
+ la_data_in[103] , la_data_in[102] , la_data_in[101] ,
+ la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] ,
+ la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] ,
+ la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] ,
+ la_data_in[88] , la_data_in[87] , la_data_in[86] , la_data_in[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[13] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] ,
+ io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] ,
+ io_in[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] ,
+ io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] ,
+ io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] ,
+ io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] ,
+ io_out[5] , io_out[4] , la_data_out[127] , la_data_out[126] ,
+ la_data_out[125] , la_data_out[124] , la_data_out[123] ,
+ la_data_out[122] , la_data_out[121] , la_data_out[120] ,
+ la_data_out[119] , la_data_out[118] , la_data_out[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[84] ,
+ la_data_out[83] , la_data_out[82] , la_data_out[81] ,
+ la_data_out[80] , la_data_out[79] , la_data_out[78] ,
+ la_data_out[77] , la_data_out[76] , la_data_out[75] ,
+ la_data_out[74] , la_data_out[73] , la_data_out[72] ,
+ la_data_out[71] , la_data_out[70] , la_data_out[69] ,
+ la_data_out[68] , la_data_out[67] , la_data_out[66] ,
+ la_data_out[65] , la_data_out[64] , la_data_out[63] ,
+ la_data_out[62] , la_data_out[61] , la_data_out[60] ,
+ la_data_out[59] , la_data_out[58] , la_data_out[57] ,
+ la_data_out[56] , la_data_out[55] , la_data_out[54] ,
+ la_data_out[53] , la_data_out[52] , la_data_out[51] ,
+ la_data_out[50] , la_data_out[49] , la_data_out[48] ,
+ la_data_out[47] , la_data_out[46] , la_data_out[45] ,
+ la_data_out[44] , la_data_out[43] , la_data_out[42] ,
+ la_data_out[41] , la_data_out[40] , la_data_out[39] ,
+ la_data_out[38] , la_data_out[37] , la_data_out[36] ,
+ la_data_out[35] , la_data_out[34] , la_data_out[33] ,
+ la_data_out[32] , la_data_out[31] , la_data_out[30] ,
+ la_data_out[29] , la_data_out[28] , la_data_out[27] ,
+ la_data_out[26] , la_data_out[25] , la_data_out[24] ,
+ la_data_out[23] , la_data_out[22] , la_data_out[21] ,
+ la_data_out[20] , la_data_out[19] , la_data_out[18] ,
+ la_data_out[17] , la_data_out[16] , la_data_out[15] ,
+ la_data_out[14] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ,
+ la_data_out[12] , la_data_out[11] , io_out[34] , io_out[33] ,
+ io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] ,
+ io_out[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] ,
+ io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] ,
+ io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] ,
+ io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] ,
+ io_oeb[5] , io_oeb[4] , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] ,
+ io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] ,
+ io_oeb[27] } ) ,
+ .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) ,
+ .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) ,
+ .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , .p0 ( optlc_net_20 ) ,
+ .p1 ( optlc_net_21 ) , .p2 ( optlc_net_22 ) , .p3 ( optlc_net_23 ) ,
+ .p4 ( optlc_net_24 ) , .p5 ( optlc_net_25 ) , .p6 ( optlc_net_26 ) ,
+ .p7 ( optlc_net_27 ) , .p8 ( optlc_net_28 ) , .p9 ( optlc_net_29 ) ,
+ .p10 ( optlc_net_30 ) , .p11 ( optlc_net_31 ) , .p12 ( optlc_net_32 ) ,
+ .p13 ( optlc_net_33 ) , .p14 ( optlc_net_34 ) , .p15 ( optlc_net_35 ) ,
+ .p16 ( optlc_net_36 ) , .p17 ( optlc_net_37 ) , .p18 ( optlc_net_38 ) ,
+ .p19 ( optlc_net_39 ) , .p20 ( optlc_net_40 ) , .p21 ( optlc_net_41 ) ,
+ .p22 ( optlc_net_42 ) , .p23 ( optlc_net_43 ) , .p24 ( optlc_net_44 ) ,
+ .p25 ( optlc_net_45 ) , .p26 ( optlc_net_46 ) , .p27 ( optlc_net_47 ) ,
+ .p28 ( optlc_net_48 ) , .p29 ( optlc_net_49 ) , .p30 ( optlc_net_50 ) ,
+ .p31 ( optlc_net_51 ) , .p32 ( optlc_net_52 ) , .p33 ( optlc_net_53 ) ,
+ .p34 ( optlc_net_54 ) , .p35 ( optlc_net_55 ) , .p36 ( optlc_net_56 ) ,
+ .p37 ( optlc_net_57 ) , .p38 ( optlc_net_58 ) , .p39 ( optlc_net_59 ) ,
+ .p40 ( optlc_net_60 ) , .p41 ( optlc_net_61 ) , .p42 ( optlc_net_62 ) ,
+ .p43 ( optlc_net_63 ) , .p44 ( optlc_net_64 ) , .p45 ( optlc_net_65 ) ,
+ .p46 ( optlc_net_66 ) , .p47 ( optlc_net_67 ) , .p48 ( optlc_net_68 ) ,
+ .p49 ( optlc_net_69 ) , .p50 ( optlc_net_70 ) , .p51 ( optlc_net_71 ) ,
+ .p52 ( optlc_net_72 ) , .p53 ( optlc_net_73 ) , .p54 ( optlc_net_74 ) ,
+ .p55 ( optlc_net_75 ) , .p56 ( optlc_net_76 ) , .p57 ( optlc_net_77 ) ,
+ .p58 ( optlc_net_78 ) , .p59 ( optlc_net_79 ) , .p60 ( optlc_net_80 ) ,
+ .p61 ( optlc_net_81 ) , .p62 ( optlc_net_82 ) , .p63 ( optlc_net_83 ) ,
+ .p64 ( optlc_net_84 ) , .p65 ( optlc_net_85 ) , .p66 ( optlc_net_86 ) ,
+ .p67 ( optlc_net_87 ) , .p68 ( optlc_net_88 ) , .p69 ( optlc_net_89 ) ,
+ .p70 ( optlc_net_90 ) , .p71 ( optlc_net_91 ) , .p72 ( optlc_net_92 ) ,
+ .p73 ( optlc_net_93 ) , .p74 ( optlc_net_94 ) , .p75 ( optlc_net_95 ) ,
+ .p76 ( optlc_net_96 ) , .p77 ( optlc_net_97 ) , .p78 ( optlc_net_98 ) ,
+ .p79 ( optlc_net_99 ) , .p80 ( optlc_net_100 ) , .p81 ( optlc_net_101 ) ,
+ .p82 ( optlc_net_102 ) , .p83 ( optlc_net_103 ) , .p84 ( optlc_net_104 ) ,
+ .p85 ( optlc_net_105 ) , .p86 ( optlc_net_106 ) , .p87 ( optlc_net_107 ) ,
+ .p88 ( optlc_net_108 ) , .p89 ( optlc_net_109 ) , .p90 ( optlc_net_110 ) ,
+ .p91 ( optlc_net_111 ) , .p92 ( optlc_net_112 ) , .p93 ( optlc_net_113 ) ,
+ .p94 ( optlc_net_114 ) , .p95 ( optlc_net_115 ) , .p96 ( optlc_net_116 ) ,
+ .p97 ( optlc_net_117 ) , .p98 ( optlc_net_118 ) , .p99 ( optlc_net_119 ) ,
+ .p100 ( optlc_net_120 ) , .p101 ( optlc_net_121 ) ,
+ .p102 ( optlc_net_122 ) , .p103 ( optlc_net_123 ) ,
+ .p104 ( optlc_net_124 ) , .p105 ( optlc_net_125 ) ,
+ .p106 ( optlc_net_126 ) , .p107 ( optlc_net_127 ) ,
+ .p108 ( optlc_net_128 ) , .p109 ( optlc_net_129 ) ,
+ .p110 ( optlc_net_130 ) , .p111 ( optlc_net_131 ) ,
+ .p112 ( optlc_net_132 ) , .p113 ( optlc_net_133 ) ,
+ .p114 ( optlc_net_134 ) , .p115 ( optlc_net_135 ) ,
+ .p116 ( optlc_net_136 ) , .p117 ( optlc_net_137 ) ,
+ .p118 ( optlc_net_138 ) , .p119 ( optlc_net_139 ) ,
+ .p120 ( optlc_net_140 ) , .p121 ( optlc_net_141 ) ,
+ .p122 ( optlc_net_142 ) , .p123 ( optlc_net_143 ) ,
+ .p124 ( optlc_net_144 ) , .p125 ( optlc_net_145 ) ,
+ .p126 ( optlc_net_146 ) , .p127 ( optlc_net_147 ) ,
+ .p128 ( optlc_net_148 ) , .p129 ( optlc_net_149 ) ,
+ .p130 ( optlc_net_150 ) , .p131 ( optlc_net_151 ) ,
+ .p132 ( optlc_net_152 ) , .p133 ( optlc_net_153 ) ,
+ .p134 ( optlc_net_154 ) , .p135 ( optlc_net_155 ) ,
+ .p136 ( optlc_net_156 ) , .p137 ( optlc_net_157 ) ,
+ .p138 ( optlc_net_158 ) , .p139 ( optlc_net_159 ) ,
+ .p140 ( optlc_net_160 ) , .p141 ( optlc_net_161 ) ,
+ .p142 ( optlc_net_162 ) , .p143 ( optlc_net_163 ) ,
+ .p144 ( optlc_net_164 ) , .p145 ( optlc_net_165 ) ,
+ .p146 ( optlc_net_166 ) , .p147 ( optlc_net_167 ) ,
+ .p148 ( optlc_net_168 ) , .p149 ( optlc_net_169 ) ,
+ .p150 ( optlc_net_170 ) , .p151 ( optlc_net_171 ) ,
+ .p152 ( optlc_net_172 ) , .p153 ( optlc_net_173 ) ,
+ .p154 ( optlc_net_174 ) , .p155 ( optlc_net_175 ) ,
+ .p156 ( optlc_net_176 ) , .p157 ( optlc_net_177 ) ,
+ .p158 ( optlc_net_178 ) , .p159 ( optlc_net_179 ) ,
+ .p160 ( optlc_net_180 ) , .p161 ( optlc_net_181 ) ,
+ .p162 ( optlc_net_182 ) , .p163 ( optlc_net_183 ) ,
+ .p164 ( optlc_net_184 ) , .p165 ( optlc_net_185 ) ,
+ .p166 ( optlc_net_186 ) , .p167 ( optlc_net_187 ) ,
+ .p168 ( optlc_net_188 ) , .p169 ( optlc_net_189 ) ,
+ .p170 ( optlc_net_190 ) , .p171 ( optlc_net_191 ) ,
+ .p172 ( optlc_net_192 ) , .p173 ( optlc_net_193 ) ,
+ .p174 ( optlc_net_194 ) , .p175 ( optlc_net_195 ) ,
+ .p176 ( optlc_net_196 ) , .p177 ( optlc_net_197 ) ,
+ .p178 ( optlc_net_198 ) , .p179 ( optlc_net_199 ) ,
+ .p180 ( optlc_net_200 ) , .p181 ( optlc_net_201 ) ,
+ .p182 ( optlc_net_202 ) , .p183 ( optlc_net_203 ) ,
+ .p184 ( optlc_net_204 ) , .p185 ( optlc_net_205 ) ,
+ .p186 ( optlc_net_206 ) , .p187 ( optlc_net_207 ) ,
+ .p188 ( optlc_net_208 ) , .p189 ( optlc_net_209 ) ,
+ .p190 ( optlc_net_210 ) , .p191 ( optlc_net_211 ) ,
+ .p192 ( optlc_net_212 ) , .p193 ( optlc_net_213 ) ,
+ .p194 ( optlc_net_214 ) , .p195 ( optlc_net_215 ) ,
+ .p196 ( optlc_net_216 ) , .p197 ( optlc_net_217 ) ,
+ .p198 ( optlc_net_218 ) , .p199 ( optlc_net_219 ) ,
+ .p200 ( optlc_net_220 ) , .p201 ( optlc_net_221 ) ,
+ .p202 ( optlc_net_222 ) , .p203 ( optlc_net_223 ) ,
+ .p204 ( optlc_net_224 ) , .p205 ( optlc_net_225 ) ,
+ .p206 ( optlc_net_226 ) , .p207 ( optlc_net_227 ) ,
+ .p208 ( optlc_net_228 ) , .p209 ( optlc_net_229 ) ,
+ .p210 ( optlc_net_230 ) , .p211 ( optlc_net_231 ) ,
+ .p212 ( optlc_net_232 ) , .p213 ( optlc_net_233 ) ,
+ .p214 ( optlc_net_234 ) , .p215 ( optlc_net_235 ) ,
+ .p216 ( optlc_net_236 ) , .p217 ( optlc_net_237 ) ,
+ .p218 ( optlc_net_238 ) , .p219 ( optlc_net_239 ) ,
+ .p220 ( optlc_net_240 ) , .p221 ( optlc_net_241 ) ,
+ .p222 ( optlc_net_242 ) , .p223 ( optlc_net_243 ) ,
+ .p224 ( optlc_net_244 ) , .p225 ( optlc_net_245 ) ,
+ .p226 ( optlc_net_246 ) , .p227 ( optlc_net_247 ) ,
+ .p228 ( optlc_net_248 ) , .p229 ( optlc_net_249 ) ,
+ .p230 ( optlc_net_250 ) , .p231 ( optlc_net_251 ) ,
+ .p232 ( optlc_net_252 ) , .p233 ( optlc_net_253 ) ,
+ .p234 ( optlc_net_254 ) , .p235 ( optlc_net_255 ) ,
+ .p236 ( optlc_net_256 ) , .p237 ( optlc_net_257 ) ,
+ .p238 ( optlc_net_258 ) , .p239 ( optlc_net_259 ) ,
+ .p240 ( optlc_net_260 ) , .p241 ( optlc_net_261 ) ,
+ .p242 ( optlc_net_262 ) , .p243 ( optlc_net_263 ) ,
+ .p244 ( optlc_net_264 ) , .p245 ( optlc_net_265 ) ,
+ .p246 ( optlc_net_266 ) , .p247 ( optlc_net_267 ) ,
+ .p248 ( optlc_net_268 ) , .p249 ( optlc_net_269 ) ,
+ .p250 ( optlc_net_270 ) , .p251 ( optlc_net_271 ) ,
+ .p252 ( optlc_net_272 ) , .p253 ( optlc_net_273 ) ,
+ .p254 ( optlc_net_274 ) , .p255 ( optlc_net_275 ) ,
+ .p256 ( optlc_net_276 ) , .p257 ( optlc_net_277 ) ,
+ .p258 ( optlc_net_278 ) , .p259 ( optlc_net_279 ) ,
+ .p260 ( optlc_net_280 ) , .p261 ( optlc_net_281 ) ,
+ .p262 ( optlc_net_282 ) , .p263 ( optlc_net_283 ) ,
+ .p264 ( optlc_net_284 ) , .p265 ( optlc_net_285 ) ,
+ .p266 ( optlc_net_286 ) , .p267 ( optlc_net_287 ) ,
+ .p268 ( optlc_net_288 ) , .p269 ( optlc_net_289 ) ,
+ .p270 ( optlc_net_290 ) , .p271 ( optlc_net_291 ) ,
+ .p272 ( optlc_net_292 ) , .p273 ( optlc_net_293 ) ,
+ .p274 ( optlc_net_294 ) , .p275 ( optlc_net_295 ) ,
+ .p276 ( optlc_net_296 ) , .p277 ( optlc_net_297 ) ,
+ .p278 ( optlc_net_298 ) , .p279 ( optlc_net_299 ) ,
+ .p280 ( optlc_net_300 ) , .p281 ( optlc_net_301 ) ,
+ .p282 ( optlc_net_302 ) , .p283 ( optlc_net_303 ) ,
+ .p284 ( optlc_net_304 ) , .p285 ( optlc_net_305 ) ,
+ .p286 ( optlc_net_306 ) , .p287 ( optlc_net_307 ) ,
+ .p288 ( optlc_net_308 ) , .p289 ( optlc_net_309 ) ,
+ .p290 ( optlc_net_310 ) , .p291 ( optlc_net_311 ) ,
+ .p292 ( optlc_net_312 ) , .p293 ( optlc_net_313 ) ,
+ .p294 ( optlc_net_314 ) , .p295 ( optlc_net_315 ) ,
+ .p296 ( optlc_net_316 ) , .p297 ( optlc_net_317 ) ,
+ .p298 ( optlc_net_318 ) , .p299 ( optlc_net_319 ) ,
+ .p300 ( optlc_net_320 ) , .p301 ( optlc_net_321 ) ,
+ .p302 ( optlc_net_322 ) , .p303 ( optlc_net_323 ) ,
+ .p304 ( optlc_net_324 ) , .p305 ( optlc_net_325 ) ,
+ .p306 ( optlc_net_326 ) , .p307 ( optlc_net_327 ) ,
+ .p308 ( optlc_net_328 ) , .p309 ( optlc_net_329 ) ,
+ .p310 ( optlc_net_330 ) , .p311 ( optlc_net_331 ) ,
+ .p312 ( optlc_net_332 ) , .p313 ( optlc_net_333 ) ,
+ .p314 ( optlc_net_334 ) , .p315 ( optlc_net_335 ) ,
+ .p316 ( optlc_net_336 ) , .p317 ( optlc_net_337 ) ,
+ .p318 ( optlc_net_338 ) , .p319 ( optlc_net_339 ) ,
+ .p320 ( optlc_net_340 ) , .p321 ( optlc_net_341 ) ,
+ .p322 ( optlc_net_342 ) , .p323 ( optlc_net_343 ) ,
+ .p324 ( optlc_net_344 ) , .p325 ( optlc_net_345 ) ,
+ .p326 ( optlc_net_346 ) , .p327 ( optlc_net_347 ) ,
+ .p328 ( optlc_net_348 ) , .p329 ( optlc_net_349 ) ,
+ .p330 ( optlc_net_350 ) , .p331 ( optlc_net_351 ) ,
+ .p332 ( optlc_net_352 ) , .p333 ( optlc_net_353 ) ,
+ .p334 ( optlc_net_354 ) , .p335 ( optlc_net_355 ) ,
+ .p336 ( optlc_net_356 ) , .p337 ( optlc_net_357 ) ,
+ .p338 ( optlc_net_358 ) , .p339 ( optlc_net_359 ) ,
+ .p340 ( optlc_net_360 ) , .p341 ( optlc_net_361 ) ,
+ .p342 ( optlc_net_362 ) , .p343 ( optlc_net_363 ) ,
+ .p344 ( optlc_net_364 ) , .p345 ( optlc_net_365 ) ,
+ .p346 ( optlc_net_366 ) , .p347 ( optlc_net_367 ) ,
+ .p348 ( optlc_net_368 ) , .p349 ( optlc_net_369 ) ,
+ .p350 ( optlc_net_370 ) , .p351 ( optlc_net_371 ) ,
+ .p352 ( optlc_net_372 ) , .p353 ( optlc_net_373 ) ,
+ .p354 ( optlc_net_374 ) , .p355 ( optlc_net_375 ) ,
+ .p356 ( optlc_net_376 ) , .p357 ( optlc_net_377 ) ,
+ .p358 ( optlc_net_378 ) , .p359 ( optlc_net_379 ) ,
+ .p360 ( optlc_net_380 ) , .p361 ( optlc_net_381 ) ,
+ .p362 ( optlc_net_382 ) , .p363 ( optlc_net_383 ) ,
+ .p364 ( optlc_net_384 ) , .p365 ( optlc_net_385 ) ,
+ .p366 ( optlc_net_386 ) , .p367 ( optlc_net_387 ) ,
+ .p368 ( optlc_net_388 ) , .p369 ( optlc_net_389 ) ,
+ .p370 ( optlc_net_390 ) , .p371 ( optlc_net_391 ) ,
+ .p372 ( optlc_net_392 ) , .p373 ( optlc_net_393 ) ,
+ .p374 ( optlc_net_394 ) , .p375 ( optlc_net_395 ) ,
+ .p376 ( optlc_net_396 ) , .p377 ( optlc_net_397 ) ,
+ .p378 ( optlc_net_398 ) , .p379 ( optlc_net_399 ) ,
+ .p380 ( optlc_net_400 ) , .p381 ( optlc_net_401 ) ,
+ .p382 ( optlc_net_402 ) , .p383 ( optlc_net_403 ) ,
+ .p384 ( optlc_net_404 ) , .p385 ( optlc_net_405 ) ,
+ .p386 ( optlc_net_406 ) , .p387 ( optlc_net_407 ) ,
+ .p388 ( optlc_net_408 ) , .p389 ( optlc_net_409 ) ,
+ .p390 ( optlc_net_410 ) , .p391 ( optlc_net_411 ) ,
+ .p392 ( optlc_net_412 ) , .p393 ( optlc_net_413 ) ,
+ .p394 ( optlc_net_414 ) , .p395 ( optlc_net_415 ) ,
+ .p396 ( optlc_net_416 ) , .p397 ( optlc_net_417 ) ,
+ .p398 ( optlc_net_418 ) , .p399 ( optlc_net_419 ) ,
+ .p400 ( optlc_net_420 ) , .p401 ( optlc_net_421 ) ,
+ .p402 ( optlc_net_422 ) , .p403 ( optlc_net_423 ) ,
+ .p404 ( optlc_net_424 ) , .p405 ( optlc_net_425 ) ,
+ .p406 ( optlc_net_426 ) , .p407 ( optlc_net_427 ) ,
+ .p408 ( optlc_net_428 ) , .p409 ( optlc_net_429 ) ,
+ .p410 ( optlc_net_430 ) , .p411 ( optlc_net_431 ) ,
+ .p412 ( optlc_net_432 ) , .p413 ( optlc_net_433 ) ,
+ .p414 ( optlc_net_434 ) , .p415 ( optlc_net_435 ) ,
+ .p416 ( optlc_net_436 ) , .p417 ( optlc_net_437 ) ,
+ .p418 ( optlc_net_438 ) , .p419 ( optlc_net_439 ) ,
+ .p420 ( optlc_net_440 ) , .p421 ( optlc_net_441 ) ,
+ .p422 ( optlc_net_442 ) , .p423 ( optlc_net_443 ) ,
+ .p424 ( optlc_net_444 ) , .p425 ( optlc_net_445 ) ,
+ .p426 ( optlc_net_446 ) , .p427 ( optlc_net_447 ) ,
+ .p428 ( optlc_net_448 ) , .p429 ( optlc_net_449 ) ,
+ .p430 ( optlc_net_450 ) , .p431 ( optlc_net_451 ) ,
+ .p432 ( optlc_net_452 ) , .p433 ( optlc_net_453 ) ,
+ .p434 ( optlc_net_454 ) , .p435 ( optlc_net_455 ) ,
+ .p436 ( optlc_net_456 ) , .p437 ( optlc_net_457 ) ,
+ .p438 ( optlc_net_458 ) , .p439 ( optlc_net_459 ) ,
+ .p440 ( optlc_net_460 ) , .p441 ( optlc_net_461 ) ,
+ .p442 ( optlc_net_462 ) , .p443 ( optlc_net_463 ) ,
+ .p444 ( optlc_net_464 ) , .p445 ( optlc_net_465 ) ,
+ .p446 ( optlc_net_466 ) , .p447 ( optlc_net_467 ) ,
+ .p448 ( optlc_net_468 ) , .p449 ( optlc_net_469 ) ,
+ .p450 ( optlc_net_470 ) , .p451 ( optlc_net_471 ) ,
+ .p452 ( optlc_net_472 ) , .p453 ( optlc_net_473 ) ,
+ .p454 ( optlc_net_474 ) , .p455 ( optlc_net_475 ) ,
+ .p456 ( optlc_net_476 ) , .p457 ( optlc_net_477 ) ,
+ .p458 ( optlc_net_478 ) , .p459 ( optlc_net_479 ) ,
+ .p460 ( optlc_net_480 ) , .p461 ( optlc_net_481 ) ,
+ .p462 ( optlc_net_482 ) , .p463 ( optlc_net_483 ) ,
+ .p464 ( optlc_net_484 ) , .p465 ( optlc_net_485 ) ,
+ .p466 ( optlc_net_486 ) , .p467 ( optlc_net_487 ) ,
+ .p468 ( optlc_net_488 ) , .p469 ( optlc_net_489 ) ,
+ .p470 ( optlc_net_490 ) , .p471 ( optlc_net_491 ) ,
+ .p472 ( optlc_net_492 ) , .p473 ( optlc_net_493 ) ,
+ .p474 ( optlc_net_494 ) , .p475 ( optlc_net_495 ) ,
+ .p476 ( optlc_net_496 ) , .p477 ( optlc_net_497 ) ,
+ .p478 ( optlc_net_498 ) , .p479 ( optlc_net_499 ) ,
+ .p480 ( optlc_net_500 ) , .p481 ( optlc_net_501 ) ,
+ .p482 ( optlc_net_502 ) , .p483 ( optlc_net_503 ) ,
+ .p484 ( optlc_net_504 ) , .p485 ( optlc_net_505 ) ,
+ .p486 ( optlc_net_506 ) , .p487 ( optlc_net_507 ) ,
+ .p488 ( optlc_net_508 ) , .p489 ( optlc_net_509 ) ,
+ .p490 ( optlc_net_510 ) , .p491 ( optlc_net_511 ) ,
+ .p492 ( optlc_net_512 ) , .p493 ( optlc_net_513 ) ,
+ .p494 ( optlc_net_514 ) , .p495 ( optlc_net_515 ) ,
+ .p496 ( optlc_net_516 ) , .p497 ( optlc_net_517 ) ,
+ .p498 ( optlc_net_518 ) , .p499 ( optlc_net_519 ) ,
+ .p500 ( optlc_net_520 ) , .p501 ( optlc_net_521 ) ,
+ .p502 ( optlc_net_522 ) , .p503 ( optlc_net_523 ) ,
+ .p504 ( optlc_net_524 ) , .p505 ( optlc_net_525 ) ,
+ .p506 ( optlc_net_526 ) , .p507 ( optlc_net_527 ) ,
+ .p508 ( optlc_net_528 ) , .p509 ( optlc_net_529 ) ,
+ .p510 ( optlc_net_530 ) , .p511 ( optlc_net_531 ) ,
+ .p512 ( optlc_net_532 ) , .p513 ( optlc_net_533 ) ,
+ .p514 ( optlc_net_534 ) , .p515 ( optlc_net_535 ) ,
+ .p516 ( optlc_net_536 ) , .p517 ( optlc_net_537 ) ,
+ .p518 ( optlc_net_538 ) , .p519 ( optlc_net_539 ) ,
+ .p520 ( optlc_net_540 ) , .p521 ( optlc_net_541 ) ,
+ .p522 ( optlc_net_542 ) , .p523 ( optlc_net_543 ) ,
+ .p524 ( optlc_net_544 ) , .p525 ( optlc_net_545 ) ,
+ .p526 ( optlc_net_546 ) , .p527 ( optlc_net_547 ) ,
+ .p528 ( optlc_net_548 ) , .p529 ( optlc_net_549 ) ,
+ .p530 ( optlc_net_550 ) , .p531 ( optlc_net_551 ) ,
+ .p532 ( optlc_net_552 ) , .p533 ( optlc_net_553 ) ,
+ .p534 ( optlc_net_554 ) , .p535 ( optlc_net_555 ) ,
+ .p536 ( optlc_net_556 ) , .p537 ( optlc_net_557 ) ,
+ .p538 ( optlc_net_558 ) , .p539 ( optlc_net_559 ) ,
+ .p540 ( optlc_net_560 ) , .p541 ( optlc_net_561 ) ,
+ .p542 ( optlc_net_562 ) , .p543 ( optlc_net_563 ) ,
+ .p544 ( optlc_net_564 ) , .p545 ( optlc_net_565 ) ,
+ .p546 ( optlc_net_566 ) , .p547 ( optlc_net_567 ) ,
+ .p548 ( optlc_net_568 ) , .p549 ( optlc_net_569 ) ,
+ .p550 ( optlc_net_570 ) , .p551 ( optlc_net_571 ) ,
+ .p552 ( optlc_net_572 ) , .p553 ( optlc_net_573 ) ,
+ .p554 ( optlc_net_574 ) , .p555 ( optlc_net_575 ) ,
+ .p556 ( optlc_net_576 ) , .p557 ( optlc_net_577 ) ,
+ .p558 ( optlc_net_578 ) , .p559 ( optlc_net_579 ) ,
+ .p560 ( optlc_net_580 ) , .p561 ( optlc_net_581 ) ,
+ .p562 ( optlc_net_582 ) , .p563 ( optlc_net_583 ) ,
+ .p564 ( optlc_net_584 ) , .p565 ( optlc_net_585 ) ,
+ .p566 ( optlc_net_586 ) , .p567 ( optlc_net_587 ) ,
+ .p568 ( optlc_net_588 ) , .p569 ( optlc_net_589 ) ,
+ .p570 ( optlc_net_590 ) , .p571 ( optlc_net_591 ) ,
+ .p572 ( optlc_net_592 ) , .p573 ( optlc_net_593 ) ,
+ .p574 ( optlc_net_594 ) , .p575 ( optlc_net_595 ) ,
+ .p576 ( optlc_net_596 ) , .p577 ( optlc_net_597 ) ,
+ .p578 ( optlc_net_598 ) , .p579 ( optlc_net_599 ) ,
+ .p580 ( optlc_net_600 ) , .p581 ( optlc_net_601 ) ,
+ .p582 ( optlc_net_602 ) , .p583 ( optlc_net_603 ) ,
+ .p584 ( optlc_net_604 ) , .p585 ( optlc_net_605 ) ,
+ .p586 ( optlc_net_606 ) , .p587 ( optlc_net_607 ) ,
+ .p588 ( optlc_net_608 ) , .p589 ( optlc_net_609 ) ,
+ .p590 ( optlc_net_610 ) , .p591 ( optlc_net_611 ) ,
+ .p592 ( optlc_net_612 ) , .p593 ( optlc_net_613 ) ,
+ .p594 ( optlc_net_614 ) , .p595 ( optlc_net_615 ) ,
+ .p596 ( optlc_net_616 ) , .p597 ( optlc_net_617 ) ,
+ .p598 ( optlc_net_618 ) , .p599 ( optlc_net_619 ) ,
+ .p600 ( optlc_net_620 ) , .p601 ( optlc_net_621 ) ,
+ .p602 ( optlc_net_622 ) , .p603 ( optlc_net_623 ) ,
+ .p604 ( optlc_net_624 ) , .p605 ( optlc_net_625 ) ,
+ .p606 ( optlc_net_626 ) , .p607 ( optlc_net_627 ) ,
+ .p608 ( optlc_net_628 ) , .p609 ( optlc_net_629 ) ,
+ .p610 ( optlc_net_630 ) , .p611 ( optlc_net_631 ) ,
+ .p612 ( optlc_net_632 ) , .p613 ( optlc_net_633 ) ,
+ .p614 ( optlc_net_634 ) , .p615 ( optlc_net_635 ) ,
+ .p616 ( optlc_net_636 ) , .p617 ( optlc_net_637 ) ,
+ .p618 ( optlc_net_638 ) , .p619 ( optlc_net_639 ) ,
+ .p620 ( optlc_net_640 ) , .p621 ( optlc_net_641 ) ,
+ .p622 ( optlc_net_642 ) , .p623 ( optlc_net_643 ) ,
+ .p624 ( optlc_net_644 ) , .p625 ( optlc_net_645 ) ,
+ .p626 ( optlc_net_646 ) , .p627 ( optlc_net_647 ) ,
+ .p628 ( optlc_net_648 ) , .p629 ( optlc_net_649 ) ,
+ .p630 ( optlc_net_650 ) , .p631 ( optlc_net_651 ) ,
+ .p632 ( optlc_net_652 ) , .p633 ( optlc_net_653 ) ,
+ .p634 ( optlc_net_654 ) , .p635 ( optlc_net_655 ) ,
+ .p636 ( optlc_net_656 ) , .p637 ( optlc_net_657 ) ,
+ .p638 ( optlc_net_658 ) , .p639 ( optlc_net_659 ) ,
+ .p640 ( optlc_net_660 ) , .p641 ( optlc_net_661 ) ,
+ .p642 ( optlc_net_662 ) , .p643 ( optlc_net_663 ) ,
+ .p644 ( optlc_net_664 ) , .p645 ( optlc_net_665 ) ,
+ .p646 ( optlc_net_666 ) , .p647 ( optlc_net_667 ) ,
+ .p648 ( optlc_net_668 ) , .p649 ( optlc_net_669 ) ,
+ .p650 ( optlc_net_670 ) , .p651 ( optlc_net_671 ) ,
+ .p652 ( optlc_net_672 ) , .p653 ( optlc_net_673 ) ,
+ .p654 ( optlc_net_674 ) , .p655 ( optlc_net_675 ) ,
+ .p656 ( optlc_net_676 ) , .p657 ( optlc_net_677 ) ,
+ .p658 ( optlc_net_678 ) , .p659 ( optlc_net_679 ) ,
+ .p660 ( optlc_net_680 ) , .p661 ( optlc_net_681 ) ,
+ .p662 ( optlc_net_682 ) , .p663 ( optlc_net_683 ) ,
+ .p664 ( optlc_net_684 ) , .p665 ( optlc_net_685 ) ,
+ .p666 ( optlc_net_686 ) , .p667 ( optlc_net_687 ) ,
+ .p668 ( optlc_net_688 ) , .p669 ( optlc_net_689 ) ,
+ .p670 ( optlc_net_690 ) , .p671 ( optlc_net_691 ) ,
+ .p672 ( optlc_net_692 ) , .p673 ( optlc_net_693 ) ,
+ .p674 ( optlc_net_694 ) , .p675 ( optlc_net_695 ) ,
+ .p676 ( optlc_net_696 ) , .p677 ( optlc_net_697 ) ,
+ .p678 ( optlc_net_698 ) , .p679 ( optlc_net_699 ) ,
+ .p680 ( optlc_net_700 ) , .p681 ( optlc_net_701 ) ,
+ .p682 ( optlc_net_702 ) , .p683 ( optlc_net_703 ) ,
+ .p684 ( optlc_net_704 ) , .p685 ( optlc_net_705 ) ,
+ .p686 ( optlc_net_706 ) , .p687 ( optlc_net_707 ) ,
+ .p688 ( optlc_net_708 ) , .p689 ( optlc_net_709 ) ,
+ .p690 ( optlc_net_710 ) , .p691 ( optlc_net_711 ) ,
+ .p692 ( optlc_net_712 ) , .p693 ( optlc_net_713 ) ,
+ .p694 ( optlc_net_714 ) , .p695 ( optlc_net_715 ) ,
+ .p696 ( optlc_net_716 ) , .p697 ( optlc_net_717 ) ,
+ .p698 ( optlc_net_718 ) , .p699 ( optlc_net_719 ) ,
+ .p700 ( optlc_net_720 ) , .p701 ( optlc_net_721 ) ,
+ .p702 ( optlc_net_722 ) , .p703 ( optlc_net_723 ) ,
+ .p704 ( optlc_net_724 ) , .p705 ( optlc_net_725 ) ,
+ .p706 ( optlc_net_726 ) , .p707 ( optlc_net_727 ) ,
+ .p708 ( optlc_net_728 ) , .p709 ( optlc_net_729 ) ,
+ .p710 ( optlc_net_730 ) , .p711 ( optlc_net_731 ) ,
+ .p712 ( optlc_net_732 ) , .p713 ( optlc_net_733 ) ,
+ .p714 ( optlc_net_734 ) , .p715 ( optlc_net_735 ) ,
+ .p716 ( optlc_net_736 ) , .p717 ( optlc_net_737 ) ,
+ .p718 ( optlc_net_738 ) , .p719 ( optlc_net_739 ) ,
+ .p720 ( optlc_net_740 ) , .p721 ( optlc_net_741 ) ,
+ .p722 ( optlc_net_742 ) , .p723 ( optlc_net_743 ) ,
+ .p724 ( optlc_net_744 ) , .p725 ( optlc_net_745 ) ,
+ .p726 ( optlc_net_746 ) , .p727 ( optlc_net_747 ) ,
+ .p728 ( optlc_net_748 ) , .p729 ( optlc_net_749 ) ,
+ .p730 ( optlc_net_750 ) , .p731 ( optlc_net_751 ) ,
+ .p732 ( optlc_net_752 ) , .p733 ( optlc_net_753 ) ,
+ .p734 ( optlc_net_754 ) , .p735 ( optlc_net_755 ) ,
+ .p736 ( optlc_net_756 ) , .p737 ( optlc_net_757 ) ,
+ .p738 ( optlc_net_758 ) , .p739 ( optlc_net_759 ) ,
+ .p740 ( optlc_net_760 ) , .p741 ( optlc_net_761 ) ,
+ .p742 ( optlc_net_762 ) , .p743 ( optlc_net_763 ) ,
+ .p744 ( optlc_net_764 ) , .p745 ( optlc_net_765 ) ,
+ .p746 ( optlc_net_766 ) , .p747 ( optlc_net_767 ) ,
+ .p748 ( optlc_net_768 ) , .p749 ( optlc_net_769 ) ,
+ .p750 ( optlc_net_770 ) , .p751 ( optlc_net_771 ) ,
+ .p752 ( optlc_net_772 ) , .p753 ( optlc_net_773 ) ,
+ .p754 ( optlc_net_774 ) , .p755 ( optlc_net_775 ) ,
+ .p756 ( optlc_net_776 ) , .p757 ( optlc_net_777 ) ,
+ .p758 ( optlc_net_778 ) , .p759 ( optlc_net_779 ) ,
+ .p760 ( optlc_net_780 ) , .p761 ( optlc_net_781 ) ,
+ .p762 ( optlc_net_782 ) , .p763 ( optlc_net_783 ) ,
+ .p764 ( optlc_net_784 ) , .p765 ( optlc_net_785 ) ,
+ .p766 ( optlc_net_786 ) , .p767 ( optlc_net_787 ) ,
+ .p768 ( optlc_net_788 ) , .p769 ( optlc_net_789 ) ,
+ .p770 ( optlc_net_790 ) , .p771 ( optlc_net_791 ) ,
+ .p772 ( optlc_net_792 ) , .p773 ( optlc_net_793 ) ,
+ .p774 ( optlc_net_794 ) , .p775 ( optlc_net_795 ) ,
+ .p776 ( optlc_net_796 ) , .p777 ( optlc_net_797 ) ,
+ .p778 ( optlc_net_798 ) , .p779 ( optlc_net_799 ) ,
+ .p780 ( optlc_net_800 ) , .p781 ( optlc_net_801 ) ,
+ .p782 ( optlc_net_802 ) , .p783 ( optlc_net_803 ) ,
+ .p784 ( optlc_net_804 ) , .p785 ( optlc_net_805 ) ,
+ .p786 ( optlc_net_806 ) , .p787 ( optlc_net_807 ) ,
+ .p788 ( optlc_net_808 ) , .p789 ( optlc_net_809 ) ,
+ .p790 ( optlc_net_810 ) , .p791 ( optlc_net_811 ) ,
+ .p792 ( optlc_net_812 ) , .p793 ( optlc_net_813 ) ,
+ .p794 ( optlc_net_814 ) , .p795 ( optlc_net_815 ) ,
+ .p796 ( optlc_net_816 ) , .p797 ( optlc_net_817 ) ,
+ .p798 ( optlc_net_818 ) , .p799 ( optlc_net_819 ) ,
+ .p800 ( optlc_net_820 ) , .p801 ( optlc_net_821 ) ,
+ .p802 ( optlc_net_822 ) , .p803 ( optlc_net_823 ) ,
+ .p804 ( optlc_net_824 ) , .p805 ( optlc_net_825 ) ,
+ .p806 ( optlc_net_826 ) , .p807 ( optlc_net_827 ) ,
+ .p808 ( optlc_net_828 ) , .p809 ( optlc_net_829 ) ,
+ .p810 ( optlc_net_830 ) , .p811 ( optlc_net_831 ) ,
+ .p812 ( optlc_net_832 ) , .p813 ( optlc_net_833 ) ,
+ .p814 ( optlc_net_834 ) , .p815 ( optlc_net_835 ) ,
+ .p816 ( optlc_net_836 ) , .p817 ( optlc_net_837 ) ,
+ .p818 ( optlc_net_838 ) , .p819 ( optlc_net_839 ) ,
+ .p820 ( optlc_net_840 ) , .p821 ( optlc_net_841 ) ,
+ .p822 ( optlc_net_842 ) , .p823 ( optlc_net_843 ) ,
+ .p824 ( optlc_net_844 ) , .p825 ( optlc_net_845 ) ,
+ .p826 ( optlc_net_846 ) , .p827 ( optlc_net_847 ) ,
+ .p828 ( optlc_net_848 ) , .p829 ( optlc_net_849 ) ,
+ .p830 ( optlc_net_850 ) , .p831 ( optlc_net_851 ) ,
+ .p832 ( optlc_net_852 ) , .p833 ( optlc_net_853 ) ,
+ .p834 ( optlc_net_854 ) , .p835 ( optlc_net_855 ) ,
+ .p836 ( optlc_net_856 ) , .p837 ( optlc_net_857 ) ,
+ .p838 ( optlc_net_858 ) , .p839 ( optlc_net_859 ) ,
+ .p840 ( optlc_net_860 ) , .p841 ( optlc_net_861 ) ,
+ .p842 ( optlc_net_862 ) , .p843 ( optlc_net_863 ) ,
+ .p844 ( optlc_net_864 ) , .p845 ( optlc_net_865 ) ,
+ .p846 ( optlc_net_866 ) , .p847 ( optlc_net_867 ) ,
+ .p848 ( optlc_net_868 ) , .p849 ( optlc_net_869 ) ,
+ .p850 ( optlc_net_870 ) , .p851 ( optlc_net_871 ) ,
+ .p852 ( optlc_net_872 ) , .p853 ( optlc_net_873 ) ,
+ .p854 ( optlc_net_874 ) , .p855 ( optlc_net_875 ) ,
+ .p856 ( optlc_net_876 ) , .p857 ( optlc_net_877 ) ,
+ .p858 ( optlc_net_878 ) , .p859 ( optlc_net_879 ) ,
+ .p860 ( optlc_net_880 ) , .p861 ( optlc_net_881 ) ,
+ .p862 ( optlc_net_882 ) , .p863 ( optlc_net_883 ) ,
+ .p864 ( optlc_net_884 ) , .p865 ( optlc_net_885 ) ,
+ .p866 ( optlc_net_886 ) , .p867 ( optlc_net_887 ) ,
+ .p868 ( optlc_net_888 ) , .p869 ( optlc_net_889 ) ,
+ .p870 ( optlc_net_890 ) , .p871 ( optlc_net_891 ) ,
+ .p872 ( optlc_net_892 ) , .p873 ( optlc_net_893 ) ,
+ .p874 ( optlc_net_894 ) , .p875 ( optlc_net_895 ) ,
+ .p876 ( optlc_net_896 ) , .p877 ( optlc_net_897 ) ,
+ .p878 ( optlc_net_898 ) , .p879 ( optlc_net_899 ) ,
+ .p880 ( optlc_net_900 ) , .p881 ( optlc_net_901 ) ,
+ .p882 ( optlc_net_902 ) , .p883 ( optlc_net_903 ) ,
+ .p884 ( optlc_net_904 ) , .p885 ( optlc_net_905 ) ,
+ .p886 ( optlc_net_906 ) , .p887 ( optlc_net_907 ) ,
+ .p888 ( optlc_net_908 ) , .p889 ( optlc_net_909 ) ,
+ .p890 ( optlc_net_910 ) , .p891 ( optlc_net_911 ) ,
+ .p892 ( optlc_net_912 ) , .p893 ( optlc_net_913 ) ,
+ .p894 ( optlc_net_914 ) , .p895 ( optlc_net_915 ) ,
+ .p896 ( optlc_net_916 ) , .p897 ( optlc_net_917 ) ,
+ .p898 ( optlc_net_918 ) , .p899 ( optlc_net_919 ) ,
+ .p900 ( optlc_net_920 ) , .p901 ( optlc_net_921 ) ,
+ .p902 ( optlc_net_922 ) , .p903 ( optlc_net_923 ) ,
+ .p904 ( optlc_net_924 ) , .p905 ( optlc_net_925 ) ,
+ .p906 ( optlc_net_926 ) , .p907 ( optlc_net_927 ) ,
+ .p908 ( optlc_net_928 ) , .p909 ( optlc_net_929 ) ,
+ .p910 ( optlc_net_930 ) , .p911 ( optlc_net_931 ) ,
+ .p912 ( optlc_net_932 ) , .p913 ( optlc_net_933 ) ,
+ .p914 ( optlc_net_934 ) , .p915 ( optlc_net_935 ) ,
+ .p916 ( optlc_net_936 ) , .p917 ( optlc_net_937 ) ,
+ .p918 ( optlc_net_938 ) , .p919 ( optlc_net_939 ) ,
+ .p920 ( optlc_net_940 ) , .p921 ( optlc_net_941 ) ,
+ .p922 ( optlc_net_942 ) , .p923 ( optlc_net_943 ) ,
+ .p924 ( optlc_net_944 ) , .p925 ( optlc_net_945 ) ,
+ .p926 ( optlc_net_946 ) , .p927 ( optlc_net_947 ) ,
+ .p928 ( optlc_net_948 ) , .p929 ( optlc_net_949 ) ,
+ .p930 ( optlc_net_950 ) , .p931 ( optlc_net_951 ) ,
+ .p932 ( optlc_net_952 ) , .p933 ( optlc_net_953 ) ,
+ .p934 ( optlc_net_954 ) , .p935 ( optlc_net_955 ) ,
+ .p936 ( optlc_net_956 ) , .p937 ( optlc_net_957 ) ,
+ .p938 ( optlc_net_958 ) , .p939 ( optlc_net_959 ) ,
+ .p940 ( optlc_net_960 ) , .p941 ( optlc_net_961 ) ,
+ .p942 ( optlc_net_962 ) , .p943 ( optlc_net_963 ) ,
+ .p944 ( optlc_net_964 ) , .p945 ( optlc_net_965 ) ,
+ .p946 ( optlc_net_966 ) , .p947 ( optlc_net_967 ) ,
+ .p948 ( optlc_net_968 ) , .p949 ( optlc_net_969 ) ,
+ .p950 ( optlc_net_970 ) , .p951 ( optlc_net_971 ) ,
+ .p952 ( optlc_net_972 ) , .p953 ( optlc_net_973 ) ,
+ .p954 ( optlc_net_974 ) , .p955 ( optlc_net_975 ) ,
+ .p956 ( optlc_net_976 ) , .p957 ( optlc_net_977 ) ,
+ .p958 ( optlc_net_978 ) , .p959 ( optlc_net_979 ) ,
+ .p960 ( optlc_net_980 ) , .p961 ( optlc_net_981 ) ,
+ .p962 ( optlc_net_982 ) , .p963 ( optlc_net_983 ) ,
+ .p964 ( optlc_net_984 ) , .p965 ( optlc_net_985 ) ,
+ .p966 ( optlc_net_986 ) , .p967 ( optlc_net_987 ) ,
+ .p968 ( optlc_net_988 ) , .p969 ( optlc_net_989 ) ,
+ .p970 ( optlc_net_990 ) , .p971 ( optlc_net_991 ) ,
+ .p972 ( optlc_net_992 ) , .p973 ( optlc_net_993 ) ,
+ .p974 ( optlc_net_994 ) , .p975 ( optlc_net_995 ) ,
+ .p976 ( optlc_net_996 ) , .p977 ( optlc_net_997 ) ,
+ .p978 ( optlc_net_998 ) , .p979 ( optlc_net_999 ) ,
+ .p980 ( optlc_net_1000 ) , .p981 ( optlc_net_1001 ) ,
+ .p982 ( optlc_net_1002 ) , .p983 ( optlc_net_1003 ) ,
+ .p984 ( optlc_net_1004 ) , .p985 ( optlc_net_1005 ) ,
+ .p986 ( optlc_net_1006 ) , .p987 ( optlc_net_1007 ) ,
+ .p988 ( optlc_net_1008 ) , .p989 ( optlc_net_1009 ) ,
+ .p990 ( optlc_net_1010 ) , .p991 ( optlc_net_1011 ) ,
+ .p992 ( optlc_net_1012 ) , .p993 ( optlc_net_1013 ) ,
+ .p994 ( optlc_net_1014 ) , .p995 ( optlc_net_1015 ) ,
+ .p996 ( optlc_net_1016 ) , .p997 ( optlc_net_1017 ) ,
+ .p998 ( optlc_net_1018 ) , .p999 ( optlc_net_1019 ) ,
+ .p1000 ( optlc_net_1020 ) , .p1001 ( optlc_net_1021 ) ,
+ .p1002 ( optlc_net_1022 ) , .p1003 ( optlc_net_1023 ) ,
+ .p1004 ( optlc_net_1024 ) , .p1005 ( optlc_net_1025 ) ,
+ .p1006 ( optlc_net_1026 ) , .p1007 ( optlc_net_1027 ) ,
+ .p1008 ( optlc_net_1028 ) , .p1009 ( optlc_net_1029 ) ,
+ .p1010 ( optlc_net_1030 ) , .p1011 ( optlc_net_1031 ) ,
+ .p1012 ( optlc_net_1032 ) , .p1013 ( optlc_net_1033 ) ,
+ .p1014 ( optlc_net_1034 ) , .p1015 ( optlc_net_1035 ) ,
+ .p1016 ( optlc_net_1036 ) , .p1017 ( optlc_net_1037 ) ,
+ .p1018 ( optlc_net_1038 ) , .p1019 ( optlc_net_1039 ) ,
+ .p1020 ( optlc_net_1040 ) , .p1021 ( optlc_net_1041 ) ,
+ .p1022 ( optlc_net_1042 ) , .p1023 ( optlc_net_1043 ) ,
+ .p1024 ( optlc_net_1044 ) , .p1025 ( optlc_net_1045 ) ,
+ .p1026 ( optlc_net_1046 ) , .p1027 ( optlc_net_1047 ) ,
+ .p1028 ( optlc_net_1048 ) , .p1029 ( optlc_net_1049 ) ,
+ .p1030 ( optlc_net_1050 ) , .p1031 ( optlc_net_1051 ) ,
+ .p1032 ( optlc_net_1052 ) , .p1033 ( optlc_net_1053 ) ,
+ .p1034 ( optlc_net_1054 ) , .p1035 ( optlc_net_1055 ) ,
+ .p1036 ( optlc_net_1056 ) , .p1037 ( optlc_net_1057 ) ,
+ .p1038 ( optlc_net_1058 ) , .p1039 ( optlc_net_1059 ) ,
+ .p1040 ( optlc_net_1060 ) , .p1041 ( optlc_net_1061 ) ,
+ .p1042 ( optlc_net_1062 ) , .p1043 ( optlc_net_1063 ) ,
+ .p1044 ( optlc_net_1064 ) , .p1045 ( optlc_net_1065 ) ,
+ .p1046 ( optlc_net_1066 ) , .p1047 ( optlc_net_1067 ) ,
+ .p1048 ( optlc_net_1068 ) , .p1049 ( optlc_net_1069 ) ,
+ .p1050 ( optlc_net_1070 ) , .p1051 ( optlc_net_1071 ) ,
+ .p1052 ( optlc_net_1072 ) , .p1053 ( optlc_net_1073 ) ,
+ .p1054 ( optlc_net_1074 ) , .p1055 ( optlc_net_1075 ) ,
+ .p1056 ( optlc_net_1076 ) , .p1057 ( optlc_net_1077 ) ,
+ .p1058 ( optlc_net_1078 ) , .p1059 ( optlc_net_1079 ) ,
+ .p1060 ( optlc_net_1080 ) , .p1061 ( optlc_net_1081 ) ,
+ .p1062 ( optlc_net_1082 ) , .p1063 ( optlc_net_1083 ) ,
+ .p1064 ( optlc_net_1084 ) , .p1065 ( optlc_net_1085 ) ,
+ .p1066 ( optlc_net_1086 ) , .p1067 ( optlc_net_1087 ) ,
+ .p1068 ( optlc_net_1088 ) , .p1069 ( optlc_net_1089 ) ,
+ .p1070 ( optlc_net_1090 ) , .p1071 ( optlc_net_1091 ) ,
+ .p1072 ( optlc_net_1092 ) , .p1073 ( optlc_net_1093 ) ,
+ .p1074 ( optlc_net_1094 ) , .p1075 ( optlc_net_1095 ) ,
+ .p1076 ( optlc_net_1096 ) , .p1077 ( optlc_net_1097 ) ,
+ .p1078 ( optlc_net_1098 ) , .p1079 ( optlc_net_1099 ) ,
+ .p1080 ( optlc_net_1100 ) , .p1081 ( optlc_net_1101 ) ,
+ .p1082 ( optlc_net_1102 ) , .p1083 ( optlc_net_1103 ) ,
+ .p1084 ( optlc_net_1104 ) , .p1085 ( optlc_net_1105 ) ,
+ .p1086 ( optlc_net_1106 ) , .p1087 ( optlc_net_1107 ) ,
+ .p1088 ( optlc_net_1108 ) , .p1089 ( optlc_net_1109 ) ,
+ .p1090 ( optlc_net_1110 ) , .p1091 ( optlc_net_1111 ) ,
+ .p1092 ( optlc_net_1112 ) , .p1093 ( optlc_net_1113 ) ,
+ .p1094 ( optlc_net_1114 ) , .p1095 ( optlc_net_1115 ) ,
+ .p1096 ( optlc_net_1116 ) , .p1097 ( optlc_net_1117 ) ,
+ .p1098 ( optlc_net_1118 ) , .p1099 ( optlc_net_1119 ) ,
+ .p1100 ( optlc_net_1120 ) , .p1101 ( optlc_net_1121 ) ,
+ .p1102 ( optlc_net_1122 ) , .p1103 ( optlc_net_1123 ) ,
+ .p1104 ( optlc_net_1124 ) , .p1105 ( optlc_net_1125 ) ,
+ .p1106 ( optlc_net_1126 ) , .p1107 ( optlc_net_1127 ) ,
+ .p1108 ( optlc_net_1128 ) , .p1109 ( optlc_net_1129 ) ,
+ .p1110 ( optlc_net_1130 ) , .p1111 ( optlc_net_1131 ) ,
+ .p1112 ( optlc_net_1132 ) , .p1113 ( optlc_net_1133 ) ,
+ .p1114 ( optlc_net_1134 ) , .p1115 ( optlc_net_1135 ) ,
+ .p1116 ( optlc_net_1136 ) , .p1117 ( optlc_net_1137 ) ,
+ .p1118 ( optlc_net_1138 ) , .p1119 ( optlc_net_1139 ) ,
+ .p1120 ( optlc_net_1140 ) , .p1121 ( optlc_net_1141 ) ,
+ .p1122 ( optlc_net_1142 ) , .p1123 ( optlc_net_1143 ) ,
+ .p1124 ( optlc_net_1144 ) , .p1125 ( optlc_net_1145 ) ,
+ .p1126 ( optlc_net_1146 ) , .p1127 ( optlc_net_1147 ) ,
+ .p1128 ( optlc_net_1148 ) , .p1129 ( optlc_net_1149 ) ,
+ .p1130 ( optlc_net_1150 ) , .p1131 ( optlc_net_1151 ) ,
+ .p1132 ( optlc_net_1152 ) , .p1133 ( optlc_net_1153 ) ,
+ .p1134 ( optlc_net_1154 ) , .p1135 ( optlc_net_1155 ) ,
+ .p1136 ( optlc_net_1156 ) , .p1137 ( optlc_net_1157 ) ,
+ .p1138 ( optlc_net_1158 ) , .p1139 ( optlc_net_1159 ) ,
+ .p1140 ( optlc_net_1160 ) , .p1141 ( optlc_net_1161 ) ,
+ .p1142 ( optlc_net_1162 ) , .p1143 ( optlc_net_1163 ) ,
+ .p1144 ( optlc_net_1164 ) , .p1145 ( optlc_net_1165 ) ,
+ .p1146 ( optlc_net_1166 ) , .p1147 ( optlc_net_1167 ) ,
+ .p1148 ( optlc_net_1168 ) , .p1149 ( optlc_net_1169 ) ,
+ .p1150 ( optlc_net_1170 ) , .p1151 ( optlc_net_1171 ) ,
+ .p1152 ( optlc_net_1172 ) , .p1153 ( optlc_net_1173 ) ,
+ .p1154 ( optlc_net_1174 ) , .p1155 ( optlc_net_1175 ) ,
+ .p1156 ( optlc_net_1176 ) , .p1157 ( optlc_net_1177 ) ,
+ .p1158 ( optlc_net_1178 ) , .p1159 ( optlc_net_1179 ) ,
+ .p1160 ( optlc_net_1180 ) , .p1161 ( optlc_net_1181 ) ,
+ .p1162 ( optlc_net_1182 ) , .p1163 ( optlc_net_1183 ) ,
+ .p1164 ( optlc_net_1184 ) , .p1165 ( optlc_net_1185 ) ,
+ .p1166 ( optlc_net_1186 ) , .p1167 ( optlc_net_1187 ) ,
+ .p1168 ( optlc_net_1188 ) , .p1169 ( optlc_net_1189 ) ,
+ .p1170 ( optlc_net_1190 ) , .p1171 ( optlc_net_1191 ) ,
+ .p1172 ( optlc_net_1192 ) , .p1173 ( optlc_net_1193 ) ,
+ .p1174 ( optlc_net_1194 ) , .p1175 ( optlc_net_1195 ) ,
+ .p1176 ( optlc_net_1196 ) , .p1177 ( optlc_net_1197 ) ,
+ .p1178 ( optlc_net_1198 ) , .p1179 ( optlc_net_1199 ) ,
+ .p1180 ( optlc_net_1200 ) , .p1181 ( optlc_net_1201 ) ,
+ .p1182 ( optlc_net_1202 ) , .p1183 ( optlc_net_1203 ) ,
+ .p1184 ( optlc_net_1204 ) , .p1185 ( optlc_net_1205 ) ,
+ .p1186 ( optlc_net_1206 ) , .p1187 ( optlc_net_1207 ) ,
+ .p1188 ( optlc_net_1208 ) , .p1189 ( optlc_net_1209 ) ,
+ .p1190 ( optlc_net_1210 ) , .p1191 ( optlc_net_1211 ) ,
+ .p1192 ( optlc_net_1212 ) , .p1193 ( optlc_net_1213 ) ,
+ .p1194 ( optlc_net_1214 ) , .p1195 ( optlc_net_1215 ) ,
+ .p1196 ( optlc_net_1216 ) , .p1197 ( optlc_net_1217 ) ,
+ .p1198 ( optlc_net_1218 ) , .p1199 ( optlc_net_1219 ) ,
+ .p1200 ( optlc_net_1220 ) , .p1201 ( optlc_net_1221 ) ,
+ .p1202 ( optlc_net_1222 ) , .p1203 ( optlc_net_1223 ) ,
+ .p1204 ( optlc_net_1224 ) , .p1205 ( optlc_net_1225 ) ,
+ .p1206 ( optlc_net_1226 ) , .p1207 ( optlc_net_1227 ) ,
+ .p1208 ( optlc_net_1228 ) , .p1209 ( optlc_net_1229 ) ,
+ .p1210 ( optlc_net_1230 ) , .p1211 ( optlc_net_1231 ) ,
+ .p1212 ( optlc_net_1232 ) , .p1213 ( optlc_net_1233 ) ,
+ .p1214 ( optlc_net_1234 ) , .p1215 ( optlc_net_1235 ) ,
+ .p1216 ( optlc_net_1236 ) , .p1217 ( optlc_net_1237 ) ,
+ .p1218 ( optlc_net_1238 ) , .p1219 ( optlc_net_1239 ) ,
+ .p1220 ( optlc_net_1240 ) , .p1221 ( optlc_net_1241 ) ,
+ .p1222 ( optlc_net_1242 ) , .p1223 ( optlc_net_1243 ) ,
+ .p1224 ( optlc_net_1244 ) , .p1225 ( optlc_net_1245 ) ,
+ .p1226 ( optlc_net_1246 ) , .p1227 ( optlc_net_1247 ) ,
+ .p1228 ( optlc_net_1248 ) , .p1229 ( optlc_net_1249 ) ,
+ .p1230 ( optlc_net_1250 ) , .p1231 ( optlc_net_1251 ) ,
+ .p1232 ( optlc_net_1252 ) , .p1233 ( optlc_net_1253 ) ,
+ .p1234 ( optlc_net_1254 ) , .p1235 ( optlc_net_1255 ) ,
+ .p1236 ( optlc_net_1256 ) , .p1237 ( optlc_net_1257 ) ,
+ .p1238 ( optlc_net_1258 ) , .p1239 ( optlc_net_1259 ) ,
+ .p1240 ( optlc_net_1260 ) , .p1241 ( optlc_net_1261 ) ,
+ .p1242 ( optlc_net_1262 ) , .p1243 ( optlc_net_1263 ) ,
+ .p1244 ( optlc_net_1264 ) , .p1245 ( optlc_net_1265 ) ,
+ .p1246 ( optlc_net_1266 ) , .p1247 ( optlc_net_1267 ) ,
+ .p1248 ( optlc_net_1268 ) , .p1249 ( optlc_net_1269 ) ,
+ .p1250 ( optlc_net_1270 ) , .p1251 ( optlc_net_1271 ) ,
+ .p1252 ( optlc_net_1272 ) , .p1253 ( optlc_net_1273 ) ,
+ .p1254 ( optlc_net_1274 ) , .p1255 ( optlc_net_1275 ) ,
+ .p1256 ( optlc_net_1276 ) , .p1257 ( optlc_net_1277 ) ,
+ .p1258 ( optlc_net_1278 ) , .p1259 ( optlc_net_1279 ) ,
+ .p1260 ( optlc_net_1280 ) , .p1261 ( optlc_net_1281 ) ,
+ .p1262 ( optlc_net_1282 ) , .p1263 ( optlc_net_1283 ) ,
+ .p1264 ( optlc_net_1284 ) , .p1265 ( optlc_net_1285 ) ,
+ .p1266 ( optlc_net_1286 ) , .p1267 ( optlc_net_1287 ) ,
+ .p1268 ( optlc_net_1288 ) , .p1269 ( optlc_net_1289 ) ,
+ .p1270 ( optlc_net_1290 ) , .p1271 ( optlc_net_1291 ) ,
+ .p1272 ( optlc_net_1292 ) , .p1273 ( optlc_net_1293 ) ,
+ .p1274 ( optlc_net_1294 ) , .p1275 ( optlc_net_1295 ) ,
+ .p1276 ( optlc_net_1296 ) , .p1277 ( optlc_net_1297 ) ,
+ .p1278 ( optlc_net_1298 ) , .p1279 ( optlc_net_1299 ) ,
+ .p1280 ( optlc_net_1300 ) , .p1281 ( optlc_net_1301 ) ,
+ .p1282 ( optlc_net_1302 ) , .p1283 ( optlc_net_1303 ) ,
+ .p1284 ( optlc_net_1304 ) , .p1285 ( optlc_net_1305 ) ,
+ .p1286 ( optlc_net_1306 ) , .p1287 ( optlc_net_1307 ) ,
+ .p1288 ( optlc_net_1308 ) , .p1289 ( optlc_net_1309 ) ,
+ .p1290 ( optlc_net_1310 ) , .p1291 ( optlc_net_1311 ) ,
+ .p1292 ( optlc_net_1312 ) , .p1293 ( optlc_net_1313 ) ,
+ .p1294 ( optlc_net_1314 ) , .p1295 ( optlc_net_1315 ) ,
+ .p1296 ( optlc_net_1316 ) , .p1297 ( optlc_net_1317 ) ,
+ .p1298 ( optlc_net_1318 ) , .p1299 ( optlc_net_1319 ) ,
+ .p1300 ( optlc_net_1320 ) , .p1301 ( optlc_net_1321 ) ,
+ .p1302 ( optlc_net_1322 ) , .p1303 ( optlc_net_1323 ) ,
+ .p1304 ( optlc_net_1324 ) , .p1305 ( optlc_net_1325 ) ,
+ .p1306 ( optlc_net_1326 ) , .p1307 ( optlc_net_1327 ) ,
+ .p1308 ( optlc_net_1328 ) , .p1309 ( optlc_net_1329 ) ,
+ .p1310 ( optlc_net_1330 ) , .p1311 ( optlc_net_1331 ) ,
+ .p1312 ( optlc_net_1332 ) , .p1313 ( optlc_net_1333 ) ,
+ .p1314 ( optlc_net_1334 ) , .p1315 ( optlc_net_1335 ) ,
+ .p1316 ( optlc_net_1336 ) , .p1317 ( optlc_net_1337 ) ,
+ .p1318 ( optlc_net_1338 ) , .p1319 ( optlc_net_1339 ) ,
+ .p1320 ( optlc_net_1340 ) , .p1321 ( optlc_net_1341 ) ,
+ .p1322 ( optlc_net_1342 ) , .p1323 ( optlc_net_1343 ) ,
+ .p1324 ( optlc_net_1344 ) , .p1325 ( optlc_net_1345 ) ,
+ .p1326 ( optlc_net_1346 ) , .p1327 ( optlc_net_1347 ) ,
+ .p1328 ( optlc_net_1348 ) , .p1329 ( optlc_net_1349 ) ,
+ .p1330 ( optlc_net_1350 ) , .p1331 ( optlc_net_1351 ) ,
+ .p1332 ( optlc_net_1352 ) , .p1333 ( optlc_net_1353 ) ,
+ .p1334 ( optlc_net_1354 ) , .p1335 ( optlc_net_1355 ) ,
+ .p1336 ( optlc_net_1356 ) , .p1337 ( optlc_net_1357 ) ,
+ .p1338 ( optlc_net_1358 ) , .p1339 ( optlc_net_1359 ) ,
+ .p1340 ( optlc_net_1360 ) , .p1341 ( optlc_net_1361 ) ,
+ .p1342 ( optlc_net_1362 ) , .p1343 ( optlc_net_1363 ) ,
+ .p1344 ( optlc_net_1364 ) , .p1345 ( optlc_net_1365 ) ,
+ .p1346 ( optlc_net_1366 ) , .p1347 ( optlc_net_1367 ) ,
+ .p1348 ( optlc_net_1368 ) , .p1349 ( optlc_net_1369 ) ,
+ .p1350 ( optlc_net_1370 ) , .p1351 ( optlc_net_1371 ) ,
+ .p1352 ( optlc_net_1372 ) , .p1353 ( optlc_net_1373 ) ,
+ .p1354 ( optlc_net_1374 ) , .p1355 ( optlc_net_1375 ) ,
+ .p1356 ( optlc_net_1376 ) , .p1357 ( optlc_net_1377 ) ,
+ .p1358 ( optlc_net_1378 ) , .p1359 ( optlc_net_1379 ) ,
+ .p1360 ( optlc_net_1380 ) , .p1361 ( optlc_net_1381 ) ,
+ .p1362 ( optlc_net_1382 ) , .p1363 ( optlc_net_1383 ) ,
+ .p1364 ( optlc_net_1384 ) , .p1365 ( optlc_net_1385 ) ,
+ .p1366 ( optlc_net_1386 ) , .p1367 ( optlc_net_1387 ) ,
+ .p1368 ( optlc_net_1388 ) , .p1369 ( optlc_net_1389 ) ,
+ .p1370 ( optlc_net_1390 ) , .p1371 ( optlc_net_1391 ) ,
+ .p1372 ( optlc_net_1392 ) , .p1373 ( optlc_net_1393 ) ,
+ .p1374 ( optlc_net_1394 ) , .p1375 ( optlc_net_1395 ) ,
+ .p1376 ( optlc_net_1396 ) , .p1377 ( optlc_net_1397 ) ,
+ .p1378 ( optlc_net_1398 ) , .p1379 ( optlc_net_1399 ) ,
+ .p1380 ( optlc_net_1400 ) , .p1381 ( optlc_net_1401 ) ,
+ .p1382 ( optlc_net_1402 ) , .p1383 ( optlc_net_1403 ) ,
+ .p1384 ( optlc_net_1404 ) , .p1385 ( optlc_net_1405 ) ,
+ .p1386 ( optlc_net_1406 ) , .p1387 ( optlc_net_1407 ) ,
+ .p1388 ( optlc_net_1408 ) , .p1389 ( optlc_net_1409 ) ,
+ .p1390 ( optlc_net_1410 ) , .p1391 ( optlc_net_1411 ) ,
+ .p1392 ( optlc_net_1412 ) , .p1393 ( optlc_net_1413 ) ,
+ .p1394 ( optlc_net_1414 ) , .p1395 ( optlc_net_1415 ) ,
+ .p1396 ( optlc_net_1416 ) , .p1397 ( optlc_net_1417 ) ,
+ .p1398 ( optlc_net_1418 ) , .p1399 ( optlc_net_1419 ) ,
+ .p1400 ( optlc_net_1420 ) , .p1401 ( optlc_net_1421 ) ,
+ .p1402 ( optlc_net_1422 ) , .p1403 ( optlc_net_1423 ) ,
+ .p1404 ( optlc_net_1424 ) , .p1405 ( optlc_net_1425 ) ,
+ .p1406 ( optlc_net_1426 ) , .p1407 ( optlc_net_1427 ) ,
+ .p1408 ( optlc_net_1428 ) , .p1409 ( optlc_net_1429 ) ,
+ .p1410 ( optlc_net_1430 ) , .p1411 ( optlc_net_1431 ) ,
+ .p1412 ( optlc_net_1432 ) , .p1413 ( optlc_net_1433 ) ,
+ .p1414 ( optlc_net_1434 ) , .p1415 ( optlc_net_1435 ) ,
+ .p1416 ( optlc_net_1436 ) , .p1417 ( optlc_net_1437 ) ,
+ .p1418 ( optlc_net_1438 ) , .p1419 ( optlc_net_1439 ) ,
+ .p1420 ( optlc_net_1440 ) , .p1421 ( optlc_net_1441 ) ,
+ .p1422 ( optlc_net_1442 ) , .p1423 ( optlc_net_1443 ) ,
+ .p1424 ( optlc_net_1444 ) , .p1425 ( optlc_net_1445 ) ,
+ .p1426 ( optlc_net_1446 ) , .p1427 ( optlc_net_1447 ) ,
+ .p1428 ( optlc_net_1448 ) , .p1429 ( optlc_net_1449 ) ,
+ .p1430 ( optlc_net_1450 ) , .p1431 ( optlc_net_1451 ) ,
+ .p1432 ( optlc_net_1452 ) , .p1433 ( optlc_net_1453 ) ,
+ .p1434 ( optlc_net_1454 ) , .p1435 ( optlc_net_1455 ) ,
+ .p1436 ( optlc_net_1456 ) , .p1437 ( optlc_net_1457 ) ,
+ .p1438 ( optlc_net_1458 ) , .p1439 ( optlc_net_1459 ) ,
+ .p1440 ( optlc_net_1460 ) , .p1441 ( optlc_net_1461 ) ,
+ .p1442 ( optlc_net_1462 ) , .p1443 ( optlc_net_1463 ) ,
+ .p1444 ( optlc_net_1464 ) , .p1445 ( optlc_net_1465 ) ,
+ .p1446 ( optlc_net_1466 ) , .p1447 ( optlc_net_1467 ) ,
+ .p1448 ( optlc_net_1468 ) , .p1449 ( optlc_net_1469 ) ,
+ .p1450 ( optlc_net_1470 ) , .p1451 ( optlc_net_1471 ) ,
+ .p1452 ( optlc_net_1472 ) , .p1453 ( optlc_net_1473 ) ,
+ .p1454 ( optlc_net_1474 ) , .p1455 ( optlc_net_1475 ) ,
+ .p1456 ( optlc_net_1476 ) , .p1457 ( optlc_net_1477 ) ,
+ .p1458 ( optlc_net_1478 ) , .p1459 ( optlc_net_1479 ) ,
+ .p1460 ( optlc_net_1480 ) , .p1461 ( optlc_net_1481 ) ,
+ .p1462 ( optlc_net_1482 ) , .p1463 ( optlc_net_1483 ) ,
+ .p1464 ( optlc_net_1484 ) , .p1465 ( optlc_net_1485 ) ,
+ .p1466 ( optlc_net_1486 ) , .p1467 ( optlc_net_1487 ) ,
+ .p1468 ( optlc_net_1488 ) , .p1469 ( optlc_net_1489 ) ,
+ .p1470 ( optlc_net_1490 ) , .p1471 ( optlc_net_1491 ) ,
+ .p1472 ( optlc_net_1492 ) , .p1473 ( optlc_net_1493 ) ,
+ .p1474 ( optlc_net_1494 ) , .p1475 ( optlc_net_1495 ) ,
+ .p1476 ( optlc_net_1496 ) , .p1477 ( optlc_net_1497 ) ,
+ .p1478 ( optlc_net_1498 ) , .p1479 ( optlc_net_1499 ) ,
+ .p1480 ( optlc_net_1500 ) , .p1481 ( optlc_net_1501 ) ,
+ .p1482 ( optlc_net_1502 ) , .p1483 ( optlc_net_1503 ) ,
+ .p1484 ( optlc_net_1504 ) , .p1485 ( optlc_net_1505 ) ,
+ .p1486 ( optlc_net_1506 ) , .p1487 ( optlc_net_1507 ) ,
+ .p1488 ( optlc_net_1508 ) , .p1489 ( optlc_net_1509 ) ,
+ .p1490 ( optlc_net_1510 ) , .p1491 ( optlc_net_1511 ) ,
+ .p1492 ( optlc_net_1512 ) , .p1493 ( optlc_net_1513 ) ,
+ .p1494 ( optlc_net_1514 ) , .p1495 ( optlc_net_1515 ) ,
+ .p1496 ( optlc_net_1516 ) , .p1497 ( optlc_net_1517 ) ,
+ .p1498 ( optlc_net_1518 ) , .p1499 ( optlc_net_1519 ) ,
+ .p1500 ( optlc_net_1520 ) , .p1501 ( optlc_net_1521 ) ,
+ .p1502 ( optlc_net_1522 ) , .p1503 ( optlc_net_1523 ) ,
+ .p1504 ( optlc_net_1524 ) , .p1505 ( optlc_net_1525 ) ,
+ .p1506 ( optlc_net_1526 ) , .p1507 ( optlc_net_1527 ) ,
+ .p1508 ( optlc_net_1528 ) , .p1509 ( optlc_net_1529 ) ,
+ .p1510 ( optlc_net_1530 ) , .p1511 ( optlc_net_1531 ) ,
+ .p1512 ( optlc_net_1532 ) , .p1513 ( optlc_net_1533 ) ,
+ .p1514 ( optlc_net_1534 ) , .p1515 ( optlc_net_1535 ) ,
+ .p1516 ( optlc_net_1536 ) , .p1517 ( optlc_net_1537 ) ,
+ .p1518 ( optlc_net_1538 ) , .p1519 ( optlc_net_1539 ) ,
+ .p1520 ( optlc_net_1540 ) , .p1521 ( optlc_net_1541 ) ,
+ .p1522 ( optlc_net_1542 ) , .p1523 ( optlc_net_1543 ) ,
+ .p1524 ( optlc_net_1544 ) , .p1525 ( optlc_net_1545 ) ,
+ .p1526 ( optlc_net_1546 ) , .p1527 ( optlc_net_1547 ) ,
+ .p1528 ( optlc_net_1548 ) , .p1529 ( optlc_net_1549 ) ,
+ .p1530 ( optlc_net_1550 ) , .p1531 ( optlc_net_1551 ) ,
+ .p1532 ( optlc_net_1552 ) , .p1533 ( optlc_net_1553 ) ,
+ .p1534 ( optlc_net_1554 ) , .p1535 ( optlc_net_1555 ) ,
+ .p1536 ( optlc_net_1556 ) , .p1537 ( optlc_net_1557 ) ,
+ .p1538 ( optlc_net_1558 ) , .p1539 ( optlc_net_1559 ) ,
+ .p1540 ( optlc_net_1560 ) , .p1541 ( optlc_net_1561 ) ,
+ .p1542 ( optlc_net_1562 ) , .p1543 ( optlc_net_1563 ) ,
+ .p1544 ( optlc_net_1564 ) , .p1545 ( optlc_net_1565 ) ,
+ .p1546 ( optlc_net_1566 ) , .p1547 ( optlc_net_1567 ) ,
+ .p1548 ( optlc_net_1568 ) , .p1549 ( optlc_net_1569 ) ,
+ .p1550 ( optlc_net_1570 ) , .p1551 ( optlc_net_1571 ) ,
+ .p1552 ( optlc_net_1572 ) , .p1553 ( optlc_net_1573 ) ,
+ .p1554 ( optlc_net_1574 ) , .p1555 ( optlc_net_1575 ) ,
+ .p1556 ( optlc_net_1576 ) , .p1557 ( optlc_net_1577 ) ,
+ .p1558 ( optlc_net_1578 ) , .p1559 ( optlc_net_1579 ) ,
+ .p1560 ( optlc_net_1580 ) , .p1561 ( optlc_net_1581 ) ,
+ .p1562 ( optlc_net_1582 ) , .p1563 ( optlc_net_1583 ) ,
+ .p1564 ( optlc_net_1584 ) , .p1565 ( optlc_net_1585 ) ,
+ .p1566 ( optlc_net_1586 ) , .p1567 ( optlc_net_1587 ) ,
+ .p1568 ( optlc_net_1588 ) , .p1569 ( optlc_net_1589 ) ,
+ .p1570 ( optlc_net_1590 ) , .p1571 ( optlc_net_1591 ) ,
+ .p1572 ( optlc_net_1592 ) , .p1573 ( optlc_net_1593 ) ,
+ .p1574 ( optlc_net_1594 ) , .p1575 ( optlc_net_1595 ) ,
+ .p1576 ( optlc_net_1596 ) , .p1577 ( optlc_net_1597 ) ,
+ .p1578 ( optlc_net_1598 ) , .p1579 ( optlc_net_1599 ) ,
+ .p1580 ( optlc_net_1600 ) , .p1581 ( optlc_net_1601 ) ,
+ .p1582 ( optlc_net_1602 ) , .p1583 ( optlc_net_1603 ) ,
+ .p1584 ( optlc_net_1604 ) , .p1585 ( optlc_net_1605 ) ,
+ .p1586 ( optlc_net_1606 ) , .p1587 ( optlc_net_1607 ) ,
+ .p1588 ( optlc_net_1608 ) , .p1589 ( optlc_net_1609 ) ,
+ .p1590 ( optlc_net_1610 ) , .p1591 ( optlc_net_1611 ) ,
+ .p1592 ( optlc_net_1612 ) , .p1593 ( optlc_net_1613 ) ,
+ .p1594 ( optlc_net_1614 ) , .p1595 ( optlc_net_1615 ) ,
+ .p1596 ( optlc_net_1616 ) , .p1597 ( optlc_net_1617 ) ,
+ .p1598 ( optlc_net_1618 ) , .p1599 ( optlc_net_1619 ) ,
+ .p1600 ( optlc_net_1620 ) , .p1601 ( optlc_net_1621 ) ,
+ .p1602 ( optlc_net_1622 ) , .p1603 ( optlc_net_1623 ) ,
+ .p1604 ( optlc_net_1624 ) , .p1605 ( optlc_net_1625 ) ,
+ .p1606 ( optlc_net_1626 ) , .p1607 ( optlc_net_1627 ) ,
+ .p1608 ( optlc_net_1628 ) , .p1609 ( optlc_net_1629 ) ,
+ .p1610 ( optlc_net_1630 ) , .p1611 ( optlc_net_1631 ) ,
+ .p1612 ( optlc_net_1632 ) , .p1613 ( optlc_net_1633 ) ,
+ .p1614 ( optlc_net_1634 ) , .p1615 ( optlc_net_1635 ) ,
+ .p1616 ( optlc_net_1636 ) , .p1617 ( optlc_net_1637 ) ,
+ .p1618 ( optlc_net_1638 ) , .p1619 ( optlc_net_1639 ) ,
+ .p1620 ( optlc_net_1640 ) , .p1621 ( optlc_net_1641 ) ,
+ .p1622 ( optlc_net_1642 ) , .p1623 ( optlc_net_1643 ) ,
+ .p1624 ( optlc_net_1644 ) , .p1625 ( optlc_net_1645 ) ,
+ .p1626 ( optlc_net_1646 ) , .p1627 ( optlc_net_1647 ) ,
+ .p1628 ( optlc_net_1648 ) , .p1629 ( optlc_net_1649 ) ,
+ .p1630 ( optlc_net_1650 ) , .p1631 ( optlc_net_1651 ) ,
+ .p1632 ( optlc_net_1652 ) , .p1633 ( optlc_net_1653 ) ,
+ .p1634 ( optlc_net_1654 ) , .p1635 ( optlc_net_1655 ) ,
+ .p1636 ( optlc_net_1656 ) , .p1637 ( optlc_net_1657 ) ,
+ .p1638 ( optlc_net_1658 ) , .p1639 ( optlc_net_1659 ) ,
+ .p1640 ( optlc_net_1660 ) , .p1641 ( optlc_net_1661 ) ,
+ .p1642 ( optlc_net_1662 ) , .p1643 ( optlc_net_1663 ) ,
+ .p1644 ( optlc_net_1664 ) , .p1645 ( optlc_net_1665 ) ,
+ .p1646 ( optlc_net_1666 ) , .p1647 ( optlc_net_1667 ) ,
+ .p1648 ( optlc_net_1668 ) , .p1649 ( optlc_net_1669 ) ,
+ .p1650 ( optlc_net_1670 ) , .p1651 ( optlc_net_1671 ) ,
+ .p1652 ( optlc_net_1672 ) , .p1653 ( optlc_net_1673 ) ,
+ .p1654 ( optlc_net_1674 ) , .p1655 ( optlc_net_1675 ) ,
+ .p1656 ( optlc_net_1676 ) , .p1657 ( optlc_net_1677 ) ,
+ .p1658 ( optlc_net_1678 ) , .p1659 ( optlc_net_1679 ) ,
+ .p1660 ( optlc_net_1680 ) , .p1661 ( optlc_net_1681 ) ,
+ .p1662 ( optlc_net_1682 ) , .p1663 ( optlc_net_1683 ) ,
+ .p1664 ( optlc_net_1684 ) , .p1665 ( optlc_net_1685 ) ,
+ .p1666 ( optlc_net_1686 ) , .p1667 ( optlc_net_1687 ) ,
+ .p1668 ( optlc_net_1688 ) , .p1669 ( optlc_net_1689 ) ,
+ .p1670 ( optlc_net_1690 ) , .p1671 ( optlc_net_1691 ) ,
+ .p1672 ( optlc_net_1692 ) , .p1673 ( optlc_net_1693 ) ,
+ .p1674 ( optlc_net_1694 ) , .p1675 ( optlc_net_1695 ) ,
+ .p1676 ( optlc_net_1696 ) , .p1677 ( optlc_net_1697 ) ,
+ .p1678 ( optlc_net_1698 ) , .p1679 ( optlc_net_1699 ) ,
+ .p1680 ( optlc_net_1700 ) , .p1681 ( optlc_net_1701 ) ,
+ .p1682 ( optlc_net_1702 ) , .p1683 ( optlc_net_1703 ) ,
+ .p1684 ( optlc_net_1704 ) , .p1685 ( optlc_net_1705 ) ,
+ .p1686 ( optlc_net_1706 ) , .p1687 ( optlc_net_1707 ) ,
+ .p1688 ( optlc_net_1708 ) , .p1689 ( optlc_net_1709 ) ,
+ .p1690 ( optlc_net_1710 ) , .p1691 ( optlc_net_1711 ) ,
+ .p1692 ( optlc_net_1712 ) , .p1693 ( optlc_net_1713 ) ,
+ .p1694 ( optlc_net_1714 ) , .p1695 ( optlc_net_1715 ) ,
+ .p1696 ( optlc_net_1716 ) , .p1697 ( optlc_net_1717 ) ,
+ .p1698 ( optlc_net_1718 ) , .p1699 ( optlc_net_1719 ) ,
+ .p1700 ( optlc_net_1720 ) , .p1701 ( optlc_net_1721 ) ,
+ .p1702 ( optlc_net_1722 ) , .p1703 ( optlc_net_1723 ) ,
+ .p1704 ( optlc_net_1724 ) , .p1705 ( optlc_net_1725 ) ,
+ .p1706 ( optlc_net_1726 ) , .p1707 ( optlc_net_1727 ) ,
+ .p1708 ( optlc_net_1728 ) , .p1709 ( optlc_net_1729 ) ,
+ .p1710 ( optlc_net_1730 ) , .p1711 ( optlc_net_1731 ) ,
+ .p1712 ( optlc_net_1732 ) , .p1713 ( optlc_net_1733 ) ,
+ .p1714 ( optlc_net_1734 ) , .p1715 ( optlc_net_1735 ) ,
+ .p1716 ( optlc_net_1736 ) , .p1717 ( optlc_net_1737 ) ,
+ .p1718 ( optlc_net_1738 ) , .p1719 ( optlc_net_1739 ) ,
+ .p1720 ( optlc_net_1740 ) , .p1721 ( optlc_net_1741 ) ,
+ .p1722 ( optlc_net_1742 ) , .p1723 ( optlc_net_1743 ) ,
+ .p1724 ( optlc_net_1744 ) , .p1725 ( optlc_net_1745 ) ,
+ .p1726 ( optlc_net_1746 ) , .p1727 ( optlc_net_1747 ) ,
+ .p1728 ( optlc_net_1748 ) , .p1729 ( optlc_net_1749 ) ,
+ .p1730 ( optlc_net_1750 ) , .p1731 ( optlc_net_1751 ) ,
+ .p1732 ( optlc_net_1752 ) , .p1733 ( optlc_net_1753 ) ,
+ .p1734 ( optlc_net_1754 ) , .p1735 ( optlc_net_1755 ) ,
+ .p1736 ( optlc_net_1756 ) , .p1737 ( optlc_net_1757 ) ,
+ .p1738 ( optlc_net_1758 ) , .p1739 ( optlc_net_1759 ) ,
+ .p1740 ( optlc_net_1760 ) , .p1741 ( optlc_net_1761 ) ,
+ .p1742 ( optlc_net_1762 ) , .p1743 ( optlc_net_1763 ) ,
+ .p1744 ( optlc_net_1764 ) , .p1745 ( optlc_net_1765 ) ,
+ .p1746 ( optlc_net_1766 ) , .p1747 ( optlc_net_1767 ) ,
+ .p1748 ( optlc_net_1768 ) , .p1749 ( optlc_net_1769 ) ,
+ .p1750 ( optlc_net_1770 ) , .p1751 ( optlc_net_1771 ) ,
+ .p1752 ( optlc_net_1772 ) , .p1753 ( optlc_net_1773 ) ,
+ .p1754 ( optlc_net_1774 ) , .p1755 ( optlc_net_1775 ) ,
+ .p1756 ( optlc_net_1776 ) , .p1757 ( optlc_net_1777 ) ,
+ .p1758 ( optlc_net_1778 ) , .p1759 ( optlc_net_1779 ) ,
+ .p1760 ( optlc_net_1780 ) , .p1761 ( optlc_net_1781 ) ,
+ .p1762 ( optlc_net_1782 ) , .p1763 ( optlc_net_1783 ) ,
+ .p1764 ( optlc_net_1784 ) , .p1765 ( optlc_net_1785 ) ,
+ .p1766 ( optlc_net_1786 ) , .p1767 ( optlc_net_1787 ) ,
+ .p1768 ( optlc_net_1788 ) , .p1769 ( optlc_net_1789 ) ,
+ .p1770 ( optlc_net_1790 ) , .p1771 ( optlc_net_1791 ) ,
+ .p1772 ( optlc_net_1792 ) , .p1773 ( optlc_net_1793 ) ,
+ .p1774 ( optlc_net_1794 ) , .p1775 ( optlc_net_1795 ) ,
+ .p1776 ( optlc_net_1796 ) , .p1777 ( optlc_net_1797 ) ,
+ .p1778 ( optlc_net_1798 ) , .p1779 ( optlc_net_1799 ) ,
+ .p1780 ( optlc_net_1800 ) , .p1781 ( optlc_net_1801 ) ,
+ .p1782 ( optlc_net_1802 ) , .p1783 ( optlc_net_1803 ) ,
+ .p1784 ( optlc_net_1804 ) , .p1785 ( optlc_net_1805 ) ,
+ .p1786 ( optlc_net_1806 ) , .p1787 ( optlc_net_1807 ) ,
+ .p1788 ( optlc_net_1808 ) , .p1789 ( optlc_net_1809 ) ,
+ .p1790 ( optlc_net_1810 ) , .p1791 ( optlc_net_1811 ) ,
+ .p1792 ( optlc_net_1812 ) , .p1793 ( optlc_net_1813 ) ,
+ .p1794 ( optlc_net_1814 ) , .p1795 ( optlc_net_1815 ) ,
+ .p1796 ( optlc_net_1816 ) , .p1797 ( optlc_net_1817 ) ,
+ .p1798 ( optlc_net_1818 ) , .p1799 ( optlc_net_1819 ) ,
+ .p1800 ( optlc_net_1820 ) , .p1801 ( optlc_net_1821 ) ,
+ .p1802 ( optlc_net_1822 ) , .p1803 ( optlc_net_1823 ) ,
+ .p1804 ( optlc_net_1824 ) , .p1805 ( optlc_net_1825 ) ,
+ .p1806 ( optlc_net_1826 ) , .p1807 ( optlc_net_1827 ) ,
+ .p1808 ( optlc_net_1828 ) , .p1809 ( optlc_net_1829 ) ,
+ .p1810 ( optlc_net_1830 ) , .p1811 ( optlc_net_1831 ) ,
+ .p1812 ( optlc_net_1832 ) , .p1813 ( optlc_net_1833 ) ,
+ .p1814 ( optlc_net_1834 ) , .p1815 ( optlc_net_1835 ) ,
+ .p1816 ( optlc_net_1836 ) , .p1817 ( optlc_net_1837 ) ,
+ .p1818 ( optlc_net_1838 ) , .p1819 ( optlc_net_1839 ) ,
+ .p1820 ( optlc_net_1840 ) , .p1821 ( optlc_net_1841 ) ,
+ .p1822 ( optlc_net_1842 ) , .p1823 ( optlc_net_1843 ) ,
+ .p1824 ( optlc_net_1844 ) , .p1825 ( optlc_net_1845 ) ,
+ .p1826 ( optlc_net_1846 ) , .p1827 ( optlc_net_1847 ) ,
+ .p1828 ( optlc_net_1848 ) , .p1829 ( optlc_net_1849 ) ,
+ .p1830 ( optlc_net_1850 ) , .p1831 ( optlc_net_1851 ) ,
+ .p1832 ( optlc_net_1852 ) , .p1833 ( optlc_net_1853 ) ,
+ .p1834 ( optlc_net_1854 ) , .p1835 ( optlc_net_1855 ) ,
+ .p1836 ( optlc_net_1856 ) , .p1837 ( optlc_net_1857 ) ,
+ .p1838 ( optlc_net_1858 ) , .p1839 ( optlc_net_1859 ) ,
+ .p1840 ( optlc_net_1860 ) , .p1841 ( optlc_net_1861 ) ,
+ .p1842 ( optlc_net_1862 ) , .p1843 ( optlc_net_1863 ) ,
+ .p1844 ( optlc_net_1864 ) , .p1845 ( optlc_net_1865 ) ,
+ .p1846 ( optlc_net_1866 ) , .p1847 ( optlc_net_1867 ) ,
+ .p1848 ( optlc_net_1868 ) , .p1849 ( optlc_net_1869 ) ,
+ .p1850 ( optlc_net_1870 ) , .p1851 ( optlc_net_1871 ) ,
+ .p1852 ( optlc_net_1872 ) , .p1853 ( optlc_net_1873 ) ,
+ .p1854 ( optlc_net_1874 ) , .p1855 ( optlc_net_1875 ) ,
+ .p1856 ( optlc_net_1876 ) , .p1857 ( optlc_net_1877 ) ,
+ .p1858 ( optlc_net_1878 ) , .p1859 ( optlc_net_1879 ) ,
+ .p1860 ( optlc_net_1880 ) , .p1861 ( optlc_net_1881 ) ,
+ .p1862 ( optlc_net_1882 ) , .p1863 ( optlc_net_1883 ) ,
+ .p1864 ( optlc_net_1884 ) , .p1865 ( optlc_net_1885 ) ,
+ .p1866 ( optlc_net_1886 ) , .p1867 ( optlc_net_1887 ) ,
+ .p1868 ( optlc_net_1888 ) , .p1869 ( optlc_net_1889 ) ,
+ .p1870 ( optlc_net_1890 ) , .p1871 ( optlc_net_1891 ) ,
+ .p1872 ( optlc_net_1892 ) , .p1873 ( optlc_net_1893 ) ,
+ .p1874 ( optlc_net_1894 ) , .p1875 ( optlc_net_1895 ) ,
+ .p1876 ( optlc_net_1896 ) , .p1877 ( optlc_net_1897 ) ,
+ .p1878 ( optlc_net_1898 ) , .p1879 ( optlc_net_1899 ) ,
+ .p1880 ( optlc_net_1900 ) , .p1881 ( optlc_net_1901 ) ,
+ .p1882 ( optlc_net_1902 ) , .p1883 ( optlc_net_1903 ) ,
+ .p1884 ( optlc_net_1904 ) , .p1885 ( optlc_net_1905 ) ,
+ .p1886 ( optlc_net_1906 ) , .p1887 ( optlc_net_1907 ) ,
+ .p1888 ( optlc_net_1908 ) , .p1889 ( optlc_net_1909 ) ,
+ .p1890 ( optlc_net_1910 ) , .p1891 ( optlc_net_1911 ) ,
+ .p1892 ( optlc_net_1912 ) , .p1893 ( optlc_net_1913 ) ,
+ .p1894 ( optlc_net_1914 ) , .p1895 ( optlc_net_1915 ) ,
+ .p1896 ( optlc_net_1916 ) , .p1897 ( optlc_net_1917 ) ,
+ .p1898 ( optlc_net_1918 ) , .p1899 ( optlc_net_1919 ) ,
+ .p1900 ( optlc_net_1920 ) , .p1901 ( optlc_net_1921 ) ,
+ .p1902 ( optlc_net_1922 ) , .p1903 ( optlc_net_1923 ) ,
+ .p1904 ( optlc_net_1924 ) , .p1905 ( optlc_net_1925 ) ,
+ .p1906 ( optlc_net_1926 ) , .p1907 ( optlc_net_1927 ) ,
+ .p1908 ( optlc_net_1928 ) , .p1909 ( optlc_net_1929 ) ,
+ .p1910 ( optlc_net_1930 ) , .p1911 ( optlc_net_1931 ) ,
+ .p1912 ( optlc_net_1932 ) , .p1913 ( optlc_net_1933 ) ,
+ .p1914 ( optlc_net_1934 ) , .p1915 ( optlc_net_1935 ) ,
+ .p1916 ( optlc_net_1936 ) , .p1917 ( optlc_net_1937 ) ,
+ .p1918 ( optlc_net_1938 ) , .p1919 ( optlc_net_1939 ) ,
+ .p1920 ( optlc_net_1940 ) , .p1921 ( optlc_net_1941 ) ,
+ .p1922 ( optlc_net_1942 ) , .p1923 ( optlc_net_1943 ) ,
+ .p1924 ( optlc_net_1944 ) , .p1925 ( optlc_net_1945 ) ,
+ .p1926 ( optlc_net_1946 ) , .p1927 ( optlc_net_1947 ) ,
+ .p1928 ( optlc_net_1948 ) , .p1929 ( optlc_net_1949 ) ,
+ .p1930 ( optlc_net_1950 ) , .p1931 ( optlc_net_1951 ) ,
+ .p1932 ( optlc_net_1952 ) , .p1933 ( optlc_net_1953 ) ,
+ .p1934 ( optlc_net_1954 ) , .p1935 ( optlc_net_1955 ) ,
+ .p1936 ( optlc_net_1956 ) , .p1937 ( optlc_net_1957 ) ,
+ .p1938 ( optlc_net_1958 ) , .p1939 ( optlc_net_1959 ) ,
+ .p1940 ( optlc_net_1960 ) , .p1941 ( optlc_net_1961 ) ,
+ .p1942 ( optlc_net_1962 ) , .p1943 ( optlc_net_1963 ) ,
+ .p1944 ( optlc_net_1964 ) , .p1945 ( optlc_net_1965 ) ,
+ .p1946 ( optlc_net_1966 ) , .p1947 ( optlc_net_1967 ) ,
+ .p1948 ( optlc_net_1968 ) , .p1949 ( optlc_net_1969 ) ,
+ .p1950 ( optlc_net_1970 ) , .p1951 ( optlc_net_1971 ) ,
+ .p1952 ( optlc_net_1972 ) , .p1953 ( optlc_net_1973 ) ,
+ .p1954 ( optlc_net_1974 ) , .p1955 ( optlc_net_1975 ) ,
+ .p1956 ( optlc_net_1976 ) , .p1957 ( optlc_net_1977 ) ,
+ .p1958 ( optlc_net_1978 ) , .p1959 ( optlc_net_1979 ) ,
+ .p1960 ( optlc_net_1980 ) , .p1961 ( optlc_net_1981 ) ,
+ .p1962 ( optlc_net_1982 ) , .p1963 ( optlc_net_1983 ) ,
+ .p1964 ( optlc_net_1984 ) , .p1965 ( optlc_net_1985 ) ,
+ .p1966 ( optlc_net_1986 ) , .p1967 ( optlc_net_1987 ) ,
+ .p1968 ( optlc_net_1988 ) , .p1969 ( optlc_net_1989 ) ,
+ .p1970 ( optlc_net_1990 ) , .p1971 ( optlc_net_1991 ) ,
+ .p1972 ( optlc_net_1992 ) , .p1973 ( optlc_net_1993 ) ,
+ .p1974 ( optlc_net_1994 ) , .p1975 ( optlc_net_1995 ) ,
+ .p1976 ( optlc_net_1996 ) , .p1977 ( optlc_net_1997 ) ,
+ .p1978 ( optlc_net_1998 ) , .p1979 ( optlc_net_1999 ) ,
+ .p1980 ( optlc_net_2000 ) , .p1981 ( optlc_net_2001 ) ,
+ .p1982 ( optlc_net_2002 ) , .p1983 ( optlc_net_2003 ) ,
+ .p1984 ( optlc_net_2004 ) , .p1985 ( optlc_net_2005 ) ,
+ .p1986 ( optlc_net_2006 ) , .p1987 ( optlc_net_2007 ) ,
+ .p1988 ( optlc_net_2008 ) , .p1989 ( optlc_net_2009 ) ,
+ .p1990 ( optlc_net_2010 ) , .p1991 ( optlc_net_2011 ) ,
+ .p1992 ( optlc_net_2012 ) , .p1993 ( optlc_net_2013 ) ,
+ .p1994 ( optlc_net_2014 ) , .p1995 ( optlc_net_2015 ) ,
+ .p1996 ( optlc_net_2016 ) , .p1997 ( optlc_net_2017 ) ,
+ .p1998 ( optlc_net_2018 ) , .p1999 ( optlc_net_2019 ) ,
+ .p2000 ( optlc_net_2020 ) , .p2001 ( optlc_net_2021 ) ,
+ .p2002 ( optlc_net_2022 ) , .p2003 ( optlc_net_2023 ) ,
+ .p2004 ( optlc_net_2024 ) , .p2005 ( optlc_net_2025 ) ,
+ .p2006 ( optlc_net_2026 ) , .p2007 ( optlc_net_2027 ) ,
+ .p2008 ( optlc_net_2028 ) , .p2009 ( optlc_net_2029 ) ,
+ .p2010 ( optlc_net_2030 ) , .p2011 ( optlc_net_2031 ) ,
+ .p2012 ( optlc_net_2032 ) , .p2013 ( optlc_net_2033 ) ,
+ .p2014 ( optlc_net_2034 ) , .p2015 ( optlc_net_2035 ) ,
+ .p2016 ( optlc_net_2036 ) , .p2017 ( optlc_net_2037 ) ,
+ .p2018 ( optlc_net_2038 ) , .p2019 ( optlc_net_2039 ) ,
+ .p2020 ( optlc_net_2040 ) , .p2021 ( optlc_net_2041 ) ,
+ .p2022 ( optlc_net_2042 ) , .p2023 ( optlc_net_2043 ) ,
+ .p2024 ( optlc_net_2044 ) , .p2025 ( optlc_net_2045 ) ,
+ .p2026 ( optlc_net_2046 ) , .p2027 ( optlc_net_2047 ) ,
+ .p2028 ( optlc_net_2048 ) , .p2029 ( optlc_net_2049 ) ,
+ .p2030 ( optlc_net_2050 ) , .p2031 ( optlc_net_2051 ) ,
+ .p2032 ( optlc_net_2052 ) , .p2033 ( optlc_net_2053 ) ,
+ .p2034 ( optlc_net_2054 ) , .p2035 ( optlc_net_2055 ) ,
+ .p2036 ( optlc_net_2056 ) , .p2037 ( optlc_net_2057 ) ,
+ .p2038 ( optlc_net_2058 ) , .p2039 ( optlc_net_2059 ) ,
+ .p2040 ( optlc_net_2060 ) , .p2041 ( optlc_net_2061 ) ,
+ .p2042 ( optlc_net_2062 ) , .p2043 ( optlc_net_2063 ) ,
+ .p2044 ( optlc_net_2064 ) , .p2045 ( optlc_net_2065 ) ,
+ .p2046 ( optlc_net_2066 ) , .p2047 ( optlc_net_2067 ) ,
+ .p2048 ( optlc_net_2068 ) , .p2049 ( optlc_net_2069 ) ,
+ .p2050 ( optlc_net_2070 ) , .p2051 ( optlc_net_2071 ) ,
+ .p2052 ( optlc_net_2072 ) , .p2053 ( optlc_net_2073 ) ,
+ .p2054 ( optlc_net_2074 ) , .p2055 ( optlc_net_2075 ) ,
+ .p2056 ( optlc_net_2076 ) , .p2057 ( optlc_net_2077 ) ,
+ .p2058 ( optlc_net_2078 ) , .p2059 ( optlc_net_2079 ) ,
+ .p2060 ( optlc_net_2080 ) , .p2061 ( optlc_net_2081 ) ,
+ .p2062 ( optlc_net_2082 ) , .p2063 ( optlc_net_2083 ) ,
+ .p2064 ( optlc_net_2084 ) , .p2065 ( optlc_net_2085 ) ,
+ .p2066 ( optlc_net_2086 ) , .p2067 ( optlc_net_2087 ) ,
+ .p2068 ( optlc_net_2088 ) , .p2069 ( optlc_net_2089 ) ,
+ .p2070 ( optlc_net_2090 ) , .p2071 ( optlc_net_2091 ) ,
+ .p2072 ( optlc_net_2092 ) , .p2073 ( optlc_net_2093 ) ,
+ .p2074 ( optlc_net_2094 ) , .p2075 ( optlc_net_2095 ) ,
+ .p2076 ( optlc_net_2096 ) , .p2077 ( optlc_net_2097 ) ,
+ .p2078 ( optlc_net_2098 ) , .p2079 ( optlc_net_2099 ) ,
+ .p2080 ( optlc_net_2100 ) , .p2081 ( optlc_net_2101 ) ,
+ .p2082 ( optlc_net_2102 ) , .p2083 ( optlc_net_2103 ) ,
+ .p2084 ( optlc_net_2104 ) , .p2085 ( optlc_net_2105 ) ,
+ .p2086 ( optlc_net_2106 ) , .p2087 ( optlc_net_2107 ) ,
+ .p2088 ( optlc_net_2108 ) , .p2089 ( optlc_net_2109 ) ,
+ .p2090 ( optlc_net_2110 ) , .p2091 ( optlc_net_2111 ) ,
+ .p2092 ( optlc_net_2112 ) , .p2093 ( optlc_net_2113 ) ,
+ .p2094 ( optlc_net_2114 ) , .p2095 ( optlc_net_2115 ) ,
+ .p2096 ( optlc_net_2116 ) , .p2097 ( optlc_net_2117 ) ,
+ .p2098 ( optlc_net_2118 ) , .p2099 ( optlc_net_2119 ) ,
+ .p2100 ( optlc_net_2120 ) , .p2101 ( optlc_net_2121 ) ,
+ .p2102 ( optlc_net_2122 ) , .p2103 ( optlc_net_2123 ) ,
+ .p2104 ( optlc_net_2124 ) , .p2105 ( optlc_net_2125 ) ,
+ .p2106 ( optlc_net_2126 ) , .p2107 ( optlc_net_2127 ) ,
+ .p2108 ( optlc_net_2128 ) , .p2109 ( optlc_net_2129 ) ,
+ .p2110 ( optlc_net_2130 ) , .p2111 ( optlc_net_2131 ) ,
+ .p2112 ( optlc_net_2132 ) , .p2113 ( optlc_net_2133 ) ,
+ .p2114 ( optlc_net_2134 ) , .p2115 ( optlc_net_2135 ) ,
+ .p2116 ( optlc_net_2136 ) , .p2117 ( optlc_net_2137 ) ,
+ .p2118 ( optlc_net_2138 ) , .p2119 ( optlc_net_2139 ) ,
+ .p2120 ( optlc_net_2140 ) , .p2121 ( optlc_net_2141 ) ,
+ .p2122 ( optlc_net_2142 ) , .p2123 ( optlc_net_2143 ) ,
+ .p2124 ( optlc_net_2144 ) , .p2125 ( optlc_net_2145 ) ,
+ .p2126 ( optlc_net_2146 ) , .p2127 ( optlc_net_2147 ) ,
+ .p2128 ( optlc_net_2148 ) , .p2129 ( optlc_net_2149 ) ,
+ .p2130 ( optlc_net_2150 ) , .p2131 ( optlc_net_2151 ) ,
+ .p2132 ( optlc_net_2152 ) , .p2133 ( optlc_net_2153 ) ,
+ .p2134 ( optlc_net_2154 ) , .p2135 ( optlc_net_2155 ) ,
+ .p2136 ( optlc_net_2156 ) , .p2137 ( optlc_net_2157 ) ,
+ .p2138 ( optlc_net_2158 ) , .p2139 ( optlc_net_2159 ) ,
+ .p2140 ( optlc_net_2160 ) , .p2141 ( optlc_net_2161 ) ,
+ .p2142 ( optlc_net_2162 ) , .p2143 ( optlc_net_2163 ) ,
+ .p2144 ( optlc_net_2164 ) , .p2145 ( optlc_net_2165 ) ,
+ .p2146 ( optlc_net_2166 ) , .p2147 ( optlc_net_2167 ) ,
+ .p2148 ( optlc_net_2168 ) , .p2149 ( optlc_net_2169 ) ,
+ .p2150 ( optlc_net_2170 ) , .p2151 ( optlc_net_2171 ) ,
+ .p2152 ( optlc_net_2172 ) , .p2153 ( optlc_net_2173 ) ,
+ .p2154 ( optlc_net_2174 ) , .p2155 ( optlc_net_2175 ) ,
+ .p2156 ( optlc_net_2176 ) , .p2157 ( optlc_net_2177 ) ,
+ .p2158 ( optlc_net_2178 ) , .p2159 ( optlc_net_2179 ) ,
+ .p2160 ( optlc_net_2180 ) , .p2161 ( optlc_net_2181 ) ,
+ .p2162 ( optlc_net_2182 ) , .p2163 ( optlc_net_2183 ) ,
+ .p2164 ( optlc_net_2184 ) , .p2165 ( optlc_net_2185 ) ,
+ .p2166 ( optlc_net_2186 ) , .p2167 ( optlc_net_2187 ) ,
+ .p2168 ( optlc_net_2188 ) , .p2169 ( optlc_net_2189 ) ,
+ .p2170 ( optlc_net_2190 ) , .p2171 ( optlc_net_2191 ) ,
+ .p2172 ( optlc_net_2192 ) , .p2173 ( optlc_net_2193 ) ,
+ .p2174 ( optlc_net_2194 ) , .p2175 ( optlc_net_2195 ) ,
+ .p2176 ( optlc_net_2196 ) , .p2177 ( optlc_net_2197 ) ,
+ .p2178 ( optlc_net_2198 ) , .p2179 ( optlc_net_2199 ) ,
+ .p2180 ( optlc_net_2200 ) , .p2181 ( optlc_net_2201 ) ,
+ .p2182 ( optlc_net_2202 ) , .p2183 ( optlc_net_2203 ) ,
+ .p2184 ( optlc_net_2204 ) , .p2185 ( optlc_net_2205 ) ,
+ .p2186 ( optlc_net_2206 ) , .p2187 ( optlc_net_2207 ) ,
+ .p2188 ( optlc_net_2208 ) , .p2189 ( optlc_net_2209 ) ,
+ .p2190 ( optlc_net_2210 ) , .p2191 ( optlc_net_2211 ) ,
+ .p2192 ( optlc_net_2212 ) , .p2193 ( optlc_net_2213 ) ,
+ .p2194 ( optlc_net_2214 ) , .p2195 ( optlc_net_2215 ) ,
+ .p2196 ( optlc_net_2216 ) , .p2197 ( optlc_net_2217 ) ,
+ .p2198 ( optlc_net_2218 ) , .p2199 ( optlc_net_2219 ) ,
+ .p2200 ( optlc_net_2220 ) , .p2201 ( optlc_net_2221 ) ,
+ .p2202 ( optlc_net_2222 ) , .p2203 ( optlc_net_2223 ) ,
+ .p2204 ( optlc_net_2224 ) , .p2205 ( optlc_net_2225 ) ,
+ .p2206 ( optlc_net_2226 ) , .p2207 ( optlc_net_2227 ) ,
+ .p2208 ( optlc_net_2228 ) , .p2209 ( optlc_net_2229 ) ,
+ .p2210 ( optlc_net_2230 ) , .p2211 ( optlc_net_2231 ) ,
+ .p2212 ( optlc_net_2232 ) , .p2213 ( optlc_net_2233 ) ,
+ .p2214 ( optlc_net_2234 ) , .p2215 ( optlc_net_2235 ) ,
+ .p2216 ( optlc_net_2236 ) , .p2217 ( optlc_net_2237 ) ,
+ .p2218 ( optlc_net_2238 ) , .p2219 ( optlc_net_2239 ) ,
+ .p2220 ( optlc_net_2240 ) , .p2221 ( optlc_net_2241 ) ,
+ .p2222 ( optlc_net_2242 ) , .p2223 ( optlc_net_2243 ) ,
+ .p2224 ( optlc_net_2244 ) , .p2225 ( optlc_net_2245 ) ,
+ .p2226 ( optlc_net_2246 ) , .p2227 ( optlc_net_2247 ) ,
+ .p2228 ( optlc_net_2248 ) , .p2229 ( optlc_net_2249 ) ,
+ .p2230 ( optlc_net_2250 ) , .p2231 ( optlc_net_2251 ) ,
+ .p2232 ( optlc_net_2252 ) , .p2233 ( optlc_net_2253 ) ,
+ .p2234 ( optlc_net_2254 ) , .p2235 ( optlc_net_2255 ) ,
+ .p2236 ( optlc_net_2256 ) , .p2237 ( optlc_net_2257 ) ,
+ .p2238 ( optlc_net_2258 ) , .p2239 ( optlc_net_2259 ) ,
+ .p2240 ( optlc_net_2260 ) , .p2241 ( optlc_net_2261 ) ,
+ .p2242 ( optlc_net_2262 ) , .p2243 ( optlc_net_2263 ) ,
+ .p2244 ( optlc_net_2264 ) , .p2245 ( optlc_net_2265 ) ,
+ .p2246 ( optlc_net_2266 ) , .p2247 ( optlc_net_2267 ) ,
+ .p2248 ( optlc_net_2268 ) , .p2249 ( optlc_net_2269 ) ,
+ .p2250 ( optlc_net_2270 ) , .p2251 ( optlc_net_2271 ) ,
+ .p2252 ( optlc_net_2272 ) , .p2253 ( optlc_net_2273 ) ,
+ .p2254 ( optlc_net_2274 ) , .p2255 ( optlc_net_2275 ) ,
+ .p2256 ( optlc_net_2276 ) , .p2257 ( optlc_net_2277 ) ,
+ .p2258 ( optlc_net_2278 ) , .p2259 ( optlc_net_2279 ) ,
+ .p2260 ( optlc_net_2280 ) , .p2261 ( optlc_net_2281 ) ,
+ .p2262 ( optlc_net_2282 ) , .p2263 ( optlc_net_2283 ) ,
+ .p2264 ( optlc_net_2284 ) , .p2265 ( optlc_net_2285 ) ,
+ .p2266 ( optlc_net_2286 ) , .p2267 ( optlc_net_2287 ) ,
+ .p2268 ( optlc_net_2288 ) , .p2269 ( optlc_net_2289 ) ,
+ .p2270 ( optlc_net_2290 ) , .p2271 ( optlc_net_2291 ) ,
+ .p2272 ( optlc_net_2292 ) , .p2273 ( optlc_net_2293 ) ,
+ .p2274 ( optlc_net_2294 ) , .p2275 ( optlc_net_2295 ) ,
+ .p2276 ( optlc_net_2296 ) , .p2277 ( optlc_net_2297 ) ,
+ .p2278 ( optlc_net_2298 ) , .p2279 ( optlc_net_2299 ) ,
+ .p2280 ( optlc_net_2300 ) , .p2281 ( optlc_net_2301 ) ,
+ .p2282 ( optlc_net_2302 ) , .p2283 ( optlc_net_2303 ) ,
+ .p2284 ( optlc_net_2304 ) , .p2285 ( optlc_net_2305 ) ,
+ .p2286 ( optlc_net_2306 ) , .p2287 ( optlc_net_2307 ) ,
+ .p2288 ( optlc_net_2308 ) , .p2289 ( optlc_net_2309 ) ,
+ .p2290 ( optlc_net_2310 ) , .p2291 ( optlc_net_2311 ) ,
+ .p2292 ( optlc_net_2312 ) , .p2293 ( optlc_net_2313 ) ,
+ .p2294 ( optlc_net_2314 ) , .p2295 ( optlc_net_2315 ) ,
+ .p2296 ( optlc_net_2316 ) , .p2297 ( optlc_net_2317 ) ,
+ .p2298 ( optlc_net_2318 ) , .p2299 ( optlc_net_2319 ) ,
+ .p2300 ( optlc_net_2320 ) , .p2301 ( optlc_net_2321 ) ,
+ .p2302 ( optlc_net_2322 ) , .p2303 ( optlc_net_2323 ) ,
+ .p2304 ( optlc_net_2324 ) , .p2305 ( optlc_net_2325 ) ,
+ .p2306 ( optlc_net_2326 ) , .p2307 ( optlc_net_2327 ) ,
+ .p2308 ( optlc_net_2328 ) , .p2309 ( optlc_net_2329 ) ,
+ .p2310 ( optlc_net_2330 ) , .p2311 ( optlc_net_2331 ) ,
+ .p2312 ( optlc_net_2332 ) , .p2313 ( optlc_net_2333 ) ,
+ .p2314 ( optlc_net_2334 ) , .p2315 ( optlc_net_2335 ) ,
+ .p2316 ( optlc_net_2336 ) , .p2317 ( optlc_net_2337 ) ,
+ .p2318 ( optlc_net_2338 ) , .p2319 ( optlc_net_2339 ) ,
+ .p2320 ( optlc_net_2340 ) , .p2321 ( optlc_net_2341 ) ,
+ .p2322 ( optlc_net_2342 ) , .p2323 ( optlc_net_2343 ) ,
+ .p2324 ( optlc_net_2344 ) , .p2325 ( optlc_net_2345 ) ,
+ .p2326 ( optlc_net_2346 ) , .p2327 ( optlc_net_2347 ) ,
+ .p2328 ( optlc_net_2348 ) , .p2329 ( optlc_net_2349 ) ,
+ .p2330 ( optlc_net_2350 ) , .p2331 ( optlc_net_2351 ) ,
+ .p2332 ( optlc_net_2352 ) , .p2333 ( optlc_net_2353 ) ,
+ .p2334 ( optlc_net_2354 ) , .p2335 ( optlc_net_2355 ) ,
+ .p2336 ( optlc_net_2356 ) , .p2337 ( optlc_net_2357 ) ,
+ .p2338 ( optlc_net_2358 ) , .p2339 ( optlc_net_2359 ) ,
+ .p2340 ( optlc_net_2360 ) , .p2341 ( optlc_net_2361 ) ,
+ .p2342 ( optlc_net_2362 ) , .p2343 ( optlc_net_2363 ) ,
+ .p2344 ( optlc_net_2364 ) , .p2345 ( optlc_net_2365 ) ,
+ .p2346 ( optlc_net_2366 ) , .p2347 ( optlc_net_2367 ) ,
+ .p2348 ( optlc_net_2368 ) , .p2349 ( optlc_net_2369 ) ,
+ .p2350 ( optlc_net_2370 ) , .p2351 ( optlc_net_2371 ) ,
+ .p2352 ( optlc_net_2372 ) , .p2353 ( optlc_net_2373 ) ,
+ .p2354 ( optlc_net_2374 ) , .p2355 ( optlc_net_2375 ) ,
+ .p2356 ( optlc_net_2376 ) , .p2357 ( optlc_net_2377 ) ,
+ .p2358 ( optlc_net_2378 ) , .p2359 ( optlc_net_2379 ) ,
+ .p2360 ( optlc_net_2380 ) , .p2361 ( optlc_net_2381 ) ,
+ .p2362 ( optlc_net_2382 ) , .p2363 ( optlc_net_2383 ) ,
+ .p2364 ( optlc_net_2384 ) , .p2365 ( optlc_net_2385 ) ,
+ .p2366 ( optlc_net_2386 ) , .p2367 ( optlc_net_2387 ) ,
+ .p2368 ( optlc_net_2388 ) , .p2369 ( optlc_net_2389 ) ,
+ .p2370 ( optlc_net_2390 ) , .p2371 ( optlc_net_2391 ) ,
+ .p2372 ( optlc_net_2392 ) , .p2373 ( optlc_net_2393 ) ,
+ .p2374 ( optlc_net_2394 ) , .p2375 ( optlc_net_2395 ) ,
+ .p2376 ( optlc_net_2396 ) , .p2377 ( optlc_net_2397 ) ,
+ .p2378 ( optlc_net_2398 ) , .p2379 ( optlc_net_2399 ) ,
+ .p2380 ( optlc_net_2400 ) , .p2381 ( optlc_net_2401 ) ,
+ .p2382 ( optlc_net_2402 ) , .p2383 ( optlc_net_2403 ) ,
+ .p2384 ( optlc_net_2404 ) , .p2385 ( optlc_net_2405 ) ,
+ .p2386 ( optlc_net_2406 ) , .p2387 ( optlc_net_2407 ) ,
+ .p2388 ( optlc_net_2408 ) , .p2389 ( optlc_net_2409 ) ,
+ .p2390 ( optlc_net_2410 ) , .p2391 ( optlc_net_2411 ) ,
+ .p2392 ( optlc_net_2412 ) , .p2393 ( optlc_net_2413 ) ,
+ .p2394 ( optlc_net_2414 ) , .p2395 ( optlc_net_2415 ) ,
+ .p2396 ( optlc_net_2416 ) , .p2397 ( optlc_net_2417 ) ,
+ .p2398 ( optlc_net_2418 ) , .p2399 ( optlc_net_2419 ) ,
+ .p2400 ( optlc_net_2420 ) , .p2401 ( optlc_net_2421 ) ,
+ .p2402 ( optlc_net_2422 ) , .p2403 ( optlc_net_2423 ) ,
+ .p2404 ( optlc_net_2424 ) , .p2405 ( optlc_net_2425 ) ,
+ .p2406 ( optlc_net_2426 ) , .p2407 ( optlc_net_2427 ) ,
+ .p2408 ( optlc_net_2428 ) , .p2409 ( optlc_net_2429 ) ,
+ .p2410 ( optlc_net_2430 ) , .p2411 ( optlc_net_2431 ) ,
+ .p2412 ( optlc_net_2432 ) , .p2413 ( optlc_net_2433 ) ,
+ .p2414 ( optlc_net_2434 ) , .p2415 ( optlc_net_2435 ) ,
+ .p2416 ( optlc_net_2436 ) , .p2417 ( optlc_net_2437 ) ,
+ .p2418 ( optlc_net_2438 ) , .p2419 ( optlc_net_2439 ) ,
+ .p2420 ( optlc_net_2440 ) , .p2421 ( optlc_net_2441 ) ,
+ .p2422 ( optlc_net_2442 ) , .p2423 ( optlc_net_2443 ) ,
+ .p2424 ( optlc_net_2444 ) , .p2425 ( optlc_net_2445 ) ,
+ .p2426 ( optlc_net_2446 ) , .p2427 ( optlc_net_2447 ) ,
+ .p2428 ( optlc_net_2448 ) , .p2429 ( optlc_net_2449 ) ,
+ .p2430 ( optlc_net_2450 ) , .p2431 ( optlc_net_2451 ) ,
+ .p2432 ( optlc_net_2452 ) , .p2433 ( optlc_net_2453 ) ,
+ .p2434 ( optlc_net_2454 ) , .p2435 ( optlc_net_2455 ) ,
+ .p2436 ( optlc_net_2456 ) , .p2437 ( optlc_net_2457 ) ,
+ .p2438 ( optlc_net_2458 ) , .p2439 ( optlc_net_2459 ) ,
+ .p2440 ( optlc_net_2460 ) , .p2441 ( optlc_net_2461 ) ,
+ .p2442 ( optlc_net_2462 ) , .p2443 ( optlc_net_2463 ) ,
+ .p2444 ( optlc_net_2464 ) , .p2445 ( optlc_net_2465 ) ,
+ .p2446 ( optlc_net_2466 ) , .p2447 ( optlc_net_2467 ) ,
+ .p2448 ( optlc_net_2468 ) , .p2449 ( optlc_net_2469 ) ,
+ .p2450 ( optlc_net_2470 ) , .p2451 ( optlc_net_2471 ) ,
+ .p2452 ( optlc_net_2472 ) , .p2453 ( optlc_net_2473 ) ,
+ .p2454 ( optlc_net_2474 ) , .p2455 ( optlc_net_2475 ) ,
+ .p2456 ( optlc_net_2476 ) , .p2457 ( optlc_net_2477 ) ,
+ .p2458 ( optlc_net_2478 ) , .p2459 ( optlc_net_2479 ) ,
+ .p2460 ( optlc_net_2480 ) , .p2461 ( optlc_net_2481 ) ,
+ .p2462 ( optlc_net_2482 ) , .p2463 ( optlc_net_2483 ) ,
+ .p2464 ( optlc_net_2484 ) , .p2465 ( optlc_net_2485 ) ,
+ .p2466 ( optlc_net_2486 ) , .p2467 ( optlc_net_2487 ) ,
+ .p2468 ( optlc_net_2488 ) , .p2469 ( optlc_net_2489 ) ,
+ .p2470 ( optlc_net_2490 ) , .p2471 ( optlc_net_2491 ) ,
+ .p2472 ( optlc_net_2492 ) , .p2473 ( optlc_net_2493 ) ,
+ .p2474 ( optlc_net_2494 ) , .p2475 ( optlc_net_2495 ) ,
+ .p2476 ( optlc_net_2496 ) , .p2477 ( optlc_net_2497 ) ,
+ .p2478 ( optlc_net_2498 ) , .p2479 ( optlc_net_2499 ) ,
+ .p2480 ( optlc_net_2500 ) , .p2481 ( optlc_net_2501 ) ,
+ .p2482 ( optlc_net_2502 ) , .p2483 ( optlc_net_2503 ) ,
+ .p2484 ( optlc_net_2504 ) , .p2485 ( optlc_net_2505 ) ,
+ .p2486 ( optlc_net_2506 ) , .p2487 ( optlc_net_2507 ) ,
+ .p2488 ( optlc_net_2508 ) , .p2489 ( optlc_net_2509 ) ,
+ .p2490 ( optlc_net_2510 ) , .p2491 ( optlc_net_2511 ) ,
+ .p2492 ( optlc_net_2512 ) , .p2493 ( optlc_net_2513 ) ,
+ .p2494 ( optlc_net_2514 ) , .p2495 ( optlc_net_2515 ) ,
+ .p2496 ( optlc_net_2516 ) , .p2497 ( optlc_net_2517 ) ,
+ .p2498 ( optlc_net_2518 ) , .p2499 ( optlc_net_2519 ) ,
+ .p2500 ( optlc_net_2520 ) , .p2501 ( optlc_net_2521 ) ,
+ .p2502 ( optlc_net_2522 ) , .p2503 ( optlc_net_2523 ) ,
+ .p2504 ( optlc_net_2524 ) , .p2505 ( optlc_net_2525 ) ,
+ .p2506 ( optlc_net_2526 ) , .p2507 ( optlc_net_2527 ) ,
+ .p2508 ( optlc_net_2528 ) , .p2509 ( optlc_net_2529 ) ,
+ .p2510 ( optlc_net_2530 ) , .p2511 ( optlc_net_2531 ) ,
+ .p2512 ( optlc_net_2532 ) , .p2513 ( optlc_net_2533 ) ,
+ .p2514 ( optlc_net_2534 ) , .p2515 ( optlc_net_2535 ) ,
+ .p2516 ( optlc_net_2536 ) , .p2517 ( optlc_net_2537 ) ,
+ .p2518 ( optlc_net_2538 ) , .p2519 ( optlc_net_2539 ) ,
+ .p2520 ( optlc_net_2540 ) , .p2521 ( optlc_net_2541 ) ,
+ .p2522 ( optlc_net_2542 ) , .p2523 ( optlc_net_2543 ) ,
+ .p2524 ( optlc_net_2544 ) , .p2525 ( optlc_net_2545 ) ,
+ .p2526 ( optlc_net_2546 ) , .p2527 ( optlc_net_2547 ) ,
+ .p2528 ( optlc_net_2548 ) , .p2529 ( optlc_net_2549 ) ,
+ .p2530 ( optlc_net_2550 ) , .p2531 ( optlc_net_2551 ) ,
+ .p2532 ( optlc_net_2552 ) , .p2533 ( optlc_net_2553 ) ,
+ .p2534 ( optlc_net_2554 ) , .p2535 ( optlc_net_2555 ) ,
+ .p2536 ( optlc_net_2556 ) , .p2537 ( optlc_net_2557 ) ,
+ .p2538 ( optlc_net_2558 ) , .p2539 ( optlc_net_2559 ) ,
+ .p2540 ( optlc_net_2560 ) , .p2541 ( optlc_net_2561 ) ,
+ .p2542 ( optlc_net_2562 ) , .p2543 ( optlc_net_2563 ) ,
+ .p2544 ( optlc_net_2564 ) , .p2545 ( optlc_net_2565 ) ,
+ .p2546 ( optlc_net_2566 ) , .p2547 ( optlc_net_2567 ) ,
+ .p2548 ( optlc_net_2568 ) , .p2549 ( optlc_net_2569 ) ,
+ .p2550 ( optlc_net_2570 ) , .p2551 ( optlc_net_2571 ) ,
+ .p2552 ( optlc_net_2572 ) , .p2553 ( optlc_net_2573 ) ,
+ .p2554 ( optlc_net_2574 ) , .p2555 ( optlc_net_2575 ) ,
+ .p2556 ( optlc_net_2576 ) , .p2557 ( optlc_net_2577 ) ,
+ .p2558 ( optlc_net_2578 ) , .p2559 ( optlc_net_2579 ) ,
+ .p2560 ( optlc_net_2580 ) , .p2561 ( optlc_net_2581 ) ,
+ .p2562 ( optlc_net_2582 ) , .p2563 ( optlc_net_2583 ) ,
+ .p2564 ( optlc_net_2584 ) , .p2565 ( optlc_net_2585 ) ,
+ .p2566 ( optlc_net_2586 ) , .p2567 ( optlc_net_2587 ) ,
+ .p2568 ( optlc_net_2588 ) , .p2569 ( optlc_net_2589 ) ,
+ .p2570 ( optlc_net_2590 ) , .p2571 ( optlc_net_2591 ) ,
+ .p2572 ( optlc_net_2592 ) , .p2573 ( optlc_net_2593 ) ,
+ .p2574 ( optlc_net_2594 ) , .p2575 ( optlc_net_2595 ) ,
+ .p2576 ( optlc_net_2596 ) , .p2577 ( optlc_net_2597 ) ,
+ .p2578 ( optlc_net_2598 ) , .p2579 ( optlc_net_2599 ) ,
+ .p2580 ( optlc_net_2600 ) , .p2581 ( optlc_net_2601 ) ,
+ .p2582 ( optlc_net_2602 ) , .p2583 ( optlc_net_2603 ) ,
+ .p2584 ( optlc_net_2604 ) , .p2585 ( optlc_net_2605 ) ,
+ .p2586 ( optlc_net_2606 ) , .p2587 ( optlc_net_2607 ) ,
+ .p2588 ( optlc_net_2608 ) , .p2589 ( optlc_net_2609 ) ,
+ .p2590 ( optlc_net_2610 ) , .p2591 ( optlc_net_2611 ) ,
+ .p2592 ( optlc_net_2612 ) , .p2593 ( optlc_net_2613 ) ,
+ .p2594 ( optlc_net_2614 ) , .p2595 ( optlc_net_2615 ) ,
+ .p2596 ( optlc_net_2616 ) , .p2597 ( optlc_net_2617 ) ,
+ .p2598 ( optlc_net_2618 ) , .p2599 ( optlc_net_2619 ) ,
+ .p2600 ( optlc_net_2620 ) , .p2601 ( optlc_net_2621 ) ,
+ .p2602 ( optlc_net_2622 ) , .p2603 ( optlc_net_2623 ) ,
+ .p2604 ( optlc_net_2624 ) , .p2605 ( optlc_net_2625 ) ,
+ .p2606 ( optlc_net_2626 ) , .p2607 ( optlc_net_2627 ) ,
+ .p2608 ( optlc_net_2628 ) , .p2609 ( optlc_net_2629 ) ,
+ .p2610 ( optlc_net_2630 ) , .p2611 ( optlc_net_2631 ) ,
+ .p2612 ( optlc_net_2632 ) , .p2613 ( optlc_net_2633 ) ,
+ .p2614 ( optlc_net_2634 ) , .p2615 ( optlc_net_2635 ) ,
+ .p2616 ( optlc_net_2636 ) , .p2617 ( optlc_net_2637 ) ,
+ .p2618 ( optlc_net_2638 ) , .p2619 ( optlc_net_2639 ) ,
+ .p2620 ( optlc_net_2640 ) , .p2621 ( optlc_net_2641 ) ,
+ .p2622 ( optlc_net_2642 ) , .p2623 ( optlc_net_2643 ) ,
+ .p2624 ( optlc_net_2644 ) , .p2625 ( optlc_net_2645 ) ,
+ .p2626 ( optlc_net_2646 ) , .p2627 ( optlc_net_2647 ) ,
+ .p2628 ( optlc_net_2648 ) , .p2629 ( optlc_net_2649 ) ,
+ .p2630 ( optlc_net_2650 ) , .p2631 ( optlc_net_2651 ) ,
+ .p2632 ( optlc_net_2652 ) , .p2633 ( optlc_net_2653 ) ,
+ .p2634 ( optlc_net_2654 ) , .p2635 ( optlc_net_2655 ) ,
+ .p2636 ( optlc_net_2656 ) , .p2637 ( optlc_net_2657 ) ,
+ .p2638 ( optlc_net_2658 ) , .p2639 ( optlc_net_2659 ) ,
+ .p2640 ( optlc_net_2660 ) , .p2641 ( optlc_net_2661 ) ,
+ .p2642 ( optlc_net_2662 ) , .p2643 ( optlc_net_2663 ) ,
+ .p2644 ( optlc_net_2664 ) , .p2645 ( optlc_net_2665 ) ,
+ .p2646 ( optlc_net_2666 ) , .p2647 ( optlc_net_2667 ) ,
+ .p2648 ( optlc_net_2668 ) , .p2649 ( optlc_net_2669 ) ,
+ .p2650 ( optlc_net_2670 ) , .p2651 ( optlc_net_2671 ) ,
+ .p2652 ( optlc_net_2672 ) , .p2653 ( optlc_net_2673 ) ,
+ .p2654 ( optlc_net_2674 ) , .p2655 ( optlc_net_2675 ) ,
+ .p2656 ( optlc_net_2676 ) , .p2657 ( optlc_net_2677 ) ,
+ .p2658 ( optlc_net_2678 ) , .p2659 ( optlc_net_2679 ) ,
+ .p2660 ( optlc_net_2680 ) , .p2661 ( optlc_net_2681 ) ,
+ .p2662 ( optlc_net_2682 ) , .p2663 ( optlc_net_2683 ) ,
+ .p2664 ( optlc_net_2684 ) , .p2665 ( optlc_net_2685 ) ,
+ .p2666 ( optlc_net_2686 ) , .p2667 ( optlc_net_2687 ) ,
+ .p2668 ( optlc_net_2688 ) , .p2669 ( optlc_net_2689 ) ,
+ .p2670 ( optlc_net_2690 ) , .p2671 ( optlc_net_2691 ) ,
+ .p2672 ( optlc_net_2692 ) , .p2673 ( optlc_net_2693 ) ,
+ .p2674 ( optlc_net_2694 ) , .p2675 ( optlc_net_2695 ) ,
+ .p2676 ( optlc_net_2696 ) , .p2677 ( optlc_net_2697 ) ,
+ .p2678 ( optlc_net_2698 ) , .p2679 ( optlc_net_2699 ) ,
+ .p2680 ( optlc_net_2700 ) , .p2681 ( optlc_net_2701 ) ,
+ .p2682 ( optlc_net_2702 ) , .p2683 ( optlc_net_2703 ) ,
+ .p2684 ( optlc_net_2704 ) , .p2685 ( optlc_net_2705 ) ,
+ .p2686 ( optlc_net_2706 ) , .p2687 ( optlc_net_2707 ) ,
+ .p2688 ( optlc_net_2708 ) , .p2689 ( optlc_net_2709 ) ,
+ .p2690 ( optlc_net_2710 ) , .p2691 ( optlc_net_2711 ) ,
+ .p2692 ( optlc_net_2712 ) , .p2693 ( optlc_net_2713 ) ,
+ .p2694 ( optlc_net_2714 ) , .p2695 ( optlc_net_2715 ) ,
+ .p2696 ( optlc_net_2716 ) , .p2697 ( optlc_net_2717 ) ,
+ .p2698 ( optlc_net_2718 ) , .p2699 ( optlc_net_2719 ) ,
+ .p2700 ( optlc_net_2720 ) , .p2701 ( optlc_net_2721 ) ,
+ .p2702 ( optlc_net_2722 ) , .p2703 ( optlc_net_2723 ) ,
+ .p2704 ( optlc_net_2724 ) , .p2705 ( optlc_net_2725 ) ,
+ .p2706 ( optlc_net_2726 ) , .p2707 ( optlc_net_2727 ) ,
+ .p2708 ( optlc_net_2728 ) , .p2709 ( optlc_net_2729 ) ,
+ .p2710 ( optlc_net_2730 ) , .p2711 ( optlc_net_2731 ) ,
+ .p2712 ( optlc_net_2732 ) , .p2713 ( optlc_net_2733 ) ,
+ .p2714 ( optlc_net_2734 ) , .p2715 ( optlc_net_2735 ) ,
+ .p2716 ( optlc_net_2736 ) , .p2717 ( optlc_net_2737 ) ,
+ .p2718 ( optlc_net_2738 ) , .p2719 ( optlc_net_2739 ) ,
+ .p2720 ( optlc_net_2740 ) , .p2721 ( optlc_net_2741 ) ,
+ .p2722 ( optlc_net_2742 ) , .p2723 ( optlc_net_2743 ) ,
+ .p2724 ( optlc_net_2744 ) , .p2725 ( optlc_net_2745 ) ,
+ .p2726 ( optlc_net_2746 ) , .p2727 ( optlc_net_2747 ) ,
+ .p2728 ( optlc_net_2748 ) , .p2729 ( optlc_net_2749 ) ,
+ .p2730 ( optlc_net_2750 ) , .p2731 ( optlc_net_2751 ) ,
+ .p2732 ( optlc_net_2752 ) , .p2733 ( optlc_net_2753 ) ,
+ .p2734 ( optlc_net_2754 ) , .p2735 ( optlc_net_2755 ) ,
+ .p2736 ( optlc_net_2756 ) , .p2737 ( optlc_net_2757 ) ,
+ .p2738 ( optlc_net_2758 ) , .p2739 ( optlc_net_2759 ) ,
+ .p2740 ( optlc_net_2760 ) , .p2741 ( optlc_net_2761 ) ,
+ .p2742 ( optlc_net_2762 ) , .p2743 ( optlc_net_2763 ) ,
+ .p2744 ( optlc_net_2764 ) , .p2745 ( optlc_net_2765 ) ,
+ .p2746 ( optlc_net_2766 ) , .p2747 ( optlc_net_2767 ) ,
+ .p2748 ( optlc_net_2768 ) , .p2749 ( optlc_net_2769 ) ,
+ .p2750 ( optlc_net_2770 ) , .p2751 ( optlc_net_2771 ) ,
+ .p2752 ( optlc_net_2772 ) , .p2753 ( optlc_net_2773 ) ,
+ .p2754 ( optlc_net_2774 ) , .p2755 ( optlc_net_2775 ) ,
+ .p2756 ( optlc_net_2776 ) , .p2757 ( optlc_net_2777 ) ,
+ .p2758 ( optlc_net_2778 ) , .p2759 ( optlc_net_2779 ) ,
+ .p2760 ( optlc_net_2780 ) , .p2761 ( optlc_net_2781 ) ,
+ .p2762 ( optlc_net_2782 ) , .p2763 ( optlc_net_2783 ) ,
+ .p2764 ( optlc_net_2784 ) , .p2765 ( optlc_net_2785 ) ,
+ .p2766 ( optlc_net_2786 ) , .p2767 ( optlc_net_2787 ) ,
+ .p2768 ( optlc_net_2788 ) , .p2769 ( optlc_net_2789 ) ,
+ .p2770 ( optlc_net_2790 ) , .p2771 ( optlc_net_2791 ) ,
+ .p2772 ( optlc_net_2792 ) , .p2773 ( optlc_net_2793 ) ,
+ .p2774 ( optlc_net_2794 ) , .p2775 ( optlc_net_2795 ) ,
+ .p2776 ( optlc_net_2796 ) , .p2777 ( optlc_net_2797 ) ,
+ .p2778 ( optlc_net_2798 ) , .p2779 ( optlc_net_2799 ) ,
+ .p2780 ( optlc_net_2800 ) , .p2781 ( optlc_net_2801 ) ,
+ .p2782 ( optlc_net_2802 ) , .p2783 ( optlc_net_2803 ) ,
+ .p2784 ( optlc_net_2804 ) , .p2785 ( optlc_net_2805 ) ,
+ .p2786 ( optlc_net_2806 ) , .p2787 ( optlc_net_2807 ) ,
+ .p2788 ( optlc_net_2808 ) , .p2789 ( optlc_net_2809 ) ,
+ .p2790 ( optlc_net_2810 ) , .p2791 ( optlc_net_2811 ) ,
+ .p2792 ( optlc_net_2812 ) , .p2793 ( optlc_net_2813 ) ,
+ .p2794 ( optlc_net_2814 ) , .p2795 ( optlc_net_2815 ) ,
+ .p2796 ( optlc_net_2816 ) , .p2797 ( optlc_net_2817 ) ,
+ .p2798 ( optlc_net_2818 ) , .p2799 ( optlc_net_2819 ) ,
+ .p2800 ( optlc_net_2820 ) , .p2801 ( optlc_net_2821 ) ,
+ .p2802 ( optlc_net_2822 ) , .p2803 ( optlc_net_2823 ) ,
+ .p2804 ( optlc_net_2824 ) , .p2805 ( optlc_net_2825 ) ,
+ .p2806 ( optlc_net_2826 ) , .p2807 ( optlc_net_2827 ) ,
+ .p2808 ( optlc_net_2828 ) , .p2809 ( optlc_net_2829 ) ,
+ .p2810 ( optlc_net_2830 ) , .p2811 ( optlc_net_2831 ) ,
+ .p2812 ( optlc_net_2832 ) , .p2813 ( optlc_net_2833 ) ,
+ .p2814 ( optlc_net_2834 ) , .p2815 ( optlc_net_2835 ) ,
+ .p2816 ( optlc_net_2836 ) , .p2817 ( optlc_net_2837 ) ,
+ .p2818 ( optlc_net_2838 ) , .p2819 ( optlc_net_2839 ) ,
+ .p2820 ( optlc_net_2840 ) , .p2821 ( optlc_net_2841 ) ,
+ .p2822 ( optlc_net_2842 ) , .p2823 ( optlc_net_2843 ) ,
+ .p2824 ( optlc_net_2844 ) , .p2825 ( optlc_net_2845 ) ,
+ .p2826 ( optlc_net_2846 ) , .p2827 ( optlc_net_2847 ) ,
+ .p2828 ( optlc_net_2848 ) , .p2829 ( optlc_net_2849 ) ,
+ .p2830 ( optlc_net_2850 ) , .p2831 ( optlc_net_2851 ) ,
+ .p2832 ( optlc_net_2852 ) , .p2833 ( optlc_net_2853 ) ,
+ .p2834 ( optlc_net_2854 ) , .p2835 ( optlc_net_2855 ) ,
+ .p2836 ( optlc_net_2856 ) , .p2837 ( optlc_net_2857 ) ,
+ .p2838 ( optlc_net_2858 ) , .p2839 ( optlc_net_2859 ) ,
+ .p2840 ( optlc_net_2860 ) , .p2841 ( optlc_net_2861 ) ,
+ .p2842 ( optlc_net_2862 ) , .p2843 ( optlc_net_2863 ) ,
+ .p2844 ( optlc_net_2864 ) , .p2845 ( optlc_net_2865 ) ,
+ .p2846 ( optlc_net_2866 ) , .p2847 ( optlc_net_2867 ) ,
+ .p2848 ( optlc_net_2868 ) , .p2849 ( optlc_net_2869 ) ,
+ .p2850 ( optlc_net_2870 ) , .p2851 ( optlc_net_2871 ) ,
+ .p2852 ( optlc_net_2872 ) , .p2853 ( optlc_net_2873 ) ,
+ .p2854 ( optlc_net_2874 ) , .p2855 ( optlc_net_2875 ) ,
+ .p2856 ( optlc_net_2876 ) , .p2857 ( optlc_net_2877 ) ,
+ .p2858 ( optlc_net_2878 ) , .p2859 ( optlc_net_2879 ) ,
+ .p2860 ( optlc_net_2880 ) , .p2861 ( optlc_net_2881 ) ,
+ .p2862 ( optlc_net_2882 ) , .p2863 ( optlc_net_2883 ) ,
+ .p2864 ( optlc_net_2884 ) , .p2865 ( optlc_net_2885 ) ,
+ .p2866 ( optlc_net_2886 ) , .p2867 ( optlc_net_2887 ) ,
+ .p2868 ( optlc_net_2888 ) , .p2869 ( optlc_net_2889 ) ,
+ .p2870 ( optlc_net_2890 ) , .p2871 ( optlc_net_2891 ) ,
+ .p2872 ( optlc_net_2892 ) , .p2873 ( optlc_net_2893 ) ,
+ .p2874 ( optlc_net_2894 ) , .p2875 ( optlc_net_2895 ) ,
+ .p2876 ( optlc_net_2896 ) , .p2877 ( optlc_net_2897 ) ,
+ .p2878 ( optlc_net_2898 ) , .p2879 ( optlc_net_2899 ) ,
+ .p2880 ( optlc_net_2900 ) , .p2881 ( optlc_net_2901 ) ,
+ .p2882 ( optlc_net_2902 ) , .p2883 ( optlc_net_2903 ) ,
+ .p2884 ( optlc_net_2904 ) , .p2885 ( optlc_net_2905 ) ,
+ .p2886 ( optlc_net_2906 ) , .p2887 ( optlc_net_2907 ) ,
+ .p2888 ( optlc_net_2908 ) , .p2889 ( optlc_net_2909 ) ,
+ .p2890 ( optlc_net_2910 ) , .p2891 ( optlc_net_2911 ) ,
+ .p2892 ( optlc_net_2912 ) , .p2893 ( optlc_net_2913 ) ,
+ .p2894 ( optlc_net_2914 ) , .p2895 ( optlc_net_2915 ) ,
+ .p2896 ( optlc_net_2916 ) , .p2897 ( optlc_net_2917 ) ,
+ .p2898 ( optlc_net_2918 ) , .p2899 ( optlc_net_2919 ) ,
+ .p2900 ( optlc_net_2920 ) , .p2901 ( optlc_net_2921 ) ,
+ .p2902 ( optlc_net_2922 ) , .p2903 ( optlc_net_2923 ) ,
+ .p2904 ( optlc_net_2924 ) , .p2905 ( optlc_net_2925 ) ,
+ .p2906 ( optlc_net_2926 ) , .p2907 ( optlc_net_2927 ) ,
+ .p2908 ( optlc_net_2928 ) , .p2909 ( optlc_net_2929 ) ,
+ .p2910 ( optlc_net_2930 ) , .p2911 ( optlc_net_2931 ) ,
+ .p2912 ( optlc_net_2932 ) , .p2913 ( optlc_net_2933 ) ,
+ .p2914 ( optlc_net_2934 ) , .p2915 ( optlc_net_2935 ) ,
+ .p2916 ( optlc_net_2936 ) , .p2917 ( optlc_net_2937 ) ,
+ .p2918 ( optlc_net_2938 ) , .p2919 ( optlc_net_2939 ) ,
+ .p2920 ( optlc_net_2940 ) , .p2921 ( optlc_net_2941 ) ,
+ .p2922 ( optlc_net_2942 ) , .p2923 ( optlc_net_2943 ) ,
+ .p2924 ( optlc_net_2944 ) , .p2925 ( optlc_net_2945 ) ,
+ .p2926 ( optlc_net_2946 ) , .p2927 ( optlc_net_2947 ) ,
+ .p2928 ( optlc_net_2948 ) , .p2929 ( optlc_net_2949 ) ,
+ .p2930 ( optlc_net_2950 ) , .p2931 ( optlc_net_2951 ) ,
+ .p2932 ( optlc_net_2952 ) , .p2933 ( optlc_net_2953 ) ,
+ .p2934 ( optlc_net_2954 ) , .p2935 ( optlc_net_2955 ) ,
+ .p2936 ( optlc_net_2956 ) , .p2937 ( optlc_net_2957 ) ,
+ .p2938 ( optlc_net_2958 ) , .p2939 ( optlc_net_2959 ) ,
+ .p2940 ( optlc_net_2960 ) , .p2941 ( optlc_net_2961 ) ,
+ .p2942 ( optlc_net_2962 ) , .p2943 ( optlc_net_2963 ) ,
+ .p2944 ( optlc_net_2964 ) , .p2945 ( optlc_net_2965 ) ,
+ .p2946 ( optlc_net_2966 ) , .p2947 ( optlc_net_2967 ) ,
+ .p2948 ( optlc_net_2968 ) , .p2949 ( optlc_net_2969 ) ,
+ .p2950 ( optlc_net_2970 ) , .p2951 ( optlc_net_2971 ) ,
+ .p2952 ( optlc_net_2972 ) , .p2953 ( optlc_net_2973 ) ,
+ .p2954 ( optlc_net_2974 ) , .p2955 ( optlc_net_2975 ) ,
+ .p2956 ( optlc_net_2976 ) , .p2957 ( optlc_net_2977 ) ,
+ .p2958 ( optlc_net_2978 ) , .p2959 ( optlc_net_2979 ) ,
+ .p2960 ( optlc_net_2980 ) , .p2961 ( optlc_net_2981 ) ,
+ .p2962 ( optlc_net_2982 ) , .p2963 ( optlc_net_2983 ) ,
+ .p2964 ( optlc_net_2984 ) , .p2965 ( optlc_net_2985 ) ,
+ .p2966 ( optlc_net_2986 ) , .p2967 ( optlc_net_2987 ) ,
+ .p2968 ( optlc_net_2988 ) , .p2969 ( optlc_net_2989 ) ,
+ .p2970 ( optlc_net_2990 ) , .p2971 ( optlc_net_2991 ) ,
+ .p2972 ( optlc_net_2992 ) , .p2973 ( optlc_net_2993 ) ,
+ .p2974 ( optlc_net_2994 ) , .p2975 ( optlc_net_2995 ) ,
+ .p2976 ( optlc_net_2996 ) , .p2977 ( optlc_net_2997 ) ,
+ .p2978 ( optlc_net_2998 ) , .p2979 ( optlc_net_2999 ) ,
+ .p2980 ( optlc_net_3000 ) , .p2981 ( optlc_net_3001 ) ,
+ .p2982 ( optlc_net_3002 ) , .p2983 ( optlc_net_3003 ) ,
+ .p2984 ( optlc_net_3004 ) , .p2985 ( optlc_net_3005 ) ,
+ .p2986 ( optlc_net_3006 ) , .p2987 ( optlc_net_3007 ) ,
+ .p2988 ( optlc_net_3008 ) , .p2989 ( optlc_net_3009 ) ,
+ .p2990 ( optlc_net_3010 ) , .p2991 ( optlc_net_3011 ) ,
+ .p2992 ( optlc_net_3012 ) , .p2993 ( optlc_net_3013 ) ,
+ .p2994 ( optlc_net_3014 ) , .p2995 ( optlc_net_3015 ) ,
+ .p2996 ( optlc_net_3016 ) , .p2997 ( optlc_net_3017 ) ,
+ .p2998 ( optlc_net_3018 ) , .p2999 ( optlc_net_3019 ) ,
+ .p3000 ( optlc_net_3020 ) , .p3001 ( optlc_net_3021 ) ,
+ .p3002 ( optlc_net_3022 ) , .p3003 ( optlc_net_3023 ) ,
+ .p3004 ( optlc_net_3024 ) , .p3005 ( optlc_net_3025 ) ,
+ .p3006 ( optlc_net_3026 ) , .p3007 ( optlc_net_3027 ) ,
+ .p3008 ( optlc_net_3028 ) , .p3009 ( optlc_net_3029 ) ,
+ .p3010 ( optlc_net_3030 ) , .p3011 ( optlc_net_3031 ) ,
+ .p3012 ( optlc_net_3032 ) , .p3013 ( optlc_net_3033 ) ,
+ .p3014 ( optlc_net_3034 ) , .p3015 ( optlc_net_3035 ) ,
+ .p3016 ( optlc_net_3036 ) , .p3017 ( optlc_net_3037 ) ,
+ .p3018 ( optlc_net_3038 ) , .p3019 ( optlc_net_3039 ) ,
+ .p3020 ( optlc_net_3040 ) , .p3021 ( optlc_net_3041 ) ,
+ .p3022 ( optlc_net_3042 ) , .p3023 ( optlc_net_3043 ) ,
+ .p3024 ( optlc_net_3044 ) , .p3025 ( optlc_net_3045 ) ,
+ .p3026 ( optlc_net_3046 ) , .p3027 ( optlc_net_3047 ) ,
+ .p3028 ( optlc_net_3048 ) , .p3029 ( optlc_net_3049 ) ,
+ .p3030 ( optlc_net_3050 ) , .p3031 ( optlc_net_3051 ) ,
+ .p3032 ( optlc_net_3052 ) , .p3033 ( optlc_net_3053 ) ,
+ .p3034 ( optlc_net_3054 ) , .p3035 ( optlc_net_3055 ) ,
+ .p3036 ( optlc_net_3056 ) , .p3037 ( optlc_net_3057 ) ,
+ .p3038 ( optlc_net_3058 ) , .p3039 ( optlc_net_3059 ) ,
+ .p3040 ( optlc_net_3060 ) , .p3041 ( optlc_net_3061 ) ,
+ .p3042 ( optlc_net_3062 ) , .p3043 ( optlc_net_3063 ) ,
+ .p3044 ( optlc_net_3064 ) , .p3045 ( optlc_net_3065 ) ,
+ .p3046 ( optlc_net_3066 ) , .p3047 ( optlc_net_3067 ) ,
+ .p3048 ( optlc_net_3068 ) , .p3049 ( optlc_net_3069 ) ,
+ .p3050 ( optlc_net_3070 ) , .p3051 ( optlc_net_3071 ) ,
+ .p3052 ( optlc_net_3072 ) , .p3053 ( optlc_net_3073 ) ,
+ .p3054 ( optlc_net_3074 ) , .p3055 ( optlc_net_3075 ) ,
+ .p3056 ( optlc_net_3076 ) , .p3057 ( optlc_net_3077 ) ,
+ .p3058 ( optlc_net_3078 ) , .p3059 ( optlc_net_3079 ) ,
+ .p3060 ( optlc_net_3080 ) , .p3061 ( optlc_net_3081 ) ,
+ .p3062 ( optlc_net_3082 ) , .p3063 ( optlc_net_3083 ) ,
+ .p3064 ( optlc_net_3084 ) , .p3065 ( optlc_net_3085 ) ,
+ .p3066 ( optlc_net_3086 ) , .p3067 ( optlc_net_3087 ) ,
+ .p3068 ( optlc_net_3088 ) , .p3069 ( optlc_net_3089 ) ,
+ .p3070 ( optlc_net_3090 ) , .p3071 ( optlc_net_3091 ) ,
+ .p3072 ( optlc_net_3092 ) , .p3073 ( optlc_net_3093 ) ,
+ .p3074 ( optlc_net_3094 ) , .p3075 ( optlc_net_3095 ) ,
+ .p3076 ( optlc_net_3096 ) , .p3077 ( optlc_net_3097 ) ,
+ .p3078 ( optlc_net_3098 ) , .p3079 ( optlc_net_3099 ) ,
+ .p3080 ( optlc_net_3100 ) , .p3081 ( optlc_net_3101 ) ,
+ .p3082 ( optlc_net_3102 ) , .p3083 ( optlc_net_3103 ) ,
+ .p3084 ( optlc_net_3104 ) , .p3085 ( optlc_net_3105 ) ,
+ .p3086 ( optlc_net_3106 ) , .p3087 ( optlc_net_3107 ) ,
+ .p3088 ( optlc_net_3108 ) , .p3089 ( optlc_net_3109 ) ,
+ .p3090 ( optlc_net_3110 ) , .p3091 ( optlc_net_3111 ) ,
+ .p3092 ( optlc_net_3112 ) , .p3093 ( optlc_net_3113 ) ,
+ .p3094 ( optlc_net_3114 ) , .p3095 ( optlc_net_3115 ) ,
+ .p3096 ( optlc_net_3116 ) , .p3097 ( optlc_net_3117 ) ,
+ .p3098 ( optlc_net_3118 ) , .p3099 ( optlc_net_3119 ) ,
+ .p3100 ( optlc_net_3120 ) , .p3101 ( optlc_net_3121 ) ,
+ .p3102 ( optlc_net_3122 ) , .p3103 ( optlc_net_3123 ) ,
+ .p3104 ( optlc_net_3124 ) , .p3105 ( optlc_net_3125 ) ,
+ .p3106 ( optlc_net_3126 ) , .p3107 ( optlc_net_3127 ) ,
+ .p3108 ( optlc_net_3128 ) , .p3109 ( optlc_net_3129 ) ,
+ .p3110 ( optlc_net_3130 ) , .p3111 ( optlc_net_3131 ) ,
+ .p3112 ( optlc_net_3132 ) , .p3113 ( optlc_net_3133 ) ,
+ .p3114 ( optlc_net_3134 ) , .p3115 ( optlc_net_3135 ) ,
+ .p3116 ( optlc_net_3136 ) , .p3117 ( optlc_net_3137 ) ,
+ .p3118 ( optlc_net_3138 ) , .p3119 ( optlc_net_3139 ) ,
+ .p3120 ( optlc_net_3140 ) , .p3121 ( optlc_net_3141 ) ,
+ .p3122 ( optlc_net_3142 ) , .p3123 ( optlc_net_3143 ) ,
+ .p3124 ( optlc_net_3144 ) , .p3125 ( optlc_net_3145 ) ,
+ .p3126 ( optlc_net_3146 ) , .p3127 ( optlc_net_3147 ) ,
+ .p3128 ( optlc_net_3148 ) , .p3129 ( optlc_net_3149 ) ,
+ .p3130 ( optlc_net_3150 ) , .p3131 ( optlc_net_3151 ) ,
+ .p3132 ( optlc_net_3152 ) , .p3133 ( optlc_net_3153 ) ,
+ .p3134 ( optlc_net_3154 ) , .p3135 ( optlc_net_3155 ) ,
+ .p3136 ( optlc_net_3156 ) , .p3137 ( optlc_net_3157 ) ,
+ .p3138 ( optlc_net_3158 ) , .p3139 ( optlc_net_3159 ) ,
+ .p3140 ( optlc_net_3160 ) , .p3141 ( optlc_net_3161 ) ,
+ .p3142 ( optlc_net_3162 ) , .p3143 ( optlc_net_3163 ) ,
+ .p3144 ( optlc_net_3164 ) , .p3145 ( optlc_net_3165 ) ,
+ .p3146 ( optlc_net_3166 ) , .p3147 ( optlc_net_3167 ) ,
+ .p3148 ( optlc_net_3168 ) , .p3149 ( optlc_net_3169 ) ,
+ .p3150 ( optlc_net_3170 ) , .p3151 ( optlc_net_3171 ) ,
+ .p3152 ( optlc_net_3172 ) , .p3153 ( optlc_net_3173 ) ,
+ .p3154 ( optlc_net_3174 ) , .p3155 ( optlc_net_3175 ) ,
+ .p3156 ( optlc_net_3176 ) , .p3157 ( optlc_net_3177 ) ,
+ .p3158 ( optlc_net_3178 ) , .p3159 ( optlc_net_3179 ) ,
+ .p3160 ( optlc_net_3180 ) , .p3161 ( optlc_net_3181 ) ,
+ .p3162 ( optlc_net_3182 ) , .p3163 ( optlc_net_3183 ) ,
+ .p3164 ( optlc_net_3184 ) , .p3165 ( optlc_net_3185 ) ,
+ .p3166 ( optlc_net_3186 ) , .p3167 ( optlc_net_3187 ) ,
+ .p3168 ( optlc_net_3188 ) , .p3169 ( optlc_net_3189 ) ,
+ .p3170 ( optlc_net_3190 ) , .p3171 ( optlc_net_3191 ) ,
+ .p3172 ( optlc_net_3192 ) , .p3173 ( optlc_net_3193 ) ,
+ .p3174 ( optlc_net_3194 ) , .p3175 ( optlc_net_3195 ) ,
+ .p3176 ( optlc_net_3196 ) , .p3177 ( optlc_net_3197 ) ,
+ .p3178 ( optlc_net_3198 ) , .p3179 ( optlc_net_3199 ) ,
+ .p3180 ( optlc_net_3200 ) , .p3181 ( optlc_net_3201 ) ,
+ .p3182 ( optlc_net_3202 ) , .p3183 ( optlc_net_3203 ) ,
+ .p3184 ( optlc_net_3204 ) , .p3185 ( optlc_net_3205 ) ,
+ .p3186 ( optlc_net_3206 ) , .p3187 ( optlc_net_3207 ) ,
+ .p3188 ( optlc_net_3208 ) , .p3189 ( optlc_net_3209 ) ,
+ .p3190 ( optlc_net_3210 ) , .p3191 ( optlc_net_3211 ) ,
+ .p3192 ( optlc_net_3212 ) , .p3193 ( optlc_net_3213 ) ,
+ .p3194 ( optlc_net_3214 ) , .p3195 ( optlc_net_3215 ) ,
+ .p3196 ( optlc_net_3216 ) , .p3197 ( optlc_net_3217 ) ,
+ .p3198 ( optlc_net_3218 ) , .p3199 ( optlc_net_3219 ) ,
+ .p3200 ( optlc_net_3220 ) , .p3201 ( optlc_net_3221 ) ,
+ .p3202 ( optlc_net_3222 ) , .p3203 ( optlc_net_3223 ) ,
+ .p3204 ( optlc_net_3224 ) , .p3205 ( optlc_net_3225 ) ,
+ .p3206 ( optlc_net_3226 ) , .p3207 ( optlc_net_3227 ) ,
+ .p3208 ( optlc_net_3228 ) , .p3209 ( optlc_net_3229 ) ,
+ .p3210 ( optlc_net_3230 ) , .p3211 ( optlc_net_3231 ) ,
+ .p3212 ( optlc_net_3232 ) , .p3213 ( optlc_net_3233 ) ,
+ .p3214 ( optlc_net_3234 ) , .p3215 ( optlc_net_3235 ) ,
+ .p3216 ( optlc_net_3236 ) , .p3217 ( optlc_net_3237 ) ,
+ .p3218 ( optlc_net_3238 ) , .p3219 ( optlc_net_3239 ) ,
+ .p3220 ( optlc_net_3240 ) , .p3221 ( optlc_net_3241 ) ,
+ .p3222 ( optlc_net_3242 ) , .p3223 ( optlc_net_3243 ) ,
+ .p3224 ( optlc_net_3244 ) , .p3225 ( optlc_net_3245 ) ,
+ .p3226 ( optlc_net_3246 ) , .p3227 ( optlc_net_3247 ) ,
+ .p3228 ( optlc_net_3248 ) , .p3229 ( optlc_net_3249 ) ,
+ .p3230 ( optlc_net_3250 ) , .p3231 ( optlc_net_3251 ) ,
+ .p3232 ( optlc_net_3252 ) , .p3233 ( optlc_net_3253 ) ,
+ .p3234 ( optlc_net_3254 ) , .p3235 ( optlc_net_3255 ) ,
+ .p3236 ( optlc_net_3256 ) , .p3237 ( optlc_net_3257 ) ,
+ .p3238 ( optlc_net_3258 ) , .p3239 ( optlc_net_3259 ) ,
+ .p3240 ( optlc_net_3260 ) , .p3241 ( optlc_net_3261 ) ,
+ .p3242 ( optlc_net_3262 ) , .p3243 ( optlc_net_3263 ) ,
+ .p3244 ( optlc_net_3264 ) , .p3245 ( optlc_net_3265 ) ,
+ .p3246 ( optlc_net_3266 ) , .p3247 ( optlc_net_3267 ) ,
+ .p3248 ( optlc_net_3268 ) , .p3249 ( optlc_net_3269 ) ,
+ .p3250 ( optlc_net_3270 ) , .p3251 ( optlc_net_3271 ) ,
+ .p3252 ( optlc_net_3272 ) , .p3253 ( optlc_net_3273 ) ,
+ .p3254 ( optlc_net_3274 ) , .p3255 ( optlc_net_3275 ) ,
+ .p3256 ( optlc_net_3276 ) , .p3257 ( optlc_net_3277 ) ,
+ .p3258 ( optlc_net_3278 ) , .p3259 ( optlc_net_3279 ) ,
+ .p3260 ( optlc_net_3280 ) , .p3261 ( optlc_net_3281 ) ,
+ .p3262 ( optlc_net_3282 ) , .p3263 ( optlc_net_3283 ) ,
+ .p3264 ( optlc_net_3284 ) , .p3265 ( optlc_net_3285 ) ,
+ .p3266 ( optlc_net_3286 ) , .p3267 ( optlc_net_3287 ) ,
+ .p3268 ( optlc_net_3288 ) , .p3269 ( optlc_net_3289 ) ,
+ .p3270 ( optlc_net_3290 ) , .p3271 ( optlc_net_3291 ) ,
+ .p3272 ( optlc_net_3292 ) , .p3273 ( optlc_net_3293 ) ,
+ .p3274 ( optlc_net_3294 ) , .p3275 ( optlc_net_3295 ) ,
+ .p3276 ( optlc_net_3296 ) , .p3277 ( optlc_net_3297 ) ,
+ .p3278 ( optlc_net_3298 ) , .p3279 ( optlc_net_3299 ) ,
+ .p3280 ( optlc_net_3300 ) , .p3281 ( optlc_net_3301 ) ,
+ .p3282 ( optlc_net_3302 ) , .p3283 ( optlc_net_3303 ) ,
+ .p3284 ( optlc_net_3304 ) , .p3285 ( optlc_net_3305 ) ,
+ .p3286 ( optlc_net_3306 ) , .p3287 ( optlc_net_3307 ) ,
+ .p3288 ( optlc_net_3308 ) , .p3289 ( optlc_net_3309 ) ,
+ .p3290 ( optlc_net_3310 ) , .p3291 ( optlc_net_3311 ) ,
+ .p3292 ( optlc_net_3312 ) , .p3293 ( optlc_net_3313 ) ,
+ .p3294 ( optlc_net_3314 ) , .p3295 ( optlc_net_3315 ) ,
+ .p3296 ( optlc_net_3316 ) , .p3297 ( optlc_net_3317 ) ,
+ .p3298 ( optlc_net_3318 ) , .p3299 ( optlc_net_3319 ) ,
+ .p3300 ( optlc_net_3320 ) , .p3301 ( optlc_net_3321 ) ,
+ .p3302 ( optlc_net_3322 ) , .p3303 ( optlc_net_3323 ) ,
+ .p3304 ( optlc_net_3324 ) , .p3305 ( optlc_net_3325 ) ,
+ .p3306 ( optlc_net_3326 ) , .p3307 ( optlc_net_3327 ) ,
+ .p3308 ( optlc_net_3328 ) , .p3309 ( optlc_net_3329 ) ,
+ .p3310 ( optlc_net_3330 ) , .p3311 ( optlc_net_3331 ) ,
+ .p3312 ( optlc_net_3332 ) , .p3313 ( optlc_net_3333 ) ,
+ .p3314 ( optlc_net_3334 ) , .p3315 ( optlc_net_3335 ) ,
+ .p3316 ( optlc_net_3336 ) , .p3317 ( optlc_net_3337 ) ,
+ .p3318 ( optlc_net_3338 ) , .p3319 ( optlc_net_3339 ) ,
+ .p3320 ( optlc_net_3340 ) , .p3321 ( optlc_net_3341 ) ,
+ .p3322 ( optlc_net_3342 ) , .p3323 ( optlc_net_3343 ) ,
+ .p3324 ( optlc_net_3344 ) , .p3325 ( optlc_net_3345 ) ,
+ .p3326 ( optlc_net_3346 ) , .p3327 ( optlc_net_3347 ) ,
+ .p3328 ( optlc_net_3348 ) , .p3329 ( optlc_net_3349 ) ,
+ .p3330 ( optlc_net_3350 ) , .p3331 ( optlc_net_3351 ) ,
+ .p3332 ( optlc_net_3352 ) , .p3333 ( optlc_net_3353 ) ,
+ .p3334 ( optlc_net_3354 ) , .p3335 ( optlc_net_3355 ) ,
+ .p3336 ( optlc_net_3356 ) , .p3337 ( optlc_net_3357 ) ,
+ .p3338 ( optlc_net_3358 ) , .p3339 ( optlc_net_3359 ) ,
+ .p3340 ( optlc_net_3360 ) , .p3341 ( optlc_net_3361 ) ,
+ .p3342 ( optlc_net_3362 ) , .p3343 ( optlc_net_3363 ) ,
+ .p3344 ( optlc_net_3364 ) , .p3345 ( optlc_net_3365 ) ,
+ .p3346 ( optlc_net_3366 ) , .p3347 ( optlc_net_3367 ) ,
+ .p3348 ( optlc_net_3368 ) , .p3349 ( optlc_net_3369 ) ,
+ .p3350 ( optlc_net_3370 ) , .p3351 ( optlc_net_3371 ) ,
+ .p3352 ( optlc_net_3372 ) , .p3353 ( optlc_net_3373 ) ,
+ .p3354 ( optlc_net_3374 ) , .p3355 ( optlc_net_3375 ) ,
+ .p3356 ( optlc_net_3376 ) , .p3357 ( optlc_net_3377 ) ,
+ .p3358 ( optlc_net_3378 ) , .p3359 ( optlc_net_3379 ) ,
+ .p3360 ( optlc_net_3380 ) , .p3361 ( optlc_net_3381 ) ,
+ .p3362 ( optlc_net_3382 ) , .p3363 ( optlc_net_3383 ) ,
+ .p3364 ( optlc_net_3384 ) , .p3365 ( optlc_net_3385 ) ,
+ .p3366 ( optlc_net_3386 ) , .p3367 ( optlc_net_3387 ) ,
+ .p3368 ( optlc_net_3388 ) , .p3369 ( optlc_net_3389 ) ,
+ .p3370 ( optlc_net_3390 ) , .p3371 ( optlc_net_3391 ) ,
+ .p3372 ( optlc_net_3392 ) , .p3373 ( optlc_net_3393 ) ,
+ .p3374 ( optlc_net_3394 ) , .p3375 ( optlc_net_3395 ) ,
+ .p3376 ( optlc_net_3396 ) , .p3377 ( optlc_net_3397 ) ,
+ .p3378 ( optlc_net_3398 ) , .p3379 ( optlc_net_3399 ) ,
+ .p3380 ( optlc_net_3400 ) , .p3381 ( optlc_net_3401 ) ,
+ .p3382 ( optlc_net_3402 ) , .p3383 ( optlc_net_3403 ) ,
+ .p3384 ( optlc_net_3404 ) , .p3385 ( optlc_net_3405 ) ,
+ .p3386 ( optlc_net_3406 ) , .p3387 ( optlc_net_3407 ) ,
+ .p3388 ( optlc_net_3408 ) , .p3389 ( optlc_net_3409 ) ,
+ .p3390 ( optlc_net_3410 ) , .p3391 ( optlc_net_3411 ) ,
+ .p3392 ( optlc_net_3412 ) , .p3393 ( optlc_net_3413 ) ,
+ .p3394 ( optlc_net_3414 ) , .p3395 ( optlc_net_3415 ) ,
+ .p3396 ( optlc_net_3416 ) , .p3397 ( optlc_net_3417 ) ,
+ .p3398 ( optlc_net_3418 ) , .p3399 ( optlc_net_3419 ) ,
+ .p3400 ( optlc_net_3420 ) , .p3401 ( optlc_net_3421 ) ,
+ .p3402 ( optlc_net_3422 ) , .p3403 ( optlc_net_3423 ) ,
+ .p3404 ( optlc_net_3424 ) , .p3405 ( optlc_net_3425 ) ,
+ .p3406 ( optlc_net_3426 ) , .p3407 ( optlc_net_3427 ) ,
+ .p3408 ( optlc_net_3428 ) , .p3409 ( optlc_net_3429 ) ,
+ .p3410 ( optlc_net_3430 ) , .p3411 ( optlc_net_3431 ) ,
+ .p3412 ( optlc_net_3432 ) , .p3413 ( optlc_net_3433 ) ,
+ .p3414 ( optlc_net_3434 ) , .p3415 ( optlc_net_3435 ) ,
+ .p3416 ( optlc_net_3436 ) , .p3417 ( optlc_net_3437 ) ,
+ .p3418 ( optlc_net_3438 ) , .p3419 ( optlc_net_3439 ) ,
+ .p3420 ( optlc_net_3440 ) , .p3421 ( optlc_net_3441 ) ,
+ .p3422 ( optlc_net_3442 ) , .p3423 ( optlc_net_3443 ) ,
+ .p3424 ( optlc_net_3444 ) , .p3425 ( optlc_net_3445 ) ,
+ .p3426 ( optlc_net_3446 ) , .p3427 ( optlc_net_3447 ) ,
+ .p3428 ( optlc_net_3448 ) , .p3429 ( optlc_net_3449 ) ,
+ .p3430 ( optlc_net_3450 ) , .p3431 ( optlc_net_3451 ) ,
+ .p3432 ( optlc_net_3452 ) , .p3433 ( optlc_net_3453 ) ,
+ .p3434 ( optlc_net_3454 ) , .p3435 ( optlc_net_3455 ) ,
+ .p3436 ( optlc_net_3456 ) , .p3437 ( optlc_net_3457 ) ,
+ .p3438 ( optlc_net_3458 ) , .p3439 ( optlc_net_3459 ) ,
+ .p3440 ( optlc_net_3460 ) , .p3441 ( optlc_net_3461 ) ,
+ .p3442 ( optlc_net_3462 ) , .p3443 ( optlc_net_3463 ) ,
+ .p3444 ( optlc_net_3464 ) , .p3445 ( optlc_net_3465 ) ,
+ .p3446 ( optlc_net_3466 ) , .p3447 ( optlc_net_3467 ) ,
+ .p3448 ( optlc_net_3468 ) , .p3449 ( optlc_net_3469 ) ,
+ .p3450 ( optlc_net_3470 ) , .p3451 ( optlc_net_3471 ) ,
+ .p3452 ( optlc_net_3472 ) , .p3453 ( optlc_net_3473 ) ,
+ .p3454 ( optlc_net_3474 ) , .p3455 ( optlc_net_3475 ) ,
+ .p3456 ( optlc_net_3476 ) , .p3457 ( optlc_net_3477 ) ,
+ .p3458 ( optlc_net_3478 ) , .p3459 ( optlc_net_3479 ) ,
+ .p3460 ( optlc_net_3480 ) , .p3461 ( optlc_net_3481 ) ,
+ .p3462 ( optlc_net_3482 ) , .p3463 ( optlc_net_3483 ) ,
+ .p3464 ( optlc_net_3484 ) , .p3465 ( optlc_net_3485 ) ,
+ .p3466 ( optlc_net_3486 ) , .p3467 ( optlc_net_3487 ) ,
+ .p3468 ( optlc_net_3488 ) , .p3469 ( optlc_net_3489 ) ,
+ .p3470 ( optlc_net_3490 ) , .p3471 ( optlc_net_3491 ) ,
+ .p3472 ( optlc_net_3492 ) , .p3473 ( optlc_net_3493 ) ,
+ .p3474 ( optlc_net_3494 ) , .p3475 ( optlc_net_3495 ) ,
+ .p3476 ( optlc_net_3496 ) , .p3477 ( optlc_net_3497 ) ,
+ .p3478 ( optlc_net_3498 ) , .p3479 ( optlc_net_3499 ) ,
+ .p3480 ( optlc_net_3500 ) , .p3481 ( optlc_net_3501 ) ,
+ .p3482 ( optlc_net_3502 ) , .p3483 ( optlc_net_3503 ) ,
+ .p3484 ( optlc_net_3504 ) , .p3485 ( optlc_net_3505 ) ,
+ .p3486 ( optlc_net_3506 ) , .p3487 ( optlc_net_3507 ) ,
+ .p3488 ( optlc_net_3508 ) , .p3489 ( optlc_net_3509 ) ,
+ .p3490 ( optlc_net_3510 ) , .p3491 ( optlc_net_3511 ) ,
+ .p3492 ( optlc_net_3512 ) , .p3493 ( optlc_net_3513 ) ,
+ .p3494 ( optlc_net_3514 ) , .p3495 ( optlc_net_3515 ) ,
+ .p3496 ( optlc_net_3516 ) , .p3497 ( optlc_net_3517 ) ,
+ .p3498 ( optlc_net_3518 ) , .p3499 ( optlc_net_3519 ) ,
+ .p3500 ( optlc_net_3520 ) , .p3501 ( optlc_net_3521 ) ,
+ .p3502 ( optlc_net_3522 ) , .p3503 ( optlc_net_3523 ) ,
+ .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) ,
+ .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) ,
+ .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) ,
+ .p3510 ( optlc_net_3530 ) , .p3511 ( optlc_net_3531 ) ,
+ .p3512 ( optlc_net_3532 ) , .p3513 ( optlc_net_3533 ) ,
+ .p3514 ( optlc_net_3534 ) , .p3515 ( optlc_net_3535 ) ,
+ .p3516 ( optlc_net_3536 ) , .p3517 ( optlc_net_3537 ) ,
+ .p3518 ( optlc_net_3538 ) , .p3519 ( optlc_net_3539 ) ,
+ .p3520 ( optlc_net_3540 ) , .p3521 ( optlc_net_3541 ) ,
+ .p3522 ( optlc_net_3542 ) , .p3523 ( optlc_net_3543 ) ,
+ .p3524 ( optlc_net_3544 ) , .p3525 ( optlc_net_3545 ) ,
+ .p3526 ( optlc_net_3546 ) , .p3527 ( optlc_net_3547 ) ,
+ .p3528 ( optlc_net_3548 ) , .p3529 ( optlc_net_3549 ) ,
+ .p3530 ( optlc_net_3550 ) , .p3531 ( optlc_net_3551 ) ,
+ .p3532 ( optlc_net_3552 ) , .p3533 ( optlc_net_3553 ) ,
+ .p3534 ( optlc_net_3554 ) , .p3535 ( optlc_net_3555 ) ,
+ .p3536 ( optlc_net_3556 ) , .p3537 ( optlc_net_3557 ) ,
+ .p3538 ( optlc_net_3558 ) , .p3539 ( optlc_net_3559 ) ,
+ .p3540 ( optlc_net_3560 ) , .p3541 ( optlc_net_3561 ) ,
+ .p3542 ( optlc_net_3562 ) , .p3543 ( optlc_net_3563 ) ,
+ .p3544 ( optlc_net_3564 ) , .p3545 ( optlc_net_3565 ) ,
+ .p3546 ( optlc_net_3566 ) , .p3547 ( optlc_net_3567 ) ,
+ .p3548 ( optlc_net_3568 ) , .p3549 ( optlc_net_3569 ) ,
+ .p3550 ( optlc_net_3570 ) , .p3551 ( optlc_net_3571 ) ,
+ .p3552 ( optlc_net_3572 ) , .p3553 ( optlc_net_3573 ) ,
+ .p3554 ( optlc_net_3574 ) , .p3555 ( optlc_net_3575 ) ,
+ .p3556 ( optlc_net_3576 ) , .p3557 ( optlc_net_3577 ) ,
+ .p3558 ( optlc_net_3578 ) , .p3559 ( optlc_net_3579 ) ,
+ .p3560 ( optlc_net_3580 ) , .p3561 ( optlc_net_3581 ) ,
+ .p3562 ( optlc_net_3582 ) , .p3563 ( optlc_net_3583 ) ,
+ .p3564 ( optlc_net_3584 ) , .p3565 ( optlc_net_3585 ) ,
+ .p3566 ( optlc_net_3586 ) , .p3567 ( optlc_net_3587 ) ,
+ .p3568 ( optlc_net_3588 ) , .p3569 ( optlc_net_3589 ) ,
+ .p3570 ( optlc_net_3590 ) , .p3571 ( optlc_net_3591 ) ,
+ .p3572 ( optlc_net_3592 ) , .p3573 ( optlc_net_3593 ) ,
+ .p3574 ( optlc_net_3594 ) , .p3575 ( optlc_net_3595 ) ,
+ .p3576 ( optlc_net_3596 ) , .p3577 ( optlc_net_3597 ) ,
+ .p3578 ( optlc_net_3598 ) , .p3579 ( optlc_net_3599 ) ,
+ .p3580 ( optlc_net_3600 ) , .p3581 ( optlc_net_3601 ) ,
+ .p3582 ( optlc_net_3602 ) , .p3583 ( optlc_net_3603 ) ,
+ .p3584 ( optlc_net_3604 ) , .p3585 ( optlc_net_3605 ) ,
+ .p3586 ( optlc_net_3606 ) , .p3587 ( optlc_net_3607 ) ,
+ .p3588 ( optlc_net_3608 ) , .p3589 ( optlc_net_3609 ) ,
+ .p3590 ( optlc_net_3610 ) , .p3591 ( optlc_net_3611 ) ,
+ .p3592 ( optlc_net_3612 ) , .p3593 ( optlc_net_3613 ) ,
+ .p3594 ( optlc_net_3614 ) , .p3595 ( optlc_net_3615 ) ,
+ .p3596 ( optlc_net_3616 ) , .p3597 ( optlc_net_3617 ) ,
+ .p3598 ( optlc_net_3618 ) , .p3599 ( optlc_net_3619 ) ,
+ .p3600 ( optlc_net_3620 ) , .p3601 ( optlc_net_3621 ) ,
+ .p3602 ( optlc_net_3622 ) , .p3603 ( optlc_net_3623 ) ,
+ .p3604 ( optlc_net_3624 ) , .p3605 ( optlc_net_3625 ) ,
+ .p3606 ( optlc_net_3626 ) , .p3607 ( optlc_net_3627 ) ,
+ .p3608 ( optlc_net_3628 ) , .p3609 ( optlc_net_3629 ) ,
+ .p3610 ( optlc_net_3630 ) , .p3611 ( optlc_net_3631 ) ,
+ .p3612 ( optlc_net_3632 ) , .p3613 ( optlc_net_3633 ) ,
+ .p3614 ( optlc_net_3634 ) , .p3615 ( optlc_net_3635 ) ,
+ .p3616 ( optlc_net_3636 ) , .p3617 ( optlc_net_3637 ) ,
+ .p3618 ( optlc_net_3638 ) , .p3619 ( optlc_net_3639 ) ,
+ .p3620 ( optlc_net_3640 ) , .p3621 ( optlc_net_3641 ) ,
+ .p3622 ( optlc_net_3642 ) , .p3623 ( optlc_net_3643 ) ,
+ .p3624 ( optlc_net_3644 ) , .p3625 ( optlc_net_3645 ) ,
+ .p3626 ( optlc_net_3646 ) , .p3627 ( optlc_net_3647 ) ,
+ .p3628 ( optlc_net_3648 ) , .p3629 ( optlc_net_3649 ) ,
+ .p3630 ( optlc_net_3650 ) , .p3631 ( optlc_net_3651 ) ,
+ .p3632 ( optlc_net_3652 ) , .p3633 ( optlc_net_3653 ) ,
+ .p3634 ( optlc_net_3654 ) , .p3635 ( optlc_net_3655 ) ,
+ .p3636 ( optlc_net_3656 ) , .p3637 ( optlc_net_3657 ) ,
+ .p3638 ( optlc_net_3658 ) , .p3639 ( optlc_net_3659 ) ,
+ .p3640 ( optlc_net_3660 ) , .p3641 ( optlc_net_3661 ) ,
+ .p3642 ( optlc_net_3662 ) , .p3643 ( optlc_net_3663 ) ,
+ .p3644 ( optlc_net_3664 ) , .p3645 ( optlc_net_3665 ) ,
+ .p3646 ( optlc_net_3666 ) , .p3647 ( optlc_net_3667 ) ,
+ .p3648 ( optlc_net_3668 ) , .p3649 ( optlc_net_3669 ) ,
+ .p3650 ( optlc_net_3670 ) , .p3651 ( optlc_net_3671 ) ,
+ .p3652 ( optlc_net_3672 ) , .p3653 ( optlc_net_3673 ) ,
+ .p3654 ( optlc_net_3674 ) , .p3655 ( optlc_net_3675 ) ,
+ .p3656 ( optlc_net_3676 ) , .p3657 ( optlc_net_3677 ) ,
+ .p3658 ( optlc_net_3678 ) , .p3659 ( optlc_net_3679 ) ,
+ .p3660 ( optlc_net_3680 ) , .p3661 ( optlc_net_3681 ) ,
+ .p3662 ( optlc_net_3682 ) , .p3663 ( optlc_net_3683 ) ,
+ .p3664 ( optlc_net_3684 ) , .p3665 ( optlc_net_3685 ) ,
+ .p3666 ( optlc_net_3686 ) , .p3667 ( optlc_net_3687 ) ,
+ .p3668 ( optlc_net_3688 ) , .p3669 ( optlc_net_3689 ) ,
+ .p3670 ( optlc_net_3690 ) , .p3671 ( optlc_net_3691 ) ,
+ .p3672 ( optlc_net_3692 ) , .p3673 ( optlc_net_3693 ) ,
+ .p3674 ( optlc_net_3694 ) , .p3675 ( optlc_net_3695 ) ,
+ .p3676 ( optlc_net_3696 ) , .p3677 ( optlc_net_3697 ) ,
+ .p3678 ( optlc_net_3698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( io_oeb[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( io_oeb[1] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( io_oeb[2] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( io_oeb[3] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .HI ( io_oeb[12] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .HI ( io_oeb[25] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .HI ( io_oeb[26] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) ,
+ .HI ( io_oeb[36] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_10 ) ,
+ .HI ( io_oeb[37] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_39 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_40 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_41 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_42 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_43 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_44 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_46 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_47 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_48 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_74 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( optlc_net_75 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( optlc_net_76 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( optlc_net_77 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_79 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( optlc_net_78 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_80 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( optlc_net_79 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_81 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( optlc_net_80 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_82 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( optlc_net_81 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( optlc_net_82 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( optlc_net_83 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( optlc_net_84 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_86 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( optlc_net_85 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_87 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_87 ( .LO ( optlc_net_86 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( optlc_net_87 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( optlc_net_88 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( optlc_net_89 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( optlc_net_90 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( optlc_net_91 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( optlc_net_92 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( optlc_net_93 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( optlc_net_94 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( optlc_net_95 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( optlc_net_96 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( optlc_net_97 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( optlc_net_98 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( optlc_net_99 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( optlc_net_100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( optlc_net_101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( optlc_net_102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( optlc_net_103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( optlc_net_104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( optlc_net_105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( optlc_net_106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( optlc_net_107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( optlc_net_108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( optlc_net_109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( optlc_net_110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( optlc_net_111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( optlc_net_112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( optlc_net_113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( optlc_net_114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( optlc_net_115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( optlc_net_116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( optlc_net_117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( optlc_net_118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( optlc_net_119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( optlc_net_120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( optlc_net_121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( optlc_net_122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( optlc_net_123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( optlc_net_124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( optlc_net_125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( optlc_net_126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( optlc_net_127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( optlc_net_128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( optlc_net_129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( optlc_net_130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( optlc_net_131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( optlc_net_132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( optlc_net_133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( optlc_net_134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( optlc_net_135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( optlc_net_136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( optlc_net_137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( optlc_net_138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( optlc_net_139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( optlc_net_140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( optlc_net_141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( optlc_net_142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( optlc_net_143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( optlc_net_144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( optlc_net_145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( optlc_net_146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( optlc_net_147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( optlc_net_148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( optlc_net_149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( optlc_net_150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( optlc_net_151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( optlc_net_152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( optlc_net_153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( optlc_net_154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( optlc_net_155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( optlc_net_156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( optlc_net_157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( optlc_net_158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( optlc_net_159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( optlc_net_160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( optlc_net_161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_163 ( .LO ( optlc_net_162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( optlc_net_163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( optlc_net_164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( optlc_net_165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( optlc_net_166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( optlc_net_167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_169 ( .LO ( optlc_net_168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( optlc_net_169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( optlc_net_170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( optlc_net_171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( optlc_net_172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( optlc_net_173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( optlc_net_174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( optlc_net_175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( optlc_net_176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( optlc_net_177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( optlc_net_178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( optlc_net_179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( optlc_net_180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( optlc_net_181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_183 ( .LO ( optlc_net_182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( optlc_net_183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( optlc_net_184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( optlc_net_185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( optlc_net_186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( optlc_net_187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( optlc_net_188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( optlc_net_189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( optlc_net_190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( optlc_net_191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( optlc_net_192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( optlc_net_193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( optlc_net_194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( optlc_net_195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( optlc_net_196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_198 ( .LO ( optlc_net_197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( optlc_net_198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( optlc_net_199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( optlc_net_200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( optlc_net_201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( optlc_net_202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( optlc_net_203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( optlc_net_204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( optlc_net_205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( optlc_net_206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( optlc_net_207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( optlc_net_208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( optlc_net_209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( optlc_net_210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( optlc_net_211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( optlc_net_212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( optlc_net_213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( optlc_net_214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( optlc_net_215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( optlc_net_216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( optlc_net_217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( optlc_net_218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( optlc_net_219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( optlc_net_220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( optlc_net_221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( optlc_net_222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( optlc_net_223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( optlc_net_224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( optlc_net_225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( optlc_net_226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( optlc_net_227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( optlc_net_228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( optlc_net_229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_231 ( .LO ( optlc_net_230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( optlc_net_231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( optlc_net_232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_234 ( .LO ( optlc_net_233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( optlc_net_234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_236 ( .LO ( optlc_net_235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( optlc_net_236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_238 ( .LO ( optlc_net_237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( optlc_net_238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_240 ( .LO ( optlc_net_239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_241 ( .LO ( optlc_net_240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_242 ( .LO ( optlc_net_241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_243 ( .LO ( optlc_net_242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_244 ( .LO ( optlc_net_243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_245 ( .LO ( optlc_net_244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_246 ( .LO ( optlc_net_245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_247 ( .LO ( optlc_net_246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_248 ( .LO ( optlc_net_247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_249 ( .LO ( optlc_net_248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_250 ( .LO ( optlc_net_249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_251 ( .LO ( optlc_net_250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_252 ( .LO ( optlc_net_251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_253 ( .LO ( optlc_net_252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_254 ( .LO ( optlc_net_253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_255 ( .LO ( optlc_net_254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_256 ( .LO ( optlc_net_255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_257 ( .LO ( optlc_net_256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_258 ( .LO ( optlc_net_257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_259 ( .LO ( optlc_net_258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_260 ( .LO ( optlc_net_259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_261 ( .LO ( optlc_net_260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_262 ( .LO ( optlc_net_261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_263 ( .LO ( optlc_net_262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_264 ( .LO ( optlc_net_263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_265 ( .LO ( optlc_net_264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_266 ( .LO ( optlc_net_265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_267 ( .LO ( optlc_net_266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_268 ( .LO ( optlc_net_267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_269 ( .LO ( optlc_net_268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_274 ( .LO ( optlc_net_273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_280 ( .LO ( optlc_net_279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_284 ( .LO ( optlc_net_283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_295 ( .LO ( optlc_net_294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_298 ( .LO ( optlc_net_297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_311 ( .LO ( optlc_net_310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_313 ( .LO ( optlc_net_312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_315 ( .LO ( optlc_net_314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_327 ( .LO ( optlc_net_326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_330 ( .LO ( optlc_net_329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_334 ( .LO ( optlc_net_333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_336 ( .LO ( optlc_net_335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_342 ( .LO ( optlc_net_341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_351 ( .LO ( optlc_net_350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_353 ( .LO ( optlc_net_352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_355 ( .LO ( optlc_net_354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_361 ( .LO ( optlc_net_360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_365 ( .LO ( optlc_net_364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_367 ( .LO ( optlc_net_366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_401 ( .LO ( optlc_net_400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_403 ( .LO ( optlc_net_402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_413 ( .LO ( optlc_net_412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_415 ( .LO ( optlc_net_414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_751 ( .LO ( optlc_net_746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_773 ( .LO ( optlc_net_768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_935 ( .LO ( optlc_net_926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_937 ( .LO ( optlc_net_928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_939 ( .LO ( optlc_net_930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_943 ( .LO ( optlc_net_934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_944 ( .LO ( optlc_net_935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_967 ( .LO ( optlc_net_956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_977 ( .LO ( optlc_net_965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_982 ( .LO ( optlc_net_970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_990 ( .LO ( optlc_net_977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_996 ( .LO ( optlc_net_983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1003 ( .LO ( optlc_net_990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1005 ( .LO ( optlc_net_992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1009 ( .LO ( optlc_net_996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1011 ( .LO ( optlc_net_998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1012 ( .LO ( optlc_net_999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_1000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1014 ( .LO ( optlc_net_1001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1015 ( .LO ( optlc_net_1002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1016 ( .LO ( optlc_net_1003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1017 ( .LO ( optlc_net_1004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1018 ( .LO ( optlc_net_1005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1019 ( .LO ( optlc_net_1006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1020 ( .LO ( optlc_net_1007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1021 ( .LO ( optlc_net_1008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1022 ( .LO ( optlc_net_1009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1023 ( .LO ( optlc_net_1010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1024 ( .LO ( optlc_net_1011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1025 ( .LO ( optlc_net_1012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1026 ( .LO ( optlc_net_1013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1027 ( .LO ( optlc_net_1014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1028 ( .LO ( optlc_net_1015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1029 ( .LO ( optlc_net_1016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1030 ( .LO ( optlc_net_1017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1031 ( .LO ( optlc_net_1018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1032 ( .LO ( optlc_net_1019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1033 ( .LO ( optlc_net_1020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1034 ( .LO ( optlc_net_1021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1036 ( .LO ( optlc_net_1022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1037 ( .LO ( optlc_net_1023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1038 ( .LO ( optlc_net_1024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1039 ( .LO ( optlc_net_1025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1040 ( .LO ( optlc_net_1026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1041 ( .LO ( optlc_net_1027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1043 ( .LO ( optlc_net_1028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1044 ( .LO ( optlc_net_1029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1045 ( .LO ( optlc_net_1030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1046 ( .LO ( optlc_net_1031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1047 ( .LO ( optlc_net_1032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1048 ( .LO ( optlc_net_1033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1049 ( .LO ( optlc_net_1034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1050 ( .LO ( optlc_net_1035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1051 ( .LO ( optlc_net_1036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1053 ( .LO ( optlc_net_1037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1054 ( .LO ( optlc_net_1038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1055 ( .LO ( optlc_net_1039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1056 ( .LO ( optlc_net_1040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1057 ( .LO ( optlc_net_1041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1058 ( .LO ( optlc_net_1042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1059 ( .LO ( optlc_net_1043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1060 ( .LO ( optlc_net_1044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1061 ( .LO ( optlc_net_1045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1062 ( .LO ( optlc_net_1046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1063 ( .LO ( optlc_net_1047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1064 ( .LO ( optlc_net_1048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1066 ( .LO ( optlc_net_1049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1067 ( .LO ( optlc_net_1050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1069 ( .LO ( optlc_net_1051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1070 ( .LO ( optlc_net_1052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1071 ( .LO ( optlc_net_1053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1073 ( .LO ( optlc_net_1054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1074 ( .LO ( optlc_net_1055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1075 ( .LO ( optlc_net_1056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1076 ( .LO ( optlc_net_1057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1077 ( .LO ( optlc_net_1058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1078 ( .LO ( optlc_net_1059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1079 ( .LO ( optlc_net_1060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1081 ( .LO ( optlc_net_1061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1082 ( .LO ( optlc_net_1062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1083 ( .LO ( optlc_net_1063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1084 ( .LO ( optlc_net_1064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1086 ( .LO ( optlc_net_1065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1088 ( .LO ( optlc_net_1066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1089 ( .LO ( optlc_net_1067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1090 ( .LO ( optlc_net_1068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1092 ( .LO ( optlc_net_1069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1093 ( .LO ( optlc_net_1070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1095 ( .LO ( optlc_net_1071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1096 ( .LO ( optlc_net_1072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1097 ( .LO ( optlc_net_1073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1098 ( .LO ( optlc_net_1074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1099 ( .LO ( optlc_net_1075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1100 ( .LO ( optlc_net_1076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1101 ( .LO ( optlc_net_1077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1102 ( .LO ( optlc_net_1078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1103 ( .LO ( optlc_net_1079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1104 ( .LO ( optlc_net_1080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1105 ( .LO ( optlc_net_1081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1106 ( .LO ( optlc_net_1082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1107 ( .LO ( optlc_net_1083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1109 ( .LO ( optlc_net_1084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1111 ( .LO ( optlc_net_1085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1112 ( .LO ( optlc_net_1086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1113 ( .LO ( optlc_net_1087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1114 ( .LO ( optlc_net_1088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1115 ( .LO ( optlc_net_1089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1116 ( .LO ( optlc_net_1090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1117 ( .LO ( optlc_net_1091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1119 ( .LO ( optlc_net_1092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1121 ( .LO ( optlc_net_1093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1123 ( .LO ( optlc_net_1094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1124 ( .LO ( optlc_net_1095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1126 ( .LO ( optlc_net_1096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1127 ( .LO ( optlc_net_1097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1128 ( .LO ( optlc_net_1098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1129 ( .LO ( optlc_net_1099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1131 ( .LO ( optlc_net_1100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1132 ( .LO ( optlc_net_1101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1133 ( .LO ( optlc_net_1102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1134 ( .LO ( optlc_net_1103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1136 ( .LO ( optlc_net_1104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1137 ( .LO ( optlc_net_1105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1138 ( .LO ( optlc_net_1106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1139 ( .LO ( optlc_net_1107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1141 ( .LO ( optlc_net_1108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1142 ( .LO ( optlc_net_1109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1143 ( .LO ( optlc_net_1110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1145 ( .LO ( optlc_net_1111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1147 ( .LO ( optlc_net_1112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1148 ( .LO ( optlc_net_1113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1149 ( .LO ( optlc_net_1114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1150 ( .LO ( optlc_net_1115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1151 ( .LO ( optlc_net_1116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1152 ( .LO ( optlc_net_1117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1153 ( .LO ( optlc_net_1118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1155 ( .LO ( optlc_net_1119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1156 ( .LO ( optlc_net_1120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1157 ( .LO ( optlc_net_1121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1159 ( .LO ( optlc_net_1122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1160 ( .LO ( optlc_net_1123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1162 ( .LO ( optlc_net_1124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1163 ( .LO ( optlc_net_1125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1164 ( .LO ( optlc_net_1126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1165 ( .LO ( optlc_net_1127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1167 ( .LO ( optlc_net_1128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1168 ( .LO ( optlc_net_1129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1170 ( .LO ( optlc_net_1130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1171 ( .LO ( optlc_net_1131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1172 ( .LO ( optlc_net_1132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1173 ( .LO ( optlc_net_1133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1175 ( .LO ( optlc_net_1134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1176 ( .LO ( optlc_net_1135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1177 ( .LO ( optlc_net_1136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1178 ( .LO ( optlc_net_1137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1179 ( .LO ( optlc_net_1138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1180 ( .LO ( optlc_net_1139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1181 ( .LO ( optlc_net_1140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1182 ( .LO ( optlc_net_1141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1183 ( .LO ( optlc_net_1142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1184 ( .LO ( optlc_net_1143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1185 ( .LO ( optlc_net_1144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1186 ( .LO ( optlc_net_1145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1187 ( .LO ( optlc_net_1146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1188 ( .LO ( optlc_net_1147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1189 ( .LO ( optlc_net_1148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1190 ( .LO ( optlc_net_1149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1192 ( .LO ( optlc_net_1150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1193 ( .LO ( optlc_net_1151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1194 ( .LO ( optlc_net_1152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1196 ( .LO ( optlc_net_1153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1197 ( .LO ( optlc_net_1154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1198 ( .LO ( optlc_net_1155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1199 ( .LO ( optlc_net_1156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1201 ( .LO ( optlc_net_1157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1203 ( .LO ( optlc_net_1158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1204 ( .LO ( optlc_net_1159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1205 ( .LO ( optlc_net_1160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1206 ( .LO ( optlc_net_1161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1207 ( .LO ( optlc_net_1162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1208 ( .LO ( optlc_net_1163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1209 ( .LO ( optlc_net_1164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1210 ( .LO ( optlc_net_1165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1212 ( .LO ( optlc_net_1166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1213 ( .LO ( optlc_net_1167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1214 ( .LO ( optlc_net_1168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1216 ( .LO ( optlc_net_1169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1217 ( .LO ( optlc_net_1170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1218 ( .LO ( optlc_net_1171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1219 ( .LO ( optlc_net_1172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1220 ( .LO ( optlc_net_1173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1222 ( .LO ( optlc_net_1174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1223 ( .LO ( optlc_net_1175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1224 ( .LO ( optlc_net_1176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1225 ( .LO ( optlc_net_1177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1226 ( .LO ( optlc_net_1178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1227 ( .LO ( optlc_net_1179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1228 ( .LO ( optlc_net_1180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1229 ( .LO ( optlc_net_1181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1230 ( .LO ( optlc_net_1182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1231 ( .LO ( optlc_net_1183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1233 ( .LO ( optlc_net_1184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1234 ( .LO ( optlc_net_1185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1235 ( .LO ( optlc_net_1186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1236 ( .LO ( optlc_net_1187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1237 ( .LO ( optlc_net_1188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1239 ( .LO ( optlc_net_1189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1240 ( .LO ( optlc_net_1190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1241 ( .LO ( optlc_net_1191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1243 ( .LO ( optlc_net_1192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1245 ( .LO ( optlc_net_1193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1246 ( .LO ( optlc_net_1194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1247 ( .LO ( optlc_net_1195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1249 ( .LO ( optlc_net_1196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1250 ( .LO ( optlc_net_1197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1251 ( .LO ( optlc_net_1198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1252 ( .LO ( optlc_net_1199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1254 ( .LO ( optlc_net_1200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1256 ( .LO ( optlc_net_1201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1257 ( .LO ( optlc_net_1202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1259 ( .LO ( optlc_net_1203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1260 ( .LO ( optlc_net_1204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1262 ( .LO ( optlc_net_1205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1263 ( .LO ( optlc_net_1206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1265 ( .LO ( optlc_net_1207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1266 ( .LO ( optlc_net_1208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1267 ( .LO ( optlc_net_1209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1269 ( .LO ( optlc_net_1210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1271 ( .LO ( optlc_net_1211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1273 ( .LO ( optlc_net_1212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1275 ( .LO ( optlc_net_1213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1277 ( .LO ( optlc_net_1214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1279 ( .LO ( optlc_net_1215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1280 ( .LO ( optlc_net_1216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1282 ( .LO ( optlc_net_1217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1284 ( .LO ( optlc_net_1218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1285 ( .LO ( optlc_net_1219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1286 ( .LO ( optlc_net_1220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1287 ( .LO ( optlc_net_1221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1288 ( .LO ( optlc_net_1222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1289 ( .LO ( optlc_net_1223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1290 ( .LO ( optlc_net_1224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1292 ( .LO ( optlc_net_1225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1293 ( .LO ( optlc_net_1226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1294 ( .LO ( optlc_net_1227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1295 ( .LO ( optlc_net_1228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1297 ( .LO ( optlc_net_1229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1299 ( .LO ( optlc_net_1230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1301 ( .LO ( optlc_net_1231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1302 ( .LO ( optlc_net_1232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1304 ( .LO ( optlc_net_1233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1306 ( .LO ( optlc_net_1234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1307 ( .LO ( optlc_net_1235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1308 ( .LO ( optlc_net_1236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1310 ( .LO ( optlc_net_1237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1312 ( .LO ( optlc_net_1238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1314 ( .LO ( optlc_net_1239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1316 ( .LO ( optlc_net_1240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1317 ( .LO ( optlc_net_1241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1318 ( .LO ( optlc_net_1242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1320 ( .LO ( optlc_net_1243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1321 ( .LO ( optlc_net_1244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1323 ( .LO ( optlc_net_1245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1324 ( .LO ( optlc_net_1246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1325 ( .LO ( optlc_net_1247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1327 ( .LO ( optlc_net_1248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1329 ( .LO ( optlc_net_1249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1330 ( .LO ( optlc_net_1250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1331 ( .LO ( optlc_net_1251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1332 ( .LO ( optlc_net_1252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1334 ( .LO ( optlc_net_1253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1335 ( .LO ( optlc_net_1254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1336 ( .LO ( optlc_net_1255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1338 ( .LO ( optlc_net_1256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1339 ( .LO ( optlc_net_1257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1340 ( .LO ( optlc_net_1258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1342 ( .LO ( optlc_net_1259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1344 ( .LO ( optlc_net_1260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1345 ( .LO ( optlc_net_1261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1346 ( .LO ( optlc_net_1262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1347 ( .LO ( optlc_net_1263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1349 ( .LO ( optlc_net_1264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1351 ( .LO ( optlc_net_1265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1353 ( .LO ( optlc_net_1266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1354 ( .LO ( optlc_net_1267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1356 ( .LO ( optlc_net_1268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1357 ( .LO ( optlc_net_1269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1359 ( .LO ( optlc_net_1270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1360 ( .LO ( optlc_net_1271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1362 ( .LO ( optlc_net_1272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1363 ( .LO ( optlc_net_1273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1365 ( .LO ( optlc_net_1274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1367 ( .LO ( optlc_net_1275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1368 ( .LO ( optlc_net_1276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1369 ( .LO ( optlc_net_1277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1371 ( .LO ( optlc_net_1278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1372 ( .LO ( optlc_net_1279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1374 ( .LO ( optlc_net_1280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1375 ( .LO ( optlc_net_1281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1376 ( .LO ( optlc_net_1282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1377 ( .LO ( optlc_net_1283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1379 ( .LO ( optlc_net_1284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1380 ( .LO ( optlc_net_1285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1381 ( .LO ( optlc_net_1286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1382 ( .LO ( optlc_net_1287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1384 ( .LO ( optlc_net_1288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1385 ( .LO ( optlc_net_1289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1386 ( .LO ( optlc_net_1290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1387 ( .LO ( optlc_net_1291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1388 ( .LO ( optlc_net_1292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1389 ( .LO ( optlc_net_1293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1390 ( .LO ( optlc_net_1294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1391 ( .LO ( optlc_net_1295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1392 ( .LO ( optlc_net_1296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1393 ( .LO ( optlc_net_1297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1395 ( .LO ( optlc_net_1298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1396 ( .LO ( optlc_net_1299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1398 ( .LO ( optlc_net_1300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1399 ( .LO ( optlc_net_1301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1400 ( .LO ( optlc_net_1302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1402 ( .LO ( optlc_net_1303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1403 ( .LO ( optlc_net_1304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1405 ( .LO ( optlc_net_1305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1406 ( .LO ( optlc_net_1306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1408 ( .LO ( optlc_net_1307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1409 ( .LO ( optlc_net_1308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1410 ( .LO ( optlc_net_1309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1411 ( .LO ( optlc_net_1310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1412 ( .LO ( optlc_net_1311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1413 ( .LO ( optlc_net_1312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1414 ( .LO ( optlc_net_1313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1416 ( .LO ( optlc_net_1314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1417 ( .LO ( optlc_net_1315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1418 ( .LO ( optlc_net_1316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1420 ( .LO ( optlc_net_1317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1422 ( .LO ( optlc_net_1318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1423 ( .LO ( optlc_net_1319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1425 ( .LO ( optlc_net_1320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1427 ( .LO ( optlc_net_1321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1429 ( .LO ( optlc_net_1322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1431 ( .LO ( optlc_net_1323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1432 ( .LO ( optlc_net_1324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1433 ( .LO ( optlc_net_1325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1435 ( .LO ( optlc_net_1326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1437 ( .LO ( optlc_net_1327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1438 ( .LO ( optlc_net_1328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1439 ( .LO ( optlc_net_1329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1440 ( .LO ( optlc_net_1330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1441 ( .LO ( optlc_net_1331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1443 ( .LO ( optlc_net_1332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1445 ( .LO ( optlc_net_1333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1447 ( .LO ( optlc_net_1334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1449 ( .LO ( optlc_net_1335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1450 ( .LO ( optlc_net_1336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1451 ( .LO ( optlc_net_1337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1453 ( .LO ( optlc_net_1338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1455 ( .LO ( optlc_net_1339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1457 ( .LO ( optlc_net_1340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1459 ( .LO ( optlc_net_1341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1461 ( .LO ( optlc_net_1342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1466 ( .LO ( optlc_net_1346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1468 ( .LO ( optlc_net_1347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1470 ( .LO ( optlc_net_1348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1473 ( .LO ( optlc_net_1350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1475 ( .LO ( optlc_net_1351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1476 ( .LO ( optlc_net_1352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1477 ( .LO ( optlc_net_1353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1478 ( .LO ( optlc_net_1354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1479 ( .LO ( optlc_net_1355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1481 ( .LO ( optlc_net_1356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1486 ( .LO ( optlc_net_1359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1487 ( .LO ( optlc_net_1360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1492 ( .LO ( optlc_net_1363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1493 ( .LO ( optlc_net_1364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1494 ( .LO ( optlc_net_1365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1495 ( .LO ( optlc_net_1366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1496 ( .LO ( optlc_net_1367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1497 ( .LO ( optlc_net_1368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1498 ( .LO ( optlc_net_1369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1499 ( .LO ( optlc_net_1370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1501 ( .LO ( optlc_net_1371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1503 ( .LO ( optlc_net_1372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1504 ( .LO ( optlc_net_1373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1505 ( .LO ( optlc_net_1374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1506 ( .LO ( optlc_net_1375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1508 ( .LO ( optlc_net_1376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1509 ( .LO ( optlc_net_1377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1511 ( .LO ( optlc_net_1378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1513 ( .LO ( optlc_net_1379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1514 ( .LO ( optlc_net_1380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1516 ( .LO ( optlc_net_1381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1518 ( .LO ( optlc_net_1382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1519 ( .LO ( optlc_net_1383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1521 ( .LO ( optlc_net_1384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1522 ( .LO ( optlc_net_1385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1523 ( .LO ( optlc_net_1386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1525 ( .LO ( optlc_net_1387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1527 ( .LO ( optlc_net_1388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1528 ( .LO ( optlc_net_1389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1529 ( .LO ( optlc_net_1390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1531 ( .LO ( optlc_net_1391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1533 ( .LO ( optlc_net_1392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1534 ( .LO ( optlc_net_1393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1535 ( .LO ( optlc_net_1394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1537 ( .LO ( optlc_net_1395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1538 ( .LO ( optlc_net_1396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1539 ( .LO ( optlc_net_1397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1540 ( .LO ( optlc_net_1398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1541 ( .LO ( optlc_net_1399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1542 ( .LO ( optlc_net_1400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1544 ( .LO ( optlc_net_1401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1545 ( .LO ( optlc_net_1402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1546 ( .LO ( optlc_net_1403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1548 ( .LO ( optlc_net_1404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1549 ( .LO ( optlc_net_1405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1551 ( .LO ( optlc_net_1406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1552 ( .LO ( optlc_net_1407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1553 ( .LO ( optlc_net_1408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1554 ( .LO ( optlc_net_1409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1555 ( .LO ( optlc_net_1410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1557 ( .LO ( optlc_net_1411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1558 ( .LO ( optlc_net_1412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1559 ( .LO ( optlc_net_1413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1560 ( .LO ( optlc_net_1414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1561 ( .LO ( optlc_net_1415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1562 ( .LO ( optlc_net_1416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1563 ( .LO ( optlc_net_1417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1564 ( .LO ( optlc_net_1418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1565 ( .LO ( optlc_net_1419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1566 ( .LO ( optlc_net_1420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1568 ( .LO ( optlc_net_1421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1569 ( .LO ( optlc_net_1422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1570 ( .LO ( optlc_net_1423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1572 ( .LO ( optlc_net_1424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1573 ( .LO ( optlc_net_1425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1575 ( .LO ( optlc_net_1426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1577 ( .LO ( optlc_net_1427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1578 ( .LO ( optlc_net_1428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1580 ( .LO ( optlc_net_1429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1581 ( .LO ( optlc_net_1430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1582 ( .LO ( optlc_net_1431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1583 ( .LO ( optlc_net_1432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1584 ( .LO ( optlc_net_1433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1586 ( .LO ( optlc_net_1434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1587 ( .LO ( optlc_net_1435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1589 ( .LO ( optlc_net_1436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1590 ( .LO ( optlc_net_1437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1592 ( .LO ( optlc_net_1438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1593 ( .LO ( optlc_net_1439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1594 ( .LO ( optlc_net_1440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1596 ( .LO ( optlc_net_1441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1598 ( .LO ( optlc_net_1442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1600 ( .LO ( optlc_net_1443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1601 ( .LO ( optlc_net_1444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1602 ( .LO ( optlc_net_1445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1604 ( .LO ( optlc_net_1446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1605 ( .LO ( optlc_net_1447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1606 ( .LO ( optlc_net_1448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1608 ( .LO ( optlc_net_1449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1609 ( .LO ( optlc_net_1450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1610 ( .LO ( optlc_net_1451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1611 ( .LO ( optlc_net_1452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1612 ( .LO ( optlc_net_1453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1613 ( .LO ( optlc_net_1454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1614 ( .LO ( optlc_net_1455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1616 ( .LO ( optlc_net_1456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1617 ( .LO ( optlc_net_1457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1618 ( .LO ( optlc_net_1458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1619 ( .LO ( optlc_net_1459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1620 ( .LO ( optlc_net_1460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1621 ( .LO ( optlc_net_1461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1622 ( .LO ( optlc_net_1462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1623 ( .LO ( optlc_net_1463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1625 ( .LO ( optlc_net_1464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1626 ( .LO ( optlc_net_1465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1628 ( .LO ( optlc_net_1466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1629 ( .LO ( optlc_net_1467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1630 ( .LO ( optlc_net_1468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1631 ( .LO ( optlc_net_1469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1632 ( .LO ( optlc_net_1470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1634 ( .LO ( optlc_net_1471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1636 ( .LO ( optlc_net_1472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1638 ( .LO ( optlc_net_1473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1639 ( .LO ( optlc_net_1474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1640 ( .LO ( optlc_net_1475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1642 ( .LO ( optlc_net_1476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1643 ( .LO ( optlc_net_1477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1644 ( .LO ( optlc_net_1478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1645 ( .LO ( optlc_net_1479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1647 ( .LO ( optlc_net_1480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1649 ( .LO ( optlc_net_1481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1651 ( .LO ( optlc_net_1482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1652 ( .LO ( optlc_net_1483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1653 ( .LO ( optlc_net_1484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1654 ( .LO ( optlc_net_1485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1655 ( .LO ( optlc_net_1486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1656 ( .LO ( optlc_net_1487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1657 ( .LO ( optlc_net_1488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1658 ( .LO ( optlc_net_1489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1659 ( .LO ( optlc_net_1490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1660 ( .LO ( optlc_net_1491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1661 ( .LO ( optlc_net_1492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1662 ( .LO ( optlc_net_1493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1663 ( .LO ( optlc_net_1494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1664 ( .LO ( optlc_net_1495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1665 ( .LO ( optlc_net_1496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1666 ( .LO ( optlc_net_1497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1667 ( .LO ( optlc_net_1498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1668 ( .LO ( optlc_net_1499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1669 ( .LO ( optlc_net_1500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1670 ( .LO ( optlc_net_1501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1671 ( .LO ( optlc_net_1502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1672 ( .LO ( optlc_net_1503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1673 ( .LO ( optlc_net_1504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1674 ( .LO ( optlc_net_1505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1675 ( .LO ( optlc_net_1506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1676 ( .LO ( optlc_net_1507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1677 ( .LO ( optlc_net_1508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1678 ( .LO ( optlc_net_1509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1679 ( .LO ( optlc_net_1510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1680 ( .LO ( optlc_net_1511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1681 ( .LO ( optlc_net_1512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1682 ( .LO ( optlc_net_1513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1683 ( .LO ( optlc_net_1514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1684 ( .LO ( optlc_net_1515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1685 ( .LO ( optlc_net_1516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1686 ( .LO ( optlc_net_1517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1687 ( .LO ( optlc_net_1518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1688 ( .LO ( optlc_net_1519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1689 ( .LO ( optlc_net_1520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1690 ( .LO ( optlc_net_1521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1691 ( .LO ( optlc_net_1522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1692 ( .LO ( optlc_net_1523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1693 ( .LO ( optlc_net_1524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1694 ( .LO ( optlc_net_1525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1695 ( .LO ( optlc_net_1526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1696 ( .LO ( optlc_net_1527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1697 ( .LO ( optlc_net_1528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1698 ( .LO ( optlc_net_1529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1699 ( .LO ( optlc_net_1530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1700 ( .LO ( optlc_net_1531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1701 ( .LO ( optlc_net_1532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1702 ( .LO ( optlc_net_1533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1703 ( .LO ( optlc_net_1534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1704 ( .LO ( optlc_net_1535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1705 ( .LO ( optlc_net_1536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1706 ( .LO ( optlc_net_1537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1707 ( .LO ( optlc_net_1538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1708 ( .LO ( optlc_net_1539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1709 ( .LO ( optlc_net_1540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1710 ( .LO ( optlc_net_1541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1711 ( .LO ( optlc_net_1542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1712 ( .LO ( optlc_net_1543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1713 ( .LO ( optlc_net_1544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1714 ( .LO ( optlc_net_1545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1715 ( .LO ( optlc_net_1546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1716 ( .LO ( optlc_net_1547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1717 ( .LO ( optlc_net_1548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1718 ( .LO ( optlc_net_1549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1719 ( .LO ( optlc_net_1550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1720 ( .LO ( optlc_net_1551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1721 ( .LO ( optlc_net_1552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1722 ( .LO ( optlc_net_1553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1723 ( .LO ( optlc_net_1554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1724 ( .LO ( optlc_net_1555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1725 ( .LO ( optlc_net_1556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1726 ( .LO ( optlc_net_1557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1727 ( .LO ( optlc_net_1558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1728 ( .LO ( optlc_net_1559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1729 ( .LO ( optlc_net_1560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1730 ( .LO ( optlc_net_1561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1731 ( .LO ( optlc_net_1562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1732 ( .LO ( optlc_net_1563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1733 ( .LO ( optlc_net_1564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1734 ( .LO ( optlc_net_1565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1735 ( .LO ( optlc_net_1566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1736 ( .LO ( optlc_net_1567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1737 ( .LO ( optlc_net_1568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1738 ( .LO ( optlc_net_1569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1739 ( .LO ( optlc_net_1570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1740 ( .LO ( optlc_net_1571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1741 ( .LO ( optlc_net_1572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1742 ( .LO ( optlc_net_1573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1743 ( .LO ( optlc_net_1574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1744 ( .LO ( optlc_net_1575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1745 ( .LO ( optlc_net_1576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1746 ( .LO ( optlc_net_1577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1747 ( .LO ( optlc_net_1578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1748 ( .LO ( optlc_net_1579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1749 ( .LO ( optlc_net_1580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1750 ( .LO ( optlc_net_1581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1751 ( .LO ( optlc_net_1582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1752 ( .LO ( optlc_net_1583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1753 ( .LO ( optlc_net_1584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1754 ( .LO ( optlc_net_1585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1755 ( .LO ( optlc_net_1586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1756 ( .LO ( optlc_net_1587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1757 ( .LO ( optlc_net_1588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1758 ( .LO ( optlc_net_1589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1759 ( .LO ( optlc_net_1590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1760 ( .LO ( optlc_net_1591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1761 ( .LO ( optlc_net_1592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1762 ( .LO ( optlc_net_1593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1763 ( .LO ( optlc_net_1594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1764 ( .LO ( optlc_net_1595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1765 ( .LO ( optlc_net_1596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1766 ( .LO ( optlc_net_1597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1767 ( .LO ( optlc_net_1598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1768 ( .LO ( optlc_net_1599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1769 ( .LO ( optlc_net_1600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1770 ( .LO ( optlc_net_1601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1771 ( .LO ( optlc_net_1602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1772 ( .LO ( optlc_net_1603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1773 ( .LO ( optlc_net_1604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1774 ( .LO ( optlc_net_1605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1775 ( .LO ( optlc_net_1606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1776 ( .LO ( optlc_net_1607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1777 ( .LO ( optlc_net_1608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1778 ( .LO ( optlc_net_1609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1779 ( .LO ( optlc_net_1610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1780 ( .LO ( optlc_net_1611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1781 ( .LO ( optlc_net_1612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1782 ( .LO ( optlc_net_1613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1783 ( .LO ( optlc_net_1614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1784 ( .LO ( optlc_net_1615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1785 ( .LO ( optlc_net_1616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1787 ( .LO ( optlc_net_1617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1788 ( .LO ( optlc_net_1618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1789 ( .LO ( optlc_net_1619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1790 ( .LO ( optlc_net_1620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1791 ( .LO ( optlc_net_1621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1792 ( .LO ( optlc_net_1622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1793 ( .LO ( optlc_net_1623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1794 ( .LO ( optlc_net_1624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1795 ( .LO ( optlc_net_1625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1796 ( .LO ( optlc_net_1626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1797 ( .LO ( optlc_net_1627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1798 ( .LO ( optlc_net_1628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1799 ( .LO ( optlc_net_1629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1800 ( .LO ( optlc_net_1630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1801 ( .LO ( optlc_net_1631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1802 ( .LO ( optlc_net_1632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1803 ( .LO ( optlc_net_1633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1804 ( .LO ( optlc_net_1634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1805 ( .LO ( optlc_net_1635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1806 ( .LO ( optlc_net_1636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1807 ( .LO ( optlc_net_1637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1808 ( .LO ( optlc_net_1638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1809 ( .LO ( optlc_net_1639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1810 ( .LO ( optlc_net_1640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1811 ( .LO ( optlc_net_1641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1812 ( .LO ( optlc_net_1642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1813 ( .LO ( optlc_net_1643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1814 ( .LO ( optlc_net_1644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1815 ( .LO ( optlc_net_1645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1816 ( .LO ( optlc_net_1646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1817 ( .LO ( optlc_net_1647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1818 ( .LO ( optlc_net_1648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1819 ( .LO ( optlc_net_1649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1821 ( .LO ( optlc_net_1650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1822 ( .LO ( optlc_net_1651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1823 ( .LO ( optlc_net_1652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1824 ( .LO ( optlc_net_1653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1825 ( .LO ( optlc_net_1654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1826 ( .LO ( optlc_net_1655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1827 ( .LO ( optlc_net_1656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1828 ( .LO ( optlc_net_1657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1829 ( .LO ( optlc_net_1658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1830 ( .LO ( optlc_net_1659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1831 ( .LO ( optlc_net_1660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1832 ( .LO ( optlc_net_1661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1833 ( .LO ( optlc_net_1662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1834 ( .LO ( optlc_net_1663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1835 ( .LO ( optlc_net_1664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1836 ( .LO ( optlc_net_1665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1837 ( .LO ( optlc_net_1666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1838 ( .LO ( optlc_net_1667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1839 ( .LO ( optlc_net_1668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1840 ( .LO ( optlc_net_1669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1842 ( .LO ( optlc_net_1670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1843 ( .LO ( optlc_net_1671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1844 ( .LO ( optlc_net_1672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1845 ( .LO ( optlc_net_1673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1846 ( .LO ( optlc_net_1674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1847 ( .LO ( optlc_net_1675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1849 ( .LO ( optlc_net_1676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1850 ( .LO ( optlc_net_1677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1851 ( .LO ( optlc_net_1678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1852 ( .LO ( optlc_net_1679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1853 ( .LO ( optlc_net_1680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1854 ( .LO ( optlc_net_1681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1855 ( .LO ( optlc_net_1682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1856 ( .LO ( optlc_net_1683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1857 ( .LO ( optlc_net_1684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1859 ( .LO ( optlc_net_1685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1860 ( .LO ( optlc_net_1686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1861 ( .LO ( optlc_net_1687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1862 ( .LO ( optlc_net_1688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1863 ( .LO ( optlc_net_1689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1864 ( .LO ( optlc_net_1690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1865 ( .LO ( optlc_net_1691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1866 ( .LO ( optlc_net_1692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1867 ( .LO ( optlc_net_1693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1868 ( .LO ( optlc_net_1694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1869 ( .LO ( optlc_net_1695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1870 ( .LO ( optlc_net_1696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1871 ( .LO ( optlc_net_1697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1872 ( .LO ( optlc_net_1698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1873 ( .LO ( optlc_net_1699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1875 ( .LO ( optlc_net_1700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1876 ( .LO ( optlc_net_1701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1877 ( .LO ( optlc_net_1702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1878 ( .LO ( optlc_net_1703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1879 ( .LO ( optlc_net_1704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1880 ( .LO ( optlc_net_1705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1881 ( .LO ( optlc_net_1706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1882 ( .LO ( optlc_net_1707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1884 ( .LO ( optlc_net_1708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1885 ( .LO ( optlc_net_1709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1886 ( .LO ( optlc_net_1710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1887 ( .LO ( optlc_net_1711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1888 ( .LO ( optlc_net_1712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1889 ( .LO ( optlc_net_1713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1891 ( .LO ( optlc_net_1714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1893 ( .LO ( optlc_net_1715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1894 ( .LO ( optlc_net_1716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1895 ( .LO ( optlc_net_1717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1896 ( .LO ( optlc_net_1718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1897 ( .LO ( optlc_net_1719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1898 ( .LO ( optlc_net_1720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1899 ( .LO ( optlc_net_1721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1901 ( .LO ( optlc_net_1722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1903 ( .LO ( optlc_net_1723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1904 ( .LO ( optlc_net_1724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1906 ( .LO ( optlc_net_1725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1907 ( .LO ( optlc_net_1726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1908 ( .LO ( optlc_net_1727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1909 ( .LO ( optlc_net_1728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1911 ( .LO ( optlc_net_1729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1912 ( .LO ( optlc_net_1730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1913 ( .LO ( optlc_net_1731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1914 ( .LO ( optlc_net_1732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1915 ( .LO ( optlc_net_1733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1916 ( .LO ( optlc_net_1734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1917 ( .LO ( optlc_net_1735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1918 ( .LO ( optlc_net_1736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1919 ( .LO ( optlc_net_1737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1921 ( .LO ( optlc_net_1738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1922 ( .LO ( optlc_net_1739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1923 ( .LO ( optlc_net_1740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1924 ( .LO ( optlc_net_1741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1926 ( .LO ( optlc_net_1742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1928 ( .LO ( optlc_net_1743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1929 ( .LO ( optlc_net_1744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1931 ( .LO ( optlc_net_1745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1932 ( .LO ( optlc_net_1746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1933 ( .LO ( optlc_net_1747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1934 ( .LO ( optlc_net_1748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1935 ( .LO ( optlc_net_1749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1936 ( .LO ( optlc_net_1750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1937 ( .LO ( optlc_net_1751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1938 ( .LO ( optlc_net_1752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1939 ( .LO ( optlc_net_1753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1941 ( .LO ( optlc_net_1754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1942 ( .LO ( optlc_net_1755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1944 ( .LO ( optlc_net_1756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1945 ( .LO ( optlc_net_1757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1946 ( .LO ( optlc_net_1758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1948 ( .LO ( optlc_net_1759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1949 ( .LO ( optlc_net_1760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1950 ( .LO ( optlc_net_1761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1951 ( .LO ( optlc_net_1762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1953 ( .LO ( optlc_net_1763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1955 ( .LO ( optlc_net_1764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1956 ( .LO ( optlc_net_1765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1957 ( .LO ( optlc_net_1766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1959 ( .LO ( optlc_net_1767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1960 ( .LO ( optlc_net_1768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1961 ( .LO ( optlc_net_1769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1962 ( .LO ( optlc_net_1770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1963 ( .LO ( optlc_net_1771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1965 ( .LO ( optlc_net_1772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1966 ( .LO ( optlc_net_1773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1967 ( .LO ( optlc_net_1774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1968 ( .LO ( optlc_net_1775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1970 ( .LO ( optlc_net_1776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1971 ( .LO ( optlc_net_1777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1972 ( .LO ( optlc_net_1778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1974 ( .LO ( optlc_net_1779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1975 ( .LO ( optlc_net_1780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1977 ( .LO ( optlc_net_1781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1979 ( .LO ( optlc_net_1782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1980 ( .LO ( optlc_net_1783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1981 ( .LO ( optlc_net_1784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1982 ( .LO ( optlc_net_1785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1983 ( .LO ( optlc_net_1786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1985 ( .LO ( optlc_net_1787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1987 ( .LO ( optlc_net_1788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1988 ( .LO ( optlc_net_1789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1989 ( .LO ( optlc_net_1790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1990 ( .LO ( optlc_net_1791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1991 ( .LO ( optlc_net_1792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1993 ( .LO ( optlc_net_1793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1995 ( .LO ( optlc_net_1794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1996 ( .LO ( optlc_net_1795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1998 ( .LO ( optlc_net_1796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2000 ( .LO ( optlc_net_1797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2001 ( .LO ( optlc_net_1798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2002 ( .LO ( optlc_net_1799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2003 ( .LO ( optlc_net_1800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2005 ( .LO ( optlc_net_1801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2006 ( .LO ( optlc_net_1802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2007 ( .LO ( optlc_net_1803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2008 ( .LO ( optlc_net_1804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2009 ( .LO ( optlc_net_1805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2010 ( .LO ( optlc_net_1806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2011 ( .LO ( optlc_net_1807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2013 ( .LO ( optlc_net_1808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2014 ( .LO ( optlc_net_1809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2015 ( .LO ( optlc_net_1810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2017 ( .LO ( optlc_net_1811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2018 ( .LO ( optlc_net_1812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2019 ( .LO ( optlc_net_1813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2020 ( .LO ( optlc_net_1814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2022 ( .LO ( optlc_net_1815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2023 ( .LO ( optlc_net_1816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2025 ( .LO ( optlc_net_1817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2027 ( .LO ( optlc_net_1818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2028 ( .LO ( optlc_net_1819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2029 ( .LO ( optlc_net_1820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2031 ( .LO ( optlc_net_1821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2032 ( .LO ( optlc_net_1822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2033 ( .LO ( optlc_net_1823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2035 ( .LO ( optlc_net_1824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2036 ( .LO ( optlc_net_1825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2037 ( .LO ( optlc_net_1826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2038 ( .LO ( optlc_net_1827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2039 ( .LO ( optlc_net_1828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2040 ( .LO ( optlc_net_1829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2041 ( .LO ( optlc_net_1830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2043 ( .LO ( optlc_net_1831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2045 ( .LO ( optlc_net_1832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2046 ( .LO ( optlc_net_1833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2047 ( .LO ( optlc_net_1834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2048 ( .LO ( optlc_net_1835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2049 ( .LO ( optlc_net_1836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2050 ( .LO ( optlc_net_1837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2051 ( .LO ( optlc_net_1838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2052 ( .LO ( optlc_net_1839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2053 ( .LO ( optlc_net_1840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2054 ( .LO ( optlc_net_1841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2055 ( .LO ( optlc_net_1842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2056 ( .LO ( optlc_net_1843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2057 ( .LO ( optlc_net_1844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2058 ( .LO ( optlc_net_1845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2059 ( .LO ( optlc_net_1846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2060 ( .LO ( optlc_net_1847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2061 ( .LO ( optlc_net_1848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2062 ( .LO ( optlc_net_1849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2063 ( .LO ( optlc_net_1850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2064 ( .LO ( optlc_net_1851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2065 ( .LO ( optlc_net_1852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2066 ( .LO ( optlc_net_1853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2067 ( .LO ( optlc_net_1854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2068 ( .LO ( optlc_net_1855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2069 ( .LO ( optlc_net_1856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2070 ( .LO ( optlc_net_1857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2071 ( .LO ( optlc_net_1858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2072 ( .LO ( optlc_net_1859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2073 ( .LO ( optlc_net_1860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2075 ( .LO ( optlc_net_1861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2076 ( .LO ( optlc_net_1862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2077 ( .LO ( optlc_net_1863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2079 ( .LO ( optlc_net_1864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2080 ( .LO ( optlc_net_1865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2081 ( .LO ( optlc_net_1866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2082 ( .LO ( optlc_net_1867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2083 ( .LO ( optlc_net_1868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2084 ( .LO ( optlc_net_1869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2085 ( .LO ( optlc_net_1870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2086 ( .LO ( optlc_net_1871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2087 ( .LO ( optlc_net_1872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2089 ( .LO ( optlc_net_1873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2090 ( .LO ( optlc_net_1874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2091 ( .LO ( optlc_net_1875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2092 ( .LO ( optlc_net_1876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2093 ( .LO ( optlc_net_1877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2094 ( .LO ( optlc_net_1878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2095 ( .LO ( optlc_net_1879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2096 ( .LO ( optlc_net_1880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2097 ( .LO ( optlc_net_1881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2098 ( .LO ( optlc_net_1882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2099 ( .LO ( optlc_net_1883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2101 ( .LO ( optlc_net_1884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2102 ( .LO ( optlc_net_1885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2103 ( .LO ( optlc_net_1886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2105 ( .LO ( optlc_net_1887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2106 ( .LO ( optlc_net_1888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2107 ( .LO ( optlc_net_1889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2108 ( .LO ( optlc_net_1890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2109 ( .LO ( optlc_net_1891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2110 ( .LO ( optlc_net_1892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2111 ( .LO ( optlc_net_1893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2112 ( .LO ( optlc_net_1894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2114 ( .LO ( optlc_net_1895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2116 ( .LO ( optlc_net_1896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2117 ( .LO ( optlc_net_1897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2119 ( .LO ( optlc_net_1898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2120 ( .LO ( optlc_net_1899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2121 ( .LO ( optlc_net_1900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2122 ( .LO ( optlc_net_1901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2124 ( .LO ( optlc_net_1902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2125 ( .LO ( optlc_net_1903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2126 ( .LO ( optlc_net_1904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2127 ( .LO ( optlc_net_1905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2129 ( .LO ( optlc_net_1906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2130 ( .LO ( optlc_net_1907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2134 ( .LO ( optlc_net_1910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2138 ( .LO ( optlc_net_1913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2140 ( .LO ( optlc_net_1915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2141 ( .LO ( optlc_net_1916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2142 ( .LO ( optlc_net_1917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2143 ( .LO ( optlc_net_1918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2146 ( .LO ( optlc_net_1920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2147 ( .LO ( optlc_net_1921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2149 ( .LO ( optlc_net_1923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2153 ( .LO ( optlc_net_1927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2154 ( .LO ( optlc_net_1928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2155 ( .LO ( optlc_net_1929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2156 ( .LO ( optlc_net_1930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2157 ( .LO ( optlc_net_1931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2158 ( .LO ( optlc_net_1932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2159 ( .LO ( optlc_net_1933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2160 ( .LO ( optlc_net_1934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2164 ( .LO ( optlc_net_1938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2166 ( .LO ( optlc_net_1940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2168 ( .LO ( optlc_net_1942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2170 ( .LO ( optlc_net_1944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2172 ( .LO ( optlc_net_1946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2174 ( .LO ( optlc_net_1948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2176 ( .LO ( optlc_net_1950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2178 ( .LO ( optlc_net_1952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2183 ( .LO ( optlc_net_1956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2185 ( .LO ( optlc_net_1958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2189 ( .LO ( optlc_net_1962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2191 ( .LO ( optlc_net_1964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2193 ( .LO ( optlc_net_1966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2195 ( .LO ( optlc_net_1968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2197 ( .LO ( optlc_net_1970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2199 ( .LO ( optlc_net_1972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2201 ( .LO ( optlc_net_1974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2203 ( .LO ( optlc_net_1976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2208 ( .LO ( optlc_net_1981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2213 ( .LO ( optlc_net_1986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2215 ( .LO ( optlc_net_1988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_1989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2217 ( .LO ( optlc_net_1990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_1991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2219 ( .LO ( optlc_net_1992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_1993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2221 ( .LO ( optlc_net_1994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_1995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2223 ( .LO ( optlc_net_1996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_1997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_1998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_1999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2227 ( .LO ( optlc_net_2000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2228 ( .LO ( optlc_net_2001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2229 ( .LO ( optlc_net_2002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2230 ( .LO ( optlc_net_2003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2231 ( .LO ( optlc_net_2004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2232 ( .LO ( optlc_net_2005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_2006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2234 ( .LO ( optlc_net_2007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_2008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_2009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_2010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_2011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_2012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_2013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2241 ( .LO ( optlc_net_2014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_2015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_2016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2244 ( .LO ( optlc_net_2017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2245 ( .LO ( optlc_net_2018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2246 ( .LO ( optlc_net_2019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_2020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_2021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2249 ( .LO ( optlc_net_2022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2250 ( .LO ( optlc_net_2023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2251 ( .LO ( optlc_net_2024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2252 ( .LO ( optlc_net_2025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2253 ( .LO ( optlc_net_2026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2254 ( .LO ( optlc_net_2027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2255 ( .LO ( optlc_net_2028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2256 ( .LO ( optlc_net_2029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2257 ( .LO ( optlc_net_2030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2258 ( .LO ( optlc_net_2031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2259 ( .LO ( optlc_net_2032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2260 ( .LO ( optlc_net_2033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2261 ( .LO ( optlc_net_2034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2262 ( .LO ( optlc_net_2035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2263 ( .LO ( optlc_net_2036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2264 ( .LO ( optlc_net_2037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2265 ( .LO ( optlc_net_2038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2266 ( .LO ( optlc_net_2039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2267 ( .LO ( optlc_net_2040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2268 ( .LO ( optlc_net_2041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2269 ( .LO ( optlc_net_2042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2270 ( .LO ( optlc_net_2043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2271 ( .LO ( optlc_net_2044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2272 ( .LO ( optlc_net_2045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2273 ( .LO ( optlc_net_2046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2274 ( .LO ( optlc_net_2047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2275 ( .LO ( optlc_net_2048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2276 ( .LO ( optlc_net_2049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2277 ( .LO ( optlc_net_2050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2278 ( .LO ( optlc_net_2051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2279 ( .LO ( optlc_net_2052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2280 ( .LO ( optlc_net_2053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2281 ( .LO ( optlc_net_2054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2282 ( .LO ( optlc_net_2055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2283 ( .LO ( optlc_net_2056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2284 ( .LO ( optlc_net_2057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2285 ( .LO ( optlc_net_2058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2286 ( .LO ( optlc_net_2059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2287 ( .LO ( optlc_net_2060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2288 ( .LO ( optlc_net_2061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2289 ( .LO ( optlc_net_2062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2290 ( .LO ( optlc_net_2063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2291 ( .LO ( optlc_net_2064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2292 ( .LO ( optlc_net_2065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2293 ( .LO ( optlc_net_2066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2294 ( .LO ( optlc_net_2067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2295 ( .LO ( optlc_net_2068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2296 ( .LO ( optlc_net_2069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2298 ( .LO ( optlc_net_2070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2299 ( .LO ( optlc_net_2071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2300 ( .LO ( optlc_net_2072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2301 ( .LO ( optlc_net_2073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2302 ( .LO ( optlc_net_2074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2303 ( .LO ( optlc_net_2075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2304 ( .LO ( optlc_net_2076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2305 ( .LO ( optlc_net_2077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2306 ( .LO ( optlc_net_2078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2307 ( .LO ( optlc_net_2079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2308 ( .LO ( optlc_net_2080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2309 ( .LO ( optlc_net_2081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2310 ( .LO ( optlc_net_2082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2311 ( .LO ( optlc_net_2083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2312 ( .LO ( optlc_net_2084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2313 ( .LO ( optlc_net_2085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2314 ( .LO ( optlc_net_2086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2315 ( .LO ( optlc_net_2087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2316 ( .LO ( optlc_net_2088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2317 ( .LO ( optlc_net_2089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2318 ( .LO ( optlc_net_2090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2319 ( .LO ( optlc_net_2091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2321 ( .LO ( optlc_net_2092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2322 ( .LO ( optlc_net_2093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2323 ( .LO ( optlc_net_2094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2324 ( .LO ( optlc_net_2095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2325 ( .LO ( optlc_net_2096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2326 ( .LO ( optlc_net_2097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2327 ( .LO ( optlc_net_2098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2328 ( .LO ( optlc_net_2099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2329 ( .LO ( optlc_net_2100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2331 ( .LO ( optlc_net_2101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2332 ( .LO ( optlc_net_2102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2333 ( .LO ( optlc_net_2103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2334 ( .LO ( optlc_net_2104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2335 ( .LO ( optlc_net_2105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2336 ( .LO ( optlc_net_2106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2337 ( .LO ( optlc_net_2107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2338 ( .LO ( optlc_net_2108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2339 ( .LO ( optlc_net_2109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2340 ( .LO ( optlc_net_2110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2341 ( .LO ( optlc_net_2111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2342 ( .LO ( optlc_net_2112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2344 ( .LO ( optlc_net_2113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2345 ( .LO ( optlc_net_2114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2346 ( .LO ( optlc_net_2115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2347 ( .LO ( optlc_net_2116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2348 ( .LO ( optlc_net_2117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2349 ( .LO ( optlc_net_2118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2350 ( .LO ( optlc_net_2119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2351 ( .LO ( optlc_net_2120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2352 ( .LO ( optlc_net_2121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2354 ( .LO ( optlc_net_2122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2355 ( .LO ( optlc_net_2123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2356 ( .LO ( optlc_net_2124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2357 ( .LO ( optlc_net_2125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2358 ( .LO ( optlc_net_2126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2359 ( .LO ( optlc_net_2127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2360 ( .LO ( optlc_net_2128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2361 ( .LO ( optlc_net_2129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2362 ( .LO ( optlc_net_2130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2363 ( .LO ( optlc_net_2131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2364 ( .LO ( optlc_net_2132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2365 ( .LO ( optlc_net_2133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2366 ( .LO ( optlc_net_2134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2367 ( .LO ( optlc_net_2135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2368 ( .LO ( optlc_net_2136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2369 ( .LO ( optlc_net_2137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2370 ( .LO ( optlc_net_2138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2371 ( .LO ( optlc_net_2139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2372 ( .LO ( optlc_net_2140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2373 ( .LO ( optlc_net_2141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2374 ( .LO ( optlc_net_2142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2375 ( .LO ( optlc_net_2143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2376 ( .LO ( optlc_net_2144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2377 ( .LO ( optlc_net_2145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2378 ( .LO ( optlc_net_2146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2379 ( .LO ( optlc_net_2147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2380 ( .LO ( optlc_net_2148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2381 ( .LO ( optlc_net_2149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2382 ( .LO ( optlc_net_2150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2383 ( .LO ( optlc_net_2151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2384 ( .LO ( optlc_net_2152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2385 ( .LO ( optlc_net_2153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2386 ( .LO ( optlc_net_2154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2387 ( .LO ( optlc_net_2155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2388 ( .LO ( optlc_net_2156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2389 ( .LO ( optlc_net_2157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2391 ( .LO ( optlc_net_2158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2392 ( .LO ( optlc_net_2159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2393 ( .LO ( optlc_net_2160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2395 ( .LO ( optlc_net_2161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2396 ( .LO ( optlc_net_2162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2397 ( .LO ( optlc_net_2163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2398 ( .LO ( optlc_net_2164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2400 ( .LO ( optlc_net_2165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2402 ( .LO ( optlc_net_2166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2403 ( .LO ( optlc_net_2167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2404 ( .LO ( optlc_net_2168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2405 ( .LO ( optlc_net_2169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2407 ( .LO ( optlc_net_2170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2408 ( .LO ( optlc_net_2171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2409 ( .LO ( optlc_net_2172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2410 ( .LO ( optlc_net_2173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2412 ( .LO ( optlc_net_2174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2413 ( .LO ( optlc_net_2175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2414 ( .LO ( optlc_net_2176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2416 ( .LO ( optlc_net_2177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2417 ( .LO ( optlc_net_2178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2418 ( .LO ( optlc_net_2179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2419 ( .LO ( optlc_net_2180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2420 ( .LO ( optlc_net_2181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2421 ( .LO ( optlc_net_2182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2422 ( .LO ( optlc_net_2183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2423 ( .LO ( optlc_net_2184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2424 ( .LO ( optlc_net_2185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2425 ( .LO ( optlc_net_2186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2427 ( .LO ( optlc_net_2187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2428 ( .LO ( optlc_net_2188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2429 ( .LO ( optlc_net_2189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2430 ( .LO ( optlc_net_2190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2431 ( .LO ( optlc_net_2191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2432 ( .LO ( optlc_net_2192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2434 ( .LO ( optlc_net_2193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2436 ( .LO ( optlc_net_2194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2437 ( .LO ( optlc_net_2195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2438 ( .LO ( optlc_net_2196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2439 ( .LO ( optlc_net_2197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2440 ( .LO ( optlc_net_2198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2441 ( .LO ( optlc_net_2199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2442 ( .LO ( optlc_net_2200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2443 ( .LO ( optlc_net_2201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2444 ( .LO ( optlc_net_2202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2445 ( .LO ( optlc_net_2203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2446 ( .LO ( optlc_net_2204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2447 ( .LO ( optlc_net_2205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2448 ( .LO ( optlc_net_2206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2449 ( .LO ( optlc_net_2207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2450 ( .LO ( optlc_net_2208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2451 ( .LO ( optlc_net_2209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2452 ( .LO ( optlc_net_2210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2453 ( .LO ( optlc_net_2211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2454 ( .LO ( optlc_net_2212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2455 ( .LO ( optlc_net_2213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2456 ( .LO ( optlc_net_2214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2457 ( .LO ( optlc_net_2215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2458 ( .LO ( optlc_net_2216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2459 ( .LO ( optlc_net_2217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2460 ( .LO ( optlc_net_2218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2461 ( .LO ( optlc_net_2219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2462 ( .LO ( optlc_net_2220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2463 ( .LO ( optlc_net_2221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2464 ( .LO ( optlc_net_2222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2465 ( .LO ( optlc_net_2223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2466 ( .LO ( optlc_net_2224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2467 ( .LO ( optlc_net_2225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2468 ( .LO ( optlc_net_2226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2469 ( .LO ( optlc_net_2227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2470 ( .LO ( optlc_net_2228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2471 ( .LO ( optlc_net_2229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2472 ( .LO ( optlc_net_2230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2474 ( .LO ( optlc_net_2231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2475 ( .LO ( optlc_net_2232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2476 ( .LO ( optlc_net_2233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2477 ( .LO ( optlc_net_2234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2478 ( .LO ( optlc_net_2235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2479 ( .LO ( optlc_net_2236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2481 ( .LO ( optlc_net_2237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2482 ( .LO ( optlc_net_2238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2483 ( .LO ( optlc_net_2239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2484 ( .LO ( optlc_net_2240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2485 ( .LO ( optlc_net_2241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2486 ( .LO ( optlc_net_2242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2487 ( .LO ( optlc_net_2243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2488 ( .LO ( optlc_net_2244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2489 ( .LO ( optlc_net_2245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2490 ( .LO ( optlc_net_2246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2491 ( .LO ( optlc_net_2247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2492 ( .LO ( optlc_net_2248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2493 ( .LO ( optlc_net_2249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2494 ( .LO ( optlc_net_2250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2495 ( .LO ( optlc_net_2251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2496 ( .LO ( optlc_net_2252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2497 ( .LO ( optlc_net_2253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2498 ( .LO ( optlc_net_2254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2499 ( .LO ( optlc_net_2255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2500 ( .LO ( optlc_net_2256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2501 ( .LO ( optlc_net_2257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2502 ( .LO ( optlc_net_2258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2503 ( .LO ( optlc_net_2259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2504 ( .LO ( optlc_net_2260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2505 ( .LO ( optlc_net_2261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2506 ( .LO ( optlc_net_2262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2507 ( .LO ( optlc_net_2263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2508 ( .LO ( optlc_net_2264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2509 ( .LO ( optlc_net_2265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2510 ( .LO ( optlc_net_2266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2511 ( .LO ( optlc_net_2267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2512 ( .LO ( optlc_net_2268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2513 ( .LO ( optlc_net_2269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2515 ( .LO ( optlc_net_2270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2516 ( .LO ( optlc_net_2271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2517 ( .LO ( optlc_net_2272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2518 ( .LO ( optlc_net_2273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2519 ( .LO ( optlc_net_2274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2520 ( .LO ( optlc_net_2275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2521 ( .LO ( optlc_net_2276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2522 ( .LO ( optlc_net_2277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2523 ( .LO ( optlc_net_2278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2524 ( .LO ( optlc_net_2279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2525 ( .LO ( optlc_net_2280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2526 ( .LO ( optlc_net_2281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2527 ( .LO ( optlc_net_2282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2528 ( .LO ( optlc_net_2283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2529 ( .LO ( optlc_net_2284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2530 ( .LO ( optlc_net_2285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2531 ( .LO ( optlc_net_2286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2532 ( .LO ( optlc_net_2287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2533 ( .LO ( optlc_net_2288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2534 ( .LO ( optlc_net_2289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2535 ( .LO ( optlc_net_2290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2536 ( .LO ( optlc_net_2291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2537 ( .LO ( optlc_net_2292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2538 ( .LO ( optlc_net_2293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2539 ( .LO ( optlc_net_2294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2540 ( .LO ( optlc_net_2295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2541 ( .LO ( optlc_net_2296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2542 ( .LO ( optlc_net_2297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2543 ( .LO ( optlc_net_2298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2544 ( .LO ( optlc_net_2299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2545 ( .LO ( optlc_net_2300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2546 ( .LO ( optlc_net_2301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2547 ( .LO ( optlc_net_2302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2548 ( .LO ( optlc_net_2303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2549 ( .LO ( optlc_net_2304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2550 ( .LO ( optlc_net_2305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2551 ( .LO ( optlc_net_2306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2552 ( .LO ( optlc_net_2307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2553 ( .LO ( optlc_net_2308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2554 ( .LO ( optlc_net_2309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2555 ( .LO ( optlc_net_2310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2556 ( .LO ( optlc_net_2311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2557 ( .LO ( optlc_net_2312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2558 ( .LO ( optlc_net_2313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2559 ( .LO ( optlc_net_2314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2560 ( .LO ( optlc_net_2315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2561 ( .LO ( optlc_net_2316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2562 ( .LO ( optlc_net_2317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2563 ( .LO ( optlc_net_2318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2564 ( .LO ( optlc_net_2319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2565 ( .LO ( optlc_net_2320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2566 ( .LO ( optlc_net_2321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2567 ( .LO ( optlc_net_2322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2568 ( .LO ( optlc_net_2323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2569 ( .LO ( optlc_net_2324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2570 ( .LO ( optlc_net_2325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2571 ( .LO ( optlc_net_2326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2572 ( .LO ( optlc_net_2327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2573 ( .LO ( optlc_net_2328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2574 ( .LO ( optlc_net_2329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2575 ( .LO ( optlc_net_2330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2576 ( .LO ( optlc_net_2331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2577 ( .LO ( optlc_net_2332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2578 ( .LO ( optlc_net_2333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2579 ( .LO ( optlc_net_2334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2580 ( .LO ( optlc_net_2335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2581 ( .LO ( optlc_net_2336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2582 ( .LO ( optlc_net_2337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2583 ( .LO ( optlc_net_2338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2584 ( .LO ( optlc_net_2339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2585 ( .LO ( optlc_net_2340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2586 ( .LO ( optlc_net_2341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2587 ( .LO ( optlc_net_2342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2588 ( .LO ( optlc_net_2343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2589 ( .LO ( optlc_net_2344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2590 ( .LO ( optlc_net_2345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2591 ( .LO ( optlc_net_2346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2592 ( .LO ( optlc_net_2347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2593 ( .LO ( optlc_net_2348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2594 ( .LO ( optlc_net_2349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2595 ( .LO ( optlc_net_2350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2596 ( .LO ( optlc_net_2351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2597 ( .LO ( optlc_net_2352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2598 ( .LO ( optlc_net_2353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2599 ( .LO ( optlc_net_2354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2600 ( .LO ( optlc_net_2355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2601 ( .LO ( optlc_net_2356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2602 ( .LO ( optlc_net_2357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2603 ( .LO ( optlc_net_2358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2604 ( .LO ( optlc_net_2359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2605 ( .LO ( optlc_net_2360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2606 ( .LO ( optlc_net_2361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2607 ( .LO ( optlc_net_2362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2608 ( .LO ( optlc_net_2363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2609 ( .LO ( optlc_net_2364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2610 ( .LO ( optlc_net_2365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2611 ( .LO ( optlc_net_2366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2612 ( .LO ( optlc_net_2367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2613 ( .LO ( optlc_net_2368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2614 ( .LO ( optlc_net_2369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2615 ( .LO ( optlc_net_2370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2616 ( .LO ( optlc_net_2371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2617 ( .LO ( optlc_net_2372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2618 ( .LO ( optlc_net_2373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2619 ( .LO ( optlc_net_2374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2620 ( .LO ( optlc_net_2375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2621 ( .LO ( optlc_net_2376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2622 ( .LO ( optlc_net_2377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2623 ( .LO ( optlc_net_2378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2624 ( .LO ( optlc_net_2379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2625 ( .LO ( optlc_net_2380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2626 ( .LO ( optlc_net_2381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2627 ( .LO ( optlc_net_2382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2628 ( .LO ( optlc_net_2383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2629 ( .LO ( optlc_net_2384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2630 ( .LO ( optlc_net_2385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2631 ( .LO ( optlc_net_2386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2632 ( .LO ( optlc_net_2387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2633 ( .LO ( optlc_net_2388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2634 ( .LO ( optlc_net_2389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2635 ( .LO ( optlc_net_2390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2636 ( .LO ( optlc_net_2391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2637 ( .LO ( optlc_net_2392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2638 ( .LO ( optlc_net_2393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2639 ( .LO ( optlc_net_2394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2640 ( .LO ( optlc_net_2395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2641 ( .LO ( optlc_net_2396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2642 ( .LO ( optlc_net_2397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2643 ( .LO ( optlc_net_2398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2644 ( .LO ( optlc_net_2399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2645 ( .LO ( optlc_net_2400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2646 ( .LO ( optlc_net_2401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2647 ( .LO ( optlc_net_2402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2648 ( .LO ( optlc_net_2403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2649 ( .LO ( optlc_net_2404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2650 ( .LO ( optlc_net_2405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2651 ( .LO ( optlc_net_2406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2652 ( .LO ( optlc_net_2407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2654 ( .LO ( optlc_net_2408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2655 ( .LO ( optlc_net_2409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2656 ( .LO ( optlc_net_2410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2657 ( .LO ( optlc_net_2411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2658 ( .LO ( optlc_net_2412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2659 ( .LO ( optlc_net_2413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2660 ( .LO ( optlc_net_2414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2661 ( .LO ( optlc_net_2415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2663 ( .LO ( optlc_net_2416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2665 ( .LO ( optlc_net_2417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2666 ( .LO ( optlc_net_2418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2667 ( .LO ( optlc_net_2419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2668 ( .LO ( optlc_net_2420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2669 ( .LO ( optlc_net_2421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2670 ( .LO ( optlc_net_2422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2671 ( .LO ( optlc_net_2423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2672 ( .LO ( optlc_net_2424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2673 ( .LO ( optlc_net_2425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2674 ( .LO ( optlc_net_2426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2675 ( .LO ( optlc_net_2427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2676 ( .LO ( optlc_net_2428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2677 ( .LO ( optlc_net_2429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2678 ( .LO ( optlc_net_2430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2679 ( .LO ( optlc_net_2431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2680 ( .LO ( optlc_net_2432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2682 ( .LO ( optlc_net_2433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2683 ( .LO ( optlc_net_2434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2684 ( .LO ( optlc_net_2435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2685 ( .LO ( optlc_net_2436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2686 ( .LO ( optlc_net_2437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2687 ( .LO ( optlc_net_2438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2688 ( .LO ( optlc_net_2439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2689 ( .LO ( optlc_net_2440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2690 ( .LO ( optlc_net_2441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2691 ( .LO ( optlc_net_2442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2692 ( .LO ( optlc_net_2443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2693 ( .LO ( optlc_net_2444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2694 ( .LO ( optlc_net_2445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2695 ( .LO ( optlc_net_2446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2696 ( .LO ( optlc_net_2447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2697 ( .LO ( optlc_net_2448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2698 ( .LO ( optlc_net_2449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2699 ( .LO ( optlc_net_2450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2700 ( .LO ( optlc_net_2451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2701 ( .LO ( optlc_net_2452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2702 ( .LO ( optlc_net_2453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2703 ( .LO ( optlc_net_2454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2704 ( .LO ( optlc_net_2455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2705 ( .LO ( optlc_net_2456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2706 ( .LO ( optlc_net_2457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2707 ( .LO ( optlc_net_2458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2708 ( .LO ( optlc_net_2459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2709 ( .LO ( optlc_net_2460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2710 ( .LO ( optlc_net_2461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2711 ( .LO ( optlc_net_2462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2712 ( .LO ( optlc_net_2463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2713 ( .LO ( optlc_net_2464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2714 ( .LO ( optlc_net_2465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2715 ( .LO ( optlc_net_2466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2716 ( .LO ( optlc_net_2467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2717 ( .LO ( optlc_net_2468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2718 ( .LO ( optlc_net_2469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2719 ( .LO ( optlc_net_2470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2720 ( .LO ( optlc_net_2471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2721 ( .LO ( optlc_net_2472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2722 ( .LO ( optlc_net_2473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2723 ( .LO ( optlc_net_2474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2724 ( .LO ( optlc_net_2475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2725 ( .LO ( optlc_net_2476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2726 ( .LO ( optlc_net_2477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2727 ( .LO ( optlc_net_2478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2728 ( .LO ( optlc_net_2479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2729 ( .LO ( optlc_net_2480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2730 ( .LO ( optlc_net_2481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2731 ( .LO ( optlc_net_2482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2732 ( .LO ( optlc_net_2483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2733 ( .LO ( optlc_net_2484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2734 ( .LO ( optlc_net_2485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2735 ( .LO ( optlc_net_2486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2736 ( .LO ( optlc_net_2487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2737 ( .LO ( optlc_net_2488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2738 ( .LO ( optlc_net_2489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2739 ( .LO ( optlc_net_2490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2740 ( .LO ( optlc_net_2491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2742 ( .LO ( optlc_net_2492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2743 ( .LO ( optlc_net_2493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2744 ( .LO ( optlc_net_2494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2745 ( .LO ( optlc_net_2495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2746 ( .LO ( optlc_net_2496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2747 ( .LO ( optlc_net_2497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2748 ( .LO ( optlc_net_2498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2749 ( .LO ( optlc_net_2499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2751 ( .LO ( optlc_net_2500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2752 ( .LO ( optlc_net_2501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2753 ( .LO ( optlc_net_2502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2754 ( .LO ( optlc_net_2503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2755 ( .LO ( optlc_net_2504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2756 ( .LO ( optlc_net_2505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2757 ( .LO ( optlc_net_2506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2758 ( .LO ( optlc_net_2507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2759 ( .LO ( optlc_net_2508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2760 ( .LO ( optlc_net_2509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2761 ( .LO ( optlc_net_2510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2762 ( .LO ( optlc_net_2511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2764 ( .LO ( optlc_net_2512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2766 ( .LO ( optlc_net_2513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2767 ( .LO ( optlc_net_2514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2768 ( .LO ( optlc_net_2515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2769 ( .LO ( optlc_net_2516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2770 ( .LO ( optlc_net_2517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2771 ( .LO ( optlc_net_2518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2772 ( .LO ( optlc_net_2519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2773 ( .LO ( optlc_net_2520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2774 ( .LO ( optlc_net_2521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2775 ( .LO ( optlc_net_2522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2776 ( .LO ( optlc_net_2523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2777 ( .LO ( optlc_net_2524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2778 ( .LO ( optlc_net_2525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2779 ( .LO ( optlc_net_2526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2780 ( .LO ( optlc_net_2527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2781 ( .LO ( optlc_net_2528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2783 ( .LO ( optlc_net_2529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2784 ( .LO ( optlc_net_2530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2785 ( .LO ( optlc_net_2531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2787 ( .LO ( optlc_net_2532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2788 ( .LO ( optlc_net_2533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2789 ( .LO ( optlc_net_2534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2790 ( .LO ( optlc_net_2535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2792 ( .LO ( optlc_net_2536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2793 ( .LO ( optlc_net_2537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2794 ( .LO ( optlc_net_2538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2795 ( .LO ( optlc_net_2539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2797 ( .LO ( optlc_net_2540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2798 ( .LO ( optlc_net_2541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2799 ( .LO ( optlc_net_2542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2800 ( .LO ( optlc_net_2543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2801 ( .LO ( optlc_net_2544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2802 ( .LO ( optlc_net_2545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2803 ( .LO ( optlc_net_2546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2804 ( .LO ( optlc_net_2547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2805 ( .LO ( optlc_net_2548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2806 ( .LO ( optlc_net_2549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2807 ( .LO ( optlc_net_2550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2808 ( .LO ( optlc_net_2551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2809 ( .LO ( optlc_net_2552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2810 ( .LO ( optlc_net_2553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2812 ( .LO ( optlc_net_2554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2813 ( .LO ( optlc_net_2555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2814 ( .LO ( optlc_net_2556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2815 ( .LO ( optlc_net_2557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2816 ( .LO ( optlc_net_2558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2817 ( .LO ( optlc_net_2559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2818 ( .LO ( optlc_net_2560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2819 ( .LO ( optlc_net_2561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2820 ( .LO ( optlc_net_2562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2821 ( .LO ( optlc_net_2563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2822 ( .LO ( optlc_net_2564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2823 ( .LO ( optlc_net_2565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2824 ( .LO ( optlc_net_2566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2826 ( .LO ( optlc_net_2567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2827 ( .LO ( optlc_net_2568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2828 ( .LO ( optlc_net_2569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2829 ( .LO ( optlc_net_2570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2830 ( .LO ( optlc_net_2571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2831 ( .LO ( optlc_net_2572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2832 ( .LO ( optlc_net_2573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2833 ( .LO ( optlc_net_2574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2834 ( .LO ( optlc_net_2575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2835 ( .LO ( optlc_net_2576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2836 ( .LO ( optlc_net_2577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2837 ( .LO ( optlc_net_2578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2838 ( .LO ( optlc_net_2579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2839 ( .LO ( optlc_net_2580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2840 ( .LO ( optlc_net_2581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2841 ( .LO ( optlc_net_2582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2842 ( .LO ( optlc_net_2583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2843 ( .LO ( optlc_net_2584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2844 ( .LO ( optlc_net_2585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2845 ( .LO ( optlc_net_2586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2846 ( .LO ( optlc_net_2587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2847 ( .LO ( optlc_net_2588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2848 ( .LO ( optlc_net_2589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2849 ( .LO ( optlc_net_2590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2850 ( .LO ( optlc_net_2591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2851 ( .LO ( optlc_net_2592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2852 ( .LO ( optlc_net_2593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2853 ( .LO ( optlc_net_2594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2854 ( .LO ( optlc_net_2595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2855 ( .LO ( optlc_net_2596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2856 ( .LO ( optlc_net_2597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2857 ( .LO ( optlc_net_2598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2858 ( .LO ( optlc_net_2599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2859 ( .LO ( optlc_net_2600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2860 ( .LO ( optlc_net_2601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2861 ( .LO ( optlc_net_2602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2862 ( .LO ( optlc_net_2603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2863 ( .LO ( optlc_net_2604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2864 ( .LO ( optlc_net_2605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2865 ( .LO ( optlc_net_2606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2866 ( .LO ( optlc_net_2607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2867 ( .LO ( optlc_net_2608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2868 ( .LO ( optlc_net_2609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2869 ( .LO ( optlc_net_2610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2870 ( .LO ( optlc_net_2611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2871 ( .LO ( optlc_net_2612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2872 ( .LO ( optlc_net_2613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2873 ( .LO ( optlc_net_2614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2874 ( .LO ( optlc_net_2615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2875 ( .LO ( optlc_net_2616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2876 ( .LO ( optlc_net_2617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2877 ( .LO ( optlc_net_2618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2878 ( .LO ( optlc_net_2619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2879 ( .LO ( optlc_net_2620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2880 ( .LO ( optlc_net_2621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2881 ( .LO ( optlc_net_2622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2882 ( .LO ( optlc_net_2623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2883 ( .LO ( optlc_net_2624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2884 ( .LO ( optlc_net_2625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2885 ( .LO ( optlc_net_2626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2886 ( .LO ( optlc_net_2627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2887 ( .LO ( optlc_net_2628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2888 ( .LO ( optlc_net_2629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2889 ( .LO ( optlc_net_2630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2890 ( .LO ( optlc_net_2631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2891 ( .LO ( optlc_net_2632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2892 ( .LO ( optlc_net_2633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2893 ( .LO ( optlc_net_2634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2894 ( .LO ( optlc_net_2635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2895 ( .LO ( optlc_net_2636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2896 ( .LO ( optlc_net_2637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2897 ( .LO ( optlc_net_2638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2898 ( .LO ( optlc_net_2639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2899 ( .LO ( optlc_net_2640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2900 ( .LO ( optlc_net_2641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2901 ( .LO ( optlc_net_2642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2902 ( .LO ( optlc_net_2643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2903 ( .LO ( optlc_net_2644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2904 ( .LO ( optlc_net_2645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2905 ( .LO ( optlc_net_2646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2906 ( .LO ( optlc_net_2647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2907 ( .LO ( optlc_net_2648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2908 ( .LO ( optlc_net_2649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2909 ( .LO ( optlc_net_2650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2910 ( .LO ( optlc_net_2651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2911 ( .LO ( optlc_net_2652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2912 ( .LO ( optlc_net_2653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2913 ( .LO ( optlc_net_2654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2914 ( .LO ( optlc_net_2655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2915 ( .LO ( optlc_net_2656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2916 ( .LO ( optlc_net_2657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2917 ( .LO ( optlc_net_2658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2918 ( .LO ( optlc_net_2659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2919 ( .LO ( optlc_net_2660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2920 ( .LO ( optlc_net_2661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2921 ( .LO ( optlc_net_2662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2922 ( .LO ( optlc_net_2663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2923 ( .LO ( optlc_net_2664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2924 ( .LO ( optlc_net_2665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2925 ( .LO ( optlc_net_2666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2926 ( .LO ( optlc_net_2667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2927 ( .LO ( optlc_net_2668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2928 ( .LO ( optlc_net_2669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2929 ( .LO ( optlc_net_2670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2930 ( .LO ( optlc_net_2671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2931 ( .LO ( optlc_net_2672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2932 ( .LO ( optlc_net_2673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2933 ( .LO ( optlc_net_2674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2934 ( .LO ( optlc_net_2675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2935 ( .LO ( optlc_net_2676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2936 ( .LO ( optlc_net_2677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2937 ( .LO ( optlc_net_2678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2938 ( .LO ( optlc_net_2679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2939 ( .LO ( optlc_net_2680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2940 ( .LO ( optlc_net_2681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2941 ( .LO ( optlc_net_2682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2942 ( .LO ( optlc_net_2683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2943 ( .LO ( optlc_net_2684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2944 ( .LO ( optlc_net_2685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2945 ( .LO ( optlc_net_2686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2946 ( .LO ( optlc_net_2687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2947 ( .LO ( optlc_net_2688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2948 ( .LO ( optlc_net_2689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2949 ( .LO ( optlc_net_2690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2950 ( .LO ( optlc_net_2691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2951 ( .LO ( optlc_net_2692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2952 ( .LO ( optlc_net_2693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2953 ( .LO ( optlc_net_2694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2954 ( .LO ( optlc_net_2695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2955 ( .LO ( optlc_net_2696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2956 ( .LO ( optlc_net_2697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2957 ( .LO ( optlc_net_2698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2958 ( .LO ( optlc_net_2699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2959 ( .LO ( optlc_net_2700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2960 ( .LO ( optlc_net_2701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2961 ( .LO ( optlc_net_2702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2962 ( .LO ( optlc_net_2703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2963 ( .LO ( optlc_net_2704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2964 ( .LO ( optlc_net_2705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2966 ( .LO ( optlc_net_2706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2967 ( .LO ( optlc_net_2707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2968 ( .LO ( optlc_net_2708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2969 ( .LO ( optlc_net_2709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2970 ( .LO ( optlc_net_2710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2971 ( .LO ( optlc_net_2711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2972 ( .LO ( optlc_net_2712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2973 ( .LO ( optlc_net_2713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2974 ( .LO ( optlc_net_2714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2976 ( .LO ( optlc_net_2715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2977 ( .LO ( optlc_net_2716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2978 ( .LO ( optlc_net_2717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2979 ( .LO ( optlc_net_2718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2980 ( .LO ( optlc_net_2719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2981 ( .LO ( optlc_net_2720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2982 ( .LO ( optlc_net_2721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2983 ( .LO ( optlc_net_2722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2984 ( .LO ( optlc_net_2723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2985 ( .LO ( optlc_net_2724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2986 ( .LO ( optlc_net_2725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2987 ( .LO ( optlc_net_2726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2988 ( .LO ( optlc_net_2727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2989 ( .LO ( optlc_net_2728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2990 ( .LO ( optlc_net_2729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2991 ( .LO ( optlc_net_2730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2992 ( .LO ( optlc_net_2731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2994 ( .LO ( optlc_net_2732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2995 ( .LO ( optlc_net_2733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2996 ( .LO ( optlc_net_2734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2997 ( .LO ( optlc_net_2735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2998 ( .LO ( optlc_net_2736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2999 ( .LO ( optlc_net_2737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3000 ( .LO ( optlc_net_2738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3001 ( .LO ( optlc_net_2739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3002 ( .LO ( optlc_net_2740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3003 ( .LO ( optlc_net_2741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3004 ( .LO ( optlc_net_2742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3006 ( .LO ( optlc_net_2743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3007 ( .LO ( optlc_net_2744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3008 ( .LO ( optlc_net_2745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3009 ( .LO ( optlc_net_2746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3010 ( .LO ( optlc_net_2747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3011 ( .LO ( optlc_net_2748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3012 ( .LO ( optlc_net_2749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3014 ( .LO ( optlc_net_2750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3015 ( .LO ( optlc_net_2751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3017 ( .LO ( optlc_net_2752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3018 ( .LO ( optlc_net_2753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3019 ( .LO ( optlc_net_2754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3020 ( .LO ( optlc_net_2755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3021 ( .LO ( optlc_net_2756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3022 ( .LO ( optlc_net_2757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3023 ( .LO ( optlc_net_2758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3024 ( .LO ( optlc_net_2759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3025 ( .LO ( optlc_net_2760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3026 ( .LO ( optlc_net_2761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3027 ( .LO ( optlc_net_2762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3028 ( .LO ( optlc_net_2763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3029 ( .LO ( optlc_net_2764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3030 ( .LO ( optlc_net_2765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3031 ( .LO ( optlc_net_2766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3032 ( .LO ( optlc_net_2767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3033 ( .LO ( optlc_net_2768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3034 ( .LO ( optlc_net_2769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3035 ( .LO ( optlc_net_2770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3037 ( .LO ( optlc_net_2771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3038 ( .LO ( optlc_net_2772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3039 ( .LO ( optlc_net_2773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3040 ( .LO ( optlc_net_2774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3041 ( .LO ( optlc_net_2775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3042 ( .LO ( optlc_net_2776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3043 ( .LO ( optlc_net_2777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3044 ( .LO ( optlc_net_2778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3045 ( .LO ( optlc_net_2779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3046 ( .LO ( optlc_net_2780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3047 ( .LO ( optlc_net_2781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3049 ( .LO ( optlc_net_2782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3050 ( .LO ( optlc_net_2783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3051 ( .LO ( optlc_net_2784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3052 ( .LO ( optlc_net_2785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3053 ( .LO ( optlc_net_2786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3054 ( .LO ( optlc_net_2787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3055 ( .LO ( optlc_net_2788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3056 ( .LO ( optlc_net_2789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3057 ( .LO ( optlc_net_2790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3058 ( .LO ( optlc_net_2791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3059 ( .LO ( optlc_net_2792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3060 ( .LO ( optlc_net_2793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3061 ( .LO ( optlc_net_2794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3062 ( .LO ( optlc_net_2795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3063 ( .LO ( optlc_net_2796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3064 ( .LO ( optlc_net_2797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3065 ( .LO ( optlc_net_2798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3066 ( .LO ( optlc_net_2799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3067 ( .LO ( optlc_net_2800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3068 ( .LO ( optlc_net_2801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3069 ( .LO ( optlc_net_2802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3070 ( .LO ( optlc_net_2803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3071 ( .LO ( optlc_net_2804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3072 ( .LO ( optlc_net_2805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3073 ( .LO ( optlc_net_2806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3074 ( .LO ( optlc_net_2807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3075 ( .LO ( optlc_net_2808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3076 ( .LO ( optlc_net_2809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3078 ( .LO ( optlc_net_2810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3079 ( .LO ( optlc_net_2811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3080 ( .LO ( optlc_net_2812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3081 ( .LO ( optlc_net_2813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3082 ( .LO ( optlc_net_2814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3083 ( .LO ( optlc_net_2815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3085 ( .LO ( optlc_net_2816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3086 ( .LO ( optlc_net_2817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3087 ( .LO ( optlc_net_2818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3088 ( .LO ( optlc_net_2819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3089 ( .LO ( optlc_net_2820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3090 ( .LO ( optlc_net_2821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3091 ( .LO ( optlc_net_2822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3092 ( .LO ( optlc_net_2823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3093 ( .LO ( optlc_net_2824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3094 ( .LO ( optlc_net_2825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3095 ( .LO ( optlc_net_2826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3096 ( .LO ( optlc_net_2827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3097 ( .LO ( optlc_net_2828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3098 ( .LO ( optlc_net_2829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3099 ( .LO ( optlc_net_2830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3100 ( .LO ( optlc_net_2831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3101 ( .LO ( optlc_net_2832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3102 ( .LO ( optlc_net_2833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3103 ( .LO ( optlc_net_2834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3104 ( .LO ( optlc_net_2835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3105 ( .LO ( optlc_net_2836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3106 ( .LO ( optlc_net_2837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3107 ( .LO ( optlc_net_2838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3108 ( .LO ( optlc_net_2839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3109 ( .LO ( optlc_net_2840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3110 ( .LO ( optlc_net_2841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3111 ( .LO ( optlc_net_2842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3112 ( .LO ( optlc_net_2843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3113 ( .LO ( optlc_net_2844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3114 ( .LO ( optlc_net_2845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3115 ( .LO ( optlc_net_2846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3116 ( .LO ( optlc_net_2847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3117 ( .LO ( optlc_net_2848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3118 ( .LO ( optlc_net_2849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3119 ( .LO ( optlc_net_2850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3120 ( .LO ( optlc_net_2851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3121 ( .LO ( optlc_net_2852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3122 ( .LO ( optlc_net_2853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3123 ( .LO ( optlc_net_2854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3124 ( .LO ( optlc_net_2855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3125 ( .LO ( optlc_net_2856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3126 ( .LO ( optlc_net_2857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3127 ( .LO ( optlc_net_2858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3128 ( .LO ( optlc_net_2859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3129 ( .LO ( optlc_net_2860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3130 ( .LO ( optlc_net_2861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3131 ( .LO ( optlc_net_2862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3132 ( .LO ( optlc_net_2863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3133 ( .LO ( optlc_net_2864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3134 ( .LO ( optlc_net_2865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3135 ( .LO ( optlc_net_2866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3136 ( .LO ( optlc_net_2867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3137 ( .LO ( optlc_net_2868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3138 ( .LO ( optlc_net_2869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3139 ( .LO ( optlc_net_2870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3140 ( .LO ( optlc_net_2871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3141 ( .LO ( optlc_net_2872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3142 ( .LO ( optlc_net_2873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3143 ( .LO ( optlc_net_2874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3144 ( .LO ( optlc_net_2875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3145 ( .LO ( optlc_net_2876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3146 ( .LO ( optlc_net_2877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3147 ( .LO ( optlc_net_2878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3148 ( .LO ( optlc_net_2879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3149 ( .LO ( optlc_net_2880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3150 ( .LO ( optlc_net_2881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3151 ( .LO ( optlc_net_2882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3152 ( .LO ( optlc_net_2883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3153 ( .LO ( optlc_net_2884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3154 ( .LO ( optlc_net_2885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3155 ( .LO ( optlc_net_2886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3156 ( .LO ( optlc_net_2887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3157 ( .LO ( optlc_net_2888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3158 ( .LO ( optlc_net_2889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3159 ( .LO ( optlc_net_2890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3160 ( .LO ( optlc_net_2891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3161 ( .LO ( optlc_net_2892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3162 ( .LO ( optlc_net_2893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3163 ( .LO ( optlc_net_2894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3164 ( .LO ( optlc_net_2895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3165 ( .LO ( optlc_net_2896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3166 ( .LO ( optlc_net_2897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3167 ( .LO ( optlc_net_2898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3168 ( .LO ( optlc_net_2899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3169 ( .LO ( optlc_net_2900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3170 ( .LO ( optlc_net_2901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3171 ( .LO ( optlc_net_2902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3172 ( .LO ( optlc_net_2903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3173 ( .LO ( optlc_net_2904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3174 ( .LO ( optlc_net_2905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3175 ( .LO ( optlc_net_2906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3176 ( .LO ( optlc_net_2907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3177 ( .LO ( optlc_net_2908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3178 ( .LO ( optlc_net_2909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3179 ( .LO ( optlc_net_2910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3180 ( .LO ( optlc_net_2911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3181 ( .LO ( optlc_net_2912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3182 ( .LO ( optlc_net_2913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3183 ( .LO ( optlc_net_2914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3184 ( .LO ( optlc_net_2915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3186 ( .LO ( optlc_net_2916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3187 ( .LO ( optlc_net_2917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3188 ( .LO ( optlc_net_2918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3189 ( .LO ( optlc_net_2919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3190 ( .LO ( optlc_net_2920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3191 ( .LO ( optlc_net_2921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3192 ( .LO ( optlc_net_2922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3193 ( .LO ( optlc_net_2923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3194 ( .LO ( optlc_net_2924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3195 ( .LO ( optlc_net_2925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3197 ( .LO ( optlc_net_2926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3198 ( .LO ( optlc_net_2927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3199 ( .LO ( optlc_net_2928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3200 ( .LO ( optlc_net_2929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3201 ( .LO ( optlc_net_2930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3202 ( .LO ( optlc_net_2931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3203 ( .LO ( optlc_net_2932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3204 ( .LO ( optlc_net_2933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3205 ( .LO ( optlc_net_2934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3206 ( .LO ( optlc_net_2935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3207 ( .LO ( optlc_net_2936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3209 ( .LO ( optlc_net_2937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3210 ( .LO ( optlc_net_2938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3211 ( .LO ( optlc_net_2939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3212 ( .LO ( optlc_net_2940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3213 ( .LO ( optlc_net_2941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3214 ( .LO ( optlc_net_2942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3215 ( .LO ( optlc_net_2943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3216 ( .LO ( optlc_net_2944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3217 ( .LO ( optlc_net_2945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3218 ( .LO ( optlc_net_2946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3219 ( .LO ( optlc_net_2947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3220 ( .LO ( optlc_net_2948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3221 ( .LO ( optlc_net_2949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3222 ( .LO ( optlc_net_2950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3223 ( .LO ( optlc_net_2951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3224 ( .LO ( optlc_net_2952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3225 ( .LO ( optlc_net_2953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3226 ( .LO ( optlc_net_2954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3227 ( .LO ( optlc_net_2955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3228 ( .LO ( optlc_net_2956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3229 ( .LO ( optlc_net_2957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3230 ( .LO ( optlc_net_2958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3231 ( .LO ( optlc_net_2959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3232 ( .LO ( optlc_net_2960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3233 ( .LO ( optlc_net_2961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3234 ( .LO ( optlc_net_2962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3235 ( .LO ( optlc_net_2963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3236 ( .LO ( optlc_net_2964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3237 ( .LO ( optlc_net_2965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3239 ( .LO ( optlc_net_2966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3240 ( .LO ( optlc_net_2967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3241 ( .LO ( optlc_net_2968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3242 ( .LO ( optlc_net_2969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3243 ( .LO ( optlc_net_2970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3244 ( .LO ( optlc_net_2971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3246 ( .LO ( optlc_net_2972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3247 ( .LO ( optlc_net_2973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3248 ( .LO ( optlc_net_2974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3249 ( .LO ( optlc_net_2975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3250 ( .LO ( optlc_net_2976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3251 ( .LO ( optlc_net_2977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3252 ( .LO ( optlc_net_2978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3254 ( .LO ( optlc_net_2979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3255 ( .LO ( optlc_net_2980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3256 ( .LO ( optlc_net_2981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3257 ( .LO ( optlc_net_2982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3258 ( .LO ( optlc_net_2983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3259 ( .LO ( optlc_net_2984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3260 ( .LO ( optlc_net_2985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3261 ( .LO ( optlc_net_2986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3262 ( .LO ( optlc_net_2987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3263 ( .LO ( optlc_net_2988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3264 ( .LO ( optlc_net_2989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3265 ( .LO ( optlc_net_2990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3266 ( .LO ( optlc_net_2991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3267 ( .LO ( optlc_net_2992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3268 ( .LO ( optlc_net_2993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3269 ( .LO ( optlc_net_2994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3270 ( .LO ( optlc_net_2995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3271 ( .LO ( optlc_net_2996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3272 ( .LO ( optlc_net_2997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3273 ( .LO ( optlc_net_2998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3274 ( .LO ( optlc_net_2999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3275 ( .LO ( optlc_net_3000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3276 ( .LO ( optlc_net_3001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3277 ( .LO ( optlc_net_3002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3278 ( .LO ( optlc_net_3003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3279 ( .LO ( optlc_net_3004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3280 ( .LO ( optlc_net_3005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3281 ( .LO ( optlc_net_3006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3282 ( .LO ( optlc_net_3007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3283 ( .LO ( optlc_net_3008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3284 ( .LO ( optlc_net_3009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3285 ( .LO ( optlc_net_3010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3286 ( .LO ( optlc_net_3011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3287 ( .LO ( optlc_net_3012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3288 ( .LO ( optlc_net_3013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3290 ( .LO ( optlc_net_3014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3291 ( .LO ( optlc_net_3015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3292 ( .LO ( optlc_net_3016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3293 ( .LO ( optlc_net_3017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3294 ( .LO ( optlc_net_3018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3295 ( .LO ( optlc_net_3019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3296 ( .LO ( optlc_net_3020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3297 ( .LO ( optlc_net_3021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3298 ( .LO ( optlc_net_3022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3299 ( .LO ( optlc_net_3023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3300 ( .LO ( optlc_net_3024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3301 ( .LO ( optlc_net_3025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3302 ( .LO ( optlc_net_3026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3303 ( .LO ( optlc_net_3027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3304 ( .LO ( optlc_net_3028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3305 ( .LO ( optlc_net_3029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3306 ( .LO ( optlc_net_3030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3307 ( .LO ( optlc_net_3031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3308 ( .LO ( optlc_net_3032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3309 ( .LO ( optlc_net_3033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3310 ( .LO ( optlc_net_3034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3311 ( .LO ( optlc_net_3035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3312 ( .LO ( optlc_net_3036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3313 ( .LO ( optlc_net_3037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3314 ( .LO ( optlc_net_3038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3315 ( .LO ( optlc_net_3039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3316 ( .LO ( optlc_net_3040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3317 ( .LO ( optlc_net_3041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3318 ( .LO ( optlc_net_3042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3319 ( .LO ( optlc_net_3043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3320 ( .LO ( optlc_net_3044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3321 ( .LO ( optlc_net_3045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3322 ( .LO ( optlc_net_3046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3323 ( .LO ( optlc_net_3047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3324 ( .LO ( optlc_net_3048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3325 ( .LO ( optlc_net_3049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3326 ( .LO ( optlc_net_3050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3327 ( .LO ( optlc_net_3051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3328 ( .LO ( optlc_net_3052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3329 ( .LO ( optlc_net_3053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3330 ( .LO ( optlc_net_3054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3331 ( .LO ( optlc_net_3055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3332 ( .LO ( optlc_net_3056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3333 ( .LO ( optlc_net_3057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3334 ( .LO ( optlc_net_3058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3335 ( .LO ( optlc_net_3059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3336 ( .LO ( optlc_net_3060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3337 ( .LO ( optlc_net_3061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3338 ( .LO ( optlc_net_3062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3339 ( .LO ( optlc_net_3063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3340 ( .LO ( optlc_net_3064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3341 ( .LO ( optlc_net_3065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3342 ( .LO ( optlc_net_3066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3343 ( .LO ( optlc_net_3067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3344 ( .LO ( optlc_net_3068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3345 ( .LO ( optlc_net_3069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3346 ( .LO ( optlc_net_3070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3347 ( .LO ( optlc_net_3071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3348 ( .LO ( optlc_net_3072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3349 ( .LO ( optlc_net_3073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3350 ( .LO ( optlc_net_3074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3351 ( .LO ( optlc_net_3075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3352 ( .LO ( optlc_net_3076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3353 ( .LO ( optlc_net_3077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3354 ( .LO ( optlc_net_3078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3355 ( .LO ( optlc_net_3079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3356 ( .LO ( optlc_net_3080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3357 ( .LO ( optlc_net_3081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3358 ( .LO ( optlc_net_3082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3359 ( .LO ( optlc_net_3083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3360 ( .LO ( optlc_net_3084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3361 ( .LO ( optlc_net_3085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3362 ( .LO ( optlc_net_3086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3363 ( .LO ( optlc_net_3087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3364 ( .LO ( optlc_net_3088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3365 ( .LO ( optlc_net_3089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3366 ( .LO ( optlc_net_3090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3367 ( .LO ( optlc_net_3091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3368 ( .LO ( optlc_net_3092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3369 ( .LO ( optlc_net_3093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3370 ( .LO ( optlc_net_3094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3371 ( .LO ( optlc_net_3095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3372 ( .LO ( optlc_net_3096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3373 ( .LO ( optlc_net_3097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3374 ( .LO ( optlc_net_3098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3375 ( .LO ( optlc_net_3099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3376 ( .LO ( optlc_net_3100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3377 ( .LO ( optlc_net_3101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3378 ( .LO ( optlc_net_3102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3379 ( .LO ( optlc_net_3103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3380 ( .LO ( optlc_net_3104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3381 ( .LO ( optlc_net_3105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3382 ( .LO ( optlc_net_3106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3383 ( .LO ( optlc_net_3107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3385 ( .LO ( optlc_net_3108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3386 ( .LO ( optlc_net_3109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3387 ( .LO ( optlc_net_3110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3388 ( .LO ( optlc_net_3111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3389 ( .LO ( optlc_net_3112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3390 ( .LO ( optlc_net_3113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3391 ( .LO ( optlc_net_3114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3392 ( .LO ( optlc_net_3115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3393 ( .LO ( optlc_net_3116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3394 ( .LO ( optlc_net_3117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3395 ( .LO ( optlc_net_3118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3396 ( .LO ( optlc_net_3119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3397 ( .LO ( optlc_net_3120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3398 ( .LO ( optlc_net_3121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3399 ( .LO ( optlc_net_3122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3400 ( .LO ( optlc_net_3123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3401 ( .LO ( optlc_net_3124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3402 ( .LO ( optlc_net_3125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3403 ( .LO ( optlc_net_3126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3404 ( .LO ( optlc_net_3127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3405 ( .LO ( optlc_net_3128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3406 ( .LO ( optlc_net_3129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3407 ( .LO ( optlc_net_3130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3408 ( .LO ( optlc_net_3131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3409 ( .LO ( optlc_net_3132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3410 ( .LO ( optlc_net_3133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3411 ( .LO ( optlc_net_3134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3412 ( .LO ( optlc_net_3135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3413 ( .LO ( optlc_net_3136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3414 ( .LO ( optlc_net_3137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3415 ( .LO ( optlc_net_3138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3416 ( .LO ( optlc_net_3139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3417 ( .LO ( optlc_net_3140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3418 ( .LO ( optlc_net_3141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3419 ( .LO ( optlc_net_3142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3420 ( .LO ( optlc_net_3143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3421 ( .LO ( optlc_net_3144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3422 ( .LO ( optlc_net_3145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3423 ( .LO ( optlc_net_3146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3424 ( .LO ( optlc_net_3147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3425 ( .LO ( optlc_net_3148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3426 ( .LO ( optlc_net_3149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3427 ( .LO ( optlc_net_3150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3428 ( .LO ( optlc_net_3151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3429 ( .LO ( optlc_net_3152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3430 ( .LO ( optlc_net_3153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3431 ( .LO ( optlc_net_3154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3432 ( .LO ( optlc_net_3155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3433 ( .LO ( optlc_net_3156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3434 ( .LO ( optlc_net_3157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3435 ( .LO ( optlc_net_3158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3436 ( .LO ( optlc_net_3159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3437 ( .LO ( optlc_net_3160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3438 ( .LO ( optlc_net_3161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3439 ( .LO ( optlc_net_3162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3440 ( .LO ( optlc_net_3163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3441 ( .LO ( optlc_net_3164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3442 ( .LO ( optlc_net_3165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3443 ( .LO ( optlc_net_3166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3444 ( .LO ( optlc_net_3167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3445 ( .LO ( optlc_net_3168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3446 ( .LO ( optlc_net_3169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3447 ( .LO ( optlc_net_3170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3448 ( .LO ( optlc_net_3171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3449 ( .LO ( optlc_net_3172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3450 ( .LO ( optlc_net_3173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3451 ( .LO ( optlc_net_3174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3452 ( .LO ( optlc_net_3175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3453 ( .LO ( optlc_net_3176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3455 ( .LO ( optlc_net_3177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3456 ( .LO ( optlc_net_3178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3457 ( .LO ( optlc_net_3179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3458 ( .LO ( optlc_net_3180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3459 ( .LO ( optlc_net_3181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3460 ( .LO ( optlc_net_3182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3461 ( .LO ( optlc_net_3183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3462 ( .LO ( optlc_net_3184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3463 ( .LO ( optlc_net_3185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3464 ( .LO ( optlc_net_3186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3465 ( .LO ( optlc_net_3187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3466 ( .LO ( optlc_net_3188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3467 ( .LO ( optlc_net_3189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3468 ( .LO ( optlc_net_3190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3469 ( .LO ( optlc_net_3191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3470 ( .LO ( optlc_net_3192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3471 ( .LO ( optlc_net_3193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3472 ( .LO ( optlc_net_3194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3473 ( .LO ( optlc_net_3195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3474 ( .LO ( optlc_net_3196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3475 ( .LO ( optlc_net_3197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3476 ( .LO ( optlc_net_3198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3477 ( .LO ( optlc_net_3199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3478 ( .LO ( optlc_net_3200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3479 ( .LO ( optlc_net_3201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3480 ( .LO ( optlc_net_3202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3481 ( .LO ( optlc_net_3203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3482 ( .LO ( optlc_net_3204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3483 ( .LO ( optlc_net_3205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3484 ( .LO ( optlc_net_3206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3485 ( .LO ( optlc_net_3207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3486 ( .LO ( optlc_net_3208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3487 ( .LO ( optlc_net_3209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3488 ( .LO ( optlc_net_3210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3489 ( .LO ( optlc_net_3211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3490 ( .LO ( optlc_net_3212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3491 ( .LO ( optlc_net_3213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3492 ( .LO ( optlc_net_3214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3493 ( .LO ( optlc_net_3215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3494 ( .LO ( optlc_net_3216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3495 ( .LO ( optlc_net_3217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3496 ( .LO ( optlc_net_3218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3497 ( .LO ( optlc_net_3219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3498 ( .LO ( optlc_net_3220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3499 ( .LO ( optlc_net_3221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3500 ( .LO ( optlc_net_3222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3501 ( .LO ( optlc_net_3223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3502 ( .LO ( optlc_net_3224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3503 ( .LO ( optlc_net_3225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3504 ( .LO ( optlc_net_3226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3505 ( .LO ( optlc_net_3227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3506 ( .LO ( optlc_net_3228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3507 ( .LO ( optlc_net_3229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3508 ( .LO ( optlc_net_3230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3509 ( .LO ( optlc_net_3231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3510 ( .LO ( optlc_net_3232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3511 ( .LO ( optlc_net_3233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3512 ( .LO ( optlc_net_3234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3513 ( .LO ( optlc_net_3235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3514 ( .LO ( optlc_net_3236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3515 ( .LO ( optlc_net_3237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3516 ( .LO ( optlc_net_3238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3517 ( .LO ( optlc_net_3239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3518 ( .LO ( optlc_net_3240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3519 ( .LO ( optlc_net_3241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3520 ( .LO ( optlc_net_3242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3521 ( .LO ( optlc_net_3243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3522 ( .LO ( optlc_net_3244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3523 ( .LO ( optlc_net_3245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3524 ( .LO ( optlc_net_3246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3525 ( .LO ( optlc_net_3247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3526 ( .LO ( optlc_net_3248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3527 ( .LO ( optlc_net_3249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3528 ( .LO ( optlc_net_3250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3529 ( .LO ( optlc_net_3251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3530 ( .LO ( optlc_net_3252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3531 ( .LO ( optlc_net_3253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3532 ( .LO ( optlc_net_3254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3534 ( .LO ( optlc_net_3255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3535 ( .LO ( optlc_net_3256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3536 ( .LO ( optlc_net_3257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3538 ( .LO ( optlc_net_3258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3539 ( .LO ( optlc_net_3259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3540 ( .LO ( optlc_net_3260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3541 ( .LO ( optlc_net_3261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3543 ( .LO ( optlc_net_3262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3544 ( .LO ( optlc_net_3263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3545 ( .LO ( optlc_net_3264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3546 ( .LO ( optlc_net_3265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3547 ( .LO ( optlc_net_3266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3548 ( .LO ( optlc_net_3267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3549 ( .LO ( optlc_net_3268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3550 ( .LO ( optlc_net_3269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3551 ( .LO ( optlc_net_3270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3552 ( .LO ( optlc_net_3271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3553 ( .LO ( optlc_net_3272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3554 ( .LO ( optlc_net_3273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3555 ( .LO ( optlc_net_3274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3556 ( .LO ( optlc_net_3275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3557 ( .LO ( optlc_net_3276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3558 ( .LO ( optlc_net_3277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3559 ( .LO ( optlc_net_3278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3560 ( .LO ( optlc_net_3279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3561 ( .LO ( optlc_net_3280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3562 ( .LO ( optlc_net_3281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3563 ( .LO ( optlc_net_3282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3564 ( .LO ( optlc_net_3283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3565 ( .LO ( optlc_net_3284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3566 ( .LO ( optlc_net_3285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3567 ( .LO ( optlc_net_3286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3568 ( .LO ( optlc_net_3287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3569 ( .LO ( optlc_net_3288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3570 ( .LO ( optlc_net_3289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3571 ( .LO ( optlc_net_3290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3572 ( .LO ( optlc_net_3291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3573 ( .LO ( optlc_net_3292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3574 ( .LO ( optlc_net_3293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3575 ( .LO ( optlc_net_3294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3576 ( .LO ( optlc_net_3295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3577 ( .LO ( optlc_net_3296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3578 ( .LO ( optlc_net_3297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3579 ( .LO ( optlc_net_3298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3580 ( .LO ( optlc_net_3299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3581 ( .LO ( optlc_net_3300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3582 ( .LO ( optlc_net_3301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3583 ( .LO ( optlc_net_3302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3584 ( .LO ( optlc_net_3303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3585 ( .LO ( optlc_net_3304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3586 ( .LO ( optlc_net_3305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3587 ( .LO ( optlc_net_3306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3588 ( .LO ( optlc_net_3307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3589 ( .LO ( optlc_net_3308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3590 ( .LO ( optlc_net_3309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3591 ( .LO ( optlc_net_3310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3592 ( .LO ( optlc_net_3311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3593 ( .LO ( optlc_net_3312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3594 ( .LO ( optlc_net_3313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3595 ( .LO ( optlc_net_3314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3596 ( .LO ( optlc_net_3315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3597 ( .LO ( optlc_net_3316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3598 ( .LO ( optlc_net_3317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3599 ( .LO ( optlc_net_3318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3600 ( .LO ( optlc_net_3319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3601 ( .LO ( optlc_net_3320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3602 ( .LO ( optlc_net_3321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3603 ( .LO ( optlc_net_3322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3604 ( .LO ( optlc_net_3323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3605 ( .LO ( optlc_net_3324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3606 ( .LO ( optlc_net_3325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3607 ( .LO ( optlc_net_3326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3608 ( .LO ( optlc_net_3327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3609 ( .LO ( optlc_net_3328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3610 ( .LO ( optlc_net_3329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3611 ( .LO ( optlc_net_3330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3612 ( .LO ( optlc_net_3331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3613 ( .LO ( optlc_net_3332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3614 ( .LO ( optlc_net_3333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3615 ( .LO ( optlc_net_3334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3616 ( .LO ( optlc_net_3335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3617 ( .LO ( optlc_net_3336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3618 ( .LO ( optlc_net_3337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3619 ( .LO ( optlc_net_3338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3620 ( .LO ( optlc_net_3339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3621 ( .LO ( optlc_net_3340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3622 ( .LO ( optlc_net_3341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3623 ( .LO ( optlc_net_3342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3624 ( .LO ( optlc_net_3343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3625 ( .LO ( optlc_net_3344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3626 ( .LO ( optlc_net_3345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3627 ( .LO ( optlc_net_3346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3628 ( .LO ( optlc_net_3347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3629 ( .LO ( optlc_net_3348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3630 ( .LO ( optlc_net_3349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3631 ( .LO ( optlc_net_3350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3632 ( .LO ( optlc_net_3351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3633 ( .LO ( optlc_net_3352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3634 ( .LO ( optlc_net_3353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3635 ( .LO ( optlc_net_3354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3636 ( .LO ( optlc_net_3355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3637 ( .LO ( optlc_net_3356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3638 ( .LO ( optlc_net_3357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3639 ( .LO ( optlc_net_3358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3640 ( .LO ( optlc_net_3359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3641 ( .LO ( optlc_net_3360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3642 ( .LO ( optlc_net_3361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3643 ( .LO ( optlc_net_3362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3644 ( .LO ( optlc_net_3363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3645 ( .LO ( optlc_net_3364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3646 ( .LO ( optlc_net_3365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3647 ( .LO ( optlc_net_3366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3648 ( .LO ( optlc_net_3367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3649 ( .LO ( optlc_net_3368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3650 ( .LO ( optlc_net_3369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3651 ( .LO ( optlc_net_3370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3652 ( .LO ( optlc_net_3371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3653 ( .LO ( optlc_net_3372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3654 ( .LO ( optlc_net_3373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3655 ( .LO ( optlc_net_3374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3656 ( .LO ( optlc_net_3375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3657 ( .LO ( optlc_net_3376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3658 ( .LO ( optlc_net_3377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3659 ( .LO ( optlc_net_3378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3660 ( .LO ( optlc_net_3379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3661 ( .LO ( optlc_net_3380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3662 ( .LO ( optlc_net_3381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3663 ( .LO ( optlc_net_3382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3664 ( .LO ( optlc_net_3383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3665 ( .LO ( optlc_net_3384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3666 ( .LO ( optlc_net_3385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3667 ( .LO ( optlc_net_3386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3668 ( .LO ( optlc_net_3387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3669 ( .LO ( optlc_net_3388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3670 ( .LO ( optlc_net_3389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3671 ( .LO ( optlc_net_3390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3672 ( .LO ( optlc_net_3391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3673 ( .LO ( optlc_net_3392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3674 ( .LO ( optlc_net_3393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3675 ( .LO ( optlc_net_3394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3676 ( .LO ( optlc_net_3395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3677 ( .LO ( optlc_net_3396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3678 ( .LO ( optlc_net_3397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3679 ( .LO ( optlc_net_3398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3680 ( .LO ( optlc_net_3399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3681 ( .LO ( optlc_net_3400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3682 ( .LO ( optlc_net_3401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3683 ( .LO ( optlc_net_3402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3684 ( .LO ( optlc_net_3403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3685 ( .LO ( optlc_net_3404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3686 ( .LO ( optlc_net_3405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3687 ( .LO ( optlc_net_3406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3688 ( .LO ( optlc_net_3407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3689 ( .LO ( optlc_net_3408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3690 ( .LO ( optlc_net_3409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3691 ( .LO ( optlc_net_3410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3692 ( .LO ( optlc_net_3411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3693 ( .LO ( optlc_net_3412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3694 ( .LO ( optlc_net_3413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3695 ( .LO ( optlc_net_3414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3696 ( .LO ( optlc_net_3415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3697 ( .LO ( optlc_net_3416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3698 ( .LO ( optlc_net_3417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3699 ( .LO ( optlc_net_3418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3700 ( .LO ( optlc_net_3419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3701 ( .LO ( optlc_net_3420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3702 ( .LO ( optlc_net_3421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3703 ( .LO ( optlc_net_3422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3704 ( .LO ( optlc_net_3423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3705 ( .LO ( optlc_net_3424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3706 ( .LO ( optlc_net_3425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3707 ( .LO ( optlc_net_3426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3708 ( .LO ( optlc_net_3427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3709 ( .LO ( optlc_net_3428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3710 ( .LO ( optlc_net_3429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3711 ( .LO ( optlc_net_3430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3712 ( .LO ( optlc_net_3431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3713 ( .LO ( optlc_net_3432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3714 ( .LO ( optlc_net_3433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3715 ( .LO ( optlc_net_3434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3716 ( .LO ( optlc_net_3435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3717 ( .LO ( optlc_net_3436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3718 ( .LO ( optlc_net_3437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3719 ( .LO ( optlc_net_3438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3720 ( .LO ( optlc_net_3439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3721 ( .LO ( optlc_net_3440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3722 ( .LO ( optlc_net_3441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3723 ( .LO ( optlc_net_3442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3724 ( .LO ( optlc_net_3443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3725 ( .LO ( optlc_net_3444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3726 ( .LO ( optlc_net_3445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3727 ( .LO ( optlc_net_3446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3728 ( .LO ( optlc_net_3447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3729 ( .LO ( optlc_net_3448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3730 ( .LO ( optlc_net_3449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3731 ( .LO ( optlc_net_3450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3732 ( .LO ( optlc_net_3451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3733 ( .LO ( optlc_net_3452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3734 ( .LO ( optlc_net_3453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3735 ( .LO ( optlc_net_3454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3736 ( .LO ( optlc_net_3455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3737 ( .LO ( optlc_net_3456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3738 ( .LO ( optlc_net_3457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3739 ( .LO ( optlc_net_3458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3740 ( .LO ( optlc_net_3459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3741 ( .LO ( optlc_net_3460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3742 ( .LO ( optlc_net_3461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3743 ( .LO ( optlc_net_3462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3744 ( .LO ( optlc_net_3463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3745 ( .LO ( optlc_net_3464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3746 ( .LO ( optlc_net_3465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3747 ( .LO ( optlc_net_3466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3748 ( .LO ( optlc_net_3467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3749 ( .LO ( optlc_net_3468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3750 ( .LO ( optlc_net_3469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3751 ( .LO ( optlc_net_3470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3753 ( .LO ( optlc_net_3471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3754 ( .LO ( optlc_net_3472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3755 ( .LO ( optlc_net_3473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3756 ( .LO ( optlc_net_3474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3757 ( .LO ( optlc_net_3475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3758 ( .LO ( optlc_net_3476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3759 ( .LO ( optlc_net_3477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3760 ( .LO ( optlc_net_3478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3761 ( .LO ( optlc_net_3479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3762 ( .LO ( optlc_net_3480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3763 ( .LO ( optlc_net_3481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3764 ( .LO ( optlc_net_3482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3765 ( .LO ( optlc_net_3483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3766 ( .LO ( optlc_net_3484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3767 ( .LO ( optlc_net_3485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3768 ( .LO ( optlc_net_3486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3769 ( .LO ( optlc_net_3487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3770 ( .LO ( optlc_net_3488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3771 ( .LO ( optlc_net_3489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3772 ( .LO ( optlc_net_3490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3773 ( .LO ( optlc_net_3491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3774 ( .LO ( optlc_net_3492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3775 ( .LO ( optlc_net_3493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3776 ( .LO ( optlc_net_3494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3777 ( .LO ( optlc_net_3495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3778 ( .LO ( optlc_net_3496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3779 ( .LO ( optlc_net_3497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3780 ( .LO ( optlc_net_3498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3781 ( .LO ( optlc_net_3499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3782 ( .LO ( optlc_net_3500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3783 ( .LO ( optlc_net_3501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3784 ( .LO ( optlc_net_3502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3785 ( .LO ( optlc_net_3503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3786 ( .LO ( optlc_net_3504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3787 ( .LO ( optlc_net_3505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3788 ( .LO ( optlc_net_3506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3789 ( .LO ( optlc_net_3507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3790 ( .LO ( optlc_net_3508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3791 ( .LO ( optlc_net_3509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3792 ( .LO ( optlc_net_3510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3793 ( .LO ( optlc_net_3511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3794 ( .LO ( optlc_net_3512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3795 ( .LO ( optlc_net_3513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3796 ( .LO ( optlc_net_3514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3797 ( .LO ( optlc_net_3515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3798 ( .LO ( optlc_net_3516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3799 ( .LO ( optlc_net_3517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3800 ( .LO ( optlc_net_3518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3801 ( .LO ( optlc_net_3519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3802 ( .LO ( optlc_net_3520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3803 ( .LO ( optlc_net_3521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3804 ( .LO ( optlc_net_3522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3805 ( .LO ( optlc_net_3523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3806 ( .LO ( optlc_net_3524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3807 ( .LO ( optlc_net_3525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3808 ( .LO ( optlc_net_3526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3809 ( .LO ( optlc_net_3527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3810 ( .LO ( optlc_net_3528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3811 ( .LO ( optlc_net_3529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3812 ( .LO ( optlc_net_3530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3813 ( .LO ( optlc_net_3531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3814 ( .LO ( optlc_net_3532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3815 ( .LO ( optlc_net_3533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3816 ( .LO ( optlc_net_3534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3817 ( .LO ( optlc_net_3535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3818 ( .LO ( optlc_net_3536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3819 ( .LO ( optlc_net_3537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3820 ( .LO ( optlc_net_3538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3821 ( .LO ( optlc_net_3539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3822 ( .LO ( optlc_net_3540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3823 ( .LO ( optlc_net_3541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3824 ( .LO ( optlc_net_3542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3825 ( .LO ( optlc_net_3543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3826 ( .LO ( optlc_net_3544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3827 ( .LO ( optlc_net_3545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3828 ( .LO ( optlc_net_3546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3829 ( .LO ( optlc_net_3547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3830 ( .LO ( optlc_net_3548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3831 ( .LO ( optlc_net_3549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3832 ( .LO ( optlc_net_3550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3833 ( .LO ( optlc_net_3551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3834 ( .LO ( optlc_net_3552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3835 ( .LO ( optlc_net_3553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3836 ( .LO ( optlc_net_3554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3837 ( .LO ( optlc_net_3555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3838 ( .LO ( optlc_net_3556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3839 ( .LO ( optlc_net_3557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3840 ( .LO ( optlc_net_3558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3841 ( .LO ( optlc_net_3559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3842 ( .LO ( optlc_net_3560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3843 ( .LO ( optlc_net_3561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3844 ( .LO ( optlc_net_3562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3845 ( .LO ( optlc_net_3563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3846 ( .LO ( optlc_net_3564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3847 ( .LO ( optlc_net_3565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3848 ( .LO ( optlc_net_3566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3849 ( .LO ( optlc_net_3567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3850 ( .LO ( optlc_net_3568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3851 ( .LO ( optlc_net_3569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3852 ( .LO ( optlc_net_3570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3853 ( .LO ( optlc_net_3571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3854 ( .LO ( optlc_net_3572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3855 ( .LO ( optlc_net_3573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3856 ( .LO ( optlc_net_3574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3857 ( .LO ( optlc_net_3575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3858 ( .LO ( optlc_net_3576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3859 ( .LO ( optlc_net_3577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3860 ( .LO ( optlc_net_3578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3861 ( .LO ( optlc_net_3579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3862 ( .LO ( optlc_net_3580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3863 ( .LO ( optlc_net_3581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3864 ( .LO ( optlc_net_3582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3865 ( .LO ( optlc_net_3583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3866 ( .LO ( optlc_net_3584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3867 ( .LO ( optlc_net_3585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3868 ( .LO ( optlc_net_3586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3869 ( .LO ( optlc_net_3587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3870 ( .LO ( optlc_net_3588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3871 ( .LO ( optlc_net_3589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3872 ( .LO ( optlc_net_3590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3873 ( .LO ( optlc_net_3591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3874 ( .LO ( optlc_net_3592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3966 ( .LO ( optlc_net_3684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3967 ( .LO ( optlc_net_3685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3968 ( .LO ( optlc_net_3686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3969 ( .LO ( optlc_net_3687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3970 ( .LO ( optlc_net_3688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3971 ( .LO ( optlc_net_3689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3972 ( .LO ( optlc_net_3690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3973 ( .LO ( optlc_net_3691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3974 ( .LO ( optlc_net_3692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3975 ( .LO ( optlc_net_3693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3976 ( .LO ( optlc_net_3694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3977 ( .LO ( optlc_net_3695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3978 ( .LO ( optlc_net_3696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3979 ( .LO ( optlc_net_3697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3980 ( .LO ( optlc_net_3698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3700 ) ) ;
+endmodule
+
+
diff --git a/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.top_only.pt.v b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.top_only.pt.v
new file mode 100644
index 0000000..08d89cb
--- /dev/null
+++ b/SOFA_QLHD/fpga_top/fpga_top_icv_in_design.top_only.pt.v
@@ -0,0 +1,10242 @@
+//
+//
+//
+//
+//
+//
+module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 ,
+ vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i ,
+ wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in ,
+ la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ ,
+ analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ ,
+ analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ ,
+ analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ ,
+ analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ ,
+ analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ ,
+ analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ ,
+ analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ ,
+ analog_io_9_ , user_clock2 ) ;
+inout vdda1 ;
+inout vdda2 ;
+inout vssa1 ;
+inout vssa2 ;
+inout vccd1 ;
+inout vccd2 ;
+inout vssd1 ;
+inout vssd2 ;
+input wb_clk_i ;
+input wb_rst_i ;
+input wbs_stb_i ;
+input wbs_cyc_i ;
+input wbs_we_i ;
+input [3:0] wbs_sel_i ;
+input [31:0] wbs_dat_i ;
+input [31:0] wbs_adr_i ;
+output wbs_ack_o ;
+output [31:0] wbs_dat_o ;
+input [127:0] la_data_in ;
+output [127:0] la_data_out ;
+input [127:0] la_oen ;
+input [37:0] io_in ;
+output [37:0] io_out ;
+output [37:0] io_oeb ;
+inout analog_io_0_ ;
+inout analog_io_10_ ;
+inout analog_io_11_ ;
+inout analog_io_12_ ;
+inout analog_io_13_ ;
+inout analog_io_14_ ;
+inout analog_io_15_ ;
+inout analog_io_16_ ;
+inout analog_io_17_ ;
+inout analog_io_18_ ;
+inout analog_io_19_ ;
+inout analog_io_1_ ;
+inout analog_io_20_ ;
+inout analog_io_21_ ;
+inout analog_io_22_ ;
+inout analog_io_23_ ;
+inout analog_io_24_ ;
+inout analog_io_25_ ;
+inout analog_io_26_ ;
+inout analog_io_27_ ;
+inout analog_io_28_ ;
+inout analog_io_29_ ;
+inout analog_io_2_ ;
+inout analog_io_30_ ;
+inout analog_io_3_ ;
+inout analog_io_4_ ;
+inout analog_io_5_ ;
+inout analog_io_6_ ;
+inout analog_io_7_ ;
+inout analog_io_8_ ;
+inout analog_io_9_ ;
+input user_clock2 ;
+
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+wire ccff_head ;
+wire sc_tail ;
+wire pReset ;
+wire Reset ;
+wire IO_ISOL_N ;
+wire Test_en ;
+wire prog_clk ;
+wire clk ;
+wire ccff_tail ;
+wire sc_head ;
+wire wb_la_switch ;
+
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ;
+assign ccff_head = io_in[12] ;
+assign sc_tail = io_out[11] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ;
+assign pReset = io_in[3] ;
+assign Reset = io_in[2] ;
+assign IO_ISOL_N = io_in[1] ;
+assign Test_en = io_in[0] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = la_data_out[127] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = la_data_out[126] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[125] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[124] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[123] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[122] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[121] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[120] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[119] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[118] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[117] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[84] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[83] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[82] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[81] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[80] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[79] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[78] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[77] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[76] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[75] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[74] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[73] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[72] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[71] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[70] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[69] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[68] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[67] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[66] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[65] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[64] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[63] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[62] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[61] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[60] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[59] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[58] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[57] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[56] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[55] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[54] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[53] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[52] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[51] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[50] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[49] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[48] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[47] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[46] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[45] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[44] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[43] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[42] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[41] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[40] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[39] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[38] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[37] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[36] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[26] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[25] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[24] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[23] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[22] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[21] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[20] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[19] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[18] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[17] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[16] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[15] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[14] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[12] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[11] ;
+assign prog_clk = io_in[37] ;
+assign clk = io_in[36] ;
+assign ccff_tail = io_out[35] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ;
+assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ;
+assign sc_head = io_in[26] ;
+assign wb_la_switch = io_in[25] ;
+
+sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) ,
+ .Y ( wb_la_switch_b ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[0] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[116] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[1] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[115] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[2] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[114] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[3] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[113] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[4] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[112] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[5] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[111] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[6] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[110] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[7] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[109] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[8] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[108] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[9] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[107] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[10] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[106] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[11] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[105] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[12] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[104] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[13] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[103] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[14] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[102] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[15] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[101] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[16] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[100] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[17] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[99] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[18] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[98] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[19] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[97] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[20] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[96] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[21] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[95] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[22] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[94] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[23] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[93] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[24] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[92] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[25] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[91] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[26] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[90] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[27] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[89] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[28] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[88] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[29] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[87] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[30] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[86] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_dat_o[31] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) ,
+ .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) ,
+ .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) ,
+ .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) ,
+ .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) ,
+ .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) ,
+ .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) ,
+ .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) ,
+ .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) ,
+ .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) ,
+ .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) ,
+ .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) ,
+ .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) ,
+ .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) ,
+ .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) ,
+ .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) ,
+ .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) ,
+ .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) ,
+ .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) ,
+ .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) ,
+ .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) ,
+ .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) ,
+ .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) ,
+ .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) ,
+ .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) ,
+ .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) ,
+ .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) ,
+ .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) ,
+ .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) ,
+ .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) ,
+ .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) ,
+ .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) ,
+ .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) ,
+ .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) ,
+ .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) ,
+ .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) ,
+ .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) ,
+ .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) ,
+ .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) ,
+ .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) ,
+ .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) ,
+ .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) ,
+ .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) ,
+ .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) ,
+ .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) ,
+ .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) ,
+ .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) ,
+ .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) ,
+ .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) ,
+ .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) ,
+ .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) ,
+ .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) ,
+ .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) ,
+ .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) ,
+ .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) ,
+ .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) ,
+ .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) ,
+ .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) ,
+ .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) ,
+ .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) ,
+ .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) ,
+ .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) ,
+ .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) ,
+ .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) ,
+ .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) ,
+ .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) ,
+ .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) ,
+ .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) ,
+ .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) ,
+ .A1 ( wbs_we_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) ,
+ .A1 ( wbs_stb_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) ,
+ .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) ,
+ .Z ( wbs_ack_o ) ) ;
+sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (
+ .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) ,
+ .Z ( la_data_out[13] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) ,
+ .A1 ( wb_rst_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ;
+sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) ,
+ .A1 ( wb_clk_i ) , .S ( io_in[25] ) ,
+ .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ;
+fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) ,
+ .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) ,
+ .Reset ( io_in[2] ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] ,
+ io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] ,
+ io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] ,
+ io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] ,
+ la_data_in[127] , la_data_in[126] , la_data_in[125] ,
+ la_data_in[124] , la_data_in[123] , la_data_in[122] ,
+ la_data_in[121] , la_data_in[120] , la_data_in[119] ,
+ la_data_in[118] , la_data_in[117] , la_data_in[116] ,
+ la_data_in[115] , la_data_in[114] , la_data_in[113] ,
+ la_data_in[112] , la_data_in[111] , la_data_in[110] ,
+ la_data_in[109] , la_data_in[108] , la_data_in[107] ,
+ la_data_in[106] , la_data_in[105] , la_data_in[104] ,
+ la_data_in[103] , la_data_in[102] , la_data_in[101] ,
+ la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] ,
+ la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] ,
+ la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] ,
+ la_data_in[88] , la_data_in[87] , la_data_in[86] , la_data_in[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[13] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] ,
+ io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] ,
+ io_in[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] ,
+ io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] ,
+ io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] ,
+ io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] ,
+ io_out[5] , io_out[4] , la_data_out[127] , la_data_out[126] ,
+ la_data_out[125] , la_data_out[124] , la_data_out[123] ,
+ la_data_out[122] , la_data_out[121] , la_data_out[120] ,
+ la_data_out[119] , la_data_out[118] , la_data_out[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[84] ,
+ la_data_out[83] , la_data_out[82] , la_data_out[81] ,
+ la_data_out[80] , la_data_out[79] , la_data_out[78] ,
+ la_data_out[77] , la_data_out[76] , la_data_out[75] ,
+ la_data_out[74] , la_data_out[73] , la_data_out[72] ,
+ la_data_out[71] , la_data_out[70] , la_data_out[69] ,
+ la_data_out[68] , la_data_out[67] , la_data_out[66] ,
+ la_data_out[65] , la_data_out[64] , la_data_out[63] ,
+ la_data_out[62] , la_data_out[61] , la_data_out[60] ,
+ la_data_out[59] , la_data_out[58] , la_data_out[57] ,
+ la_data_out[56] , la_data_out[55] , la_data_out[54] ,
+ la_data_out[53] , la_data_out[52] , la_data_out[51] ,
+ la_data_out[50] , la_data_out[49] , la_data_out[48] ,
+ la_data_out[47] , la_data_out[46] , la_data_out[45] ,
+ la_data_out[44] , la_data_out[43] , la_data_out[42] ,
+ la_data_out[41] , la_data_out[40] , la_data_out[39] ,
+ la_data_out[38] , la_data_out[37] , la_data_out[36] ,
+ la_data_out[35] , la_data_out[34] , la_data_out[33] ,
+ la_data_out[32] , la_data_out[31] , la_data_out[30] ,
+ la_data_out[29] , la_data_out[28] , la_data_out[27] ,
+ la_data_out[26] , la_data_out[25] , la_data_out[24] ,
+ la_data_out[23] , la_data_out[22] , la_data_out[21] ,
+ la_data_out[20] , la_data_out[19] , la_data_out[18] ,
+ la_data_out[17] , la_data_out[16] , la_data_out[15] ,
+ la_data_out[14] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ,
+ la_data_out[12] , la_data_out[11] , io_out[34] , io_out[33] ,
+ io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] ,
+ io_out[27] } ) ,
+ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] ,
+ io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] ,
+ io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] ,
+ io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] ,
+ io_oeb[5] , io_oeb[4] , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ,
+ gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] ,
+ io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] ,
+ io_oeb[27] } ) ,
+ .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) ,
+ .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) ,
+ .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , .p0 ( optlc_net_20 ) ,
+ .p1 ( optlc_net_21 ) , .p2 ( optlc_net_22 ) , .p3 ( optlc_net_23 ) ,
+ .p4 ( optlc_net_24 ) , .p5 ( optlc_net_25 ) , .p6 ( optlc_net_26 ) ,
+ .p7 ( optlc_net_27 ) , .p8 ( optlc_net_28 ) , .p9 ( optlc_net_29 ) ,
+ .p10 ( optlc_net_30 ) , .p11 ( optlc_net_31 ) , .p12 ( optlc_net_32 ) ,
+ .p13 ( optlc_net_33 ) , .p14 ( optlc_net_34 ) , .p15 ( optlc_net_35 ) ,
+ .p16 ( optlc_net_36 ) , .p17 ( optlc_net_37 ) , .p18 ( optlc_net_38 ) ,
+ .p19 ( optlc_net_39 ) , .p20 ( optlc_net_40 ) , .p21 ( optlc_net_41 ) ,
+ .p22 ( optlc_net_42 ) , .p23 ( optlc_net_43 ) , .p24 ( optlc_net_44 ) ,
+ .p25 ( optlc_net_45 ) , .p26 ( optlc_net_46 ) , .p27 ( optlc_net_47 ) ,
+ .p28 ( optlc_net_48 ) , .p29 ( optlc_net_49 ) , .p30 ( optlc_net_50 ) ,
+ .p31 ( optlc_net_51 ) , .p32 ( optlc_net_52 ) , .p33 ( optlc_net_53 ) ,
+ .p34 ( optlc_net_54 ) , .p35 ( optlc_net_55 ) , .p36 ( optlc_net_56 ) ,
+ .p37 ( optlc_net_57 ) , .p38 ( optlc_net_58 ) , .p39 ( optlc_net_59 ) ,
+ .p40 ( optlc_net_60 ) , .p41 ( optlc_net_61 ) , .p42 ( optlc_net_62 ) ,
+ .p43 ( optlc_net_63 ) , .p44 ( optlc_net_64 ) , .p45 ( optlc_net_65 ) ,
+ .p46 ( optlc_net_66 ) , .p47 ( optlc_net_67 ) , .p48 ( optlc_net_68 ) ,
+ .p49 ( optlc_net_69 ) , .p50 ( optlc_net_70 ) , .p51 ( optlc_net_71 ) ,
+ .p52 ( optlc_net_72 ) , .p53 ( optlc_net_73 ) , .p54 ( optlc_net_74 ) ,
+ .p55 ( optlc_net_75 ) , .p56 ( optlc_net_76 ) , .p57 ( optlc_net_77 ) ,
+ .p58 ( optlc_net_78 ) , .p59 ( optlc_net_79 ) , .p60 ( optlc_net_80 ) ,
+ .p61 ( optlc_net_81 ) , .p62 ( optlc_net_82 ) , .p63 ( optlc_net_83 ) ,
+ .p64 ( optlc_net_84 ) , .p65 ( optlc_net_85 ) , .p66 ( optlc_net_86 ) ,
+ .p67 ( optlc_net_87 ) , .p68 ( optlc_net_88 ) , .p69 ( optlc_net_89 ) ,
+ .p70 ( optlc_net_90 ) , .p71 ( optlc_net_91 ) , .p72 ( optlc_net_92 ) ,
+ .p73 ( optlc_net_93 ) , .p74 ( optlc_net_94 ) , .p75 ( optlc_net_95 ) ,
+ .p76 ( optlc_net_96 ) , .p77 ( optlc_net_97 ) , .p78 ( optlc_net_98 ) ,
+ .p79 ( optlc_net_99 ) , .p80 ( optlc_net_100 ) , .p81 ( optlc_net_101 ) ,
+ .p82 ( optlc_net_102 ) , .p83 ( optlc_net_103 ) , .p84 ( optlc_net_104 ) ,
+ .p85 ( optlc_net_105 ) , .p86 ( optlc_net_106 ) , .p87 ( optlc_net_107 ) ,
+ .p88 ( optlc_net_108 ) , .p89 ( optlc_net_109 ) , .p90 ( optlc_net_110 ) ,
+ .p91 ( optlc_net_111 ) , .p92 ( optlc_net_112 ) , .p93 ( optlc_net_113 ) ,
+ .p94 ( optlc_net_114 ) , .p95 ( optlc_net_115 ) , .p96 ( optlc_net_116 ) ,
+ .p97 ( optlc_net_117 ) , .p98 ( optlc_net_118 ) , .p99 ( optlc_net_119 ) ,
+ .p100 ( optlc_net_120 ) , .p101 ( optlc_net_121 ) ,
+ .p102 ( optlc_net_122 ) , .p103 ( optlc_net_123 ) ,
+ .p104 ( optlc_net_124 ) , .p105 ( optlc_net_125 ) ,
+ .p106 ( optlc_net_126 ) , .p107 ( optlc_net_127 ) ,
+ .p108 ( optlc_net_128 ) , .p109 ( optlc_net_129 ) ,
+ .p110 ( optlc_net_130 ) , .p111 ( optlc_net_131 ) ,
+ .p112 ( optlc_net_132 ) , .p113 ( optlc_net_133 ) ,
+ .p114 ( optlc_net_134 ) , .p115 ( optlc_net_135 ) ,
+ .p116 ( optlc_net_136 ) , .p117 ( optlc_net_137 ) ,
+ .p118 ( optlc_net_138 ) , .p119 ( optlc_net_139 ) ,
+ .p120 ( optlc_net_140 ) , .p121 ( optlc_net_141 ) ,
+ .p122 ( optlc_net_142 ) , .p123 ( optlc_net_143 ) ,
+ .p124 ( optlc_net_144 ) , .p125 ( optlc_net_145 ) ,
+ .p126 ( optlc_net_146 ) , .p127 ( optlc_net_147 ) ,
+ .p128 ( optlc_net_148 ) , .p129 ( optlc_net_149 ) ,
+ .p130 ( optlc_net_150 ) , .p131 ( optlc_net_151 ) ,
+ .p132 ( optlc_net_152 ) , .p133 ( optlc_net_153 ) ,
+ .p134 ( optlc_net_154 ) , .p135 ( optlc_net_155 ) ,
+ .p136 ( optlc_net_156 ) , .p137 ( optlc_net_157 ) ,
+ .p138 ( optlc_net_158 ) , .p139 ( optlc_net_159 ) ,
+ .p140 ( optlc_net_160 ) , .p141 ( optlc_net_161 ) ,
+ .p142 ( optlc_net_162 ) , .p143 ( optlc_net_163 ) ,
+ .p144 ( optlc_net_164 ) , .p145 ( optlc_net_165 ) ,
+ .p146 ( optlc_net_166 ) , .p147 ( optlc_net_167 ) ,
+ .p148 ( optlc_net_168 ) , .p149 ( optlc_net_169 ) ,
+ .p150 ( optlc_net_170 ) , .p151 ( optlc_net_171 ) ,
+ .p152 ( optlc_net_172 ) , .p153 ( optlc_net_173 ) ,
+ .p154 ( optlc_net_174 ) , .p155 ( optlc_net_175 ) ,
+ .p156 ( optlc_net_176 ) , .p157 ( optlc_net_177 ) ,
+ .p158 ( optlc_net_178 ) , .p159 ( optlc_net_179 ) ,
+ .p160 ( optlc_net_180 ) , .p161 ( optlc_net_181 ) ,
+ .p162 ( optlc_net_182 ) , .p163 ( optlc_net_183 ) ,
+ .p164 ( optlc_net_184 ) , .p165 ( optlc_net_185 ) ,
+ .p166 ( optlc_net_186 ) , .p167 ( optlc_net_187 ) ,
+ .p168 ( optlc_net_188 ) , .p169 ( optlc_net_189 ) ,
+ .p170 ( optlc_net_190 ) , .p171 ( optlc_net_191 ) ,
+ .p172 ( optlc_net_192 ) , .p173 ( optlc_net_193 ) ,
+ .p174 ( optlc_net_194 ) , .p175 ( optlc_net_195 ) ,
+ .p176 ( optlc_net_196 ) , .p177 ( optlc_net_197 ) ,
+ .p178 ( optlc_net_198 ) , .p179 ( optlc_net_199 ) ,
+ .p180 ( optlc_net_200 ) , .p181 ( optlc_net_201 ) ,
+ .p182 ( optlc_net_202 ) , .p183 ( optlc_net_203 ) ,
+ .p184 ( optlc_net_204 ) , .p185 ( optlc_net_205 ) ,
+ .p186 ( optlc_net_206 ) , .p187 ( optlc_net_207 ) ,
+ .p188 ( optlc_net_208 ) , .p189 ( optlc_net_209 ) ,
+ .p190 ( optlc_net_210 ) , .p191 ( optlc_net_211 ) ,
+ .p192 ( optlc_net_212 ) , .p193 ( optlc_net_213 ) ,
+ .p194 ( optlc_net_214 ) , .p195 ( optlc_net_215 ) ,
+ .p196 ( optlc_net_216 ) , .p197 ( optlc_net_217 ) ,
+ .p198 ( optlc_net_218 ) , .p199 ( optlc_net_219 ) ,
+ .p200 ( optlc_net_220 ) , .p201 ( optlc_net_221 ) ,
+ .p202 ( optlc_net_222 ) , .p203 ( optlc_net_223 ) ,
+ .p204 ( optlc_net_224 ) , .p205 ( optlc_net_225 ) ,
+ .p206 ( optlc_net_226 ) , .p207 ( optlc_net_227 ) ,
+ .p208 ( optlc_net_228 ) , .p209 ( optlc_net_229 ) ,
+ .p210 ( optlc_net_230 ) , .p211 ( optlc_net_231 ) ,
+ .p212 ( optlc_net_232 ) , .p213 ( optlc_net_233 ) ,
+ .p214 ( optlc_net_234 ) , .p215 ( optlc_net_235 ) ,
+ .p216 ( optlc_net_236 ) , .p217 ( optlc_net_237 ) ,
+ .p218 ( optlc_net_238 ) , .p219 ( optlc_net_239 ) ,
+ .p220 ( optlc_net_240 ) , .p221 ( optlc_net_241 ) ,
+ .p222 ( optlc_net_242 ) , .p223 ( optlc_net_243 ) ,
+ .p224 ( optlc_net_244 ) , .p225 ( optlc_net_245 ) ,
+ .p226 ( optlc_net_246 ) , .p227 ( optlc_net_247 ) ,
+ .p228 ( optlc_net_248 ) , .p229 ( optlc_net_249 ) ,
+ .p230 ( optlc_net_250 ) , .p231 ( optlc_net_251 ) ,
+ .p232 ( optlc_net_252 ) , .p233 ( optlc_net_253 ) ,
+ .p234 ( optlc_net_254 ) , .p235 ( optlc_net_255 ) ,
+ .p236 ( optlc_net_256 ) , .p237 ( optlc_net_257 ) ,
+ .p238 ( optlc_net_258 ) , .p239 ( optlc_net_259 ) ,
+ .p240 ( optlc_net_260 ) , .p241 ( optlc_net_261 ) ,
+ .p242 ( optlc_net_262 ) , .p243 ( optlc_net_263 ) ,
+ .p244 ( optlc_net_264 ) , .p245 ( optlc_net_265 ) ,
+ .p246 ( optlc_net_266 ) , .p247 ( optlc_net_267 ) ,
+ .p248 ( optlc_net_268 ) , .p249 ( optlc_net_269 ) ,
+ .p250 ( optlc_net_270 ) , .p251 ( optlc_net_271 ) ,
+ .p252 ( optlc_net_272 ) , .p253 ( optlc_net_273 ) ,
+ .p254 ( optlc_net_274 ) , .p255 ( optlc_net_275 ) ,
+ .p256 ( optlc_net_276 ) , .p257 ( optlc_net_277 ) ,
+ .p258 ( optlc_net_278 ) , .p259 ( optlc_net_279 ) ,
+ .p260 ( optlc_net_280 ) , .p261 ( optlc_net_281 ) ,
+ .p262 ( optlc_net_282 ) , .p263 ( optlc_net_283 ) ,
+ .p264 ( optlc_net_284 ) , .p265 ( optlc_net_285 ) ,
+ .p266 ( optlc_net_286 ) , .p267 ( optlc_net_287 ) ,
+ .p268 ( optlc_net_288 ) , .p269 ( optlc_net_289 ) ,
+ .p270 ( optlc_net_290 ) , .p271 ( optlc_net_291 ) ,
+ .p272 ( optlc_net_292 ) , .p273 ( optlc_net_293 ) ,
+ .p274 ( optlc_net_294 ) , .p275 ( optlc_net_295 ) ,
+ .p276 ( optlc_net_296 ) , .p277 ( optlc_net_297 ) ,
+ .p278 ( optlc_net_298 ) , .p279 ( optlc_net_299 ) ,
+ .p280 ( optlc_net_300 ) , .p281 ( optlc_net_301 ) ,
+ .p282 ( optlc_net_302 ) , .p283 ( optlc_net_303 ) ,
+ .p284 ( optlc_net_304 ) , .p285 ( optlc_net_305 ) ,
+ .p286 ( optlc_net_306 ) , .p287 ( optlc_net_307 ) ,
+ .p288 ( optlc_net_308 ) , .p289 ( optlc_net_309 ) ,
+ .p290 ( optlc_net_310 ) , .p291 ( optlc_net_311 ) ,
+ .p292 ( optlc_net_312 ) , .p293 ( optlc_net_313 ) ,
+ .p294 ( optlc_net_314 ) , .p295 ( optlc_net_315 ) ,
+ .p296 ( optlc_net_316 ) , .p297 ( optlc_net_317 ) ,
+ .p298 ( optlc_net_318 ) , .p299 ( optlc_net_319 ) ,
+ .p300 ( optlc_net_320 ) , .p301 ( optlc_net_321 ) ,
+ .p302 ( optlc_net_322 ) , .p303 ( optlc_net_323 ) ,
+ .p304 ( optlc_net_324 ) , .p305 ( optlc_net_325 ) ,
+ .p306 ( optlc_net_326 ) , .p307 ( optlc_net_327 ) ,
+ .p308 ( optlc_net_328 ) , .p309 ( optlc_net_329 ) ,
+ .p310 ( optlc_net_330 ) , .p311 ( optlc_net_331 ) ,
+ .p312 ( optlc_net_332 ) , .p313 ( optlc_net_333 ) ,
+ .p314 ( optlc_net_334 ) , .p315 ( optlc_net_335 ) ,
+ .p316 ( optlc_net_336 ) , .p317 ( optlc_net_337 ) ,
+ .p318 ( optlc_net_338 ) , .p319 ( optlc_net_339 ) ,
+ .p320 ( optlc_net_340 ) , .p321 ( optlc_net_341 ) ,
+ .p322 ( optlc_net_342 ) , .p323 ( optlc_net_343 ) ,
+ .p324 ( optlc_net_344 ) , .p325 ( optlc_net_345 ) ,
+ .p326 ( optlc_net_346 ) , .p327 ( optlc_net_347 ) ,
+ .p328 ( optlc_net_348 ) , .p329 ( optlc_net_349 ) ,
+ .p330 ( optlc_net_350 ) , .p331 ( optlc_net_351 ) ,
+ .p332 ( optlc_net_352 ) , .p333 ( optlc_net_353 ) ,
+ .p334 ( optlc_net_354 ) , .p335 ( optlc_net_355 ) ,
+ .p336 ( optlc_net_356 ) , .p337 ( optlc_net_357 ) ,
+ .p338 ( optlc_net_358 ) , .p339 ( optlc_net_359 ) ,
+ .p340 ( optlc_net_360 ) , .p341 ( optlc_net_361 ) ,
+ .p342 ( optlc_net_362 ) , .p343 ( optlc_net_363 ) ,
+ .p344 ( optlc_net_364 ) , .p345 ( optlc_net_365 ) ,
+ .p346 ( optlc_net_366 ) , .p347 ( optlc_net_367 ) ,
+ .p348 ( optlc_net_368 ) , .p349 ( optlc_net_369 ) ,
+ .p350 ( optlc_net_370 ) , .p351 ( optlc_net_371 ) ,
+ .p352 ( optlc_net_372 ) , .p353 ( optlc_net_373 ) ,
+ .p354 ( optlc_net_374 ) , .p355 ( optlc_net_375 ) ,
+ .p356 ( optlc_net_376 ) , .p357 ( optlc_net_377 ) ,
+ .p358 ( optlc_net_378 ) , .p359 ( optlc_net_379 ) ,
+ .p360 ( optlc_net_380 ) , .p361 ( optlc_net_381 ) ,
+ .p362 ( optlc_net_382 ) , .p363 ( optlc_net_383 ) ,
+ .p364 ( optlc_net_384 ) , .p365 ( optlc_net_385 ) ,
+ .p366 ( optlc_net_386 ) , .p367 ( optlc_net_387 ) ,
+ .p368 ( optlc_net_388 ) , .p369 ( optlc_net_389 ) ,
+ .p370 ( optlc_net_390 ) , .p371 ( optlc_net_391 ) ,
+ .p372 ( optlc_net_392 ) , .p373 ( optlc_net_393 ) ,
+ .p374 ( optlc_net_394 ) , .p375 ( optlc_net_395 ) ,
+ .p376 ( optlc_net_396 ) , .p377 ( optlc_net_397 ) ,
+ .p378 ( optlc_net_398 ) , .p379 ( optlc_net_399 ) ,
+ .p380 ( optlc_net_400 ) , .p381 ( optlc_net_401 ) ,
+ .p382 ( optlc_net_402 ) , .p383 ( optlc_net_403 ) ,
+ .p384 ( optlc_net_404 ) , .p385 ( optlc_net_405 ) ,
+ .p386 ( optlc_net_406 ) , .p387 ( optlc_net_407 ) ,
+ .p388 ( optlc_net_408 ) , .p389 ( optlc_net_409 ) ,
+ .p390 ( optlc_net_410 ) , .p391 ( optlc_net_411 ) ,
+ .p392 ( optlc_net_412 ) , .p393 ( optlc_net_413 ) ,
+ .p394 ( optlc_net_414 ) , .p395 ( optlc_net_415 ) ,
+ .p396 ( optlc_net_416 ) , .p397 ( optlc_net_417 ) ,
+ .p398 ( optlc_net_418 ) , .p399 ( optlc_net_419 ) ,
+ .p400 ( optlc_net_420 ) , .p401 ( optlc_net_421 ) ,
+ .p402 ( optlc_net_422 ) , .p403 ( optlc_net_423 ) ,
+ .p404 ( optlc_net_424 ) , .p405 ( optlc_net_425 ) ,
+ .p406 ( optlc_net_426 ) , .p407 ( optlc_net_427 ) ,
+ .p408 ( optlc_net_428 ) , .p409 ( optlc_net_429 ) ,
+ .p410 ( optlc_net_430 ) , .p411 ( optlc_net_431 ) ,
+ .p412 ( optlc_net_432 ) , .p413 ( optlc_net_433 ) ,
+ .p414 ( optlc_net_434 ) , .p415 ( optlc_net_435 ) ,
+ .p416 ( optlc_net_436 ) , .p417 ( optlc_net_437 ) ,
+ .p418 ( optlc_net_438 ) , .p419 ( optlc_net_439 ) ,
+ .p420 ( optlc_net_440 ) , .p421 ( optlc_net_441 ) ,
+ .p422 ( optlc_net_442 ) , .p423 ( optlc_net_443 ) ,
+ .p424 ( optlc_net_444 ) , .p425 ( optlc_net_445 ) ,
+ .p426 ( optlc_net_446 ) , .p427 ( optlc_net_447 ) ,
+ .p428 ( optlc_net_448 ) , .p429 ( optlc_net_449 ) ,
+ .p430 ( optlc_net_450 ) , .p431 ( optlc_net_451 ) ,
+ .p432 ( optlc_net_452 ) , .p433 ( optlc_net_453 ) ,
+ .p434 ( optlc_net_454 ) , .p435 ( optlc_net_455 ) ,
+ .p436 ( optlc_net_456 ) , .p437 ( optlc_net_457 ) ,
+ .p438 ( optlc_net_458 ) , .p439 ( optlc_net_459 ) ,
+ .p440 ( optlc_net_460 ) , .p441 ( optlc_net_461 ) ,
+ .p442 ( optlc_net_462 ) , .p443 ( optlc_net_463 ) ,
+ .p444 ( optlc_net_464 ) , .p445 ( optlc_net_465 ) ,
+ .p446 ( optlc_net_466 ) , .p447 ( optlc_net_467 ) ,
+ .p448 ( optlc_net_468 ) , .p449 ( optlc_net_469 ) ,
+ .p450 ( optlc_net_470 ) , .p451 ( optlc_net_471 ) ,
+ .p452 ( optlc_net_472 ) , .p453 ( optlc_net_473 ) ,
+ .p454 ( optlc_net_474 ) , .p455 ( optlc_net_475 ) ,
+ .p456 ( optlc_net_476 ) , .p457 ( optlc_net_477 ) ,
+ .p458 ( optlc_net_478 ) , .p459 ( optlc_net_479 ) ,
+ .p460 ( optlc_net_480 ) , .p461 ( optlc_net_481 ) ,
+ .p462 ( optlc_net_482 ) , .p463 ( optlc_net_483 ) ,
+ .p464 ( optlc_net_484 ) , .p465 ( optlc_net_485 ) ,
+ .p466 ( optlc_net_486 ) , .p467 ( optlc_net_487 ) ,
+ .p468 ( optlc_net_488 ) , .p469 ( optlc_net_489 ) ,
+ .p470 ( optlc_net_490 ) , .p471 ( optlc_net_491 ) ,
+ .p472 ( optlc_net_492 ) , .p473 ( optlc_net_493 ) ,
+ .p474 ( optlc_net_494 ) , .p475 ( optlc_net_495 ) ,
+ .p476 ( optlc_net_496 ) , .p477 ( optlc_net_497 ) ,
+ .p478 ( optlc_net_498 ) , .p479 ( optlc_net_499 ) ,
+ .p480 ( optlc_net_500 ) , .p481 ( optlc_net_501 ) ,
+ .p482 ( optlc_net_502 ) , .p483 ( optlc_net_503 ) ,
+ .p484 ( optlc_net_504 ) , .p485 ( optlc_net_505 ) ,
+ .p486 ( optlc_net_506 ) , .p487 ( optlc_net_507 ) ,
+ .p488 ( optlc_net_508 ) , .p489 ( optlc_net_509 ) ,
+ .p490 ( optlc_net_510 ) , .p491 ( optlc_net_511 ) ,
+ .p492 ( optlc_net_512 ) , .p493 ( optlc_net_513 ) ,
+ .p494 ( optlc_net_514 ) , .p495 ( optlc_net_515 ) ,
+ .p496 ( optlc_net_516 ) , .p497 ( optlc_net_517 ) ,
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+ .p500 ( optlc_net_520 ) , .p501 ( optlc_net_521 ) ,
+ .p502 ( optlc_net_522 ) , .p503 ( optlc_net_523 ) ,
+ .p504 ( optlc_net_524 ) , .p505 ( optlc_net_525 ) ,
+ .p506 ( optlc_net_526 ) , .p507 ( optlc_net_527 ) ,
+ .p508 ( optlc_net_528 ) , .p509 ( optlc_net_529 ) ,
+ .p510 ( optlc_net_530 ) , .p511 ( optlc_net_531 ) ,
+ .p512 ( optlc_net_532 ) , .p513 ( optlc_net_533 ) ,
+ .p514 ( optlc_net_534 ) , .p515 ( optlc_net_535 ) ,
+ .p516 ( optlc_net_536 ) , .p517 ( optlc_net_537 ) ,
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+ .p520 ( optlc_net_540 ) , .p521 ( optlc_net_541 ) ,
+ .p522 ( optlc_net_542 ) , .p523 ( optlc_net_543 ) ,
+ .p524 ( optlc_net_544 ) , .p525 ( optlc_net_545 ) ,
+ .p526 ( optlc_net_546 ) , .p527 ( optlc_net_547 ) ,
+ .p528 ( optlc_net_548 ) , .p529 ( optlc_net_549 ) ,
+ .p530 ( optlc_net_550 ) , .p531 ( optlc_net_551 ) ,
+ .p532 ( optlc_net_552 ) , .p533 ( optlc_net_553 ) ,
+ .p534 ( optlc_net_554 ) , .p535 ( optlc_net_555 ) ,
+ .p536 ( optlc_net_556 ) , .p537 ( optlc_net_557 ) ,
+ .p538 ( optlc_net_558 ) , .p539 ( optlc_net_559 ) ,
+ .p540 ( optlc_net_560 ) , .p541 ( optlc_net_561 ) ,
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+ .p544 ( optlc_net_564 ) , .p545 ( optlc_net_565 ) ,
+ .p546 ( optlc_net_566 ) , .p547 ( optlc_net_567 ) ,
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+ .p550 ( optlc_net_570 ) , .p551 ( optlc_net_571 ) ,
+ .p552 ( optlc_net_572 ) , .p553 ( optlc_net_573 ) ,
+ .p554 ( optlc_net_574 ) , .p555 ( optlc_net_575 ) ,
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+ .p590 ( optlc_net_610 ) , .p591 ( optlc_net_611 ) ,
+ .p592 ( optlc_net_612 ) , .p593 ( optlc_net_613 ) ,
+ .p594 ( optlc_net_614 ) , .p595 ( optlc_net_615 ) ,
+ .p596 ( optlc_net_616 ) , .p597 ( optlc_net_617 ) ,
+ .p598 ( optlc_net_618 ) , .p599 ( optlc_net_619 ) ,
+ .p600 ( optlc_net_620 ) , .p601 ( optlc_net_621 ) ,
+ .p602 ( optlc_net_622 ) , .p603 ( optlc_net_623 ) ,
+ .p604 ( optlc_net_624 ) , .p605 ( optlc_net_625 ) ,
+ .p606 ( optlc_net_626 ) , .p607 ( optlc_net_627 ) ,
+ .p608 ( optlc_net_628 ) , .p609 ( optlc_net_629 ) ,
+ .p610 ( optlc_net_630 ) , .p611 ( optlc_net_631 ) ,
+ .p612 ( optlc_net_632 ) , .p613 ( optlc_net_633 ) ,
+ .p614 ( optlc_net_634 ) , .p615 ( optlc_net_635 ) ,
+ .p616 ( optlc_net_636 ) , .p617 ( optlc_net_637 ) ,
+ .p618 ( optlc_net_638 ) , .p619 ( optlc_net_639 ) ,
+ .p620 ( optlc_net_640 ) , .p621 ( optlc_net_641 ) ,
+ .p622 ( optlc_net_642 ) , .p623 ( optlc_net_643 ) ,
+ .p624 ( optlc_net_644 ) , .p625 ( optlc_net_645 ) ,
+ .p626 ( optlc_net_646 ) , .p627 ( optlc_net_647 ) ,
+ .p628 ( optlc_net_648 ) , .p629 ( optlc_net_649 ) ,
+ .p630 ( optlc_net_650 ) , .p631 ( optlc_net_651 ) ,
+ .p632 ( optlc_net_652 ) , .p633 ( optlc_net_653 ) ,
+ .p634 ( optlc_net_654 ) , .p635 ( optlc_net_655 ) ,
+ .p636 ( optlc_net_656 ) , .p637 ( optlc_net_657 ) ,
+ .p638 ( optlc_net_658 ) , .p639 ( optlc_net_659 ) ,
+ .p640 ( optlc_net_660 ) , .p641 ( optlc_net_661 ) ,
+ .p642 ( optlc_net_662 ) , .p643 ( optlc_net_663 ) ,
+ .p644 ( optlc_net_664 ) , .p645 ( optlc_net_665 ) ,
+ .p646 ( optlc_net_666 ) , .p647 ( optlc_net_667 ) ,
+ .p648 ( optlc_net_668 ) , .p649 ( optlc_net_669 ) ,
+ .p650 ( optlc_net_670 ) , .p651 ( optlc_net_671 ) ,
+ .p652 ( optlc_net_672 ) , .p653 ( optlc_net_673 ) ,
+ .p654 ( optlc_net_674 ) , .p655 ( optlc_net_675 ) ,
+ .p656 ( optlc_net_676 ) , .p657 ( optlc_net_677 ) ,
+ .p658 ( optlc_net_678 ) , .p659 ( optlc_net_679 ) ,
+ .p660 ( optlc_net_680 ) , .p661 ( optlc_net_681 ) ,
+ .p662 ( optlc_net_682 ) , .p663 ( optlc_net_683 ) ,
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+ .p666 ( optlc_net_686 ) , .p667 ( optlc_net_687 ) ,
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+ .p670 ( optlc_net_690 ) , .p671 ( optlc_net_691 ) ,
+ .p672 ( optlc_net_692 ) , .p673 ( optlc_net_693 ) ,
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+ .p676 ( optlc_net_696 ) , .p677 ( optlc_net_697 ) ,
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+ .p680 ( optlc_net_700 ) , .p681 ( optlc_net_701 ) ,
+ .p682 ( optlc_net_702 ) , .p683 ( optlc_net_703 ) ,
+ .p684 ( optlc_net_704 ) , .p685 ( optlc_net_705 ) ,
+ .p686 ( optlc_net_706 ) , .p687 ( optlc_net_707 ) ,
+ .p688 ( optlc_net_708 ) , .p689 ( optlc_net_709 ) ,
+ .p690 ( optlc_net_710 ) , .p691 ( optlc_net_711 ) ,
+ .p692 ( optlc_net_712 ) , .p693 ( optlc_net_713 ) ,
+ .p694 ( optlc_net_714 ) , .p695 ( optlc_net_715 ) ,
+ .p696 ( optlc_net_716 ) , .p697 ( optlc_net_717 ) ,
+ .p698 ( optlc_net_718 ) , .p699 ( optlc_net_719 ) ,
+ .p700 ( optlc_net_720 ) , .p701 ( optlc_net_721 ) ,
+ .p702 ( optlc_net_722 ) , .p703 ( optlc_net_723 ) ,
+ .p704 ( optlc_net_724 ) , .p705 ( optlc_net_725 ) ,
+ .p706 ( optlc_net_726 ) , .p707 ( optlc_net_727 ) ,
+ .p708 ( optlc_net_728 ) , .p709 ( optlc_net_729 ) ,
+ .p710 ( optlc_net_730 ) , .p711 ( optlc_net_731 ) ,
+ .p712 ( optlc_net_732 ) , .p713 ( optlc_net_733 ) ,
+ .p714 ( optlc_net_734 ) , .p715 ( optlc_net_735 ) ,
+ .p716 ( optlc_net_736 ) , .p717 ( optlc_net_737 ) ,
+ .p718 ( optlc_net_738 ) , .p719 ( optlc_net_739 ) ,
+ .p720 ( optlc_net_740 ) , .p721 ( optlc_net_741 ) ,
+ .p722 ( optlc_net_742 ) , .p723 ( optlc_net_743 ) ,
+ .p724 ( optlc_net_744 ) , .p725 ( optlc_net_745 ) ,
+ .p726 ( optlc_net_746 ) , .p727 ( optlc_net_747 ) ,
+ .p728 ( optlc_net_748 ) , .p729 ( optlc_net_749 ) ,
+ .p730 ( optlc_net_750 ) , .p731 ( optlc_net_751 ) ,
+ .p732 ( optlc_net_752 ) , .p733 ( optlc_net_753 ) ,
+ .p734 ( optlc_net_754 ) , .p735 ( optlc_net_755 ) ,
+ .p736 ( optlc_net_756 ) , .p737 ( optlc_net_757 ) ,
+ .p738 ( optlc_net_758 ) , .p739 ( optlc_net_759 ) ,
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+ .p742 ( optlc_net_762 ) , .p743 ( optlc_net_763 ) ,
+ .p744 ( optlc_net_764 ) , .p745 ( optlc_net_765 ) ,
+ .p746 ( optlc_net_766 ) , .p747 ( optlc_net_767 ) ,
+ .p748 ( optlc_net_768 ) , .p749 ( optlc_net_769 ) ,
+ .p750 ( optlc_net_770 ) , .p751 ( optlc_net_771 ) ,
+ .p752 ( optlc_net_772 ) , .p753 ( optlc_net_773 ) ,
+ .p754 ( optlc_net_774 ) , .p755 ( optlc_net_775 ) ,
+ .p756 ( optlc_net_776 ) , .p757 ( optlc_net_777 ) ,
+ .p758 ( optlc_net_778 ) , .p759 ( optlc_net_779 ) ,
+ .p760 ( optlc_net_780 ) , .p761 ( optlc_net_781 ) ,
+ .p762 ( optlc_net_782 ) , .p763 ( optlc_net_783 ) ,
+ .p764 ( optlc_net_784 ) , .p765 ( optlc_net_785 ) ,
+ .p766 ( optlc_net_786 ) , .p767 ( optlc_net_787 ) ,
+ .p768 ( optlc_net_788 ) , .p769 ( optlc_net_789 ) ,
+ .p770 ( optlc_net_790 ) , .p771 ( optlc_net_791 ) ,
+ .p772 ( optlc_net_792 ) , .p773 ( optlc_net_793 ) ,
+ .p774 ( optlc_net_794 ) , .p775 ( optlc_net_795 ) ,
+ .p776 ( optlc_net_796 ) , .p777 ( optlc_net_797 ) ,
+ .p778 ( optlc_net_798 ) , .p779 ( optlc_net_799 ) ,
+ .p780 ( optlc_net_800 ) , .p781 ( optlc_net_801 ) ,
+ .p782 ( optlc_net_802 ) , .p783 ( optlc_net_803 ) ,
+ .p784 ( optlc_net_804 ) , .p785 ( optlc_net_805 ) ,
+ .p786 ( optlc_net_806 ) , .p787 ( optlc_net_807 ) ,
+ .p788 ( optlc_net_808 ) , .p789 ( optlc_net_809 ) ,
+ .p790 ( optlc_net_810 ) , .p791 ( optlc_net_811 ) ,
+ .p792 ( optlc_net_812 ) , .p793 ( optlc_net_813 ) ,
+ .p794 ( optlc_net_814 ) , .p795 ( optlc_net_815 ) ,
+ .p796 ( optlc_net_816 ) , .p797 ( optlc_net_817 ) ,
+ .p798 ( optlc_net_818 ) , .p799 ( optlc_net_819 ) ,
+ .p800 ( optlc_net_820 ) , .p801 ( optlc_net_821 ) ,
+ .p802 ( optlc_net_822 ) , .p803 ( optlc_net_823 ) ,
+ .p804 ( optlc_net_824 ) , .p805 ( optlc_net_825 ) ,
+ .p806 ( optlc_net_826 ) , .p807 ( optlc_net_827 ) ,
+ .p808 ( optlc_net_828 ) , .p809 ( optlc_net_829 ) ,
+ .p810 ( optlc_net_830 ) , .p811 ( optlc_net_831 ) ,
+ .p812 ( optlc_net_832 ) , .p813 ( optlc_net_833 ) ,
+ .p814 ( optlc_net_834 ) , .p815 ( optlc_net_835 ) ,
+ .p816 ( optlc_net_836 ) , .p817 ( optlc_net_837 ) ,
+ .p818 ( optlc_net_838 ) , .p819 ( optlc_net_839 ) ,
+ .p820 ( optlc_net_840 ) , .p821 ( optlc_net_841 ) ,
+ .p822 ( optlc_net_842 ) , .p823 ( optlc_net_843 ) ,
+ .p824 ( optlc_net_844 ) , .p825 ( optlc_net_845 ) ,
+ .p826 ( optlc_net_846 ) , .p827 ( optlc_net_847 ) ,
+ .p828 ( optlc_net_848 ) , .p829 ( optlc_net_849 ) ,
+ .p830 ( optlc_net_850 ) , .p831 ( optlc_net_851 ) ,
+ .p832 ( optlc_net_852 ) , .p833 ( optlc_net_853 ) ,
+ .p834 ( optlc_net_854 ) , .p835 ( optlc_net_855 ) ,
+ .p836 ( optlc_net_856 ) , .p837 ( optlc_net_857 ) ,
+ .p838 ( optlc_net_858 ) , .p839 ( optlc_net_859 ) ,
+ .p840 ( optlc_net_860 ) , .p841 ( optlc_net_861 ) ,
+ .p842 ( optlc_net_862 ) , .p843 ( optlc_net_863 ) ,
+ .p844 ( optlc_net_864 ) , .p845 ( optlc_net_865 ) ,
+ .p846 ( optlc_net_866 ) , .p847 ( optlc_net_867 ) ,
+ .p848 ( optlc_net_868 ) , .p849 ( optlc_net_869 ) ,
+ .p850 ( optlc_net_870 ) , .p851 ( optlc_net_871 ) ,
+ .p852 ( optlc_net_872 ) , .p853 ( optlc_net_873 ) ,
+ .p854 ( optlc_net_874 ) , .p855 ( optlc_net_875 ) ,
+ .p856 ( optlc_net_876 ) , .p857 ( optlc_net_877 ) ,
+ .p858 ( optlc_net_878 ) , .p859 ( optlc_net_879 ) ,
+ .p860 ( optlc_net_880 ) , .p861 ( optlc_net_881 ) ,
+ .p862 ( optlc_net_882 ) , .p863 ( optlc_net_883 ) ,
+ .p864 ( optlc_net_884 ) , .p865 ( optlc_net_885 ) ,
+ .p866 ( optlc_net_886 ) , .p867 ( optlc_net_887 ) ,
+ .p868 ( optlc_net_888 ) , .p869 ( optlc_net_889 ) ,
+ .p870 ( optlc_net_890 ) , .p871 ( optlc_net_891 ) ,
+ .p872 ( optlc_net_892 ) , .p873 ( optlc_net_893 ) ,
+ .p874 ( optlc_net_894 ) , .p875 ( optlc_net_895 ) ,
+ .p876 ( optlc_net_896 ) , .p877 ( optlc_net_897 ) ,
+ .p878 ( optlc_net_898 ) , .p879 ( optlc_net_899 ) ,
+ .p880 ( optlc_net_900 ) , .p881 ( optlc_net_901 ) ,
+ .p882 ( optlc_net_902 ) , .p883 ( optlc_net_903 ) ,
+ .p884 ( optlc_net_904 ) , .p885 ( optlc_net_905 ) ,
+ .p886 ( optlc_net_906 ) , .p887 ( optlc_net_907 ) ,
+ .p888 ( optlc_net_908 ) , .p889 ( optlc_net_909 ) ,
+ .p890 ( optlc_net_910 ) , .p891 ( optlc_net_911 ) ,
+ .p892 ( optlc_net_912 ) , .p893 ( optlc_net_913 ) ,
+ .p894 ( optlc_net_914 ) , .p895 ( optlc_net_915 ) ,
+ .p896 ( optlc_net_916 ) , .p897 ( optlc_net_917 ) ,
+ .p898 ( optlc_net_918 ) , .p899 ( optlc_net_919 ) ,
+ .p900 ( optlc_net_920 ) , .p901 ( optlc_net_921 ) ,
+ .p902 ( optlc_net_922 ) , .p903 ( optlc_net_923 ) ,
+ .p904 ( optlc_net_924 ) , .p905 ( optlc_net_925 ) ,
+ .p906 ( optlc_net_926 ) , .p907 ( optlc_net_927 ) ,
+ .p908 ( optlc_net_928 ) , .p909 ( optlc_net_929 ) ,
+ .p910 ( optlc_net_930 ) , .p911 ( optlc_net_931 ) ,
+ .p912 ( optlc_net_932 ) , .p913 ( optlc_net_933 ) ,
+ .p914 ( optlc_net_934 ) , .p915 ( optlc_net_935 ) ,
+ .p916 ( optlc_net_936 ) , .p917 ( optlc_net_937 ) ,
+ .p918 ( optlc_net_938 ) , .p919 ( optlc_net_939 ) ,
+ .p920 ( optlc_net_940 ) , .p921 ( optlc_net_941 ) ,
+ .p922 ( optlc_net_942 ) , .p923 ( optlc_net_943 ) ,
+ .p924 ( optlc_net_944 ) , .p925 ( optlc_net_945 ) ,
+ .p926 ( optlc_net_946 ) , .p927 ( optlc_net_947 ) ,
+ .p928 ( optlc_net_948 ) , .p929 ( optlc_net_949 ) ,
+ .p930 ( optlc_net_950 ) , .p931 ( optlc_net_951 ) ,
+ .p932 ( optlc_net_952 ) , .p933 ( optlc_net_953 ) ,
+ .p934 ( optlc_net_954 ) , .p935 ( optlc_net_955 ) ,
+ .p936 ( optlc_net_956 ) , .p937 ( optlc_net_957 ) ,
+ .p938 ( optlc_net_958 ) , .p939 ( optlc_net_959 ) ,
+ .p940 ( optlc_net_960 ) , .p941 ( optlc_net_961 ) ,
+ .p942 ( optlc_net_962 ) , .p943 ( optlc_net_963 ) ,
+ .p944 ( optlc_net_964 ) , .p945 ( optlc_net_965 ) ,
+ .p946 ( optlc_net_966 ) , .p947 ( optlc_net_967 ) ,
+ .p948 ( optlc_net_968 ) , .p949 ( optlc_net_969 ) ,
+ .p950 ( optlc_net_970 ) , .p951 ( optlc_net_971 ) ,
+ .p952 ( optlc_net_972 ) , .p953 ( optlc_net_973 ) ,
+ .p954 ( optlc_net_974 ) , .p955 ( optlc_net_975 ) ,
+ .p956 ( optlc_net_976 ) , .p957 ( optlc_net_977 ) ,
+ .p958 ( optlc_net_978 ) , .p959 ( optlc_net_979 ) ,
+ .p960 ( optlc_net_980 ) , .p961 ( optlc_net_981 ) ,
+ .p962 ( optlc_net_982 ) , .p963 ( optlc_net_983 ) ,
+ .p964 ( optlc_net_984 ) , .p965 ( optlc_net_985 ) ,
+ .p966 ( optlc_net_986 ) , .p967 ( optlc_net_987 ) ,
+ .p968 ( optlc_net_988 ) , .p969 ( optlc_net_989 ) ,
+ .p970 ( optlc_net_990 ) , .p971 ( optlc_net_991 ) ,
+ .p972 ( optlc_net_992 ) , .p973 ( optlc_net_993 ) ,
+ .p974 ( optlc_net_994 ) , .p975 ( optlc_net_995 ) ,
+ .p976 ( optlc_net_996 ) , .p977 ( optlc_net_997 ) ,
+ .p978 ( optlc_net_998 ) , .p979 ( optlc_net_999 ) ,
+ .p980 ( optlc_net_1000 ) , .p981 ( optlc_net_1001 ) ,
+ .p982 ( optlc_net_1002 ) , .p983 ( optlc_net_1003 ) ,
+ .p984 ( optlc_net_1004 ) , .p985 ( optlc_net_1005 ) ,
+ .p986 ( optlc_net_1006 ) , .p987 ( optlc_net_1007 ) ,
+ .p988 ( optlc_net_1008 ) , .p989 ( optlc_net_1009 ) ,
+ .p990 ( optlc_net_1010 ) , .p991 ( optlc_net_1011 ) ,
+ .p992 ( optlc_net_1012 ) , .p993 ( optlc_net_1013 ) ,
+ .p994 ( optlc_net_1014 ) , .p995 ( optlc_net_1015 ) ,
+ .p996 ( optlc_net_1016 ) , .p997 ( optlc_net_1017 ) ,
+ .p998 ( optlc_net_1018 ) , .p999 ( optlc_net_1019 ) ,
+ .p1000 ( optlc_net_1020 ) , .p1001 ( optlc_net_1021 ) ,
+ .p1002 ( optlc_net_1022 ) , .p1003 ( optlc_net_1023 ) ,
+ .p1004 ( optlc_net_1024 ) , .p1005 ( optlc_net_1025 ) ,
+ .p1006 ( optlc_net_1026 ) , .p1007 ( optlc_net_1027 ) ,
+ .p1008 ( optlc_net_1028 ) , .p1009 ( optlc_net_1029 ) ,
+ .p1010 ( optlc_net_1030 ) , .p1011 ( optlc_net_1031 ) ,
+ .p1012 ( optlc_net_1032 ) , .p1013 ( optlc_net_1033 ) ,
+ .p1014 ( optlc_net_1034 ) , .p1015 ( optlc_net_1035 ) ,
+ .p1016 ( optlc_net_1036 ) , .p1017 ( optlc_net_1037 ) ,
+ .p1018 ( optlc_net_1038 ) , .p1019 ( optlc_net_1039 ) ,
+ .p1020 ( optlc_net_1040 ) , .p1021 ( optlc_net_1041 ) ,
+ .p1022 ( optlc_net_1042 ) , .p1023 ( optlc_net_1043 ) ,
+ .p1024 ( optlc_net_1044 ) , .p1025 ( optlc_net_1045 ) ,
+ .p1026 ( optlc_net_1046 ) , .p1027 ( optlc_net_1047 ) ,
+ .p1028 ( optlc_net_1048 ) , .p1029 ( optlc_net_1049 ) ,
+ .p1030 ( optlc_net_1050 ) , .p1031 ( optlc_net_1051 ) ,
+ .p1032 ( optlc_net_1052 ) , .p1033 ( optlc_net_1053 ) ,
+ .p1034 ( optlc_net_1054 ) , .p1035 ( optlc_net_1055 ) ,
+ .p1036 ( optlc_net_1056 ) , .p1037 ( optlc_net_1057 ) ,
+ .p1038 ( optlc_net_1058 ) , .p1039 ( optlc_net_1059 ) ,
+ .p1040 ( optlc_net_1060 ) , .p1041 ( optlc_net_1061 ) ,
+ .p1042 ( optlc_net_1062 ) , .p1043 ( optlc_net_1063 ) ,
+ .p1044 ( optlc_net_1064 ) , .p1045 ( optlc_net_1065 ) ,
+ .p1046 ( optlc_net_1066 ) , .p1047 ( optlc_net_1067 ) ,
+ .p1048 ( optlc_net_1068 ) , .p1049 ( optlc_net_1069 ) ,
+ .p1050 ( optlc_net_1070 ) , .p1051 ( optlc_net_1071 ) ,
+ .p1052 ( optlc_net_1072 ) , .p1053 ( optlc_net_1073 ) ,
+ .p1054 ( optlc_net_1074 ) , .p1055 ( optlc_net_1075 ) ,
+ .p1056 ( optlc_net_1076 ) , .p1057 ( optlc_net_1077 ) ,
+ .p1058 ( optlc_net_1078 ) , .p1059 ( optlc_net_1079 ) ,
+ .p1060 ( optlc_net_1080 ) , .p1061 ( optlc_net_1081 ) ,
+ .p1062 ( optlc_net_1082 ) , .p1063 ( optlc_net_1083 ) ,
+ .p1064 ( optlc_net_1084 ) , .p1065 ( optlc_net_1085 ) ,
+ .p1066 ( optlc_net_1086 ) , .p1067 ( optlc_net_1087 ) ,
+ .p1068 ( optlc_net_1088 ) , .p1069 ( optlc_net_1089 ) ,
+ .p1070 ( optlc_net_1090 ) , .p1071 ( optlc_net_1091 ) ,
+ .p1072 ( optlc_net_1092 ) , .p1073 ( optlc_net_1093 ) ,
+ .p1074 ( optlc_net_1094 ) , .p1075 ( optlc_net_1095 ) ,
+ .p1076 ( optlc_net_1096 ) , .p1077 ( optlc_net_1097 ) ,
+ .p1078 ( optlc_net_1098 ) , .p1079 ( optlc_net_1099 ) ,
+ .p1080 ( optlc_net_1100 ) , .p1081 ( optlc_net_1101 ) ,
+ .p1082 ( optlc_net_1102 ) , .p1083 ( optlc_net_1103 ) ,
+ .p1084 ( optlc_net_1104 ) , .p1085 ( optlc_net_1105 ) ,
+ .p1086 ( optlc_net_1106 ) , .p1087 ( optlc_net_1107 ) ,
+ .p1088 ( optlc_net_1108 ) , .p1089 ( optlc_net_1109 ) ,
+ .p1090 ( optlc_net_1110 ) , .p1091 ( optlc_net_1111 ) ,
+ .p1092 ( optlc_net_1112 ) , .p1093 ( optlc_net_1113 ) ,
+ .p1094 ( optlc_net_1114 ) , .p1095 ( optlc_net_1115 ) ,
+ .p1096 ( optlc_net_1116 ) , .p1097 ( optlc_net_1117 ) ,
+ .p1098 ( optlc_net_1118 ) , .p1099 ( optlc_net_1119 ) ,
+ .p1100 ( optlc_net_1120 ) , .p1101 ( optlc_net_1121 ) ,
+ .p1102 ( optlc_net_1122 ) , .p1103 ( optlc_net_1123 ) ,
+ .p1104 ( optlc_net_1124 ) , .p1105 ( optlc_net_1125 ) ,
+ .p1106 ( optlc_net_1126 ) , .p1107 ( optlc_net_1127 ) ,
+ .p1108 ( optlc_net_1128 ) , .p1109 ( optlc_net_1129 ) ,
+ .p1110 ( optlc_net_1130 ) , .p1111 ( optlc_net_1131 ) ,
+ .p1112 ( optlc_net_1132 ) , .p1113 ( optlc_net_1133 ) ,
+ .p1114 ( optlc_net_1134 ) , .p1115 ( optlc_net_1135 ) ,
+ .p1116 ( optlc_net_1136 ) , .p1117 ( optlc_net_1137 ) ,
+ .p1118 ( optlc_net_1138 ) , .p1119 ( optlc_net_1139 ) ,
+ .p1120 ( optlc_net_1140 ) , .p1121 ( optlc_net_1141 ) ,
+ .p1122 ( optlc_net_1142 ) , .p1123 ( optlc_net_1143 ) ,
+ .p1124 ( optlc_net_1144 ) , .p1125 ( optlc_net_1145 ) ,
+ .p1126 ( optlc_net_1146 ) , .p1127 ( optlc_net_1147 ) ,
+ .p1128 ( optlc_net_1148 ) , .p1129 ( optlc_net_1149 ) ,
+ .p1130 ( optlc_net_1150 ) , .p1131 ( optlc_net_1151 ) ,
+ .p1132 ( optlc_net_1152 ) , .p1133 ( optlc_net_1153 ) ,
+ .p1134 ( optlc_net_1154 ) , .p1135 ( optlc_net_1155 ) ,
+ .p1136 ( optlc_net_1156 ) , .p1137 ( optlc_net_1157 ) ,
+ .p1138 ( optlc_net_1158 ) , .p1139 ( optlc_net_1159 ) ,
+ .p1140 ( optlc_net_1160 ) , .p1141 ( optlc_net_1161 ) ,
+ .p1142 ( optlc_net_1162 ) , .p1143 ( optlc_net_1163 ) ,
+ .p1144 ( optlc_net_1164 ) , .p1145 ( optlc_net_1165 ) ,
+ .p1146 ( optlc_net_1166 ) , .p1147 ( optlc_net_1167 ) ,
+ .p1148 ( optlc_net_1168 ) , .p1149 ( optlc_net_1169 ) ,
+ .p1150 ( optlc_net_1170 ) , .p1151 ( optlc_net_1171 ) ,
+ .p1152 ( optlc_net_1172 ) , .p1153 ( optlc_net_1173 ) ,
+ .p1154 ( optlc_net_1174 ) , .p1155 ( optlc_net_1175 ) ,
+ .p1156 ( optlc_net_1176 ) , .p1157 ( optlc_net_1177 ) ,
+ .p1158 ( optlc_net_1178 ) , .p1159 ( optlc_net_1179 ) ,
+ .p1160 ( optlc_net_1180 ) , .p1161 ( optlc_net_1181 ) ,
+ .p1162 ( optlc_net_1182 ) , .p1163 ( optlc_net_1183 ) ,
+ .p1164 ( optlc_net_1184 ) , .p1165 ( optlc_net_1185 ) ,
+ .p1166 ( optlc_net_1186 ) , .p1167 ( optlc_net_1187 ) ,
+ .p1168 ( optlc_net_1188 ) , .p1169 ( optlc_net_1189 ) ,
+ .p1170 ( optlc_net_1190 ) , .p1171 ( optlc_net_1191 ) ,
+ .p1172 ( optlc_net_1192 ) , .p1173 ( optlc_net_1193 ) ,
+ .p1174 ( optlc_net_1194 ) , .p1175 ( optlc_net_1195 ) ,
+ .p1176 ( optlc_net_1196 ) , .p1177 ( optlc_net_1197 ) ,
+ .p1178 ( optlc_net_1198 ) , .p1179 ( optlc_net_1199 ) ,
+ .p1180 ( optlc_net_1200 ) , .p1181 ( optlc_net_1201 ) ,
+ .p1182 ( optlc_net_1202 ) , .p1183 ( optlc_net_1203 ) ,
+ .p1184 ( optlc_net_1204 ) , .p1185 ( optlc_net_1205 ) ,
+ .p1186 ( optlc_net_1206 ) , .p1187 ( optlc_net_1207 ) ,
+ .p1188 ( optlc_net_1208 ) , .p1189 ( optlc_net_1209 ) ,
+ .p1190 ( optlc_net_1210 ) , .p1191 ( optlc_net_1211 ) ,
+ .p1192 ( optlc_net_1212 ) , .p1193 ( optlc_net_1213 ) ,
+ .p1194 ( optlc_net_1214 ) , .p1195 ( optlc_net_1215 ) ,
+ .p1196 ( optlc_net_1216 ) , .p1197 ( optlc_net_1217 ) ,
+ .p1198 ( optlc_net_1218 ) , .p1199 ( optlc_net_1219 ) ,
+ .p1200 ( optlc_net_1220 ) , .p1201 ( optlc_net_1221 ) ,
+ .p1202 ( optlc_net_1222 ) , .p1203 ( optlc_net_1223 ) ,
+ .p1204 ( optlc_net_1224 ) , .p1205 ( optlc_net_1225 ) ,
+ .p1206 ( optlc_net_1226 ) , .p1207 ( optlc_net_1227 ) ,
+ .p1208 ( optlc_net_1228 ) , .p1209 ( optlc_net_1229 ) ,
+ .p1210 ( optlc_net_1230 ) , .p1211 ( optlc_net_1231 ) ,
+ .p1212 ( optlc_net_1232 ) , .p1213 ( optlc_net_1233 ) ,
+ .p1214 ( optlc_net_1234 ) , .p1215 ( optlc_net_1235 ) ,
+ .p1216 ( optlc_net_1236 ) , .p1217 ( optlc_net_1237 ) ,
+ .p1218 ( optlc_net_1238 ) , .p1219 ( optlc_net_1239 ) ,
+ .p1220 ( optlc_net_1240 ) , .p1221 ( optlc_net_1241 ) ,
+ .p1222 ( optlc_net_1242 ) , .p1223 ( optlc_net_1243 ) ,
+ .p1224 ( optlc_net_1244 ) , .p1225 ( optlc_net_1245 ) ,
+ .p1226 ( optlc_net_1246 ) , .p1227 ( optlc_net_1247 ) ,
+ .p1228 ( optlc_net_1248 ) , .p1229 ( optlc_net_1249 ) ,
+ .p1230 ( optlc_net_1250 ) , .p1231 ( optlc_net_1251 ) ,
+ .p1232 ( optlc_net_1252 ) , .p1233 ( optlc_net_1253 ) ,
+ .p1234 ( optlc_net_1254 ) , .p1235 ( optlc_net_1255 ) ,
+ .p1236 ( optlc_net_1256 ) , .p1237 ( optlc_net_1257 ) ,
+ .p1238 ( optlc_net_1258 ) , .p1239 ( optlc_net_1259 ) ,
+ .p1240 ( optlc_net_1260 ) , .p1241 ( optlc_net_1261 ) ,
+ .p1242 ( optlc_net_1262 ) , .p1243 ( optlc_net_1263 ) ,
+ .p1244 ( optlc_net_1264 ) , .p1245 ( optlc_net_1265 ) ,
+ .p1246 ( optlc_net_1266 ) , .p1247 ( optlc_net_1267 ) ,
+ .p1248 ( optlc_net_1268 ) , .p1249 ( optlc_net_1269 ) ,
+ .p1250 ( optlc_net_1270 ) , .p1251 ( optlc_net_1271 ) ,
+ .p1252 ( optlc_net_1272 ) , .p1253 ( optlc_net_1273 ) ,
+ .p1254 ( optlc_net_1274 ) , .p1255 ( optlc_net_1275 ) ,
+ .p1256 ( optlc_net_1276 ) , .p1257 ( optlc_net_1277 ) ,
+ .p1258 ( optlc_net_1278 ) , .p1259 ( optlc_net_1279 ) ,
+ .p1260 ( optlc_net_1280 ) , .p1261 ( optlc_net_1281 ) ,
+ .p1262 ( optlc_net_1282 ) , .p1263 ( optlc_net_1283 ) ,
+ .p1264 ( optlc_net_1284 ) , .p1265 ( optlc_net_1285 ) ,
+ .p1266 ( optlc_net_1286 ) , .p1267 ( optlc_net_1287 ) ,
+ .p1268 ( optlc_net_1288 ) , .p1269 ( optlc_net_1289 ) ,
+ .p1270 ( optlc_net_1290 ) , .p1271 ( optlc_net_1291 ) ,
+ .p1272 ( optlc_net_1292 ) , .p1273 ( optlc_net_1293 ) ,
+ .p1274 ( optlc_net_1294 ) , .p1275 ( optlc_net_1295 ) ,
+ .p1276 ( optlc_net_1296 ) , .p1277 ( optlc_net_1297 ) ,
+ .p1278 ( optlc_net_1298 ) , .p1279 ( optlc_net_1299 ) ,
+ .p1280 ( optlc_net_1300 ) , .p1281 ( optlc_net_1301 ) ,
+ .p1282 ( optlc_net_1302 ) , .p1283 ( optlc_net_1303 ) ,
+ .p1284 ( optlc_net_1304 ) , .p1285 ( optlc_net_1305 ) ,
+ .p1286 ( optlc_net_1306 ) , .p1287 ( optlc_net_1307 ) ,
+ .p1288 ( optlc_net_1308 ) , .p1289 ( optlc_net_1309 ) ,
+ .p1290 ( optlc_net_1310 ) , .p1291 ( optlc_net_1311 ) ,
+ .p1292 ( optlc_net_1312 ) , .p1293 ( optlc_net_1313 ) ,
+ .p1294 ( optlc_net_1314 ) , .p1295 ( optlc_net_1315 ) ,
+ .p1296 ( optlc_net_1316 ) , .p1297 ( optlc_net_1317 ) ,
+ .p1298 ( optlc_net_1318 ) , .p1299 ( optlc_net_1319 ) ,
+ .p1300 ( optlc_net_1320 ) , .p1301 ( optlc_net_1321 ) ,
+ .p1302 ( optlc_net_1322 ) , .p1303 ( optlc_net_1323 ) ,
+ .p1304 ( optlc_net_1324 ) , .p1305 ( optlc_net_1325 ) ,
+ .p1306 ( optlc_net_1326 ) , .p1307 ( optlc_net_1327 ) ,
+ .p1308 ( optlc_net_1328 ) , .p1309 ( optlc_net_1329 ) ,
+ .p1310 ( optlc_net_1330 ) , .p1311 ( optlc_net_1331 ) ,
+ .p1312 ( optlc_net_1332 ) , .p1313 ( optlc_net_1333 ) ,
+ .p1314 ( optlc_net_1334 ) , .p1315 ( optlc_net_1335 ) ,
+ .p1316 ( optlc_net_1336 ) , .p1317 ( optlc_net_1337 ) ,
+ .p1318 ( optlc_net_1338 ) , .p1319 ( optlc_net_1339 ) ,
+ .p1320 ( optlc_net_1340 ) , .p1321 ( optlc_net_1341 ) ,
+ .p1322 ( optlc_net_1342 ) , .p1323 ( optlc_net_1343 ) ,
+ .p1324 ( optlc_net_1344 ) , .p1325 ( optlc_net_1345 ) ,
+ .p1326 ( optlc_net_1346 ) , .p1327 ( optlc_net_1347 ) ,
+ .p1328 ( optlc_net_1348 ) , .p1329 ( optlc_net_1349 ) ,
+ .p1330 ( optlc_net_1350 ) , .p1331 ( optlc_net_1351 ) ,
+ .p1332 ( optlc_net_1352 ) , .p1333 ( optlc_net_1353 ) ,
+ .p1334 ( optlc_net_1354 ) , .p1335 ( optlc_net_1355 ) ,
+ .p1336 ( optlc_net_1356 ) , .p1337 ( optlc_net_1357 ) ,
+ .p1338 ( optlc_net_1358 ) , .p1339 ( optlc_net_1359 ) ,
+ .p1340 ( optlc_net_1360 ) , .p1341 ( optlc_net_1361 ) ,
+ .p1342 ( optlc_net_1362 ) , .p1343 ( optlc_net_1363 ) ,
+ .p1344 ( optlc_net_1364 ) , .p1345 ( optlc_net_1365 ) ,
+ .p1346 ( optlc_net_1366 ) , .p1347 ( optlc_net_1367 ) ,
+ .p1348 ( optlc_net_1368 ) , .p1349 ( optlc_net_1369 ) ,
+ .p1350 ( optlc_net_1370 ) , .p1351 ( optlc_net_1371 ) ,
+ .p1352 ( optlc_net_1372 ) , .p1353 ( optlc_net_1373 ) ,
+ .p1354 ( optlc_net_1374 ) , .p1355 ( optlc_net_1375 ) ,
+ .p1356 ( optlc_net_1376 ) , .p1357 ( optlc_net_1377 ) ,
+ .p1358 ( optlc_net_1378 ) , .p1359 ( optlc_net_1379 ) ,
+ .p1360 ( optlc_net_1380 ) , .p1361 ( optlc_net_1381 ) ,
+ .p1362 ( optlc_net_1382 ) , .p1363 ( optlc_net_1383 ) ,
+ .p1364 ( optlc_net_1384 ) , .p1365 ( optlc_net_1385 ) ,
+ .p1366 ( optlc_net_1386 ) , .p1367 ( optlc_net_1387 ) ,
+ .p1368 ( optlc_net_1388 ) , .p1369 ( optlc_net_1389 ) ,
+ .p1370 ( optlc_net_1390 ) , .p1371 ( optlc_net_1391 ) ,
+ .p1372 ( optlc_net_1392 ) , .p1373 ( optlc_net_1393 ) ,
+ .p1374 ( optlc_net_1394 ) , .p1375 ( optlc_net_1395 ) ,
+ .p1376 ( optlc_net_1396 ) , .p1377 ( optlc_net_1397 ) ,
+ .p1378 ( optlc_net_1398 ) , .p1379 ( optlc_net_1399 ) ,
+ .p1380 ( optlc_net_1400 ) , .p1381 ( optlc_net_1401 ) ,
+ .p1382 ( optlc_net_1402 ) , .p1383 ( optlc_net_1403 ) ,
+ .p1384 ( optlc_net_1404 ) , .p1385 ( optlc_net_1405 ) ,
+ .p1386 ( optlc_net_1406 ) , .p1387 ( optlc_net_1407 ) ,
+ .p1388 ( optlc_net_1408 ) , .p1389 ( optlc_net_1409 ) ,
+ .p1390 ( optlc_net_1410 ) , .p1391 ( optlc_net_1411 ) ,
+ .p1392 ( optlc_net_1412 ) , .p1393 ( optlc_net_1413 ) ,
+ .p1394 ( optlc_net_1414 ) , .p1395 ( optlc_net_1415 ) ,
+ .p1396 ( optlc_net_1416 ) , .p1397 ( optlc_net_1417 ) ,
+ .p1398 ( optlc_net_1418 ) , .p1399 ( optlc_net_1419 ) ,
+ .p1400 ( optlc_net_1420 ) , .p1401 ( optlc_net_1421 ) ,
+ .p1402 ( optlc_net_1422 ) , .p1403 ( optlc_net_1423 ) ,
+ .p1404 ( optlc_net_1424 ) , .p1405 ( optlc_net_1425 ) ,
+ .p1406 ( optlc_net_1426 ) , .p1407 ( optlc_net_1427 ) ,
+ .p1408 ( optlc_net_1428 ) , .p1409 ( optlc_net_1429 ) ,
+ .p1410 ( optlc_net_1430 ) , .p1411 ( optlc_net_1431 ) ,
+ .p1412 ( optlc_net_1432 ) , .p1413 ( optlc_net_1433 ) ,
+ .p1414 ( optlc_net_1434 ) , .p1415 ( optlc_net_1435 ) ,
+ .p1416 ( optlc_net_1436 ) , .p1417 ( optlc_net_1437 ) ,
+ .p1418 ( optlc_net_1438 ) , .p1419 ( optlc_net_1439 ) ,
+ .p1420 ( optlc_net_1440 ) , .p1421 ( optlc_net_1441 ) ,
+ .p1422 ( optlc_net_1442 ) , .p1423 ( optlc_net_1443 ) ,
+ .p1424 ( optlc_net_1444 ) , .p1425 ( optlc_net_1445 ) ,
+ .p1426 ( optlc_net_1446 ) , .p1427 ( optlc_net_1447 ) ,
+ .p1428 ( optlc_net_1448 ) , .p1429 ( optlc_net_1449 ) ,
+ .p1430 ( optlc_net_1450 ) , .p1431 ( optlc_net_1451 ) ,
+ .p1432 ( optlc_net_1452 ) , .p1433 ( optlc_net_1453 ) ,
+ .p1434 ( optlc_net_1454 ) , .p1435 ( optlc_net_1455 ) ,
+ .p1436 ( optlc_net_1456 ) , .p1437 ( optlc_net_1457 ) ,
+ .p1438 ( optlc_net_1458 ) , .p1439 ( optlc_net_1459 ) ,
+ .p1440 ( optlc_net_1460 ) , .p1441 ( optlc_net_1461 ) ,
+ .p1442 ( optlc_net_1462 ) , .p1443 ( optlc_net_1463 ) ,
+ .p1444 ( optlc_net_1464 ) , .p1445 ( optlc_net_1465 ) ,
+ .p1446 ( optlc_net_1466 ) , .p1447 ( optlc_net_1467 ) ,
+ .p1448 ( optlc_net_1468 ) , .p1449 ( optlc_net_1469 ) ,
+ .p1450 ( optlc_net_1470 ) , .p1451 ( optlc_net_1471 ) ,
+ .p1452 ( optlc_net_1472 ) , .p1453 ( optlc_net_1473 ) ,
+ .p1454 ( optlc_net_1474 ) , .p1455 ( optlc_net_1475 ) ,
+ .p1456 ( optlc_net_1476 ) , .p1457 ( optlc_net_1477 ) ,
+ .p1458 ( optlc_net_1478 ) , .p1459 ( optlc_net_1479 ) ,
+ .p1460 ( optlc_net_1480 ) , .p1461 ( optlc_net_1481 ) ,
+ .p1462 ( optlc_net_1482 ) , .p1463 ( optlc_net_1483 ) ,
+ .p1464 ( optlc_net_1484 ) , .p1465 ( optlc_net_1485 ) ,
+ .p1466 ( optlc_net_1486 ) , .p1467 ( optlc_net_1487 ) ,
+ .p1468 ( optlc_net_1488 ) , .p1469 ( optlc_net_1489 ) ,
+ .p1470 ( optlc_net_1490 ) , .p1471 ( optlc_net_1491 ) ,
+ .p1472 ( optlc_net_1492 ) , .p1473 ( optlc_net_1493 ) ,
+ .p1474 ( optlc_net_1494 ) , .p1475 ( optlc_net_1495 ) ,
+ .p1476 ( optlc_net_1496 ) , .p1477 ( optlc_net_1497 ) ,
+ .p1478 ( optlc_net_1498 ) , .p1479 ( optlc_net_1499 ) ,
+ .p1480 ( optlc_net_1500 ) , .p1481 ( optlc_net_1501 ) ,
+ .p1482 ( optlc_net_1502 ) , .p1483 ( optlc_net_1503 ) ,
+ .p1484 ( optlc_net_1504 ) , .p1485 ( optlc_net_1505 ) ,
+ .p1486 ( optlc_net_1506 ) , .p1487 ( optlc_net_1507 ) ,
+ .p1488 ( optlc_net_1508 ) , .p1489 ( optlc_net_1509 ) ,
+ .p1490 ( optlc_net_1510 ) , .p1491 ( optlc_net_1511 ) ,
+ .p1492 ( optlc_net_1512 ) , .p1493 ( optlc_net_1513 ) ,
+ .p1494 ( optlc_net_1514 ) , .p1495 ( optlc_net_1515 ) ,
+ .p1496 ( optlc_net_1516 ) , .p1497 ( optlc_net_1517 ) ,
+ .p1498 ( optlc_net_1518 ) , .p1499 ( optlc_net_1519 ) ,
+ .p1500 ( optlc_net_1520 ) , .p1501 ( optlc_net_1521 ) ,
+ .p1502 ( optlc_net_1522 ) , .p1503 ( optlc_net_1523 ) ,
+ .p1504 ( optlc_net_1524 ) , .p1505 ( optlc_net_1525 ) ,
+ .p1506 ( optlc_net_1526 ) , .p1507 ( optlc_net_1527 ) ,
+ .p1508 ( optlc_net_1528 ) , .p1509 ( optlc_net_1529 ) ,
+ .p1510 ( optlc_net_1530 ) , .p1511 ( optlc_net_1531 ) ,
+ .p1512 ( optlc_net_1532 ) , .p1513 ( optlc_net_1533 ) ,
+ .p1514 ( optlc_net_1534 ) , .p1515 ( optlc_net_1535 ) ,
+ .p1516 ( optlc_net_1536 ) , .p1517 ( optlc_net_1537 ) ,
+ .p1518 ( optlc_net_1538 ) , .p1519 ( optlc_net_1539 ) ,
+ .p1520 ( optlc_net_1540 ) , .p1521 ( optlc_net_1541 ) ,
+ .p1522 ( optlc_net_1542 ) , .p1523 ( optlc_net_1543 ) ,
+ .p1524 ( optlc_net_1544 ) , .p1525 ( optlc_net_1545 ) ,
+ .p1526 ( optlc_net_1546 ) , .p1527 ( optlc_net_1547 ) ,
+ .p1528 ( optlc_net_1548 ) , .p1529 ( optlc_net_1549 ) ,
+ .p1530 ( optlc_net_1550 ) , .p1531 ( optlc_net_1551 ) ,
+ .p1532 ( optlc_net_1552 ) , .p1533 ( optlc_net_1553 ) ,
+ .p1534 ( optlc_net_1554 ) , .p1535 ( optlc_net_1555 ) ,
+ .p1536 ( optlc_net_1556 ) , .p1537 ( optlc_net_1557 ) ,
+ .p1538 ( optlc_net_1558 ) , .p1539 ( optlc_net_1559 ) ,
+ .p1540 ( optlc_net_1560 ) , .p1541 ( optlc_net_1561 ) ,
+ .p1542 ( optlc_net_1562 ) , .p1543 ( optlc_net_1563 ) ,
+ .p1544 ( optlc_net_1564 ) , .p1545 ( optlc_net_1565 ) ,
+ .p1546 ( optlc_net_1566 ) , .p1547 ( optlc_net_1567 ) ,
+ .p1548 ( optlc_net_1568 ) , .p1549 ( optlc_net_1569 ) ,
+ .p1550 ( optlc_net_1570 ) , .p1551 ( optlc_net_1571 ) ,
+ .p1552 ( optlc_net_1572 ) , .p1553 ( optlc_net_1573 ) ,
+ .p1554 ( optlc_net_1574 ) , .p1555 ( optlc_net_1575 ) ,
+ .p1556 ( optlc_net_1576 ) , .p1557 ( optlc_net_1577 ) ,
+ .p1558 ( optlc_net_1578 ) , .p1559 ( optlc_net_1579 ) ,
+ .p1560 ( optlc_net_1580 ) , .p1561 ( optlc_net_1581 ) ,
+ .p1562 ( optlc_net_1582 ) , .p1563 ( optlc_net_1583 ) ,
+ .p1564 ( optlc_net_1584 ) , .p1565 ( optlc_net_1585 ) ,
+ .p1566 ( optlc_net_1586 ) , .p1567 ( optlc_net_1587 ) ,
+ .p1568 ( optlc_net_1588 ) , .p1569 ( optlc_net_1589 ) ,
+ .p1570 ( optlc_net_1590 ) , .p1571 ( optlc_net_1591 ) ,
+ .p1572 ( optlc_net_1592 ) , .p1573 ( optlc_net_1593 ) ,
+ .p1574 ( optlc_net_1594 ) , .p1575 ( optlc_net_1595 ) ,
+ .p1576 ( optlc_net_1596 ) , .p1577 ( optlc_net_1597 ) ,
+ .p1578 ( optlc_net_1598 ) , .p1579 ( optlc_net_1599 ) ,
+ .p1580 ( optlc_net_1600 ) , .p1581 ( optlc_net_1601 ) ,
+ .p1582 ( optlc_net_1602 ) , .p1583 ( optlc_net_1603 ) ,
+ .p1584 ( optlc_net_1604 ) , .p1585 ( optlc_net_1605 ) ,
+ .p1586 ( optlc_net_1606 ) , .p1587 ( optlc_net_1607 ) ,
+ .p1588 ( optlc_net_1608 ) , .p1589 ( optlc_net_1609 ) ,
+ .p1590 ( optlc_net_1610 ) , .p1591 ( optlc_net_1611 ) ,
+ .p1592 ( optlc_net_1612 ) , .p1593 ( optlc_net_1613 ) ,
+ .p1594 ( optlc_net_1614 ) , .p1595 ( optlc_net_1615 ) ,
+ .p1596 ( optlc_net_1616 ) , .p1597 ( optlc_net_1617 ) ,
+ .p1598 ( optlc_net_1618 ) , .p1599 ( optlc_net_1619 ) ,
+ .p1600 ( optlc_net_1620 ) , .p1601 ( optlc_net_1621 ) ,
+ .p1602 ( optlc_net_1622 ) , .p1603 ( optlc_net_1623 ) ,
+ .p1604 ( optlc_net_1624 ) , .p1605 ( optlc_net_1625 ) ,
+ .p1606 ( optlc_net_1626 ) , .p1607 ( optlc_net_1627 ) ,
+ .p1608 ( optlc_net_1628 ) , .p1609 ( optlc_net_1629 ) ,
+ .p1610 ( optlc_net_1630 ) , .p1611 ( optlc_net_1631 ) ,
+ .p1612 ( optlc_net_1632 ) , .p1613 ( optlc_net_1633 ) ,
+ .p1614 ( optlc_net_1634 ) , .p1615 ( optlc_net_1635 ) ,
+ .p1616 ( optlc_net_1636 ) , .p1617 ( optlc_net_1637 ) ,
+ .p1618 ( optlc_net_1638 ) , .p1619 ( optlc_net_1639 ) ,
+ .p1620 ( optlc_net_1640 ) , .p1621 ( optlc_net_1641 ) ,
+ .p1622 ( optlc_net_1642 ) , .p1623 ( optlc_net_1643 ) ,
+ .p1624 ( optlc_net_1644 ) , .p1625 ( optlc_net_1645 ) ,
+ .p1626 ( optlc_net_1646 ) , .p1627 ( optlc_net_1647 ) ,
+ .p1628 ( optlc_net_1648 ) , .p1629 ( optlc_net_1649 ) ,
+ .p1630 ( optlc_net_1650 ) , .p1631 ( optlc_net_1651 ) ,
+ .p1632 ( optlc_net_1652 ) , .p1633 ( optlc_net_1653 ) ,
+ .p1634 ( optlc_net_1654 ) , .p1635 ( optlc_net_1655 ) ,
+ .p1636 ( optlc_net_1656 ) , .p1637 ( optlc_net_1657 ) ,
+ .p1638 ( optlc_net_1658 ) , .p1639 ( optlc_net_1659 ) ,
+ .p1640 ( optlc_net_1660 ) , .p1641 ( optlc_net_1661 ) ,
+ .p1642 ( optlc_net_1662 ) , .p1643 ( optlc_net_1663 ) ,
+ .p1644 ( optlc_net_1664 ) , .p1645 ( optlc_net_1665 ) ,
+ .p1646 ( optlc_net_1666 ) , .p1647 ( optlc_net_1667 ) ,
+ .p1648 ( optlc_net_1668 ) , .p1649 ( optlc_net_1669 ) ,
+ .p1650 ( optlc_net_1670 ) , .p1651 ( optlc_net_1671 ) ,
+ .p1652 ( optlc_net_1672 ) , .p1653 ( optlc_net_1673 ) ,
+ .p1654 ( optlc_net_1674 ) , .p1655 ( optlc_net_1675 ) ,
+ .p1656 ( optlc_net_1676 ) , .p1657 ( optlc_net_1677 ) ,
+ .p1658 ( optlc_net_1678 ) , .p1659 ( optlc_net_1679 ) ,
+ .p1660 ( optlc_net_1680 ) , .p1661 ( optlc_net_1681 ) ,
+ .p1662 ( optlc_net_1682 ) , .p1663 ( optlc_net_1683 ) ,
+ .p1664 ( optlc_net_1684 ) , .p1665 ( optlc_net_1685 ) ,
+ .p1666 ( optlc_net_1686 ) , .p1667 ( optlc_net_1687 ) ,
+ .p1668 ( optlc_net_1688 ) , .p1669 ( optlc_net_1689 ) ,
+ .p1670 ( optlc_net_1690 ) , .p1671 ( optlc_net_1691 ) ,
+ .p1672 ( optlc_net_1692 ) , .p1673 ( optlc_net_1693 ) ,
+ .p1674 ( optlc_net_1694 ) , .p1675 ( optlc_net_1695 ) ,
+ .p1676 ( optlc_net_1696 ) , .p1677 ( optlc_net_1697 ) ,
+ .p1678 ( optlc_net_1698 ) , .p1679 ( optlc_net_1699 ) ,
+ .p1680 ( optlc_net_1700 ) , .p1681 ( optlc_net_1701 ) ,
+ .p1682 ( optlc_net_1702 ) , .p1683 ( optlc_net_1703 ) ,
+ .p1684 ( optlc_net_1704 ) , .p1685 ( optlc_net_1705 ) ,
+ .p1686 ( optlc_net_1706 ) , .p1687 ( optlc_net_1707 ) ,
+ .p1688 ( optlc_net_1708 ) , .p1689 ( optlc_net_1709 ) ,
+ .p1690 ( optlc_net_1710 ) , .p1691 ( optlc_net_1711 ) ,
+ .p1692 ( optlc_net_1712 ) , .p1693 ( optlc_net_1713 ) ,
+ .p1694 ( optlc_net_1714 ) , .p1695 ( optlc_net_1715 ) ,
+ .p1696 ( optlc_net_1716 ) , .p1697 ( optlc_net_1717 ) ,
+ .p1698 ( optlc_net_1718 ) , .p1699 ( optlc_net_1719 ) ,
+ .p1700 ( optlc_net_1720 ) , .p1701 ( optlc_net_1721 ) ,
+ .p1702 ( optlc_net_1722 ) , .p1703 ( optlc_net_1723 ) ,
+ .p1704 ( optlc_net_1724 ) , .p1705 ( optlc_net_1725 ) ,
+ .p1706 ( optlc_net_1726 ) , .p1707 ( optlc_net_1727 ) ,
+ .p1708 ( optlc_net_1728 ) , .p1709 ( optlc_net_1729 ) ,
+ .p1710 ( optlc_net_1730 ) , .p1711 ( optlc_net_1731 ) ,
+ .p1712 ( optlc_net_1732 ) , .p1713 ( optlc_net_1733 ) ,
+ .p1714 ( optlc_net_1734 ) , .p1715 ( optlc_net_1735 ) ,
+ .p1716 ( optlc_net_1736 ) , .p1717 ( optlc_net_1737 ) ,
+ .p1718 ( optlc_net_1738 ) , .p1719 ( optlc_net_1739 ) ,
+ .p1720 ( optlc_net_1740 ) , .p1721 ( optlc_net_1741 ) ,
+ .p1722 ( optlc_net_1742 ) , .p1723 ( optlc_net_1743 ) ,
+ .p1724 ( optlc_net_1744 ) , .p1725 ( optlc_net_1745 ) ,
+ .p1726 ( optlc_net_1746 ) , .p1727 ( optlc_net_1747 ) ,
+ .p1728 ( optlc_net_1748 ) , .p1729 ( optlc_net_1749 ) ,
+ .p1730 ( optlc_net_1750 ) , .p1731 ( optlc_net_1751 ) ,
+ .p1732 ( optlc_net_1752 ) , .p1733 ( optlc_net_1753 ) ,
+ .p1734 ( optlc_net_1754 ) , .p1735 ( optlc_net_1755 ) ,
+ .p1736 ( optlc_net_1756 ) , .p1737 ( optlc_net_1757 ) ,
+ .p1738 ( optlc_net_1758 ) , .p1739 ( optlc_net_1759 ) ,
+ .p1740 ( optlc_net_1760 ) , .p1741 ( optlc_net_1761 ) ,
+ .p1742 ( optlc_net_1762 ) , .p1743 ( optlc_net_1763 ) ,
+ .p1744 ( optlc_net_1764 ) , .p1745 ( optlc_net_1765 ) ,
+ .p1746 ( optlc_net_1766 ) , .p1747 ( optlc_net_1767 ) ,
+ .p1748 ( optlc_net_1768 ) , .p1749 ( optlc_net_1769 ) ,
+ .p1750 ( optlc_net_1770 ) , .p1751 ( optlc_net_1771 ) ,
+ .p1752 ( optlc_net_1772 ) , .p1753 ( optlc_net_1773 ) ,
+ .p1754 ( optlc_net_1774 ) , .p1755 ( optlc_net_1775 ) ,
+ .p1756 ( optlc_net_1776 ) , .p1757 ( optlc_net_1777 ) ,
+ .p1758 ( optlc_net_1778 ) , .p1759 ( optlc_net_1779 ) ,
+ .p1760 ( optlc_net_1780 ) , .p1761 ( optlc_net_1781 ) ,
+ .p1762 ( optlc_net_1782 ) , .p1763 ( optlc_net_1783 ) ,
+ .p1764 ( optlc_net_1784 ) , .p1765 ( optlc_net_1785 ) ,
+ .p1766 ( optlc_net_1786 ) , .p1767 ( optlc_net_1787 ) ,
+ .p1768 ( optlc_net_1788 ) , .p1769 ( optlc_net_1789 ) ,
+ .p1770 ( optlc_net_1790 ) , .p1771 ( optlc_net_1791 ) ,
+ .p1772 ( optlc_net_1792 ) , .p1773 ( optlc_net_1793 ) ,
+ .p1774 ( optlc_net_1794 ) , .p1775 ( optlc_net_1795 ) ,
+ .p1776 ( optlc_net_1796 ) , .p1777 ( optlc_net_1797 ) ,
+ .p1778 ( optlc_net_1798 ) , .p1779 ( optlc_net_1799 ) ,
+ .p1780 ( optlc_net_1800 ) , .p1781 ( optlc_net_1801 ) ,
+ .p1782 ( optlc_net_1802 ) , .p1783 ( optlc_net_1803 ) ,
+ .p1784 ( optlc_net_1804 ) , .p1785 ( optlc_net_1805 ) ,
+ .p1786 ( optlc_net_1806 ) , .p1787 ( optlc_net_1807 ) ,
+ .p1788 ( optlc_net_1808 ) , .p1789 ( optlc_net_1809 ) ,
+ .p1790 ( optlc_net_1810 ) , .p1791 ( optlc_net_1811 ) ,
+ .p1792 ( optlc_net_1812 ) , .p1793 ( optlc_net_1813 ) ,
+ .p1794 ( optlc_net_1814 ) , .p1795 ( optlc_net_1815 ) ,
+ .p1796 ( optlc_net_1816 ) , .p1797 ( optlc_net_1817 ) ,
+ .p1798 ( optlc_net_1818 ) , .p1799 ( optlc_net_1819 ) ,
+ .p1800 ( optlc_net_1820 ) , .p1801 ( optlc_net_1821 ) ,
+ .p1802 ( optlc_net_1822 ) , .p1803 ( optlc_net_1823 ) ,
+ .p1804 ( optlc_net_1824 ) , .p1805 ( optlc_net_1825 ) ,
+ .p1806 ( optlc_net_1826 ) , .p1807 ( optlc_net_1827 ) ,
+ .p1808 ( optlc_net_1828 ) , .p1809 ( optlc_net_1829 ) ,
+ .p1810 ( optlc_net_1830 ) , .p1811 ( optlc_net_1831 ) ,
+ .p1812 ( optlc_net_1832 ) , .p1813 ( optlc_net_1833 ) ,
+ .p1814 ( optlc_net_1834 ) , .p1815 ( optlc_net_1835 ) ,
+ .p1816 ( optlc_net_1836 ) , .p1817 ( optlc_net_1837 ) ,
+ .p1818 ( optlc_net_1838 ) , .p1819 ( optlc_net_1839 ) ,
+ .p1820 ( optlc_net_1840 ) , .p1821 ( optlc_net_1841 ) ,
+ .p1822 ( optlc_net_1842 ) , .p1823 ( optlc_net_1843 ) ,
+ .p1824 ( optlc_net_1844 ) , .p1825 ( optlc_net_1845 ) ,
+ .p1826 ( optlc_net_1846 ) , .p1827 ( optlc_net_1847 ) ,
+ .p1828 ( optlc_net_1848 ) , .p1829 ( optlc_net_1849 ) ,
+ .p1830 ( optlc_net_1850 ) , .p1831 ( optlc_net_1851 ) ,
+ .p1832 ( optlc_net_1852 ) , .p1833 ( optlc_net_1853 ) ,
+ .p1834 ( optlc_net_1854 ) , .p1835 ( optlc_net_1855 ) ,
+ .p1836 ( optlc_net_1856 ) , .p1837 ( optlc_net_1857 ) ,
+ .p1838 ( optlc_net_1858 ) , .p1839 ( optlc_net_1859 ) ,
+ .p1840 ( optlc_net_1860 ) , .p1841 ( optlc_net_1861 ) ,
+ .p1842 ( optlc_net_1862 ) , .p1843 ( optlc_net_1863 ) ,
+ .p1844 ( optlc_net_1864 ) , .p1845 ( optlc_net_1865 ) ,
+ .p1846 ( optlc_net_1866 ) , .p1847 ( optlc_net_1867 ) ,
+ .p1848 ( optlc_net_1868 ) , .p1849 ( optlc_net_1869 ) ,
+ .p1850 ( optlc_net_1870 ) , .p1851 ( optlc_net_1871 ) ,
+ .p1852 ( optlc_net_1872 ) , .p1853 ( optlc_net_1873 ) ,
+ .p1854 ( optlc_net_1874 ) , .p1855 ( optlc_net_1875 ) ,
+ .p1856 ( optlc_net_1876 ) , .p1857 ( optlc_net_1877 ) ,
+ .p1858 ( optlc_net_1878 ) , .p1859 ( optlc_net_1879 ) ,
+ .p1860 ( optlc_net_1880 ) , .p1861 ( optlc_net_1881 ) ,
+ .p1862 ( optlc_net_1882 ) , .p1863 ( optlc_net_1883 ) ,
+ .p1864 ( optlc_net_1884 ) , .p1865 ( optlc_net_1885 ) ,
+ .p1866 ( optlc_net_1886 ) , .p1867 ( optlc_net_1887 ) ,
+ .p1868 ( optlc_net_1888 ) , .p1869 ( optlc_net_1889 ) ,
+ .p1870 ( optlc_net_1890 ) , .p1871 ( optlc_net_1891 ) ,
+ .p1872 ( optlc_net_1892 ) , .p1873 ( optlc_net_1893 ) ,
+ .p1874 ( optlc_net_1894 ) , .p1875 ( optlc_net_1895 ) ,
+ .p1876 ( optlc_net_1896 ) , .p1877 ( optlc_net_1897 ) ,
+ .p1878 ( optlc_net_1898 ) , .p1879 ( optlc_net_1899 ) ,
+ .p1880 ( optlc_net_1900 ) , .p1881 ( optlc_net_1901 ) ,
+ .p1882 ( optlc_net_1902 ) , .p1883 ( optlc_net_1903 ) ,
+ .p1884 ( optlc_net_1904 ) , .p1885 ( optlc_net_1905 ) ,
+ .p1886 ( optlc_net_1906 ) , .p1887 ( optlc_net_1907 ) ,
+ .p1888 ( optlc_net_1908 ) , .p1889 ( optlc_net_1909 ) ,
+ .p1890 ( optlc_net_1910 ) , .p1891 ( optlc_net_1911 ) ,
+ .p1892 ( optlc_net_1912 ) , .p1893 ( optlc_net_1913 ) ,
+ .p1894 ( optlc_net_1914 ) , .p1895 ( optlc_net_1915 ) ,
+ .p1896 ( optlc_net_1916 ) , .p1897 ( optlc_net_1917 ) ,
+ .p1898 ( optlc_net_1918 ) , .p1899 ( optlc_net_1919 ) ,
+ .p1900 ( optlc_net_1920 ) , .p1901 ( optlc_net_1921 ) ,
+ .p1902 ( optlc_net_1922 ) , .p1903 ( optlc_net_1923 ) ,
+ .p1904 ( optlc_net_1924 ) , .p1905 ( optlc_net_1925 ) ,
+ .p1906 ( optlc_net_1926 ) , .p1907 ( optlc_net_1927 ) ,
+ .p1908 ( optlc_net_1928 ) , .p1909 ( optlc_net_1929 ) ,
+ .p1910 ( optlc_net_1930 ) , .p1911 ( optlc_net_1931 ) ,
+ .p1912 ( optlc_net_1932 ) , .p1913 ( optlc_net_1933 ) ,
+ .p1914 ( optlc_net_1934 ) , .p1915 ( optlc_net_1935 ) ,
+ .p1916 ( optlc_net_1936 ) , .p1917 ( optlc_net_1937 ) ,
+ .p1918 ( optlc_net_1938 ) , .p1919 ( optlc_net_1939 ) ,
+ .p1920 ( optlc_net_1940 ) , .p1921 ( optlc_net_1941 ) ,
+ .p1922 ( optlc_net_1942 ) , .p1923 ( optlc_net_1943 ) ,
+ .p1924 ( optlc_net_1944 ) , .p1925 ( optlc_net_1945 ) ,
+ .p1926 ( optlc_net_1946 ) , .p1927 ( optlc_net_1947 ) ,
+ .p1928 ( optlc_net_1948 ) , .p1929 ( optlc_net_1949 ) ,
+ .p1930 ( optlc_net_1950 ) , .p1931 ( optlc_net_1951 ) ,
+ .p1932 ( optlc_net_1952 ) , .p1933 ( optlc_net_1953 ) ,
+ .p1934 ( optlc_net_1954 ) , .p1935 ( optlc_net_1955 ) ,
+ .p1936 ( optlc_net_1956 ) , .p1937 ( optlc_net_1957 ) ,
+ .p1938 ( optlc_net_1958 ) , .p1939 ( optlc_net_1959 ) ,
+ .p1940 ( optlc_net_1960 ) , .p1941 ( optlc_net_1961 ) ,
+ .p1942 ( optlc_net_1962 ) , .p1943 ( optlc_net_1963 ) ,
+ .p1944 ( optlc_net_1964 ) , .p1945 ( optlc_net_1965 ) ,
+ .p1946 ( optlc_net_1966 ) , .p1947 ( optlc_net_1967 ) ,
+ .p1948 ( optlc_net_1968 ) , .p1949 ( optlc_net_1969 ) ,
+ .p1950 ( optlc_net_1970 ) , .p1951 ( optlc_net_1971 ) ,
+ .p1952 ( optlc_net_1972 ) , .p1953 ( optlc_net_1973 ) ,
+ .p1954 ( optlc_net_1974 ) , .p1955 ( optlc_net_1975 ) ,
+ .p1956 ( optlc_net_1976 ) , .p1957 ( optlc_net_1977 ) ,
+ .p1958 ( optlc_net_1978 ) , .p1959 ( optlc_net_1979 ) ,
+ .p1960 ( optlc_net_1980 ) , .p1961 ( optlc_net_1981 ) ,
+ .p1962 ( optlc_net_1982 ) , .p1963 ( optlc_net_1983 ) ,
+ .p1964 ( optlc_net_1984 ) , .p1965 ( optlc_net_1985 ) ,
+ .p1966 ( optlc_net_1986 ) , .p1967 ( optlc_net_1987 ) ,
+ .p1968 ( optlc_net_1988 ) , .p1969 ( optlc_net_1989 ) ,
+ .p1970 ( optlc_net_1990 ) , .p1971 ( optlc_net_1991 ) ,
+ .p1972 ( optlc_net_1992 ) , .p1973 ( optlc_net_1993 ) ,
+ .p1974 ( optlc_net_1994 ) , .p1975 ( optlc_net_1995 ) ,
+ .p1976 ( optlc_net_1996 ) , .p1977 ( optlc_net_1997 ) ,
+ .p1978 ( optlc_net_1998 ) , .p1979 ( optlc_net_1999 ) ,
+ .p1980 ( optlc_net_2000 ) , .p1981 ( optlc_net_2001 ) ,
+ .p1982 ( optlc_net_2002 ) , .p1983 ( optlc_net_2003 ) ,
+ .p1984 ( optlc_net_2004 ) , .p1985 ( optlc_net_2005 ) ,
+ .p1986 ( optlc_net_2006 ) , .p1987 ( optlc_net_2007 ) ,
+ .p1988 ( optlc_net_2008 ) , .p1989 ( optlc_net_2009 ) ,
+ .p1990 ( optlc_net_2010 ) , .p1991 ( optlc_net_2011 ) ,
+ .p1992 ( optlc_net_2012 ) , .p1993 ( optlc_net_2013 ) ,
+ .p1994 ( optlc_net_2014 ) , .p1995 ( optlc_net_2015 ) ,
+ .p1996 ( optlc_net_2016 ) , .p1997 ( optlc_net_2017 ) ,
+ .p1998 ( optlc_net_2018 ) , .p1999 ( optlc_net_2019 ) ,
+ .p2000 ( optlc_net_2020 ) , .p2001 ( optlc_net_2021 ) ,
+ .p2002 ( optlc_net_2022 ) , .p2003 ( optlc_net_2023 ) ,
+ .p2004 ( optlc_net_2024 ) , .p2005 ( optlc_net_2025 ) ,
+ .p2006 ( optlc_net_2026 ) , .p2007 ( optlc_net_2027 ) ,
+ .p2008 ( optlc_net_2028 ) , .p2009 ( optlc_net_2029 ) ,
+ .p2010 ( optlc_net_2030 ) , .p2011 ( optlc_net_2031 ) ,
+ .p2012 ( optlc_net_2032 ) , .p2013 ( optlc_net_2033 ) ,
+ .p2014 ( optlc_net_2034 ) , .p2015 ( optlc_net_2035 ) ,
+ .p2016 ( optlc_net_2036 ) , .p2017 ( optlc_net_2037 ) ,
+ .p2018 ( optlc_net_2038 ) , .p2019 ( optlc_net_2039 ) ,
+ .p2020 ( optlc_net_2040 ) , .p2021 ( optlc_net_2041 ) ,
+ .p2022 ( optlc_net_2042 ) , .p2023 ( optlc_net_2043 ) ,
+ .p2024 ( optlc_net_2044 ) , .p2025 ( optlc_net_2045 ) ,
+ .p2026 ( optlc_net_2046 ) , .p2027 ( optlc_net_2047 ) ,
+ .p2028 ( optlc_net_2048 ) , .p2029 ( optlc_net_2049 ) ,
+ .p2030 ( optlc_net_2050 ) , .p2031 ( optlc_net_2051 ) ,
+ .p2032 ( optlc_net_2052 ) , .p2033 ( optlc_net_2053 ) ,
+ .p2034 ( optlc_net_2054 ) , .p2035 ( optlc_net_2055 ) ,
+ .p2036 ( optlc_net_2056 ) , .p2037 ( optlc_net_2057 ) ,
+ .p2038 ( optlc_net_2058 ) , .p2039 ( optlc_net_2059 ) ,
+ .p2040 ( optlc_net_2060 ) , .p2041 ( optlc_net_2061 ) ,
+ .p2042 ( optlc_net_2062 ) , .p2043 ( optlc_net_2063 ) ,
+ .p2044 ( optlc_net_2064 ) , .p2045 ( optlc_net_2065 ) ,
+ .p2046 ( optlc_net_2066 ) , .p2047 ( optlc_net_2067 ) ,
+ .p2048 ( optlc_net_2068 ) , .p2049 ( optlc_net_2069 ) ,
+ .p2050 ( optlc_net_2070 ) , .p2051 ( optlc_net_2071 ) ,
+ .p2052 ( optlc_net_2072 ) , .p2053 ( optlc_net_2073 ) ,
+ .p2054 ( optlc_net_2074 ) , .p2055 ( optlc_net_2075 ) ,
+ .p2056 ( optlc_net_2076 ) , .p2057 ( optlc_net_2077 ) ,
+ .p2058 ( optlc_net_2078 ) , .p2059 ( optlc_net_2079 ) ,
+ .p2060 ( optlc_net_2080 ) , .p2061 ( optlc_net_2081 ) ,
+ .p2062 ( optlc_net_2082 ) , .p2063 ( optlc_net_2083 ) ,
+ .p2064 ( optlc_net_2084 ) , .p2065 ( optlc_net_2085 ) ,
+ .p2066 ( optlc_net_2086 ) , .p2067 ( optlc_net_2087 ) ,
+ .p2068 ( optlc_net_2088 ) , .p2069 ( optlc_net_2089 ) ,
+ .p2070 ( optlc_net_2090 ) , .p2071 ( optlc_net_2091 ) ,
+ .p2072 ( optlc_net_2092 ) , .p2073 ( optlc_net_2093 ) ,
+ .p2074 ( optlc_net_2094 ) , .p2075 ( optlc_net_2095 ) ,
+ .p2076 ( optlc_net_2096 ) , .p2077 ( optlc_net_2097 ) ,
+ .p2078 ( optlc_net_2098 ) , .p2079 ( optlc_net_2099 ) ,
+ .p2080 ( optlc_net_2100 ) , .p2081 ( optlc_net_2101 ) ,
+ .p2082 ( optlc_net_2102 ) , .p2083 ( optlc_net_2103 ) ,
+ .p2084 ( optlc_net_2104 ) , .p2085 ( optlc_net_2105 ) ,
+ .p2086 ( optlc_net_2106 ) , .p2087 ( optlc_net_2107 ) ,
+ .p2088 ( optlc_net_2108 ) , .p2089 ( optlc_net_2109 ) ,
+ .p2090 ( optlc_net_2110 ) , .p2091 ( optlc_net_2111 ) ,
+ .p2092 ( optlc_net_2112 ) , .p2093 ( optlc_net_2113 ) ,
+ .p2094 ( optlc_net_2114 ) , .p2095 ( optlc_net_2115 ) ,
+ .p2096 ( optlc_net_2116 ) , .p2097 ( optlc_net_2117 ) ,
+ .p2098 ( optlc_net_2118 ) , .p2099 ( optlc_net_2119 ) ,
+ .p2100 ( optlc_net_2120 ) , .p2101 ( optlc_net_2121 ) ,
+ .p2102 ( optlc_net_2122 ) , .p2103 ( optlc_net_2123 ) ,
+ .p2104 ( optlc_net_2124 ) , .p2105 ( optlc_net_2125 ) ,
+ .p2106 ( optlc_net_2126 ) , .p2107 ( optlc_net_2127 ) ,
+ .p2108 ( optlc_net_2128 ) , .p2109 ( optlc_net_2129 ) ,
+ .p2110 ( optlc_net_2130 ) , .p2111 ( optlc_net_2131 ) ,
+ .p2112 ( optlc_net_2132 ) , .p2113 ( optlc_net_2133 ) ,
+ .p2114 ( optlc_net_2134 ) , .p2115 ( optlc_net_2135 ) ,
+ .p2116 ( optlc_net_2136 ) , .p2117 ( optlc_net_2137 ) ,
+ .p2118 ( optlc_net_2138 ) , .p2119 ( optlc_net_2139 ) ,
+ .p2120 ( optlc_net_2140 ) , .p2121 ( optlc_net_2141 ) ,
+ .p2122 ( optlc_net_2142 ) , .p2123 ( optlc_net_2143 ) ,
+ .p2124 ( optlc_net_2144 ) , .p2125 ( optlc_net_2145 ) ,
+ .p2126 ( optlc_net_2146 ) , .p2127 ( optlc_net_2147 ) ,
+ .p2128 ( optlc_net_2148 ) , .p2129 ( optlc_net_2149 ) ,
+ .p2130 ( optlc_net_2150 ) , .p2131 ( optlc_net_2151 ) ,
+ .p2132 ( optlc_net_2152 ) , .p2133 ( optlc_net_2153 ) ,
+ .p2134 ( optlc_net_2154 ) , .p2135 ( optlc_net_2155 ) ,
+ .p2136 ( optlc_net_2156 ) , .p2137 ( optlc_net_2157 ) ,
+ .p2138 ( optlc_net_2158 ) , .p2139 ( optlc_net_2159 ) ,
+ .p2140 ( optlc_net_2160 ) , .p2141 ( optlc_net_2161 ) ,
+ .p2142 ( optlc_net_2162 ) , .p2143 ( optlc_net_2163 ) ,
+ .p2144 ( optlc_net_2164 ) , .p2145 ( optlc_net_2165 ) ,
+ .p2146 ( optlc_net_2166 ) , .p2147 ( optlc_net_2167 ) ,
+ .p2148 ( optlc_net_2168 ) , .p2149 ( optlc_net_2169 ) ,
+ .p2150 ( optlc_net_2170 ) , .p2151 ( optlc_net_2171 ) ,
+ .p2152 ( optlc_net_2172 ) , .p2153 ( optlc_net_2173 ) ,
+ .p2154 ( optlc_net_2174 ) , .p2155 ( optlc_net_2175 ) ,
+ .p2156 ( optlc_net_2176 ) , .p2157 ( optlc_net_2177 ) ,
+ .p2158 ( optlc_net_2178 ) , .p2159 ( optlc_net_2179 ) ,
+ .p2160 ( optlc_net_2180 ) , .p2161 ( optlc_net_2181 ) ,
+ .p2162 ( optlc_net_2182 ) , .p2163 ( optlc_net_2183 ) ,
+ .p2164 ( optlc_net_2184 ) , .p2165 ( optlc_net_2185 ) ,
+ .p2166 ( optlc_net_2186 ) , .p2167 ( optlc_net_2187 ) ,
+ .p2168 ( optlc_net_2188 ) , .p2169 ( optlc_net_2189 ) ,
+ .p2170 ( optlc_net_2190 ) , .p2171 ( optlc_net_2191 ) ,
+ .p2172 ( optlc_net_2192 ) , .p2173 ( optlc_net_2193 ) ,
+ .p2174 ( optlc_net_2194 ) , .p2175 ( optlc_net_2195 ) ,
+ .p2176 ( optlc_net_2196 ) , .p2177 ( optlc_net_2197 ) ,
+ .p2178 ( optlc_net_2198 ) , .p2179 ( optlc_net_2199 ) ,
+ .p2180 ( optlc_net_2200 ) , .p2181 ( optlc_net_2201 ) ,
+ .p2182 ( optlc_net_2202 ) , .p2183 ( optlc_net_2203 ) ,
+ .p2184 ( optlc_net_2204 ) , .p2185 ( optlc_net_2205 ) ,
+ .p2186 ( optlc_net_2206 ) , .p2187 ( optlc_net_2207 ) ,
+ .p2188 ( optlc_net_2208 ) , .p2189 ( optlc_net_2209 ) ,
+ .p2190 ( optlc_net_2210 ) , .p2191 ( optlc_net_2211 ) ,
+ .p2192 ( optlc_net_2212 ) , .p2193 ( optlc_net_2213 ) ,
+ .p2194 ( optlc_net_2214 ) , .p2195 ( optlc_net_2215 ) ,
+ .p2196 ( optlc_net_2216 ) , .p2197 ( optlc_net_2217 ) ,
+ .p2198 ( optlc_net_2218 ) , .p2199 ( optlc_net_2219 ) ,
+ .p2200 ( optlc_net_2220 ) , .p2201 ( optlc_net_2221 ) ,
+ .p2202 ( optlc_net_2222 ) , .p2203 ( optlc_net_2223 ) ,
+ .p2204 ( optlc_net_2224 ) , .p2205 ( optlc_net_2225 ) ,
+ .p2206 ( optlc_net_2226 ) , .p2207 ( optlc_net_2227 ) ,
+ .p2208 ( optlc_net_2228 ) , .p2209 ( optlc_net_2229 ) ,
+ .p2210 ( optlc_net_2230 ) , .p2211 ( optlc_net_2231 ) ,
+ .p2212 ( optlc_net_2232 ) , .p2213 ( optlc_net_2233 ) ,
+ .p2214 ( optlc_net_2234 ) , .p2215 ( optlc_net_2235 ) ,
+ .p2216 ( optlc_net_2236 ) , .p2217 ( optlc_net_2237 ) ,
+ .p2218 ( optlc_net_2238 ) , .p2219 ( optlc_net_2239 ) ,
+ .p2220 ( optlc_net_2240 ) , .p2221 ( optlc_net_2241 ) ,
+ .p2222 ( optlc_net_2242 ) , .p2223 ( optlc_net_2243 ) ,
+ .p2224 ( optlc_net_2244 ) , .p2225 ( optlc_net_2245 ) ,
+ .p2226 ( optlc_net_2246 ) , .p2227 ( optlc_net_2247 ) ,
+ .p2228 ( optlc_net_2248 ) , .p2229 ( optlc_net_2249 ) ,
+ .p2230 ( optlc_net_2250 ) , .p2231 ( optlc_net_2251 ) ,
+ .p2232 ( optlc_net_2252 ) , .p2233 ( optlc_net_2253 ) ,
+ .p2234 ( optlc_net_2254 ) , .p2235 ( optlc_net_2255 ) ,
+ .p2236 ( optlc_net_2256 ) , .p2237 ( optlc_net_2257 ) ,
+ .p2238 ( optlc_net_2258 ) , .p2239 ( optlc_net_2259 ) ,
+ .p2240 ( optlc_net_2260 ) , .p2241 ( optlc_net_2261 ) ,
+ .p2242 ( optlc_net_2262 ) , .p2243 ( optlc_net_2263 ) ,
+ .p2244 ( optlc_net_2264 ) , .p2245 ( optlc_net_2265 ) ,
+ .p2246 ( optlc_net_2266 ) , .p2247 ( optlc_net_2267 ) ,
+ .p2248 ( optlc_net_2268 ) , .p2249 ( optlc_net_2269 ) ,
+ .p2250 ( optlc_net_2270 ) , .p2251 ( optlc_net_2271 ) ,
+ .p2252 ( optlc_net_2272 ) , .p2253 ( optlc_net_2273 ) ,
+ .p2254 ( optlc_net_2274 ) , .p2255 ( optlc_net_2275 ) ,
+ .p2256 ( optlc_net_2276 ) , .p2257 ( optlc_net_2277 ) ,
+ .p2258 ( optlc_net_2278 ) , .p2259 ( optlc_net_2279 ) ,
+ .p2260 ( optlc_net_2280 ) , .p2261 ( optlc_net_2281 ) ,
+ .p2262 ( optlc_net_2282 ) , .p2263 ( optlc_net_2283 ) ,
+ .p2264 ( optlc_net_2284 ) , .p2265 ( optlc_net_2285 ) ,
+ .p2266 ( optlc_net_2286 ) , .p2267 ( optlc_net_2287 ) ,
+ .p2268 ( optlc_net_2288 ) , .p2269 ( optlc_net_2289 ) ,
+ .p2270 ( optlc_net_2290 ) , .p2271 ( optlc_net_2291 ) ,
+ .p2272 ( optlc_net_2292 ) , .p2273 ( optlc_net_2293 ) ,
+ .p2274 ( optlc_net_2294 ) , .p2275 ( optlc_net_2295 ) ,
+ .p2276 ( optlc_net_2296 ) , .p2277 ( optlc_net_2297 ) ,
+ .p2278 ( optlc_net_2298 ) , .p2279 ( optlc_net_2299 ) ,
+ .p2280 ( optlc_net_2300 ) , .p2281 ( optlc_net_2301 ) ,
+ .p2282 ( optlc_net_2302 ) , .p2283 ( optlc_net_2303 ) ,
+ .p2284 ( optlc_net_2304 ) , .p2285 ( optlc_net_2305 ) ,
+ .p2286 ( optlc_net_2306 ) , .p2287 ( optlc_net_2307 ) ,
+ .p2288 ( optlc_net_2308 ) , .p2289 ( optlc_net_2309 ) ,
+ .p2290 ( optlc_net_2310 ) , .p2291 ( optlc_net_2311 ) ,
+ .p2292 ( optlc_net_2312 ) , .p2293 ( optlc_net_2313 ) ,
+ .p2294 ( optlc_net_2314 ) , .p2295 ( optlc_net_2315 ) ,
+ .p2296 ( optlc_net_2316 ) , .p2297 ( optlc_net_2317 ) ,
+ .p2298 ( optlc_net_2318 ) , .p2299 ( optlc_net_2319 ) ,
+ .p2300 ( optlc_net_2320 ) , .p2301 ( optlc_net_2321 ) ,
+ .p2302 ( optlc_net_2322 ) , .p2303 ( optlc_net_2323 ) ,
+ .p2304 ( optlc_net_2324 ) , .p2305 ( optlc_net_2325 ) ,
+ .p2306 ( optlc_net_2326 ) , .p2307 ( optlc_net_2327 ) ,
+ .p2308 ( optlc_net_2328 ) , .p2309 ( optlc_net_2329 ) ,
+ .p2310 ( optlc_net_2330 ) , .p2311 ( optlc_net_2331 ) ,
+ .p2312 ( optlc_net_2332 ) , .p2313 ( optlc_net_2333 ) ,
+ .p2314 ( optlc_net_2334 ) , .p2315 ( optlc_net_2335 ) ,
+ .p2316 ( optlc_net_2336 ) , .p2317 ( optlc_net_2337 ) ,
+ .p2318 ( optlc_net_2338 ) , .p2319 ( optlc_net_2339 ) ,
+ .p2320 ( optlc_net_2340 ) , .p2321 ( optlc_net_2341 ) ,
+ .p2322 ( optlc_net_2342 ) , .p2323 ( optlc_net_2343 ) ,
+ .p2324 ( optlc_net_2344 ) , .p2325 ( optlc_net_2345 ) ,
+ .p2326 ( optlc_net_2346 ) , .p2327 ( optlc_net_2347 ) ,
+ .p2328 ( optlc_net_2348 ) , .p2329 ( optlc_net_2349 ) ,
+ .p2330 ( optlc_net_2350 ) , .p2331 ( optlc_net_2351 ) ,
+ .p2332 ( optlc_net_2352 ) , .p2333 ( optlc_net_2353 ) ,
+ .p2334 ( optlc_net_2354 ) , .p2335 ( optlc_net_2355 ) ,
+ .p2336 ( optlc_net_2356 ) , .p2337 ( optlc_net_2357 ) ,
+ .p2338 ( optlc_net_2358 ) , .p2339 ( optlc_net_2359 ) ,
+ .p2340 ( optlc_net_2360 ) , .p2341 ( optlc_net_2361 ) ,
+ .p2342 ( optlc_net_2362 ) , .p2343 ( optlc_net_2363 ) ,
+ .p2344 ( optlc_net_2364 ) , .p2345 ( optlc_net_2365 ) ,
+ .p2346 ( optlc_net_2366 ) , .p2347 ( optlc_net_2367 ) ,
+ .p2348 ( optlc_net_2368 ) , .p2349 ( optlc_net_2369 ) ,
+ .p2350 ( optlc_net_2370 ) , .p2351 ( optlc_net_2371 ) ,
+ .p2352 ( optlc_net_2372 ) , .p2353 ( optlc_net_2373 ) ,
+ .p2354 ( optlc_net_2374 ) , .p2355 ( optlc_net_2375 ) ,
+ .p2356 ( optlc_net_2376 ) , .p2357 ( optlc_net_2377 ) ,
+ .p2358 ( optlc_net_2378 ) , .p2359 ( optlc_net_2379 ) ,
+ .p2360 ( optlc_net_2380 ) , .p2361 ( optlc_net_2381 ) ,
+ .p2362 ( optlc_net_2382 ) , .p2363 ( optlc_net_2383 ) ,
+ .p2364 ( optlc_net_2384 ) , .p2365 ( optlc_net_2385 ) ,
+ .p2366 ( optlc_net_2386 ) , .p2367 ( optlc_net_2387 ) ,
+ .p2368 ( optlc_net_2388 ) , .p2369 ( optlc_net_2389 ) ,
+ .p2370 ( optlc_net_2390 ) , .p2371 ( optlc_net_2391 ) ,
+ .p2372 ( optlc_net_2392 ) , .p2373 ( optlc_net_2393 ) ,
+ .p2374 ( optlc_net_2394 ) , .p2375 ( optlc_net_2395 ) ,
+ .p2376 ( optlc_net_2396 ) , .p2377 ( optlc_net_2397 ) ,
+ .p2378 ( optlc_net_2398 ) , .p2379 ( optlc_net_2399 ) ,
+ .p2380 ( optlc_net_2400 ) , .p2381 ( optlc_net_2401 ) ,
+ .p2382 ( optlc_net_2402 ) , .p2383 ( optlc_net_2403 ) ,
+ .p2384 ( optlc_net_2404 ) , .p2385 ( optlc_net_2405 ) ,
+ .p2386 ( optlc_net_2406 ) , .p2387 ( optlc_net_2407 ) ,
+ .p2388 ( optlc_net_2408 ) , .p2389 ( optlc_net_2409 ) ,
+ .p2390 ( optlc_net_2410 ) , .p2391 ( optlc_net_2411 ) ,
+ .p2392 ( optlc_net_2412 ) , .p2393 ( optlc_net_2413 ) ,
+ .p2394 ( optlc_net_2414 ) , .p2395 ( optlc_net_2415 ) ,
+ .p2396 ( optlc_net_2416 ) , .p2397 ( optlc_net_2417 ) ,
+ .p2398 ( optlc_net_2418 ) , .p2399 ( optlc_net_2419 ) ,
+ .p2400 ( optlc_net_2420 ) , .p2401 ( optlc_net_2421 ) ,
+ .p2402 ( optlc_net_2422 ) , .p2403 ( optlc_net_2423 ) ,
+ .p2404 ( optlc_net_2424 ) , .p2405 ( optlc_net_2425 ) ,
+ .p2406 ( optlc_net_2426 ) , .p2407 ( optlc_net_2427 ) ,
+ .p2408 ( optlc_net_2428 ) , .p2409 ( optlc_net_2429 ) ,
+ .p2410 ( optlc_net_2430 ) , .p2411 ( optlc_net_2431 ) ,
+ .p2412 ( optlc_net_2432 ) , .p2413 ( optlc_net_2433 ) ,
+ .p2414 ( optlc_net_2434 ) , .p2415 ( optlc_net_2435 ) ,
+ .p2416 ( optlc_net_2436 ) , .p2417 ( optlc_net_2437 ) ,
+ .p2418 ( optlc_net_2438 ) , .p2419 ( optlc_net_2439 ) ,
+ .p2420 ( optlc_net_2440 ) , .p2421 ( optlc_net_2441 ) ,
+ .p2422 ( optlc_net_2442 ) , .p2423 ( optlc_net_2443 ) ,
+ .p2424 ( optlc_net_2444 ) , .p2425 ( optlc_net_2445 ) ,
+ .p2426 ( optlc_net_2446 ) , .p2427 ( optlc_net_2447 ) ,
+ .p2428 ( optlc_net_2448 ) , .p2429 ( optlc_net_2449 ) ,
+ .p2430 ( optlc_net_2450 ) , .p2431 ( optlc_net_2451 ) ,
+ .p2432 ( optlc_net_2452 ) , .p2433 ( optlc_net_2453 ) ,
+ .p2434 ( optlc_net_2454 ) , .p2435 ( optlc_net_2455 ) ,
+ .p2436 ( optlc_net_2456 ) , .p2437 ( optlc_net_2457 ) ,
+ .p2438 ( optlc_net_2458 ) , .p2439 ( optlc_net_2459 ) ,
+ .p2440 ( optlc_net_2460 ) , .p2441 ( optlc_net_2461 ) ,
+ .p2442 ( optlc_net_2462 ) , .p2443 ( optlc_net_2463 ) ,
+ .p2444 ( optlc_net_2464 ) , .p2445 ( optlc_net_2465 ) ,
+ .p2446 ( optlc_net_2466 ) , .p2447 ( optlc_net_2467 ) ,
+ .p2448 ( optlc_net_2468 ) , .p2449 ( optlc_net_2469 ) ,
+ .p2450 ( optlc_net_2470 ) , .p2451 ( optlc_net_2471 ) ,
+ .p2452 ( optlc_net_2472 ) , .p2453 ( optlc_net_2473 ) ,
+ .p2454 ( optlc_net_2474 ) , .p2455 ( optlc_net_2475 ) ,
+ .p2456 ( optlc_net_2476 ) , .p2457 ( optlc_net_2477 ) ,
+ .p2458 ( optlc_net_2478 ) , .p2459 ( optlc_net_2479 ) ,
+ .p2460 ( optlc_net_2480 ) , .p2461 ( optlc_net_2481 ) ,
+ .p2462 ( optlc_net_2482 ) , .p2463 ( optlc_net_2483 ) ,
+ .p2464 ( optlc_net_2484 ) , .p2465 ( optlc_net_2485 ) ,
+ .p2466 ( optlc_net_2486 ) , .p2467 ( optlc_net_2487 ) ,
+ .p2468 ( optlc_net_2488 ) , .p2469 ( optlc_net_2489 ) ,
+ .p2470 ( optlc_net_2490 ) , .p2471 ( optlc_net_2491 ) ,
+ .p2472 ( optlc_net_2492 ) , .p2473 ( optlc_net_2493 ) ,
+ .p2474 ( optlc_net_2494 ) , .p2475 ( optlc_net_2495 ) ,
+ .p2476 ( optlc_net_2496 ) , .p2477 ( optlc_net_2497 ) ,
+ .p2478 ( optlc_net_2498 ) , .p2479 ( optlc_net_2499 ) ,
+ .p2480 ( optlc_net_2500 ) , .p2481 ( optlc_net_2501 ) ,
+ .p2482 ( optlc_net_2502 ) , .p2483 ( optlc_net_2503 ) ,
+ .p2484 ( optlc_net_2504 ) , .p2485 ( optlc_net_2505 ) ,
+ .p2486 ( optlc_net_2506 ) , .p2487 ( optlc_net_2507 ) ,
+ .p2488 ( optlc_net_2508 ) , .p2489 ( optlc_net_2509 ) ,
+ .p2490 ( optlc_net_2510 ) , .p2491 ( optlc_net_2511 ) ,
+ .p2492 ( optlc_net_2512 ) , .p2493 ( optlc_net_2513 ) ,
+ .p2494 ( optlc_net_2514 ) , .p2495 ( optlc_net_2515 ) ,
+ .p2496 ( optlc_net_2516 ) , .p2497 ( optlc_net_2517 ) ,
+ .p2498 ( optlc_net_2518 ) , .p2499 ( optlc_net_2519 ) ,
+ .p2500 ( optlc_net_2520 ) , .p2501 ( optlc_net_2521 ) ,
+ .p2502 ( optlc_net_2522 ) , .p2503 ( optlc_net_2523 ) ,
+ .p2504 ( optlc_net_2524 ) , .p2505 ( optlc_net_2525 ) ,
+ .p2506 ( optlc_net_2526 ) , .p2507 ( optlc_net_2527 ) ,
+ .p2508 ( optlc_net_2528 ) , .p2509 ( optlc_net_2529 ) ,
+ .p2510 ( optlc_net_2530 ) , .p2511 ( optlc_net_2531 ) ,
+ .p2512 ( optlc_net_2532 ) , .p2513 ( optlc_net_2533 ) ,
+ .p2514 ( optlc_net_2534 ) , .p2515 ( optlc_net_2535 ) ,
+ .p2516 ( optlc_net_2536 ) , .p2517 ( optlc_net_2537 ) ,
+ .p2518 ( optlc_net_2538 ) , .p2519 ( optlc_net_2539 ) ,
+ .p2520 ( optlc_net_2540 ) , .p2521 ( optlc_net_2541 ) ,
+ .p2522 ( optlc_net_2542 ) , .p2523 ( optlc_net_2543 ) ,
+ .p2524 ( optlc_net_2544 ) , .p2525 ( optlc_net_2545 ) ,
+ .p2526 ( optlc_net_2546 ) , .p2527 ( optlc_net_2547 ) ,
+ .p2528 ( optlc_net_2548 ) , .p2529 ( optlc_net_2549 ) ,
+ .p2530 ( optlc_net_2550 ) , .p2531 ( optlc_net_2551 ) ,
+ .p2532 ( optlc_net_2552 ) , .p2533 ( optlc_net_2553 ) ,
+ .p2534 ( optlc_net_2554 ) , .p2535 ( optlc_net_2555 ) ,
+ .p2536 ( optlc_net_2556 ) , .p2537 ( optlc_net_2557 ) ,
+ .p2538 ( optlc_net_2558 ) , .p2539 ( optlc_net_2559 ) ,
+ .p2540 ( optlc_net_2560 ) , .p2541 ( optlc_net_2561 ) ,
+ .p2542 ( optlc_net_2562 ) , .p2543 ( optlc_net_2563 ) ,
+ .p2544 ( optlc_net_2564 ) , .p2545 ( optlc_net_2565 ) ,
+ .p2546 ( optlc_net_2566 ) , .p2547 ( optlc_net_2567 ) ,
+ .p2548 ( optlc_net_2568 ) , .p2549 ( optlc_net_2569 ) ,
+ .p2550 ( optlc_net_2570 ) , .p2551 ( optlc_net_2571 ) ,
+ .p2552 ( optlc_net_2572 ) , .p2553 ( optlc_net_2573 ) ,
+ .p2554 ( optlc_net_2574 ) , .p2555 ( optlc_net_2575 ) ,
+ .p2556 ( optlc_net_2576 ) , .p2557 ( optlc_net_2577 ) ,
+ .p2558 ( optlc_net_2578 ) , .p2559 ( optlc_net_2579 ) ,
+ .p2560 ( optlc_net_2580 ) , .p2561 ( optlc_net_2581 ) ,
+ .p2562 ( optlc_net_2582 ) , .p2563 ( optlc_net_2583 ) ,
+ .p2564 ( optlc_net_2584 ) , .p2565 ( optlc_net_2585 ) ,
+ .p2566 ( optlc_net_2586 ) , .p2567 ( optlc_net_2587 ) ,
+ .p2568 ( optlc_net_2588 ) , .p2569 ( optlc_net_2589 ) ,
+ .p2570 ( optlc_net_2590 ) , .p2571 ( optlc_net_2591 ) ,
+ .p2572 ( optlc_net_2592 ) , .p2573 ( optlc_net_2593 ) ,
+ .p2574 ( optlc_net_2594 ) , .p2575 ( optlc_net_2595 ) ,
+ .p2576 ( optlc_net_2596 ) , .p2577 ( optlc_net_2597 ) ,
+ .p2578 ( optlc_net_2598 ) , .p2579 ( optlc_net_2599 ) ,
+ .p2580 ( optlc_net_2600 ) , .p2581 ( optlc_net_2601 ) ,
+ .p2582 ( optlc_net_2602 ) , .p2583 ( optlc_net_2603 ) ,
+ .p2584 ( optlc_net_2604 ) , .p2585 ( optlc_net_2605 ) ,
+ .p2586 ( optlc_net_2606 ) , .p2587 ( optlc_net_2607 ) ,
+ .p2588 ( optlc_net_2608 ) , .p2589 ( optlc_net_2609 ) ,
+ .p2590 ( optlc_net_2610 ) , .p2591 ( optlc_net_2611 ) ,
+ .p2592 ( optlc_net_2612 ) , .p2593 ( optlc_net_2613 ) ,
+ .p2594 ( optlc_net_2614 ) , .p2595 ( optlc_net_2615 ) ,
+ .p2596 ( optlc_net_2616 ) , .p2597 ( optlc_net_2617 ) ,
+ .p2598 ( optlc_net_2618 ) , .p2599 ( optlc_net_2619 ) ,
+ .p2600 ( optlc_net_2620 ) , .p2601 ( optlc_net_2621 ) ,
+ .p2602 ( optlc_net_2622 ) , .p2603 ( optlc_net_2623 ) ,
+ .p2604 ( optlc_net_2624 ) , .p2605 ( optlc_net_2625 ) ,
+ .p2606 ( optlc_net_2626 ) , .p2607 ( optlc_net_2627 ) ,
+ .p2608 ( optlc_net_2628 ) , .p2609 ( optlc_net_2629 ) ,
+ .p2610 ( optlc_net_2630 ) , .p2611 ( optlc_net_2631 ) ,
+ .p2612 ( optlc_net_2632 ) , .p2613 ( optlc_net_2633 ) ,
+ .p2614 ( optlc_net_2634 ) , .p2615 ( optlc_net_2635 ) ,
+ .p2616 ( optlc_net_2636 ) , .p2617 ( optlc_net_2637 ) ,
+ .p2618 ( optlc_net_2638 ) , .p2619 ( optlc_net_2639 ) ,
+ .p2620 ( optlc_net_2640 ) , .p2621 ( optlc_net_2641 ) ,
+ .p2622 ( optlc_net_2642 ) , .p2623 ( optlc_net_2643 ) ,
+ .p2624 ( optlc_net_2644 ) , .p2625 ( optlc_net_2645 ) ,
+ .p2626 ( optlc_net_2646 ) , .p2627 ( optlc_net_2647 ) ,
+ .p2628 ( optlc_net_2648 ) , .p2629 ( optlc_net_2649 ) ,
+ .p2630 ( optlc_net_2650 ) , .p2631 ( optlc_net_2651 ) ,
+ .p2632 ( optlc_net_2652 ) , .p2633 ( optlc_net_2653 ) ,
+ .p2634 ( optlc_net_2654 ) , .p2635 ( optlc_net_2655 ) ,
+ .p2636 ( optlc_net_2656 ) , .p2637 ( optlc_net_2657 ) ,
+ .p2638 ( optlc_net_2658 ) , .p2639 ( optlc_net_2659 ) ,
+ .p2640 ( optlc_net_2660 ) , .p2641 ( optlc_net_2661 ) ,
+ .p2642 ( optlc_net_2662 ) , .p2643 ( optlc_net_2663 ) ,
+ .p2644 ( optlc_net_2664 ) , .p2645 ( optlc_net_2665 ) ,
+ .p2646 ( optlc_net_2666 ) , .p2647 ( optlc_net_2667 ) ,
+ .p2648 ( optlc_net_2668 ) , .p2649 ( optlc_net_2669 ) ,
+ .p2650 ( optlc_net_2670 ) , .p2651 ( optlc_net_2671 ) ,
+ .p2652 ( optlc_net_2672 ) , .p2653 ( optlc_net_2673 ) ,
+ .p2654 ( optlc_net_2674 ) , .p2655 ( optlc_net_2675 ) ,
+ .p2656 ( optlc_net_2676 ) , .p2657 ( optlc_net_2677 ) ,
+ .p2658 ( optlc_net_2678 ) , .p2659 ( optlc_net_2679 ) ,
+ .p2660 ( optlc_net_2680 ) , .p2661 ( optlc_net_2681 ) ,
+ .p2662 ( optlc_net_2682 ) , .p2663 ( optlc_net_2683 ) ,
+ .p2664 ( optlc_net_2684 ) , .p2665 ( optlc_net_2685 ) ,
+ .p2666 ( optlc_net_2686 ) , .p2667 ( optlc_net_2687 ) ,
+ .p2668 ( optlc_net_2688 ) , .p2669 ( optlc_net_2689 ) ,
+ .p2670 ( optlc_net_2690 ) , .p2671 ( optlc_net_2691 ) ,
+ .p2672 ( optlc_net_2692 ) , .p2673 ( optlc_net_2693 ) ,
+ .p2674 ( optlc_net_2694 ) , .p2675 ( optlc_net_2695 ) ,
+ .p2676 ( optlc_net_2696 ) , .p2677 ( optlc_net_2697 ) ,
+ .p2678 ( optlc_net_2698 ) , .p2679 ( optlc_net_2699 ) ,
+ .p2680 ( optlc_net_2700 ) , .p2681 ( optlc_net_2701 ) ,
+ .p2682 ( optlc_net_2702 ) , .p2683 ( optlc_net_2703 ) ,
+ .p2684 ( optlc_net_2704 ) , .p2685 ( optlc_net_2705 ) ,
+ .p2686 ( optlc_net_2706 ) , .p2687 ( optlc_net_2707 ) ,
+ .p2688 ( optlc_net_2708 ) , .p2689 ( optlc_net_2709 ) ,
+ .p2690 ( optlc_net_2710 ) , .p2691 ( optlc_net_2711 ) ,
+ .p2692 ( optlc_net_2712 ) , .p2693 ( optlc_net_2713 ) ,
+ .p2694 ( optlc_net_2714 ) , .p2695 ( optlc_net_2715 ) ,
+ .p2696 ( optlc_net_2716 ) , .p2697 ( optlc_net_2717 ) ,
+ .p2698 ( optlc_net_2718 ) , .p2699 ( optlc_net_2719 ) ,
+ .p2700 ( optlc_net_2720 ) , .p2701 ( optlc_net_2721 ) ,
+ .p2702 ( optlc_net_2722 ) , .p2703 ( optlc_net_2723 ) ,
+ .p2704 ( optlc_net_2724 ) , .p2705 ( optlc_net_2725 ) ,
+ .p2706 ( optlc_net_2726 ) , .p2707 ( optlc_net_2727 ) ,
+ .p2708 ( optlc_net_2728 ) , .p2709 ( optlc_net_2729 ) ,
+ .p2710 ( optlc_net_2730 ) , .p2711 ( optlc_net_2731 ) ,
+ .p2712 ( optlc_net_2732 ) , .p2713 ( optlc_net_2733 ) ,
+ .p2714 ( optlc_net_2734 ) , .p2715 ( optlc_net_2735 ) ,
+ .p2716 ( optlc_net_2736 ) , .p2717 ( optlc_net_2737 ) ,
+ .p2718 ( optlc_net_2738 ) , .p2719 ( optlc_net_2739 ) ,
+ .p2720 ( optlc_net_2740 ) , .p2721 ( optlc_net_2741 ) ,
+ .p2722 ( optlc_net_2742 ) , .p2723 ( optlc_net_2743 ) ,
+ .p2724 ( optlc_net_2744 ) , .p2725 ( optlc_net_2745 ) ,
+ .p2726 ( optlc_net_2746 ) , .p2727 ( optlc_net_2747 ) ,
+ .p2728 ( optlc_net_2748 ) , .p2729 ( optlc_net_2749 ) ,
+ .p2730 ( optlc_net_2750 ) , .p2731 ( optlc_net_2751 ) ,
+ .p2732 ( optlc_net_2752 ) , .p2733 ( optlc_net_2753 ) ,
+ .p2734 ( optlc_net_2754 ) , .p2735 ( optlc_net_2755 ) ,
+ .p2736 ( optlc_net_2756 ) , .p2737 ( optlc_net_2757 ) ,
+ .p2738 ( optlc_net_2758 ) , .p2739 ( optlc_net_2759 ) ,
+ .p2740 ( optlc_net_2760 ) , .p2741 ( optlc_net_2761 ) ,
+ .p2742 ( optlc_net_2762 ) , .p2743 ( optlc_net_2763 ) ,
+ .p2744 ( optlc_net_2764 ) , .p2745 ( optlc_net_2765 ) ,
+ .p2746 ( optlc_net_2766 ) , .p2747 ( optlc_net_2767 ) ,
+ .p2748 ( optlc_net_2768 ) , .p2749 ( optlc_net_2769 ) ,
+ .p2750 ( optlc_net_2770 ) , .p2751 ( optlc_net_2771 ) ,
+ .p2752 ( optlc_net_2772 ) , .p2753 ( optlc_net_2773 ) ,
+ .p2754 ( optlc_net_2774 ) , .p2755 ( optlc_net_2775 ) ,
+ .p2756 ( optlc_net_2776 ) , .p2757 ( optlc_net_2777 ) ,
+ .p2758 ( optlc_net_2778 ) , .p2759 ( optlc_net_2779 ) ,
+ .p2760 ( optlc_net_2780 ) , .p2761 ( optlc_net_2781 ) ,
+ .p2762 ( optlc_net_2782 ) , .p2763 ( optlc_net_2783 ) ,
+ .p2764 ( optlc_net_2784 ) , .p2765 ( optlc_net_2785 ) ,
+ .p2766 ( optlc_net_2786 ) , .p2767 ( optlc_net_2787 ) ,
+ .p2768 ( optlc_net_2788 ) , .p2769 ( optlc_net_2789 ) ,
+ .p2770 ( optlc_net_2790 ) , .p2771 ( optlc_net_2791 ) ,
+ .p2772 ( optlc_net_2792 ) , .p2773 ( optlc_net_2793 ) ,
+ .p2774 ( optlc_net_2794 ) , .p2775 ( optlc_net_2795 ) ,
+ .p2776 ( optlc_net_2796 ) , .p2777 ( optlc_net_2797 ) ,
+ .p2778 ( optlc_net_2798 ) , .p2779 ( optlc_net_2799 ) ,
+ .p2780 ( optlc_net_2800 ) , .p2781 ( optlc_net_2801 ) ,
+ .p2782 ( optlc_net_2802 ) , .p2783 ( optlc_net_2803 ) ,
+ .p2784 ( optlc_net_2804 ) , .p2785 ( optlc_net_2805 ) ,
+ .p2786 ( optlc_net_2806 ) , .p2787 ( optlc_net_2807 ) ,
+ .p2788 ( optlc_net_2808 ) , .p2789 ( optlc_net_2809 ) ,
+ .p2790 ( optlc_net_2810 ) , .p2791 ( optlc_net_2811 ) ,
+ .p2792 ( optlc_net_2812 ) , .p2793 ( optlc_net_2813 ) ,
+ .p2794 ( optlc_net_2814 ) , .p2795 ( optlc_net_2815 ) ,
+ .p2796 ( optlc_net_2816 ) , .p2797 ( optlc_net_2817 ) ,
+ .p2798 ( optlc_net_2818 ) , .p2799 ( optlc_net_2819 ) ,
+ .p2800 ( optlc_net_2820 ) , .p2801 ( optlc_net_2821 ) ,
+ .p2802 ( optlc_net_2822 ) , .p2803 ( optlc_net_2823 ) ,
+ .p2804 ( optlc_net_2824 ) , .p2805 ( optlc_net_2825 ) ,
+ .p2806 ( optlc_net_2826 ) , .p2807 ( optlc_net_2827 ) ,
+ .p2808 ( optlc_net_2828 ) , .p2809 ( optlc_net_2829 ) ,
+ .p2810 ( optlc_net_2830 ) , .p2811 ( optlc_net_2831 ) ,
+ .p2812 ( optlc_net_2832 ) , .p2813 ( optlc_net_2833 ) ,
+ .p2814 ( optlc_net_2834 ) , .p2815 ( optlc_net_2835 ) ,
+ .p2816 ( optlc_net_2836 ) , .p2817 ( optlc_net_2837 ) ,
+ .p2818 ( optlc_net_2838 ) , .p2819 ( optlc_net_2839 ) ,
+ .p2820 ( optlc_net_2840 ) , .p2821 ( optlc_net_2841 ) ,
+ .p2822 ( optlc_net_2842 ) , .p2823 ( optlc_net_2843 ) ,
+ .p2824 ( optlc_net_2844 ) , .p2825 ( optlc_net_2845 ) ,
+ .p2826 ( optlc_net_2846 ) , .p2827 ( optlc_net_2847 ) ,
+ .p2828 ( optlc_net_2848 ) , .p2829 ( optlc_net_2849 ) ,
+ .p2830 ( optlc_net_2850 ) , .p2831 ( optlc_net_2851 ) ,
+ .p2832 ( optlc_net_2852 ) , .p2833 ( optlc_net_2853 ) ,
+ .p2834 ( optlc_net_2854 ) , .p2835 ( optlc_net_2855 ) ,
+ .p2836 ( optlc_net_2856 ) , .p2837 ( optlc_net_2857 ) ,
+ .p2838 ( optlc_net_2858 ) , .p2839 ( optlc_net_2859 ) ,
+ .p2840 ( optlc_net_2860 ) , .p2841 ( optlc_net_2861 ) ,
+ .p2842 ( optlc_net_2862 ) , .p2843 ( optlc_net_2863 ) ,
+ .p2844 ( optlc_net_2864 ) , .p2845 ( optlc_net_2865 ) ,
+ .p2846 ( optlc_net_2866 ) , .p2847 ( optlc_net_2867 ) ,
+ .p2848 ( optlc_net_2868 ) , .p2849 ( optlc_net_2869 ) ,
+ .p2850 ( optlc_net_2870 ) , .p2851 ( optlc_net_2871 ) ,
+ .p2852 ( optlc_net_2872 ) , .p2853 ( optlc_net_2873 ) ,
+ .p2854 ( optlc_net_2874 ) , .p2855 ( optlc_net_2875 ) ,
+ .p2856 ( optlc_net_2876 ) , .p2857 ( optlc_net_2877 ) ,
+ .p2858 ( optlc_net_2878 ) , .p2859 ( optlc_net_2879 ) ,
+ .p2860 ( optlc_net_2880 ) , .p2861 ( optlc_net_2881 ) ,
+ .p2862 ( optlc_net_2882 ) , .p2863 ( optlc_net_2883 ) ,
+ .p2864 ( optlc_net_2884 ) , .p2865 ( optlc_net_2885 ) ,
+ .p2866 ( optlc_net_2886 ) , .p2867 ( optlc_net_2887 ) ,
+ .p2868 ( optlc_net_2888 ) , .p2869 ( optlc_net_2889 ) ,
+ .p2870 ( optlc_net_2890 ) , .p2871 ( optlc_net_2891 ) ,
+ .p2872 ( optlc_net_2892 ) , .p2873 ( optlc_net_2893 ) ,
+ .p2874 ( optlc_net_2894 ) , .p2875 ( optlc_net_2895 ) ,
+ .p2876 ( optlc_net_2896 ) , .p2877 ( optlc_net_2897 ) ,
+ .p2878 ( optlc_net_2898 ) , .p2879 ( optlc_net_2899 ) ,
+ .p2880 ( optlc_net_2900 ) , .p2881 ( optlc_net_2901 ) ,
+ .p2882 ( optlc_net_2902 ) , .p2883 ( optlc_net_2903 ) ,
+ .p2884 ( optlc_net_2904 ) , .p2885 ( optlc_net_2905 ) ,
+ .p2886 ( optlc_net_2906 ) , .p2887 ( optlc_net_2907 ) ,
+ .p2888 ( optlc_net_2908 ) , .p2889 ( optlc_net_2909 ) ,
+ .p2890 ( optlc_net_2910 ) , .p2891 ( optlc_net_2911 ) ,
+ .p2892 ( optlc_net_2912 ) , .p2893 ( optlc_net_2913 ) ,
+ .p2894 ( optlc_net_2914 ) , .p2895 ( optlc_net_2915 ) ,
+ .p2896 ( optlc_net_2916 ) , .p2897 ( optlc_net_2917 ) ,
+ .p2898 ( optlc_net_2918 ) , .p2899 ( optlc_net_2919 ) ,
+ .p2900 ( optlc_net_2920 ) , .p2901 ( optlc_net_2921 ) ,
+ .p2902 ( optlc_net_2922 ) , .p2903 ( optlc_net_2923 ) ,
+ .p2904 ( optlc_net_2924 ) , .p2905 ( optlc_net_2925 ) ,
+ .p2906 ( optlc_net_2926 ) , .p2907 ( optlc_net_2927 ) ,
+ .p2908 ( optlc_net_2928 ) , .p2909 ( optlc_net_2929 ) ,
+ .p2910 ( optlc_net_2930 ) , .p2911 ( optlc_net_2931 ) ,
+ .p2912 ( optlc_net_2932 ) , .p2913 ( optlc_net_2933 ) ,
+ .p2914 ( optlc_net_2934 ) , .p2915 ( optlc_net_2935 ) ,
+ .p2916 ( optlc_net_2936 ) , .p2917 ( optlc_net_2937 ) ,
+ .p2918 ( optlc_net_2938 ) , .p2919 ( optlc_net_2939 ) ,
+ .p2920 ( optlc_net_2940 ) , .p2921 ( optlc_net_2941 ) ,
+ .p2922 ( optlc_net_2942 ) , .p2923 ( optlc_net_2943 ) ,
+ .p2924 ( optlc_net_2944 ) , .p2925 ( optlc_net_2945 ) ,
+ .p2926 ( optlc_net_2946 ) , .p2927 ( optlc_net_2947 ) ,
+ .p2928 ( optlc_net_2948 ) , .p2929 ( optlc_net_2949 ) ,
+ .p2930 ( optlc_net_2950 ) , .p2931 ( optlc_net_2951 ) ,
+ .p2932 ( optlc_net_2952 ) , .p2933 ( optlc_net_2953 ) ,
+ .p2934 ( optlc_net_2954 ) , .p2935 ( optlc_net_2955 ) ,
+ .p2936 ( optlc_net_2956 ) , .p2937 ( optlc_net_2957 ) ,
+ .p2938 ( optlc_net_2958 ) , .p2939 ( optlc_net_2959 ) ,
+ .p2940 ( optlc_net_2960 ) , .p2941 ( optlc_net_2961 ) ,
+ .p2942 ( optlc_net_2962 ) , .p2943 ( optlc_net_2963 ) ,
+ .p2944 ( optlc_net_2964 ) , .p2945 ( optlc_net_2965 ) ,
+ .p2946 ( optlc_net_2966 ) , .p2947 ( optlc_net_2967 ) ,
+ .p2948 ( optlc_net_2968 ) , .p2949 ( optlc_net_2969 ) ,
+ .p2950 ( optlc_net_2970 ) , .p2951 ( optlc_net_2971 ) ,
+ .p2952 ( optlc_net_2972 ) , .p2953 ( optlc_net_2973 ) ,
+ .p2954 ( optlc_net_2974 ) , .p2955 ( optlc_net_2975 ) ,
+ .p2956 ( optlc_net_2976 ) , .p2957 ( optlc_net_2977 ) ,
+ .p2958 ( optlc_net_2978 ) , .p2959 ( optlc_net_2979 ) ,
+ .p2960 ( optlc_net_2980 ) , .p2961 ( optlc_net_2981 ) ,
+ .p2962 ( optlc_net_2982 ) , .p2963 ( optlc_net_2983 ) ,
+ .p2964 ( optlc_net_2984 ) , .p2965 ( optlc_net_2985 ) ,
+ .p2966 ( optlc_net_2986 ) , .p2967 ( optlc_net_2987 ) ,
+ .p2968 ( optlc_net_2988 ) , .p2969 ( optlc_net_2989 ) ,
+ .p2970 ( optlc_net_2990 ) , .p2971 ( optlc_net_2991 ) ,
+ .p2972 ( optlc_net_2992 ) , .p2973 ( optlc_net_2993 ) ,
+ .p2974 ( optlc_net_2994 ) , .p2975 ( optlc_net_2995 ) ,
+ .p2976 ( optlc_net_2996 ) , .p2977 ( optlc_net_2997 ) ,
+ .p2978 ( optlc_net_2998 ) , .p2979 ( optlc_net_2999 ) ,
+ .p2980 ( optlc_net_3000 ) , .p2981 ( optlc_net_3001 ) ,
+ .p2982 ( optlc_net_3002 ) , .p2983 ( optlc_net_3003 ) ,
+ .p2984 ( optlc_net_3004 ) , .p2985 ( optlc_net_3005 ) ,
+ .p2986 ( optlc_net_3006 ) , .p2987 ( optlc_net_3007 ) ,
+ .p2988 ( optlc_net_3008 ) , .p2989 ( optlc_net_3009 ) ,
+ .p2990 ( optlc_net_3010 ) , .p2991 ( optlc_net_3011 ) ,
+ .p2992 ( optlc_net_3012 ) , .p2993 ( optlc_net_3013 ) ,
+ .p2994 ( optlc_net_3014 ) , .p2995 ( optlc_net_3015 ) ,
+ .p2996 ( optlc_net_3016 ) , .p2997 ( optlc_net_3017 ) ,
+ .p2998 ( optlc_net_3018 ) , .p2999 ( optlc_net_3019 ) ,
+ .p3000 ( optlc_net_3020 ) , .p3001 ( optlc_net_3021 ) ,
+ .p3002 ( optlc_net_3022 ) , .p3003 ( optlc_net_3023 ) ,
+ .p3004 ( optlc_net_3024 ) , .p3005 ( optlc_net_3025 ) ,
+ .p3006 ( optlc_net_3026 ) , .p3007 ( optlc_net_3027 ) ,
+ .p3008 ( optlc_net_3028 ) , .p3009 ( optlc_net_3029 ) ,
+ .p3010 ( optlc_net_3030 ) , .p3011 ( optlc_net_3031 ) ,
+ .p3012 ( optlc_net_3032 ) , .p3013 ( optlc_net_3033 ) ,
+ .p3014 ( optlc_net_3034 ) , .p3015 ( optlc_net_3035 ) ,
+ .p3016 ( optlc_net_3036 ) , .p3017 ( optlc_net_3037 ) ,
+ .p3018 ( optlc_net_3038 ) , .p3019 ( optlc_net_3039 ) ,
+ .p3020 ( optlc_net_3040 ) , .p3021 ( optlc_net_3041 ) ,
+ .p3022 ( optlc_net_3042 ) , .p3023 ( optlc_net_3043 ) ,
+ .p3024 ( optlc_net_3044 ) , .p3025 ( optlc_net_3045 ) ,
+ .p3026 ( optlc_net_3046 ) , .p3027 ( optlc_net_3047 ) ,
+ .p3028 ( optlc_net_3048 ) , .p3029 ( optlc_net_3049 ) ,
+ .p3030 ( optlc_net_3050 ) , .p3031 ( optlc_net_3051 ) ,
+ .p3032 ( optlc_net_3052 ) , .p3033 ( optlc_net_3053 ) ,
+ .p3034 ( optlc_net_3054 ) , .p3035 ( optlc_net_3055 ) ,
+ .p3036 ( optlc_net_3056 ) , .p3037 ( optlc_net_3057 ) ,
+ .p3038 ( optlc_net_3058 ) , .p3039 ( optlc_net_3059 ) ,
+ .p3040 ( optlc_net_3060 ) , .p3041 ( optlc_net_3061 ) ,
+ .p3042 ( optlc_net_3062 ) , .p3043 ( optlc_net_3063 ) ,
+ .p3044 ( optlc_net_3064 ) , .p3045 ( optlc_net_3065 ) ,
+ .p3046 ( optlc_net_3066 ) , .p3047 ( optlc_net_3067 ) ,
+ .p3048 ( optlc_net_3068 ) , .p3049 ( optlc_net_3069 ) ,
+ .p3050 ( optlc_net_3070 ) , .p3051 ( optlc_net_3071 ) ,
+ .p3052 ( optlc_net_3072 ) , .p3053 ( optlc_net_3073 ) ,
+ .p3054 ( optlc_net_3074 ) , .p3055 ( optlc_net_3075 ) ,
+ .p3056 ( optlc_net_3076 ) , .p3057 ( optlc_net_3077 ) ,
+ .p3058 ( optlc_net_3078 ) , .p3059 ( optlc_net_3079 ) ,
+ .p3060 ( optlc_net_3080 ) , .p3061 ( optlc_net_3081 ) ,
+ .p3062 ( optlc_net_3082 ) , .p3063 ( optlc_net_3083 ) ,
+ .p3064 ( optlc_net_3084 ) , .p3065 ( optlc_net_3085 ) ,
+ .p3066 ( optlc_net_3086 ) , .p3067 ( optlc_net_3087 ) ,
+ .p3068 ( optlc_net_3088 ) , .p3069 ( optlc_net_3089 ) ,
+ .p3070 ( optlc_net_3090 ) , .p3071 ( optlc_net_3091 ) ,
+ .p3072 ( optlc_net_3092 ) , .p3073 ( optlc_net_3093 ) ,
+ .p3074 ( optlc_net_3094 ) , .p3075 ( optlc_net_3095 ) ,
+ .p3076 ( optlc_net_3096 ) , .p3077 ( optlc_net_3097 ) ,
+ .p3078 ( optlc_net_3098 ) , .p3079 ( optlc_net_3099 ) ,
+ .p3080 ( optlc_net_3100 ) , .p3081 ( optlc_net_3101 ) ,
+ .p3082 ( optlc_net_3102 ) , .p3083 ( optlc_net_3103 ) ,
+ .p3084 ( optlc_net_3104 ) , .p3085 ( optlc_net_3105 ) ,
+ .p3086 ( optlc_net_3106 ) , .p3087 ( optlc_net_3107 ) ,
+ .p3088 ( optlc_net_3108 ) , .p3089 ( optlc_net_3109 ) ,
+ .p3090 ( optlc_net_3110 ) , .p3091 ( optlc_net_3111 ) ,
+ .p3092 ( optlc_net_3112 ) , .p3093 ( optlc_net_3113 ) ,
+ .p3094 ( optlc_net_3114 ) , .p3095 ( optlc_net_3115 ) ,
+ .p3096 ( optlc_net_3116 ) , .p3097 ( optlc_net_3117 ) ,
+ .p3098 ( optlc_net_3118 ) , .p3099 ( optlc_net_3119 ) ,
+ .p3100 ( optlc_net_3120 ) , .p3101 ( optlc_net_3121 ) ,
+ .p3102 ( optlc_net_3122 ) , .p3103 ( optlc_net_3123 ) ,
+ .p3104 ( optlc_net_3124 ) , .p3105 ( optlc_net_3125 ) ,
+ .p3106 ( optlc_net_3126 ) , .p3107 ( optlc_net_3127 ) ,
+ .p3108 ( optlc_net_3128 ) , .p3109 ( optlc_net_3129 ) ,
+ .p3110 ( optlc_net_3130 ) , .p3111 ( optlc_net_3131 ) ,
+ .p3112 ( optlc_net_3132 ) , .p3113 ( optlc_net_3133 ) ,
+ .p3114 ( optlc_net_3134 ) , .p3115 ( optlc_net_3135 ) ,
+ .p3116 ( optlc_net_3136 ) , .p3117 ( optlc_net_3137 ) ,
+ .p3118 ( optlc_net_3138 ) , .p3119 ( optlc_net_3139 ) ,
+ .p3120 ( optlc_net_3140 ) , .p3121 ( optlc_net_3141 ) ,
+ .p3122 ( optlc_net_3142 ) , .p3123 ( optlc_net_3143 ) ,
+ .p3124 ( optlc_net_3144 ) , .p3125 ( optlc_net_3145 ) ,
+ .p3126 ( optlc_net_3146 ) , .p3127 ( optlc_net_3147 ) ,
+ .p3128 ( optlc_net_3148 ) , .p3129 ( optlc_net_3149 ) ,
+ .p3130 ( optlc_net_3150 ) , .p3131 ( optlc_net_3151 ) ,
+ .p3132 ( optlc_net_3152 ) , .p3133 ( optlc_net_3153 ) ,
+ .p3134 ( optlc_net_3154 ) , .p3135 ( optlc_net_3155 ) ,
+ .p3136 ( optlc_net_3156 ) , .p3137 ( optlc_net_3157 ) ,
+ .p3138 ( optlc_net_3158 ) , .p3139 ( optlc_net_3159 ) ,
+ .p3140 ( optlc_net_3160 ) , .p3141 ( optlc_net_3161 ) ,
+ .p3142 ( optlc_net_3162 ) , .p3143 ( optlc_net_3163 ) ,
+ .p3144 ( optlc_net_3164 ) , .p3145 ( optlc_net_3165 ) ,
+ .p3146 ( optlc_net_3166 ) , .p3147 ( optlc_net_3167 ) ,
+ .p3148 ( optlc_net_3168 ) , .p3149 ( optlc_net_3169 ) ,
+ .p3150 ( optlc_net_3170 ) , .p3151 ( optlc_net_3171 ) ,
+ .p3152 ( optlc_net_3172 ) , .p3153 ( optlc_net_3173 ) ,
+ .p3154 ( optlc_net_3174 ) , .p3155 ( optlc_net_3175 ) ,
+ .p3156 ( optlc_net_3176 ) , .p3157 ( optlc_net_3177 ) ,
+ .p3158 ( optlc_net_3178 ) , .p3159 ( optlc_net_3179 ) ,
+ .p3160 ( optlc_net_3180 ) , .p3161 ( optlc_net_3181 ) ,
+ .p3162 ( optlc_net_3182 ) , .p3163 ( optlc_net_3183 ) ,
+ .p3164 ( optlc_net_3184 ) , .p3165 ( optlc_net_3185 ) ,
+ .p3166 ( optlc_net_3186 ) , .p3167 ( optlc_net_3187 ) ,
+ .p3168 ( optlc_net_3188 ) , .p3169 ( optlc_net_3189 ) ,
+ .p3170 ( optlc_net_3190 ) , .p3171 ( optlc_net_3191 ) ,
+ .p3172 ( optlc_net_3192 ) , .p3173 ( optlc_net_3193 ) ,
+ .p3174 ( optlc_net_3194 ) , .p3175 ( optlc_net_3195 ) ,
+ .p3176 ( optlc_net_3196 ) , .p3177 ( optlc_net_3197 ) ,
+ .p3178 ( optlc_net_3198 ) , .p3179 ( optlc_net_3199 ) ,
+ .p3180 ( optlc_net_3200 ) , .p3181 ( optlc_net_3201 ) ,
+ .p3182 ( optlc_net_3202 ) , .p3183 ( optlc_net_3203 ) ,
+ .p3184 ( optlc_net_3204 ) , .p3185 ( optlc_net_3205 ) ,
+ .p3186 ( optlc_net_3206 ) , .p3187 ( optlc_net_3207 ) ,
+ .p3188 ( optlc_net_3208 ) , .p3189 ( optlc_net_3209 ) ,
+ .p3190 ( optlc_net_3210 ) , .p3191 ( optlc_net_3211 ) ,
+ .p3192 ( optlc_net_3212 ) , .p3193 ( optlc_net_3213 ) ,
+ .p3194 ( optlc_net_3214 ) , .p3195 ( optlc_net_3215 ) ,
+ .p3196 ( optlc_net_3216 ) , .p3197 ( optlc_net_3217 ) ,
+ .p3198 ( optlc_net_3218 ) , .p3199 ( optlc_net_3219 ) ,
+ .p3200 ( optlc_net_3220 ) , .p3201 ( optlc_net_3221 ) ,
+ .p3202 ( optlc_net_3222 ) , .p3203 ( optlc_net_3223 ) ,
+ .p3204 ( optlc_net_3224 ) , .p3205 ( optlc_net_3225 ) ,
+ .p3206 ( optlc_net_3226 ) , .p3207 ( optlc_net_3227 ) ,
+ .p3208 ( optlc_net_3228 ) , .p3209 ( optlc_net_3229 ) ,
+ .p3210 ( optlc_net_3230 ) , .p3211 ( optlc_net_3231 ) ,
+ .p3212 ( optlc_net_3232 ) , .p3213 ( optlc_net_3233 ) ,
+ .p3214 ( optlc_net_3234 ) , .p3215 ( optlc_net_3235 ) ,
+ .p3216 ( optlc_net_3236 ) , .p3217 ( optlc_net_3237 ) ,
+ .p3218 ( optlc_net_3238 ) , .p3219 ( optlc_net_3239 ) ,
+ .p3220 ( optlc_net_3240 ) , .p3221 ( optlc_net_3241 ) ,
+ .p3222 ( optlc_net_3242 ) , .p3223 ( optlc_net_3243 ) ,
+ .p3224 ( optlc_net_3244 ) , .p3225 ( optlc_net_3245 ) ,
+ .p3226 ( optlc_net_3246 ) , .p3227 ( optlc_net_3247 ) ,
+ .p3228 ( optlc_net_3248 ) , .p3229 ( optlc_net_3249 ) ,
+ .p3230 ( optlc_net_3250 ) , .p3231 ( optlc_net_3251 ) ,
+ .p3232 ( optlc_net_3252 ) , .p3233 ( optlc_net_3253 ) ,
+ .p3234 ( optlc_net_3254 ) , .p3235 ( optlc_net_3255 ) ,
+ .p3236 ( optlc_net_3256 ) , .p3237 ( optlc_net_3257 ) ,
+ .p3238 ( optlc_net_3258 ) , .p3239 ( optlc_net_3259 ) ,
+ .p3240 ( optlc_net_3260 ) , .p3241 ( optlc_net_3261 ) ,
+ .p3242 ( optlc_net_3262 ) , .p3243 ( optlc_net_3263 ) ,
+ .p3244 ( optlc_net_3264 ) , .p3245 ( optlc_net_3265 ) ,
+ .p3246 ( optlc_net_3266 ) , .p3247 ( optlc_net_3267 ) ,
+ .p3248 ( optlc_net_3268 ) , .p3249 ( optlc_net_3269 ) ,
+ .p3250 ( optlc_net_3270 ) , .p3251 ( optlc_net_3271 ) ,
+ .p3252 ( optlc_net_3272 ) , .p3253 ( optlc_net_3273 ) ,
+ .p3254 ( optlc_net_3274 ) , .p3255 ( optlc_net_3275 ) ,
+ .p3256 ( optlc_net_3276 ) , .p3257 ( optlc_net_3277 ) ,
+ .p3258 ( optlc_net_3278 ) , .p3259 ( optlc_net_3279 ) ,
+ .p3260 ( optlc_net_3280 ) , .p3261 ( optlc_net_3281 ) ,
+ .p3262 ( optlc_net_3282 ) , .p3263 ( optlc_net_3283 ) ,
+ .p3264 ( optlc_net_3284 ) , .p3265 ( optlc_net_3285 ) ,
+ .p3266 ( optlc_net_3286 ) , .p3267 ( optlc_net_3287 ) ,
+ .p3268 ( optlc_net_3288 ) , .p3269 ( optlc_net_3289 ) ,
+ .p3270 ( optlc_net_3290 ) , .p3271 ( optlc_net_3291 ) ,
+ .p3272 ( optlc_net_3292 ) , .p3273 ( optlc_net_3293 ) ,
+ .p3274 ( optlc_net_3294 ) , .p3275 ( optlc_net_3295 ) ,
+ .p3276 ( optlc_net_3296 ) , .p3277 ( optlc_net_3297 ) ,
+ .p3278 ( optlc_net_3298 ) , .p3279 ( optlc_net_3299 ) ,
+ .p3280 ( optlc_net_3300 ) , .p3281 ( optlc_net_3301 ) ,
+ .p3282 ( optlc_net_3302 ) , .p3283 ( optlc_net_3303 ) ,
+ .p3284 ( optlc_net_3304 ) , .p3285 ( optlc_net_3305 ) ,
+ .p3286 ( optlc_net_3306 ) , .p3287 ( optlc_net_3307 ) ,
+ .p3288 ( optlc_net_3308 ) , .p3289 ( optlc_net_3309 ) ,
+ .p3290 ( optlc_net_3310 ) , .p3291 ( optlc_net_3311 ) ,
+ .p3292 ( optlc_net_3312 ) , .p3293 ( optlc_net_3313 ) ,
+ .p3294 ( optlc_net_3314 ) , .p3295 ( optlc_net_3315 ) ,
+ .p3296 ( optlc_net_3316 ) , .p3297 ( optlc_net_3317 ) ,
+ .p3298 ( optlc_net_3318 ) , .p3299 ( optlc_net_3319 ) ,
+ .p3300 ( optlc_net_3320 ) , .p3301 ( optlc_net_3321 ) ,
+ .p3302 ( optlc_net_3322 ) , .p3303 ( optlc_net_3323 ) ,
+ .p3304 ( optlc_net_3324 ) , .p3305 ( optlc_net_3325 ) ,
+ .p3306 ( optlc_net_3326 ) , .p3307 ( optlc_net_3327 ) ,
+ .p3308 ( optlc_net_3328 ) , .p3309 ( optlc_net_3329 ) ,
+ .p3310 ( optlc_net_3330 ) , .p3311 ( optlc_net_3331 ) ,
+ .p3312 ( optlc_net_3332 ) , .p3313 ( optlc_net_3333 ) ,
+ .p3314 ( optlc_net_3334 ) , .p3315 ( optlc_net_3335 ) ,
+ .p3316 ( optlc_net_3336 ) , .p3317 ( optlc_net_3337 ) ,
+ .p3318 ( optlc_net_3338 ) , .p3319 ( optlc_net_3339 ) ,
+ .p3320 ( optlc_net_3340 ) , .p3321 ( optlc_net_3341 ) ,
+ .p3322 ( optlc_net_3342 ) , .p3323 ( optlc_net_3343 ) ,
+ .p3324 ( optlc_net_3344 ) , .p3325 ( optlc_net_3345 ) ,
+ .p3326 ( optlc_net_3346 ) , .p3327 ( optlc_net_3347 ) ,
+ .p3328 ( optlc_net_3348 ) , .p3329 ( optlc_net_3349 ) ,
+ .p3330 ( optlc_net_3350 ) , .p3331 ( optlc_net_3351 ) ,
+ .p3332 ( optlc_net_3352 ) , .p3333 ( optlc_net_3353 ) ,
+ .p3334 ( optlc_net_3354 ) , .p3335 ( optlc_net_3355 ) ,
+ .p3336 ( optlc_net_3356 ) , .p3337 ( optlc_net_3357 ) ,
+ .p3338 ( optlc_net_3358 ) , .p3339 ( optlc_net_3359 ) ,
+ .p3340 ( optlc_net_3360 ) , .p3341 ( optlc_net_3361 ) ,
+ .p3342 ( optlc_net_3362 ) , .p3343 ( optlc_net_3363 ) ,
+ .p3344 ( optlc_net_3364 ) , .p3345 ( optlc_net_3365 ) ,
+ .p3346 ( optlc_net_3366 ) , .p3347 ( optlc_net_3367 ) ,
+ .p3348 ( optlc_net_3368 ) , .p3349 ( optlc_net_3369 ) ,
+ .p3350 ( optlc_net_3370 ) , .p3351 ( optlc_net_3371 ) ,
+ .p3352 ( optlc_net_3372 ) , .p3353 ( optlc_net_3373 ) ,
+ .p3354 ( optlc_net_3374 ) , .p3355 ( optlc_net_3375 ) ,
+ .p3356 ( optlc_net_3376 ) , .p3357 ( optlc_net_3377 ) ,
+ .p3358 ( optlc_net_3378 ) , .p3359 ( optlc_net_3379 ) ,
+ .p3360 ( optlc_net_3380 ) , .p3361 ( optlc_net_3381 ) ,
+ .p3362 ( optlc_net_3382 ) , .p3363 ( optlc_net_3383 ) ,
+ .p3364 ( optlc_net_3384 ) , .p3365 ( optlc_net_3385 ) ,
+ .p3366 ( optlc_net_3386 ) , .p3367 ( optlc_net_3387 ) ,
+ .p3368 ( optlc_net_3388 ) , .p3369 ( optlc_net_3389 ) ,
+ .p3370 ( optlc_net_3390 ) , .p3371 ( optlc_net_3391 ) ,
+ .p3372 ( optlc_net_3392 ) , .p3373 ( optlc_net_3393 ) ,
+ .p3374 ( optlc_net_3394 ) , .p3375 ( optlc_net_3395 ) ,
+ .p3376 ( optlc_net_3396 ) , .p3377 ( optlc_net_3397 ) ,
+ .p3378 ( optlc_net_3398 ) , .p3379 ( optlc_net_3399 ) ,
+ .p3380 ( optlc_net_3400 ) , .p3381 ( optlc_net_3401 ) ,
+ .p3382 ( optlc_net_3402 ) , .p3383 ( optlc_net_3403 ) ,
+ .p3384 ( optlc_net_3404 ) , .p3385 ( optlc_net_3405 ) ,
+ .p3386 ( optlc_net_3406 ) , .p3387 ( optlc_net_3407 ) ,
+ .p3388 ( optlc_net_3408 ) , .p3389 ( optlc_net_3409 ) ,
+ .p3390 ( optlc_net_3410 ) , .p3391 ( optlc_net_3411 ) ,
+ .p3392 ( optlc_net_3412 ) , .p3393 ( optlc_net_3413 ) ,
+ .p3394 ( optlc_net_3414 ) , .p3395 ( optlc_net_3415 ) ,
+ .p3396 ( optlc_net_3416 ) , .p3397 ( optlc_net_3417 ) ,
+ .p3398 ( optlc_net_3418 ) , .p3399 ( optlc_net_3419 ) ,
+ .p3400 ( optlc_net_3420 ) , .p3401 ( optlc_net_3421 ) ,
+ .p3402 ( optlc_net_3422 ) , .p3403 ( optlc_net_3423 ) ,
+ .p3404 ( optlc_net_3424 ) , .p3405 ( optlc_net_3425 ) ,
+ .p3406 ( optlc_net_3426 ) , .p3407 ( optlc_net_3427 ) ,
+ .p3408 ( optlc_net_3428 ) , .p3409 ( optlc_net_3429 ) ,
+ .p3410 ( optlc_net_3430 ) , .p3411 ( optlc_net_3431 ) ,
+ .p3412 ( optlc_net_3432 ) , .p3413 ( optlc_net_3433 ) ,
+ .p3414 ( optlc_net_3434 ) , .p3415 ( optlc_net_3435 ) ,
+ .p3416 ( optlc_net_3436 ) , .p3417 ( optlc_net_3437 ) ,
+ .p3418 ( optlc_net_3438 ) , .p3419 ( optlc_net_3439 ) ,
+ .p3420 ( optlc_net_3440 ) , .p3421 ( optlc_net_3441 ) ,
+ .p3422 ( optlc_net_3442 ) , .p3423 ( optlc_net_3443 ) ,
+ .p3424 ( optlc_net_3444 ) , .p3425 ( optlc_net_3445 ) ,
+ .p3426 ( optlc_net_3446 ) , .p3427 ( optlc_net_3447 ) ,
+ .p3428 ( optlc_net_3448 ) , .p3429 ( optlc_net_3449 ) ,
+ .p3430 ( optlc_net_3450 ) , .p3431 ( optlc_net_3451 ) ,
+ .p3432 ( optlc_net_3452 ) , .p3433 ( optlc_net_3453 ) ,
+ .p3434 ( optlc_net_3454 ) , .p3435 ( optlc_net_3455 ) ,
+ .p3436 ( optlc_net_3456 ) , .p3437 ( optlc_net_3457 ) ,
+ .p3438 ( optlc_net_3458 ) , .p3439 ( optlc_net_3459 ) ,
+ .p3440 ( optlc_net_3460 ) , .p3441 ( optlc_net_3461 ) ,
+ .p3442 ( optlc_net_3462 ) , .p3443 ( optlc_net_3463 ) ,
+ .p3444 ( optlc_net_3464 ) , .p3445 ( optlc_net_3465 ) ,
+ .p3446 ( optlc_net_3466 ) , .p3447 ( optlc_net_3467 ) ,
+ .p3448 ( optlc_net_3468 ) , .p3449 ( optlc_net_3469 ) ,
+ .p3450 ( optlc_net_3470 ) , .p3451 ( optlc_net_3471 ) ,
+ .p3452 ( optlc_net_3472 ) , .p3453 ( optlc_net_3473 ) ,
+ .p3454 ( optlc_net_3474 ) , .p3455 ( optlc_net_3475 ) ,
+ .p3456 ( optlc_net_3476 ) , .p3457 ( optlc_net_3477 ) ,
+ .p3458 ( optlc_net_3478 ) , .p3459 ( optlc_net_3479 ) ,
+ .p3460 ( optlc_net_3480 ) , .p3461 ( optlc_net_3481 ) ,
+ .p3462 ( optlc_net_3482 ) , .p3463 ( optlc_net_3483 ) ,
+ .p3464 ( optlc_net_3484 ) , .p3465 ( optlc_net_3485 ) ,
+ .p3466 ( optlc_net_3486 ) , .p3467 ( optlc_net_3487 ) ,
+ .p3468 ( optlc_net_3488 ) , .p3469 ( optlc_net_3489 ) ,
+ .p3470 ( optlc_net_3490 ) , .p3471 ( optlc_net_3491 ) ,
+ .p3472 ( optlc_net_3492 ) , .p3473 ( optlc_net_3493 ) ,
+ .p3474 ( optlc_net_3494 ) , .p3475 ( optlc_net_3495 ) ,
+ .p3476 ( optlc_net_3496 ) , .p3477 ( optlc_net_3497 ) ,
+ .p3478 ( optlc_net_3498 ) , .p3479 ( optlc_net_3499 ) ,
+ .p3480 ( optlc_net_3500 ) , .p3481 ( optlc_net_3501 ) ,
+ .p3482 ( optlc_net_3502 ) , .p3483 ( optlc_net_3503 ) ,
+ .p3484 ( optlc_net_3504 ) , .p3485 ( optlc_net_3505 ) ,
+ .p3486 ( optlc_net_3506 ) , .p3487 ( optlc_net_3507 ) ,
+ .p3488 ( optlc_net_3508 ) , .p3489 ( optlc_net_3509 ) ,
+ .p3490 ( optlc_net_3510 ) , .p3491 ( optlc_net_3511 ) ,
+ .p3492 ( optlc_net_3512 ) , .p3493 ( optlc_net_3513 ) ,
+ .p3494 ( optlc_net_3514 ) , .p3495 ( optlc_net_3515 ) ,
+ .p3496 ( optlc_net_3516 ) , .p3497 ( optlc_net_3517 ) ,
+ .p3498 ( optlc_net_3518 ) , .p3499 ( optlc_net_3519 ) ,
+ .p3500 ( optlc_net_3520 ) , .p3501 ( optlc_net_3521 ) ,
+ .p3502 ( optlc_net_3522 ) , .p3503 ( optlc_net_3523 ) ,
+ .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) ,
+ .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) ,
+ .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) ,
+ .p3510 ( optlc_net_3530 ) , .p3511 ( optlc_net_3531 ) ,
+ .p3512 ( optlc_net_3532 ) , .p3513 ( optlc_net_3533 ) ,
+ .p3514 ( optlc_net_3534 ) , .p3515 ( optlc_net_3535 ) ,
+ .p3516 ( optlc_net_3536 ) , .p3517 ( optlc_net_3537 ) ,
+ .p3518 ( optlc_net_3538 ) , .p3519 ( optlc_net_3539 ) ,
+ .p3520 ( optlc_net_3540 ) , .p3521 ( optlc_net_3541 ) ,
+ .p3522 ( optlc_net_3542 ) , .p3523 ( optlc_net_3543 ) ,
+ .p3524 ( optlc_net_3544 ) , .p3525 ( optlc_net_3545 ) ,
+ .p3526 ( optlc_net_3546 ) , .p3527 ( optlc_net_3547 ) ,
+ .p3528 ( optlc_net_3548 ) , .p3529 ( optlc_net_3549 ) ,
+ .p3530 ( optlc_net_3550 ) , .p3531 ( optlc_net_3551 ) ,
+ .p3532 ( optlc_net_3552 ) , .p3533 ( optlc_net_3553 ) ,
+ .p3534 ( optlc_net_3554 ) , .p3535 ( optlc_net_3555 ) ,
+ .p3536 ( optlc_net_3556 ) , .p3537 ( optlc_net_3557 ) ,
+ .p3538 ( optlc_net_3558 ) , .p3539 ( optlc_net_3559 ) ,
+ .p3540 ( optlc_net_3560 ) , .p3541 ( optlc_net_3561 ) ,
+ .p3542 ( optlc_net_3562 ) , .p3543 ( optlc_net_3563 ) ,
+ .p3544 ( optlc_net_3564 ) , .p3545 ( optlc_net_3565 ) ,
+ .p3546 ( optlc_net_3566 ) , .p3547 ( optlc_net_3567 ) ,
+ .p3548 ( optlc_net_3568 ) , .p3549 ( optlc_net_3569 ) ,
+ .p3550 ( optlc_net_3570 ) , .p3551 ( optlc_net_3571 ) ,
+ .p3552 ( optlc_net_3572 ) , .p3553 ( optlc_net_3573 ) ,
+ .p3554 ( optlc_net_3574 ) , .p3555 ( optlc_net_3575 ) ,
+ .p3556 ( optlc_net_3576 ) , .p3557 ( optlc_net_3577 ) ,
+ .p3558 ( optlc_net_3578 ) , .p3559 ( optlc_net_3579 ) ,
+ .p3560 ( optlc_net_3580 ) , .p3561 ( optlc_net_3581 ) ,
+ .p3562 ( optlc_net_3582 ) , .p3563 ( optlc_net_3583 ) ,
+ .p3564 ( optlc_net_3584 ) , .p3565 ( optlc_net_3585 ) ,
+ .p3566 ( optlc_net_3586 ) , .p3567 ( optlc_net_3587 ) ,
+ .p3568 ( optlc_net_3588 ) , .p3569 ( optlc_net_3589 ) ,
+ .p3570 ( optlc_net_3590 ) , .p3571 ( optlc_net_3591 ) ,
+ .p3572 ( optlc_net_3592 ) , .p3573 ( optlc_net_3593 ) ,
+ .p3574 ( optlc_net_3594 ) , .p3575 ( optlc_net_3595 ) ,
+ .p3576 ( optlc_net_3596 ) , .p3577 ( optlc_net_3597 ) ,
+ .p3578 ( optlc_net_3598 ) , .p3579 ( optlc_net_3599 ) ,
+ .p3580 ( optlc_net_3600 ) , .p3581 ( optlc_net_3601 ) ,
+ .p3582 ( optlc_net_3602 ) , .p3583 ( optlc_net_3603 ) ,
+ .p3584 ( optlc_net_3604 ) , .p3585 ( optlc_net_3605 ) ,
+ .p3586 ( optlc_net_3606 ) , .p3587 ( optlc_net_3607 ) ,
+ .p3588 ( optlc_net_3608 ) , .p3589 ( optlc_net_3609 ) ,
+ .p3590 ( optlc_net_3610 ) , .p3591 ( optlc_net_3611 ) ,
+ .p3592 ( optlc_net_3612 ) , .p3593 ( optlc_net_3613 ) ,
+ .p3594 ( optlc_net_3614 ) , .p3595 ( optlc_net_3615 ) ,
+ .p3596 ( optlc_net_3616 ) , .p3597 ( optlc_net_3617 ) ,
+ .p3598 ( optlc_net_3618 ) , .p3599 ( optlc_net_3619 ) ,
+ .p3600 ( optlc_net_3620 ) , .p3601 ( optlc_net_3621 ) ,
+ .p3602 ( optlc_net_3622 ) , .p3603 ( optlc_net_3623 ) ,
+ .p3604 ( optlc_net_3624 ) , .p3605 ( optlc_net_3625 ) ,
+ .p3606 ( optlc_net_3626 ) , .p3607 ( optlc_net_3627 ) ,
+ .p3608 ( optlc_net_3628 ) , .p3609 ( optlc_net_3629 ) ,
+ .p3610 ( optlc_net_3630 ) , .p3611 ( optlc_net_3631 ) ,
+ .p3612 ( optlc_net_3632 ) , .p3613 ( optlc_net_3633 ) ,
+ .p3614 ( optlc_net_3634 ) , .p3615 ( optlc_net_3635 ) ,
+ .p3616 ( optlc_net_3636 ) , .p3617 ( optlc_net_3637 ) ,
+ .p3618 ( optlc_net_3638 ) , .p3619 ( optlc_net_3639 ) ,
+ .p3620 ( optlc_net_3640 ) , .p3621 ( optlc_net_3641 ) ,
+ .p3622 ( optlc_net_3642 ) , .p3623 ( optlc_net_3643 ) ,
+ .p3624 ( optlc_net_3644 ) , .p3625 ( optlc_net_3645 ) ,
+ .p3626 ( optlc_net_3646 ) , .p3627 ( optlc_net_3647 ) ,
+ .p3628 ( optlc_net_3648 ) , .p3629 ( optlc_net_3649 ) ,
+ .p3630 ( optlc_net_3650 ) , .p3631 ( optlc_net_3651 ) ,
+ .p3632 ( optlc_net_3652 ) , .p3633 ( optlc_net_3653 ) ,
+ .p3634 ( optlc_net_3654 ) , .p3635 ( optlc_net_3655 ) ,
+ .p3636 ( optlc_net_3656 ) , .p3637 ( optlc_net_3657 ) ,
+ .p3638 ( optlc_net_3658 ) , .p3639 ( optlc_net_3659 ) ,
+ .p3640 ( optlc_net_3660 ) , .p3641 ( optlc_net_3661 ) ,
+ .p3642 ( optlc_net_3662 ) , .p3643 ( optlc_net_3663 ) ,
+ .p3644 ( optlc_net_3664 ) , .p3645 ( optlc_net_3665 ) ,
+ .p3646 ( optlc_net_3666 ) , .p3647 ( optlc_net_3667 ) ,
+ .p3648 ( optlc_net_3668 ) , .p3649 ( optlc_net_3669 ) ,
+ .p3650 ( optlc_net_3670 ) , .p3651 ( optlc_net_3671 ) ,
+ .p3652 ( optlc_net_3672 ) , .p3653 ( optlc_net_3673 ) ,
+ .p3654 ( optlc_net_3674 ) , .p3655 ( optlc_net_3675 ) ,
+ .p3656 ( optlc_net_3676 ) , .p3657 ( optlc_net_3677 ) ,
+ .p3658 ( optlc_net_3678 ) , .p3659 ( optlc_net_3679 ) ,
+ .p3660 ( optlc_net_3680 ) , .p3661 ( optlc_net_3681 ) ,
+ .p3662 ( optlc_net_3682 ) , .p3663 ( optlc_net_3683 ) ,
+ .p3664 ( optlc_net_3684 ) , .p3665 ( optlc_net_3685 ) ,
+ .p3666 ( optlc_net_3686 ) , .p3667 ( optlc_net_3687 ) ,
+ .p3668 ( optlc_net_3688 ) , .p3669 ( optlc_net_3689 ) ,
+ .p3670 ( optlc_net_3690 ) , .p3671 ( optlc_net_3691 ) ,
+ .p3672 ( optlc_net_3692 ) , .p3673 ( optlc_net_3693 ) ,
+ .p3674 ( optlc_net_3694 ) , .p3675 ( optlc_net_3695 ) ,
+ .p3676 ( optlc_net_3696 ) , .p3677 ( optlc_net_3697 ) ,
+ .p3678 ( optlc_net_3698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) ,
+ .HI ( io_oeb[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) ,
+ .HI ( io_oeb[1] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) ,
+ .HI ( io_oeb[2] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
+ .HI ( io_oeb[3] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) ,
+ .HI ( io_oeb[12] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) ,
+ .HI ( io_oeb[25] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) ,
+ .HI ( io_oeb[26] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) ,
+ .HI ( io_oeb[36] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_10 ) ,
+ .HI ( io_oeb[37] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_39 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_40 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_41 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_42 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_43 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_44 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_46 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_47 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_48 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_74 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( optlc_net_75 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( optlc_net_76 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_78 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( optlc_net_77 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_79 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( optlc_net_78 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_80 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( optlc_net_79 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_81 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( optlc_net_80 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_82 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( optlc_net_81 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_83 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( optlc_net_82 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_84 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( optlc_net_83 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_85 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( optlc_net_84 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_86 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( optlc_net_85 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_87 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_87 ( .LO ( optlc_net_86 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_88 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( optlc_net_87 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_89 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( optlc_net_88 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_90 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( optlc_net_89 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_91 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( optlc_net_90 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_92 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( optlc_net_91 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_93 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( optlc_net_92 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_94 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( optlc_net_93 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_95 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( optlc_net_94 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_96 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( optlc_net_95 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_97 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( optlc_net_96 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_98 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( optlc_net_97 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_99 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( optlc_net_98 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( optlc_net_99 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( optlc_net_100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( optlc_net_101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( optlc_net_102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( optlc_net_103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( optlc_net_104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( optlc_net_105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( optlc_net_106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( optlc_net_107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( optlc_net_108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( optlc_net_109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( optlc_net_110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( optlc_net_111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( optlc_net_112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( optlc_net_113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( optlc_net_114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( optlc_net_115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( optlc_net_116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( optlc_net_117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( optlc_net_118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( optlc_net_119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( optlc_net_120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( optlc_net_121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( optlc_net_122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( optlc_net_123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( optlc_net_124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( optlc_net_125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( optlc_net_126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( optlc_net_127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( optlc_net_128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( optlc_net_129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( optlc_net_130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( optlc_net_131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( optlc_net_132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( optlc_net_133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( optlc_net_134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( optlc_net_135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( optlc_net_136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( optlc_net_137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( optlc_net_138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( optlc_net_139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( optlc_net_140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( optlc_net_141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( optlc_net_142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( optlc_net_143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( optlc_net_144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( optlc_net_145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( optlc_net_146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( optlc_net_147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( optlc_net_148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( optlc_net_149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( optlc_net_150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( optlc_net_151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( optlc_net_152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( optlc_net_153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( optlc_net_154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( optlc_net_155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( optlc_net_156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( optlc_net_157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( optlc_net_158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( optlc_net_159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( optlc_net_160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( optlc_net_161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_163 ( .LO ( optlc_net_162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( optlc_net_163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( optlc_net_164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( optlc_net_165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( optlc_net_166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( optlc_net_167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_169 ( .LO ( optlc_net_168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( optlc_net_169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( optlc_net_170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( optlc_net_171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( optlc_net_172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( optlc_net_173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( optlc_net_174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( optlc_net_175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( optlc_net_176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( optlc_net_177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( optlc_net_178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( optlc_net_179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( optlc_net_180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( optlc_net_181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_183 ( .LO ( optlc_net_182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( optlc_net_183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( optlc_net_184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( optlc_net_185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( optlc_net_186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( optlc_net_187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( optlc_net_188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( optlc_net_189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( optlc_net_190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( optlc_net_191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( optlc_net_192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( optlc_net_193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( optlc_net_194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( optlc_net_195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( optlc_net_196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_198 ( .LO ( optlc_net_197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( optlc_net_198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( optlc_net_199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( optlc_net_200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( optlc_net_201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( optlc_net_202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( optlc_net_203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( optlc_net_204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( optlc_net_205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( optlc_net_206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( optlc_net_207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( optlc_net_208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( optlc_net_209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( optlc_net_210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( optlc_net_211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( optlc_net_212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( optlc_net_213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( optlc_net_214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( optlc_net_215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( optlc_net_216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( optlc_net_217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( optlc_net_218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( optlc_net_219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( optlc_net_220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( optlc_net_221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( optlc_net_222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( optlc_net_223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( optlc_net_224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( optlc_net_225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( optlc_net_226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( optlc_net_227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( optlc_net_228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( optlc_net_229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_231 ( .LO ( optlc_net_230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( optlc_net_231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( optlc_net_232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_234 ( .LO ( optlc_net_233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( optlc_net_234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_236 ( .LO ( optlc_net_235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( optlc_net_236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_238 ( .LO ( optlc_net_237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( optlc_net_238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_240 ( .LO ( optlc_net_239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_241 ( .LO ( optlc_net_240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_242 ( .LO ( optlc_net_241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_243 ( .LO ( optlc_net_242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_244 ( .LO ( optlc_net_243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_245 ( .LO ( optlc_net_244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_246 ( .LO ( optlc_net_245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_247 ( .LO ( optlc_net_246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_248 ( .LO ( optlc_net_247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_249 ( .LO ( optlc_net_248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_250 ( .LO ( optlc_net_249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_251 ( .LO ( optlc_net_250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_252 ( .LO ( optlc_net_251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_253 ( .LO ( optlc_net_252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_254 ( .LO ( optlc_net_253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_255 ( .LO ( optlc_net_254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_256 ( .LO ( optlc_net_255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_257 ( .LO ( optlc_net_256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_258 ( .LO ( optlc_net_257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_259 ( .LO ( optlc_net_258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_260 ( .LO ( optlc_net_259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_261 ( .LO ( optlc_net_260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_262 ( .LO ( optlc_net_261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_263 ( .LO ( optlc_net_262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_264 ( .LO ( optlc_net_263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_265 ( .LO ( optlc_net_264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_266 ( .LO ( optlc_net_265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_267 ( .LO ( optlc_net_266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_268 ( .LO ( optlc_net_267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_269 ( .LO ( optlc_net_268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_274 ( .LO ( optlc_net_273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_280 ( .LO ( optlc_net_279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_284 ( .LO ( optlc_net_283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_295 ( .LO ( optlc_net_294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_298 ( .LO ( optlc_net_297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_311 ( .LO ( optlc_net_310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_313 ( .LO ( optlc_net_312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_315 ( .LO ( optlc_net_314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_327 ( .LO ( optlc_net_326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_330 ( .LO ( optlc_net_329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_334 ( .LO ( optlc_net_333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_336 ( .LO ( optlc_net_335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_342 ( .LO ( optlc_net_341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_351 ( .LO ( optlc_net_350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_353 ( .LO ( optlc_net_352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_355 ( .LO ( optlc_net_354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_361 ( .LO ( optlc_net_360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_365 ( .LO ( optlc_net_364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_367 ( .LO ( optlc_net_366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_401 ( .LO ( optlc_net_400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_403 ( .LO ( optlc_net_402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_413 ( .LO ( optlc_net_412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_415 ( .LO ( optlc_net_414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_751 ( .LO ( optlc_net_746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_773 ( .LO ( optlc_net_768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_935 ( .LO ( optlc_net_926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_937 ( .LO ( optlc_net_928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_939 ( .LO ( optlc_net_930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_943 ( .LO ( optlc_net_934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_944 ( .LO ( optlc_net_935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_967 ( .LO ( optlc_net_956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_977 ( .LO ( optlc_net_965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_982 ( .LO ( optlc_net_970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_990 ( .LO ( optlc_net_977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_996 ( .LO ( optlc_net_983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1003 ( .LO ( optlc_net_990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1005 ( .LO ( optlc_net_992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1009 ( .LO ( optlc_net_996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1011 ( .LO ( optlc_net_998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1012 ( .LO ( optlc_net_999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_1000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1014 ( .LO ( optlc_net_1001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1015 ( .LO ( optlc_net_1002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1016 ( .LO ( optlc_net_1003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1017 ( .LO ( optlc_net_1004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1018 ( .LO ( optlc_net_1005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1019 ( .LO ( optlc_net_1006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1020 ( .LO ( optlc_net_1007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1021 ( .LO ( optlc_net_1008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1022 ( .LO ( optlc_net_1009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1023 ( .LO ( optlc_net_1010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1024 ( .LO ( optlc_net_1011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1025 ( .LO ( optlc_net_1012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1026 ( .LO ( optlc_net_1013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1027 ( .LO ( optlc_net_1014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1028 ( .LO ( optlc_net_1015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1029 ( .LO ( optlc_net_1016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1030 ( .LO ( optlc_net_1017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1031 ( .LO ( optlc_net_1018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1032 ( .LO ( optlc_net_1019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1033 ( .LO ( optlc_net_1020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1034 ( .LO ( optlc_net_1021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1036 ( .LO ( optlc_net_1022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1037 ( .LO ( optlc_net_1023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1038 ( .LO ( optlc_net_1024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1039 ( .LO ( optlc_net_1025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1040 ( .LO ( optlc_net_1026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1041 ( .LO ( optlc_net_1027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1043 ( .LO ( optlc_net_1028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1044 ( .LO ( optlc_net_1029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1045 ( .LO ( optlc_net_1030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1046 ( .LO ( optlc_net_1031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1047 ( .LO ( optlc_net_1032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1048 ( .LO ( optlc_net_1033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1049 ( .LO ( optlc_net_1034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1050 ( .LO ( optlc_net_1035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1051 ( .LO ( optlc_net_1036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1053 ( .LO ( optlc_net_1037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1054 ( .LO ( optlc_net_1038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1055 ( .LO ( optlc_net_1039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1056 ( .LO ( optlc_net_1040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1057 ( .LO ( optlc_net_1041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1058 ( .LO ( optlc_net_1042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1059 ( .LO ( optlc_net_1043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1060 ( .LO ( optlc_net_1044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1061 ( .LO ( optlc_net_1045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1062 ( .LO ( optlc_net_1046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1063 ( .LO ( optlc_net_1047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1064 ( .LO ( optlc_net_1048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1066 ( .LO ( optlc_net_1049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1067 ( .LO ( optlc_net_1050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1069 ( .LO ( optlc_net_1051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1070 ( .LO ( optlc_net_1052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1071 ( .LO ( optlc_net_1053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1073 ( .LO ( optlc_net_1054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1074 ( .LO ( optlc_net_1055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1075 ( .LO ( optlc_net_1056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1076 ( .LO ( optlc_net_1057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1077 ( .LO ( optlc_net_1058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1078 ( .LO ( optlc_net_1059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1079 ( .LO ( optlc_net_1060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1081 ( .LO ( optlc_net_1061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1082 ( .LO ( optlc_net_1062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1083 ( .LO ( optlc_net_1063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1084 ( .LO ( optlc_net_1064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1086 ( .LO ( optlc_net_1065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1088 ( .LO ( optlc_net_1066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1089 ( .LO ( optlc_net_1067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1090 ( .LO ( optlc_net_1068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1092 ( .LO ( optlc_net_1069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1093 ( .LO ( optlc_net_1070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1095 ( .LO ( optlc_net_1071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1096 ( .LO ( optlc_net_1072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1097 ( .LO ( optlc_net_1073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1098 ( .LO ( optlc_net_1074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1099 ( .LO ( optlc_net_1075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1100 ( .LO ( optlc_net_1076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1101 ( .LO ( optlc_net_1077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1102 ( .LO ( optlc_net_1078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1103 ( .LO ( optlc_net_1079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1104 ( .LO ( optlc_net_1080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1105 ( .LO ( optlc_net_1081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1106 ( .LO ( optlc_net_1082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1107 ( .LO ( optlc_net_1083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1109 ( .LO ( optlc_net_1084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1111 ( .LO ( optlc_net_1085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1112 ( .LO ( optlc_net_1086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1113 ( .LO ( optlc_net_1087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1114 ( .LO ( optlc_net_1088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1115 ( .LO ( optlc_net_1089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1116 ( .LO ( optlc_net_1090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1117 ( .LO ( optlc_net_1091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1119 ( .LO ( optlc_net_1092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1121 ( .LO ( optlc_net_1093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1123 ( .LO ( optlc_net_1094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1124 ( .LO ( optlc_net_1095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1126 ( .LO ( optlc_net_1096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1127 ( .LO ( optlc_net_1097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1128 ( .LO ( optlc_net_1098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1129 ( .LO ( optlc_net_1099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1131 ( .LO ( optlc_net_1100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1132 ( .LO ( optlc_net_1101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1133 ( .LO ( optlc_net_1102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1134 ( .LO ( optlc_net_1103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1136 ( .LO ( optlc_net_1104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1137 ( .LO ( optlc_net_1105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1138 ( .LO ( optlc_net_1106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1139 ( .LO ( optlc_net_1107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1141 ( .LO ( optlc_net_1108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1142 ( .LO ( optlc_net_1109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1143 ( .LO ( optlc_net_1110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1145 ( .LO ( optlc_net_1111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1147 ( .LO ( optlc_net_1112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1148 ( .LO ( optlc_net_1113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1149 ( .LO ( optlc_net_1114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1150 ( .LO ( optlc_net_1115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1151 ( .LO ( optlc_net_1116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1152 ( .LO ( optlc_net_1117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1153 ( .LO ( optlc_net_1118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1155 ( .LO ( optlc_net_1119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1156 ( .LO ( optlc_net_1120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1157 ( .LO ( optlc_net_1121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1159 ( .LO ( optlc_net_1122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1160 ( .LO ( optlc_net_1123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1162 ( .LO ( optlc_net_1124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1163 ( .LO ( optlc_net_1125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1164 ( .LO ( optlc_net_1126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1165 ( .LO ( optlc_net_1127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1167 ( .LO ( optlc_net_1128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1168 ( .LO ( optlc_net_1129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1170 ( .LO ( optlc_net_1130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1171 ( .LO ( optlc_net_1131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1172 ( .LO ( optlc_net_1132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1173 ( .LO ( optlc_net_1133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1175 ( .LO ( optlc_net_1134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1176 ( .LO ( optlc_net_1135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1177 ( .LO ( optlc_net_1136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1178 ( .LO ( optlc_net_1137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1179 ( .LO ( optlc_net_1138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1180 ( .LO ( optlc_net_1139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1181 ( .LO ( optlc_net_1140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1182 ( .LO ( optlc_net_1141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1183 ( .LO ( optlc_net_1142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1184 ( .LO ( optlc_net_1143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1185 ( .LO ( optlc_net_1144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1186 ( .LO ( optlc_net_1145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1187 ( .LO ( optlc_net_1146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1188 ( .LO ( optlc_net_1147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1189 ( .LO ( optlc_net_1148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1190 ( .LO ( optlc_net_1149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1192 ( .LO ( optlc_net_1150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1193 ( .LO ( optlc_net_1151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1194 ( .LO ( optlc_net_1152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1196 ( .LO ( optlc_net_1153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1197 ( .LO ( optlc_net_1154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1198 ( .LO ( optlc_net_1155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1199 ( .LO ( optlc_net_1156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1201 ( .LO ( optlc_net_1157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1203 ( .LO ( optlc_net_1158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1204 ( .LO ( optlc_net_1159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1205 ( .LO ( optlc_net_1160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1206 ( .LO ( optlc_net_1161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1207 ( .LO ( optlc_net_1162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1208 ( .LO ( optlc_net_1163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1209 ( .LO ( optlc_net_1164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1210 ( .LO ( optlc_net_1165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1212 ( .LO ( optlc_net_1166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1213 ( .LO ( optlc_net_1167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1214 ( .LO ( optlc_net_1168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1216 ( .LO ( optlc_net_1169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1217 ( .LO ( optlc_net_1170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1218 ( .LO ( optlc_net_1171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1219 ( .LO ( optlc_net_1172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1220 ( .LO ( optlc_net_1173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1222 ( .LO ( optlc_net_1174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1223 ( .LO ( optlc_net_1175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1224 ( .LO ( optlc_net_1176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1225 ( .LO ( optlc_net_1177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1226 ( .LO ( optlc_net_1178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1227 ( .LO ( optlc_net_1179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1228 ( .LO ( optlc_net_1180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1229 ( .LO ( optlc_net_1181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1230 ( .LO ( optlc_net_1182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1231 ( .LO ( optlc_net_1183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1233 ( .LO ( optlc_net_1184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1234 ( .LO ( optlc_net_1185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1235 ( .LO ( optlc_net_1186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1236 ( .LO ( optlc_net_1187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1237 ( .LO ( optlc_net_1188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1239 ( .LO ( optlc_net_1189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1240 ( .LO ( optlc_net_1190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1241 ( .LO ( optlc_net_1191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1243 ( .LO ( optlc_net_1192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1245 ( .LO ( optlc_net_1193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1246 ( .LO ( optlc_net_1194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1247 ( .LO ( optlc_net_1195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1249 ( .LO ( optlc_net_1196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1250 ( .LO ( optlc_net_1197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1251 ( .LO ( optlc_net_1198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1252 ( .LO ( optlc_net_1199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1254 ( .LO ( optlc_net_1200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1256 ( .LO ( optlc_net_1201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1257 ( .LO ( optlc_net_1202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1259 ( .LO ( optlc_net_1203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1260 ( .LO ( optlc_net_1204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1262 ( .LO ( optlc_net_1205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1263 ( .LO ( optlc_net_1206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1265 ( .LO ( optlc_net_1207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1266 ( .LO ( optlc_net_1208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1267 ( .LO ( optlc_net_1209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1269 ( .LO ( optlc_net_1210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1271 ( .LO ( optlc_net_1211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1273 ( .LO ( optlc_net_1212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1275 ( .LO ( optlc_net_1213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1277 ( .LO ( optlc_net_1214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1279 ( .LO ( optlc_net_1215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1280 ( .LO ( optlc_net_1216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1282 ( .LO ( optlc_net_1217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1284 ( .LO ( optlc_net_1218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1285 ( .LO ( optlc_net_1219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1286 ( .LO ( optlc_net_1220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1287 ( .LO ( optlc_net_1221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1288 ( .LO ( optlc_net_1222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1289 ( .LO ( optlc_net_1223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1290 ( .LO ( optlc_net_1224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1292 ( .LO ( optlc_net_1225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1293 ( .LO ( optlc_net_1226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1294 ( .LO ( optlc_net_1227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1295 ( .LO ( optlc_net_1228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1297 ( .LO ( optlc_net_1229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1299 ( .LO ( optlc_net_1230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1301 ( .LO ( optlc_net_1231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1302 ( .LO ( optlc_net_1232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1304 ( .LO ( optlc_net_1233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1306 ( .LO ( optlc_net_1234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1307 ( .LO ( optlc_net_1235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1308 ( .LO ( optlc_net_1236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1310 ( .LO ( optlc_net_1237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1312 ( .LO ( optlc_net_1238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1314 ( .LO ( optlc_net_1239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1316 ( .LO ( optlc_net_1240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1317 ( .LO ( optlc_net_1241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1318 ( .LO ( optlc_net_1242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1320 ( .LO ( optlc_net_1243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1321 ( .LO ( optlc_net_1244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1323 ( .LO ( optlc_net_1245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1324 ( .LO ( optlc_net_1246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1325 ( .LO ( optlc_net_1247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1327 ( .LO ( optlc_net_1248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1329 ( .LO ( optlc_net_1249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1330 ( .LO ( optlc_net_1250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1331 ( .LO ( optlc_net_1251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1332 ( .LO ( optlc_net_1252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1334 ( .LO ( optlc_net_1253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1335 ( .LO ( optlc_net_1254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1336 ( .LO ( optlc_net_1255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1338 ( .LO ( optlc_net_1256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1339 ( .LO ( optlc_net_1257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1340 ( .LO ( optlc_net_1258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1342 ( .LO ( optlc_net_1259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1344 ( .LO ( optlc_net_1260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1345 ( .LO ( optlc_net_1261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1346 ( .LO ( optlc_net_1262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1347 ( .LO ( optlc_net_1263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1349 ( .LO ( optlc_net_1264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1351 ( .LO ( optlc_net_1265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1353 ( .LO ( optlc_net_1266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1354 ( .LO ( optlc_net_1267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1356 ( .LO ( optlc_net_1268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1357 ( .LO ( optlc_net_1269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1359 ( .LO ( optlc_net_1270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1360 ( .LO ( optlc_net_1271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1362 ( .LO ( optlc_net_1272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1363 ( .LO ( optlc_net_1273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1365 ( .LO ( optlc_net_1274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1367 ( .LO ( optlc_net_1275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1368 ( .LO ( optlc_net_1276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1369 ( .LO ( optlc_net_1277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1371 ( .LO ( optlc_net_1278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1372 ( .LO ( optlc_net_1279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1374 ( .LO ( optlc_net_1280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1375 ( .LO ( optlc_net_1281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1376 ( .LO ( optlc_net_1282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1377 ( .LO ( optlc_net_1283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1379 ( .LO ( optlc_net_1284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1380 ( .LO ( optlc_net_1285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1381 ( .LO ( optlc_net_1286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1382 ( .LO ( optlc_net_1287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1384 ( .LO ( optlc_net_1288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1385 ( .LO ( optlc_net_1289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1386 ( .LO ( optlc_net_1290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1387 ( .LO ( optlc_net_1291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1388 ( .LO ( optlc_net_1292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1389 ( .LO ( optlc_net_1293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1390 ( .LO ( optlc_net_1294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1391 ( .LO ( optlc_net_1295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1392 ( .LO ( optlc_net_1296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1393 ( .LO ( optlc_net_1297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1395 ( .LO ( optlc_net_1298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1396 ( .LO ( optlc_net_1299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1398 ( .LO ( optlc_net_1300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1399 ( .LO ( optlc_net_1301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1400 ( .LO ( optlc_net_1302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1402 ( .LO ( optlc_net_1303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1403 ( .LO ( optlc_net_1304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1405 ( .LO ( optlc_net_1305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1406 ( .LO ( optlc_net_1306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1408 ( .LO ( optlc_net_1307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1409 ( .LO ( optlc_net_1308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1410 ( .LO ( optlc_net_1309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1411 ( .LO ( optlc_net_1310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1412 ( .LO ( optlc_net_1311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1413 ( .LO ( optlc_net_1312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1414 ( .LO ( optlc_net_1313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1416 ( .LO ( optlc_net_1314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1417 ( .LO ( optlc_net_1315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1418 ( .LO ( optlc_net_1316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1420 ( .LO ( optlc_net_1317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1422 ( .LO ( optlc_net_1318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1423 ( .LO ( optlc_net_1319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1425 ( .LO ( optlc_net_1320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1427 ( .LO ( optlc_net_1321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1429 ( .LO ( optlc_net_1322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1431 ( .LO ( optlc_net_1323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1432 ( .LO ( optlc_net_1324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1433 ( .LO ( optlc_net_1325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1435 ( .LO ( optlc_net_1326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1437 ( .LO ( optlc_net_1327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1438 ( .LO ( optlc_net_1328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1439 ( .LO ( optlc_net_1329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1440 ( .LO ( optlc_net_1330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1441 ( .LO ( optlc_net_1331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1443 ( .LO ( optlc_net_1332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1445 ( .LO ( optlc_net_1333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1447 ( .LO ( optlc_net_1334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1449 ( .LO ( optlc_net_1335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1450 ( .LO ( optlc_net_1336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1451 ( .LO ( optlc_net_1337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1453 ( .LO ( optlc_net_1338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1455 ( .LO ( optlc_net_1339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1457 ( .LO ( optlc_net_1340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1459 ( .LO ( optlc_net_1341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1461 ( .LO ( optlc_net_1342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1466 ( .LO ( optlc_net_1346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1468 ( .LO ( optlc_net_1347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1470 ( .LO ( optlc_net_1348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1473 ( .LO ( optlc_net_1350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1475 ( .LO ( optlc_net_1351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1476 ( .LO ( optlc_net_1352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1477 ( .LO ( optlc_net_1353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1478 ( .LO ( optlc_net_1354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1479 ( .LO ( optlc_net_1355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1481 ( .LO ( optlc_net_1356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1486 ( .LO ( optlc_net_1359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1487 ( .LO ( optlc_net_1360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1492 ( .LO ( optlc_net_1363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1493 ( .LO ( optlc_net_1364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1494 ( .LO ( optlc_net_1365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1495 ( .LO ( optlc_net_1366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1496 ( .LO ( optlc_net_1367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1497 ( .LO ( optlc_net_1368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1498 ( .LO ( optlc_net_1369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1499 ( .LO ( optlc_net_1370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1501 ( .LO ( optlc_net_1371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1503 ( .LO ( optlc_net_1372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1504 ( .LO ( optlc_net_1373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1505 ( .LO ( optlc_net_1374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1506 ( .LO ( optlc_net_1375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1508 ( .LO ( optlc_net_1376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1509 ( .LO ( optlc_net_1377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1511 ( .LO ( optlc_net_1378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1513 ( .LO ( optlc_net_1379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1514 ( .LO ( optlc_net_1380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1516 ( .LO ( optlc_net_1381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1518 ( .LO ( optlc_net_1382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1519 ( .LO ( optlc_net_1383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1521 ( .LO ( optlc_net_1384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1522 ( .LO ( optlc_net_1385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1523 ( .LO ( optlc_net_1386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1525 ( .LO ( optlc_net_1387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1527 ( .LO ( optlc_net_1388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1528 ( .LO ( optlc_net_1389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1529 ( .LO ( optlc_net_1390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1531 ( .LO ( optlc_net_1391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1533 ( .LO ( optlc_net_1392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1534 ( .LO ( optlc_net_1393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1535 ( .LO ( optlc_net_1394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1537 ( .LO ( optlc_net_1395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1538 ( .LO ( optlc_net_1396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1539 ( .LO ( optlc_net_1397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1540 ( .LO ( optlc_net_1398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1541 ( .LO ( optlc_net_1399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1542 ( .LO ( optlc_net_1400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1544 ( .LO ( optlc_net_1401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1545 ( .LO ( optlc_net_1402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1546 ( .LO ( optlc_net_1403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1548 ( .LO ( optlc_net_1404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1549 ( .LO ( optlc_net_1405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1551 ( .LO ( optlc_net_1406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1552 ( .LO ( optlc_net_1407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1553 ( .LO ( optlc_net_1408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1554 ( .LO ( optlc_net_1409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1555 ( .LO ( optlc_net_1410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1557 ( .LO ( optlc_net_1411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1558 ( .LO ( optlc_net_1412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1559 ( .LO ( optlc_net_1413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1560 ( .LO ( optlc_net_1414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1561 ( .LO ( optlc_net_1415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1562 ( .LO ( optlc_net_1416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1563 ( .LO ( optlc_net_1417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1564 ( .LO ( optlc_net_1418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1565 ( .LO ( optlc_net_1419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1566 ( .LO ( optlc_net_1420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1568 ( .LO ( optlc_net_1421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1569 ( .LO ( optlc_net_1422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1570 ( .LO ( optlc_net_1423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1572 ( .LO ( optlc_net_1424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1573 ( .LO ( optlc_net_1425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1575 ( .LO ( optlc_net_1426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1577 ( .LO ( optlc_net_1427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1578 ( .LO ( optlc_net_1428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1580 ( .LO ( optlc_net_1429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1581 ( .LO ( optlc_net_1430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1582 ( .LO ( optlc_net_1431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1583 ( .LO ( optlc_net_1432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1584 ( .LO ( optlc_net_1433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1586 ( .LO ( optlc_net_1434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1587 ( .LO ( optlc_net_1435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1589 ( .LO ( optlc_net_1436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1590 ( .LO ( optlc_net_1437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1592 ( .LO ( optlc_net_1438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1593 ( .LO ( optlc_net_1439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1594 ( .LO ( optlc_net_1440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1596 ( .LO ( optlc_net_1441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1598 ( .LO ( optlc_net_1442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1600 ( .LO ( optlc_net_1443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1601 ( .LO ( optlc_net_1444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1602 ( .LO ( optlc_net_1445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1604 ( .LO ( optlc_net_1446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1605 ( .LO ( optlc_net_1447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1606 ( .LO ( optlc_net_1448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1608 ( .LO ( optlc_net_1449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1609 ( .LO ( optlc_net_1450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1610 ( .LO ( optlc_net_1451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1611 ( .LO ( optlc_net_1452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1612 ( .LO ( optlc_net_1453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1613 ( .LO ( optlc_net_1454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1614 ( .LO ( optlc_net_1455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1616 ( .LO ( optlc_net_1456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1617 ( .LO ( optlc_net_1457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1618 ( .LO ( optlc_net_1458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1619 ( .LO ( optlc_net_1459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1620 ( .LO ( optlc_net_1460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1621 ( .LO ( optlc_net_1461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1622 ( .LO ( optlc_net_1462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1623 ( .LO ( optlc_net_1463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1625 ( .LO ( optlc_net_1464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1626 ( .LO ( optlc_net_1465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1628 ( .LO ( optlc_net_1466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1629 ( .LO ( optlc_net_1467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1630 ( .LO ( optlc_net_1468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1631 ( .LO ( optlc_net_1469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1632 ( .LO ( optlc_net_1470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1634 ( .LO ( optlc_net_1471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1636 ( .LO ( optlc_net_1472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1638 ( .LO ( optlc_net_1473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1639 ( .LO ( optlc_net_1474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1640 ( .LO ( optlc_net_1475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1642 ( .LO ( optlc_net_1476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1643 ( .LO ( optlc_net_1477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1644 ( .LO ( optlc_net_1478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1645 ( .LO ( optlc_net_1479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1647 ( .LO ( optlc_net_1480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1649 ( .LO ( optlc_net_1481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1651 ( .LO ( optlc_net_1482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1652 ( .LO ( optlc_net_1483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1653 ( .LO ( optlc_net_1484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1654 ( .LO ( optlc_net_1485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1655 ( .LO ( optlc_net_1486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1656 ( .LO ( optlc_net_1487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1657 ( .LO ( optlc_net_1488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1658 ( .LO ( optlc_net_1489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1659 ( .LO ( optlc_net_1490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1660 ( .LO ( optlc_net_1491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1661 ( .LO ( optlc_net_1492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1662 ( .LO ( optlc_net_1493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1663 ( .LO ( optlc_net_1494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1664 ( .LO ( optlc_net_1495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1665 ( .LO ( optlc_net_1496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1666 ( .LO ( optlc_net_1497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1667 ( .LO ( optlc_net_1498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1668 ( .LO ( optlc_net_1499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1669 ( .LO ( optlc_net_1500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1670 ( .LO ( optlc_net_1501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1671 ( .LO ( optlc_net_1502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1672 ( .LO ( optlc_net_1503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1673 ( .LO ( optlc_net_1504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1674 ( .LO ( optlc_net_1505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1675 ( .LO ( optlc_net_1506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1676 ( .LO ( optlc_net_1507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1677 ( .LO ( optlc_net_1508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1678 ( .LO ( optlc_net_1509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1679 ( .LO ( optlc_net_1510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1680 ( .LO ( optlc_net_1511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1681 ( .LO ( optlc_net_1512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1682 ( .LO ( optlc_net_1513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1683 ( .LO ( optlc_net_1514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1684 ( .LO ( optlc_net_1515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1685 ( .LO ( optlc_net_1516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1686 ( .LO ( optlc_net_1517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1687 ( .LO ( optlc_net_1518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1688 ( .LO ( optlc_net_1519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1689 ( .LO ( optlc_net_1520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1690 ( .LO ( optlc_net_1521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1691 ( .LO ( optlc_net_1522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1692 ( .LO ( optlc_net_1523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1693 ( .LO ( optlc_net_1524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1694 ( .LO ( optlc_net_1525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1695 ( .LO ( optlc_net_1526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1696 ( .LO ( optlc_net_1527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1697 ( .LO ( optlc_net_1528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1698 ( .LO ( optlc_net_1529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1699 ( .LO ( optlc_net_1530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1700 ( .LO ( optlc_net_1531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1701 ( .LO ( optlc_net_1532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1702 ( .LO ( optlc_net_1533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1703 ( .LO ( optlc_net_1534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1704 ( .LO ( optlc_net_1535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1705 ( .LO ( optlc_net_1536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1706 ( .LO ( optlc_net_1537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1707 ( .LO ( optlc_net_1538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1708 ( .LO ( optlc_net_1539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1709 ( .LO ( optlc_net_1540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1710 ( .LO ( optlc_net_1541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1711 ( .LO ( optlc_net_1542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1712 ( .LO ( optlc_net_1543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1713 ( .LO ( optlc_net_1544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1714 ( .LO ( optlc_net_1545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1715 ( .LO ( optlc_net_1546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1716 ( .LO ( optlc_net_1547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1717 ( .LO ( optlc_net_1548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1718 ( .LO ( optlc_net_1549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1719 ( .LO ( optlc_net_1550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1720 ( .LO ( optlc_net_1551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1721 ( .LO ( optlc_net_1552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1722 ( .LO ( optlc_net_1553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1723 ( .LO ( optlc_net_1554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1724 ( .LO ( optlc_net_1555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1725 ( .LO ( optlc_net_1556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1726 ( .LO ( optlc_net_1557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1727 ( .LO ( optlc_net_1558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1728 ( .LO ( optlc_net_1559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1729 ( .LO ( optlc_net_1560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1730 ( .LO ( optlc_net_1561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1731 ( .LO ( optlc_net_1562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1732 ( .LO ( optlc_net_1563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1733 ( .LO ( optlc_net_1564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1734 ( .LO ( optlc_net_1565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1735 ( .LO ( optlc_net_1566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1736 ( .LO ( optlc_net_1567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1737 ( .LO ( optlc_net_1568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1738 ( .LO ( optlc_net_1569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1739 ( .LO ( optlc_net_1570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1740 ( .LO ( optlc_net_1571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1741 ( .LO ( optlc_net_1572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1742 ( .LO ( optlc_net_1573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1743 ( .LO ( optlc_net_1574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1744 ( .LO ( optlc_net_1575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1745 ( .LO ( optlc_net_1576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1746 ( .LO ( optlc_net_1577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1747 ( .LO ( optlc_net_1578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1748 ( .LO ( optlc_net_1579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1749 ( .LO ( optlc_net_1580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1750 ( .LO ( optlc_net_1581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1751 ( .LO ( optlc_net_1582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1752 ( .LO ( optlc_net_1583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1753 ( .LO ( optlc_net_1584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1754 ( .LO ( optlc_net_1585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1755 ( .LO ( optlc_net_1586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1756 ( .LO ( optlc_net_1587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1757 ( .LO ( optlc_net_1588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1758 ( .LO ( optlc_net_1589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1759 ( .LO ( optlc_net_1590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1760 ( .LO ( optlc_net_1591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1761 ( .LO ( optlc_net_1592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1762 ( .LO ( optlc_net_1593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1763 ( .LO ( optlc_net_1594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1764 ( .LO ( optlc_net_1595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1765 ( .LO ( optlc_net_1596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1766 ( .LO ( optlc_net_1597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1767 ( .LO ( optlc_net_1598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1768 ( .LO ( optlc_net_1599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1769 ( .LO ( optlc_net_1600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1770 ( .LO ( optlc_net_1601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1771 ( .LO ( optlc_net_1602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1772 ( .LO ( optlc_net_1603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1773 ( .LO ( optlc_net_1604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1774 ( .LO ( optlc_net_1605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1775 ( .LO ( optlc_net_1606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1776 ( .LO ( optlc_net_1607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1777 ( .LO ( optlc_net_1608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1778 ( .LO ( optlc_net_1609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1779 ( .LO ( optlc_net_1610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1780 ( .LO ( optlc_net_1611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1781 ( .LO ( optlc_net_1612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1782 ( .LO ( optlc_net_1613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1783 ( .LO ( optlc_net_1614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1784 ( .LO ( optlc_net_1615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1785 ( .LO ( optlc_net_1616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1787 ( .LO ( optlc_net_1617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1788 ( .LO ( optlc_net_1618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1789 ( .LO ( optlc_net_1619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1790 ( .LO ( optlc_net_1620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1791 ( .LO ( optlc_net_1621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1792 ( .LO ( optlc_net_1622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1793 ( .LO ( optlc_net_1623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1794 ( .LO ( optlc_net_1624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1795 ( .LO ( optlc_net_1625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1796 ( .LO ( optlc_net_1626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1797 ( .LO ( optlc_net_1627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1798 ( .LO ( optlc_net_1628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1799 ( .LO ( optlc_net_1629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1800 ( .LO ( optlc_net_1630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1801 ( .LO ( optlc_net_1631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1802 ( .LO ( optlc_net_1632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1803 ( .LO ( optlc_net_1633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1804 ( .LO ( optlc_net_1634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1805 ( .LO ( optlc_net_1635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1806 ( .LO ( optlc_net_1636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1807 ( .LO ( optlc_net_1637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1808 ( .LO ( optlc_net_1638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1809 ( .LO ( optlc_net_1639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1810 ( .LO ( optlc_net_1640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1811 ( .LO ( optlc_net_1641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1812 ( .LO ( optlc_net_1642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1813 ( .LO ( optlc_net_1643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1814 ( .LO ( optlc_net_1644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1815 ( .LO ( optlc_net_1645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1816 ( .LO ( optlc_net_1646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1817 ( .LO ( optlc_net_1647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1818 ( .LO ( optlc_net_1648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1819 ( .LO ( optlc_net_1649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1821 ( .LO ( optlc_net_1650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1822 ( .LO ( optlc_net_1651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1823 ( .LO ( optlc_net_1652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1824 ( .LO ( optlc_net_1653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1825 ( .LO ( optlc_net_1654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1826 ( .LO ( optlc_net_1655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1827 ( .LO ( optlc_net_1656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1828 ( .LO ( optlc_net_1657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1829 ( .LO ( optlc_net_1658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1830 ( .LO ( optlc_net_1659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1831 ( .LO ( optlc_net_1660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1832 ( .LO ( optlc_net_1661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1833 ( .LO ( optlc_net_1662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1834 ( .LO ( optlc_net_1663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1835 ( .LO ( optlc_net_1664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1836 ( .LO ( optlc_net_1665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1837 ( .LO ( optlc_net_1666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1838 ( .LO ( optlc_net_1667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1839 ( .LO ( optlc_net_1668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1840 ( .LO ( optlc_net_1669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1842 ( .LO ( optlc_net_1670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1843 ( .LO ( optlc_net_1671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1844 ( .LO ( optlc_net_1672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1845 ( .LO ( optlc_net_1673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1846 ( .LO ( optlc_net_1674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1847 ( .LO ( optlc_net_1675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1849 ( .LO ( optlc_net_1676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1850 ( .LO ( optlc_net_1677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1851 ( .LO ( optlc_net_1678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1852 ( .LO ( optlc_net_1679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1853 ( .LO ( optlc_net_1680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1854 ( .LO ( optlc_net_1681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1855 ( .LO ( optlc_net_1682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1856 ( .LO ( optlc_net_1683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1857 ( .LO ( optlc_net_1684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1859 ( .LO ( optlc_net_1685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1860 ( .LO ( optlc_net_1686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1861 ( .LO ( optlc_net_1687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1862 ( .LO ( optlc_net_1688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1863 ( .LO ( optlc_net_1689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1864 ( .LO ( optlc_net_1690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1865 ( .LO ( optlc_net_1691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1866 ( .LO ( optlc_net_1692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1867 ( .LO ( optlc_net_1693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1868 ( .LO ( optlc_net_1694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1869 ( .LO ( optlc_net_1695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1870 ( .LO ( optlc_net_1696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1871 ( .LO ( optlc_net_1697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1872 ( .LO ( optlc_net_1698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1873 ( .LO ( optlc_net_1699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1875 ( .LO ( optlc_net_1700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1876 ( .LO ( optlc_net_1701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1877 ( .LO ( optlc_net_1702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1878 ( .LO ( optlc_net_1703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1879 ( .LO ( optlc_net_1704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1880 ( .LO ( optlc_net_1705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1881 ( .LO ( optlc_net_1706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1882 ( .LO ( optlc_net_1707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1884 ( .LO ( optlc_net_1708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1885 ( .LO ( optlc_net_1709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1886 ( .LO ( optlc_net_1710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1887 ( .LO ( optlc_net_1711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1888 ( .LO ( optlc_net_1712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1889 ( .LO ( optlc_net_1713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1891 ( .LO ( optlc_net_1714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1893 ( .LO ( optlc_net_1715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1894 ( .LO ( optlc_net_1716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1895 ( .LO ( optlc_net_1717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1896 ( .LO ( optlc_net_1718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1897 ( .LO ( optlc_net_1719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1898 ( .LO ( optlc_net_1720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1899 ( .LO ( optlc_net_1721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1901 ( .LO ( optlc_net_1722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1903 ( .LO ( optlc_net_1723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1904 ( .LO ( optlc_net_1724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1906 ( .LO ( optlc_net_1725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1907 ( .LO ( optlc_net_1726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1908 ( .LO ( optlc_net_1727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1909 ( .LO ( optlc_net_1728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1911 ( .LO ( optlc_net_1729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1912 ( .LO ( optlc_net_1730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1913 ( .LO ( optlc_net_1731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1914 ( .LO ( optlc_net_1732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1915 ( .LO ( optlc_net_1733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1916 ( .LO ( optlc_net_1734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1917 ( .LO ( optlc_net_1735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1918 ( .LO ( optlc_net_1736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1919 ( .LO ( optlc_net_1737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1921 ( .LO ( optlc_net_1738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1922 ( .LO ( optlc_net_1739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1923 ( .LO ( optlc_net_1740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1924 ( .LO ( optlc_net_1741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1926 ( .LO ( optlc_net_1742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1928 ( .LO ( optlc_net_1743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1929 ( .LO ( optlc_net_1744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1931 ( .LO ( optlc_net_1745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1932 ( .LO ( optlc_net_1746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1933 ( .LO ( optlc_net_1747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1934 ( .LO ( optlc_net_1748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1935 ( .LO ( optlc_net_1749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1936 ( .LO ( optlc_net_1750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1937 ( .LO ( optlc_net_1751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1938 ( .LO ( optlc_net_1752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1939 ( .LO ( optlc_net_1753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1941 ( .LO ( optlc_net_1754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1942 ( .LO ( optlc_net_1755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1944 ( .LO ( optlc_net_1756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1945 ( .LO ( optlc_net_1757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1946 ( .LO ( optlc_net_1758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1948 ( .LO ( optlc_net_1759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1949 ( .LO ( optlc_net_1760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1950 ( .LO ( optlc_net_1761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1951 ( .LO ( optlc_net_1762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1953 ( .LO ( optlc_net_1763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1955 ( .LO ( optlc_net_1764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1956 ( .LO ( optlc_net_1765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1957 ( .LO ( optlc_net_1766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1959 ( .LO ( optlc_net_1767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1960 ( .LO ( optlc_net_1768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1961 ( .LO ( optlc_net_1769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1962 ( .LO ( optlc_net_1770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1963 ( .LO ( optlc_net_1771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1965 ( .LO ( optlc_net_1772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1966 ( .LO ( optlc_net_1773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1967 ( .LO ( optlc_net_1774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1968 ( .LO ( optlc_net_1775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1970 ( .LO ( optlc_net_1776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1971 ( .LO ( optlc_net_1777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1972 ( .LO ( optlc_net_1778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1974 ( .LO ( optlc_net_1779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1975 ( .LO ( optlc_net_1780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1977 ( .LO ( optlc_net_1781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1979 ( .LO ( optlc_net_1782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1980 ( .LO ( optlc_net_1783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1981 ( .LO ( optlc_net_1784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1982 ( .LO ( optlc_net_1785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1983 ( .LO ( optlc_net_1786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1985 ( .LO ( optlc_net_1787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1987 ( .LO ( optlc_net_1788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1988 ( .LO ( optlc_net_1789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1989 ( .LO ( optlc_net_1790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1990 ( .LO ( optlc_net_1791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1991 ( .LO ( optlc_net_1792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1993 ( .LO ( optlc_net_1793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1995 ( .LO ( optlc_net_1794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1996 ( .LO ( optlc_net_1795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_1998 ( .LO ( optlc_net_1796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2000 ( .LO ( optlc_net_1797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2001 ( .LO ( optlc_net_1798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2002 ( .LO ( optlc_net_1799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2003 ( .LO ( optlc_net_1800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2005 ( .LO ( optlc_net_1801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2006 ( .LO ( optlc_net_1802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2007 ( .LO ( optlc_net_1803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2008 ( .LO ( optlc_net_1804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2009 ( .LO ( optlc_net_1805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2010 ( .LO ( optlc_net_1806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2011 ( .LO ( optlc_net_1807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2013 ( .LO ( optlc_net_1808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2014 ( .LO ( optlc_net_1809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2015 ( .LO ( optlc_net_1810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2017 ( .LO ( optlc_net_1811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2018 ( .LO ( optlc_net_1812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2019 ( .LO ( optlc_net_1813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2020 ( .LO ( optlc_net_1814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2022 ( .LO ( optlc_net_1815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2023 ( .LO ( optlc_net_1816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2025 ( .LO ( optlc_net_1817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2027 ( .LO ( optlc_net_1818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2028 ( .LO ( optlc_net_1819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2029 ( .LO ( optlc_net_1820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2031 ( .LO ( optlc_net_1821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2032 ( .LO ( optlc_net_1822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2033 ( .LO ( optlc_net_1823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2035 ( .LO ( optlc_net_1824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2036 ( .LO ( optlc_net_1825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2037 ( .LO ( optlc_net_1826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2038 ( .LO ( optlc_net_1827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2039 ( .LO ( optlc_net_1828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2040 ( .LO ( optlc_net_1829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2041 ( .LO ( optlc_net_1830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2043 ( .LO ( optlc_net_1831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2045 ( .LO ( optlc_net_1832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2046 ( .LO ( optlc_net_1833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2047 ( .LO ( optlc_net_1834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2048 ( .LO ( optlc_net_1835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2049 ( .LO ( optlc_net_1836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2050 ( .LO ( optlc_net_1837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2051 ( .LO ( optlc_net_1838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2052 ( .LO ( optlc_net_1839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2053 ( .LO ( optlc_net_1840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2054 ( .LO ( optlc_net_1841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2055 ( .LO ( optlc_net_1842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2056 ( .LO ( optlc_net_1843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2057 ( .LO ( optlc_net_1844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2058 ( .LO ( optlc_net_1845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2059 ( .LO ( optlc_net_1846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2060 ( .LO ( optlc_net_1847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2061 ( .LO ( optlc_net_1848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2062 ( .LO ( optlc_net_1849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2063 ( .LO ( optlc_net_1850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2064 ( .LO ( optlc_net_1851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2065 ( .LO ( optlc_net_1852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2066 ( .LO ( optlc_net_1853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2067 ( .LO ( optlc_net_1854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2068 ( .LO ( optlc_net_1855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2069 ( .LO ( optlc_net_1856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2070 ( .LO ( optlc_net_1857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2071 ( .LO ( optlc_net_1858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2072 ( .LO ( optlc_net_1859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2073 ( .LO ( optlc_net_1860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2075 ( .LO ( optlc_net_1861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2076 ( .LO ( optlc_net_1862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2077 ( .LO ( optlc_net_1863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2079 ( .LO ( optlc_net_1864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2080 ( .LO ( optlc_net_1865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2081 ( .LO ( optlc_net_1866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2082 ( .LO ( optlc_net_1867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2083 ( .LO ( optlc_net_1868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2084 ( .LO ( optlc_net_1869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2085 ( .LO ( optlc_net_1870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2086 ( .LO ( optlc_net_1871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2087 ( .LO ( optlc_net_1872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2089 ( .LO ( optlc_net_1873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2090 ( .LO ( optlc_net_1874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2091 ( .LO ( optlc_net_1875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2092 ( .LO ( optlc_net_1876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2093 ( .LO ( optlc_net_1877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2094 ( .LO ( optlc_net_1878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2095 ( .LO ( optlc_net_1879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2096 ( .LO ( optlc_net_1880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2097 ( .LO ( optlc_net_1881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2098 ( .LO ( optlc_net_1882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2099 ( .LO ( optlc_net_1883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2101 ( .LO ( optlc_net_1884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2102 ( .LO ( optlc_net_1885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2103 ( .LO ( optlc_net_1886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2105 ( .LO ( optlc_net_1887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2106 ( .LO ( optlc_net_1888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2107 ( .LO ( optlc_net_1889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2108 ( .LO ( optlc_net_1890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2109 ( .LO ( optlc_net_1891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2110 ( .LO ( optlc_net_1892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2111 ( .LO ( optlc_net_1893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2112 ( .LO ( optlc_net_1894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2114 ( .LO ( optlc_net_1895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2116 ( .LO ( optlc_net_1896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2117 ( .LO ( optlc_net_1897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2119 ( .LO ( optlc_net_1898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2120 ( .LO ( optlc_net_1899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2121 ( .LO ( optlc_net_1900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2122 ( .LO ( optlc_net_1901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2124 ( .LO ( optlc_net_1902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2125 ( .LO ( optlc_net_1903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2126 ( .LO ( optlc_net_1904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2127 ( .LO ( optlc_net_1905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2129 ( .LO ( optlc_net_1906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2130 ( .LO ( optlc_net_1907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2134 ( .LO ( optlc_net_1910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2138 ( .LO ( optlc_net_1913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2140 ( .LO ( optlc_net_1915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2141 ( .LO ( optlc_net_1916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2142 ( .LO ( optlc_net_1917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2143 ( .LO ( optlc_net_1918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2146 ( .LO ( optlc_net_1920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2147 ( .LO ( optlc_net_1921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2149 ( .LO ( optlc_net_1923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2153 ( .LO ( optlc_net_1927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2154 ( .LO ( optlc_net_1928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2155 ( .LO ( optlc_net_1929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2156 ( .LO ( optlc_net_1930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2157 ( .LO ( optlc_net_1931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2158 ( .LO ( optlc_net_1932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2159 ( .LO ( optlc_net_1933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2160 ( .LO ( optlc_net_1934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2164 ( .LO ( optlc_net_1938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2166 ( .LO ( optlc_net_1940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2168 ( .LO ( optlc_net_1942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2170 ( .LO ( optlc_net_1944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2172 ( .LO ( optlc_net_1946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2174 ( .LO ( optlc_net_1948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2176 ( .LO ( optlc_net_1950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2178 ( .LO ( optlc_net_1952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2183 ( .LO ( optlc_net_1956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2185 ( .LO ( optlc_net_1958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2189 ( .LO ( optlc_net_1962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2191 ( .LO ( optlc_net_1964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2193 ( .LO ( optlc_net_1966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2195 ( .LO ( optlc_net_1968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2197 ( .LO ( optlc_net_1970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2199 ( .LO ( optlc_net_1972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2201 ( .LO ( optlc_net_1974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2203 ( .LO ( optlc_net_1976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2208 ( .LO ( optlc_net_1981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2213 ( .LO ( optlc_net_1986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2215 ( .LO ( optlc_net_1988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_1989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2217 ( .LO ( optlc_net_1990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_1991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2219 ( .LO ( optlc_net_1992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_1993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2221 ( .LO ( optlc_net_1994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_1995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2223 ( .LO ( optlc_net_1996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_1997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_1999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_1998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_1999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2227 ( .LO ( optlc_net_2000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2228 ( .LO ( optlc_net_2001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2229 ( .LO ( optlc_net_2002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2230 ( .LO ( optlc_net_2003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2231 ( .LO ( optlc_net_2004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2232 ( .LO ( optlc_net_2005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_2006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2234 ( .LO ( optlc_net_2007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_2008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_2009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_2010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_2011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_2012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_2013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2241 ( .LO ( optlc_net_2014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_2015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_2016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2244 ( .LO ( optlc_net_2017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2245 ( .LO ( optlc_net_2018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2246 ( .LO ( optlc_net_2019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_2020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_2021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2249 ( .LO ( optlc_net_2022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2250 ( .LO ( optlc_net_2023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2251 ( .LO ( optlc_net_2024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2252 ( .LO ( optlc_net_2025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2253 ( .LO ( optlc_net_2026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2254 ( .LO ( optlc_net_2027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2255 ( .LO ( optlc_net_2028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2256 ( .LO ( optlc_net_2029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2257 ( .LO ( optlc_net_2030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2258 ( .LO ( optlc_net_2031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2259 ( .LO ( optlc_net_2032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2260 ( .LO ( optlc_net_2033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2261 ( .LO ( optlc_net_2034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2262 ( .LO ( optlc_net_2035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2263 ( .LO ( optlc_net_2036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2264 ( .LO ( optlc_net_2037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2265 ( .LO ( optlc_net_2038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2266 ( .LO ( optlc_net_2039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2267 ( .LO ( optlc_net_2040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2268 ( .LO ( optlc_net_2041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2269 ( .LO ( optlc_net_2042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2270 ( .LO ( optlc_net_2043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2271 ( .LO ( optlc_net_2044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2272 ( .LO ( optlc_net_2045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2273 ( .LO ( optlc_net_2046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2274 ( .LO ( optlc_net_2047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2275 ( .LO ( optlc_net_2048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2276 ( .LO ( optlc_net_2049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2277 ( .LO ( optlc_net_2050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2278 ( .LO ( optlc_net_2051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2279 ( .LO ( optlc_net_2052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2280 ( .LO ( optlc_net_2053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2281 ( .LO ( optlc_net_2054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2282 ( .LO ( optlc_net_2055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2283 ( .LO ( optlc_net_2056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2284 ( .LO ( optlc_net_2057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2285 ( .LO ( optlc_net_2058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2286 ( .LO ( optlc_net_2059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2287 ( .LO ( optlc_net_2060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2288 ( .LO ( optlc_net_2061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2289 ( .LO ( optlc_net_2062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2290 ( .LO ( optlc_net_2063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2291 ( .LO ( optlc_net_2064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2292 ( .LO ( optlc_net_2065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2293 ( .LO ( optlc_net_2066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2294 ( .LO ( optlc_net_2067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2295 ( .LO ( optlc_net_2068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2296 ( .LO ( optlc_net_2069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2298 ( .LO ( optlc_net_2070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2299 ( .LO ( optlc_net_2071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2300 ( .LO ( optlc_net_2072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2301 ( .LO ( optlc_net_2073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2302 ( .LO ( optlc_net_2074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2303 ( .LO ( optlc_net_2075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2304 ( .LO ( optlc_net_2076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2305 ( .LO ( optlc_net_2077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2306 ( .LO ( optlc_net_2078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2307 ( .LO ( optlc_net_2079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2308 ( .LO ( optlc_net_2080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2309 ( .LO ( optlc_net_2081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2310 ( .LO ( optlc_net_2082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2311 ( .LO ( optlc_net_2083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2312 ( .LO ( optlc_net_2084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2313 ( .LO ( optlc_net_2085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2314 ( .LO ( optlc_net_2086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2315 ( .LO ( optlc_net_2087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2316 ( .LO ( optlc_net_2088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2317 ( .LO ( optlc_net_2089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2318 ( .LO ( optlc_net_2090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2319 ( .LO ( optlc_net_2091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2321 ( .LO ( optlc_net_2092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2322 ( .LO ( optlc_net_2093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2323 ( .LO ( optlc_net_2094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2324 ( .LO ( optlc_net_2095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2325 ( .LO ( optlc_net_2096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2326 ( .LO ( optlc_net_2097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2327 ( .LO ( optlc_net_2098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2328 ( .LO ( optlc_net_2099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2329 ( .LO ( optlc_net_2100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2331 ( .LO ( optlc_net_2101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2332 ( .LO ( optlc_net_2102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2333 ( .LO ( optlc_net_2103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2334 ( .LO ( optlc_net_2104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2335 ( .LO ( optlc_net_2105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2336 ( .LO ( optlc_net_2106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2337 ( .LO ( optlc_net_2107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2338 ( .LO ( optlc_net_2108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2339 ( .LO ( optlc_net_2109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2340 ( .LO ( optlc_net_2110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2341 ( .LO ( optlc_net_2111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2342 ( .LO ( optlc_net_2112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2344 ( .LO ( optlc_net_2113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2345 ( .LO ( optlc_net_2114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2346 ( .LO ( optlc_net_2115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2347 ( .LO ( optlc_net_2116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2348 ( .LO ( optlc_net_2117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2349 ( .LO ( optlc_net_2118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2350 ( .LO ( optlc_net_2119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2351 ( .LO ( optlc_net_2120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2352 ( .LO ( optlc_net_2121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2354 ( .LO ( optlc_net_2122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2355 ( .LO ( optlc_net_2123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2356 ( .LO ( optlc_net_2124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2357 ( .LO ( optlc_net_2125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2358 ( .LO ( optlc_net_2126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2359 ( .LO ( optlc_net_2127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2360 ( .LO ( optlc_net_2128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2361 ( .LO ( optlc_net_2129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2362 ( .LO ( optlc_net_2130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2363 ( .LO ( optlc_net_2131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2364 ( .LO ( optlc_net_2132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2365 ( .LO ( optlc_net_2133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2366 ( .LO ( optlc_net_2134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2367 ( .LO ( optlc_net_2135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2368 ( .LO ( optlc_net_2136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2369 ( .LO ( optlc_net_2137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2370 ( .LO ( optlc_net_2138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2371 ( .LO ( optlc_net_2139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2372 ( .LO ( optlc_net_2140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2373 ( .LO ( optlc_net_2141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2374 ( .LO ( optlc_net_2142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2375 ( .LO ( optlc_net_2143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2376 ( .LO ( optlc_net_2144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2377 ( .LO ( optlc_net_2145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2378 ( .LO ( optlc_net_2146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2379 ( .LO ( optlc_net_2147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2380 ( .LO ( optlc_net_2148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2381 ( .LO ( optlc_net_2149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2382 ( .LO ( optlc_net_2150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2383 ( .LO ( optlc_net_2151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2384 ( .LO ( optlc_net_2152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2385 ( .LO ( optlc_net_2153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2386 ( .LO ( optlc_net_2154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2387 ( .LO ( optlc_net_2155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2388 ( .LO ( optlc_net_2156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2389 ( .LO ( optlc_net_2157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2391 ( .LO ( optlc_net_2158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2392 ( .LO ( optlc_net_2159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2393 ( .LO ( optlc_net_2160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2395 ( .LO ( optlc_net_2161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2396 ( .LO ( optlc_net_2162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2397 ( .LO ( optlc_net_2163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2398 ( .LO ( optlc_net_2164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2400 ( .LO ( optlc_net_2165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2402 ( .LO ( optlc_net_2166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2403 ( .LO ( optlc_net_2167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2404 ( .LO ( optlc_net_2168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2405 ( .LO ( optlc_net_2169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2407 ( .LO ( optlc_net_2170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2408 ( .LO ( optlc_net_2171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2409 ( .LO ( optlc_net_2172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2410 ( .LO ( optlc_net_2173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2412 ( .LO ( optlc_net_2174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2413 ( .LO ( optlc_net_2175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2414 ( .LO ( optlc_net_2176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2416 ( .LO ( optlc_net_2177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2417 ( .LO ( optlc_net_2178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2418 ( .LO ( optlc_net_2179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2419 ( .LO ( optlc_net_2180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2420 ( .LO ( optlc_net_2181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2421 ( .LO ( optlc_net_2182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2422 ( .LO ( optlc_net_2183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2423 ( .LO ( optlc_net_2184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2424 ( .LO ( optlc_net_2185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2425 ( .LO ( optlc_net_2186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2427 ( .LO ( optlc_net_2187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2428 ( .LO ( optlc_net_2188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2429 ( .LO ( optlc_net_2189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2430 ( .LO ( optlc_net_2190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2431 ( .LO ( optlc_net_2191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2432 ( .LO ( optlc_net_2192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2434 ( .LO ( optlc_net_2193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2436 ( .LO ( optlc_net_2194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2437 ( .LO ( optlc_net_2195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2438 ( .LO ( optlc_net_2196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2439 ( .LO ( optlc_net_2197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2440 ( .LO ( optlc_net_2198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2441 ( .LO ( optlc_net_2199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2442 ( .LO ( optlc_net_2200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2443 ( .LO ( optlc_net_2201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2444 ( .LO ( optlc_net_2202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2445 ( .LO ( optlc_net_2203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2446 ( .LO ( optlc_net_2204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2447 ( .LO ( optlc_net_2205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2448 ( .LO ( optlc_net_2206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2449 ( .LO ( optlc_net_2207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2450 ( .LO ( optlc_net_2208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2451 ( .LO ( optlc_net_2209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2452 ( .LO ( optlc_net_2210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2453 ( .LO ( optlc_net_2211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2454 ( .LO ( optlc_net_2212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2455 ( .LO ( optlc_net_2213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2456 ( .LO ( optlc_net_2214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2457 ( .LO ( optlc_net_2215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2458 ( .LO ( optlc_net_2216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2459 ( .LO ( optlc_net_2217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2460 ( .LO ( optlc_net_2218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2461 ( .LO ( optlc_net_2219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2462 ( .LO ( optlc_net_2220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2463 ( .LO ( optlc_net_2221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2464 ( .LO ( optlc_net_2222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2465 ( .LO ( optlc_net_2223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2466 ( .LO ( optlc_net_2224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2467 ( .LO ( optlc_net_2225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2468 ( .LO ( optlc_net_2226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2469 ( .LO ( optlc_net_2227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2470 ( .LO ( optlc_net_2228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2471 ( .LO ( optlc_net_2229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2472 ( .LO ( optlc_net_2230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2474 ( .LO ( optlc_net_2231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2475 ( .LO ( optlc_net_2232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2476 ( .LO ( optlc_net_2233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2477 ( .LO ( optlc_net_2234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2478 ( .LO ( optlc_net_2235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2479 ( .LO ( optlc_net_2236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2481 ( .LO ( optlc_net_2237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2482 ( .LO ( optlc_net_2238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2483 ( .LO ( optlc_net_2239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2484 ( .LO ( optlc_net_2240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2485 ( .LO ( optlc_net_2241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2486 ( .LO ( optlc_net_2242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2487 ( .LO ( optlc_net_2243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2488 ( .LO ( optlc_net_2244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2489 ( .LO ( optlc_net_2245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2490 ( .LO ( optlc_net_2246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2491 ( .LO ( optlc_net_2247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2492 ( .LO ( optlc_net_2248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2493 ( .LO ( optlc_net_2249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2494 ( .LO ( optlc_net_2250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2495 ( .LO ( optlc_net_2251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2496 ( .LO ( optlc_net_2252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2497 ( .LO ( optlc_net_2253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2498 ( .LO ( optlc_net_2254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2499 ( .LO ( optlc_net_2255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2500 ( .LO ( optlc_net_2256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2501 ( .LO ( optlc_net_2257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2502 ( .LO ( optlc_net_2258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2503 ( .LO ( optlc_net_2259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2504 ( .LO ( optlc_net_2260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2505 ( .LO ( optlc_net_2261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2506 ( .LO ( optlc_net_2262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2507 ( .LO ( optlc_net_2263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2508 ( .LO ( optlc_net_2264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2509 ( .LO ( optlc_net_2265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2510 ( .LO ( optlc_net_2266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2511 ( .LO ( optlc_net_2267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2512 ( .LO ( optlc_net_2268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2513 ( .LO ( optlc_net_2269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2515 ( .LO ( optlc_net_2270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2516 ( .LO ( optlc_net_2271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2517 ( .LO ( optlc_net_2272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2518 ( .LO ( optlc_net_2273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2519 ( .LO ( optlc_net_2274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2520 ( .LO ( optlc_net_2275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2521 ( .LO ( optlc_net_2276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2522 ( .LO ( optlc_net_2277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2523 ( .LO ( optlc_net_2278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2524 ( .LO ( optlc_net_2279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2525 ( .LO ( optlc_net_2280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2526 ( .LO ( optlc_net_2281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2527 ( .LO ( optlc_net_2282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2528 ( .LO ( optlc_net_2283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2529 ( .LO ( optlc_net_2284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2530 ( .LO ( optlc_net_2285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2531 ( .LO ( optlc_net_2286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2532 ( .LO ( optlc_net_2287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2533 ( .LO ( optlc_net_2288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2534 ( .LO ( optlc_net_2289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2535 ( .LO ( optlc_net_2290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2536 ( .LO ( optlc_net_2291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2537 ( .LO ( optlc_net_2292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2538 ( .LO ( optlc_net_2293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2539 ( .LO ( optlc_net_2294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2540 ( .LO ( optlc_net_2295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2541 ( .LO ( optlc_net_2296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2542 ( .LO ( optlc_net_2297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2543 ( .LO ( optlc_net_2298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2544 ( .LO ( optlc_net_2299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2545 ( .LO ( optlc_net_2300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2546 ( .LO ( optlc_net_2301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2547 ( .LO ( optlc_net_2302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2548 ( .LO ( optlc_net_2303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2549 ( .LO ( optlc_net_2304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2550 ( .LO ( optlc_net_2305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2551 ( .LO ( optlc_net_2306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2552 ( .LO ( optlc_net_2307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2553 ( .LO ( optlc_net_2308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2554 ( .LO ( optlc_net_2309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2555 ( .LO ( optlc_net_2310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2556 ( .LO ( optlc_net_2311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2557 ( .LO ( optlc_net_2312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2558 ( .LO ( optlc_net_2313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2559 ( .LO ( optlc_net_2314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2560 ( .LO ( optlc_net_2315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2561 ( .LO ( optlc_net_2316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2562 ( .LO ( optlc_net_2317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2563 ( .LO ( optlc_net_2318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2564 ( .LO ( optlc_net_2319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2565 ( .LO ( optlc_net_2320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2566 ( .LO ( optlc_net_2321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2567 ( .LO ( optlc_net_2322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2568 ( .LO ( optlc_net_2323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2569 ( .LO ( optlc_net_2324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2570 ( .LO ( optlc_net_2325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2571 ( .LO ( optlc_net_2326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2572 ( .LO ( optlc_net_2327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2573 ( .LO ( optlc_net_2328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2574 ( .LO ( optlc_net_2329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2575 ( .LO ( optlc_net_2330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2576 ( .LO ( optlc_net_2331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2577 ( .LO ( optlc_net_2332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2578 ( .LO ( optlc_net_2333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2579 ( .LO ( optlc_net_2334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2580 ( .LO ( optlc_net_2335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2581 ( .LO ( optlc_net_2336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2582 ( .LO ( optlc_net_2337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2583 ( .LO ( optlc_net_2338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2584 ( .LO ( optlc_net_2339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2585 ( .LO ( optlc_net_2340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2586 ( .LO ( optlc_net_2341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2587 ( .LO ( optlc_net_2342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2588 ( .LO ( optlc_net_2343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2589 ( .LO ( optlc_net_2344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2590 ( .LO ( optlc_net_2345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2591 ( .LO ( optlc_net_2346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2592 ( .LO ( optlc_net_2347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2593 ( .LO ( optlc_net_2348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2594 ( .LO ( optlc_net_2349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2595 ( .LO ( optlc_net_2350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2596 ( .LO ( optlc_net_2351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2597 ( .LO ( optlc_net_2352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2598 ( .LO ( optlc_net_2353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2599 ( .LO ( optlc_net_2354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2600 ( .LO ( optlc_net_2355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2601 ( .LO ( optlc_net_2356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2602 ( .LO ( optlc_net_2357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2603 ( .LO ( optlc_net_2358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2604 ( .LO ( optlc_net_2359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2605 ( .LO ( optlc_net_2360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2606 ( .LO ( optlc_net_2361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2607 ( .LO ( optlc_net_2362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2608 ( .LO ( optlc_net_2363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2609 ( .LO ( optlc_net_2364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2610 ( .LO ( optlc_net_2365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2611 ( .LO ( optlc_net_2366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2612 ( .LO ( optlc_net_2367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2613 ( .LO ( optlc_net_2368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2614 ( .LO ( optlc_net_2369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2615 ( .LO ( optlc_net_2370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2616 ( .LO ( optlc_net_2371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2617 ( .LO ( optlc_net_2372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2618 ( .LO ( optlc_net_2373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2619 ( .LO ( optlc_net_2374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2620 ( .LO ( optlc_net_2375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2621 ( .LO ( optlc_net_2376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2622 ( .LO ( optlc_net_2377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2623 ( .LO ( optlc_net_2378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2624 ( .LO ( optlc_net_2379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2625 ( .LO ( optlc_net_2380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2626 ( .LO ( optlc_net_2381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2627 ( .LO ( optlc_net_2382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2628 ( .LO ( optlc_net_2383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2629 ( .LO ( optlc_net_2384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2630 ( .LO ( optlc_net_2385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2631 ( .LO ( optlc_net_2386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2632 ( .LO ( optlc_net_2387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2633 ( .LO ( optlc_net_2388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2634 ( .LO ( optlc_net_2389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2635 ( .LO ( optlc_net_2390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2636 ( .LO ( optlc_net_2391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2637 ( .LO ( optlc_net_2392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2638 ( .LO ( optlc_net_2393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2639 ( .LO ( optlc_net_2394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2640 ( .LO ( optlc_net_2395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2641 ( .LO ( optlc_net_2396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2642 ( .LO ( optlc_net_2397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2643 ( .LO ( optlc_net_2398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2644 ( .LO ( optlc_net_2399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2645 ( .LO ( optlc_net_2400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2646 ( .LO ( optlc_net_2401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2647 ( .LO ( optlc_net_2402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2648 ( .LO ( optlc_net_2403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2649 ( .LO ( optlc_net_2404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2650 ( .LO ( optlc_net_2405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2651 ( .LO ( optlc_net_2406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2652 ( .LO ( optlc_net_2407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2654 ( .LO ( optlc_net_2408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2655 ( .LO ( optlc_net_2409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2656 ( .LO ( optlc_net_2410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2657 ( .LO ( optlc_net_2411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2658 ( .LO ( optlc_net_2412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2659 ( .LO ( optlc_net_2413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2660 ( .LO ( optlc_net_2414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2661 ( .LO ( optlc_net_2415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2663 ( .LO ( optlc_net_2416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2665 ( .LO ( optlc_net_2417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2666 ( .LO ( optlc_net_2418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2667 ( .LO ( optlc_net_2419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2668 ( .LO ( optlc_net_2420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2669 ( .LO ( optlc_net_2421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2670 ( .LO ( optlc_net_2422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2671 ( .LO ( optlc_net_2423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2672 ( .LO ( optlc_net_2424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2673 ( .LO ( optlc_net_2425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2674 ( .LO ( optlc_net_2426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2675 ( .LO ( optlc_net_2427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2676 ( .LO ( optlc_net_2428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2677 ( .LO ( optlc_net_2429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2678 ( .LO ( optlc_net_2430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2679 ( .LO ( optlc_net_2431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2680 ( .LO ( optlc_net_2432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2682 ( .LO ( optlc_net_2433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2683 ( .LO ( optlc_net_2434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2684 ( .LO ( optlc_net_2435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2685 ( .LO ( optlc_net_2436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2686 ( .LO ( optlc_net_2437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2687 ( .LO ( optlc_net_2438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2688 ( .LO ( optlc_net_2439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2689 ( .LO ( optlc_net_2440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2690 ( .LO ( optlc_net_2441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2691 ( .LO ( optlc_net_2442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2692 ( .LO ( optlc_net_2443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2693 ( .LO ( optlc_net_2444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2694 ( .LO ( optlc_net_2445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2695 ( .LO ( optlc_net_2446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2696 ( .LO ( optlc_net_2447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2697 ( .LO ( optlc_net_2448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2698 ( .LO ( optlc_net_2449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2699 ( .LO ( optlc_net_2450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2700 ( .LO ( optlc_net_2451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2701 ( .LO ( optlc_net_2452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2702 ( .LO ( optlc_net_2453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2703 ( .LO ( optlc_net_2454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2704 ( .LO ( optlc_net_2455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2705 ( .LO ( optlc_net_2456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2706 ( .LO ( optlc_net_2457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2707 ( .LO ( optlc_net_2458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2708 ( .LO ( optlc_net_2459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2709 ( .LO ( optlc_net_2460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2710 ( .LO ( optlc_net_2461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2711 ( .LO ( optlc_net_2462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2712 ( .LO ( optlc_net_2463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2713 ( .LO ( optlc_net_2464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2714 ( .LO ( optlc_net_2465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2715 ( .LO ( optlc_net_2466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2716 ( .LO ( optlc_net_2467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2717 ( .LO ( optlc_net_2468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2718 ( .LO ( optlc_net_2469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2719 ( .LO ( optlc_net_2470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2720 ( .LO ( optlc_net_2471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2721 ( .LO ( optlc_net_2472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2722 ( .LO ( optlc_net_2473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2723 ( .LO ( optlc_net_2474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2724 ( .LO ( optlc_net_2475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2725 ( .LO ( optlc_net_2476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2726 ( .LO ( optlc_net_2477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2727 ( .LO ( optlc_net_2478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2728 ( .LO ( optlc_net_2479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2729 ( .LO ( optlc_net_2480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2730 ( .LO ( optlc_net_2481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2731 ( .LO ( optlc_net_2482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2732 ( .LO ( optlc_net_2483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2733 ( .LO ( optlc_net_2484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2734 ( .LO ( optlc_net_2485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2735 ( .LO ( optlc_net_2486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2736 ( .LO ( optlc_net_2487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2737 ( .LO ( optlc_net_2488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2738 ( .LO ( optlc_net_2489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2739 ( .LO ( optlc_net_2490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2740 ( .LO ( optlc_net_2491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2742 ( .LO ( optlc_net_2492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2743 ( .LO ( optlc_net_2493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2744 ( .LO ( optlc_net_2494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2745 ( .LO ( optlc_net_2495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2746 ( .LO ( optlc_net_2496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2747 ( .LO ( optlc_net_2497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2748 ( .LO ( optlc_net_2498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2749 ( .LO ( optlc_net_2499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2751 ( .LO ( optlc_net_2500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2752 ( .LO ( optlc_net_2501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2753 ( .LO ( optlc_net_2502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2754 ( .LO ( optlc_net_2503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2755 ( .LO ( optlc_net_2504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2756 ( .LO ( optlc_net_2505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2757 ( .LO ( optlc_net_2506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2758 ( .LO ( optlc_net_2507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2759 ( .LO ( optlc_net_2508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2760 ( .LO ( optlc_net_2509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2761 ( .LO ( optlc_net_2510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2762 ( .LO ( optlc_net_2511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2764 ( .LO ( optlc_net_2512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2766 ( .LO ( optlc_net_2513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2767 ( .LO ( optlc_net_2514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2768 ( .LO ( optlc_net_2515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2769 ( .LO ( optlc_net_2516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2770 ( .LO ( optlc_net_2517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2771 ( .LO ( optlc_net_2518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2772 ( .LO ( optlc_net_2519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2773 ( .LO ( optlc_net_2520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2774 ( .LO ( optlc_net_2521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2775 ( .LO ( optlc_net_2522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2776 ( .LO ( optlc_net_2523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2777 ( .LO ( optlc_net_2524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2778 ( .LO ( optlc_net_2525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2779 ( .LO ( optlc_net_2526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2780 ( .LO ( optlc_net_2527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2781 ( .LO ( optlc_net_2528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2783 ( .LO ( optlc_net_2529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2784 ( .LO ( optlc_net_2530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2785 ( .LO ( optlc_net_2531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2787 ( .LO ( optlc_net_2532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2788 ( .LO ( optlc_net_2533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2789 ( .LO ( optlc_net_2534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2790 ( .LO ( optlc_net_2535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2792 ( .LO ( optlc_net_2536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2793 ( .LO ( optlc_net_2537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2794 ( .LO ( optlc_net_2538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2795 ( .LO ( optlc_net_2539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2797 ( .LO ( optlc_net_2540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2798 ( .LO ( optlc_net_2541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2799 ( .LO ( optlc_net_2542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2800 ( .LO ( optlc_net_2543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2801 ( .LO ( optlc_net_2544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2802 ( .LO ( optlc_net_2545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2803 ( .LO ( optlc_net_2546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2804 ( .LO ( optlc_net_2547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2805 ( .LO ( optlc_net_2548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2806 ( .LO ( optlc_net_2549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2807 ( .LO ( optlc_net_2550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2808 ( .LO ( optlc_net_2551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2809 ( .LO ( optlc_net_2552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2810 ( .LO ( optlc_net_2553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2812 ( .LO ( optlc_net_2554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2813 ( .LO ( optlc_net_2555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2814 ( .LO ( optlc_net_2556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2815 ( .LO ( optlc_net_2557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2816 ( .LO ( optlc_net_2558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2817 ( .LO ( optlc_net_2559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2818 ( .LO ( optlc_net_2560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2819 ( .LO ( optlc_net_2561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2820 ( .LO ( optlc_net_2562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2821 ( .LO ( optlc_net_2563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2822 ( .LO ( optlc_net_2564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2823 ( .LO ( optlc_net_2565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2824 ( .LO ( optlc_net_2566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2826 ( .LO ( optlc_net_2567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2827 ( .LO ( optlc_net_2568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2828 ( .LO ( optlc_net_2569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2829 ( .LO ( optlc_net_2570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2830 ( .LO ( optlc_net_2571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2831 ( .LO ( optlc_net_2572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2832 ( .LO ( optlc_net_2573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2833 ( .LO ( optlc_net_2574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2834 ( .LO ( optlc_net_2575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2835 ( .LO ( optlc_net_2576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2836 ( .LO ( optlc_net_2577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2837 ( .LO ( optlc_net_2578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2838 ( .LO ( optlc_net_2579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2839 ( .LO ( optlc_net_2580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2840 ( .LO ( optlc_net_2581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2841 ( .LO ( optlc_net_2582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2842 ( .LO ( optlc_net_2583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2843 ( .LO ( optlc_net_2584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2844 ( .LO ( optlc_net_2585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2845 ( .LO ( optlc_net_2586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2846 ( .LO ( optlc_net_2587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2847 ( .LO ( optlc_net_2588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2848 ( .LO ( optlc_net_2589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2849 ( .LO ( optlc_net_2590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2850 ( .LO ( optlc_net_2591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2851 ( .LO ( optlc_net_2592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2852 ( .LO ( optlc_net_2593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2853 ( .LO ( optlc_net_2594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2854 ( .LO ( optlc_net_2595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2855 ( .LO ( optlc_net_2596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2856 ( .LO ( optlc_net_2597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2857 ( .LO ( optlc_net_2598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2858 ( .LO ( optlc_net_2599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2859 ( .LO ( optlc_net_2600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2860 ( .LO ( optlc_net_2601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2861 ( .LO ( optlc_net_2602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2862 ( .LO ( optlc_net_2603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2863 ( .LO ( optlc_net_2604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2864 ( .LO ( optlc_net_2605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2865 ( .LO ( optlc_net_2606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2866 ( .LO ( optlc_net_2607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2867 ( .LO ( optlc_net_2608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2868 ( .LO ( optlc_net_2609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2869 ( .LO ( optlc_net_2610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2870 ( .LO ( optlc_net_2611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2871 ( .LO ( optlc_net_2612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2872 ( .LO ( optlc_net_2613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2873 ( .LO ( optlc_net_2614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2874 ( .LO ( optlc_net_2615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2875 ( .LO ( optlc_net_2616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2876 ( .LO ( optlc_net_2617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2877 ( .LO ( optlc_net_2618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2878 ( .LO ( optlc_net_2619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2879 ( .LO ( optlc_net_2620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2880 ( .LO ( optlc_net_2621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2881 ( .LO ( optlc_net_2622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2882 ( .LO ( optlc_net_2623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2883 ( .LO ( optlc_net_2624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2884 ( .LO ( optlc_net_2625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2885 ( .LO ( optlc_net_2626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2886 ( .LO ( optlc_net_2627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2887 ( .LO ( optlc_net_2628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2888 ( .LO ( optlc_net_2629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2889 ( .LO ( optlc_net_2630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2890 ( .LO ( optlc_net_2631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2891 ( .LO ( optlc_net_2632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2892 ( .LO ( optlc_net_2633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2893 ( .LO ( optlc_net_2634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2894 ( .LO ( optlc_net_2635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2895 ( .LO ( optlc_net_2636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2896 ( .LO ( optlc_net_2637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2897 ( .LO ( optlc_net_2638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2898 ( .LO ( optlc_net_2639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2899 ( .LO ( optlc_net_2640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2900 ( .LO ( optlc_net_2641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2901 ( .LO ( optlc_net_2642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2902 ( .LO ( optlc_net_2643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2903 ( .LO ( optlc_net_2644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2904 ( .LO ( optlc_net_2645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2905 ( .LO ( optlc_net_2646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2906 ( .LO ( optlc_net_2647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2907 ( .LO ( optlc_net_2648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2908 ( .LO ( optlc_net_2649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2909 ( .LO ( optlc_net_2650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2910 ( .LO ( optlc_net_2651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2911 ( .LO ( optlc_net_2652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2912 ( .LO ( optlc_net_2653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2913 ( .LO ( optlc_net_2654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2914 ( .LO ( optlc_net_2655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2915 ( .LO ( optlc_net_2656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2916 ( .LO ( optlc_net_2657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2917 ( .LO ( optlc_net_2658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2918 ( .LO ( optlc_net_2659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2919 ( .LO ( optlc_net_2660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2920 ( .LO ( optlc_net_2661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2921 ( .LO ( optlc_net_2662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2922 ( .LO ( optlc_net_2663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2923 ( .LO ( optlc_net_2664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2924 ( .LO ( optlc_net_2665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2925 ( .LO ( optlc_net_2666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2926 ( .LO ( optlc_net_2667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2927 ( .LO ( optlc_net_2668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2928 ( .LO ( optlc_net_2669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2929 ( .LO ( optlc_net_2670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2930 ( .LO ( optlc_net_2671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2931 ( .LO ( optlc_net_2672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2932 ( .LO ( optlc_net_2673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2933 ( .LO ( optlc_net_2674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2934 ( .LO ( optlc_net_2675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2935 ( .LO ( optlc_net_2676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2936 ( .LO ( optlc_net_2677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2937 ( .LO ( optlc_net_2678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2938 ( .LO ( optlc_net_2679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2939 ( .LO ( optlc_net_2680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2940 ( .LO ( optlc_net_2681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2941 ( .LO ( optlc_net_2682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2942 ( .LO ( optlc_net_2683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2943 ( .LO ( optlc_net_2684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2944 ( .LO ( optlc_net_2685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2945 ( .LO ( optlc_net_2686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2946 ( .LO ( optlc_net_2687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2947 ( .LO ( optlc_net_2688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2948 ( .LO ( optlc_net_2689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2949 ( .LO ( optlc_net_2690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2950 ( .LO ( optlc_net_2691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2951 ( .LO ( optlc_net_2692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2952 ( .LO ( optlc_net_2693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2953 ( .LO ( optlc_net_2694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2954 ( .LO ( optlc_net_2695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2955 ( .LO ( optlc_net_2696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2956 ( .LO ( optlc_net_2697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2957 ( .LO ( optlc_net_2698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2700 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2958 ( .LO ( optlc_net_2699 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2701 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2959 ( .LO ( optlc_net_2700 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2702 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2960 ( .LO ( optlc_net_2701 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2703 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2961 ( .LO ( optlc_net_2702 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2704 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2962 ( .LO ( optlc_net_2703 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2705 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2963 ( .LO ( optlc_net_2704 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2706 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2964 ( .LO ( optlc_net_2705 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2707 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2966 ( .LO ( optlc_net_2706 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2708 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2967 ( .LO ( optlc_net_2707 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2709 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2968 ( .LO ( optlc_net_2708 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2710 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2969 ( .LO ( optlc_net_2709 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2711 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2970 ( .LO ( optlc_net_2710 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2971 ( .LO ( optlc_net_2711 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2713 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2972 ( .LO ( optlc_net_2712 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2714 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2973 ( .LO ( optlc_net_2713 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2715 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2974 ( .LO ( optlc_net_2714 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2716 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2976 ( .LO ( optlc_net_2715 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2717 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2977 ( .LO ( optlc_net_2716 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2718 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2978 ( .LO ( optlc_net_2717 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2719 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2979 ( .LO ( optlc_net_2718 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2720 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2980 ( .LO ( optlc_net_2719 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2721 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2981 ( .LO ( optlc_net_2720 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2722 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2982 ( .LO ( optlc_net_2721 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2723 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2983 ( .LO ( optlc_net_2722 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2724 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2984 ( .LO ( optlc_net_2723 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2725 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2985 ( .LO ( optlc_net_2724 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2726 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2986 ( .LO ( optlc_net_2725 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2727 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2987 ( .LO ( optlc_net_2726 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2728 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2988 ( .LO ( optlc_net_2727 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2989 ( .LO ( optlc_net_2728 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2730 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2990 ( .LO ( optlc_net_2729 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2731 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2991 ( .LO ( optlc_net_2730 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2732 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2992 ( .LO ( optlc_net_2731 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2733 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2994 ( .LO ( optlc_net_2732 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2734 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2995 ( .LO ( optlc_net_2733 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2735 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2996 ( .LO ( optlc_net_2734 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2997 ( .LO ( optlc_net_2735 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2737 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2998 ( .LO ( optlc_net_2736 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2738 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_2999 ( .LO ( optlc_net_2737 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2739 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3000 ( .LO ( optlc_net_2738 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2740 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3001 ( .LO ( optlc_net_2739 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2741 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3002 ( .LO ( optlc_net_2740 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2742 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3003 ( .LO ( optlc_net_2741 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2743 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3004 ( .LO ( optlc_net_2742 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2744 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3006 ( .LO ( optlc_net_2743 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2745 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3007 ( .LO ( optlc_net_2744 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2746 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3008 ( .LO ( optlc_net_2745 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2747 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3009 ( .LO ( optlc_net_2746 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2748 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3010 ( .LO ( optlc_net_2747 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2749 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3011 ( .LO ( optlc_net_2748 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2750 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3012 ( .LO ( optlc_net_2749 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2751 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3014 ( .LO ( optlc_net_2750 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2752 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3015 ( .LO ( optlc_net_2751 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2753 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3017 ( .LO ( optlc_net_2752 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2754 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3018 ( .LO ( optlc_net_2753 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3019 ( .LO ( optlc_net_2754 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2756 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3020 ( .LO ( optlc_net_2755 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2757 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3021 ( .LO ( optlc_net_2756 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2758 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3022 ( .LO ( optlc_net_2757 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2759 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3023 ( .LO ( optlc_net_2758 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3024 ( .LO ( optlc_net_2759 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3025 ( .LO ( optlc_net_2760 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3026 ( .LO ( optlc_net_2761 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3027 ( .LO ( optlc_net_2762 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3028 ( .LO ( optlc_net_2763 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3029 ( .LO ( optlc_net_2764 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3030 ( .LO ( optlc_net_2765 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3031 ( .LO ( optlc_net_2766 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3032 ( .LO ( optlc_net_2767 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3033 ( .LO ( optlc_net_2768 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3034 ( .LO ( optlc_net_2769 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3035 ( .LO ( optlc_net_2770 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3037 ( .LO ( optlc_net_2771 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3038 ( .LO ( optlc_net_2772 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3039 ( .LO ( optlc_net_2773 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3040 ( .LO ( optlc_net_2774 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3041 ( .LO ( optlc_net_2775 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3042 ( .LO ( optlc_net_2776 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3043 ( .LO ( optlc_net_2777 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3044 ( .LO ( optlc_net_2778 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2780 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3045 ( .LO ( optlc_net_2779 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2781 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3046 ( .LO ( optlc_net_2780 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2782 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3047 ( .LO ( optlc_net_2781 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2783 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3049 ( .LO ( optlc_net_2782 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3050 ( .LO ( optlc_net_2783 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2785 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3051 ( .LO ( optlc_net_2784 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2786 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3052 ( .LO ( optlc_net_2785 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2787 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3053 ( .LO ( optlc_net_2786 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2788 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3054 ( .LO ( optlc_net_2787 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3055 ( .LO ( optlc_net_2788 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3056 ( .LO ( optlc_net_2789 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3057 ( .LO ( optlc_net_2790 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3058 ( .LO ( optlc_net_2791 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3059 ( .LO ( optlc_net_2792 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3060 ( .LO ( optlc_net_2793 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3061 ( .LO ( optlc_net_2794 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3062 ( .LO ( optlc_net_2795 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3063 ( .LO ( optlc_net_2796 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3064 ( .LO ( optlc_net_2797 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3065 ( .LO ( optlc_net_2798 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3066 ( .LO ( optlc_net_2799 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3067 ( .LO ( optlc_net_2800 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3068 ( .LO ( optlc_net_2801 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3069 ( .LO ( optlc_net_2802 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3070 ( .LO ( optlc_net_2803 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3071 ( .LO ( optlc_net_2804 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3072 ( .LO ( optlc_net_2805 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3073 ( .LO ( optlc_net_2806 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3074 ( .LO ( optlc_net_2807 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3075 ( .LO ( optlc_net_2808 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2810 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3076 ( .LO ( optlc_net_2809 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2811 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3078 ( .LO ( optlc_net_2810 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2812 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3079 ( .LO ( optlc_net_2811 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2813 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3080 ( .LO ( optlc_net_2812 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2814 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3081 ( .LO ( optlc_net_2813 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2815 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3082 ( .LO ( optlc_net_2814 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2816 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3083 ( .LO ( optlc_net_2815 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2817 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3085 ( .LO ( optlc_net_2816 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3086 ( .LO ( optlc_net_2817 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3087 ( .LO ( optlc_net_2818 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3088 ( .LO ( optlc_net_2819 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3089 ( .LO ( optlc_net_2820 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3090 ( .LO ( optlc_net_2821 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3091 ( .LO ( optlc_net_2822 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3092 ( .LO ( optlc_net_2823 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3093 ( .LO ( optlc_net_2824 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3094 ( .LO ( optlc_net_2825 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3095 ( .LO ( optlc_net_2826 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3096 ( .LO ( optlc_net_2827 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3097 ( .LO ( optlc_net_2828 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3098 ( .LO ( optlc_net_2829 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3099 ( .LO ( optlc_net_2830 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3100 ( .LO ( optlc_net_2831 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3101 ( .LO ( optlc_net_2832 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3102 ( .LO ( optlc_net_2833 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3103 ( .LO ( optlc_net_2834 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3104 ( .LO ( optlc_net_2835 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2837 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3105 ( .LO ( optlc_net_2836 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2838 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3106 ( .LO ( optlc_net_2837 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2839 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3107 ( .LO ( optlc_net_2838 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2840 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3108 ( .LO ( optlc_net_2839 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2841 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3109 ( .LO ( optlc_net_2840 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2842 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3110 ( .LO ( optlc_net_2841 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2843 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3111 ( .LO ( optlc_net_2842 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2844 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3112 ( .LO ( optlc_net_2843 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2845 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3113 ( .LO ( optlc_net_2844 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2846 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3114 ( .LO ( optlc_net_2845 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3115 ( .LO ( optlc_net_2846 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3116 ( .LO ( optlc_net_2847 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3117 ( .LO ( optlc_net_2848 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3118 ( .LO ( optlc_net_2849 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3119 ( .LO ( optlc_net_2850 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3120 ( .LO ( optlc_net_2851 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3121 ( .LO ( optlc_net_2852 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3122 ( .LO ( optlc_net_2853 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3123 ( .LO ( optlc_net_2854 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3124 ( .LO ( optlc_net_2855 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3125 ( .LO ( optlc_net_2856 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3126 ( .LO ( optlc_net_2857 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3127 ( .LO ( optlc_net_2858 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3128 ( .LO ( optlc_net_2859 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3129 ( .LO ( optlc_net_2860 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3130 ( .LO ( optlc_net_2861 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3131 ( .LO ( optlc_net_2862 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3132 ( .LO ( optlc_net_2863 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3133 ( .LO ( optlc_net_2864 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2866 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3134 ( .LO ( optlc_net_2865 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2867 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3135 ( .LO ( optlc_net_2866 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2868 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3136 ( .LO ( optlc_net_2867 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2869 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3137 ( .LO ( optlc_net_2868 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2870 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3138 ( .LO ( optlc_net_2869 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2871 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3139 ( .LO ( optlc_net_2870 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2872 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3140 ( .LO ( optlc_net_2871 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2873 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3141 ( .LO ( optlc_net_2872 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3142 ( .LO ( optlc_net_2873 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2875 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3143 ( .LO ( optlc_net_2874 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3144 ( .LO ( optlc_net_2875 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3145 ( .LO ( optlc_net_2876 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3146 ( .LO ( optlc_net_2877 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3147 ( .LO ( optlc_net_2878 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3148 ( .LO ( optlc_net_2879 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3149 ( .LO ( optlc_net_2880 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3150 ( .LO ( optlc_net_2881 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3151 ( .LO ( optlc_net_2882 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3152 ( .LO ( optlc_net_2883 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3153 ( .LO ( optlc_net_2884 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3154 ( .LO ( optlc_net_2885 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3155 ( .LO ( optlc_net_2886 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3156 ( .LO ( optlc_net_2887 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3157 ( .LO ( optlc_net_2888 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3158 ( .LO ( optlc_net_2889 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3159 ( .LO ( optlc_net_2890 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3160 ( .LO ( optlc_net_2891 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3161 ( .LO ( optlc_net_2892 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3162 ( .LO ( optlc_net_2893 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2895 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3163 ( .LO ( optlc_net_2894 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2896 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3164 ( .LO ( optlc_net_2895 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2897 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3165 ( .LO ( optlc_net_2896 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2898 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3166 ( .LO ( optlc_net_2897 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2899 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3167 ( .LO ( optlc_net_2898 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2900 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3168 ( .LO ( optlc_net_2899 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2901 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3169 ( .LO ( optlc_net_2900 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2902 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3170 ( .LO ( optlc_net_2901 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2903 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3171 ( .LO ( optlc_net_2902 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2904 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3172 ( .LO ( optlc_net_2903 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3173 ( .LO ( optlc_net_2904 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3174 ( .LO ( optlc_net_2905 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3175 ( .LO ( optlc_net_2906 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3176 ( .LO ( optlc_net_2907 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3177 ( .LO ( optlc_net_2908 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3178 ( .LO ( optlc_net_2909 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3179 ( .LO ( optlc_net_2910 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3180 ( .LO ( optlc_net_2911 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3181 ( .LO ( optlc_net_2912 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3182 ( .LO ( optlc_net_2913 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3183 ( .LO ( optlc_net_2914 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3184 ( .LO ( optlc_net_2915 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3186 ( .LO ( optlc_net_2916 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3187 ( .LO ( optlc_net_2917 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3188 ( .LO ( optlc_net_2918 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3189 ( .LO ( optlc_net_2919 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3190 ( .LO ( optlc_net_2920 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3191 ( .LO ( optlc_net_2921 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3192 ( .LO ( optlc_net_2922 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2924 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3193 ( .LO ( optlc_net_2923 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2925 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3194 ( .LO ( optlc_net_2924 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2926 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3195 ( .LO ( optlc_net_2925 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2927 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3197 ( .LO ( optlc_net_2926 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2928 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3198 ( .LO ( optlc_net_2927 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2929 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3199 ( .LO ( optlc_net_2928 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2930 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3200 ( .LO ( optlc_net_2929 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2931 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3201 ( .LO ( optlc_net_2930 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2932 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3202 ( .LO ( optlc_net_2931 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2933 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3203 ( .LO ( optlc_net_2932 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3204 ( .LO ( optlc_net_2933 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3205 ( .LO ( optlc_net_2934 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3206 ( .LO ( optlc_net_2935 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3207 ( .LO ( optlc_net_2936 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3209 ( .LO ( optlc_net_2937 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3210 ( .LO ( optlc_net_2938 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3211 ( .LO ( optlc_net_2939 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3212 ( .LO ( optlc_net_2940 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3213 ( .LO ( optlc_net_2941 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3214 ( .LO ( optlc_net_2942 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3215 ( .LO ( optlc_net_2943 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3216 ( .LO ( optlc_net_2944 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3217 ( .LO ( optlc_net_2945 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3218 ( .LO ( optlc_net_2946 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3219 ( .LO ( optlc_net_2947 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3220 ( .LO ( optlc_net_2948 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3221 ( .LO ( optlc_net_2949 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3222 ( .LO ( optlc_net_2950 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3223 ( .LO ( optlc_net_2951 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2953 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3224 ( .LO ( optlc_net_2952 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3225 ( .LO ( optlc_net_2953 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2955 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3226 ( .LO ( optlc_net_2954 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2956 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3227 ( .LO ( optlc_net_2955 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2957 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3228 ( .LO ( optlc_net_2956 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2958 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3229 ( .LO ( optlc_net_2957 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2959 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3230 ( .LO ( optlc_net_2958 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2960 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3231 ( .LO ( optlc_net_2959 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2961 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3232 ( .LO ( optlc_net_2960 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2962 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3233 ( .LO ( optlc_net_2961 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3234 ( .LO ( optlc_net_2962 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3235 ( .LO ( optlc_net_2963 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3236 ( .LO ( optlc_net_2964 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3237 ( .LO ( optlc_net_2965 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3239 ( .LO ( optlc_net_2966 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3240 ( .LO ( optlc_net_2967 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3241 ( .LO ( optlc_net_2968 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3242 ( .LO ( optlc_net_2969 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3243 ( .LO ( optlc_net_2970 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3244 ( .LO ( optlc_net_2971 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3246 ( .LO ( optlc_net_2972 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3247 ( .LO ( optlc_net_2973 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3248 ( .LO ( optlc_net_2974 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3249 ( .LO ( optlc_net_2975 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3250 ( .LO ( optlc_net_2976 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3251 ( .LO ( optlc_net_2977 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3252 ( .LO ( optlc_net_2978 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3254 ( .LO ( optlc_net_2979 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3255 ( .LO ( optlc_net_2980 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2982 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3256 ( .LO ( optlc_net_2981 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2983 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3257 ( .LO ( optlc_net_2982 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2984 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3258 ( .LO ( optlc_net_2983 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2985 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3259 ( .LO ( optlc_net_2984 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2986 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3260 ( .LO ( optlc_net_2985 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2987 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3261 ( .LO ( optlc_net_2986 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2988 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3262 ( .LO ( optlc_net_2987 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2989 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3263 ( .LO ( optlc_net_2988 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2990 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3264 ( .LO ( optlc_net_2989 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3265 ( .LO ( optlc_net_2990 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3266 ( .LO ( optlc_net_2991 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3267 ( .LO ( optlc_net_2992 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3268 ( .LO ( optlc_net_2993 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3269 ( .LO ( optlc_net_2994 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3270 ( .LO ( optlc_net_2995 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3271 ( .LO ( optlc_net_2996 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3272 ( .LO ( optlc_net_2997 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3273 ( .LO ( optlc_net_2998 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3274 ( .LO ( optlc_net_2999 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3275 ( .LO ( optlc_net_3000 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3276 ( .LO ( optlc_net_3001 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3277 ( .LO ( optlc_net_3002 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3278 ( .LO ( optlc_net_3003 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3279 ( .LO ( optlc_net_3004 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3280 ( .LO ( optlc_net_3005 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3281 ( .LO ( optlc_net_3006 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3282 ( .LO ( optlc_net_3007 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3283 ( .LO ( optlc_net_3008 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3284 ( .LO ( optlc_net_3009 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3011 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3285 ( .LO ( optlc_net_3010 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3012 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3286 ( .LO ( optlc_net_3011 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3013 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3287 ( .LO ( optlc_net_3012 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3014 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3288 ( .LO ( optlc_net_3013 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3015 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3290 ( .LO ( optlc_net_3014 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3016 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3291 ( .LO ( optlc_net_3015 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3292 ( .LO ( optlc_net_3016 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3018 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3293 ( .LO ( optlc_net_3017 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3019 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3294 ( .LO ( optlc_net_3018 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3020 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3295 ( .LO ( optlc_net_3019 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3296 ( .LO ( optlc_net_3020 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3297 ( .LO ( optlc_net_3021 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3298 ( .LO ( optlc_net_3022 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3299 ( .LO ( optlc_net_3023 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3300 ( .LO ( optlc_net_3024 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3301 ( .LO ( optlc_net_3025 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3302 ( .LO ( optlc_net_3026 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3303 ( .LO ( optlc_net_3027 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3304 ( .LO ( optlc_net_3028 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3305 ( .LO ( optlc_net_3029 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3306 ( .LO ( optlc_net_3030 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3307 ( .LO ( optlc_net_3031 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3308 ( .LO ( optlc_net_3032 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3309 ( .LO ( optlc_net_3033 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3310 ( .LO ( optlc_net_3034 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3311 ( .LO ( optlc_net_3035 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3312 ( .LO ( optlc_net_3036 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3313 ( .LO ( optlc_net_3037 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3314 ( .LO ( optlc_net_3038 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3315 ( .LO ( optlc_net_3039 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3041 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3316 ( .LO ( optlc_net_3040 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3042 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3317 ( .LO ( optlc_net_3041 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3043 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3318 ( .LO ( optlc_net_3042 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3044 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3319 ( .LO ( optlc_net_3043 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3320 ( .LO ( optlc_net_3044 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3046 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3321 ( .LO ( optlc_net_3045 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3047 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3322 ( .LO ( optlc_net_3046 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3048 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3323 ( .LO ( optlc_net_3047 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3049 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3324 ( .LO ( optlc_net_3048 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3325 ( .LO ( optlc_net_3049 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3326 ( .LO ( optlc_net_3050 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3327 ( .LO ( optlc_net_3051 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3328 ( .LO ( optlc_net_3052 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3329 ( .LO ( optlc_net_3053 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3330 ( .LO ( optlc_net_3054 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3331 ( .LO ( optlc_net_3055 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3332 ( .LO ( optlc_net_3056 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3333 ( .LO ( optlc_net_3057 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3334 ( .LO ( optlc_net_3058 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3335 ( .LO ( optlc_net_3059 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3336 ( .LO ( optlc_net_3060 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3337 ( .LO ( optlc_net_3061 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3338 ( .LO ( optlc_net_3062 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3339 ( .LO ( optlc_net_3063 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3340 ( .LO ( optlc_net_3064 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3341 ( .LO ( optlc_net_3065 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3342 ( .LO ( optlc_net_3066 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3343 ( .LO ( optlc_net_3067 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3069 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3344 ( .LO ( optlc_net_3068 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3070 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3345 ( .LO ( optlc_net_3069 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3346 ( .LO ( optlc_net_3070 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3072 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3347 ( .LO ( optlc_net_3071 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3073 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3348 ( .LO ( optlc_net_3072 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3074 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3349 ( .LO ( optlc_net_3073 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3075 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3350 ( .LO ( optlc_net_3074 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3076 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3351 ( .LO ( optlc_net_3075 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3077 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3352 ( .LO ( optlc_net_3076 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3078 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3353 ( .LO ( optlc_net_3077 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3354 ( .LO ( optlc_net_3078 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3355 ( .LO ( optlc_net_3079 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3356 ( .LO ( optlc_net_3080 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3357 ( .LO ( optlc_net_3081 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3358 ( .LO ( optlc_net_3082 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3359 ( .LO ( optlc_net_3083 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3360 ( .LO ( optlc_net_3084 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3361 ( .LO ( optlc_net_3085 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3362 ( .LO ( optlc_net_3086 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3363 ( .LO ( optlc_net_3087 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3364 ( .LO ( optlc_net_3088 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3365 ( .LO ( optlc_net_3089 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3366 ( .LO ( optlc_net_3090 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3367 ( .LO ( optlc_net_3091 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3368 ( .LO ( optlc_net_3092 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3369 ( .LO ( optlc_net_3093 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3370 ( .LO ( optlc_net_3094 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3371 ( .LO ( optlc_net_3095 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3097 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3372 ( .LO ( optlc_net_3096 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3098 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3373 ( .LO ( optlc_net_3097 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3374 ( .LO ( optlc_net_3098 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3100 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3375 ( .LO ( optlc_net_3099 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3101 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3376 ( .LO ( optlc_net_3100 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3102 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3377 ( .LO ( optlc_net_3101 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3103 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3378 ( .LO ( optlc_net_3102 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3104 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3379 ( .LO ( optlc_net_3103 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3105 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3380 ( .LO ( optlc_net_3104 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3106 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3381 ( .LO ( optlc_net_3105 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3107 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3382 ( .LO ( optlc_net_3106 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3108 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3383 ( .LO ( optlc_net_3107 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3109 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3385 ( .LO ( optlc_net_3108 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3110 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3386 ( .LO ( optlc_net_3109 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3111 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3387 ( .LO ( optlc_net_3110 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3112 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3388 ( .LO ( optlc_net_3111 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3113 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3389 ( .LO ( optlc_net_3112 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3390 ( .LO ( optlc_net_3113 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3391 ( .LO ( optlc_net_3114 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3116 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3392 ( .LO ( optlc_net_3115 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3117 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3393 ( .LO ( optlc_net_3116 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3118 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3394 ( .LO ( optlc_net_3117 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3119 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3395 ( .LO ( optlc_net_3118 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3120 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3396 ( .LO ( optlc_net_3119 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3121 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3397 ( .LO ( optlc_net_3120 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3122 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3398 ( .LO ( optlc_net_3121 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3123 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3399 ( .LO ( optlc_net_3122 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3124 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3400 ( .LO ( optlc_net_3123 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3125 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3401 ( .LO ( optlc_net_3124 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3402 ( .LO ( optlc_net_3125 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3127 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3403 ( .LO ( optlc_net_3126 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3128 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3404 ( .LO ( optlc_net_3127 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3129 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3405 ( .LO ( optlc_net_3128 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3130 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3406 ( .LO ( optlc_net_3129 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3131 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3407 ( .LO ( optlc_net_3130 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3132 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3408 ( .LO ( optlc_net_3131 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3133 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3409 ( .LO ( optlc_net_3132 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3134 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3410 ( .LO ( optlc_net_3133 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3135 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3411 ( .LO ( optlc_net_3134 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3136 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3412 ( .LO ( optlc_net_3135 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3137 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3413 ( .LO ( optlc_net_3136 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3138 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3414 ( .LO ( optlc_net_3137 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3139 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3415 ( .LO ( optlc_net_3138 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3140 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3416 ( .LO ( optlc_net_3139 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3141 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3417 ( .LO ( optlc_net_3140 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3142 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3418 ( .LO ( optlc_net_3141 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3143 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3419 ( .LO ( optlc_net_3142 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3144 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3420 ( .LO ( optlc_net_3143 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3421 ( .LO ( optlc_net_3144 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3146 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3422 ( .LO ( optlc_net_3145 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3147 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3423 ( .LO ( optlc_net_3146 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3148 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3424 ( .LO ( optlc_net_3147 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3149 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3425 ( .LO ( optlc_net_3148 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3150 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3426 ( .LO ( optlc_net_3149 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3151 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3427 ( .LO ( optlc_net_3150 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3152 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3428 ( .LO ( optlc_net_3151 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3153 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3429 ( .LO ( optlc_net_3152 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3154 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3430 ( .LO ( optlc_net_3153 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3155 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3431 ( .LO ( optlc_net_3154 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3156 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3432 ( .LO ( optlc_net_3155 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3157 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3433 ( .LO ( optlc_net_3156 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3158 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3434 ( .LO ( optlc_net_3157 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3159 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3435 ( .LO ( optlc_net_3158 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3160 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3436 ( .LO ( optlc_net_3159 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3161 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3437 ( .LO ( optlc_net_3160 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3162 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3438 ( .LO ( optlc_net_3161 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3163 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3439 ( .LO ( optlc_net_3162 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3164 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3440 ( .LO ( optlc_net_3163 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3165 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3441 ( .LO ( optlc_net_3164 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3166 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3442 ( .LO ( optlc_net_3165 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3167 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3443 ( .LO ( optlc_net_3166 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3168 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3444 ( .LO ( optlc_net_3167 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3169 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3445 ( .LO ( optlc_net_3168 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3170 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3446 ( .LO ( optlc_net_3169 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3171 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3447 ( .LO ( optlc_net_3170 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3172 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3448 ( .LO ( optlc_net_3171 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3173 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3449 ( .LO ( optlc_net_3172 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3174 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3450 ( .LO ( optlc_net_3173 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3175 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3451 ( .LO ( optlc_net_3174 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3176 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3452 ( .LO ( optlc_net_3175 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3177 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3453 ( .LO ( optlc_net_3176 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3178 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3455 ( .LO ( optlc_net_3177 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3179 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3456 ( .LO ( optlc_net_3178 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3180 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3457 ( .LO ( optlc_net_3179 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3181 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3458 ( .LO ( optlc_net_3180 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3182 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3459 ( .LO ( optlc_net_3181 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3183 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3460 ( .LO ( optlc_net_3182 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3184 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3461 ( .LO ( optlc_net_3183 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3185 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3462 ( .LO ( optlc_net_3184 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3186 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3463 ( .LO ( optlc_net_3185 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3187 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3464 ( .LO ( optlc_net_3186 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3188 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3465 ( .LO ( optlc_net_3187 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3189 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3466 ( .LO ( optlc_net_3188 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3190 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3467 ( .LO ( optlc_net_3189 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3191 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3468 ( .LO ( optlc_net_3190 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3192 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3469 ( .LO ( optlc_net_3191 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3193 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3470 ( .LO ( optlc_net_3192 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3194 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3471 ( .LO ( optlc_net_3193 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3195 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3472 ( .LO ( optlc_net_3194 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3196 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3473 ( .LO ( optlc_net_3195 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3197 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3474 ( .LO ( optlc_net_3196 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3198 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3475 ( .LO ( optlc_net_3197 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3199 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3476 ( .LO ( optlc_net_3198 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3200 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3477 ( .LO ( optlc_net_3199 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3201 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3478 ( .LO ( optlc_net_3200 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3202 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3479 ( .LO ( optlc_net_3201 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3203 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3480 ( .LO ( optlc_net_3202 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3204 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3481 ( .LO ( optlc_net_3203 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3205 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3482 ( .LO ( optlc_net_3204 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3206 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3483 ( .LO ( optlc_net_3205 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3207 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3484 ( .LO ( optlc_net_3206 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3208 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3485 ( .LO ( optlc_net_3207 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3209 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3486 ( .LO ( optlc_net_3208 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3487 ( .LO ( optlc_net_3209 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3211 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3488 ( .LO ( optlc_net_3210 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3212 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3489 ( .LO ( optlc_net_3211 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3213 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3490 ( .LO ( optlc_net_3212 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3214 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3491 ( .LO ( optlc_net_3213 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3215 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3492 ( .LO ( optlc_net_3214 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3216 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3493 ( .LO ( optlc_net_3215 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3217 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3494 ( .LO ( optlc_net_3216 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3218 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3495 ( .LO ( optlc_net_3217 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3219 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3496 ( .LO ( optlc_net_3218 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3220 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3497 ( .LO ( optlc_net_3219 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3221 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3498 ( .LO ( optlc_net_3220 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3222 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3499 ( .LO ( optlc_net_3221 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3223 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3500 ( .LO ( optlc_net_3222 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3224 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3501 ( .LO ( optlc_net_3223 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3225 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3502 ( .LO ( optlc_net_3224 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3226 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3503 ( .LO ( optlc_net_3225 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3227 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3504 ( .LO ( optlc_net_3226 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3228 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3505 ( .LO ( optlc_net_3227 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3229 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3506 ( .LO ( optlc_net_3228 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3230 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3507 ( .LO ( optlc_net_3229 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3231 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3508 ( .LO ( optlc_net_3230 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3232 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3509 ( .LO ( optlc_net_3231 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3233 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3510 ( .LO ( optlc_net_3232 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3234 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3511 ( .LO ( optlc_net_3233 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3235 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3512 ( .LO ( optlc_net_3234 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3236 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3513 ( .LO ( optlc_net_3235 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3237 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3514 ( .LO ( optlc_net_3236 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3238 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3515 ( .LO ( optlc_net_3237 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3239 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3516 ( .LO ( optlc_net_3238 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3240 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3517 ( .LO ( optlc_net_3239 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3241 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3518 ( .LO ( optlc_net_3240 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3242 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3519 ( .LO ( optlc_net_3241 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3243 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3520 ( .LO ( optlc_net_3242 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3244 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3521 ( .LO ( optlc_net_3243 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3245 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3522 ( .LO ( optlc_net_3244 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3246 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3523 ( .LO ( optlc_net_3245 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3524 ( .LO ( optlc_net_3246 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3248 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3525 ( .LO ( optlc_net_3247 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3249 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3526 ( .LO ( optlc_net_3248 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3250 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3527 ( .LO ( optlc_net_3249 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3251 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3528 ( .LO ( optlc_net_3250 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3252 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3529 ( .LO ( optlc_net_3251 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3253 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3530 ( .LO ( optlc_net_3252 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3254 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3531 ( .LO ( optlc_net_3253 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3255 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3532 ( .LO ( optlc_net_3254 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3256 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3534 ( .LO ( optlc_net_3255 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3257 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3535 ( .LO ( optlc_net_3256 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3258 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3536 ( .LO ( optlc_net_3257 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3259 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3538 ( .LO ( optlc_net_3258 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3260 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3539 ( .LO ( optlc_net_3259 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3261 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3540 ( .LO ( optlc_net_3260 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3262 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3541 ( .LO ( optlc_net_3261 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3263 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3543 ( .LO ( optlc_net_3262 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3264 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3544 ( .LO ( optlc_net_3263 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3265 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3545 ( .LO ( optlc_net_3264 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3266 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3546 ( .LO ( optlc_net_3265 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3267 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3547 ( .LO ( optlc_net_3266 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3268 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3548 ( .LO ( optlc_net_3267 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3269 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3549 ( .LO ( optlc_net_3268 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3270 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3550 ( .LO ( optlc_net_3269 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3271 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3551 ( .LO ( optlc_net_3270 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3272 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3552 ( .LO ( optlc_net_3271 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3273 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3553 ( .LO ( optlc_net_3272 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3274 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3554 ( .LO ( optlc_net_3273 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3275 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3555 ( .LO ( optlc_net_3274 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3276 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3556 ( .LO ( optlc_net_3275 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3277 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3557 ( .LO ( optlc_net_3276 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3278 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3558 ( .LO ( optlc_net_3277 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3559 ( .LO ( optlc_net_3278 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3280 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3560 ( .LO ( optlc_net_3279 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3281 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3561 ( .LO ( optlc_net_3280 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3282 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3562 ( .LO ( optlc_net_3281 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3283 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3563 ( .LO ( optlc_net_3282 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3284 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3564 ( .LO ( optlc_net_3283 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3285 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3565 ( .LO ( optlc_net_3284 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3286 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3566 ( .LO ( optlc_net_3285 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3287 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3567 ( .LO ( optlc_net_3286 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3288 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3568 ( .LO ( optlc_net_3287 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3289 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3569 ( .LO ( optlc_net_3288 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3290 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3570 ( .LO ( optlc_net_3289 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3291 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3571 ( .LO ( optlc_net_3290 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3292 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3572 ( .LO ( optlc_net_3291 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3293 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3573 ( .LO ( optlc_net_3292 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3294 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3574 ( .LO ( optlc_net_3293 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3295 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3575 ( .LO ( optlc_net_3294 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3296 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3576 ( .LO ( optlc_net_3295 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3297 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3577 ( .LO ( optlc_net_3296 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3298 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3578 ( .LO ( optlc_net_3297 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3299 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3579 ( .LO ( optlc_net_3298 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3300 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3580 ( .LO ( optlc_net_3299 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3301 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3581 ( .LO ( optlc_net_3300 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3302 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3582 ( .LO ( optlc_net_3301 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3303 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3583 ( .LO ( optlc_net_3302 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3304 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3584 ( .LO ( optlc_net_3303 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3305 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3585 ( .LO ( optlc_net_3304 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3306 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3586 ( .LO ( optlc_net_3305 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3307 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3587 ( .LO ( optlc_net_3306 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3308 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3588 ( .LO ( optlc_net_3307 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3589 ( .LO ( optlc_net_3308 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3310 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3590 ( .LO ( optlc_net_3309 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3311 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3591 ( .LO ( optlc_net_3310 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3312 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3592 ( .LO ( optlc_net_3311 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3313 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3593 ( .LO ( optlc_net_3312 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3314 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3594 ( .LO ( optlc_net_3313 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3315 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3595 ( .LO ( optlc_net_3314 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3316 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3596 ( .LO ( optlc_net_3315 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3317 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3597 ( .LO ( optlc_net_3316 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3318 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3598 ( .LO ( optlc_net_3317 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3319 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3599 ( .LO ( optlc_net_3318 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3320 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3600 ( .LO ( optlc_net_3319 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3321 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3601 ( .LO ( optlc_net_3320 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3322 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3602 ( .LO ( optlc_net_3321 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3323 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3603 ( .LO ( optlc_net_3322 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3324 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3604 ( .LO ( optlc_net_3323 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3325 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3605 ( .LO ( optlc_net_3324 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3326 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3606 ( .LO ( optlc_net_3325 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3327 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3607 ( .LO ( optlc_net_3326 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3328 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3608 ( .LO ( optlc_net_3327 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3329 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3609 ( .LO ( optlc_net_3328 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3330 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3610 ( .LO ( optlc_net_3329 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3331 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3611 ( .LO ( optlc_net_3330 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3332 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3612 ( .LO ( optlc_net_3331 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3333 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3613 ( .LO ( optlc_net_3332 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3334 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3614 ( .LO ( optlc_net_3333 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3335 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3615 ( .LO ( optlc_net_3334 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3336 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3616 ( .LO ( optlc_net_3335 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3617 ( .LO ( optlc_net_3336 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3338 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3618 ( .LO ( optlc_net_3337 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3339 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3619 ( .LO ( optlc_net_3338 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3340 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3620 ( .LO ( optlc_net_3339 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3341 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3621 ( .LO ( optlc_net_3340 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3342 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3622 ( .LO ( optlc_net_3341 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3343 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3623 ( .LO ( optlc_net_3342 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3344 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3624 ( .LO ( optlc_net_3343 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3345 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3625 ( .LO ( optlc_net_3344 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3346 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3626 ( .LO ( optlc_net_3345 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3347 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3627 ( .LO ( optlc_net_3346 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3348 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3628 ( .LO ( optlc_net_3347 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3349 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3629 ( .LO ( optlc_net_3348 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3350 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3630 ( .LO ( optlc_net_3349 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3351 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3631 ( .LO ( optlc_net_3350 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3352 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3632 ( .LO ( optlc_net_3351 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3353 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3633 ( .LO ( optlc_net_3352 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3354 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3634 ( .LO ( optlc_net_3353 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3355 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3635 ( .LO ( optlc_net_3354 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3356 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3636 ( .LO ( optlc_net_3355 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3357 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3637 ( .LO ( optlc_net_3356 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3358 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3638 ( .LO ( optlc_net_3357 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3359 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3639 ( .LO ( optlc_net_3358 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3360 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3640 ( .LO ( optlc_net_3359 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3361 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3641 ( .LO ( optlc_net_3360 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3362 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3642 ( .LO ( optlc_net_3361 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3643 ( .LO ( optlc_net_3362 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3364 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3644 ( .LO ( optlc_net_3363 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3365 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3645 ( .LO ( optlc_net_3364 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3366 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3646 ( .LO ( optlc_net_3365 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3367 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3647 ( .LO ( optlc_net_3366 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3368 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3648 ( .LO ( optlc_net_3367 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3369 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3649 ( .LO ( optlc_net_3368 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3370 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3650 ( .LO ( optlc_net_3369 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3371 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3651 ( .LO ( optlc_net_3370 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3372 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3652 ( .LO ( optlc_net_3371 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3373 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3653 ( .LO ( optlc_net_3372 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3374 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3654 ( .LO ( optlc_net_3373 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3375 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3655 ( .LO ( optlc_net_3374 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3376 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3656 ( .LO ( optlc_net_3375 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3377 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3657 ( .LO ( optlc_net_3376 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3378 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3658 ( .LO ( optlc_net_3377 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3379 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3659 ( .LO ( optlc_net_3378 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3380 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3660 ( .LO ( optlc_net_3379 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3381 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3661 ( .LO ( optlc_net_3380 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3382 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3662 ( .LO ( optlc_net_3381 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3383 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3663 ( .LO ( optlc_net_3382 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3384 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3664 ( .LO ( optlc_net_3383 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3385 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3665 ( .LO ( optlc_net_3384 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3386 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3666 ( .LO ( optlc_net_3385 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3667 ( .LO ( optlc_net_3386 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3388 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3668 ( .LO ( optlc_net_3387 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3389 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3669 ( .LO ( optlc_net_3388 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3390 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3670 ( .LO ( optlc_net_3389 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3391 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3671 ( .LO ( optlc_net_3390 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3392 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3672 ( .LO ( optlc_net_3391 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3393 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3673 ( .LO ( optlc_net_3392 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3394 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3674 ( .LO ( optlc_net_3393 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3395 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3675 ( .LO ( optlc_net_3394 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3396 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3676 ( .LO ( optlc_net_3395 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3397 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3677 ( .LO ( optlc_net_3396 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3398 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3678 ( .LO ( optlc_net_3397 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3399 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3679 ( .LO ( optlc_net_3398 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3400 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3680 ( .LO ( optlc_net_3399 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3401 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3681 ( .LO ( optlc_net_3400 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3402 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3682 ( .LO ( optlc_net_3401 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3403 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3683 ( .LO ( optlc_net_3402 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3404 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3684 ( .LO ( optlc_net_3403 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3405 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3685 ( .LO ( optlc_net_3404 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3406 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3686 ( .LO ( optlc_net_3405 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3407 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3687 ( .LO ( optlc_net_3406 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3688 ( .LO ( optlc_net_3407 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3409 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3689 ( .LO ( optlc_net_3408 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3410 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3690 ( .LO ( optlc_net_3409 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3411 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3691 ( .LO ( optlc_net_3410 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3412 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3692 ( .LO ( optlc_net_3411 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3413 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3693 ( .LO ( optlc_net_3412 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3414 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3694 ( .LO ( optlc_net_3413 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3415 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3695 ( .LO ( optlc_net_3414 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3416 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3696 ( .LO ( optlc_net_3415 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3697 ( .LO ( optlc_net_3416 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3418 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3698 ( .LO ( optlc_net_3417 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3419 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3699 ( .LO ( optlc_net_3418 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3420 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3700 ( .LO ( optlc_net_3419 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3421 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3701 ( .LO ( optlc_net_3420 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3422 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3702 ( .LO ( optlc_net_3421 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3423 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3703 ( .LO ( optlc_net_3422 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3424 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3704 ( .LO ( optlc_net_3423 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3425 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3705 ( .LO ( optlc_net_3424 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3426 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3706 ( .LO ( optlc_net_3425 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3427 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3707 ( .LO ( optlc_net_3426 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3428 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3708 ( .LO ( optlc_net_3427 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3429 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3709 ( .LO ( optlc_net_3428 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3430 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3710 ( .LO ( optlc_net_3429 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3711 ( .LO ( optlc_net_3430 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3432 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3712 ( .LO ( optlc_net_3431 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3433 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3713 ( .LO ( optlc_net_3432 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3434 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3714 ( .LO ( optlc_net_3433 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3435 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3715 ( .LO ( optlc_net_3434 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3436 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3716 ( .LO ( optlc_net_3435 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3437 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3717 ( .LO ( optlc_net_3436 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3438 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3718 ( .LO ( optlc_net_3437 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3439 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3719 ( .LO ( optlc_net_3438 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3440 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3720 ( .LO ( optlc_net_3439 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3721 ( .LO ( optlc_net_3440 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3442 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3722 ( .LO ( optlc_net_3441 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3443 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3723 ( .LO ( optlc_net_3442 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3444 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3724 ( .LO ( optlc_net_3443 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3445 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3725 ( .LO ( optlc_net_3444 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3446 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3726 ( .LO ( optlc_net_3445 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3447 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3727 ( .LO ( optlc_net_3446 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3448 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3728 ( .LO ( optlc_net_3447 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3449 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3729 ( .LO ( optlc_net_3448 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3450 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3730 ( .LO ( optlc_net_3449 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3451 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3731 ( .LO ( optlc_net_3450 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3452 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3732 ( .LO ( optlc_net_3451 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3453 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3733 ( .LO ( optlc_net_3452 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3454 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3734 ( .LO ( optlc_net_3453 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3455 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3735 ( .LO ( optlc_net_3454 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3456 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3736 ( .LO ( optlc_net_3455 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3457 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3737 ( .LO ( optlc_net_3456 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3458 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3738 ( .LO ( optlc_net_3457 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3459 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3739 ( .LO ( optlc_net_3458 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3460 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3740 ( .LO ( optlc_net_3459 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3461 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3741 ( .LO ( optlc_net_3460 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3462 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3742 ( .LO ( optlc_net_3461 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3463 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3743 ( .LO ( optlc_net_3462 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3464 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3744 ( .LO ( optlc_net_3463 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3465 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3745 ( .LO ( optlc_net_3464 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3466 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3746 ( .LO ( optlc_net_3465 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3467 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3747 ( .LO ( optlc_net_3466 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3468 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3748 ( .LO ( optlc_net_3467 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3749 ( .LO ( optlc_net_3468 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3470 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3750 ( .LO ( optlc_net_3469 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3751 ( .LO ( optlc_net_3470 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3472 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3753 ( .LO ( optlc_net_3471 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3473 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3754 ( .LO ( optlc_net_3472 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3474 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3755 ( .LO ( optlc_net_3473 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3475 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3756 ( .LO ( optlc_net_3474 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3476 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3757 ( .LO ( optlc_net_3475 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3477 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3758 ( .LO ( optlc_net_3476 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3478 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3759 ( .LO ( optlc_net_3477 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3479 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3760 ( .LO ( optlc_net_3478 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3480 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3761 ( .LO ( optlc_net_3479 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3481 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3762 ( .LO ( optlc_net_3480 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3482 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3763 ( .LO ( optlc_net_3481 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3483 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3764 ( .LO ( optlc_net_3482 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3484 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3765 ( .LO ( optlc_net_3483 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3485 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3766 ( .LO ( optlc_net_3484 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3486 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3767 ( .LO ( optlc_net_3485 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3487 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3768 ( .LO ( optlc_net_3486 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3488 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3769 ( .LO ( optlc_net_3487 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3489 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3770 ( .LO ( optlc_net_3488 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3490 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3771 ( .LO ( optlc_net_3489 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3491 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3772 ( .LO ( optlc_net_3490 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3492 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3773 ( .LO ( optlc_net_3491 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3774 ( .LO ( optlc_net_3492 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3494 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3775 ( .LO ( optlc_net_3493 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3495 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3776 ( .LO ( optlc_net_3494 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3496 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3777 ( .LO ( optlc_net_3495 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3497 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3778 ( .LO ( optlc_net_3496 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3498 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3779 ( .LO ( optlc_net_3497 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3499 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3780 ( .LO ( optlc_net_3498 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3500 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3781 ( .LO ( optlc_net_3499 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3501 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3782 ( .LO ( optlc_net_3500 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3502 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3783 ( .LO ( optlc_net_3501 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3503 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3784 ( .LO ( optlc_net_3502 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3504 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3785 ( .LO ( optlc_net_3503 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3505 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3786 ( .LO ( optlc_net_3504 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3506 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3787 ( .LO ( optlc_net_3505 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3507 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3788 ( .LO ( optlc_net_3506 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3508 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3789 ( .LO ( optlc_net_3507 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3509 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3790 ( .LO ( optlc_net_3508 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3510 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3791 ( .LO ( optlc_net_3509 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3511 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3792 ( .LO ( optlc_net_3510 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3512 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3793 ( .LO ( optlc_net_3511 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3513 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3794 ( .LO ( optlc_net_3512 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3514 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3795 ( .LO ( optlc_net_3513 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3796 ( .LO ( optlc_net_3514 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3797 ( .LO ( optlc_net_3515 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3798 ( .LO ( optlc_net_3516 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3799 ( .LO ( optlc_net_3517 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3800 ( .LO ( optlc_net_3518 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3801 ( .LO ( optlc_net_3519 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3802 ( .LO ( optlc_net_3520 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3803 ( .LO ( optlc_net_3521 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3804 ( .LO ( optlc_net_3522 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3805 ( .LO ( optlc_net_3523 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3806 ( .LO ( optlc_net_3524 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3807 ( .LO ( optlc_net_3525 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3808 ( .LO ( optlc_net_3526 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3809 ( .LO ( optlc_net_3527 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3810 ( .LO ( optlc_net_3528 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3811 ( .LO ( optlc_net_3529 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3812 ( .LO ( optlc_net_3530 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3813 ( .LO ( optlc_net_3531 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3814 ( .LO ( optlc_net_3532 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3815 ( .LO ( optlc_net_3533 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3816 ( .LO ( optlc_net_3534 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3817 ( .LO ( optlc_net_3535 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3818 ( .LO ( optlc_net_3536 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3819 ( .LO ( optlc_net_3537 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3820 ( .LO ( optlc_net_3538 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3821 ( .LO ( optlc_net_3539 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3541 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3822 ( .LO ( optlc_net_3540 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3542 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3823 ( .LO ( optlc_net_3541 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3543 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3824 ( .LO ( optlc_net_3542 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3544 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3825 ( .LO ( optlc_net_3543 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3545 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3826 ( .LO ( optlc_net_3544 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3546 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3827 ( .LO ( optlc_net_3545 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3828 ( .LO ( optlc_net_3546 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3548 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3829 ( .LO ( optlc_net_3547 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3549 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3830 ( .LO ( optlc_net_3548 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3550 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3831 ( .LO ( optlc_net_3549 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3551 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3832 ( .LO ( optlc_net_3550 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3552 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3833 ( .LO ( optlc_net_3551 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3553 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3834 ( .LO ( optlc_net_3552 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3554 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3835 ( .LO ( optlc_net_3553 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3555 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3836 ( .LO ( optlc_net_3554 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3556 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3837 ( .LO ( optlc_net_3555 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3557 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3838 ( .LO ( optlc_net_3556 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3558 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3839 ( .LO ( optlc_net_3557 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3559 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3840 ( .LO ( optlc_net_3558 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3560 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3841 ( .LO ( optlc_net_3559 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3561 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3842 ( .LO ( optlc_net_3560 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3562 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3843 ( .LO ( optlc_net_3561 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3563 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3844 ( .LO ( optlc_net_3562 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3564 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3845 ( .LO ( optlc_net_3563 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3565 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3846 ( .LO ( optlc_net_3564 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3566 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3847 ( .LO ( optlc_net_3565 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3567 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3848 ( .LO ( optlc_net_3566 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3568 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3849 ( .LO ( optlc_net_3567 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3569 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3850 ( .LO ( optlc_net_3568 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3570 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3851 ( .LO ( optlc_net_3569 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3571 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3852 ( .LO ( optlc_net_3570 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3572 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3853 ( .LO ( optlc_net_3571 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3573 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3854 ( .LO ( optlc_net_3572 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3574 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3855 ( .LO ( optlc_net_3573 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3856 ( .LO ( optlc_net_3574 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3576 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3857 ( .LO ( optlc_net_3575 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3577 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3858 ( .LO ( optlc_net_3576 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3578 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3859 ( .LO ( optlc_net_3577 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3579 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3860 ( .LO ( optlc_net_3578 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3580 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3861 ( .LO ( optlc_net_3579 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3581 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3862 ( .LO ( optlc_net_3580 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3582 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3863 ( .LO ( optlc_net_3581 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3583 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3864 ( .LO ( optlc_net_3582 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3584 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3865 ( .LO ( optlc_net_3583 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3585 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3866 ( .LO ( optlc_net_3584 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3586 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3867 ( .LO ( optlc_net_3585 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3587 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3868 ( .LO ( optlc_net_3586 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3588 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3869 ( .LO ( optlc_net_3587 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3589 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3870 ( .LO ( optlc_net_3588 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3590 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3871 ( .LO ( optlc_net_3589 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3591 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3872 ( .LO ( optlc_net_3590 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3592 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3873 ( .LO ( optlc_net_3591 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3593 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3874 ( .LO ( optlc_net_3592 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3594 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3593 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3595 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3594 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3596 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3595 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3597 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3596 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3598 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3597 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3599 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3598 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3600 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3599 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3601 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3600 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3602 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3601 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3603 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3602 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3604 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3603 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3605 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3604 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3606 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3605 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3607 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3606 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3608 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3607 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3609 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3608 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3610 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3609 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3611 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3610 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3612 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3611 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3613 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3612 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3614 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3613 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3615 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3614 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3616 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3615 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3617 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3616 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3618 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3617 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3619 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3618 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3620 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3619 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3621 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3620 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3622 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3621 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3623 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3622 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3624 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3623 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3625 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3624 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3626 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3625 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3627 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3626 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3628 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3627 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3629 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3628 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3630 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3629 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3631 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3630 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3632 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3631 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3633 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3632 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3634 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3633 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3635 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3634 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3636 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3635 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3637 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3636 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3638 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3637 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3639 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3638 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3640 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3639 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3641 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3640 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3642 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3641 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3643 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3642 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3644 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3643 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3645 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3644 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3646 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3645 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3647 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3646 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3648 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3647 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3649 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3648 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3650 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3649 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3651 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3650 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3652 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3651 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3653 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3652 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3654 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3653 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3655 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3654 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3656 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3655 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3657 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3656 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3658 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3657 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3659 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3658 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3660 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3659 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3661 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3660 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3662 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3661 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3663 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3662 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3664 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3663 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3665 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3664 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3666 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3665 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3667 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3666 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3668 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3667 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3669 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3668 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3670 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3669 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3671 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3670 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3672 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3671 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3673 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3672 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3674 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3673 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3675 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3674 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3676 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3675 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3677 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3676 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3678 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3677 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3679 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3678 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3680 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3679 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3681 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3680 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3682 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3681 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3683 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3682 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3684 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3683 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3685 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3966 ( .LO ( optlc_net_3684 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3686 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3967 ( .LO ( optlc_net_3685 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3687 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3968 ( .LO ( optlc_net_3686 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3688 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3969 ( .LO ( optlc_net_3687 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3689 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3970 ( .LO ( optlc_net_3688 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3690 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3971 ( .LO ( optlc_net_3689 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3691 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3972 ( .LO ( optlc_net_3690 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3692 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3973 ( .LO ( optlc_net_3691 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3693 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3974 ( .LO ( optlc_net_3692 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3694 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3975 ( .LO ( optlc_net_3693 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3695 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3976 ( .LO ( optlc_net_3694 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3696 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3977 ( .LO ( optlc_net_3695 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3697 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3978 ( .LO ( optlc_net_3696 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3698 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3979 ( .LO ( optlc_net_3697 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3699 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_3980 ( .LO ( optlc_net_3698 ) ,
+ .HI ( SYNOPSYS_UNCONNECTED_3700 ) ) ;
+endmodule
+
+
